Feature-gate trap-related code in riscv

Author: romancardenas

riscv/CHANGELOG.md

@@ -11,6 +11,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Add `miselect` CSR
 - Improved assembly macro handling in asm.rs
+- New `rt` and `rt-v-trap` features to opt-in `riscv-rt`-related code in `riscv::pac_enum` macro.
+
+# Changed
+
+- Now, `riscv::pac_enum` macro only includes trap-related code if `rt` or `rt-v-trap` features are enabled.
 
 ## [v0.15.0] - 2025-09-08
 

riscv/Cargo.toml

@@ -23,6 +23,8 @@ targets = [
 default = ["riscv-macros"]
 s-mode = []
 critical-section-single-hart = ["critical-section/restore-state-bool"]
+rt = ["riscv-macros/rt"]
+rt-v-trap = ["rt", "riscv-macros/rt-v-trap"]
 
 [dependencies]
 critical-section = "1.2.0"

riscv/macros/Cargo.toml

@@ -15,6 +15,10 @@ edition = "2021"
 [lib]
 proc-macro = true
 
+[features]
+rt = []
+rt-v-trap = ["rt"]
+
 [dependencies]
 proc-macro2 = "1.0"
 quote = "1.0"

riscv/macros/src/lib.rs

@@ -264,6 +264,7 @@ impl PacEnumItem {
         vectors
     }
 
+    #[cfg(feature = "rt-v-trap")]
     fn vector_table(&self) -> TokenStream2 {
         let align = match std::env::var("RISCV_MTVEC_ALIGN") {
             Ok(x) => x.parse::<u32>().ok(),
@@ -280,7 +281,7 @@ impl PacEnumItem {
         };
         let mut asm = format!(
             r#"
-#[cfg(all(feature = "v-trap", any(target_arch = "riscv32", target_arch = "riscv64")))]
+#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 core::arch::global_asm!("
     .section .trap.vector, \"ax\"
     .global _vector_table
@@ -328,8 +329,6 @@ core::arch::global_asm!("
         let max_discriminant = self.max_number;
         let valid_matches = self.valid_matches();
 
-        let is_core_interrupt = matches!(attr, PacTrait::Interrupt(InterruptType::Core));
-
         // Push the trait implementation
         res.push(quote! {
             unsafe impl riscv::#trait_name for #name {
@@ -354,54 +353,51 @@ core::arch::global_asm!("
             res.push(quote! { unsafe impl riscv::#marker_trait_name for #name {} });
         }
 
+        #[cfg(feature = "rt")]
         if let Some(trap_config) = attr.trap_config() {
-            let default_handler = &trap_config.default_handler;
-            let extern_signature = trap_config.extern_signature();
-            let handler_input = trap_config.handler_input();
-            let array_signature = trap_config.array_signature();
-            let dispatch_fn_name = &trap_config.dispatch_fn_name;
-            let dispatch_fn_args = &trap_config.dispatch_fn_signature();
-            let vector_table = &trap_config.handlers_array_name;
-
-            let handlers = self.handlers(&trap_config);
-            let interrupt_array = self.handlers_array();
-            let cfg_v_trap = match is_core_interrupt {
-                true => Some(quote!(#[cfg(not(feature = "v-trap"))])),
-                false => None,
-            };
-
-            // Push the interrupt handler functions and the interrupt array
-            res.push(quote! {
-                #cfg_v_trap
-                extern "C" {
-                    #(#handlers;)*
+            match attr {
+                #[cfg(feature = "rt-v-trap")]
+                PacTrait::Interrupt(InterruptType::Core) => {
+                    res.push(self.vector_table());
                 }
-
-                #cfg_v_trap
-                #[doc(hidden)]
-                #[no_mangle]
-                pub static #vector_table: [Option<unsafe extern "C" fn(#(#array_signature),*)>; #max_discriminant + 1] = [
-                    #(#interrupt_array),*
-                ];
-
-                #cfg_v_trap
-                #[inline]
-                #[no_mangle]
-                unsafe extern "C" fn #dispatch_fn_name(#(#dispatch_fn_args),*) {
-                    extern "C" {
-                        fn #default_handler(#(#extern_signature),*);
-                    }
-
-                    match #vector_table.get(code) {
-                        Some(Some(handler)) => handler(#(#handler_input),*),
-                        _ => #default_handler(#(#handler_input),*),
-                    }
+                _ => {
+                    let default_handler = &trap_config.default_handler;
+                    let extern_signature = trap_config.extern_signature();
+                    let handler_input = trap_config.handler_input();
+                    let array_signature = trap_config.array_signature();
+                    let dispatch_fn_name = &trap_config.dispatch_fn_name;
+                    let dispatch_fn_args = &trap_config.dispatch_fn_signature();
+                    let vector_table = &trap_config.handlers_array_name;
+
+                    let handlers = self.handlers(&trap_config);
+                    let interrupt_array = self.handlers_array();
+
+                    res.push(quote! {
+                        extern "C" {
+                            #(#handlers;)*
+                        }
+
+                        #[doc(hidden)]
+                        #[no_mangle]
+                        pub static #vector_table: [Option<unsafe extern "C" fn(#(#array_signature),*)>; #max_discriminant + 1] = [
+                            #(#interrupt_array),*
+                        ];
+
+                        #[inline]
+                        #[no_mangle]
+                        unsafe extern "C" fn #dispatch_fn_name(#(#dispatch_fn_args),*) {
+                            extern "C" {
+                                fn #default_handler(#(#extern_signature),*);
+                            }
+
+                            match #vector_table.get(code) {
+                                Some(Some(handler)) => handler(#(#handler_input),*),
+                                _ => #default_handler(#(#handler_input),*),
+                            }
+                        }
+                    });
                 }
-            });
-        }
-
-        if is_core_interrupt {
-            res.push(self.vector_table());
+            }
         }
 
         res

riscv/src/lib.rs

@@ -31,6 +31,17 @@
 //! and may cause functional problems in systems where some interrupts must NOT be disabled
 //! or critical sections are managed as part of an RTOS. In these cases, you should use
 //! a target-specific implementation instead, typically provided by a HAL or RTOS crate.
+//!
+//! ## `rt`
+//!
+//! This feature enables code related to [`riscv-rt`](https://github.com/rust-embedded/riscv/tree/master/riscv-rt)
+//! runtime support in the `riscv::pac_enum` macro. Namely, it enables the generation of
+//! trap handler functions and dispatch functions.
+//!
+//! ## `rt-v-trap`
+//!
+//! This feature enables code related to vectored trap handling in addition to the `rt` feature.
+//! Namely, it enables the generation of a vector table and the corresponding assembly code for core interrupts.
 
 #![no_std]
 #![allow(clippy::missing_safety_doc)]