diff --git a/asm.S b/asm.S
index 910d359..db553a8 100644
--- a/asm.S
+++ b/asm.S
@@ -46,6 +46,21 @@ _abs_start:
     .cfi_startproc
     .cfi_undefined ra
 
+    // Save boot arguments to RAM if on hartid 0
+    csrr t0, mhartid
+    bnez t0, 1f
+    la t1, boot_args
+    STORE a0, 0*REGBYTES(t1)
+    STORE a1, 1*REGBYTES(t1)
+    STORE a2, 2*REGBYTES(t1)
+    STORE a3, 3*REGBYTES(t1)
+    STORE a4, 4*REGBYTES(t1)
+    STORE a5, 5*REGBYTES(t1)
+    STORE a6, 6*REGBYTES(t1)
+    STORE a7, 7*REGBYTES(t1)
+    fence rw, rw
+1:
+
     csrw mie, 0
     csrw mip, 0
 
@@ -117,6 +132,15 @@ _abs_start:
 
     .cfi_endproc
 
+/*
+    Space to save the value of argument registers at boot
+*/
+.section .data
+.global boot_args
+boot_args:
+#define ARGUMENT_REGISTER_COUNT 8 // a0 to a7
+.skip REGBYTES * ARGUMENT_REGISTER_COUNT
+
 /*
     Trap entry point (_start_trap)
 
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diff --git a/src/lib.rs b/src/lib.rs
index 50b86cd..8e0f991 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -353,8 +353,13 @@ extern "C" {
 
     // Initial values of the .data section (stored in Flash)
     static _sidata: u32;
+
+    static boot_args: [usize; ARGUMENT_REGISTERS_COUNT];
 }
 
+/// a0 to a7
+const ARGUMENT_REGISTERS_COUNT: usize = 8;
+
 /// Rust entry point (_start_rust)
 ///
 /// Zeros bss section, initializes data section and calls main. This function
@@ -389,6 +394,18 @@ pub unsafe extern "C" fn start_rust() -> ! {
     main();
 }
 
+/// Returns the value an argument register had when this firmware was first booted.
+///
+/// The argument registers are `a0` to `a7`, indexed 0 to 7.
+/// This returns `None` for an out-of-bounds index.
+///
+/// Some of these registers may have had values passed by the previous boot stage:
+/// <https://doc.coreboot.org/arch/riscv/index.html#stage-handoff-protocol>.
+/// Otherwise, the returned `usize` value is undefined.
+pub fn boot_argument(index: usize) -> Option<usize> {
+    unsafe { boot_args.get(index).copied() }
+}
+
 /// Registers saved in trap handler
 #[allow(missing_docs)]
 #[repr(C)]