Releases: rust-embedded/cortex-m
Releases · rust-embedded/cortex-m
v0.7.0
Added
- New
InterruptNumber
trait is now required on interrupt arguments to the
various NVIC functions, replacing the previous use ofNr
from bare-metal.
For backwards compatibility,InterruptNumber
is implemented for types
which areNr + Copy
, but this will be removed in a future version. - Associated const
PTR
is introduced to Core Peripherals to
eventually replace the existingptr()
API. - A delay driver based on SysTick.
- You can now use LTO to inline assembly calls, even on stable Rust.
See theasm/lib.rs
documentation for more details. - Initial ARMv8-M MPU support
- ICTR and ACTLR registers added
- Support for the Security Attribution Unit on ARMv8-M
Changed
- Previously, asm calls without the
inline-asm
feature enabled used pre-built
objects which were built by a GCC compiler, whileinline-asm
enabled the
use ofllvm_asm!
calls. The asm system has been replaced with a new
technique which generates Rust static libs for stable calling, and uses the
newasm!
macro withinline-asm
. See theasm/lib.rs
documentation for
more details. - Cache enabling now uses an assembly sequence to ensure correctness.
ptr()
methods are nowconst
.
Breaking Changes
SCB::invalidate_dcache
and related methods are now unsafe, see #188Peripherals
struct is now non-exhaustive, so fields may be added in future
non-breaking changes- Removed
aligned
dependency - Removed const-fn feature
- Removed previously deprecated APIs
NVIC::clear_pending
NVIC::disable
NVIC::enable
NVIC::set_pending
SCB::system_reset
- Removed
basepri
,basepri_max
, andfaultmask
registers from thumbv8m.base
v0.6.3
Added
- Initial Cortex-M Security Extension support for armv8m
UDF
intrinsic- Methods to enable/disable exceptions in SCB
Fixed
- Fix bug in
asm::delay
not updating status clobber flags - Swapped to
llvm_asm!
to support inline assembly on new nightlies - Our precompiled assembly routines have additional debug information
- ITM
is_fifo_ready
improved to support armv8 - Cache enabling moved to pre-built assembly routines to prevent possible
undefined behaviour