Apply suggestions from code review

Co-authored-by: Adam Greig <[email protected]>

Author: Dirbaio

src/lib.rs

@@ -12,10 +12,12 @@
 //! ## `critical-section-single-core`
 //!
 //! This feature enables a [`critical-section`](https://github.com/rust-embedded/critical-section)
-//! implementation suitable for single-core targets, based on disabling interrupt globally.
+//! implementation suitable for single-core targets, based on disabling interrupts globally.
 //!
-//! It is **unsound** to enable it on multi-core targets. You should use a target-specific
-//! implementation that synchronizes all cores instead, typically provided by the HAL crate.
+//! It is **unsound** to enable it on multi-core targets or for code running in unprivileged mode,
+//! and may cause functional problems in systems where some interrupts must be not be disabled
+//! or critical sections are managed as part of an RTOS.
+//! You should use a target-specific implementation instead, typically provided by a HAL crate.
 //!
 //! ## `cm7-r0p1`
 //!

src/macros.rs

@@ -32,8 +32,8 @@ macro_rules! iprintln {
 ///
 /// # Notes
 ///
-/// This macro requires a `critical-section` implementation to be set. For single core systems, you can
-/// enable the `critical-section-single-core` feature for this crate. For multi core systems, you
+/// This macro requires a `critical-section` implementation to be set. For most single core systems,
+/// you can enable the `critical-section-single-core` feature for this crate. For other systems, you
 /// have to provide one from elsewhere, typically your chip's HAL crate.
 ///
 /// For debuggability, you can set an explicit name for a singleton.  This name only shows up the