diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 3e80cb5..d7c152c 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -38,7 +38,7 @@ jobs:
           rustup target add ${{ matrix.target }}
       - name: Build
         run: |
-          cargo build --target ${{ matrix.target }} --features "serde, defmt"
+          cargo build --target ${{ matrix.target }} --features "serde, defmt, check-asm"
           cargo build --target ${{ matrix.target }} --no-default-features
 
   build-versatileab:
@@ -126,7 +126,7 @@ jobs:
           rustup component add rust-src --toolchain nightly
       - name: Build
         run: |
-          cargo build --target ${{ matrix.target }} -Zbuild-std=core
+          cargo build --target ${{ matrix.target }} -Zbuild-std=core --features "serde, defmt, check-asm"
           cargo build --target ${{ matrix.target }} -Zbuild-std=core --no-default-features
 
   # Gather all the above build jobs together for the purposes of getting an overall pass-fail
diff --git a/aarch32-cpu/src/pmsav7.rs b/aarch32-cpu/src/pmsav7.rs
index d1252ae..2b55a45 100644
--- a/aarch32-cpu/src/pmsav7.rs
+++ b/aarch32-cpu/src/pmsav7.rs
@@ -56,7 +56,7 @@ impl Mpu {
             return None;
         }
         register::Rgnr::write(register::Rgnr(idx as u32));
-        let base = register::Irbar::read().0;
+        let base = register::Irbar::read().0 as *mut u8;
         let rsr = register::Irsr::read();
         let racr = register::Iracr::read();
 
@@ -85,7 +85,7 @@ impl Mpu {
             return None;
         }
         register::Rgnr::write(register::Rgnr(idx as u32));
-        let base = register::Drbar::read().0;
+        let base = register::Drbar::read().0 as *mut u8;
         let rsr = register::Drsr::read();
         let racr = register::Dracr::read();
 
@@ -120,7 +120,7 @@ impl Mpu {
             if !region.size.is_aligned(region.base) {
                 return Err(Error::UnalignedRegion(region.base));
             }
-            register::Irbar::write(register::Irbar(region.base));
+            register::Irbar::write(register::Irbar(region.base as u32));
             register::Irsr::write({
                 let mut out = register::Irsr::new_with_raw_value(0);
                 out.set_enabled(region.enabled);
@@ -145,7 +145,7 @@ impl Mpu {
                 return Err(Error::UnalignedRegion(region.base));
             }
             register::Rgnr::write(register::Rgnr(idx as u32));
-            register::Drbar::write(register::Drbar(region.base));
+            register::Drbar::write(register::Drbar(region.base as u32));
             register::Drsr::write({
                 let mut out = register::Drsr::new_with_raw_value(0);
                 out.set_enabled(region.enabled);
diff --git a/aarch32-cpu/src/register/actlr.rs b/aarch32-cpu/src/register/actlr.rs
index d6cde04..d4b909f 100644
--- a/aarch32-cpu/src/register/actlr.rs
+++ b/aarch32-cpu/src/register/actlr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Actlr(pub u32);
+
 impl SysReg for Actlr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Actlr {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Actlr {}
+
 impl Actlr {
     #[inline]
     /// Reads ACTLR (*Auxiliary Control Register*)
@@ -22,7 +25,9 @@ impl Actlr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Actlr {}
+
 impl Actlr {
     #[inline]
     /// Writes ACTLR (*Auxiliary Control Register*)
diff --git a/aarch32-cpu/src/register/actlr2.rs b/aarch32-cpu/src/register/actlr2.rs
index e0fbd1c..bc2b79f 100644
--- a/aarch32-cpu/src/register/actlr2.rs
+++ b/aarch32-cpu/src/register/actlr2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Actlr2(pub u32);
+
 impl SysReg for Actlr2 {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Actlr2 {
     const CRM: u32 = 0;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Actlr2 {}
+
 impl Actlr2 {
     #[inline]
     /// Reads ACTLR2 (*Auxiliary Control Register 2*)
@@ -22,7 +25,9 @@ impl Actlr2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Actlr2 {}
+
 impl Actlr2 {
     #[inline]
     /// Writes ACTLR2 (*Auxiliary Control Register 2*)
diff --git a/aarch32-cpu/src/register/adfsr.rs b/aarch32-cpu/src/register/adfsr.rs
index c272efd..17406c9 100644
--- a/aarch32-cpu/src/register/adfsr.rs
+++ b/aarch32-cpu/src/register/adfsr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Adfsr(pub u32);
+
 impl SysReg for Adfsr {
     const CP: u32 = 15;
     const CRN: u32 = 5;
@@ -14,7 +15,9 @@ impl SysReg for Adfsr {
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Adfsr {}
+
 impl Adfsr {
     #[inline]
     /// Reads ADFSR (*Auxiliary Data Fault Status Register*)
@@ -22,7 +25,9 @@ impl Adfsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Adfsr {}
+
 impl Adfsr {
     #[inline]
     /// Writes ADFSR (*Auxiliary Data Fault Status Register*)
diff --git a/aarch32-cpu/src/register/aidr.rs b/aarch32-cpu/src/register/aidr.rs
index ae6ac80..d126d46 100644
--- a/aarch32-cpu/src/register/aidr.rs
+++ b/aarch32-cpu/src/register/aidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Aidr(pub u32);
+
 impl SysReg for Aidr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Aidr {
     const CRM: u32 = 0;
     const OP2: u32 = 7;
 }
+
 impl crate::register::SysRegRead for Aidr {}
+
 impl Aidr {
     #[inline]
     /// Reads AIDR (*Auxiliary ID Register*)
diff --git a/aarch32-cpu/src/register/aifsr.rs b/aarch32-cpu/src/register/aifsr.rs
index 6bbf801..dc99a22 100644
--- a/aarch32-cpu/src/register/aifsr.rs
+++ b/aarch32-cpu/src/register/aifsr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Aifsr(pub u32);
+
 impl SysReg for Aifsr {
     const CP: u32 = 15;
     const CRN: u32 = 5;
@@ -14,7 +15,9 @@ impl SysReg for Aifsr {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Aifsr {}
+
 impl Aifsr {
     #[inline]
     /// Reads AIFSR (*Auxiliary Instruction Fault Status Register*)
@@ -22,7 +25,9 @@ impl Aifsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Aifsr {}
+
 impl Aifsr {
     #[inline]
     /// Writes AIFSR (*Auxiliary Instruction Fault Status Register*)
diff --git a/aarch32-cpu/src/register/amair0.rs b/aarch32-cpu/src/register/amair0.rs
index 917023c..9f3ebfc 100644
--- a/aarch32-cpu/src/register/amair0.rs
+++ b/aarch32-cpu/src/register/amair0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Amair0(pub u32);
+
 impl SysReg for Amair0 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
@@ -14,7 +15,9 @@ impl SysReg for Amair0 {
     const CRM: u32 = 3;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Amair0 {}
+
 impl Amair0 {
     #[inline]
     /// Reads AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
@@ -22,7 +25,9 @@ impl Amair0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Amair0 {}
+
 impl Amair0 {
     #[inline]
     /// Writes AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
diff --git a/aarch32-cpu/src/register/amair1.rs b/aarch32-cpu/src/register/amair1.rs
index 55574e6..5a9e8d6 100644
--- a/aarch32-cpu/src/register/amair1.rs
+++ b/aarch32-cpu/src/register/amair1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Amair1(pub u32);
+
 impl SysReg for Amair1 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
@@ -14,7 +15,9 @@ impl SysReg for Amair1 {
     const CRM: u32 = 3;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Amair1 {}
+
 impl Amair1 {
     #[inline]
     /// Reads AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
@@ -22,7 +25,9 @@ impl Amair1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Amair1 {}
+
 impl Amair1 {
     #[inline]
     /// Writes AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
diff --git a/aarch32-cpu/src/register/armv8r/cntfrq.rs b/aarch32-cpu/src/register/armv8r/cntfrq.rs
index 4df5969..a29f903 100644
--- a/aarch32-cpu/src/register/armv8r/cntfrq.rs
+++ b/aarch32-cpu/src/register/armv8r/cntfrq.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Cntfrq(pub u32);
+
 impl SysReg for Cntfrq {
     const CP: u32 = 15;
     const CRN: u32 = 14;
diff --git a/aarch32-cpu/src/register/armv8r/cntp_ctl.rs b/aarch32-cpu/src/register/armv8r/cntp_ctl.rs
index e902ec7..a61da3b 100644
--- a/aarch32-cpu/src/register/armv8r/cntp_ctl.rs
+++ b/aarch32-cpu/src/register/armv8r/cntp_ctl.rs
@@ -37,6 +37,7 @@ impl SysReg for CntpCtl {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl SysRegRead for CntpCtl {}
 
 impl CntpCtl {
diff --git a/aarch32-cpu/src/register/armv8r/cntp_tval.rs b/aarch32-cpu/src/register/armv8r/cntp_tval.rs
index 56fa952..ba255f0 100644
--- a/aarch32-cpu/src/register/armv8r/cntp_tval.rs
+++ b/aarch32-cpu/src/register/armv8r/cntp_tval.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntpTval(pub u32);
+
 impl SysReg for CntpTval {
     const CP: u32 = 15;
     const CRN: u32 = 14;
diff --git a/aarch32-cpu/src/register/armv8r/cntv_tval.rs b/aarch32-cpu/src/register/armv8r/cntv_tval.rs
index 8ca3a8d..ba184f4 100644
--- a/aarch32-cpu/src/register/armv8r/cntv_tval.rs
+++ b/aarch32-cpu/src/register/armv8r/cntv_tval.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntvTval(pub u32);
+
 impl SysReg for CntvTval {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for CntvTval {
     const CRM: u32 = 3;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for CntvTval {}
+
 impl CntvTval {
     #[inline]
     /// Reads CNTV_TVAL (*Virtual Counter-timer TimerValue Register*)
@@ -22,7 +25,9 @@ impl CntvTval {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for CntvTval {}
+
 impl CntvTval {
     #[inline]
     /// Writes CNTV_TVAL (*Virtual Counter-timer TimerValue Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hacr.rs b/aarch32-cpu/src/register/armv8r/hacr.rs
index 6fa36dd..1690e9c 100644
--- a/aarch32-cpu/src/register/armv8r/hacr.rs
+++ b/aarch32-cpu/src/register/armv8r/hacr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hacr(pub u32);
+
 impl SysReg for Hacr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Hacr {
     const CRM: u32 = 1;
     const OP2: u32 = 7;
 }
+
 impl crate::register::SysRegRead for Hacr {}
+
 impl Hacr {
     #[inline]
     /// Reads HACR (*Hyp Auxiliary Configuration Register*)
@@ -22,7 +25,9 @@ impl Hacr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hacr {}
+
 impl Hacr {
     #[inline]
     /// Writes HACR (*Hyp Auxiliary Configuration Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hactlr2.rs b/aarch32-cpu/src/register/armv8r/hactlr2.rs
index f25b07e..23cb434 100644
--- a/aarch32-cpu/src/register/armv8r/hactlr2.rs
+++ b/aarch32-cpu/src/register/armv8r/hactlr2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hactlr2(pub u32);
+
 impl SysReg for Hactlr2 {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Hactlr2 {
     const CRM: u32 = 0;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Hactlr2 {}
+
 impl Hactlr2 {
     #[inline]
     /// Reads HACTLR2 (*Hyp Auxiliary Control Register 2*)
@@ -22,7 +25,9 @@ impl Hactlr2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hactlr2 {}
+
 impl Hactlr2 {
     #[inline]
     /// Writes HACTLR2 (*Hyp Auxiliary Control Register 2*)
diff --git a/aarch32-cpu/src/register/armv8r/hadfsr.rs b/aarch32-cpu/src/register/armv8r/hadfsr.rs
index 16a8f98..c7041c0 100644
--- a/aarch32-cpu/src/register/armv8r/hadfsr.rs
+++ b/aarch32-cpu/src/register/armv8r/hadfsr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hadfsr(pub u32);
+
 impl SysReg for Hadfsr {
     const CP: u32 = 15;
     const CRN: u32 = 5;
@@ -14,7 +15,9 @@ impl SysReg for Hadfsr {
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hadfsr {}
+
 impl Hadfsr {
     #[inline]
     /// Reads HADFSR (*Hyp Auxiliary Data Fault Status Register*)
@@ -22,7 +25,9 @@ impl Hadfsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hadfsr {}
+
 impl Hadfsr {
     #[inline]
     /// Writes HADFSR (*Hyp Auxiliary Data Fault Status Register*)
diff --git a/aarch32-cpu/src/register/armv8r/haifsr.rs b/aarch32-cpu/src/register/armv8r/haifsr.rs
index 5799a16..e97b31f 100644
--- a/aarch32-cpu/src/register/armv8r/haifsr.rs
+++ b/aarch32-cpu/src/register/armv8r/haifsr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Haifsr(pub u32);
+
 impl SysReg for Haifsr {
     const CP: u32 = 15;
     const CRN: u32 = 5;
@@ -14,7 +15,9 @@ impl SysReg for Haifsr {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Haifsr {}
+
 impl Haifsr {
     #[inline]
     /// Reads HAIFSR (*Hyp Auxiliary Instruction Fault Status Register*)
@@ -22,7 +25,9 @@ impl Haifsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Haifsr {}
+
 impl Haifsr {
     #[inline]
     /// Writes HAIFSR (*Hyp Auxiliary Instruction Fault Status Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hamair0.rs b/aarch32-cpu/src/register/armv8r/hamair0.rs
index 0a91186..afa1300 100644
--- a/aarch32-cpu/src/register/armv8r/hamair0.rs
+++ b/aarch32-cpu/src/register/armv8r/hamair0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hamair0(pub u32);
+
 impl SysReg for Hamair0 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
@@ -14,7 +15,9 @@ impl SysReg for Hamair0 {
     const CRM: u32 = 3;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hamair0 {}
+
 impl Hamair0 {
     #[inline]
     /// Reads HAMAIR0 (*Hyp Auxiliary Memory Attribute Indirection Register 0*)
@@ -22,7 +25,9 @@ impl Hamair0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hamair0 {}
+
 impl Hamair0 {
     #[inline]
     /// Writes HAMAIR0 (*Hyp Auxiliary Memory Attribute Indirection Register 0*)
diff --git a/aarch32-cpu/src/register/armv8r/hamair1.rs b/aarch32-cpu/src/register/armv8r/hamair1.rs
index cdf56b3..4f8b6a1 100644
--- a/aarch32-cpu/src/register/armv8r/hamair1.rs
+++ b/aarch32-cpu/src/register/armv8r/hamair1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hamair1(pub u32);
+
 impl SysReg for Hamair1 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
@@ -14,7 +15,9 @@ impl SysReg for Hamair1 {
     const CRM: u32 = 3;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hamair1 {}
+
 impl Hamair1 {
     #[inline]
     /// Reads HAMAIR1 (*Hyp Auxiliary Memory Attribute Indirection Register 1*)
@@ -22,7 +25,9 @@ impl Hamair1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hamair1 {}
+
 impl Hamair1 {
     #[inline]
     /// Writes HAMAIR1 (*Hyp Auxiliary Memory Attribute Indirection Register 1*)
diff --git a/aarch32-cpu/src/register/armv8r/hcptr.rs b/aarch32-cpu/src/register/armv8r/hcptr.rs
index fe2f4c1..b4057aa 100644
--- a/aarch32-cpu/src/register/armv8r/hcptr.rs
+++ b/aarch32-cpu/src/register/armv8r/hcptr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hcptr(pub u32);
+
 impl SysReg for Hcptr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Hcptr {
     const CRM: u32 = 1;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Hcptr {}
+
 impl Hcptr {
     #[inline]
     /// Reads HCPTR (*Hyp Architectural Feature Trap Register*)
@@ -22,7 +25,9 @@ impl Hcptr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hcptr {}
+
 impl Hcptr {
     #[inline]
     /// Writes HCPTR (*Hyp Architectural Feature Trap Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hcr.rs b/aarch32-cpu/src/register/armv8r/hcr.rs
index 210d441..9da4117 100644
--- a/aarch32-cpu/src/register/armv8r/hcr.rs
+++ b/aarch32-cpu/src/register/armv8r/hcr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hcr(pub u32);
+
 impl SysReg for Hcr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Hcr {
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hcr {}
+
 impl Hcr {
     #[inline]
     /// Reads HCR (*Hyp Configuration Register*)
@@ -22,7 +25,9 @@ impl Hcr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hcr {}
+
 impl Hcr {
     #[inline]
     /// Writes HCR (*Hyp Configuration Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hcr2.rs b/aarch32-cpu/src/register/armv8r/hcr2.rs
index e761483..436873e 100644
--- a/aarch32-cpu/src/register/armv8r/hcr2.rs
+++ b/aarch32-cpu/src/register/armv8r/hcr2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hcr2(pub u32);
+
 impl SysReg for Hcr2 {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Hcr2 {
     const CRM: u32 = 1;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hcr2 {}
+
 impl Hcr2 {
     #[inline]
     /// Reads HCR2 (*Hyp Configuration Register 2*)
@@ -22,7 +25,9 @@ impl Hcr2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hcr2 {}
+
 impl Hcr2 {
     #[inline]
     /// Writes HCR2 (*Hyp Configuration Register 2*)
diff --git a/aarch32-cpu/src/register/armv8r/hdcr.rs b/aarch32-cpu/src/register/armv8r/hdcr.rs
index 35ef3b2..2fb3101 100644
--- a/aarch32-cpu/src/register/armv8r/hdcr.rs
+++ b/aarch32-cpu/src/register/armv8r/hdcr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hdcr(pub u32);
+
 impl SysReg for Hdcr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Hdcr {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hdcr {}
+
 impl Hdcr {
     #[inline]
     /// Reads HDCR (*Hyp Debug Control Register*)
@@ -22,7 +25,9 @@ impl Hdcr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hdcr {}
+
 impl Hdcr {
     #[inline]
     /// Writes HDCR (*Hyp Debug Control Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hdfar.rs b/aarch32-cpu/src/register/armv8r/hdfar.rs
index fffbcdd..a6eff51 100644
--- a/aarch32-cpu/src/register/armv8r/hdfar.rs
+++ b/aarch32-cpu/src/register/armv8r/hdfar.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hdfar(pub u32);
+
 impl SysReg for Hdfar {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hdfar {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hdfar {}
+
 impl Hdfar {
     #[inline]
     /// Reads HDFAR (*Hyp Data Fault Address Register*)
@@ -22,7 +25,9 @@ impl Hdfar {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hdfar {}
+
 impl Hdfar {
     #[inline]
     /// Writes HDFAR (*Hyp Data Fault Address Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hifar.rs b/aarch32-cpu/src/register/armv8r/hifar.rs
index 46dbaf9..ed38515 100644
--- a/aarch32-cpu/src/register/armv8r/hifar.rs
+++ b/aarch32-cpu/src/register/armv8r/hifar.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hifar(pub u32);
+
 impl SysReg for Hifar {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hifar {
     const CRM: u32 = 0;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Hifar {}
+
 impl Hifar {
     #[inline]
     /// Reads HIFAR (*Hyp Instruction Fault Address Register*)
@@ -22,7 +25,9 @@ impl Hifar {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hifar {}
+
 impl Hifar {
     #[inline]
     /// Writes HIFAR (*Hyp Instruction Fault Address Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hmair0.rs b/aarch32-cpu/src/register/armv8r/hmair0.rs
index 264fd5e..3e217c4 100644
--- a/aarch32-cpu/src/register/armv8r/hmair0.rs
+++ b/aarch32-cpu/src/register/armv8r/hmair0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hmair0(pub u32);
+
 impl SysReg for Hmair0 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
@@ -14,7 +15,9 @@ impl SysReg for Hmair0 {
     const CRM: u32 = 2;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hmair0 {}
+
 impl Hmair0 {
     #[inline]
     /// Reads HMAIR0 (*Hyp Memory Attribute Indirection Register 0*)
@@ -22,7 +25,9 @@ impl Hmair0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hmair0 {}
+
 impl Hmair0 {
     #[inline]
     /// Writes HMAIR0 (*Hyp Memory Attribute Indirection Register 0*)
diff --git a/aarch32-cpu/src/register/armv8r/hmair1.rs b/aarch32-cpu/src/register/armv8r/hmair1.rs
index 473a53d..75febb2 100644
--- a/aarch32-cpu/src/register/armv8r/hmair1.rs
+++ b/aarch32-cpu/src/register/armv8r/hmair1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hmair1(pub u32);
+
 impl SysReg for Hmair1 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
@@ -14,7 +15,9 @@ impl SysReg for Hmair1 {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hmair1 {}
+
 impl Hmair1 {
     #[inline]
     /// Reads HMAIR1 (*Hyp Memory Attribute Indirection Register 1*)
@@ -22,7 +25,9 @@ impl Hmair1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hmair1 {}
+
 impl Hmair1 {
     #[inline]
     /// Writes HMAIR1 (*Hyp Memory Attribute Indirection Register 1*)
diff --git a/aarch32-cpu/src/register/armv8r/hmpuir.rs b/aarch32-cpu/src/register/armv8r/hmpuir.rs
index fe4f345..090fc4b 100644
--- a/aarch32-cpu/src/register/armv8r/hmpuir.rs
+++ b/aarch32-cpu/src/register/armv8r/hmpuir.rs
@@ -18,7 +18,9 @@ impl SysReg for Hmpuir {
     const CRM: u32 = 0;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hmpuir {}
+
 impl Hmpuir {
     #[inline]
     /// Reads HMPUIR (*Hyp MPU Type Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hpfar.rs b/aarch32-cpu/src/register/armv8r/hpfar.rs
index 319ea7b..261004e 100644
--- a/aarch32-cpu/src/register/armv8r/hpfar.rs
+++ b/aarch32-cpu/src/register/armv8r/hpfar.rs
@@ -3,10 +3,12 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// HPFAR (*Hyp IPA Fault Address Register*)
-#[derive(Debug, Copy, Clone)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(transparent)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hpfar(pub u32);
+
 impl SysReg for Hpfar {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +16,9 @@ impl SysReg for Hpfar {
     const CRM: u32 = 0;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hpfar {}
+
 impl Hpfar {
     #[inline]
     /// Reads HPFAR (*Hyp IPA Fault Address Register*)
@@ -22,7 +26,9 @@ impl Hpfar {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hpfar {}
+
 impl Hpfar {
     #[inline]
     /// Writes HPFAR (*Hyp IPA Fault Address Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar.rs b/aarch32-cpu/src/register/armv8r/hprbar.rs
index 81face7..e313c1e 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar.rs
@@ -60,7 +60,9 @@ impl SysReg for Hprbar {
     const CRM: u32 = 3;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar {}
+
 impl Hprbar {
     #[inline]
     /// Reads HPRBAR (*Hyp Protection Region Base Address Register*)
@@ -68,7 +70,9 @@ impl Hprbar {
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar {}
+
 impl Hprbar {
     #[inline]
     /// Writes HPRBAR (*Hyp Protection Region Base Address Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar0.rs b/aarch32-cpu/src/register/armv8r/hprbar0.rs
index 6a6e99a..00161ab 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar0.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar0(pub u32);
+
 impl SysReg for Hprbar0 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar0 {
     const CRM: u32 = 8;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar0 {}
+
 impl Hprbar0 {
     #[inline]
     /// Reads HPRBAR0 (*Hyp Protection Region Base Address Register 0*)
@@ -22,7 +25,9 @@ impl Hprbar0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar0 {}
+
 impl Hprbar0 {
     #[inline]
     /// Writes HPRBAR0 (*Hyp Protection Region Base Address Register 0*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar1.rs b/aarch32-cpu/src/register/armv8r/hprbar1.rs
index c0765f6..f5c988a 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar1.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar1(pub u32);
+
 impl SysReg for Hprbar1 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar1 {
     const CRM: u32 = 8;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hprbar1 {}
+
 impl Hprbar1 {
     #[inline]
     /// Reads HPRBAR1 (*Hyp Protection Region Base Address Register 1*)
@@ -22,7 +25,9 @@ impl Hprbar1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar1 {}
+
 impl Hprbar1 {
     #[inline]
     /// Writes HPRBAR1 (*Hyp Protection Region Base Address Register 1*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar10.rs b/aarch32-cpu/src/register/armv8r/hprbar10.rs
index f14de32..3167b27 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar10.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar10.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar10(pub u32);
+
 impl SysReg for Hprbar10 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar10 {
     const CRM: u32 = 13;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar10 {}
+
 impl Hprbar10 {
     #[inline]
     /// Reads HPRBAR10 (*Hyp Protection Region Base Address Register 10*)
@@ -22,7 +25,9 @@ impl Hprbar10 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar10 {}
+
 impl Hprbar10 {
     #[inline]
     /// Writes HPRBAR10 (*Hyp Protection Region Base Address Register 10*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar11.rs b/aarch32-cpu/src/register/armv8r/hprbar11.rs
index bc22da1..8abca05 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar11.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar11.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar11(pub u32);
+
 impl SysReg for Hprbar11 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar11 {
     const CRM: u32 = 13;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hprbar11 {}
+
 impl Hprbar11 {
     #[inline]
     /// Reads HPRBAR11 (*Hyp Protection Region Base Address Register 11*)
@@ -22,7 +25,9 @@ impl Hprbar11 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar11 {}
+
 impl Hprbar11 {
     #[inline]
     /// Writes HPRBAR11 (*Hyp Protection Region Base Address Register 11*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar12.rs b/aarch32-cpu/src/register/armv8r/hprbar12.rs
index 8f27213..735a147 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar12.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar12.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar12(pub u32);
+
 impl SysReg for Hprbar12 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar12 {
     const CRM: u32 = 14;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar12 {}
+
 impl Hprbar12 {
     #[inline]
     /// Reads HPRBAR12 (*Hyp Protection Region Base Address Register 12*)
@@ -22,7 +25,9 @@ impl Hprbar12 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar12 {}
+
 impl Hprbar12 {
     #[inline]
     /// Writes HPRBAR12 (*Hyp Protection Region Base Address Register 12*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar13.rs b/aarch32-cpu/src/register/armv8r/hprbar13.rs
index db2cb81..4afa814 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar13.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar13.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar13(pub u32);
+
 impl SysReg for Hprbar13 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar13 {
     const CRM: u32 = 14;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hprbar13 {}
+
 impl Hprbar13 {
     #[inline]
     /// Reads HPRBAR13 (*Hyp Protection Region Base Address Register 13*)
@@ -22,7 +25,9 @@ impl Hprbar13 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar13 {}
+
 impl Hprbar13 {
     #[inline]
     /// Writes HPRBAR13 (*Hyp Protection Region Base Address Register 13*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar14.rs b/aarch32-cpu/src/register/armv8r/hprbar14.rs
index 2c256dd..9ae75ca 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar14.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar14.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar14(pub u32);
+
 impl SysReg for Hprbar14 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar14 {
     const CRM: u32 = 15;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar14 {}
+
 impl Hprbar14 {
     #[inline]
     /// Reads HPRBAR14 (*Hyp Protection Region Base Address Register 14*)
@@ -22,7 +25,9 @@ impl Hprbar14 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar14 {}
+
 impl Hprbar14 {
     #[inline]
     /// Writes HPRBAR14 (*Hyp Protection Region Base Address Register 14*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar15.rs b/aarch32-cpu/src/register/armv8r/hprbar15.rs
index f3e05c4..ce6e56d 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar15.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar15.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar15(pub u32);
+
 impl SysReg for Hprbar15 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar15 {
     const CRM: u32 = 15;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hprbar15 {}
+
 impl Hprbar15 {
     #[inline]
     /// Reads HPRBAR15 (*Hyp Protection Region Base Address Register 15*)
@@ -22,7 +25,9 @@ impl Hprbar15 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar15 {}
+
 impl Hprbar15 {
     #[inline]
     /// Writes HPRBAR15 (*Hyp Protection Region Base Address Register 15*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar2.rs b/aarch32-cpu/src/register/armv8r/hprbar2.rs
index 6141d36..1d4a1af 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar2.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar2(pub u32);
+
 impl SysReg for Hprbar2 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar2 {
     const CRM: u32 = 9;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar2 {}
+
 impl Hprbar2 {
     #[inline]
     /// Reads HPRBAR2 (*Hyp Protection Region Base Address Register 2*)
@@ -22,7 +25,9 @@ impl Hprbar2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar2 {}
+
 impl Hprbar2 {
     #[inline]
     /// Writes HPRBAR2 (*Hyp Protection Region Base Address Register 2*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar3.rs b/aarch32-cpu/src/register/armv8r/hprbar3.rs
index bcdb282..208743d 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar3.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar3.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar3(pub u32);
+
 impl SysReg for Hprbar3 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar3 {
     const CRM: u32 = 9;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hprbar3 {}
+
 impl Hprbar3 {
     #[inline]
     /// Reads HPRBAR3 (*Hyp Protection Region Base Address Register 3*)
@@ -22,7 +25,9 @@ impl Hprbar3 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar3 {}
+
 impl Hprbar3 {
     #[inline]
     /// Writes HPRBAR3 (*Hyp Protection Region Base Address Register 3*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar4.rs b/aarch32-cpu/src/register/armv8r/hprbar4.rs
index 3700ef7..3476af5 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar4.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar4.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar4(pub u32);
+
 impl SysReg for Hprbar4 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar4 {
     const CRM: u32 = 10;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar4 {}
+
 impl Hprbar4 {
     #[inline]
     /// Reads HPRBAR4 (*Hyp Protection Region Base Address Register 4*)
@@ -22,7 +25,9 @@ impl Hprbar4 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar4 {}
+
 impl Hprbar4 {
     #[inline]
     /// Writes HPRBAR4 (*Hyp Protection Region Base Address Register 4*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar5.rs b/aarch32-cpu/src/register/armv8r/hprbar5.rs
index d2cdbc6..ee606ac 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar5.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar5.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar5(pub u32);
+
 impl SysReg for Hprbar5 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar5 {
     const CRM: u32 = 10;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hprbar5 {}
+
 impl Hprbar5 {
     #[inline]
     /// Reads HPRBAR5 (*Hyp Protection Region Base Address Register 5*)
@@ -22,7 +25,9 @@ impl Hprbar5 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar5 {}
+
 impl Hprbar5 {
     #[inline]
     /// Writes HPRBAR5 (*Hyp Protection Region Base Address Register 5*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar6.rs b/aarch32-cpu/src/register/armv8r/hprbar6.rs
index 5f17958..743fdf5 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar6.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar6.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar6(pub u32);
+
 impl SysReg for Hprbar6 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar6 {
     const CRM: u32 = 11;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar6 {}
+
 impl Hprbar6 {
     #[inline]
     /// Reads HPRBAR6 (*Hyp Protection Region Base Address Register 6*)
@@ -22,7 +25,9 @@ impl Hprbar6 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar6 {}
+
 impl Hprbar6 {
     #[inline]
     /// Writes HPRBAR6 (*Hyp Protection Region Base Address Register 6*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar7.rs b/aarch32-cpu/src/register/armv8r/hprbar7.rs
index 016406e..5ee4cce 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar7.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar7.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar7(pub u32);
+
 impl SysReg for Hprbar7 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar7 {
     const CRM: u32 = 11;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hprbar7 {}
+
 impl Hprbar7 {
     #[inline]
     /// Reads HPRBAR7 (*Hyp Protection Region Base Address Register 7*)
@@ -22,7 +25,9 @@ impl Hprbar7 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar7 {}
+
 impl Hprbar7 {
     #[inline]
     /// Writes HPRBAR7 (*Hyp Protection Region Base Address Register 7*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar8.rs b/aarch32-cpu/src/register/armv8r/hprbar8.rs
index 1baef5b..a8404af 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar8.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar8.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar8(pub u32);
+
 impl SysReg for Hprbar8 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar8 {
     const CRM: u32 = 12;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hprbar8 {}
+
 impl Hprbar8 {
     #[inline]
     /// Reads HPRBAR8 (*Hyp Protection Region Base Address Register 8*)
@@ -22,7 +25,9 @@ impl Hprbar8 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar8 {}
+
 impl Hprbar8 {
     #[inline]
     /// Writes HPRBAR8 (*Hyp Protection Region Base Address Register 8*)
diff --git a/aarch32-cpu/src/register/armv8r/hprbar9.rs b/aarch32-cpu/src/register/armv8r/hprbar9.rs
index 9d2472b..93d07c8 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar9.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar9.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprbar9(pub u32);
+
 impl SysReg for Hprbar9 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprbar9 {
     const CRM: u32 = 12;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Hprbar9 {}
+
 impl Hprbar9 {
     #[inline]
     /// Reads HPRBAR9 (*Hyp Protection Region Base Address Register 9*)
@@ -22,7 +25,9 @@ impl Hprbar9 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprbar9 {}
+
 impl Hprbar9 {
     #[inline]
     /// Writes HPRBAR9 (*Hyp Protection Region Base Address Register 9*)
diff --git a/aarch32-cpu/src/register/armv8r/hprenr.rs b/aarch32-cpu/src/register/armv8r/hprenr.rs
index 551230c..ccc556b 100644
--- a/aarch32-cpu/src/register/armv8r/hprenr.rs
+++ b/aarch32-cpu/src/register/armv8r/hprenr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprenr(pub u32);
+
 impl SysReg for Hprenr {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprenr {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprenr {}
+
 impl Hprenr {
     #[inline]
     /// Reads HPRENR (*Hyp MPU Region Enable Register*)
@@ -22,7 +25,9 @@ impl Hprenr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprenr {}
+
 impl Hprenr {
     #[inline]
     /// Writes HPRENR (*Hyp MPU Region Enable Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar.rs b/aarch32-cpu/src/register/armv8r/hprlar.rs
index ffeb0fb..b4f4549 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar.rs
@@ -25,7 +25,9 @@ impl SysReg for Hprlar {
     const CRM: u32 = 3;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar {}
+
 impl Hprlar {
     #[inline]
     /// Reads HPRLAR (*Hyp Protection Region Limit Address Register*)
@@ -33,7 +35,9 @@ impl Hprlar {
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar {}
+
 impl Hprlar {
     #[inline]
     /// Writes HPRLAR (*Hyp Protection Region Limit Address Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar0.rs b/aarch32-cpu/src/register/armv8r/hprlar0.rs
index 0fb241b..cdfec7d 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar0.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar0(pub u32);
+
 impl SysReg for Hprlar0 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar0 {
     const CRM: u32 = 8;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar0 {}
+
 impl Hprlar0 {
     #[inline]
     /// Reads HPRLAR0 (*Hyp Protection Region Limit Address Register 0*)
@@ -22,7 +25,9 @@ impl Hprlar0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar0 {}
+
 impl Hprlar0 {
     #[inline]
     /// Writes HPRLAR0 (*Hyp Protection Region Limit Address Register 0*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar1.rs b/aarch32-cpu/src/register/armv8r/hprlar1.rs
index e461a66..34dc23b 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar1.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar1(pub u32);
+
 impl SysReg for Hprlar1 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar1 {
     const CRM: u32 = 8;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Hprlar1 {}
+
 impl Hprlar1 {
     #[inline]
     /// Reads HPRLAR1 (*Hyp Protection Region Limit Address Register 1*)
@@ -22,7 +25,9 @@ impl Hprlar1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar1 {}
+
 impl Hprlar1 {
     #[inline]
     /// Writes HPRLAR1 (*Hyp Protection Region Limit Address Register 1*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar10.rs b/aarch32-cpu/src/register/armv8r/hprlar10.rs
index 9fd7f9a..e32f205 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar10.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar10.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar10(pub u32);
+
 impl SysReg for Hprlar10 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar10 {
     const CRM: u32 = 13;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar10 {}
+
 impl Hprlar10 {
     #[inline]
     /// Reads HPRLAR10 (*Hyp Protection Region Limit Address Register 10*)
@@ -22,7 +25,9 @@ impl Hprlar10 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar10 {}
+
 impl Hprlar10 {
     #[inline]
     /// Writes HPRLAR10 (*Hyp Protection Region Limit Address Register 10*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar11.rs b/aarch32-cpu/src/register/armv8r/hprlar11.rs
index f1ed22b..4685e3a 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar11.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar11.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar11(pub u32);
+
 impl SysReg for Hprlar11 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar11 {
     const CRM: u32 = 13;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Hprlar11 {}
+
 impl Hprlar11 {
     #[inline]
     /// Reads HPRLAR11 (*Hyp Protection Region Limit Address Register 11*)
@@ -22,7 +25,9 @@ impl Hprlar11 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar11 {}
+
 impl Hprlar11 {
     #[inline]
     /// Writes HPRLAR11 (*Hyp Protection Region Limit Address Register 11*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar12.rs b/aarch32-cpu/src/register/armv8r/hprlar12.rs
index 94bd70f..7b44a65 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar12.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar12.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar12(pub u32);
+
 impl SysReg for Hprlar12 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar12 {
     const CRM: u32 = 14;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar12 {}
+
 impl Hprlar12 {
     #[inline]
     /// Reads HPRLAR12 (*Hyp Protection Region Limit Address Register 12*)
@@ -22,7 +25,9 @@ impl Hprlar12 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar12 {}
+
 impl Hprlar12 {
     #[inline]
     /// Writes HPRLAR12 (*Hyp Protection Region Limit Address Register 12*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar13.rs b/aarch32-cpu/src/register/armv8r/hprlar13.rs
index b9a6ccf..ca44175 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar13.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar13.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar13(pub u32);
+
 impl SysReg for Hprlar13 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar13 {
     const CRM: u32 = 14;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Hprlar13 {}
+
 impl Hprlar13 {
     #[inline]
     /// Reads HPRLAR13 (*Hyp Protection Region Limit Address Register 13*)
@@ -22,7 +25,9 @@ impl Hprlar13 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar13 {}
+
 impl Hprlar13 {
     #[inline]
     /// Writes HPRLAR13 (*Hyp Protection Region Limit Address Register 13*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar14.rs b/aarch32-cpu/src/register/armv8r/hprlar14.rs
index fef31a9..339d09d 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar14.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar14.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar14(pub u32);
+
 impl SysReg for Hprlar14 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar14 {
     const CRM: u32 = 15;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar14 {}
+
 impl Hprlar14 {
     #[inline]
     /// Reads HPRLAR14 (*Hyp Protection Region Limit Address Register 14*)
@@ -22,7 +25,9 @@ impl Hprlar14 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar14 {}
+
 impl Hprlar14 {
     #[inline]
     /// Writes HPRLAR14 (*Hyp Protection Region Limit Address Register 14*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar15.rs b/aarch32-cpu/src/register/armv8r/hprlar15.rs
index 51ab73e..e06fa45 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar15.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar15.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar15(pub u32);
+
 impl SysReg for Hprlar15 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar15 {
     const CRM: u32 = 15;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Hprlar15 {}
+
 impl Hprlar15 {
     #[inline]
     /// Reads HPRLAR15 (*Hyp Protection Region Limit Address Register 15*)
@@ -22,7 +25,9 @@ impl Hprlar15 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar15 {}
+
 impl Hprlar15 {
     #[inline]
     /// Writes HPRLAR15 (*Hyp Protection Region Limit Address Register 15*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar2.rs b/aarch32-cpu/src/register/armv8r/hprlar2.rs
index 922851a..ecc55c1 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar2.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar2(pub u32);
+
 impl SysReg for Hprlar2 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar2 {
     const CRM: u32 = 9;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar2 {}
+
 impl Hprlar2 {
     #[inline]
     /// Reads HPRLAR2 (*Hyp Protection Region Limit Address Register 2*)
@@ -22,7 +25,9 @@ impl Hprlar2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar2 {}
+
 impl Hprlar2 {
     #[inline]
     /// Writes HPRLAR2 (*Hyp Protection Region Limit Address Register 2*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar3.rs b/aarch32-cpu/src/register/armv8r/hprlar3.rs
index 3364250..2d80fb5 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar3.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar3.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar3(pub u32);
+
 impl SysReg for Hprlar3 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar3 {
     const CRM: u32 = 9;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Hprlar3 {}
+
 impl Hprlar3 {
     #[inline]
     /// Reads HPRLAR3 (*Hyp Protection Region Limit Address Register 3*)
@@ -22,7 +25,9 @@ impl Hprlar3 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar3 {}
+
 impl Hprlar3 {
     #[inline]
     /// Writes HPRLAR3 (*Hyp Protection Region Limit Address Register 3*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar4.rs b/aarch32-cpu/src/register/armv8r/hprlar4.rs
index 04e7cd4..840ea92 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar4.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar4.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar4(pub u32);
+
 impl SysReg for Hprlar4 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar4 {
     const CRM: u32 = 10;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar4 {}
+
 impl Hprlar4 {
     #[inline]
     /// Reads HPRLAR4 (*Hyp Protection Region Limit Address Register 4*)
@@ -22,7 +25,9 @@ impl Hprlar4 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar4 {}
+
 impl Hprlar4 {
     #[inline]
     /// Writes HPRLAR4 (*Hyp Protection Region Limit Address Register 4*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar5.rs b/aarch32-cpu/src/register/armv8r/hprlar5.rs
index 696f839..254d358 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar5.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar5.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar5(pub u32);
+
 impl SysReg for Hprlar5 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar5 {
     const CRM: u32 = 10;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Hprlar5 {}
+
 impl Hprlar5 {
     #[inline]
     /// Reads HPRLAR5 (*Hyp Protection Region Limit Address Register 5*)
@@ -22,7 +25,9 @@ impl Hprlar5 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar5 {}
+
 impl Hprlar5 {
     #[inline]
     /// Writes HPRLAR5 (*Hyp Protection Region Limit Address Register 5*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar6.rs b/aarch32-cpu/src/register/armv8r/hprlar6.rs
index f6e99af..3f35515 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar6.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar6.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar6(pub u32);
+
 impl SysReg for Hprlar6 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar6 {
     const CRM: u32 = 11;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar6 {}
+
 impl Hprlar6 {
     #[inline]
     /// Reads HPRLAR6 (*Hyp Protection Region Limit Address Register 6*)
@@ -22,7 +25,9 @@ impl Hprlar6 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar6 {}
+
 impl Hprlar6 {
     #[inline]
     /// Writes HPRLAR6 (*Hyp Protection Region Limit Address Register 6*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar7.rs b/aarch32-cpu/src/register/armv8r/hprlar7.rs
index e24dc28..bd57de7 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar7.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar7.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar7(pub u32);
+
 impl SysReg for Hprlar7 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar7 {
     const CRM: u32 = 11;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Hprlar7 {}
+
 impl Hprlar7 {
     #[inline]
     /// Reads HPRLAR7 (*Hyp Protection Region Limit Address Register 7*)
@@ -22,7 +25,9 @@ impl Hprlar7 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar7 {}
+
 impl Hprlar7 {
     #[inline]
     /// Writes HPRLAR7 (*Hyp Protection Region Limit Address Register 7*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar8.rs b/aarch32-cpu/src/register/armv8r/hprlar8.rs
index 25b8b2b..67f5246 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar8.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar8.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar8(pub u32);
+
 impl SysReg for Hprlar8 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar8 {
     const CRM: u32 = 12;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprlar8 {}
+
 impl Hprlar8 {
     #[inline]
     /// Reads HPRLAR8 (*Hyp Protection Region Limit Address Register 8*)
@@ -22,7 +25,9 @@ impl Hprlar8 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar8 {}
+
 impl Hprlar8 {
     #[inline]
     /// Writes HPRLAR8 (*Hyp Protection Region Limit Address Register 8*)
diff --git a/aarch32-cpu/src/register/armv8r/hprlar9.rs b/aarch32-cpu/src/register/armv8r/hprlar9.rs
index c7e5c3a..0045976 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar9.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar9.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprlar9(pub u32);
+
 impl SysReg for Hprlar9 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprlar9 {
     const CRM: u32 = 12;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Hprlar9 {}
+
 impl Hprlar9 {
     #[inline]
     /// Reads HPRLAR9 (*Hyp Protection Region Limit Address Register 9*)
@@ -22,7 +25,9 @@ impl Hprlar9 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprlar9 {}
+
 impl Hprlar9 {
     #[inline]
     /// Writes HPRLAR9 (*Hyp Protection Region Limit Address Register 9*)
diff --git a/aarch32-cpu/src/register/armv8r/hprselr.rs b/aarch32-cpu/src/register/armv8r/hprselr.rs
index ebdb443..ea2c18b 100644
--- a/aarch32-cpu/src/register/armv8r/hprselr.rs
+++ b/aarch32-cpu/src/register/armv8r/hprselr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hprselr(pub u32);
+
 impl SysReg for Hprselr {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Hprselr {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Hprselr {}
+
 impl Hprselr {
     #[inline]
     /// Reads HPRSELR (*Hyp Protection Region Selection Register*)
@@ -22,7 +25,9 @@ impl Hprselr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hprselr {}
+
 impl Hprselr {
     #[inline]
     /// Writes HPRSELR (*Hyp Protection Region Selection Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hsctlr.rs b/aarch32-cpu/src/register/armv8r/hsctlr.rs
index f4e7210..b09e65e 100644
--- a/aarch32-cpu/src/register/armv8r/hsctlr.rs
+++ b/aarch32-cpu/src/register/armv8r/hsctlr.rs
@@ -50,7 +50,9 @@ impl SysReg for Hsctlr {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hsctlr {}
+
 impl Hsctlr {
     #[inline]
     /// Reads HSCTLR (*Hyp System Control Register*)
@@ -58,7 +60,9 @@ impl Hsctlr {
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hsctlr {}
+
 impl Hsctlr {
     #[inline]
     /// Writes HSCTLR (*Hyp System Control Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hsr.rs b/aarch32-cpu/src/register/armv8r/hsr.rs
index 1e5bbcb..0075256 100644
--- a/aarch32-cpu/src/register/armv8r/hsr.rs
+++ b/aarch32-cpu/src/register/armv8r/hsr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hsr(pub u32);
+
 impl SysReg for Hsr {
     const CP: u32 = 15;
     const CRN: u32 = 5;
@@ -14,7 +15,9 @@ impl SysReg for Hsr {
     const CRM: u32 = 2;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Hsr {}
+
 impl Hsr {
     #[inline]
     /// Reads HSR (*Hyp Syndrome Register*)
@@ -22,7 +25,9 @@ impl Hsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hsr {}
+
 impl Hsr {
     #[inline]
     /// Writes HSR (*Hyp Syndrome Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hstr.rs b/aarch32-cpu/src/register/armv8r/hstr.rs
index 1d46ee5..331f136 100644
--- a/aarch32-cpu/src/register/armv8r/hstr.rs
+++ b/aarch32-cpu/src/register/armv8r/hstr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Hstr(pub u32);
+
 impl SysReg for Hstr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Hstr {
     const CRM: u32 = 1;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Hstr {}
+
 impl Hstr {
     #[inline]
     /// Reads HSTR (*Hyp System Trap Register*)
@@ -22,7 +25,9 @@ impl Hstr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Hstr {}
+
 impl Hstr {
     #[inline]
     /// Writes HSTR (*Hyp System Trap Register*)
diff --git a/aarch32-cpu/src/register/armv8r/htpidr.rs b/aarch32-cpu/src/register/armv8r/htpidr.rs
index 6491683..7534bf0 100644
--- a/aarch32-cpu/src/register/armv8r/htpidr.rs
+++ b/aarch32-cpu/src/register/armv8r/htpidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Htpidr(pub u32);
+
 impl SysReg for Htpidr {
     const CP: u32 = 15;
     const CRN: u32 = 13;
@@ -14,7 +15,9 @@ impl SysReg for Htpidr {
     const CRM: u32 = 0;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Htpidr {}
+
 impl Htpidr {
     #[inline]
     /// Reads HTPIDR (*Hyp Software Thread ID Register*)
@@ -22,7 +25,9 @@ impl Htpidr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Htpidr {}
+
 impl Htpidr {
     #[inline]
     /// Writes HTPIDR (*Hyp Software Thread ID Register*)
diff --git a/aarch32-cpu/src/register/armv8r/hvbar.rs b/aarch32-cpu/src/register/armv8r/hvbar.rs
index 643f180..f9aebbd 100644
--- a/aarch32-cpu/src/register/armv8r/hvbar.rs
+++ b/aarch32-cpu/src/register/armv8r/hvbar.rs
@@ -7,9 +7,11 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 /// There is no `modify` method because this register holds a single 32-bit address.
 ///
 /// This is only available in EL2.
-#[derive(Clone, Copy, PartialEq, Eq)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
 #[repr(transparent)]
-pub struct Hvbar(*mut u32);
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+pub struct Hvbar(pub u32);
 
 impl SysReg for Hvbar {
     const CP: u32 = 15;
@@ -28,7 +30,7 @@ impl Hvbar {
     #[inline]
     pub fn read() -> Hvbar {
         // Safety: Reading this register has no side-effects and is atomic
-        unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u32) }
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 
     /// Write HVBAR (*Hyp Vector Base Address Register*)
@@ -45,16 +47,3 @@ impl Hvbar {
         }
     }
 }
-
-impl core::fmt::Debug for Hvbar {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "HVBAR {{ {:010p} }}", self.0)
-    }
-}
-
-#[cfg(feature = "defmt")]
-impl defmt::Format for Hvbar {
-    fn format(&self, f: defmt::Formatter) {
-        defmt::write!(f, "HVBAR {{ 0x{=usize:08x} }}", self.0 as usize)
-    }
-}
diff --git a/aarch32-cpu/src/register/armv8r/prbar.rs b/aarch32-cpu/src/register/armv8r/prbar.rs
index b9209d6..399e487 100644
--- a/aarch32-cpu/src/register/armv8r/prbar.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar.rs
@@ -60,7 +60,9 @@ impl SysReg for Prbar {
     const CRM: u32 = 3;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar {}
+
 impl Prbar {
     #[inline]
     /// Reads PRBAR (*Protection Region Base Address Register*)
@@ -68,7 +70,9 @@ impl Prbar {
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar {}
+
 impl Prbar {
     #[inline]
     /// Writes PRBAR (*Protection Region Base Address Register*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar0.rs b/aarch32-cpu/src/register/armv8r/prbar0.rs
index 68f2e8e..46ed63f 100644
--- a/aarch32-cpu/src/register/armv8r/prbar0.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar0(pub u32);
+
 impl SysReg for Prbar0 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar0 {
     const CRM: u32 = 8;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar0 {}
+
 impl Prbar0 {
     #[inline]
     /// Reads PRBAR0 (*Protection Region Base Address Register 0*)
@@ -22,7 +25,9 @@ impl Prbar0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar0 {}
+
 impl Prbar0 {
     #[inline]
     /// Writes PRBAR0 (*Protection Region Base Address Register 0*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar1.rs b/aarch32-cpu/src/register/armv8r/prbar1.rs
index 3449068..3a0f011 100644
--- a/aarch32-cpu/src/register/armv8r/prbar1.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar1(pub u32);
+
 impl SysReg for Prbar1 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar1 {
     const CRM: u32 = 8;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Prbar1 {}
+
 impl Prbar1 {
     #[inline]
     /// Reads PRBAR1 (*Protection Region Base Address Register 1*)
@@ -22,7 +25,9 @@ impl Prbar1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar1 {}
+
 impl Prbar1 {
     #[inline]
     /// Writes PRBAR1 (*Protection Region Base Address Register 1*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar10.rs b/aarch32-cpu/src/register/armv8r/prbar10.rs
index 92a8316..c4a1f10 100644
--- a/aarch32-cpu/src/register/armv8r/prbar10.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar10.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar10(pub u32);
+
 impl SysReg for Prbar10 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar10 {
     const CRM: u32 = 13;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar10 {}
+
 impl Prbar10 {
     #[inline]
     /// Reads PRBAR10 (*Protection Region Base Address Register 10*)
@@ -22,7 +25,9 @@ impl Prbar10 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar10 {}
+
 impl Prbar10 {
     #[inline]
     /// Writes PRBAR10 (*Protection Region Base Address Register 10*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar11.rs b/aarch32-cpu/src/register/armv8r/prbar11.rs
index ed203fa..d3aacd5 100644
--- a/aarch32-cpu/src/register/armv8r/prbar11.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar11.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar11(pub u32);
+
 impl SysReg for Prbar11 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar11 {
     const CRM: u32 = 13;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Prbar11 {}
+
 impl Prbar11 {
     #[inline]
     /// Reads PRBAR11 (*Protection Region Base Address Register 11*)
@@ -22,7 +25,9 @@ impl Prbar11 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar11 {}
+
 impl Prbar11 {
     #[inline]
     /// Writes PRBAR11 (*Protection Region Base Address Register 11*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar12.rs b/aarch32-cpu/src/register/armv8r/prbar12.rs
index d1c7f64..c6d2db6 100644
--- a/aarch32-cpu/src/register/armv8r/prbar12.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar12.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar12(pub u32);
+
 impl SysReg for Prbar12 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar12 {
     const CRM: u32 = 14;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar12 {}
+
 impl Prbar12 {
     #[inline]
     /// Reads PRBAR12 (*Protection Region Base Address Register 12*)
@@ -22,7 +25,9 @@ impl Prbar12 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar12 {}
+
 impl Prbar12 {
     #[inline]
     /// Writes PRBAR12 (*Protection Region Base Address Register 12*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar13.rs b/aarch32-cpu/src/register/armv8r/prbar13.rs
index e6b8ee5..aab6a59 100644
--- a/aarch32-cpu/src/register/armv8r/prbar13.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar13.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar13(pub u32);
+
 impl SysReg for Prbar13 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar13 {
     const CRM: u32 = 14;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Prbar13 {}
+
 impl Prbar13 {
     #[inline]
     /// Reads PRBAR13 (*Protection Region Base Address Register 13*)
@@ -22,7 +25,9 @@ impl Prbar13 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar13 {}
+
 impl Prbar13 {
     #[inline]
     /// Writes PRBAR13 (*Protection Region Base Address Register 13*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar14.rs b/aarch32-cpu/src/register/armv8r/prbar14.rs
index bb94534..e502ecf 100644
--- a/aarch32-cpu/src/register/armv8r/prbar14.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar14.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar14(pub u32);
+
 impl SysReg for Prbar14 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar14 {
     const CRM: u32 = 15;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar14 {}
+
 impl Prbar14 {
     #[inline]
     /// Reads PRBAR14 (*Protection Region Base Address Register 14*)
@@ -22,7 +25,9 @@ impl Prbar14 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar14 {}
+
 impl Prbar14 {
     #[inline]
     /// Writes PRBAR14 (*Protection Region Base Address Register 14*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar15.rs b/aarch32-cpu/src/register/armv8r/prbar15.rs
index 61c8d09..db55d24 100644
--- a/aarch32-cpu/src/register/armv8r/prbar15.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar15.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar15(pub u32);
+
 impl SysReg for Prbar15 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar15 {
     const CRM: u32 = 15;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Prbar15 {}
+
 impl Prbar15 {
     #[inline]
     /// Reads PRBAR15 (*Protection Region Base Address Register 15*)
@@ -22,7 +25,9 @@ impl Prbar15 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar15 {}
+
 impl Prbar15 {
     #[inline]
     /// Writes PRBAR15 (*Protection Region Base Address Register 15*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar2.rs b/aarch32-cpu/src/register/armv8r/prbar2.rs
index 2e804fc..6ad526a 100644
--- a/aarch32-cpu/src/register/armv8r/prbar2.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar2(pub u32);
+
 impl SysReg for Prbar2 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar2 {
     const CRM: u32 = 9;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar2 {}
+
 impl Prbar2 {
     #[inline]
     /// Reads PRBAR2 (*Protection Region Base Address Register 2*)
@@ -22,7 +25,9 @@ impl Prbar2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar2 {}
+
 impl Prbar2 {
     #[inline]
     /// Writes PRBAR2 (*Protection Region Base Address Register 2*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar3.rs b/aarch32-cpu/src/register/armv8r/prbar3.rs
index 79dc96f..b219626 100644
--- a/aarch32-cpu/src/register/armv8r/prbar3.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar3.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar3(pub u32);
+
 impl SysReg for Prbar3 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar3 {
     const CRM: u32 = 9;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Prbar3 {}
+
 impl Prbar3 {
     #[inline]
     /// Reads PRBAR3 (*Protection Region Base Address Register 3*)
@@ -22,7 +25,9 @@ impl Prbar3 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar3 {}
+
 impl Prbar3 {
     #[inline]
     /// Writes PRBAR3 (*Protection Region Base Address Register 3*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar4.rs b/aarch32-cpu/src/register/armv8r/prbar4.rs
index 58e3574..6593c93 100644
--- a/aarch32-cpu/src/register/armv8r/prbar4.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar4.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar4(pub u32);
+
 impl SysReg for Prbar4 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar4 {
     const CRM: u32 = 10;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar4 {}
+
 impl Prbar4 {
     #[inline]
     /// Reads PRBAR4 (*Protection Region Base Address Register 4*)
@@ -22,7 +25,9 @@ impl Prbar4 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar4 {}
+
 impl Prbar4 {
     #[inline]
     /// Writes PRBAR4 (*Protection Region Base Address Register 4*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar5.rs b/aarch32-cpu/src/register/armv8r/prbar5.rs
index 6abb6f7..c96149a 100644
--- a/aarch32-cpu/src/register/armv8r/prbar5.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar5.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar5(pub u32);
+
 impl SysReg for Prbar5 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar5 {
     const CRM: u32 = 10;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Prbar5 {}
+
 impl Prbar5 {
     #[inline]
     /// Reads PRBAR5 (*Protection Region Base Address Register 5*)
@@ -22,7 +25,9 @@ impl Prbar5 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar5 {}
+
 impl Prbar5 {
     #[inline]
     /// Writes PRBAR5 (*Protection Region Base Address Register 5*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar6.rs b/aarch32-cpu/src/register/armv8r/prbar6.rs
index 3e03d0b..9000561 100644
--- a/aarch32-cpu/src/register/armv8r/prbar6.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar6.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar6(pub u32);
+
 impl SysReg for Prbar6 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar6 {
     const CRM: u32 = 11;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar6 {}
+
 impl Prbar6 {
     #[inline]
     /// Reads PRBAR6 (*Protection Region Base Address Register 6*)
@@ -22,7 +25,9 @@ impl Prbar6 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar6 {}
+
 impl Prbar6 {
     #[inline]
     /// Writes PRBAR6 (*Protection Region Base Address Register 6*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar7.rs b/aarch32-cpu/src/register/armv8r/prbar7.rs
index e1791d7..45d7c50 100644
--- a/aarch32-cpu/src/register/armv8r/prbar7.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar7.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar7(pub u32);
+
 impl SysReg for Prbar7 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar7 {
     const CRM: u32 = 11;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Prbar7 {}
+
 impl Prbar7 {
     #[inline]
     /// Reads PRBAR7 (*Protection Region Base Address Register 7*)
@@ -22,7 +25,9 @@ impl Prbar7 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar7 {}
+
 impl Prbar7 {
     #[inline]
     /// Writes PRBAR7 (*Protection Region Base Address Register 7*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar8.rs b/aarch32-cpu/src/register/armv8r/prbar8.rs
index bfcde93..bfecb4f 100644
--- a/aarch32-cpu/src/register/armv8r/prbar8.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar8.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar8(pub u32);
+
 impl SysReg for Prbar8 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar8 {
     const CRM: u32 = 12;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Prbar8 {}
+
 impl Prbar8 {
     #[inline]
     /// Reads PRBAR8 (*Protection Region Base Address Register 8*)
@@ -22,7 +25,9 @@ impl Prbar8 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar8 {}
+
 impl Prbar8 {
     #[inline]
     /// Writes PRBAR8 (*Protection Region Base Address Register 8*)
diff --git a/aarch32-cpu/src/register/armv8r/prbar9.rs b/aarch32-cpu/src/register/armv8r/prbar9.rs
index 19da2fa..fcd036d 100644
--- a/aarch32-cpu/src/register/armv8r/prbar9.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar9.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prbar9(pub u32);
+
 impl SysReg for Prbar9 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prbar9 {
     const CRM: u32 = 12;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Prbar9 {}
+
 impl Prbar9 {
     #[inline]
     /// Reads PRBAR9 (*Protection Region Base Address Register 9*)
@@ -22,7 +25,9 @@ impl Prbar9 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prbar9 {}
+
 impl Prbar9 {
     #[inline]
     /// Writes PRBAR9 (*Protection Region Base Address Register 9*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar.rs b/aarch32-cpu/src/register/armv8r/prlar.rs
index a4804ba..042bb01 100644
--- a/aarch32-cpu/src/register/armv8r/prlar.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar.rs
@@ -25,7 +25,9 @@ impl SysReg for Prlar {
     const CRM: u32 = 3;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar {}
+
 impl Prlar {
     #[inline]
     /// Reads PRLAR (*Protection Region Limit Address Register*)
@@ -33,7 +35,9 @@ impl Prlar {
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar {}
+
 impl Prlar {
     #[inline]
     /// Writes PRLAR (*Protection Region Limit Address Register*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar0.rs b/aarch32-cpu/src/register/armv8r/prlar0.rs
index 9d1cbf0..5ef43af 100644
--- a/aarch32-cpu/src/register/armv8r/prlar0.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar0(pub u32);
+
 impl SysReg for Prlar0 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar0 {
     const CRM: u32 = 8;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar0 {}
+
 impl Prlar0 {
     #[inline]
     /// Reads PRLAR0 (*Protection Region Limit Address Register 0*)
@@ -22,7 +25,9 @@ impl Prlar0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar0 {}
+
 impl Prlar0 {
     #[inline]
     /// Writes PRLAR0 (*Protection Region Limit Address Register 0*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar1.rs b/aarch32-cpu/src/register/armv8r/prlar1.rs
index e0680a9..24e8df9 100644
--- a/aarch32-cpu/src/register/armv8r/prlar1.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar1(pub u32);
+
 impl SysReg for Prlar1 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar1 {
     const CRM: u32 = 8;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Prlar1 {}
+
 impl Prlar1 {
     #[inline]
     /// Reads PRLAR1 (*Protection Region Limit Address Register 1*)
@@ -22,7 +25,9 @@ impl Prlar1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar1 {}
+
 impl Prlar1 {
     #[inline]
     /// Writes PRLAR1 (*Protection Region Limit Address Register 1*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar10.rs b/aarch32-cpu/src/register/armv8r/prlar10.rs
index d2ca155..991ff15 100644
--- a/aarch32-cpu/src/register/armv8r/prlar10.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar10.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar10(pub u32);
+
 impl SysReg for Prlar10 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar10 {
     const CRM: u32 = 13;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar10 {}
+
 impl Prlar10 {
     #[inline]
     /// Reads PRLAR10 (*Protection Region Limit Address Register 10*)
@@ -22,7 +25,9 @@ impl Prlar10 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar10 {}
+
 impl Prlar10 {
     #[inline]
     /// Writes PRLAR10 (*Protection Region Limit Address Register 10*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar11.rs b/aarch32-cpu/src/register/armv8r/prlar11.rs
index d2dd657..713ba11 100644
--- a/aarch32-cpu/src/register/armv8r/prlar11.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar11.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar11(pub u32);
+
 impl SysReg for Prlar11 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar11 {
     const CRM: u32 = 13;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Prlar11 {}
+
 impl Prlar11 {
     #[inline]
     /// Reads PRLAR11 (*Protection Region Limit Address Register 11*)
@@ -22,7 +25,9 @@ impl Prlar11 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar11 {}
+
 impl Prlar11 {
     #[inline]
     /// Writes PRLAR11 (*Protection Region Limit Address Register 11*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar12.rs b/aarch32-cpu/src/register/armv8r/prlar12.rs
index 4c777a2..9d0973c 100644
--- a/aarch32-cpu/src/register/armv8r/prlar12.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar12.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar12(pub u32);
+
 impl SysReg for Prlar12 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar12 {
     const CRM: u32 = 14;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar12 {}
+
 impl Prlar12 {
     #[inline]
     /// Reads PRLAR12 (*Protection Region Limit Address Register 12*)
@@ -22,7 +25,9 @@ impl Prlar12 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar12 {}
+
 impl Prlar12 {
     #[inline]
     /// Writes PRLAR12 (*Protection Region Limit Address Register 12*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar13.rs b/aarch32-cpu/src/register/armv8r/prlar13.rs
index c8e414f..b31d0cd 100644
--- a/aarch32-cpu/src/register/armv8r/prlar13.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar13.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar13(pub u32);
+
 impl SysReg for Prlar13 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar13 {
     const CRM: u32 = 14;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Prlar13 {}
+
 impl Prlar13 {
     #[inline]
     /// Reads PRLAR13 (*Protection Region Limit Address Register 13*)
@@ -22,7 +25,9 @@ impl Prlar13 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar13 {}
+
 impl Prlar13 {
     #[inline]
     /// Writes PRLAR13 (*Protection Region Limit Address Register 13*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar14.rs b/aarch32-cpu/src/register/armv8r/prlar14.rs
index 7dde72e..ad7f070 100644
--- a/aarch32-cpu/src/register/armv8r/prlar14.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar14.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar14(pub u32);
+
 impl SysReg for Prlar14 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar14 {
     const CRM: u32 = 15;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar14 {}
+
 impl Prlar14 {
     #[inline]
     /// Reads PRLAR14 (*Protection Region Limit Address Register 14*)
@@ -22,7 +25,9 @@ impl Prlar14 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar14 {}
+
 impl Prlar14 {
     #[inline]
     /// Writes PRLAR14 (*Protection Region Limit Address Register 14*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar15.rs b/aarch32-cpu/src/register/armv8r/prlar15.rs
index 9cc05b5..e2c93e5 100644
--- a/aarch32-cpu/src/register/armv8r/prlar15.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar15.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar15(pub u32);
+
 impl SysReg for Prlar15 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar15 {
     const CRM: u32 = 15;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Prlar15 {}
+
 impl Prlar15 {
     #[inline]
     /// Reads PRLAR15 (*Protection Region Limit Address Register 15*)
@@ -22,7 +25,9 @@ impl Prlar15 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar15 {}
+
 impl Prlar15 {
     #[inline]
     /// Writes PRLAR15 (*Protection Region Limit Address Register 15*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar2.rs b/aarch32-cpu/src/register/armv8r/prlar2.rs
index b918918..9164a06 100644
--- a/aarch32-cpu/src/register/armv8r/prlar2.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar2(pub u32);
+
 impl SysReg for Prlar2 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar2 {
     const CRM: u32 = 9;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar2 {}
+
 impl Prlar2 {
     #[inline]
     /// Reads PRLAR2 (*Protection Region Limit Address Register 2*)
@@ -22,7 +25,9 @@ impl Prlar2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar2 {}
+
 impl Prlar2 {
     #[inline]
     /// Writes PRLAR2 (*Protection Region Limit Address Register 2*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar3.rs b/aarch32-cpu/src/register/armv8r/prlar3.rs
index f7996d5..848a42d 100644
--- a/aarch32-cpu/src/register/armv8r/prlar3.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar3.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar3(pub u32);
+
 impl SysReg for Prlar3 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar3 {
     const CRM: u32 = 9;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Prlar3 {}
+
 impl Prlar3 {
     #[inline]
     /// Reads PRLAR3 (*Protection Region Limit Address Register 3*)
@@ -22,7 +25,9 @@ impl Prlar3 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar3 {}
+
 impl Prlar3 {
     #[inline]
     /// Writes PRLAR3 (*Protection Region Limit Address Register 3*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar4.rs b/aarch32-cpu/src/register/armv8r/prlar4.rs
index db4442d..dac02e9 100644
--- a/aarch32-cpu/src/register/armv8r/prlar4.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar4.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar4(pub u32);
+
 impl SysReg for Prlar4 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar4 {
     const CRM: u32 = 10;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar4 {}
+
 impl Prlar4 {
     #[inline]
     /// Reads PRLAR4 (*Protection Region Limit Address Register 4*)
@@ -22,7 +25,9 @@ impl Prlar4 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar4 {}
+
 impl Prlar4 {
     #[inline]
     /// Writes PRLAR4 (*Protection Region Limit Address Register 4*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar5.rs b/aarch32-cpu/src/register/armv8r/prlar5.rs
index b006807..0cd9e91 100644
--- a/aarch32-cpu/src/register/armv8r/prlar5.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar5.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar5(pub u32);
+
 impl SysReg for Prlar5 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar5 {
     const CRM: u32 = 10;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Prlar5 {}
+
 impl Prlar5 {
     #[inline]
     /// Reads PRLAR5 (*Protection Region Limit Address Register 5*)
@@ -22,7 +25,9 @@ impl Prlar5 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar5 {}
+
 impl Prlar5 {
     #[inline]
     /// Writes PRLAR5 (*Protection Region Limit Address Register 5*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar6.rs b/aarch32-cpu/src/register/armv8r/prlar6.rs
index 7fe777e..3c4b7a0 100644
--- a/aarch32-cpu/src/register/armv8r/prlar6.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar6.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar6(pub u32);
+
 impl SysReg for Prlar6 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar6 {
     const CRM: u32 = 11;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar6 {}
+
 impl Prlar6 {
     #[inline]
     /// Reads PRLAR6 (*Protection Region Limit Address Register 6*)
@@ -22,7 +25,9 @@ impl Prlar6 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar6 {}
+
 impl Prlar6 {
     #[inline]
     /// Writes PRLAR6 (*Protection Region Limit Address Register 6*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar7.rs b/aarch32-cpu/src/register/armv8r/prlar7.rs
index ab4e617..ae971f0 100644
--- a/aarch32-cpu/src/register/armv8r/prlar7.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar7.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar7(pub u32);
+
 impl SysReg for Prlar7 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar7 {
     const CRM: u32 = 11;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Prlar7 {}
+
 impl Prlar7 {
     #[inline]
     /// Reads PRLAR7 (*Protection Region Limit Address Register 7*)
@@ -22,7 +25,9 @@ impl Prlar7 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar7 {}
+
 impl Prlar7 {
     #[inline]
     /// Writes PRLAR7 (*Protection Region Limit Address Register 7*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar8.rs b/aarch32-cpu/src/register/armv8r/prlar8.rs
index 9b14e5f..e1951cf 100644
--- a/aarch32-cpu/src/register/armv8r/prlar8.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar8.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar8(pub u32);
+
 impl SysReg for Prlar8 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar8 {
     const CRM: u32 = 12;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prlar8 {}
+
 impl Prlar8 {
     #[inline]
     /// Reads PRLAR8 (*Protection Region Limit Address Register 8*)
@@ -22,7 +25,9 @@ impl Prlar8 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar8 {}
+
 impl Prlar8 {
     #[inline]
     /// Writes PRLAR8 (*Protection Region Limit Address Register 8*)
diff --git a/aarch32-cpu/src/register/armv8r/prlar9.rs b/aarch32-cpu/src/register/armv8r/prlar9.rs
index 8149f2a..d61aaf4 100644
--- a/aarch32-cpu/src/register/armv8r/prlar9.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar9.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prlar9(pub u32);
+
 impl SysReg for Prlar9 {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prlar9 {
     const CRM: u32 = 12;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Prlar9 {}
+
 impl Prlar9 {
     #[inline]
     /// Reads PRLAR9 (*Protection Region Limit Address Register 9*)
@@ -22,7 +25,9 @@ impl Prlar9 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prlar9 {}
+
 impl Prlar9 {
     #[inline]
     /// Writes PRLAR9 (*Protection Region Limit Address Register 9*)
diff --git a/aarch32-cpu/src/register/armv8r/prselr.rs b/aarch32-cpu/src/register/armv8r/prselr.rs
index 267b275..01f3e6c 100644
--- a/aarch32-cpu/src/register/armv8r/prselr.rs
+++ b/aarch32-cpu/src/register/armv8r/prselr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Prselr(pub u32);
+
 impl SysReg for Prselr {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Prselr {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Prselr {}
+
 impl Prselr {
     #[inline]
     /// Reads PRSELR (*Protection Region Selection Register*)
@@ -22,7 +25,9 @@ impl Prselr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Prselr {}
+
 impl Prselr {
     #[inline]
     /// Writes PRSELR (*Protection Region Selection Register*)
diff --git a/aarch32-cpu/src/register/armv8r/vbar.rs b/aarch32-cpu/src/register/armv8r/vbar.rs
index f81f140..b6d6672 100644
--- a/aarch32-cpu/src/register/armv8r/vbar.rs
+++ b/aarch32-cpu/src/register/armv8r/vbar.rs
@@ -5,10 +5,11 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 /// VBAR (*Vector Base Address Register*)
 ///
 /// There is no `modify` method because this register holds a single 32-bit address.
-#[derive(Clone, Copy, PartialEq, Eq)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
 #[repr(transparent)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
-pub struct Vbar(pub *mut u32);
+pub struct Vbar(pub u32);
 
 impl SysReg for Vbar {
     const CP: u32 = 15;
@@ -27,7 +28,7 @@ impl Vbar {
     #[inline]
     pub fn read() -> Vbar {
         // Safety: Reading this register has no side-effects and is atomic
-        unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u32) }
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 
     /// Write VBAR (*Vector Base Address Register*)
@@ -44,16 +45,3 @@ impl Vbar {
         }
     }
 }
-
-impl core::fmt::Debug for Vbar {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "VBAR {{ {:010p} }}", self.0)
-    }
-}
-
-#[cfg(feature = "defmt")]
-impl defmt::Format for Vbar {
-    fn format(&self, f: defmt::Formatter) {
-        defmt::write!(f, "VBAR {{ 0x{=usize:08x} }}", self.0 as usize)
-    }
-}
diff --git a/aarch32-cpu/src/register/clidr.rs b/aarch32-cpu/src/register/clidr.rs
index b77ba2a..25b7803 100644
--- a/aarch32-cpu/src/register/clidr.rs
+++ b/aarch32-cpu/src/register/clidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Clidr(pub u32);
+
 impl SysReg for Clidr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Clidr {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Clidr {}
+
 impl Clidr {
     #[inline]
     /// Reads CLIDR (*Cache Level ID Register*)
diff --git a/aarch32-cpu/src/register/contextidr.rs b/aarch32-cpu/src/register/contextidr.rs
index 2a58179..9c503fe 100644
--- a/aarch32-cpu/src/register/contextidr.rs
+++ b/aarch32-cpu/src/register/contextidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Contextidr(pub u32);
+
 impl SysReg for Contextidr {
     const CP: u32 = 15;
     const CRN: u32 = 13;
@@ -14,7 +15,9 @@ impl SysReg for Contextidr {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Contextidr {}
+
 impl Contextidr {
     #[inline]
     /// Reads CONTEXTIDR (*Context ID Register*)
@@ -22,7 +25,9 @@ impl Contextidr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Contextidr {}
+
 impl Contextidr {
     #[inline]
     /// Writes CONTEXTIDR (*Context ID Register*)
diff --git a/aarch32-cpu/src/register/cpacr.rs b/aarch32-cpu/src/register/cpacr.rs
index aeca387..29a5c55 100644
--- a/aarch32-cpu/src/register/cpacr.rs
+++ b/aarch32-cpu/src/register/cpacr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Cpacr(pub u32);
+
 impl SysReg for Cpacr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Cpacr {
     const CRM: u32 = 0;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Cpacr {}
+
 impl Cpacr {
     #[inline]
     /// Reads CPACR (*Architectural Feature Access Control Register*)
@@ -22,7 +25,9 @@ impl Cpacr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Cpacr {}
+
 impl Cpacr {
     #[inline]
     /// Writes CPACR (*Architectural Feature Access Control Register*)
diff --git a/aarch32-cpu/src/register/csselr.rs b/aarch32-cpu/src/register/csselr.rs
index 7f5ad86..eed4831 100644
--- a/aarch32-cpu/src/register/csselr.rs
+++ b/aarch32-cpu/src/register/csselr.rs
@@ -31,7 +31,9 @@ impl SysReg for Csselr {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Csselr {}
+
 impl Csselr {
     #[inline]
     /// Reads CSSELR (*Cache Size Selection Register*)
@@ -39,7 +41,9 @@ impl Csselr {
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Csselr {}
+
 impl Csselr {
     #[inline]
     /// Writes CSSELR (*Cache Size Selection Register*)
diff --git a/aarch32-cpu/src/register/ctr.rs b/aarch32-cpu/src/register/ctr.rs
index 3a24459..14b9c1b 100644
--- a/aarch32-cpu/src/register/ctr.rs
+++ b/aarch32-cpu/src/register/ctr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Ctr(pub u32);
+
 impl SysReg for Ctr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Ctr {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Ctr {}
+
 impl Ctr {
     #[inline]
     /// Reads CTR (*Cache Type Register*)
diff --git a/aarch32-cpu/src/register/dccisw.rs b/aarch32-cpu/src/register/dccisw.rs
index 34bbb22..d4657c0 100644
--- a/aarch32-cpu/src/register/dccisw.rs
+++ b/aarch32-cpu/src/register/dccisw.rs
@@ -39,6 +39,7 @@ impl Dccisw {
         Self(super::dc_sw_ops::new_with_offsets(a, way, n, set, level))
     }
 }
+
 impl SysReg for Dccisw {
     const CP: u32 = 15;
     const CRN: u32 = 7;
diff --git a/aarch32-cpu/src/register/dccmvau.rs b/aarch32-cpu/src/register/dccmvau.rs
index 8356f86..ee64f97 100644
--- a/aarch32-cpu/src/register/dccmvau.rs
+++ b/aarch32-cpu/src/register/dccmvau.rs
@@ -12,6 +12,7 @@ impl Dccmvau {
         Self(addr)
     }
 }
+
 impl SysReg for Dccmvau {
     const CP: u32 = 15;
     const CRN: u32 = 7;
diff --git a/aarch32-cpu/src/register/dccsw.rs b/aarch32-cpu/src/register/dccsw.rs
index ea17426..639e283 100644
--- a/aarch32-cpu/src/register/dccsw.rs
+++ b/aarch32-cpu/src/register/dccsw.rs
@@ -39,6 +39,7 @@ impl Dccsw {
         Self(super::dc_sw_ops::new_with_offsets(a, way, n, set, level))
     }
 }
+
 impl SysReg for Dccsw {
     const CP: u32 = 15;
     const CRN: u32 = 7;
diff --git a/aarch32-cpu/src/register/dcisw.rs b/aarch32-cpu/src/register/dcisw.rs
index fa1a260..42188b1 100644
--- a/aarch32-cpu/src/register/dcisw.rs
+++ b/aarch32-cpu/src/register/dcisw.rs
@@ -39,6 +39,7 @@ impl Dcisw {
         Self(super::dc_sw_ops::new_with_offsets(a, way, n, set, level))
     }
 }
+
 impl SysReg for Dcisw {
     const CP: u32 = 15;
     const CRN: u32 = 7;
diff --git a/aarch32-cpu/src/register/dfar.rs b/aarch32-cpu/src/register/dfar.rs
index 0849c96..7fa38db 100644
--- a/aarch32-cpu/src/register/dfar.rs
+++ b/aarch32-cpu/src/register/dfar.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Dfar(pub u32);
+
 impl SysReg for Dfar {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Dfar {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Dfar {}
+
 impl Dfar {
     #[inline]
     /// Reads DFAR (*Data Fault Address Register*)
@@ -22,7 +25,9 @@ impl Dfar {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Dfar {}
+
 impl Dfar {
     #[inline]
     /// Writes DFAR (*Data Fault Address Register*)
diff --git a/aarch32-cpu/src/register/dfsr.rs b/aarch32-cpu/src/register/dfsr.rs
index d9865ce..6a59e3a 100644
--- a/aarch32-cpu/src/register/dfsr.rs
+++ b/aarch32-cpu/src/register/dfsr.rs
@@ -56,7 +56,9 @@ impl SysReg for Dfsr {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Dfsr {}
+
 impl Dfsr {
     pub fn status(&self) -> Result<DfsrStatus, u8> {
         let status = self.status_raw().as_u8();
@@ -69,7 +71,9 @@ impl Dfsr {
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Dfsr {}
+
 impl Dfsr {
     #[inline]
     /// Writes DFSR (*Data Fault Status Register*)
diff --git a/aarch32-cpu/src/register/dlr.rs b/aarch32-cpu/src/register/dlr.rs
index 7155230..03c7f53 100644
--- a/aarch32-cpu/src/register/dlr.rs
+++ b/aarch32-cpu/src/register/dlr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Dlr(pub u32);
+
 impl SysReg for Dlr {
     const CP: u32 = 15;
     const CRN: u32 = 4;
@@ -14,7 +15,9 @@ impl SysReg for Dlr {
     const CRM: u32 = 5;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Dlr {}
+
 impl Dlr {
     #[inline]
     /// Reads DLR (*Debug Link Register*)
@@ -22,7 +25,9 @@ impl Dlr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Dlr {}
+
 impl Dlr {
     #[inline]
     /// Writes DLR (*Debug Link Register*)
diff --git a/aarch32-cpu/src/register/dracr.rs b/aarch32-cpu/src/register/dracr.rs
index 6e5aa98..5edd99c 100644
--- a/aarch32-cpu/src/register/dracr.rs
+++ b/aarch32-cpu/src/register/dracr.rs
@@ -35,7 +35,9 @@ impl SysReg for Dracr {
     const CRM: u32 = 1;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Dracr {}
+
 impl Dracr {
     #[inline]
     /// Reads DRACR (*Data Region Access Control Register*)
@@ -47,6 +49,7 @@ impl Dracr {
 }
 
 impl crate::register::SysRegWrite for Dracr {}
+
 impl Dracr {
     #[inline]
     /// Writes DRACR (*Data Region Access Control Register*)
diff --git a/aarch32-cpu/src/register/drbar.rs b/aarch32-cpu/src/register/drbar.rs
index b513e13..5e5f85f 100644
--- a/aarch32-cpu/src/register/drbar.rs
+++ b/aarch32-cpu/src/register/drbar.rs
@@ -3,9 +3,11 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// DRBAR (*Data Region Base Address Register*)
-#[derive(Debug, Copy, Clone)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(transparent)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct Drbar(pub *mut u8);
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+pub struct Drbar(pub u32);
 
 impl SysReg for Drbar {
     const CP: u32 = 15;
@@ -14,24 +16,27 @@ impl SysReg for Drbar {
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Drbar {}
+
 impl Drbar {
     #[inline]
     /// Reads DRBAR (*Data Region Base Address Register*)
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Drbar {
-        unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u8) }
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
 
 impl crate::register::SysRegWrite for Drbar {}
+
 impl Drbar {
     #[inline]
     /// Writes DRBAR (*Data Region Base Address Register*)
     ///
     /// Set RGNR to control which region this affects.
     pub fn write(value: Drbar) {
-        unsafe { <Self as SysRegWrite>::write_raw(value.0 as u32) }
+        unsafe { <Self as SysRegWrite>::write_raw(value.0) }
     }
 }
diff --git a/aarch32-cpu/src/register/drsr.rs b/aarch32-cpu/src/register/drsr.rs
index b1fe4dc..b0d893c 100644
--- a/aarch32-cpu/src/register/drsr.rs
+++ b/aarch32-cpu/src/register/drsr.rs
@@ -118,7 +118,9 @@ impl SysReg for Drsr {
     const CRM: u32 = 1;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Drsr {}
+
 impl Drsr {
     #[inline]
     /// Reads DRSR (*Data Region Size and Enable Register*)
@@ -130,6 +132,7 @@ impl Drsr {
 }
 
 impl crate::register::SysRegWrite for Drsr {}
+
 impl Drsr {
     #[inline]
     /// Writes DRSR (*Data Region Size and Enable Register*)
diff --git a/aarch32-cpu/src/register/dspsr.rs b/aarch32-cpu/src/register/dspsr.rs
index c34b3ee..ad5287b 100644
--- a/aarch32-cpu/src/register/dspsr.rs
+++ b/aarch32-cpu/src/register/dspsr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Dspsr(pub u32);
+
 impl SysReg for Dspsr {
     const CP: u32 = 15;
     const CRN: u32 = 4;
@@ -14,7 +15,9 @@ impl SysReg for Dspsr {
     const CRM: u32 = 5;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Dspsr {}
+
 impl Dspsr {
     #[inline]
     /// Reads DSPSR (*Debug Saved Program Status Register*)
@@ -22,7 +25,9 @@ impl Dspsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Dspsr {}
+
 impl Dspsr {
     #[inline]
     /// Writes DSPSR (*Debug Saved Program Status Register*)
diff --git a/aarch32-cpu/src/register/fcseidr.rs b/aarch32-cpu/src/register/fcseidr.rs
index dccc125..1ad63f0 100644
--- a/aarch32-cpu/src/register/fcseidr.rs
+++ b/aarch32-cpu/src/register/fcseidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Fcseidr(pub u32);
+
 impl SysReg for Fcseidr {
     const CP: u32 = 15;
     const CRN: u32 = 13;
@@ -14,7 +15,9 @@ impl SysReg for Fcseidr {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Fcseidr {}
+
 impl Fcseidr {
     #[inline]
     /// Reads FCSEIDR (*FCSE Process ID Register*)
@@ -22,7 +25,9 @@ impl Fcseidr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Fcseidr {}
+
 impl Fcseidr {
     #[inline]
     /// Writes FCSEIDR (*FCSE Process ID Register*)
diff --git a/aarch32-cpu/src/register/icc_pmr.rs b/aarch32-cpu/src/register/icc_pmr.rs
index 94a138b..7e5c77b 100644
--- a/aarch32-cpu/src/register/icc_pmr.rs
+++ b/aarch32-cpu/src/register/icc_pmr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IccPmr(pub u32);
+
 impl SysReg for IccPmr {
     const CP: u32 = 15;
     const CRN: u32 = 4;
@@ -14,7 +15,9 @@ impl SysReg for IccPmr {
     const CRM: u32 = 6;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for IccPmr {}
+
 impl IccPmr {
     #[inline]
     /// Reads ICC_PMR (*Interrupt Controller Interrupt Priority Mask Register*)
@@ -22,7 +25,9 @@ impl IccPmr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for IccPmr {}
+
 impl IccPmr {
     #[inline]
     /// Writes ICC_PMR (*Interrupt Controller Interrupt Priority Mask Register*)
diff --git a/aarch32-cpu/src/register/id_afr0.rs b/aarch32-cpu/src/register/id_afr0.rs
index ebcbdb2..54fbf32 100644
--- a/aarch32-cpu/src/register/id_afr0.rs
+++ b/aarch32-cpu/src/register/id_afr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdAfr0(pub u32);
+
 impl SysReg for IdAfr0 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdAfr0 {
     const CRM: u32 = 1;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for IdAfr0 {}
+
 impl IdAfr0 {
     #[inline]
     /// Reads ID_AFR0 (*Auxiliary Feature Register 0*)
diff --git a/aarch32-cpu/src/register/id_dfr0.rs b/aarch32-cpu/src/register/id_dfr0.rs
index 83da1bd..c19b0e4 100644
--- a/aarch32-cpu/src/register/id_dfr0.rs
+++ b/aarch32-cpu/src/register/id_dfr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdDfr0(pub u32);
+
 impl SysReg for IdDfr0 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdDfr0 {
     const CRM: u32 = 1;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for IdDfr0 {}
+
 impl IdDfr0 {
     #[inline]
     /// Reads ID_DFR0 (*Debug Feature Register 0*)
diff --git a/aarch32-cpu/src/register/id_isar0.rs b/aarch32-cpu/src/register/id_isar0.rs
index 666203b..63cf885 100644
--- a/aarch32-cpu/src/register/id_isar0.rs
+++ b/aarch32-cpu/src/register/id_isar0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdIsar0(pub u32);
+
 impl SysReg for IdIsar0 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdIsar0 {
     const CRM: u32 = 2;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for IdIsar0 {}
+
 impl IdIsar0 {
     #[inline]
     /// Reads ID_ISAR0 (*Instruction Set Attribute Register 0*)
diff --git a/aarch32-cpu/src/register/id_isar1.rs b/aarch32-cpu/src/register/id_isar1.rs
index eb7faa2..4fdce86 100644
--- a/aarch32-cpu/src/register/id_isar1.rs
+++ b/aarch32-cpu/src/register/id_isar1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdIsar1(pub u32);
+
 impl SysReg for IdIsar1 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdIsar1 {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for IdIsar1 {}
+
 impl IdIsar1 {
     #[inline]
     /// Reads ID_ISAR1 (*Instruction Set Attribute Register 1*)
diff --git a/aarch32-cpu/src/register/id_isar2.rs b/aarch32-cpu/src/register/id_isar2.rs
index 1873b13..84b9d0a 100644
--- a/aarch32-cpu/src/register/id_isar2.rs
+++ b/aarch32-cpu/src/register/id_isar2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdIsar2(pub u32);
+
 impl SysReg for IdIsar2 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdIsar2 {
     const CRM: u32 = 2;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for IdIsar2 {}
+
 impl IdIsar2 {
     #[inline]
     /// Reads ID_ISAR2 (*Instruction Set Attribute Register 2*)
diff --git a/aarch32-cpu/src/register/id_isar3.rs b/aarch32-cpu/src/register/id_isar3.rs
index 3381b8b..6676431 100644
--- a/aarch32-cpu/src/register/id_isar3.rs
+++ b/aarch32-cpu/src/register/id_isar3.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdIsar3(pub u32);
+
 impl SysReg for IdIsar3 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdIsar3 {
     const CRM: u32 = 2;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for IdIsar3 {}
+
 impl IdIsar3 {
     #[inline]
     /// Reads ID_ISAR3 (*Instruction Set Attribute Register 3*)
diff --git a/aarch32-cpu/src/register/id_isar4.rs b/aarch32-cpu/src/register/id_isar4.rs
index 54259f9..8d2cab9 100644
--- a/aarch32-cpu/src/register/id_isar4.rs
+++ b/aarch32-cpu/src/register/id_isar4.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdIsar4(pub u32);
+
 impl SysReg for IdIsar4 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdIsar4 {
     const CRM: u32 = 2;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for IdIsar4 {}
+
 impl IdIsar4 {
     #[inline]
     /// Reads ID_ISAR4 (*Instruction Set Attribute Register 4*)
diff --git a/aarch32-cpu/src/register/id_isar5.rs b/aarch32-cpu/src/register/id_isar5.rs
index 6682f13..ed6540d 100644
--- a/aarch32-cpu/src/register/id_isar5.rs
+++ b/aarch32-cpu/src/register/id_isar5.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdIsar5(pub u32);
+
 impl SysReg for IdIsar5 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdIsar5 {
     const CRM: u32 = 2;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for IdIsar5 {}
+
 impl IdIsar5 {
     #[inline]
     /// Reads ID_ISAR5 (*Instruction Set Attribute Register 5*)
diff --git a/aarch32-cpu/src/register/id_mmfr0.rs b/aarch32-cpu/src/register/id_mmfr0.rs
index 292a1d7..fd9d3c2 100644
--- a/aarch32-cpu/src/register/id_mmfr0.rs
+++ b/aarch32-cpu/src/register/id_mmfr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdMmfr0(pub u32);
+
 impl SysReg for IdMmfr0 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdMmfr0 {
     const CRM: u32 = 1;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for IdMmfr0 {}
+
 impl IdMmfr0 {
     #[inline]
     /// Reads ID_MMFR0 (*Memory Model Feature Register 0*)
diff --git a/aarch32-cpu/src/register/id_mmfr1.rs b/aarch32-cpu/src/register/id_mmfr1.rs
index a05eb80..6ebd0ec 100644
--- a/aarch32-cpu/src/register/id_mmfr1.rs
+++ b/aarch32-cpu/src/register/id_mmfr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdMmfr1(pub u32);
+
 impl SysReg for IdMmfr1 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdMmfr1 {
     const CRM: u32 = 1;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for IdMmfr1 {}
+
 impl IdMmfr1 {
     #[inline]
     /// Reads ID_MMFR1 (*Memory Model Feature Register 1*)
diff --git a/aarch32-cpu/src/register/id_mmfr2.rs b/aarch32-cpu/src/register/id_mmfr2.rs
index 77a015d..e71fb8b 100644
--- a/aarch32-cpu/src/register/id_mmfr2.rs
+++ b/aarch32-cpu/src/register/id_mmfr2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdMmfr2(pub u32);
+
 impl SysReg for IdMmfr2 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdMmfr2 {
     const CRM: u32 = 1;
     const OP2: u32 = 6;
 }
+
 impl crate::register::SysRegRead for IdMmfr2 {}
+
 impl IdMmfr2 {
     #[inline]
     /// Reads ID_MMFR2 (*Memory Model Feature Register 2*)
diff --git a/aarch32-cpu/src/register/id_mmfr3.rs b/aarch32-cpu/src/register/id_mmfr3.rs
index fed7e1a..4fe042a 100644
--- a/aarch32-cpu/src/register/id_mmfr3.rs
+++ b/aarch32-cpu/src/register/id_mmfr3.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdMmfr3(pub u32);
+
 impl SysReg for IdMmfr3 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdMmfr3 {
     const CRM: u32 = 1;
     const OP2: u32 = 7;
 }
+
 impl crate::register::SysRegRead for IdMmfr3 {}
+
 impl IdMmfr3 {
     #[inline]
     /// Reads ID_MMFR3 (*Memory Model Feature Register 3*)
diff --git a/aarch32-cpu/src/register/id_mmfr4.rs b/aarch32-cpu/src/register/id_mmfr4.rs
index dbc7ab4..a4d101f 100644
--- a/aarch32-cpu/src/register/id_mmfr4.rs
+++ b/aarch32-cpu/src/register/id_mmfr4.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdMmfr4(pub u32);
+
 impl SysReg for IdMmfr4 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdMmfr4 {
     const CRM: u32 = 2;
     const OP2: u32 = 6;
 }
+
 impl crate::register::SysRegRead for IdMmfr4 {}
+
 impl IdMmfr4 {
     #[inline]
     /// Reads ID_MMFR4 (*Memory Model Feature Register 4*)
diff --git a/aarch32-cpu/src/register/id_pfr0.rs b/aarch32-cpu/src/register/id_pfr0.rs
index 9898a5c..0643571 100644
--- a/aarch32-cpu/src/register/id_pfr0.rs
+++ b/aarch32-cpu/src/register/id_pfr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdPfr0(pub u32);
+
 impl SysReg for IdPfr0 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdPfr0 {
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for IdPfr0 {}
+
 impl IdPfr0 {
     #[inline]
     /// Reads ID_PFR0 (*Processor Feature Register 0*)
diff --git a/aarch32-cpu/src/register/id_pfr1.rs b/aarch32-cpu/src/register/id_pfr1.rs
index b5103b0..f3bea17 100644
--- a/aarch32-cpu/src/register/id_pfr1.rs
+++ b/aarch32-cpu/src/register/id_pfr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct IdPfr1(pub u32);
+
 impl SysReg for IdPfr1 {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for IdPfr1 {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for IdPfr1 {}
+
 impl IdPfr1 {
     #[inline]
     /// Reads ID_PFR1 (*Processor Feature Register 1*)
diff --git a/aarch32-cpu/src/register/ifar.rs b/aarch32-cpu/src/register/ifar.rs
index 4dd19be..b2cfa87 100644
--- a/aarch32-cpu/src/register/ifar.rs
+++ b/aarch32-cpu/src/register/ifar.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Ifar(pub u32);
+
 impl SysReg for Ifar {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -14,7 +15,9 @@ impl SysReg for Ifar {
     const CRM: u32 = 0;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Ifar {}
+
 impl Ifar {
     #[inline]
     /// Reads IFAR (*Instruction Fault Address Register*)
@@ -22,7 +25,9 @@ impl Ifar {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Ifar {}
+
 impl Ifar {
     #[inline]
     /// Writes IFAR (*Instruction Fault Address Register*)
diff --git a/aarch32-cpu/src/register/ifsr.rs b/aarch32-cpu/src/register/ifsr.rs
index b8fd384..e34ea18 100644
--- a/aarch32-cpu/src/register/ifsr.rs
+++ b/aarch32-cpu/src/register/ifsr.rs
@@ -58,7 +58,9 @@ impl SysReg for Ifsr {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Ifsr {}
+
 impl Ifsr {
     #[inline]
     /// Reads IFSR (*Instruction Fault Status Register*)
@@ -66,7 +68,9 @@ impl Ifsr {
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Ifsr {}
+
 impl Ifsr {
     #[inline]
     /// Writes IFSR (*Instruction Fault Status Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_atcmregionr.rs b/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
index dfaf7d7..d64b6bf 100644
--- a/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpAtcmregionr(pub u32);
+
 impl SysReg for ImpAtcmregionr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for ImpAtcmregionr {
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpAtcmregionr {}
+
 impl ImpAtcmregionr {
     #[inline]
     /// Reads IMP_ATCMREGIONR (*TCM Region Registers A B and C*)
@@ -22,7 +25,9 @@ impl ImpAtcmregionr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpAtcmregionr {}
+
 impl ImpAtcmregionr {
     #[inline]
     /// Writes IMP_ATCMREGIONR (*TCM Region Registers A B and C*)
diff --git a/aarch32-cpu/src/register/imp/imp_bpctlr.rs b/aarch32-cpu/src/register/imp/imp_bpctlr.rs
index 070626a..4f1a282 100644
--- a/aarch32-cpu/src/register/imp/imp_bpctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_bpctlr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpBpctlr(pub u32);
+
 impl SysReg for ImpBpctlr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for ImpBpctlr {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpBpctlr {}
+
 impl ImpBpctlr {
     #[inline]
     /// Reads IMP_BPCTLR (*Branch Predictor Control Register*)
@@ -22,7 +25,9 @@ impl ImpBpctlr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpBpctlr {}
+
 impl ImpBpctlr {
     #[inline]
     /// Writes IMP_BPCTLR (*Branch Predictor Control Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_btcmregionr.rs b/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
index 25063ca..60dccb0 100644
--- a/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpBtcmregionr(pub u32);
+
 impl SysReg for ImpBtcmregionr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for ImpBtcmregionr {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpBtcmregionr {}
+
 impl ImpBtcmregionr {
     #[inline]
     /// Reads IMP_BTCMREGIONR (*TCM Region Registers A B and C*)
@@ -22,7 +25,9 @@ impl ImpBtcmregionr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpBtcmregionr {}
+
 impl ImpBtcmregionr {
     #[inline]
     /// Writes IMP_BTCMREGIONR (*TCM Region Registers A B and C*)
diff --git a/aarch32-cpu/src/register/imp/imp_buildoptr.rs b/aarch32-cpu/src/register/imp/imp_buildoptr.rs
index 65d0b13..6b173d7 100644
--- a/aarch32-cpu/src/register/imp/imp_buildoptr.rs
+++ b/aarch32-cpu/src/register/imp/imp_buildoptr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpBuildoptr(pub u32);
+
 impl SysReg for ImpBuildoptr {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpBuildoptr {
     const CRM: u32 = 2;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpBuildoptr {}
+
 impl ImpBuildoptr {
     #[inline]
     /// Reads IMP_BUILDOPTR (*Build Options Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs b/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
index 5e6b2ce..2fe9b22 100644
--- a/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
+++ b/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpBustimeoutr(pub u32);
+
 impl SysReg for ImpBustimeoutr {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpBustimeoutr {
     const CRM: u32 = 3;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for ImpBustimeoutr {}
+
 impl ImpBustimeoutr {
     #[inline]
     /// Reads IMP_BUSTIMEOUTR (*Bus Timeout Register*)
@@ -22,7 +25,9 @@ impl ImpBustimeoutr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpBustimeoutr {}
+
 impl ImpBustimeoutr {
     #[inline]
     /// Writes IMP_BUSTIMEOUTR (*Bus Timeout Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs b/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
index 14847ab..9abc129 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCdbgdcd(pub u32);
+
 impl SysReg for ImpCdbgdcd {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpCdbgdcd {
     const CRM: u32 = 4;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegWrite for ImpCdbgdcd {}
+
 impl ImpCdbgdcd {
     #[inline]
     /// Writes IMP_CDBGDCD (*Data Cache Data Read Operation.*)
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdci.rs b/aarch32-cpu/src/register/imp/imp_cdbgdci.rs
index 998ff88..e1dfb71 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdci.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdci.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCdbgdci(pub u32);
+
 impl SysReg for ImpCdbgdci {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpCdbgdci {
     const CRM: u32 = 14;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegWrite for ImpCdbgdci {}
+
 impl ImpCdbgdci {
     #[inline]
     /// Writes IMP_CDBGDCI (*Invalidate All Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdct.rs b/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
index d3451a2..00194b3 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCdbgdct(pub u32);
+
 impl SysReg for ImpCdbgdct {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpCdbgdct {
     const CRM: u32 = 2;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegWrite for ImpCdbgdct {}
+
 impl ImpCdbgdct {
     #[inline]
     /// Writes IMP_CDBGDCT (*Data Cache Tag Read Operation.*)
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
index 142a514..1d3e87b 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCdbgdr0(pub u32);
+
 impl SysReg for ImpCdbgdr0 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpCdbgdr0 {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpCdbgdr0 {}
+
 impl ImpCdbgdr0 {
     #[inline]
     /// Reads IMP_CDBGDR0 (*Cache Debug Data Register 0.*)
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
index e4864e7..128919d 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCdbgdr1(pub u32);
+
 impl SysReg for ImpCdbgdr1 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpCdbgdr1 {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpCdbgdr1 {}
+
 impl ImpCdbgdr1 {
     #[inline]
     /// Reads IMP_CDBGDR1 (*Cache Debug Data Register 1.*)
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
index 67046ce..4fc3e10 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCdbgdr2(pub u32);
+
 impl SysReg for ImpCdbgdr2 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpCdbgdr2 {
     const CRM: u32 = 0;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for ImpCdbgdr2 {}
+
 impl ImpCdbgdr2 {
     #[inline]
     /// Reads IMP_CDBGDR2 (*Cache Debug Data Register 2.*)
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgicd.rs b/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
index 1d0e2a6..9847be2 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCdbgicd(pub u32);
+
 impl SysReg for ImpCdbgicd {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpCdbgicd {
     const CRM: u32 = 4;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegWrite for ImpCdbgicd {}
+
 impl ImpCdbgicd {
     #[inline]
     /// Writes IMP_CDBGICD (*Instruction Cache Data Read Operation.*)
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgict.rs b/aarch32-cpu/src/register/imp/imp_cdbgict.rs
index f0a2220..cab5cec 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgict.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgict.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCdbgict(pub u32);
+
 impl SysReg for ImpCdbgict {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpCdbgict {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegWrite for ImpCdbgict {}
+
 impl ImpCdbgict {
     #[inline]
     /// Writes IMP_CDBGICT (*Instruction Cache Tag Read Operation.*)
diff --git a/aarch32-cpu/src/register/imp/imp_csctlr.rs b/aarch32-cpu/src/register/imp/imp_csctlr.rs
index 792d28f..aa0d8d9 100644
--- a/aarch32-cpu/src/register/imp/imp_csctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_csctlr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCsctlr(pub u32);
+
 impl SysReg for ImpCsctlr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for ImpCsctlr {
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpCsctlr {}
+
 impl ImpCsctlr {
     #[inline]
     /// Reads IMP_CSCTLR (*Cache Segregation Control Register*)
@@ -22,7 +25,9 @@ impl ImpCsctlr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpCsctlr {}
+
 impl ImpCsctlr {
     #[inline]
     /// Writes IMP_CSCTLR (*Cache Segregation Control Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs b/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
index 09c4064..6674163 100644
--- a/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpCtcmregionr(pub u32);
+
 impl SysReg for ImpCtcmregionr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for ImpCtcmregionr {
     const CRM: u32 = 1;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for ImpCtcmregionr {}
+
 impl ImpCtcmregionr {
     #[inline]
     /// Reads IMP_CTCMREGIONR (*TCM Region Registers A B and C*)
@@ -22,7 +25,9 @@ impl ImpCtcmregionr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpCtcmregionr {}
+
 impl ImpCtcmregionr {
     #[inline]
     /// Writes IMP_CTCMREGIONR (*TCM Region Registers A B and C*)
diff --git a/aarch32-cpu/src/register/imp/imp_dcerr0.rs b/aarch32-cpu/src/register/imp/imp_dcerr0.rs
index 01ccb69..1ef40da 100644
--- a/aarch32-cpu/src/register/imp/imp_dcerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_dcerr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpDcerr0(pub u32);
+
 impl SysReg for ImpDcerr0 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpDcerr0 {
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpDcerr0 {}
+
 impl ImpDcerr0 {
     #[inline]
     /// Reads IMP_DCERR0 (*Data Cache Error Record Register 0*)
@@ -22,7 +25,9 @@ impl ImpDcerr0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpDcerr0 {}
+
 impl ImpDcerr0 {
     #[inline]
     /// Writes IMP_DCERR0 (*Data Cache Error Record Register 0*)
diff --git a/aarch32-cpu/src/register/imp/imp_dcerr1.rs b/aarch32-cpu/src/register/imp/imp_dcerr1.rs
index 1eb657c..07b9e5c 100644
--- a/aarch32-cpu/src/register/imp/imp_dcerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_dcerr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpDcerr1(pub u32);
+
 impl SysReg for ImpDcerr1 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpDcerr1 {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpDcerr1 {}
+
 impl ImpDcerr1 {
     #[inline]
     /// Reads DMP_ICERR1 (*Data Cache Error Record Register 1*)
@@ -22,7 +25,9 @@ impl ImpDcerr1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpDcerr1 {}
+
 impl ImpDcerr1 {
     #[inline]
     /// Writes DMP_ICERR1 (*Data Cache Error Record Register 1*)
diff --git a/aarch32-cpu/src/register/imp/imp_flasherr0.rs b/aarch32-cpu/src/register/imp/imp_flasherr0.rs
index 560cf81..ebdea8d 100644
--- a/aarch32-cpu/src/register/imp/imp_flasherr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_flasherr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpFlasherr0(pub u32);
+
 impl SysReg for ImpFlasherr0 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpFlasherr0 {
     const CRM: u32 = 3;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpFlasherr0 {}
+
 impl ImpFlasherr0 {
     #[inline]
     /// Reads IMP_FLASHERR0 (*Flash Error Record Register 0*)
@@ -22,7 +25,9 @@ impl ImpFlasherr0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpFlasherr0 {}
+
 impl ImpFlasherr0 {
     #[inline]
     /// Writes IMP_FLASHERR0 (*Flash Error Record Register 0*)
diff --git a/aarch32-cpu/src/register/imp/imp_flasherr1.rs b/aarch32-cpu/src/register/imp/imp_flasherr1.rs
index e9b7265..1fe8378 100644
--- a/aarch32-cpu/src/register/imp/imp_flasherr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_flasherr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpFlasherr1(pub u32);
+
 impl SysReg for ImpFlasherr1 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpFlasherr1 {
     const CRM: u32 = 3;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpFlasherr1 {}
+
 impl ImpFlasherr1 {
     #[inline]
     /// Reads IMP_FLASHERR1 (*Flash Error Record Register 1*)
@@ -22,7 +25,9 @@ impl ImpFlasherr1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpFlasherr1 {}
+
 impl ImpFlasherr1 {
     #[inline]
     /// Writes IMP_FLASHERR1 (*Flash Error Record Register 1*)
diff --git a/aarch32-cpu/src/register/imp/imp_flashifregionr.rs b/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
index 39c8606..8b9290e 100644
--- a/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpFlashifregionr(pub u32);
+
 impl SysReg for ImpFlashifregionr {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpFlashifregionr {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpFlashifregionr {}
+
 impl ImpFlashifregionr {
     #[inline]
     /// Reads IMP_FLASHIFREGIONR (*Flash Interface Region Register*)
@@ -22,7 +25,9 @@ impl ImpFlashifregionr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpFlashifregionr {}
+
 impl ImpFlashifregionr {
     #[inline]
     /// Writes IMP_FLASHIFREGIONR (*Flash Interface Region Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_icerr0.rs b/aarch32-cpu/src/register/imp/imp_icerr0.rs
index 6ddc426..cdfb24f 100644
--- a/aarch32-cpu/src/register/imp/imp_icerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_icerr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpIcerr0(pub u32);
+
 impl SysReg for ImpIcerr0 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpIcerr0 {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpIcerr0 {}
+
 impl ImpIcerr0 {
     #[inline]
     /// Reads IMP_ICERR0 (*Instruction Cache Error Record Register 0*)
@@ -22,7 +25,9 @@ impl ImpIcerr0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpIcerr0 {}
+
 impl ImpIcerr0 {
     #[inline]
     /// Writes IMP_ICERR0 (*Instruction Cache Error Record Register 0*)
diff --git a/aarch32-cpu/src/register/imp/imp_icerr1.rs b/aarch32-cpu/src/register/imp/imp_icerr1.rs
index 60dca05..12da076 100644
--- a/aarch32-cpu/src/register/imp/imp_icerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_icerr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpIcerr1(pub u32);
+
 impl SysReg for ImpIcerr1 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpIcerr1 {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpIcerr1 {}
+
 impl ImpIcerr1 {
     #[inline]
     /// Reads IMP_ICERR1 (*Instruction Cache Error Record Register 1*)
@@ -22,7 +25,9 @@ impl ImpIcerr1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpIcerr1 {}
+
 impl ImpIcerr1 {
     #[inline]
     /// Writes IMP_ICERR1 (*Instruction Cache Error Record Register 1*)
diff --git a/aarch32-cpu/src/register/imp/imp_intmonr.rs b/aarch32-cpu/src/register/imp/imp_intmonr.rs
index 5f69c55..86315ab 100644
--- a/aarch32-cpu/src/register/imp/imp_intmonr.rs
+++ b/aarch32-cpu/src/register/imp/imp_intmonr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpIntmonr(pub u32);
+
 impl SysReg for ImpIntmonr {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpIntmonr {
     const CRM: u32 = 3;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for ImpIntmonr {}
+
 impl ImpIntmonr {
     #[inline]
     /// Reads IMP_INTMONR (*Interrupt Monitoring Register*)
@@ -22,7 +25,9 @@ impl ImpIntmonr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpIntmonr {}
+
 impl ImpIntmonr {
     #[inline]
     /// Writes IMP_INTMONR (*Interrupt Monitoring Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_memprotctlr.rs b/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
index 827b9da..1496024 100644
--- a/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpMemprotctlr(pub u32);
+
 impl SysReg for ImpMemprotctlr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for ImpMemprotctlr {
     const CRM: u32 = 1;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for ImpMemprotctlr {}
+
 impl ImpMemprotctlr {
     #[inline]
     /// Reads IMP_MEMPROTCTLR (*Memory Protection Control Register*)
@@ -22,7 +25,9 @@ impl ImpMemprotctlr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpMemprotctlr {}
+
 impl ImpMemprotctlr {
     #[inline]
     /// Writes IMP_MEMPROTCTLR (*Memory Protection Control Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_periphpregionr.rs b/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
index 06c20b3..5164375 100644
--- a/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpPeriphpregionr(pub u32);
+
 impl SysReg for ImpPeriphpregionr {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpPeriphpregionr {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpPeriphpregionr {}
+
 impl ImpPeriphpregionr {
     #[inline]
     /// Reads IMP_PERIPHPREGIONR (*Peripheral Port Region Register*)
@@ -22,7 +25,9 @@ impl ImpPeriphpregionr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpPeriphpregionr {}
+
 impl ImpPeriphpregionr {
     #[inline]
     /// Writes IMP_PERIPHPREGIONR (*Peripheral Port Region Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_pinoptr.rs b/aarch32-cpu/src/register/imp/imp_pinoptr.rs
index 7801f88..e2b7b6a 100644
--- a/aarch32-cpu/src/register/imp/imp_pinoptr.rs
+++ b/aarch32-cpu/src/register/imp/imp_pinoptr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpPinoptr(pub u32);
+
 impl SysReg for ImpPinoptr {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpPinoptr {
     const CRM: u32 = 2;
     const OP2: u32 = 7;
 }
+
 impl crate::register::SysRegRead for ImpPinoptr {}
+
 impl ImpPinoptr {
     #[inline]
     /// Reads IMP_PINOPTR (*Pin Options Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_qosr.rs b/aarch32-cpu/src/register/imp/imp_qosr.rs
index 2d55a5d..d8e74e7 100644
--- a/aarch32-cpu/src/register/imp/imp_qosr.rs
+++ b/aarch32-cpu/src/register/imp/imp_qosr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpQosr(pub u32);
+
 impl SysReg for ImpQosr {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpQosr {
     const CRM: u32 = 3;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpQosr {}
+
 impl ImpQosr {
     #[inline]
     /// Reads IMP_QOSR (*Quality Of Service Register*)
@@ -22,7 +25,9 @@ impl ImpQosr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpQosr {}
+
 impl ImpQosr {
     #[inline]
     /// Writes IMP_QOSR (*Quality Of Service Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_slavepctlr.rs b/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
index be815a7..f259a0d 100644
--- a/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpSlavepctlr(pub u32);
+
 impl SysReg for ImpSlavepctlr {
     const CP: u32 = 15;
     const CRN: u32 = 11;
@@ -14,7 +15,9 @@ impl SysReg for ImpSlavepctlr {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpSlavepctlr {}
+
 impl ImpSlavepctlr {
     #[inline]
     /// Reads IMP_SLAVEPCTLR (*Slave Port Control Register*)
@@ -22,7 +25,9 @@ impl ImpSlavepctlr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpSlavepctlr {}
+
 impl ImpSlavepctlr {
     #[inline]
     /// Writes IMP_SLAVEPCTLR (*Slave Port Control Register*)
diff --git a/aarch32-cpu/src/register/imp/imp_tcmerr0.rs b/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
index e299acf..b98ccad 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpTcmerr0(pub u32);
+
 impl SysReg for ImpTcmerr0 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpTcmerr0 {
     const CRM: u32 = 2;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpTcmerr0 {}
+
 impl ImpTcmerr0 {
     #[inline]
     /// Reads IMP_TCMERR0 (*TCM Error Record Register 0*)
@@ -22,7 +25,9 @@ impl ImpTcmerr0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpTcmerr0 {}
+
 impl ImpTcmerr0 {
     #[inline]
     /// Writes IMP_TCMERR0 (*TCM Error Record Register 0*)
diff --git a/aarch32-cpu/src/register/imp/imp_tcmerr1.rs b/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
index 9487100..99fea8e 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpTcmerr1(pub u32);
+
 impl SysReg for ImpTcmerr1 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpTcmerr1 {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for ImpTcmerr1 {}
+
 impl ImpTcmerr1 {
     #[inline]
     /// Reads IMP_TCMERR1 (*TCM Error Record Register 1*)
@@ -22,7 +25,9 @@ impl ImpTcmerr1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for ImpTcmerr1 {}
+
 impl ImpTcmerr1 {
     #[inline]
     /// Writes IMP_TCMERR1 (*TCM Error Record Register 1*)
diff --git a/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs b/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
index 6f72b8c..38be291 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpTcmsyndr0(pub u32);
+
 impl SysReg for ImpTcmsyndr0 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpTcmsyndr0 {
     const CRM: u32 = 2;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for ImpTcmsyndr0 {}
+
 impl ImpTcmsyndr0 {
     #[inline]
     /// Reads IMP_TCMSYNDR0 (*TCM Syndrome Register 0*)
diff --git a/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs b/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
index 7508792..e9ba590 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpTcmsyndr1(pub u32);
+
 impl SysReg for ImpTcmsyndr1 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpTcmsyndr1 {
     const CRM: u32 = 2;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for ImpTcmsyndr1 {}
+
 impl ImpTcmsyndr1 {
     #[inline]
     /// Reads IMP_TCMSYNDR1 (*TCM Syndrome Register 1*)
diff --git a/aarch32-cpu/src/register/imp/imp_testr0.rs b/aarch32-cpu/src/register/imp/imp_testr0.rs
index 1c90dcc..1948ad1 100644
--- a/aarch32-cpu/src/register/imp/imp_testr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_testr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct ImpTestr0(pub u32);
+
 impl SysReg for ImpTestr0 {
     const CP: u32 = 15;
     const CRN: u32 = 15;
@@ -14,7 +15,9 @@ impl SysReg for ImpTestr0 {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for ImpTestr0 {}
+
 impl ImpTestr0 {
     #[inline]
     /// Reads IMP_TESTR0 (*Test Register 0*)
diff --git a/aarch32-cpu/src/register/iracr.rs b/aarch32-cpu/src/register/iracr.rs
index 42afc96..ae640f0 100644
--- a/aarch32-cpu/src/register/iracr.rs
+++ b/aarch32-cpu/src/register/iracr.rs
@@ -35,7 +35,9 @@ impl SysReg for Iracr {
     const CRM: u32 = 1;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Iracr {}
+
 impl Iracr {
     #[inline]
     /// Reads IRACR (*Instruction Region Access Control Register*)
@@ -47,6 +49,7 @@ impl Iracr {
 }
 
 impl crate::register::SysRegWrite for Iracr {}
+
 impl Iracr {
     #[inline]
     /// Writes IRACR (*Instruction Region Access Control Register*)
diff --git a/aarch32-cpu/src/register/irbar.rs b/aarch32-cpu/src/register/irbar.rs
index 0754cd2..db70420 100644
--- a/aarch32-cpu/src/register/irbar.rs
+++ b/aarch32-cpu/src/register/irbar.rs
@@ -3,9 +3,12 @@
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
 /// IRBAR (*Instruction Region Base Address Register*)
-#[derive(Debug, Copy, Clone)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(transparent)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct Irbar(pub *mut u8);
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+pub struct Irbar(pub u32);
+
 impl SysReg for Irbar {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -13,24 +16,27 @@ impl SysReg for Irbar {
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Irbar {}
+
 impl Irbar {
     #[inline]
     /// Reads IRBAR (*Instruction Region Base Address Register*)
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Irbar {
-        unsafe { Self(<Self as SysRegRead>::read_raw() as *mut u8) }
+        unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
 
 impl crate::register::SysRegWrite for Irbar {}
+
 impl Irbar {
     #[inline]
     /// Writes IRBAR (*Instruction Region Base Address Register*)
     ///
     /// Set RGNR to control which region this affects.
     pub fn write(value: Irbar) {
-        unsafe { <Self as SysRegWrite>::write_raw(value.0 as u32) }
+        unsafe { <Self as SysRegWrite>::write_raw(value.0) }
     }
 }
diff --git a/aarch32-cpu/src/register/mair0.rs b/aarch32-cpu/src/register/mair0.rs
index 75bc30c..60713a8 100644
--- a/aarch32-cpu/src/register/mair0.rs
+++ b/aarch32-cpu/src/register/mair0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Mair0(pub u32);
+
 impl SysReg for Mair0 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
@@ -14,7 +15,9 @@ impl SysReg for Mair0 {
     const CRM: u32 = 2;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Mair0 {}
+
 impl Mair0 {
     #[inline]
     /// Reads MAIR0 (*Memory Attribute Indirection Register 0*)
@@ -22,7 +25,9 @@ impl Mair0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Mair0 {}
+
 impl Mair0 {
     #[inline]
     /// Writes MAIR0 (*Memory Attribute Indirection Register 0*)
diff --git a/aarch32-cpu/src/register/mair1.rs b/aarch32-cpu/src/register/mair1.rs
index fc2158f..6e90d31 100644
--- a/aarch32-cpu/src/register/mair1.rs
+++ b/aarch32-cpu/src/register/mair1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Mair1(pub u32);
+
 impl SysReg for Mair1 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
@@ -14,7 +15,9 @@ impl SysReg for Mair1 {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Mair1 {}
+
 impl Mair1 {
     #[inline]
     /// Reads MAIR1 (*Memory Attribute Indirection Register 1*)
@@ -22,7 +25,9 @@ impl Mair1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Mair1 {}
+
 impl Mair1 {
     #[inline]
     /// Writes MAIR1 (*Memory Attribute Indirection Register 1*)
diff --git a/aarch32-cpu/src/register/mpidr.rs b/aarch32-cpu/src/register/mpidr.rs
index bf3b87c..2495b24 100644
--- a/aarch32-cpu/src/register/mpidr.rs
+++ b/aarch32-cpu/src/register/mpidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Mpidr(pub u32);
+
 impl SysReg for Mpidr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Mpidr {
     const CRM: u32 = 0;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Mpidr {}
+
 impl Mpidr {
     #[inline]
     /// Reads MPIDR (*Multiprocessor Affinity Register*)
diff --git a/aarch32-cpu/src/register/mpuir.rs b/aarch32-cpu/src/register/mpuir.rs
index 8b64826..f28df79 100644
--- a/aarch32-cpu/src/register/mpuir.rs
+++ b/aarch32-cpu/src/register/mpuir.rs
@@ -26,7 +26,9 @@ impl SysReg for Mpuir {
     const CRM: u32 = 0;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Mpuir {}
+
 impl Mpuir {
     #[inline]
     /// Reads MPUIR (*MPU Type Register*)
diff --git a/aarch32-cpu/src/register/nsacr.rs b/aarch32-cpu/src/register/nsacr.rs
index b35e939..d980657 100644
--- a/aarch32-cpu/src/register/nsacr.rs
+++ b/aarch32-cpu/src/register/nsacr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Nsacr(pub u32);
+
 impl SysReg for Nsacr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
@@ -14,7 +15,9 @@ impl SysReg for Nsacr {
     const CRM: u32 = 1;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Nsacr {}
+
 impl Nsacr {
     #[inline]
     /// Reads NSACR (*Non-Secure Access Control Register*)
diff --git a/aarch32-cpu/src/register/par.rs b/aarch32-cpu/src/register/par.rs
index 241021d..ac29f58 100644
--- a/aarch32-cpu/src/register/par.rs
+++ b/aarch32-cpu/src/register/par.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Par(pub u32);
+
 impl SysReg for Par {
     const CP: u32 = 15;
     const CRN: u32 = 7;
@@ -14,7 +15,9 @@ impl SysReg for Par {
     const CRM: u32 = 4;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Par {}
+
 impl Par {
     #[inline]
     /// Reads PAR (*Physical Address Register*)
@@ -22,7 +25,9 @@ impl Par {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Par {}
+
 impl Par {
     #[inline]
     /// Writes PAR (*Physical Address Register*)
diff --git a/aarch32-cpu/src/register/pmccfiltr.rs b/aarch32-cpu/src/register/pmccfiltr.rs
index 2a83e48..2dcd5ba 100644
--- a/aarch32-cpu/src/register/pmccfiltr.rs
+++ b/aarch32-cpu/src/register/pmccfiltr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmccfiltr(pub u32);
+
 impl SysReg for Pmccfiltr {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmccfiltr {
     const CRM: u32 = 15;
     const OP2: u32 = 7;
 }
+
 impl crate::register::SysRegRead for Pmccfiltr {}
+
 impl Pmccfiltr {
     #[inline]
     /// Reads PMCCFILTR (*Performance Monitors Cycle Count Filter Register*)
@@ -22,7 +25,9 @@ impl Pmccfiltr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmccfiltr {}
+
 impl Pmccfiltr {
     #[inline]
     /// Writes PMCCFILTR (*Performance Monitors Cycle Count Filter Register*)
diff --git a/aarch32-cpu/src/register/pmccntr.rs b/aarch32-cpu/src/register/pmccntr.rs
index 3a3c9ca..63ab0dc 100644
--- a/aarch32-cpu/src/register/pmccntr.rs
+++ b/aarch32-cpu/src/register/pmccntr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmccntr(pub u32);
+
 impl SysReg for Pmccntr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmccntr {
     const CRM: u32 = 13;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Pmccntr {}
+
 impl Pmccntr {
     #[inline]
     /// Reads PMCCNTR (*Performance Monitors Cycle Count Register*)
@@ -22,7 +25,9 @@ impl Pmccntr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmccntr {}
+
 impl Pmccntr {
     #[inline]
     /// Writes PMCCNTR (*Performance Monitors Cycle Count Register*)
diff --git a/aarch32-cpu/src/register/pmceid0.rs b/aarch32-cpu/src/register/pmceid0.rs
index 1e37a40..dd87cd7 100644
--- a/aarch32-cpu/src/register/pmceid0.rs
+++ b/aarch32-cpu/src/register/pmceid0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmceid0(pub u32);
+
 impl SysReg for Pmceid0 {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmceid0 {
     const CRM: u32 = 12;
     const OP2: u32 = 6;
 }
+
 impl crate::register::SysRegRead for Pmceid0 {}
+
 impl Pmceid0 {
     #[inline]
     /// Reads PMCEID0 (*Performance Monitors Common Event Identification Register 0*)
diff --git a/aarch32-cpu/src/register/pmceid1.rs b/aarch32-cpu/src/register/pmceid1.rs
index 4b329d7..2d25097 100644
--- a/aarch32-cpu/src/register/pmceid1.rs
+++ b/aarch32-cpu/src/register/pmceid1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmceid1(pub u32);
+
 impl SysReg for Pmceid1 {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmceid1 {
     const CRM: u32 = 12;
     const OP2: u32 = 7;
 }
+
 impl crate::register::SysRegRead for Pmceid1 {}
+
 impl Pmceid1 {
     #[inline]
     /// Reads PMCEID1 (*Performance Monitors Common Event Identification Register 1*)
diff --git a/aarch32-cpu/src/register/pmcntenclr.rs b/aarch32-cpu/src/register/pmcntenclr.rs
index fdc826a..3eceb9d 100644
--- a/aarch32-cpu/src/register/pmcntenclr.rs
+++ b/aarch32-cpu/src/register/pmcntenclr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmcntenclr(pub u32);
+
 impl SysReg for Pmcntenclr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmcntenclr {
     const CRM: u32 = 12;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Pmcntenclr {}
+
 impl Pmcntenclr {
     #[inline]
     /// Reads PMCNTENCLR (*Performance Monitors Count Enable Clear Register*)
@@ -22,7 +25,9 @@ impl Pmcntenclr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmcntenclr {}
+
 impl Pmcntenclr {
     #[inline]
     /// Writes PMCNTENCLR (*Performance Monitors Count Enable Clear Register*)
diff --git a/aarch32-cpu/src/register/pmcntenset.rs b/aarch32-cpu/src/register/pmcntenset.rs
index e5f5607..dfc07bf 100644
--- a/aarch32-cpu/src/register/pmcntenset.rs
+++ b/aarch32-cpu/src/register/pmcntenset.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmcntenset(pub u32);
+
 impl SysReg for Pmcntenset {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmcntenset {
     const CRM: u32 = 12;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Pmcntenset {}
+
 impl Pmcntenset {
     #[inline]
     /// Reads PMCNTENSET (*Performance Monitors Count Enable Set Register*)
@@ -22,7 +25,9 @@ impl Pmcntenset {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmcntenset {}
+
 impl Pmcntenset {
     #[inline]
     /// Writes PMCNTENSET (*Performance Monitors Count Enable Set Register*)
diff --git a/aarch32-cpu/src/register/pmcr.rs b/aarch32-cpu/src/register/pmcr.rs
index ebc20eb..df22c6c 100644
--- a/aarch32-cpu/src/register/pmcr.rs
+++ b/aarch32-cpu/src/register/pmcr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmcr(pub u32);
+
 impl SysReg for Pmcr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmcr {
     const CRM: u32 = 12;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Pmcr {}
+
 impl Pmcr {
     #[inline]
     /// Reads PMCR (*Performance Monitors Control Register*)
@@ -22,7 +25,9 @@ impl Pmcr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmcr {}
+
 impl Pmcr {
     #[inline]
     /// Writes PMCR (*Performance Monitors Control Register*)
diff --git a/aarch32-cpu/src/register/pmevcntr0.rs b/aarch32-cpu/src/register/pmevcntr0.rs
index 74e6dcd..cbdf038 100644
--- a/aarch32-cpu/src/register/pmevcntr0.rs
+++ b/aarch32-cpu/src/register/pmevcntr0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmevcntr0(pub u32);
+
 impl SysReg for Pmevcntr0 {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmevcntr0 {
     const CRM: u32 = 8;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Pmevcntr0 {}
+
 impl Pmevcntr0 {
     #[inline]
     /// Reads PMEVCNTR0 (*Performance Monitors Event Count Register 0*)
@@ -22,7 +25,9 @@ impl Pmevcntr0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmevcntr0 {}
+
 impl Pmevcntr0 {
     #[inline]
     /// Writes PMEVCNTR0 (*Performance Monitors Event Count Register 0*)
diff --git a/aarch32-cpu/src/register/pmevcntr1.rs b/aarch32-cpu/src/register/pmevcntr1.rs
index 6104164..4f0b0cb 100644
--- a/aarch32-cpu/src/register/pmevcntr1.rs
+++ b/aarch32-cpu/src/register/pmevcntr1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmevcntr1(pub u32);
+
 impl SysReg for Pmevcntr1 {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmevcntr1 {
     const CRM: u32 = 8;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Pmevcntr1 {}
+
 impl Pmevcntr1 {
     #[inline]
     /// Reads PMEVCNTR1 (*Performance Monitors Event Count Register 1*)
@@ -22,7 +25,9 @@ impl Pmevcntr1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmevcntr1 {}
+
 impl Pmevcntr1 {
     #[inline]
     /// Writes PMEVCNTR1 (*Performance Monitors Event Count Register 1*)
diff --git a/aarch32-cpu/src/register/pmevcntr2.rs b/aarch32-cpu/src/register/pmevcntr2.rs
index 1493371..d2c9bc9 100644
--- a/aarch32-cpu/src/register/pmevcntr2.rs
+++ b/aarch32-cpu/src/register/pmevcntr2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmevcntr2(pub u32);
+
 impl SysReg for Pmevcntr2 {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmevcntr2 {
     const CRM: u32 = 8;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Pmevcntr2 {}
+
 impl Pmevcntr2 {
     #[inline]
     /// Reads PMEVCNTR2 (*Performance Monitors Event Count Register 2 *)
@@ -22,7 +25,9 @@ impl Pmevcntr2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmevcntr2 {}
+
 impl Pmevcntr2 {
     #[inline]
     /// Writes PMEVCNTR2 (*Performance Monitors Event Count Register 2 *)
diff --git a/aarch32-cpu/src/register/pmevcntr3.rs b/aarch32-cpu/src/register/pmevcntr3.rs
index e409255..4ce3865 100644
--- a/aarch32-cpu/src/register/pmevcntr3.rs
+++ b/aarch32-cpu/src/register/pmevcntr3.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmevcntr3(pub u32);
+
 impl SysReg for Pmevcntr3 {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmevcntr3 {
     const CRM: u32 = 8;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Pmevcntr3 {}
+
 impl Pmevcntr3 {
     #[inline]
     /// Reads PMEVCNTR3 (*Performance Monitors Event Count Register 3*)
@@ -22,7 +25,9 @@ impl Pmevcntr3 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmevcntr3 {}
+
 impl Pmevcntr3 {
     #[inline]
     /// Writes PMEVCNTR3 (*Performance Monitors Event Count Register 3*)
diff --git a/aarch32-cpu/src/register/pmevtyper0.rs b/aarch32-cpu/src/register/pmevtyper0.rs
index 7a0ee1b..aad9168 100644
--- a/aarch32-cpu/src/register/pmevtyper0.rs
+++ b/aarch32-cpu/src/register/pmevtyper0.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmevtyper0(pub u32);
+
 impl SysReg for Pmevtyper0 {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmevtyper0 {
     const CRM: u32 = 12;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Pmevtyper0 {}
+
 impl Pmevtyper0 {
     #[inline]
     /// Reads PMEVTYPER0 (*Performance Monitors Event Type Register 0*)
@@ -22,7 +25,9 @@ impl Pmevtyper0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmevtyper0 {}
+
 impl Pmevtyper0 {
     #[inline]
     /// Writes PMEVTYPER0 (*Performance Monitors Event Type Register 0*)
diff --git a/aarch32-cpu/src/register/pmevtyper1.rs b/aarch32-cpu/src/register/pmevtyper1.rs
index 67e59a1..3bf5822 100644
--- a/aarch32-cpu/src/register/pmevtyper1.rs
+++ b/aarch32-cpu/src/register/pmevtyper1.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmevtyper1(pub u32);
+
 impl SysReg for Pmevtyper1 {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmevtyper1 {
     const CRM: u32 = 12;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Pmevtyper1 {}
+
 impl Pmevtyper1 {
     #[inline]
     /// Reads PMEVTYPER1 (*Performance Monitors Event Type Register 1*)
@@ -22,7 +25,9 @@ impl Pmevtyper1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmevtyper1 {}
+
 impl Pmevtyper1 {
     #[inline]
     /// Writes PMEVTYPER1 (*Performance Monitors Event Type Register 1*)
diff --git a/aarch32-cpu/src/register/pmevtyper2.rs b/aarch32-cpu/src/register/pmevtyper2.rs
index 70574b5..8207fe3 100644
--- a/aarch32-cpu/src/register/pmevtyper2.rs
+++ b/aarch32-cpu/src/register/pmevtyper2.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmevtyper2(pub u32);
+
 impl SysReg for Pmevtyper2 {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmevtyper2 {
     const CRM: u32 = 12;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Pmevtyper2 {}
+
 impl Pmevtyper2 {
     #[inline]
     /// Reads PMEVTYPER2 (*Performance Monitors Event Type Register 2*)
@@ -22,7 +25,9 @@ impl Pmevtyper2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmevtyper2 {}
+
 impl Pmevtyper2 {
     #[inline]
     /// Writes PMEVTYPER2 (*Performance Monitors Event Type Register 2*)
diff --git a/aarch32-cpu/src/register/pmevtyper3.rs b/aarch32-cpu/src/register/pmevtyper3.rs
index 0d325fa..b5d4bc6 100644
--- a/aarch32-cpu/src/register/pmevtyper3.rs
+++ b/aarch32-cpu/src/register/pmevtyper3.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmevtyper3(pub u32);
+
 impl SysReg for Pmevtyper3 {
     const CP: u32 = 15;
     const CRN: u32 = 14;
@@ -14,7 +15,9 @@ impl SysReg for Pmevtyper3 {
     const CRM: u32 = 12;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Pmevtyper3 {}
+
 impl Pmevtyper3 {
     #[inline]
     /// Reads PMEVTYPER3 (*Performance Monitors Event Type Register 3*)
@@ -22,7 +25,9 @@ impl Pmevtyper3 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmevtyper3 {}
+
 impl Pmevtyper3 {
     #[inline]
     /// Writes PMEVTYPER3 (*Performance Monitors Event Type Register 3*)
diff --git a/aarch32-cpu/src/register/pmintenclr.rs b/aarch32-cpu/src/register/pmintenclr.rs
index ec87ea5..f82eac0 100644
--- a/aarch32-cpu/src/register/pmintenclr.rs
+++ b/aarch32-cpu/src/register/pmintenclr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmintenclr(pub u32);
+
 impl SysReg for Pmintenclr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmintenclr {
     const CRM: u32 = 14;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Pmintenclr {}
+
 impl Pmintenclr {
     #[inline]
     /// Reads PMINTENCLR (*Performance Monitors Interrupt Enable Clear Register*)
@@ -22,7 +25,9 @@ impl Pmintenclr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmintenclr {}
+
 impl Pmintenclr {
     #[inline]
     /// Writes PMINTENCLR (*Performance Monitors Interrupt Enable Clear Register*)
diff --git a/aarch32-cpu/src/register/pmintenset.rs b/aarch32-cpu/src/register/pmintenset.rs
index a1d6cbb..fbf3588 100644
--- a/aarch32-cpu/src/register/pmintenset.rs
+++ b/aarch32-cpu/src/register/pmintenset.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmintenset(pub u32);
+
 impl SysReg for Pmintenset {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmintenset {
     const CRM: u32 = 14;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Pmintenset {}
+
 impl Pmintenset {
     #[inline]
     /// Reads PMINTENSET (*Performance Monitors Interrupt Enable Set Register*)
@@ -22,7 +25,9 @@ impl Pmintenset {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmintenset {}
+
 impl Pmintenset {
     #[inline]
     /// Writes PMINTENSET (*Performance Monitors Interrupt Enable Set Register*)
diff --git a/aarch32-cpu/src/register/pmovsr.rs b/aarch32-cpu/src/register/pmovsr.rs
index ed59d9b..c063419 100644
--- a/aarch32-cpu/src/register/pmovsr.rs
+++ b/aarch32-cpu/src/register/pmovsr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmovsr(pub u32);
+
 impl SysReg for Pmovsr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmovsr {
     const CRM: u32 = 12;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Pmovsr {}
+
 impl Pmovsr {
     #[inline]
     /// Reads PMOVSR (*Performance Monitor Overflow Flag Status Clear Register*)
@@ -22,7 +25,9 @@ impl Pmovsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmovsr {}
+
 impl Pmovsr {
     #[inline]
     /// Writes PMOVSR (*Performance Monitor Overflow Flag Status Clear Register*)
diff --git a/aarch32-cpu/src/register/pmovsset.rs b/aarch32-cpu/src/register/pmovsset.rs
index b1764aa..4ad574f 100644
--- a/aarch32-cpu/src/register/pmovsset.rs
+++ b/aarch32-cpu/src/register/pmovsset.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmovsset(pub u32);
+
 impl SysReg for Pmovsset {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmovsset {
     const CRM: u32 = 14;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Pmovsset {}
+
 impl Pmovsset {
     #[inline]
     /// Reads PMOVSSET (*Performance Monitor Overflow Flag Status Set Register*)
@@ -22,7 +25,9 @@ impl Pmovsset {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmovsset {}
+
 impl Pmovsset {
     #[inline]
     /// Writes PMOVSSET (*Performance Monitor Overflow Flag Status Set Register*)
diff --git a/aarch32-cpu/src/register/pmselr.rs b/aarch32-cpu/src/register/pmselr.rs
index fa6fb56..7a7b44d 100644
--- a/aarch32-cpu/src/register/pmselr.rs
+++ b/aarch32-cpu/src/register/pmselr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmselr(pub u32);
+
 impl SysReg for Pmselr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmselr {
     const CRM: u32 = 12;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Pmselr {}
+
 impl Pmselr {
     #[inline]
     /// Reads PMSELR (*Performance Monitors Event Counter Selection Register*)
@@ -22,7 +25,9 @@ impl Pmselr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmselr {}
+
 impl Pmselr {
     #[inline]
     /// Writes PMSELR (*Performance Monitors Event Counter Selection Register*)
diff --git a/aarch32-cpu/src/register/pmswinc.rs b/aarch32-cpu/src/register/pmswinc.rs
index b24b330..9f9c064 100644
--- a/aarch32-cpu/src/register/pmswinc.rs
+++ b/aarch32-cpu/src/register/pmswinc.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmswinc(pub u32);
+
 impl SysReg for Pmswinc {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmswinc {
     const CRM: u32 = 12;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegWrite for Pmswinc {}
+
 impl Pmswinc {
     #[inline]
     /// Writes PMSWINC (*Performance Monitors Software Increment Register*)
diff --git a/aarch32-cpu/src/register/pmuserenr.rs b/aarch32-cpu/src/register/pmuserenr.rs
index da10d3b..266814c 100644
--- a/aarch32-cpu/src/register/pmuserenr.rs
+++ b/aarch32-cpu/src/register/pmuserenr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmuserenr(pub u32);
+
 impl SysReg for Pmuserenr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmuserenr {
     const CRM: u32 = 14;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Pmuserenr {}
+
 impl Pmuserenr {
     #[inline]
     /// Reads PMUSERENR (*Performance Monitors User Enable Register*)
@@ -22,7 +25,9 @@ impl Pmuserenr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmuserenr {}
+
 impl Pmuserenr {
     #[inline]
     /// Writes PMUSERENR (*Performance Monitors User Enable Register*)
diff --git a/aarch32-cpu/src/register/pmxevcntr.rs b/aarch32-cpu/src/register/pmxevcntr.rs
index ddd35f2..9c7f7d4 100644
--- a/aarch32-cpu/src/register/pmxevcntr.rs
+++ b/aarch32-cpu/src/register/pmxevcntr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmxevcntr(pub u32);
+
 impl SysReg for Pmxevcntr {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmxevcntr {
     const CRM: u32 = 13;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Pmxevcntr {}
+
 impl Pmxevcntr {
     #[inline]
     /// Reads PMXEVCNTR (*Performance Monitors Selected Event Count Register*)
@@ -22,7 +25,9 @@ impl Pmxevcntr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmxevcntr {}
+
 impl Pmxevcntr {
     #[inline]
     /// Writes PMXEVCNTR (*Performance Monitors Selected Event Count Register*)
diff --git a/aarch32-cpu/src/register/pmxevtyper.rs b/aarch32-cpu/src/register/pmxevtyper.rs
index 5aaef51..4be65a2 100644
--- a/aarch32-cpu/src/register/pmxevtyper.rs
+++ b/aarch32-cpu/src/register/pmxevtyper.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Pmxevtyper(pub u32);
+
 impl SysReg for Pmxevtyper {
     const CP: u32 = 15;
     const CRN: u32 = 9;
@@ -14,7 +15,9 @@ impl SysReg for Pmxevtyper {
     const CRM: u32 = 13;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Pmxevtyper {}
+
 impl Pmxevtyper {
     #[inline]
     /// Reads PMXEVTYPER (*Performance Monitors Selected Event Type Register*)
@@ -22,7 +25,9 @@ impl Pmxevtyper {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Pmxevtyper {}
+
 impl Pmxevtyper {
     #[inline]
     /// Writes PMXEVTYPER (*Performance Monitors Selected Event Type Register*)
diff --git a/aarch32-cpu/src/register/revidr.rs b/aarch32-cpu/src/register/revidr.rs
index fb2aae0..e86dc7e 100644
--- a/aarch32-cpu/src/register/revidr.rs
+++ b/aarch32-cpu/src/register/revidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Revidr(pub u32);
+
 impl SysReg for Revidr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Revidr {
     const CRM: u32 = 0;
     const OP2: u32 = 6;
 }
+
 impl crate::register::SysRegRead for Revidr {}
+
 impl Revidr {
     #[inline]
     /// Reads REVIDR (*Revision ID Register*)
diff --git a/aarch32-cpu/src/register/rgnr.rs b/aarch32-cpu/src/register/rgnr.rs
index 82cba4d..c7f05c3 100644
--- a/aarch32-cpu/src/register/rgnr.rs
+++ b/aarch32-cpu/src/register/rgnr.rs
@@ -9,6 +9,7 @@ use super::SysRegWrite;
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Rgnr(pub u32);
+
 impl SysReg for Rgnr {
     const CP: u32 = 15;
     const CRN: u32 = 6;
@@ -16,7 +17,9 @@ impl SysReg for Rgnr {
     const CRM: u32 = 2;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Rgnr {}
+
 impl Rgnr {
     #[inline]
     /// Reads RGNR (*MPU Region Number Register*)
@@ -26,6 +29,7 @@ impl Rgnr {
 }
 
 impl crate::register::SysRegWrite for Rgnr {}
+
 impl Rgnr {
     #[inline]
     /// Writes RGNR (*MPU Region Number Register*)
diff --git a/aarch32-cpu/src/register/rvbar.rs b/aarch32-cpu/src/register/rvbar.rs
index 8c5a684..02f7922 100644
--- a/aarch32-cpu/src/register/rvbar.rs
+++ b/aarch32-cpu/src/register/rvbar.rs
@@ -3,10 +3,12 @@
 use crate::register::{SysReg, SysRegRead};
 
 /// RVBAR (*Reset Vector Base Address Register*)
-#[derive(Debug, Clone, Copy)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(transparent)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Rvbar(pub u32);
+
 impl SysReg for Rvbar {
     const CP: u32 = 15;
     const CRN: u32 = 12;
@@ -14,7 +16,9 @@ impl SysReg for Rvbar {
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Rvbar {}
+
 impl Rvbar {
     #[inline]
     /// Reads RVBAR (*Reset Vector Base Address Register*)
diff --git a/aarch32-cpu/src/register/tcmtr.rs b/aarch32-cpu/src/register/tcmtr.rs
index 145fbea..19789ce 100644
--- a/aarch32-cpu/src/register/tcmtr.rs
+++ b/aarch32-cpu/src/register/tcmtr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Tcmtr(pub u32);
+
 impl SysReg for Tcmtr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Tcmtr {
     const CRM: u32 = 0;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Tcmtr {}
+
 impl Tcmtr {
     #[inline]
     /// Reads TCMTR (*TCM Type Register*)
diff --git a/aarch32-cpu/src/register/tlbtr.rs b/aarch32-cpu/src/register/tlbtr.rs
index 4b64851..41ce0ae 100644
--- a/aarch32-cpu/src/register/tlbtr.rs
+++ b/aarch32-cpu/src/register/tlbtr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Tlbtr(pub u32);
+
 impl SysReg for Tlbtr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Tlbtr {
     const CRM: u32 = 0;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Tlbtr {}
+
 impl Tlbtr {
     #[inline]
     /// Reads TLBTR (*TLB Type Register*)
diff --git a/aarch32-cpu/src/register/tpidrprw.rs b/aarch32-cpu/src/register/tpidrprw.rs
index 1332407..c6bcc91 100644
--- a/aarch32-cpu/src/register/tpidrprw.rs
+++ b/aarch32-cpu/src/register/tpidrprw.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Tpidrprw(pub u32);
+
 impl SysReg for Tpidrprw {
     const CP: u32 = 15;
     const CRN: u32 = 13;
@@ -14,7 +15,9 @@ impl SysReg for Tpidrprw {
     const CRM: u32 = 0;
     const OP2: u32 = 4;
 }
+
 impl crate::register::SysRegRead for Tpidrprw {}
+
 impl Tpidrprw {
     #[inline]
     /// Reads TPIDRPRW (*EL1 Software Thread ID Register*)
@@ -22,7 +25,9 @@ impl Tpidrprw {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Tpidrprw {}
+
 impl Tpidrprw {
     #[inline]
     /// Writes TPIDRPRW (*EL1 Software Thread ID Register*)
diff --git a/aarch32-cpu/src/register/tpidruro.rs b/aarch32-cpu/src/register/tpidruro.rs
index 87190c9..a17fed5 100644
--- a/aarch32-cpu/src/register/tpidruro.rs
+++ b/aarch32-cpu/src/register/tpidruro.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Tpidruro(pub u32);
+
 impl SysReg for Tpidruro {
     const CP: u32 = 15;
     const CRN: u32 = 13;
@@ -14,7 +15,9 @@ impl SysReg for Tpidruro {
     const CRM: u32 = 0;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Tpidruro {}
+
 impl Tpidruro {
     #[inline]
     /// Reads TPIDRURO (*EL0 Read-Only Software Thread ID Register*)
@@ -22,7 +25,9 @@ impl Tpidruro {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Tpidruro {}
+
 impl Tpidruro {
     #[inline]
     /// Writes TPIDRURO (*EL0 Read-Only Software Thread ID Register*)
diff --git a/aarch32-cpu/src/register/tpidrurw.rs b/aarch32-cpu/src/register/tpidrurw.rs
index 7a54f0f..3733b2e 100644
--- a/aarch32-cpu/src/register/tpidrurw.rs
+++ b/aarch32-cpu/src/register/tpidrurw.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Tpidrurw(pub u32);
+
 impl SysReg for Tpidrurw {
     const CP: u32 = 15;
     const CRN: u32 = 13;
@@ -14,7 +15,9 @@ impl SysReg for Tpidrurw {
     const CRM: u32 = 0;
     const OP2: u32 = 2;
 }
+
 impl crate::register::SysRegRead for Tpidrurw {}
+
 impl Tpidrurw {
     #[inline]
     /// Reads TPIDRURW (*EL0 Read/Write Software Thread ID Register*)
@@ -22,7 +25,9 @@ impl Tpidrurw {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Tpidrurw {}
+
 impl Tpidrurw {
     #[inline]
     /// Writes TPIDRURW (*EL0 Read/Write Software Thread ID Register*)
diff --git a/aarch32-cpu/src/register/vmpidr.rs b/aarch32-cpu/src/register/vmpidr.rs
index d581769..3a0fed3 100644
--- a/aarch32-cpu/src/register/vmpidr.rs
+++ b/aarch32-cpu/src/register/vmpidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Vmpidr(pub u32);
+
 impl SysReg for Vmpidr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Vmpidr {
     const CRM: u32 = 0;
     const OP2: u32 = 5;
 }
+
 impl crate::register::SysRegRead for Vmpidr {}
+
 impl Vmpidr {
     #[inline]
     /// Reads VMPIDR (*Virtualization Multiprocessor ID Register*)
@@ -22,7 +25,9 @@ impl Vmpidr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Vmpidr {}
+
 impl Vmpidr {
     #[inline]
     /// Writes VMPIDR (*Virtualization Multiprocessor ID Register*)
diff --git a/aarch32-cpu/src/register/vpidr.rs b/aarch32-cpu/src/register/vpidr.rs
index a67e305..2e82415 100644
--- a/aarch32-cpu/src/register/vpidr.rs
+++ b/aarch32-cpu/src/register/vpidr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Vpidr(pub u32);
+
 impl SysReg for Vpidr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
@@ -14,7 +15,9 @@ impl SysReg for Vpidr {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Vpidr {}
+
 impl Vpidr {
     #[inline]
     /// Reads VPIDR (*Virtualization Processor ID Register*)
@@ -22,7 +25,9 @@ impl Vpidr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Vpidr {}
+
 impl Vpidr {
     #[inline]
     /// Writes VPIDR (*Virtualization Processor ID Register*)
diff --git a/aarch32-cpu/src/register/vsctlr.rs b/aarch32-cpu/src/register/vsctlr.rs
index 4036ed2..dfc9258 100644
--- a/aarch32-cpu/src/register/vsctlr.rs
+++ b/aarch32-cpu/src/register/vsctlr.rs
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Vsctlr(pub u32);
+
 impl SysReg for Vsctlr {
     const CP: u32 = 15;
     const CRN: u32 = 2;
@@ -14,7 +15,9 @@ impl SysReg for Vsctlr {
     const CRM: u32 = 0;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Vsctlr {}
+
 impl Vsctlr {
     #[inline]
     /// Reads VSCTLR (*Virtualization System Control Register*)
@@ -22,7 +25,9 @@ impl Vsctlr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Vsctlr {}
+
 impl Vsctlr {
     #[inline]
     /// Writes VSCTLR (*Virtualization System Control Register*)
diff --git a/examples/mps3-an536/reference/registers-armv8r-none-eabihf.out b/examples/mps3-an536/reference/registers-armv8r-none-eabihf.out
index 39c2c55..ffd2137 100644
--- a/examples/mps3-an536/reference/registers-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/registers-armv8r-none-eabihf.out
@@ -1,7 +1,7 @@
 MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xd13 rev=0x3 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
 IMP_CBAR { 0xf0000000 }
-VBAR { 0x08000000 }
+Vbar(8000000)
 PMSA-v8 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
 Region 0: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
 Region 1: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
diff --git a/examples/mps3-an536/src/bin/registers.rs b/examples/mps3-an536/src/bin/registers.rs
index 114ac90..ba989fe 100644
--- a/examples/mps3-an536/src/bin/registers.rs
+++ b/examples/mps3-an536/src/bin/registers.rs
@@ -22,12 +22,12 @@ fn main() -> ! {
 }
 
 fn chip_info() {
-    println!("{:?}", aarch32_cpu::register::Midr::read());
-    println!("{:?}", aarch32_cpu::register::Cpsr::read());
+    println!("{:x?}", aarch32_cpu::register::Midr::read());
+    println!("{:x?}", aarch32_cpu::register::Cpsr::read());
     #[cfg(arm_architecture = "v8-r")]
     {
-        println!("{:?}", aarch32_cpu::register::ImpCbar::read());
-        println!("{:?}", aarch32_cpu::register::Vbar::read());
+        println!("{:x?}", aarch32_cpu::register::ImpCbar::read());
+        println!("{:x?}", aarch32_cpu::register::Vbar::read());
         // This only works in EL2 and start-up put us in EL1
         // println!("{:?}", aarch32_cpu::register::Hvbar::read());
     }
diff --git a/examples/versatileab/reference/registers-armv4t-none-eabi.out b/examples/versatileab/reference/registers-armv4t-none-eabi.out
index 5837893..881a48f 100644
--- a/examples/versatileab/reference/registers-armv4t-none-eabi.out
+++ b/examples/versatileab/reference/registers-armv4t-none-eabi.out
@@ -1,5 +1,5 @@
 MIDR { implementer=0x69 variant=0x0 arch=0x5 part_no=0x210 rev=0x0 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(1761943808)
+Mpidr(69052100)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/registers-armv5te-none-eabi.out b/examples/versatileab/reference/registers-armv5te-none-eabi.out
index 48cca85..b58d175 100644
--- a/examples/versatileab/reference/registers-armv5te-none-eabi.out
+++ b/examples/versatileab/reference/registers-armv5te-none-eabi.out
@@ -1,5 +1,5 @@
 MIDR { implementer=0x41 variant=0x0 arch=0x6 part_no=0x926 rev=0x5 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(1090949733)
+Mpidr(41069265)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/registers-armv7r-none-eabi.out b/examples/versatileab/reference/registers-armv7r-none-eabi.out
index 79c7e24..6d58047 100644
--- a/examples/versatileab/reference/registers-armv7r-none-eabi.out
+++ b/examples/versatileab/reference/registers-armv7r-none-eabi.out
@@ -1,6 +1,6 @@
 MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(3221225472)
+Mpidr(c0000000)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
 PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
diff --git a/examples/versatileab/reference/registers-armv7r-none-eabihf.out b/examples/versatileab/reference/registers-armv7r-none-eabihf.out
index 79c7e24..6d58047 100644
--- a/examples/versatileab/reference/registers-armv7r-none-eabihf.out
+++ b/examples/versatileab/reference/registers-armv7r-none-eabihf.out
@@ -1,6 +1,6 @@
 MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(3221225472)
+Mpidr(c0000000)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
 PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
diff --git a/examples/versatileab/reference/registers-thumbv4t-none-eabi.out b/examples/versatileab/reference/registers-thumbv4t-none-eabi.out
index 5837893..881a48f 100644
--- a/examples/versatileab/reference/registers-thumbv4t-none-eabi.out
+++ b/examples/versatileab/reference/registers-thumbv4t-none-eabi.out
@@ -1,5 +1,5 @@
 MIDR { implementer=0x69 variant=0x0 arch=0x5 part_no=0x210 rev=0x0 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(1761943808)
+Mpidr(69052100)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/registers-thumbv5te-none-eabi.out b/examples/versatileab/reference/registers-thumbv5te-none-eabi.out
index 48cca85..b58d175 100644
--- a/examples/versatileab/reference/registers-thumbv5te-none-eabi.out
+++ b/examples/versatileab/reference/registers-thumbv5te-none-eabi.out
@@ -1,5 +1,5 @@
 MIDR { implementer=0x41 variant=0x0 arch=0x6 part_no=0x926 rev=0x5 }
 CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
-Mpidr(1090949733)
+Mpidr(41069265)
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
 SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/src/bin/registers.rs b/examples/versatileab/src/bin/registers.rs
index 2ed1ab3..94f2a0c 100644
--- a/examples/versatileab/src/bin/registers.rs
+++ b/examples/versatileab/src/bin/registers.rs
@@ -20,9 +20,9 @@ fn main() -> ! {
 }
 
 fn chip_info() {
-    println!("{:?}", aarch32_cpu::register::Midr::read());
-    println!("{:?}", aarch32_cpu::register::Cpsr::read());
-    println!("{:?}", aarch32_cpu::register::Mpidr::read());
+    println!("{:x?}", aarch32_cpu::register::Midr::read());
+    println!("{:x?}", aarch32_cpu::register::Cpsr::read());
+    println!("{:x?}", aarch32_cpu::register::Mpidr::read());
 }
 
 #[cfg(arm_architecture = "v7-r")]