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Support thumb-mode Armv7-R, Armv7-A and Armv8-R #99

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dda62b3
Support thumb-mode Armv7-R, Armv7-A and Armv8-R
thejpster Dec 31, 2025
a87904c
Ignore .DS_Store files
thejpster Jan 1, 2026
87d1971
Don't rely on CPSR contents.
thejpster Jan 2, 2026
edecf04
Need updated nightly for the examples.
thejpster Jan 25, 2026
71bf032
Fixup the new output files.
thejpster Jan 25, 2026
3a7e27b
Rationalise the directive order for inline asm.
thejpster Feb 1, 2026
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22 changes: 20 additions & 2 deletions .cargo/config.toml
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Expand Up @@ -2,27 +2,45 @@
# Note, this requires QEMU 9 or higher
runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"

[target.thumbv8r-none-eabihf]
# Note, this requires QEMU 9 or higher
runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"

[target.armv7r-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"

[target.thumbv7r-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"

[target.armv7r-none-eabi]
# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
# qemu-system-arm will lock up
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"

[target.thumbv7r-none-eabi]
# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
# qemu-system-arm will lock up
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"

[target.armv7a-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.thumbv7a-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.armv7a-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.thumbv7a-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.armv5te-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.armv4t-none-eabi]
[target.thumbv5te-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.thumbv5te-none-eabi]
[target.armv4t-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.thumbv4t-none-eabi]
Expand Down
37 changes: 32 additions & 5 deletions .github/workflows/build.yml
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Expand Up @@ -44,7 +44,34 @@ jobs:
run: |
just build-tier2 ${{ matrix.target }}

# These targets need build-std, and have no atomics
# These targets need build-std
build-tier3:
runs-on: ubuntu-24.04
needs: setup
strategy:
matrix:
target:
- thumbv7r-none-eabi
- thumbv7r-none-eabihf
- thumbv7a-none-eabi
- thumbv7a-none-eabihf
- thumbv8r-none-eabihf
steps:
- name: Checkout
uses: actions/checkout@v4
- name: Install Just
uses: taiki-e/install-action@just
- name: Install Rust
run: |
rustup install nightly-2026-01-25
rustup component add rust-src --toolchain nightly-2026-01-25
rustup default nightly-2026-01-25
- name: Build
run: |
just build-tier3 ${{ matrix.target }}

# These targets need build-std, and have no atomics so we have to skip
# the 'critical-section-multi-core' feature
build-tier3-no-atomics:
runs-on: ubuntu-24.04
needs: setup
Expand All @@ -62,9 +89,9 @@ jobs:
uses: taiki-e/install-action@just
- name: Install Rust
run: |
rustup install nightly-2025-10-29
rustup component add rust-src --toolchain nightly-2025-10-29
rustup default nightly-2025-10-29
rustup install nightly-2026-01-25
rustup component add rust-src --toolchain nightly-2026-01-25
rustup default nightly-2026-01-25
- name: Build
run: |
just build-tier3-no-atomics ${{ matrix.target }}
Expand Down Expand Up @@ -92,7 +119,7 @@ jobs:
# Gather all the above build jobs together for the purposes of getting an overall pass-fail
build-all:
runs-on: ubuntu-24.04
needs: [build-tier2, build-tier3-no-atomics, build-arm-targets]
needs: [build-tier2, build-tier3-no-atomics, build-tier3, build-arm-targets]
steps:
- run: /bin/true

Expand Down
2 changes: 2 additions & 0 deletions .gitignore
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Expand Up @@ -4,3 +4,5 @@ examples/mps3-an536/target-d32
examples/versatileab/target
examples/versatileab/target-d32
Cargo.lock
**/.DS_Store

8 changes: 4 additions & 4 deletions aarch32-rt/src/arch_v4/abort.rs
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Expand Up @@ -5,13 +5,13 @@ core::arch::global_asm!(
// Work around https://github.com/rust-lang/rust/issues/127269
.fpu vfp2

.section .text._asm_default_data_abort_handler

// Called from the vector table when we have an undefined exception.
// Saves state and calls a C-compatible handler like
// `extern "C" fn _data_abort_handler(addr: usize);`
.global _asm_default_data_abort_handler
.section .text._asm_default_data_abort_handler
.arm
.global _asm_default_data_abort_handler
.type _asm_default_data_abort_handler, %function
_asm_default_data_abort_handler:
// Subtract 8 from the stored LR, see p.1214 of the ARMv7-A architecture manual.
Expand Down Expand Up @@ -39,13 +39,13 @@ core::arch::global_asm!(
movs pc, lr
.size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler

.section .text._asm_default_prefetch_abort_handler

// Called from the vector table when we have a prefetch abort.
// Saves state and calls a C-compatible handler like
// `extern "C" fn _prefetch_abort_handler(addr: usize);`
.global _asm_default_prefetch_abort_handler
.section .text._asm_default_prefetch_abort_handler
.arm
.global _asm_default_prefetch_abort_handler
.type _asm_default_prefetch_abort_handler, %function
_asm_default_prefetch_abort_handler:
// Subtract 4 from the stored LR, see p.1212 of the ARMv7-A architecture manual.
Expand Down
5 changes: 2 additions & 3 deletions aarch32-rt/src/arch_v4/interrupt.rs
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Expand Up @@ -8,13 +8,12 @@ core::arch::global_asm!(
// Work around https://github.com/rust-lang/rust/issues/127269
.fpu vfp2

.section .text._asm_default_irq_handler

// Called from the vector table when we have an interrupt.
// Saves state and calls a C-compatible handler like
// `extern "C" fn _irq_handler();`
.global _asm_default_irq_handler
.section .text._asm_default_irq_handler
.arm
.global _asm_default_irq_handler
.type _asm_default_irq_handler, %function
_asm_default_irq_handler:
// make sure we jump back to the right place
Expand Down
4 changes: 2 additions & 2 deletions aarch32-rt/src/arch_v4/svc.rs
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Expand Up @@ -6,13 +6,13 @@ core::arch::global_asm!(
// Work around https://github.com/rust-lang/rust/issues/127269
.fpu vfp2

.section .text._asm_default_svc_handler

// Called from the vector table when we have an software interrupt.
// Saves state and calls a C-compatible handler like
// `extern "C" fn _svc_handler(svc: u32);`
.global _asm_default_svc_handler
.section .text._asm_default_svc_handler
.arm
.global _asm_default_svc_handler
.type _asm_default_svc_handler, %function
_asm_default_svc_handler:
stmfd sp!, {{ r0, lr }}
Expand Down
12 changes: 8 additions & 4 deletions aarch32-rt/src/arch_v7/svc.rs
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Expand Up @@ -21,10 +21,14 @@ core::arch::global_asm!(
r#"
mrs r0, spsr // Load processor status that was banked on entry
tst r0, {t_bit} // SVC occurred from Thumb state?
ldrhne r0, [lr,#-2] // Yes: Load halfword and...
bicne r0, r0, #0xFF00 // ...extract comment field
ldreq r0, [lr,#-4] // No: Load word and...
biceq r0, r0, #0xFF000000 // ...extract comment field
beq 1f
ldrh r0, [lr,#-2] // Yes: Load halfword and...
bic r0, r0, #0xFF00 // ...extract comment field
b 2f
1:
ldr r0, [lr,#-4] // No: Load word and...
bic r0, r0, #0xFF000000 // ...extract comment field
2:
// r0 now contains SVC number
bl _svc_handler
"#,
Expand Down
2 changes: 1 addition & 1 deletion aarch32-rt/src/lib.rs
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Expand Up @@ -804,8 +804,8 @@ core::arch::global_asm!(

// Initialises stacks, .data and .bss
.section .text._init_segments
.global _init_segments
.arm
.global _init_segments
.type _init_segments, %function
_init_segments:
// Initialise .bss
Expand Down
19 changes: 16 additions & 3 deletions arm-targets/src/lib.rs
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Expand Up @@ -216,11 +216,14 @@ impl Arch {
Some(Arch::Armv8MBase)
} else if target.starts_with("thumbv8m.main-") {
Some(Arch::Armv8MMain)
} else if target.starts_with("armv7r-") || target.starts_with("armebv7r") {
} else if target.starts_with("armv7r-")
|| target.starts_with("armebv7r-")
|| target.starts_with("thumbv7r-")
{
Some(Arch::Armv7R)
} else if target.starts_with("armv8r-") {
} else if target.starts_with("armv8r-") || target.starts_with("thumbv8r-") {
Some(Arch::Armv8R)
} else if target.starts_with("armv7a-") {
} else if target.starts_with("armv7a-") || target.starts_with("thumbv7a-") {
Some(Arch::Armv7A)
} else if target.starts_with("aarch64-") || target.starts_with("aarch64be-") {
Some(Arch::Armv8A)
Expand Down Expand Up @@ -484,6 +487,16 @@ mod test {
assert_eq!(target_info.abi(), Some(Abi::EabiHf));
}

#[test]
fn thumbv8r_none_eabihf() {
let target = "thumbv8r-none-eabihf";
let target_info = process_target(target);
assert_eq!(target_info.isa(), Some(Isa::T32));
assert_eq!(target_info.arch(), Some(Arch::Armv8R));
assert_eq!(target_info.profile(), Some(Profile::R));
assert_eq!(target_info.abi(), Some(Abi::EabiHf));
}

#[test]
fn armv7a_none_eabi() {
let target = "armv7a-none-eabi";
Expand Down
14 changes: 14 additions & 0 deletions examples/mps3-an536/reference/abt-exception-a32-thumbv8r-none-eabihf.out
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@@ -0,0 +1,14 @@
Hello, this is an data abort exception example
data abort occurred
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
DFSR Status: Ok(AlignmentFault)
caught unaligned_from_a32
caught fault on COUNTER
Doing it again
data abort occurred
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
DFSR Status: Ok(AlignmentFault)
caught unaligned_from_a32
caught fault on COUNTER
Skipping instruction
Recovered from fault OK!
14 changes: 14 additions & 0 deletions examples/mps3-an536/reference/abt-exception-t32-thumbv8r-none-eabihf.out
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@@ -0,0 +1,14 @@
Hello, this is an data abort exception example
data abort occurred
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
DFSR Status: Ok(AlignmentFault)
caught unaligned_from_t32
caught fault on COUNTER
Doing it again
data abort occurred
DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
DFSR Status: Ok(AlignmentFault)
caught unaligned_from_t32
caught fault on COUNTER
Skipping instruction
Recovered from fault OK!
27 changes: 27 additions & 0 deletions examples/mps3-an536/reference/el2_hello-thumbv8r-none-eabihf.out
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@@ -0,0 +1,27 @@
Hello, this is semihosting! x = 1.000, y = 2.000
Region 0: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 1: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 2: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 3: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 4: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 5: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 6: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 7: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 8: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 9: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 10: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 11: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 12: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 13: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 14: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
Region 15: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
PANIC: PanicInfo {
message: I am an example panic,
location: Location {
file: "src/bin/el2_hello.rs",
line: 28,
column: 5,
},
can_unwind: true,
force_no_backtrace: false,
}
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