diff --git a/.cargo/config.toml b/.cargo/config.toml
index 1d43fc3..d4d345e 100644
--- a/.cargo/config.toml
+++ b/.cargo/config.toml
@@ -2,27 +2,54 @@
 # Note, this requires QEMU 9 or higher
 runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"
 
+[target.thumbv8r-none-eabihf]
+# Note, this requires QEMU 9 or higher
+runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"
+
 [target.armv7r-none-eabihf]
 runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"
 
+[target.thumbv7r-none-eabihf]
+runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"
+
 [target.armv7r-none-eabi]
 # change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
 # qemu-system-arm will lock up
 runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"
 
+[target.thumbv7r-none-eabi]
+# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
+# qemu-system-arm will lock up
+runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"
+
 [target.armv7a-none-eabihf]
 runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
 
+[target.thumbv7a-none-eabihf]
+runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
+
 [target.armv7a-none-eabi]
 runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
 
+[target.thumbv7a-none-eabi]
+runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"
+
+[target.armv6-none-eabihf]
+runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
+
+[target.armv6-none-eabi]
+runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
+
+[target.thumbv6-none-eabi]
+runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"
+
 [target.armv5te-none-eabi]
 runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
 
-[target.armv4t-none-eabi]
+[target.thumbv5te-none-eabi]
 runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
 
-[target.thumbv5te-none-eabi]
+[target.armv4t-none-eabi]
 runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
 
 [target.thumbv4t-none-eabi]
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index ba71484..69a2c2a 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -44,7 +44,34 @@ jobs:
         run: |
           just build-tier2 ${{ matrix.target }}
 
-  # These targets need build-std, and have no atomics
+  # These targets need build-std
+  build-tier3:
+    runs-on: ubuntu-24.04
+    needs: setup
+    strategy:
+      matrix:
+        target:
+          - thumbv7r-none-eabi
+          - thumbv7r-none-eabihf
+          - thumbv7a-none-eabi
+          - thumbv7a-none-eabihf
+          - thumbv8r-none-eabihf
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Install Just
+        uses: taiki-e/install-action@just
+      - name: Install Rust
+        run: |
+          rustup install nightly-2026-01-26
+          rustup component add rust-src --toolchain nightly-2026-01-26
+          rustup default nightly-2026-01-26
+      - name: Build
+        run: |
+          just build-tier3 ${{ matrix.target }}
+
+  # These targets need build-std, and have no atomics so we have to skip
+  # the 'critical-section-multi-core' feature
   build-tier3-no-atomics:
     runs-on: ubuntu-24.04
     needs: setup
@@ -62,9 +89,9 @@ jobs:
         uses: taiki-e/install-action@just
       - name: Install Rust
         run: |
-          rustup install nightly-2025-10-29
-          rustup component add rust-src --toolchain nightly-2025-10-29
-          rustup default nightly-2025-10-29
+          rustup install nightly-2026-01-26
+          rustup component add rust-src --toolchain nightly-2026-01-26
+          rustup default nightly-2026-01-26
       - name: Build
         run: |
           just build-tier3-no-atomics ${{ matrix.target }}
@@ -92,7 +119,7 @@ jobs:
   # Gather all the above build jobs together for the purposes of getting an overall pass-fail
   build-all:
     runs-on: ubuntu-24.04
-    needs: [build-tier2, build-tier3-no-atomics, build-arm-targets]
+    needs: [build-tier2, build-tier3-no-atomics, build-tier3, build-arm-targets]
     steps:
       - run: /bin/true
 
diff --git a/.gitignore b/.gitignore
index 75337a3..a139b23 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,3 +4,5 @@ examples/mps3-an536/target-d32
 examples/versatileab/target
 examples/versatileab/target-d32
 Cargo.lock
+**/.DS_Store
+
diff --git a/aarch32-cpu/src/register/cpsr.rs b/aarch32-cpu/src/register/cpsr.rs
index 8fab4af..718f0e3 100644
--- a/aarch32-cpu/src/register/cpsr.rs
+++ b/aarch32-cpu/src/register/cpsr.rs
@@ -75,7 +75,11 @@ impl Cpsr {
     /// `thumb*` targets, as Thumb-1 cannot do an MRS.
     #[cfg_attr(not(feature = "check-asm"), inline)]
     #[cfg_attr(
-        any(arm_architecture = "v4t", arm_architecture = "v5te"),
+        any(
+            arm_architecture = "v4t",
+            arm_architecture = "v5te",
+            arm_architecture = "v6"
+        ),
         instruction_set(arm::a32)
     )]
     pub fn read() -> Self {
@@ -108,7 +112,11 @@ impl Cpsr {
     /// `thumb*` targets, as Thumb-1 cannot do an MSR.
     #[cfg_attr(not(feature = "check-asm"), inline)]
     #[cfg_attr(
-        any(arm_architecture = "v4t", arm_architecture = "v5te"),
+        any(
+            arm_architecture = "v4t",
+            arm_architecture = "v5te",
+            arm_architecture = "v6"
+        ),
         instruction_set(arm::a32)
     )]
     pub unsafe fn write(_value: Self) {
diff --git a/aarch32-cpu/src/register/mod.rs b/aarch32-cpu/src/register/mod.rs
index 7dac1a3..f8ba885 100644
--- a/aarch32-cpu/src/register/mod.rs
+++ b/aarch32-cpu/src/register/mod.rs
@@ -225,7 +225,11 @@ pub trait SysRegRead: SysReg {
     /// may have side-effects.
     #[cfg_attr(not(feature = "check-asm"), inline)]
     #[cfg_attr(
-        any(arm_architecture = "v4t", arm_architecture = "v5te"),
+        any(
+            arm_architecture = "v4t",
+            arm_architecture = "v5te",
+            arm_architecture = "v6"
+        ),
         instruction_set(arm::a32)
     )]
     unsafe fn read_raw() -> u32 {
@@ -261,7 +265,11 @@ pub trait SysRegWrite: SysReg {
     /// writing valid data here.
     #[cfg_attr(not(feature = "check-asm"), inline)]
     #[cfg_attr(
-        any(arm_architecture = "v4t", arm_architecture = "v5te"),
+        any(
+            arm_architecture = "v4t",
+            arm_architecture = "v5te",
+            arm_architecture = "v6"
+        ),
         instruction_set(arm::a32)
     )]
     unsafe fn write_raw(_value: u32) {
diff --git a/aarch32-rt/src/arch_v7/svc.rs b/aarch32-rt/src/arch_v7/svc.rs
index 3a906e1..000fa69 100644
--- a/aarch32-rt/src/arch_v7/svc.rs
+++ b/aarch32-rt/src/arch_v7/svc.rs
@@ -21,10 +21,14 @@ core::arch::global_asm!(
     r#"
         mrs     r0, spsr                 // Load processor status that was banked on entry
         tst     r0, {t_bit}              // SVC occurred from Thumb state?
-        ldrhne  r0, [lr,#-2]             // Yes: Load halfword and...
-        bicne   r0, r0, #0xFF00          // ...extract comment field
-        ldreq   r0, [lr,#-4]             // No: Load word and...
-        biceq   r0, r0, #0xFF000000      // ...extract comment field
+        beq     1f
+        ldrh    r0, [lr,#-2]             // Yes: Load halfword and...
+        bic     r0, r0, #0xFF00          // ...extract comment field
+        b       2f
+    1:
+        ldr     r0, [lr,#-4]             // No: Load word and...
+        bic     r0, r0, #0xFF000000      // ...extract comment field
+    2:
         // r0 now contains SVC number
         bl      _svc_handler
     "#,
diff --git a/arm-targets/src/lib.rs b/arm-targets/src/lib.rs
index bd71463..7b02726 100644
--- a/arm-targets/src/lib.rs
+++ b/arm-targets/src/lib.rs
@@ -216,15 +216,21 @@ impl Arch {
             Some(Arch::Armv8MBase)
         } else if target.starts_with("thumbv8m.main-") {
             Some(Arch::Armv8MMain)
-        } else if target.starts_with("armv7r-") || target.starts_with("armebv7r") {
+        } else if target.starts_with("armv7r-")
+            || target.starts_with("armebv7r-")
+            || target.starts_with("thumbv7r-")
+        {
             Some(Arch::Armv7R)
-        } else if target.starts_with("armv8r-") {
+        } else if target.starts_with("armv8r-") || target.starts_with("thumbv8r-") {
             Some(Arch::Armv8R)
-        } else if target.starts_with("armv7a-") {
+        } else if target.starts_with("armv7a-") || target.starts_with("thumbv7a-") {
             Some(Arch::Armv7A)
         } else if target.starts_with("aarch64-") || target.starts_with("aarch64be-") {
             Some(Arch::Armv8A)
-        } else if target.starts_with("arm-") {
+        } else if target.starts_with("arm-")
+            || target.starts_with("armv6-")
+            || target.starts_with("thumbv6-")
+        {
             // If not specified, assume Armv6
             Some(Arch::Armv6)
         } else {
@@ -404,6 +410,26 @@ mod test {
         assert_eq!(target_info.abi(), Some(Abi::Eabi));
     }
 
+    #[test]
+    fn armv6_none_eabi() {
+        let target = "armv6-none-eabi";
+        let target_info = process_target(target);
+        assert_eq!(target_info.isa(), Some(Isa::A32));
+        assert_eq!(target_info.arch(), Some(Arch::Armv6));
+        assert_eq!(target_info.profile(), Some(Profile::Legacy));
+        assert_eq!(target_info.abi(), Some(Abi::Eabi));
+    }
+
+    #[test]
+    fn armv6_none_eabihf() {
+        let target = "armv6-none-eabihf";
+        let target_info = process_target(target);
+        assert_eq!(target_info.isa(), Some(Isa::A32));
+        assert_eq!(target_info.arch(), Some(Arch::Armv6));
+        assert_eq!(target_info.profile(), Some(Profile::Legacy));
+        assert_eq!(target_info.abi(), Some(Abi::EabiHf));
+    }
+
     #[test]
     fn arm_unknown_linux_gnueabi() {
         let target = "arm-unknown-linux-gnueabi";
@@ -484,6 +510,16 @@ mod test {
         assert_eq!(target_info.abi(), Some(Abi::EabiHf));
     }
 
+    #[test]
+    fn thumbv8r_none_eabihf() {
+        let target = "thumbv8r-none-eabihf";
+        let target_info = process_target(target);
+        assert_eq!(target_info.isa(), Some(Isa::T32));
+        assert_eq!(target_info.arch(), Some(Arch::Armv8R));
+        assert_eq!(target_info.profile(), Some(Profile::R));
+        assert_eq!(target_info.abi(), Some(Abi::EabiHf));
+    }
+
     #[test]
     fn armv7a_none_eabi() {
         let target = "armv7a-none-eabi";
diff --git a/examples/mps3-an536/reference/abt-exception-a32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/abt-exception-a32-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..d521f0b
--- /dev/null
+++ b/examples/mps3-an536/reference/abt-exception-a32-thumbv8r-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/mps3-an536/reference/abt-exception-t32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/abt-exception-t32-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..0067a8b
--- /dev/null
+++ b/examples/mps3-an536/reference/abt-exception-t32-thumbv8r-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/mps3-an536/reference/el2_hello-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/el2_hello-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..bf0ed13
--- /dev/null
+++ b/examples/mps3-an536/reference/el2_hello-thumbv8r-none-eabihf.out
@@ -0,0 +1,27 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+Region 0: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 1: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 2: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 3: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 4: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 5: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 6: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 7: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 8: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 9: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 10: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 11: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 12: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 13: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 14: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+Region 15: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false }
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/el2_hello.rs",
+        line: 28,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/mps3-an536/reference/fpu-test-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/fpu-test-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/mps3-an536/reference/fpu-test-thumbv8r-none-eabihf.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) ..............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+Sine wave test (f64)...
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
+( 0.0000) ..............................o
+( 0.1253) .................................o
+( 0.2487) .....................................o
+( 0.3681) .........................................o
+( 0.4818) ............................................o
+( 0.5878) ...............................................o
+( 0.6845) ..................................................o
+( 0.7705) .....................................................o
+( 0.8443) .......................................................o
+( 0.9048) .........................................................o
+( 0.9511) ..........................................................o
+( 0.9823) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9980) ...........................................................o
+( 0.9823) ...........................................................o
+( 0.9511) ..........................................................o
+( 0.9048) .........................................................o
+( 0.8443) .......................................................o
+( 0.7705) .....................................................o
+( 0.6845) ..................................................o
+( 0.5878) ...............................................o
+( 0.4818) ............................................o
+( 0.3681) .........................................o
+( 0.2487) .....................................o
+( 0.1253) .................................o
+(-0.0000) .............................o
+(-0.1253) ..........................o
+(-0.2487) ......................o
+(-0.3681) ..................o
+(-0.4818) ...............o
+(-0.5878) ............o
+(-0.6845) .........o
+(-0.7705) ......o
+(-0.8443) ....o
+(-0.9048) ..o
+(-0.9511) .o
+(-0.9823) o
+(-0.9980) o
+(-0.9980) o
+(-0.9823) o
+(-0.9511) .o
+(-0.9048) ..o
+(-0.8443) ....o
+(-0.7705) ......o
+(-0.6845) .........o
+(-0.5878) ............o
+(-0.4818) ...............o
+(-0.3681) ..................o
+(-0.2487) ......................o
+(-0.1253) ..........................o
diff --git a/examples/mps3-an536/reference/generic_timer-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/generic_timer-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..bd2c08a
--- /dev/null
+++ b/examples/mps3-an536/reference/generic_timer-thumbv8r-none-eabihf.out
@@ -0,0 +1,26 @@
+Found PERIPHBASE 0xf0000000
+Creating GIC driver @ 0xf0000000 / 0xf0100000
+Calling git.setup(0)
+cntfrq = 62.500 MHz
+Using physical timer ************************
+Print five, every 100ms...
+i = 0
+i = 1
+i = 2
+i = 3
+i = 4
+Waiting for 31250000 physical ticks to count up...
+Matched! physical
+Waiting for 31250000 physical ticks to count down...
+physical countdown hit zero!
+Using virtual timer ************************
+Print five, every 100ms...
+i = 0
+i = 1
+i = 2
+i = 3
+i = 4
+Waiting for 31250000 virtual ticks to count up...
+Matched! virtual
+Waiting for 31250000 virtual ticks to count down...
+virtual countdown hit zero!
diff --git a/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out
index d44bcd5..1c3bdd6 100644
--- a/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out
@@ -3,8 +3,8 @@ Creating GIC driver @ 0xf0000000 / 0xf0100000
 Calling git.setup(0)
 Configure Timer Interrupt...
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
   > IRQ
     - Timer fired, resetting
   < IRQ
diff --git a/examples/mps3-an536/reference/generic_timer_irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/generic_timer_irq-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..1c3bdd6
--- /dev/null
+++ b/examples/mps3-an536/reference/generic_timer_irq-thumbv8r-none-eabihf.out
@@ -0,0 +1,48 @@
+Found PERIPHBASE 0xf0000000
+Creating GIC driver @ 0xf0000000 / 0xf0100000
+Calling git.setup(0)
+Configure Timer Interrupt...
+Enabling interrupts...
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 0
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 1
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 2
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 3
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 4
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 5
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 6
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 7
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 8
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 9
+Timer IRQ test completed OK
diff --git a/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out
index db56b21..05e6eea 100644
--- a/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - handle_interrupt_with_id(SGI 3)
diff --git a/examples/mps3-an536/reference/gic-map-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-map-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..05e6eea
--- /dev/null
+++ b/examples/mps3-an536/reference/gic-map-thumbv8r-none-eabihf.out
@@ -0,0 +1,20 @@
+Found PERIPHBASE 0xf0000000
+Creating GIC driver @ 0xf0000000 / 0xf0100000
+Calling git.setup(0)
+Configure low-prio SGI...
+Configure high-prio SGI...
+gic.enable_interrupt()
+Enabling interrupts...
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+Send lo-prio SGI
+> IRQ
+- handle_interrupt_with_id(SGI 3)
+- got SGI 3, sending hi-prio SGI 4
+> IRQ
+- handle_interrupt_with_id(SGI 4)
+- got hi-prio SGI 4!
+< IRQ
+- finished sending hi-prio!
+< IRQ
+IRQ test completed OK
diff --git a/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out
index bd00a91..bde2935 100644
--- a/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - IRQ Handling SGI 3
diff --git a/examples/mps3-an536/reference/gic-priority-ceiling-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-priority-ceiling-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..bde2935
--- /dev/null
+++ b/examples/mps3-an536/reference/gic-priority-ceiling-thumbv8r-none-eabihf.out
@@ -0,0 +1,23 @@
+Found PERIPHBASE 0xf0000000
+Creating GIC driver @ 0xf0000000 / 0xf0100000
+Calling git.setup(0)
+Configure low-prio SGI...
+Configure high-prio SGI...
+gic.enable_interrupt()
+Enabling interrupts...
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+Send lo-prio SGI
+> IRQ
+- IRQ Handling SGI 3
+    - Low prio!
+    - Pre lock exit
+    - HIGH PRIO SHOULD RUN AFTER THIS
+> IRQ
+- IRQ Handling SGI 4
+    - High prio!
+< IRQ
+    - HIGH PRIO SHOULD RUN BEFORE THIS
+    - Post lock exit
+< IRQ
+IRQ test completed OK
diff --git a/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out
index db56b21..05e6eea 100644
--- a/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - handle_interrupt_with_id(SGI 3)
diff --git a/examples/mps3-an536/reference/gic-static-section-irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-static-section-irq-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..05e6eea
--- /dev/null
+++ b/examples/mps3-an536/reference/gic-static-section-irq-thumbv8r-none-eabihf.out
@@ -0,0 +1,20 @@
+Found PERIPHBASE 0xf0000000
+Creating GIC driver @ 0xf0000000 / 0xf0100000
+Calling git.setup(0)
+Configure low-prio SGI...
+Configure high-prio SGI...
+gic.enable_interrupt()
+Enabling interrupts...
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+Send lo-prio SGI
+> IRQ
+- handle_interrupt_with_id(SGI 3)
+- got SGI 3, sending hi-prio SGI 4
+> IRQ
+- handle_interrupt_with_id(SGI 4)
+- got hi-prio SGI 4!
+< IRQ
+- finished sending hi-prio!
+< IRQ
+IRQ test completed OK
diff --git a/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out
index ab68c14..94023e1 100644
--- a/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out
+++ b/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out
@@ -5,8 +5,8 @@ Configure low-prio SGI...
 Configure high-prio SGI...
 gic.enable_interrupt()
 Enabling interrupts...
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
-CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
 Send lo-prio SGI
 > IRQ
 - IRQ Handling SGI 3
diff --git a/examples/mps3-an536/reference/gic-unified-irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-unified-irq-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..94023e1
--- /dev/null
+++ b/examples/mps3-an536/reference/gic-unified-irq-thumbv8r-none-eabihf.out
@@ -0,0 +1,19 @@
+Found PERIPHBASE 0xf0000000
+Creating GIC driver @ 0xf0000000 / 0xf0100000
+Calling git.setup(0)
+Configure low-prio SGI...
+Configure high-prio SGI...
+gic.enable_interrupt()
+Enabling interrupts...
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 }
+Send lo-prio SGI
+> IRQ
+- IRQ Handling SGI 3
+- IRQ got SGI 3, sending hi-prio SGI 4
+> IRQ
+- IRQ Handling SGI 4
+< IRQ
+- IRQ finished sending hi-prio!
+< IRQ
+IRQ test completed OK
diff --git a/examples/mps3-an536/reference/hello-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/hello-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..3d5180e
--- /dev/null
+++ b/examples/mps3-an536/reference/hello-thumbv8r-none-eabihf.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 20,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/mps3-an536/reference/prefetch-exception-a32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/prefetch-exception-a32-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..0443a50
--- /dev/null
+++ b/examples/mps3-an536/reference/prefetch-exception-a32-thumbv8r-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0010 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0010 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/mps3-an536/reference/prefetch-exception-t32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/prefetch-exception-t32-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..94da556
--- /dev/null
+++ b/examples/mps3-an536/reference/prefetch-exception-t32-thumbv8r-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0010 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0010 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/mps3-an536/reference/registers-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/registers-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..ffd2137
--- /dev/null
+++ b/examples/mps3-an536/reference/registers-thumbv8r-none-eabihf.out
@@ -0,0 +1,39 @@
+MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xd13 rev=0x3 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
+IMP_CBAR { 0xf0000000 }
+Vbar(8000000)
+PMSA-v8 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
+Region 0: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 1: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 2: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 3: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 4: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 5: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 6: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 7: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 8: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 9: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 10: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 11: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 12: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 13: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 14: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 15: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 0: El1Region { range: 0x0..=0x3fffffff, shareability: OuterShareable, access: ReadWrite, no_exec: true, mair: 0, enable: true }
+Region 1: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 2: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 3: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 4: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 5: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 6: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 7: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 8: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 9: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 10: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 11: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 12: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 13: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 14: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+Region 15: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false }
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=1 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=1 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..7fe30b8
--- /dev/null
+++ b/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf.out
@@ -0,0 +1 @@
+CPU 1 is missing?!
diff --git a/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf_smp2.out b/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf_smp2.out
new file mode 100644
index 0000000..7fe30b8
--- /dev/null
+++ b/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf_smp2.out
@@ -0,0 +1 @@
+CPU 1 is missing?!
diff --git a/examples/mps3-an536/reference/svc-a32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/svc-a32-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..fe4deb8
--- /dev/null
+++ b/examples/mps3-an536/reference/svc-a32-thumbv8r-none-eabihf.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
diff --git a/examples/mps3-an536/reference/svc-t32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/svc-t32-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..c9edfeb
--- /dev/null
+++ b/examples/mps3-an536/reference/svc-t32-thumbv8r-none-eabihf.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
diff --git a/examples/mps3-an536/reference/undef-exception-a32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/undef-exception-a32-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/mps3-an536/reference/undef-exception-a32-thumbv8r-none-eabihf.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/mps3-an536/reference/undef-exception-t32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/undef-exception-t32-thumbv8r-none-eabihf.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/mps3-an536/reference/undef-exception-t32-thumbv8r-none-eabihf.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/mps3-an536/rust-toolchain.toml b/examples/mps3-an536/rust-toolchain.toml
index 92667db..7e4d9e6 100644
--- a/examples/mps3-an536/rust-toolchain.toml
+++ b/examples/mps3-an536/rust-toolchain.toml
@@ -1,5 +1,5 @@
 [toolchain]
-channel = "nightly-2026-01-02"
+channel = "nightly-2026-01-26"
 targets = [
 	"armv8r-none-eabihf",
 ]
diff --git a/examples/mps3-an536/src/bin/generic_timer_irq.rs b/examples/mps3-an536/src/bin/generic_timer_irq.rs
index 98cad0a..165bca1 100644
--- a/examples/mps3-an536/src/bin/generic_timer_irq.rs
+++ b/examples/mps3-an536/src/bin/generic_timer_irq.rs
@@ -44,11 +44,11 @@ fn main() -> ! {
     );
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     let mut count: u32 = 0;
     loop {
@@ -63,9 +63,9 @@ fn main() -> ! {
     }
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 #[irq]
diff --git a/examples/mps3-an536/src/bin/gic-map.rs b/examples/mps3-an536/src/bin/gic-map.rs
index 8be088c..f1caa4a 100644
--- a/examples/mps3-an536/src/bin/gic-map.rs
+++ b/examples/mps3-an536/src/bin/gic-map.rs
@@ -80,11 +80,11 @@ fn main() -> ! {
     });
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     // Send it
     println!("Send lo-prio SGI");
@@ -109,9 +109,9 @@ fn main() -> ! {
     semihosting::process::exit(0);
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 /// Handles the low-prio SGI
diff --git a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs
index e0fc815..9ea98a7 100644
--- a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs
+++ b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs
@@ -61,11 +61,11 @@ fn main() -> ! {
         .unwrap();
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     // Send it
     println!("Send lo-prio SGI");
@@ -90,9 +90,9 @@ fn main() -> ! {
     semihosting::process::exit(0);
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 // This function doesn't need to be unsafe - I'm just checking you can apply the unsafe
diff --git a/examples/mps3-an536/src/bin/gic-static-section-irq.rs b/examples/mps3-an536/src/bin/gic-static-section-irq.rs
index 18717d3..79e807c 100644
--- a/examples/mps3-an536/src/bin/gic-static-section-irq.rs
+++ b/examples/mps3-an536/src/bin/gic-static-section-irq.rs
@@ -58,11 +58,11 @@ fn main() -> ! {
         .unwrap();
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     // Send it
     println!("Send lo-prio SGI");
@@ -87,9 +87,9 @@ fn main() -> ! {
     semihosting::process::exit(0);
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 #[unsafe(link_section = ".irq_entries")]
diff --git a/examples/mps3-an536/src/bin/gic-unified-irq.rs b/examples/mps3-an536/src/bin/gic-unified-irq.rs
index 0cb00c2..844c7b6 100644
--- a/examples/mps3-an536/src/bin/gic-unified-irq.rs
+++ b/examples/mps3-an536/src/bin/gic-unified-irq.rs
@@ -58,11 +58,11 @@ fn main() -> ! {
         .unwrap();
 
     println!("Enabling interrupts...");
-    dump_cpsr();
+    dump_sctlr();
     unsafe {
         aarch32_cpu::interrupt::enable();
     }
-    dump_cpsr();
+    dump_sctlr();
 
     // Send it
     println!("Send lo-prio SGI");
@@ -87,9 +87,9 @@ fn main() -> ! {
     semihosting::process::exit(0);
 }
 
-fn dump_cpsr() {
-    let cpsr = aarch32_cpu::register::Cpsr::read();
-    println!("CPSR: {:?}", cpsr);
+fn dump_sctlr() {
+    let sctlr = aarch32_cpu::register::Sctlr::read();
+    println!("{:?}", sctlr);
 }
 
 #[irq]
diff --git a/examples/mps3-an536/src/bin/svc-a32.rs b/examples/mps3-an536/src/bin/svc-a32.rs
index cade824..d4deece 100644
--- a/examples/mps3-an536/src/bin/svc-a32.rs
+++ b/examples/mps3-an536/src/bin/svc-a32.rs
@@ -16,7 +16,7 @@ fn main() -> ! {
     let y = x + 1;
     let z = (y as f64) * 1.5;
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
-    aarch32_cpu::svc!(0xABCDEF);
+    do_svc1();
     println!("x = {}, y = {}, z = {:0.3}", x, y, z);
     semihosting::process::exit(0);
 }
@@ -27,6 +27,16 @@ fn svc_handler(arg: u32) {
     println!("In svc_handler, with arg=0x{:06x}", arg);
     if arg == 0xABCDEF {
         // test nested SVC calls
-        aarch32_cpu::svc!(0x456789);
+        do_svc2();
     }
 }
+
+#[instruction_set(arm::a32)]
+fn do_svc1() {
+    aarch32_cpu::svc!(0xABCDEF);
+}
+
+#[instruction_set(arm::a32)]
+fn do_svc2() {
+    aarch32_cpu::svc!(0x456789);
+}
diff --git a/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out
new file mode 100644
index 0000000..a41df9a
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out
new file mode 100644
index 0000000..a41df9a
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..a41df9a
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..a41df9a
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..a41df9a
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..a41df9a
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_a32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out
new file mode 100644
index 0000000..35dff8b
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out
new file mode 100644
index 0000000..35dff8b
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..35dff8b
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..35dff8b
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..35dff8b
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..35dff8b
--- /dev/null
+++ b/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is an data abort exception example
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Doing it again
+data abort occurred
+DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 }
+DFSR Status: Ok(AlignmentFault)
+caught unaligned_from_t32
+caught fault on COUNTER
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/fpu-test-armv6-none-eabi.out b/examples/versatileab/reference/fpu-test-armv6-none-eabi.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/versatileab/reference/fpu-test-armv6-none-eabi.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
+( 0.0000) ..............................o
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+Sine wave test (f64)...
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diff --git a/examples/versatileab/reference/fpu-test-armv6-none-eabihf.out b/examples/versatileab/reference/fpu-test-armv6-none-eabihf.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/versatileab/reference/fpu-test-armv6-none-eabihf.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
+( 0.0000) ..............................o
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+Sine wave test (f64)...
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diff --git a/examples/versatileab/reference/fpu-test-thumbv7a-none-eabi.out b/examples/versatileab/reference/fpu-test-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/versatileab/reference/fpu-test-thumbv7a-none-eabi.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
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+Sine wave test (f64)...
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diff --git a/examples/versatileab/reference/fpu-test-thumbv7a-none-eabihf.out b/examples/versatileab/reference/fpu-test-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/versatileab/reference/fpu-test-thumbv7a-none-eabihf.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
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diff --git a/examples/versatileab/reference/fpu-test-thumbv7r-none-eabi.out b/examples/versatileab/reference/fpu-test-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/versatileab/reference/fpu-test-thumbv7r-none-eabi.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
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+Sine wave test (f64)...
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diff --git a/examples/versatileab/reference/fpu-test-thumbv7r-none-eabihf.out b/examples/versatileab/reference/fpu-test-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..e26f6b9
--- /dev/null
+++ b/examples/versatileab/reference/fpu-test-thumbv7r-none-eabihf.out
@@ -0,0 +1,202 @@
+Sine wave test (f32)...
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diff --git a/examples/versatileab/reference/hello-armv6-none-eabi.out b/examples/versatileab/reference/hello-armv6-none-eabi.out
new file mode 100644
index 0000000..59aae22
--- /dev/null
+++ b/examples/versatileab/reference/hello-armv6-none-eabi.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 19,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/hello-armv6-none-eabihf.out b/examples/versatileab/reference/hello-armv6-none-eabihf.out
new file mode 100644
index 0000000..59aae22
--- /dev/null
+++ b/examples/versatileab/reference/hello-armv6-none-eabihf.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 19,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/hello-thumbv7a-none-eabi.out b/examples/versatileab/reference/hello-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..59aae22
--- /dev/null
+++ b/examples/versatileab/reference/hello-thumbv7a-none-eabi.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 19,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/hello-thumbv7a-none-eabihf.out b/examples/versatileab/reference/hello-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..59aae22
--- /dev/null
+++ b/examples/versatileab/reference/hello-thumbv7a-none-eabihf.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 19,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/hello-thumbv7r-none-eabi.out b/examples/versatileab/reference/hello-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..59aae22
--- /dev/null
+++ b/examples/versatileab/reference/hello-thumbv7r-none-eabi.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 19,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/hello-thumbv7r-none-eabihf.out b/examples/versatileab/reference/hello-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..59aae22
--- /dev/null
+++ b/examples/versatileab/reference/hello-thumbv7r-none-eabihf.out
@@ -0,0 +1,11 @@
+Hello, this is semihosting! x = 1.000, y = 2.000
+PANIC: PanicInfo {
+    message: I am an example panic,
+    location: Location {
+        file: "src/bin/hello.rs",
+        line: 19,
+        column: 5,
+    },
+    can_unwind: true,
+    force_no_backtrace: false,
+}
diff --git a/examples/versatileab/reference/interrupt-armv6-none-eabi.out b/examples/versatileab/reference/interrupt-armv6-none-eabi.out
new file mode 100644
index 0000000..51b9aea
--- /dev/null
+++ b/examples/versatileab/reference/interrupt-armv6-none-eabi.out
@@ -0,0 +1,15 @@
+Setting up interrupts...
+Firing interrupt...
+> interrupt_handler()
+> soft_handler1()
+> interrupt_handler()
+> soft_handler2()
+< soft_handler2()
+< interrupt_handler()
+< soft_handler1()
+< interrupt_handler()
+Got interrupted :)
+> interrupt_handler()
+catchall_handler() fired
+< interrupt_handler()
+catch all works. All done!
diff --git a/examples/versatileab/reference/interrupt-armv6-none-eabihf.out b/examples/versatileab/reference/interrupt-armv6-none-eabihf.out
new file mode 100644
index 0000000..51b9aea
--- /dev/null
+++ b/examples/versatileab/reference/interrupt-armv6-none-eabihf.out
@@ -0,0 +1,15 @@
+Setting up interrupts...
+Firing interrupt...
+> interrupt_handler()
+> soft_handler1()
+> interrupt_handler()
+> soft_handler2()
+< soft_handler2()
+< interrupt_handler()
+< soft_handler1()
+< interrupt_handler()
+Got interrupted :)
+> interrupt_handler()
+catchall_handler() fired
+< interrupt_handler()
+catch all works. All done!
diff --git a/examples/versatileab/reference/interrupt-thumbv7a-none-eabi.out b/examples/versatileab/reference/interrupt-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..51b9aea
--- /dev/null
+++ b/examples/versatileab/reference/interrupt-thumbv7a-none-eabi.out
@@ -0,0 +1,15 @@
+Setting up interrupts...
+Firing interrupt...
+> interrupt_handler()
+> soft_handler1()
+> interrupt_handler()
+> soft_handler2()
+< soft_handler2()
+< interrupt_handler()
+< soft_handler1()
+< interrupt_handler()
+Got interrupted :)
+> interrupt_handler()
+catchall_handler() fired
+< interrupt_handler()
+catch all works. All done!
diff --git a/examples/versatileab/reference/interrupt-thumbv7a-none-eabihf.out b/examples/versatileab/reference/interrupt-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..51b9aea
--- /dev/null
+++ b/examples/versatileab/reference/interrupt-thumbv7a-none-eabihf.out
@@ -0,0 +1,15 @@
+Setting up interrupts...
+Firing interrupt...
+> interrupt_handler()
+> soft_handler1()
+> interrupt_handler()
+> soft_handler2()
+< soft_handler2()
+< interrupt_handler()
+< soft_handler1()
+< interrupt_handler()
+Got interrupted :)
+> interrupt_handler()
+catchall_handler() fired
+< interrupt_handler()
+catch all works. All done!
diff --git a/examples/versatileab/reference/interrupt-thumbv7r-none-eabi.out b/examples/versatileab/reference/interrupt-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..51b9aea
--- /dev/null
+++ b/examples/versatileab/reference/interrupt-thumbv7r-none-eabi.out
@@ -0,0 +1,15 @@
+Setting up interrupts...
+Firing interrupt...
+> interrupt_handler()
+> soft_handler1()
+> interrupt_handler()
+> soft_handler2()
+< soft_handler2()
+< interrupt_handler()
+< soft_handler1()
+< interrupt_handler()
+Got interrupted :)
+> interrupt_handler()
+catchall_handler() fired
+< interrupt_handler()
+catch all works. All done!
diff --git a/examples/versatileab/reference/interrupt-thumbv7r-none-eabihf.out b/examples/versatileab/reference/interrupt-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..51b9aea
--- /dev/null
+++ b/examples/versatileab/reference/interrupt-thumbv7r-none-eabihf.out
@@ -0,0 +1,15 @@
+Setting up interrupts...
+Firing interrupt...
+> interrupt_handler()
+> soft_handler1()
+> interrupt_handler()
+> soft_handler2()
+< soft_handler2()
+< interrupt_handler()
+< soft_handler1()
+< interrupt_handler()
+Got interrupted :)
+> interrupt_handler()
+catchall_handler() fired
+< interrupt_handler()
+catch all works. All done!
diff --git a/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out
new file mode 100644
index 0000000..6d48bd3
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out
@@ -0,0 +1,10 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out
new file mode 100644
index 0000000..6d48bd3
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out
@@ -0,0 +1,10 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..1929eee
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..1929eee
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..1929eee
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..1929eee
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out
new file mode 100644
index 0000000..6d48bd3
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out
@@ -0,0 +1,10 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out
new file mode 100644
index 0000000..6d48bd3
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out
@@ -0,0 +1,10 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..2b5664f
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..2b5664f
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..2b5664f
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabi.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..2b5664f
--- /dev/null
+++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabihf.out
@@ -0,0 +1,14 @@
+Hello, this is a prefetch abort exception example
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Doing it again
+prefetch abort occurred
+IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 }
+IFSR Status: Ok(DebugEvent)
+IFAR (Faulting Address Register): Ifar(0)
+caught bkpt_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/registers-armv6-none-eabi.out b/examples/versatileab/reference/registers-armv6-none-eabi.out
new file mode 100644
index 0000000..f24dd0c
--- /dev/null
+++ b/examples/versatileab/reference/registers-armv6-none-eabi.out
@@ -0,0 +1,5 @@
+MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xb76 rev=0x7 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
+Mpidr(410fb767)
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/registers-armv6-none-eabihf.out b/examples/versatileab/reference/registers-armv6-none-eabihf.out
new file mode 100644
index 0000000..f24dd0c
--- /dev/null
+++ b/examples/versatileab/reference/registers-armv6-none-eabihf.out
@@ -0,0 +1,5 @@
+MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xb76 rev=0x7 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
+Mpidr(410fb767)
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/registers-thumbv7a-none-eabi.out b/examples/versatileab/reference/registers-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..27fdee0
--- /dev/null
+++ b/examples/versatileab/reference/registers-thumbv7a-none-eabi.out
@@ -0,0 +1,5 @@
+MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xc08 rev=0x0 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
+Mpidr(0)
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/registers-thumbv7a-none-eabihf.out b/examples/versatileab/reference/registers-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..27fdee0
--- /dev/null
+++ b/examples/versatileab/reference/registers-thumbv7a-none-eabihf.out
@@ -0,0 +1,5 @@
+MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xc08 rev=0x0 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
+Mpidr(0)
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
diff --git a/examples/versatileab/reference/registers-thumbv7r-none-eabi.out b/examples/versatileab/reference/registers-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..6d58047
--- /dev/null
+++ b/examples/versatileab/reference/registers-thumbv7r-none-eabi.out
@@ -0,0 +1,38 @@
+MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
+Mpidr(c0000000)
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
+PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
+DRegion 0: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out b/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..6d58047
--- /dev/null
+++ b/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out
@@ -0,0 +1,38 @@
+MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 }
+CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) }
+Mpidr(c0000000)
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z
+SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after
+PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false }
+DRegion 0: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
+DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/reference/svc-a32-armv6-none-eabi.out b/examples/versatileab/reference/svc-a32-armv6-none-eabi.out
new file mode 100644
index 0000000..fe4deb8
--- /dev/null
+++ b/examples/versatileab/reference/svc-a32-armv6-none-eabi.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out b/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out
new file mode 100644
index 0000000..fe4deb8
--- /dev/null
+++ b/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-a32-thumbv7a-none-eabi.out b/examples/versatileab/reference/svc-a32-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..fe4deb8
--- /dev/null
+++ b/examples/versatileab/reference/svc-a32-thumbv7a-none-eabi.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-a32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/svc-a32-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..fe4deb8
--- /dev/null
+++ b/examples/versatileab/reference/svc-a32-thumbv7a-none-eabihf.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-a32-thumbv7r-none-eabi.out b/examples/versatileab/reference/svc-a32-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..fe4deb8
--- /dev/null
+++ b/examples/versatileab/reference/svc-a32-thumbv7r-none-eabi.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-a32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/svc-a32-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..fe4deb8
--- /dev/null
+++ b/examples/versatileab/reference/svc-a32-thumbv7r-none-eabihf.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0xabcdef
+In svc_handler, with arg=0x456789
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-t32-armv6-none-eabi.out b/examples/versatileab/reference/svc-t32-armv6-none-eabi.out
new file mode 100644
index 0000000..c9edfeb
--- /dev/null
+++ b/examples/versatileab/reference/svc-t32-armv6-none-eabi.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out b/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out
new file mode 100644
index 0000000..c9edfeb
--- /dev/null
+++ b/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-t32-thumbv7a-none-eabi.out b/examples/versatileab/reference/svc-t32-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..c9edfeb
--- /dev/null
+++ b/examples/versatileab/reference/svc-t32-thumbv7a-none-eabi.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-t32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/svc-t32-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..c9edfeb
--- /dev/null
+++ b/examples/versatileab/reference/svc-t32-thumbv7a-none-eabihf.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-t32-thumbv7r-none-eabi.out b/examples/versatileab/reference/svc-t32-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..c9edfeb
--- /dev/null
+++ b/examples/versatileab/reference/svc-t32-thumbv7r-none-eabi.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/svc-t32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/svc-t32-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..c9edfeb
--- /dev/null
+++ b/examples/versatileab/reference/svc-t32-thumbv7r-none-eabihf.out
@@ -0,0 +1,4 @@
+x = 1, y = 2, z = 3.000
+In svc_handler, with arg=0x000012
+In svc_handler, with arg=0x000034
+x = 1, y = 2, z = 3.000
diff --git a/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabihf.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..dbafb84
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabihf.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_a32
+Doing it again
+undefined abort occurred
+caught udf_from_a32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabi.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabihf.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabihf.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabi.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabi.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabihf.out
new file mode 100644
index 0000000..083a29c
--- /dev/null
+++ b/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabihf.out
@@ -0,0 +1,8 @@
+Hello, this is a undef exception example
+undefined abort occurred
+caught udf_from_t32
+Doing it again
+undefined abort occurred
+caught udf_from_t32
+Skipping instruction
+Recovered from fault OK!
diff --git a/examples/versatileab/rust-toolchain.toml b/examples/versatileab/rust-toolchain.toml
index cf1e917..1373346 100644
--- a/examples/versatileab/rust-toolchain.toml
+++ b/examples/versatileab/rust-toolchain.toml
@@ -1,5 +1,5 @@
 [toolchain]
-channel = "nightly-2026-01-02"
+channel = "nightly-2026-01-26"
 targets = [
 	"armv7r-none-eabi",
 	"armv7r-none-eabihf",
diff --git a/examples/versatileab/src/bin/prefetch-exception-a32.rs b/examples/versatileab/src/bin/prefetch-exception-a32.rs
index 0dd67aa..b1c913a 100644
--- a/examples/versatileab/src/bin/prefetch-exception-a32.rs
+++ b/examples/versatileab/src/bin/prefetch-exception-a32.rs
@@ -63,7 +63,8 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize {
 
     if cfg!(not(any(
         arm_architecture = "v4t",
-        arm_architecture = "v5te"
+        arm_architecture = "v5te",
+        arm_architecture = "v6"
     ))) {
         let ifar = Ifar::read();
         println!("IFAR (Faulting Address Register): {:?}", ifar);
diff --git a/examples/versatileab/src/bin/prefetch-exception-t32.rs b/examples/versatileab/src/bin/prefetch-exception-t32.rs
index ab9631c..996b5f9 100644
--- a/examples/versatileab/src/bin/prefetch-exception-t32.rs
+++ b/examples/versatileab/src/bin/prefetch-exception-t32.rs
@@ -63,7 +63,8 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize {
 
     if cfg!(not(any(
         arm_architecture = "v4t",
-        arm_architecture = "v5te"
+        arm_architecture = "v5te",
+        arm_architecture = "v6"
     ))) {
         let ifar = Ifar::read();
         println!("IFAR (Faulting Address Register): {:?}", ifar);
diff --git a/justfile b/justfile
index 52e7f3c..f25f54a 100644
--- a/justfile
+++ b/justfile
@@ -34,21 +34,35 @@ build-all: \
 	(build-tier3-no-atomics "thumbv4t-none-eabi") \
 	(build-tier3-no-atomics "armv5te-none-eabi") \
 	(build-tier3-no-atomics "thumbv5te-none-eabi") \
+	(build-tier3-no-atomics "armv6-none-eabi") \
+	(build-tier3-no-atomics "thumbv6-none-eabi") \
+	(build-tier3-no-atomics "armv6-none-eabihf") \
 	(build-tier2 "armv7r-none-eabi") \
+	(build-tier3 "thumbv7r-none-eabi") \
 	(build-tier2 "armv7r-none-eabihf") \
+	(build-tier3 "thumbv7r-none-eabihf") \
 	(build-tier2 "armv7a-none-eabi") \
+	(build-tier3 "thumbv7a-none-eabi") \
 	(build-tier2 "armv7a-none-eabihf") \
+	(build-tier3 "thumbv7a-none-eabihf") \
 	(build-tier2 "armv8r-none-eabihf") \
+	(build-tier3 "thumbv8r-none-eabihf") \
 
 # Build the arm-targets library
 build-arm-targets:
 		cd arm-targets && cargo build {{verbose}}
 
-# Builds our workspace with various features, building core from source
+# Builds our workspace with various features, building core from source, but skipping anything that requires atomics
 build-tier3-no-atomics target:
     cargo build --target {{target}} -Zbuild-std=core {{verbose}}
     cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-single-core, check-asm" {{verbose}}
 
+# Builds our workspace with various features, building core from source
+build-tier3 target:
+    cargo build --target {{target}} -Zbuild-std=core {{verbose}}
+    cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-multi-core, check-asm" {{verbose}}
+    cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-single-core, check-asm" {{verbose}}
+
 # Builds our workspace with various features
 build-tier2 target:
     cargo build --target {{target}} {{verbose}}
@@ -61,11 +75,19 @@ build-all-examples: \
 	(build-versatileab-tier3 "thumbv4t-none-eabi") \
 	(build-versatileab-tier3 "armv5te-none-eabi") \
 	(build-versatileab-tier3 "thumbv5te-none-eabi") \
+	(build-versatileab-tier3 "armv6-none-eabi") \
+	(build-versatileab-tier3 "armv6-none-eabihf") \
 	(build-versatileab-tier2 "armv7r-none-eabi") \
+	(build-versatileab-tier3 "thumbv7r-none-eabi") \
 	(build-versatileab-tier2 "armv7r-none-eabihf") \
+	(build-versatileab-tier3 "thumbv7r-none-eabihf") \
 	(build-versatileab-tier2 "armv7a-none-eabi") \
+	(build-versatileab-tier3 "thumbv7a-none-eabi") \
 	(build-versatileab-tier2 "armv7a-none-eabihf") \
+	(build-versatileab-tier3 "thumbv7a-none-eabihf") \
 	(build-mps3-tier2 "armv8r-none-eabihf") \
+	(build-mps3-tier3 "thumbv8r-none-eabihf") \
+	# (build-versatileab-tier3 "thumbv6-none-eabi") \
 
 # Builds the Versatile AB examples, building core from source
 build-versatileab-tier3 target:
@@ -75,6 +97,10 @@ build-versatileab-tier3 target:
 build-versatileab-tier2 target:
 	cd examples/versatileab && cargo build --target={{target}} {{verbose}}
 
+# Builds the MPS3-AN536 examples, building core from source
+build-mps3-tier3 target:
+	cd examples/mps3-an536 && cargo build --target={{target}} -Zbuild-std=core {{verbose}}
+
 # Builds the MPS3-AN536 examples, assuming core has been prebuilt
 build-mps3-tier2 target:
 	cd examples/mps3-an536 && cargo build --target={{target}} {{verbose}}
@@ -141,13 +167,23 @@ test-qemu:
 	./tests.sh examples/versatileab thumbv4t-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1
 	./tests.sh examples/versatileab armv5te-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1
 	./tests.sh examples/versatileab thumbv5te-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1
+	./tests.sh examples/versatileab armv6-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1
+	./tests.sh examples/versatileab armv6-none-eabihf -Zbuild-std=core {{verbose}} || FAIL=1
+	# ./tests.sh examples/versatileab thumbv6-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1
 	./tests.sh examples/versatileab armv7r-none-eabi {{verbose}} || FAIL=1
+	./tests.sh examples/versatileab thumbv7r-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1
 	./tests.sh examples/versatileab armv7r-none-eabihf {{verbose}} || FAIL=1
+	./tests.sh examples/versatileab thumbv7r-none-eabihf -Zbuild-std=core {{verbose}} || FAIL=1
 	./tests.sh examples/versatileab armv7a-none-eabi {{verbose}} || FAIL=1
+	./tests.sh examples/versatileab thumbv7a-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1
 	./tests.sh examples/versatileab armv7a-none-eabihf {{verbose}} || FAIL=1
+	./tests.sh examples/versatileab thumbv7a-none-eabihf -Zbuild-std=core {{verbose}} || FAIL=1
 	RUSTFLAGS=-Ctarget-feature=+d32 ./tests.sh examples/versatileab armv7a-none-eabihf --features=fpu-d32 --target-dir=target-d32 {{verbose}} || FAIL=1
+	RUSTFLAGS=-Ctarget-feature=+d32 ./tests.sh examples/versatileab thumbv7a-none-eabihf -Zbuild-std=core --features=fpu-d32 --target-dir=target-d32 {{verbose}} || FAIL=1
 	./tests.sh examples/mps3-an536 armv8r-none-eabihf {{verbose}} || FAIL=1
+	./tests.sh examples/mps3-an536 thumbv8r-none-eabihf -Zbuild-std=core {{verbose}} || FAIL=1
 	RUSTFLAGS=-Ctarget-cpu=cortex-r52 ./tests.sh examples/mps3-an536 armv8r-none-eabihf --features=fpu-d32 --target-dir=target-d32 {{verbose}} || FAIL=1
+	RUSTFLAGS=-Ctarget-cpu=cortex-r52 ./tests.sh examples/mps3-an536 thumbv8r-none-eabihf -Zbuild-std=core --features=fpu-d32 --target-dir=target-d32 {{verbose}} || FAIL=1
 	if [ "${FAIL}" == "1" ]; then exit 1; fi
 
 # Run the special SMP test