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Add a syscall mechanism #108

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dda62b3
Support thumb-mode Armv7-R, Armv7-A and Armv8-R
thejpster Dec 31, 2025
a87904c
Ignore .DS_Store files
thejpster Jan 1, 2026
87d1971
Don't rely on CPSR contents.
thejpster Jan 2, 2026
edecf04
Need updated nightly for the examples.
thejpster Jan 25, 2026
71bf032
Fixup the new output files.
thejpster Jan 25, 2026
3a7e27b
Rationalise the directive order for inline asm.
thejpster Feb 1, 2026
af1919a
Adds support for ARMv6 targets.
thejpster Dec 18, 2025
f357f1d
Bump the toolchain to pick up Armv6 targets.
jonathanpallant Jan 26, 2026
7052b2a
Provide r0-r3 to SVC exception handler, for implementing syscalls.
thejpster Jan 30, 2026
fc4b29c
Add syscall examples.
thejpster Jan 30, 2026
80a02c0
Fix tests.sh so it copies over output files even if the file doesn't …
thejpster Jan 30, 2026
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31 changes: 29 additions & 2 deletions .cargo/config.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -2,27 +2,54 @@
# Note, this requires QEMU 9 or higher
runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"

[target.thumbv8r-none-eabihf]
# Note, this requires QEMU 9 or higher
runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"

[target.armv7r-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"

[target.thumbv7r-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"

[target.armv7r-none-eabi]
# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
# qemu-system-arm will lock up
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"

[target.thumbv7r-none-eabi]
# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
# qemu-system-arm will lock up
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"

[target.armv7a-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.thumbv7a-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.armv7a-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.thumbv7a-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.armv6-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"

[target.armv6-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"

[target.thumbv6-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"

[target.armv5te-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.armv4t-none-eabi]
[target.thumbv5te-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.thumbv5te-none-eabi]
[target.armv4t-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.thumbv4t-none-eabi]
Expand Down
37 changes: 32 additions & 5 deletions .github/workflows/build.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,34 @@ jobs:
run: |
just build-tier2 ${{ matrix.target }}

# These targets need build-std, and have no atomics
# These targets need build-std
build-tier3:
runs-on: ubuntu-24.04
needs: setup
strategy:
matrix:
target:
- thumbv7r-none-eabi
- thumbv7r-none-eabihf
- thumbv7a-none-eabi
- thumbv7a-none-eabihf
- thumbv8r-none-eabihf
steps:
- name: Checkout
uses: actions/checkout@v4
- name: Install Just
uses: taiki-e/install-action@just
- name: Install Rust
run: |
rustup install nightly-2026-01-26
rustup component add rust-src --toolchain nightly-2026-01-26
rustup default nightly-2026-01-26
- name: Build
run: |
just build-tier3 ${{ matrix.target }}

# These targets need build-std, and have no atomics so we have to skip
# the 'critical-section-multi-core' feature
build-tier3-no-atomics:
runs-on: ubuntu-24.04
needs: setup
Expand All @@ -62,9 +89,9 @@ jobs:
uses: taiki-e/install-action@just
- name: Install Rust
run: |
rustup install nightly-2025-10-29
rustup component add rust-src --toolchain nightly-2025-10-29
rustup default nightly-2025-10-29
rustup install nightly-2026-01-26
rustup component add rust-src --toolchain nightly-2026-01-26
rustup default nightly-2026-01-26
- name: Build
run: |
just build-tier3-no-atomics ${{ matrix.target }}
Expand Down Expand Up @@ -92,7 +119,7 @@ jobs:
# Gather all the above build jobs together for the purposes of getting an overall pass-fail
build-all:
runs-on: ubuntu-24.04
needs: [build-tier2, build-tier3-no-atomics, build-arm-targets]
needs: [build-tier2, build-tier3-no-atomics, build-tier3, build-arm-targets]
steps:
- run: /bin/true

Expand Down
2 changes: 2 additions & 0 deletions .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -4,3 +4,5 @@ examples/mps3-an536/target-d32
examples/versatileab/target
examples/versatileab/target-d32
Cargo.lock
**/.DS_Store

80 changes: 76 additions & 4 deletions aarch32-cpu/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -37,13 +37,85 @@ pub mod pmsav8;

/// Generate an SVC call with the given argument.
///
/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your Svc handler
/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler
/// saves and restores SPSR_svc correctly.
#[macro_export]
macro_rules! svc {
($r0:expr) => {
($num:expr) => { {
let retval: u32;
unsafe {
core::arch::asm!("svc {arg}", arg = const $r0, out("lr") _);
core::arch::asm!("svc {arg}", arg = const $num, lateout("r0") retval, out("lr") _);
}
}
retval
} }
}

/// Generate an SVC call with the given argument, plus setup r0 with the given value
///
/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler
/// saves and restores SPSR_svc correctly.
#[macro_export]
macro_rules! svc1 {
($num:expr, $arg0:expr) => { {
let retval: u32;
let arg0: u32 = $arg0;
unsafe {
core::arch::asm!("svc {arg}", arg = const $num, inout("r0") arg0 => retval, out("lr") _);
}
retval
} }
}

/// Generate an SVC call with the given argument, plus setup r0-r1 with the given values
///
/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler
/// saves and restores SPSR_svc correctly.
#[macro_export]
macro_rules! svc2 {
($num:expr, $arg0:expr, $arg1:expr) => { {
let retval: u32;
let arg0: u32 = $arg0;
let arg1: u32 = $arg1;
unsafe {
core::arch::asm!("svc {arg}", arg = const $num, inout("r0") arg0 => retval, in("r1") arg1, out("lr") _);
}
retval
} }
}

/// Generate an SVC call with the given argument, plus setup r0-r2 with the given values
///
/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler
/// saves and restores SPSR_svc correctly.
#[macro_export]
macro_rules! svc3 {
($num:expr, $arg0:expr, $arg1:expr, $arg2:expr) => { {
let retval: u32;
let arg0: u32 = $arg0;
let arg1: u32 = $arg1;
let arg2: u32 = $arg2;
unsafe {
core::arch::asm!("svc {arg}", arg = const $num, inout("r0") arg0 => retval, in("r1") arg1, in("r2") arg2, out("lr") _);
}
retval
} }
}

/// Generate an SVC call with the given argument, plus setup r0-r3 with the given values
///
/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler
/// saves and restores SPSR_svc correctly.
#[macro_export]
macro_rules! svc4 {
($num:expr, $arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr) => { {
let retval: u32;
let arg0: u32 = $arg0;
let arg1: u32 = $arg1;
let arg2: u32 = $arg2;
let arg3: u32 = $arg3;
unsafe {
core::arch::asm!("svc {arg}", arg = const $num, inout("r0") arg0 => retval, in("r1") arg1, in("r2") arg2, in("r3") arg3, out("lr") _);
}
retval
} }
}
12 changes: 10 additions & 2 deletions aarch32-cpu/src/register/cpsr.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,11 @@ impl Cpsr {
/// `thumb*` targets, as Thumb-1 cannot do an MRS.
#[cfg_attr(not(feature = "check-asm"), inline)]
#[cfg_attr(
any(arm_architecture = "v4t", arm_architecture = "v5te"),
any(
arm_architecture = "v4t",
arm_architecture = "v5te",
arm_architecture = "v6"
),
instruction_set(arm::a32)
)]
pub fn read() -> Self {
Expand Down Expand Up @@ -108,7 +112,11 @@ impl Cpsr {
/// `thumb*` targets, as Thumb-1 cannot do an MSR.
#[cfg_attr(not(feature = "check-asm"), inline)]
#[cfg_attr(
any(arm_architecture = "v4t", arm_architecture = "v5te"),
any(
arm_architecture = "v4t",
arm_architecture = "v5te",
arm_architecture = "v6"
),
instruction_set(arm::a32)
)]
pub unsafe fn write(_value: Self) {
Expand Down
12 changes: 10 additions & 2 deletions aarch32-cpu/src/register/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -225,7 +225,11 @@ pub trait SysRegRead: SysReg {
/// may have side-effects.
#[cfg_attr(not(feature = "check-asm"), inline)]
#[cfg_attr(
any(arm_architecture = "v4t", arm_architecture = "v5te"),
any(
arm_architecture = "v4t",
arm_architecture = "v5te",
arm_architecture = "v6"
),
instruction_set(arm::a32)
)]
unsafe fn read_raw() -> u32 {
Expand Down Expand Up @@ -261,7 +265,11 @@ pub trait SysRegWrite: SysReg {
/// writing valid data here.
#[cfg_attr(not(feature = "check-asm"), inline)]
#[cfg_attr(
any(arm_architecture = "v4t", arm_architecture = "v5te"),
any(
arm_architecture = "v4t",
arm_architecture = "v5te",
arm_architecture = "v6"
),
instruction_set(arm::a32)
)]
unsafe fn write_raw(_value: u32) {
Expand Down
11 changes: 7 additions & 4 deletions aarch32-rt-macros/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -301,7 +301,8 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
VectorKind::Interrupt => Exception::Irq,
};

let block = f.block;
let func_name = f.sig.ident.clone();
let block = f.block.clone();
let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone());

let handler = match exception {
Expand Down Expand Up @@ -387,16 +388,18 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
)
}
}
// extern "C" fn _svc_handler(addr: usize);
// extern "C" fn _svc_handler(arg: u32, args: &Frame) -> u32
Exception::SupervisorCall => {
let tramp_ident = Ident::new("__aarch32_rt_svc_handler", Span::call_site());
quote!(
#(#cfgs)*
#(#attrs)*
#[doc(hidden)]
#[export_name = "_svc_handler"]
pub unsafe extern "C" fn #tramp_ident(arg: u32) {
#block
pub unsafe extern "C" fn #tramp_ident(arg: u32, frame: &aarch32_rt::Frame) -> u32 {
#f

#func_name(arg, frame)
}
)
}
Expand Down
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