diff --git a/.cargo/config.toml b/.cargo/config.toml index 1d43fc3..d4d345e 100644 --- a/.cargo/config.toml +++ b/.cargo/config.toml @@ -2,27 +2,54 @@ # Note, this requires QEMU 9 or higher runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel" +[target.thumbv8r-none-eabihf] +# Note, this requires QEMU 9 or higher +runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel" + [target.armv7r-none-eabihf] runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel" +[target.thumbv7r-none-eabihf] +runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel" + [target.armv7r-none-eabi] # change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise # qemu-system-arm will lock up runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel" +[target.thumbv7r-none-eabi] +# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise +# qemu-system-arm will lock up +runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel" + [target.armv7a-none-eabihf] runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel" +[target.thumbv7a-none-eabihf] +runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel" + [target.armv7a-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel" +[target.thumbv7a-none-eabi] +runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel" + +[target.armv6-none-eabihf] +runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel" + +[target.armv6-none-eabi] +runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel" + +[target.thumbv6-none-eabi] +runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel" + [target.armv5te-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel" -[target.armv4t-none-eabi] +[target.thumbv5te-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel" -[target.thumbv5te-none-eabi] +[target.armv4t-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel" [target.thumbv4t-none-eabi] diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index ba71484..69a2c2a 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -44,7 +44,34 @@ jobs: run: | just build-tier2 ${{ matrix.target }} - # These targets need build-std, and have no atomics + # These targets need build-std + build-tier3: + runs-on: ubuntu-24.04 + needs: setup + strategy: + matrix: + target: + - thumbv7r-none-eabi + - thumbv7r-none-eabihf + - thumbv7a-none-eabi + - thumbv7a-none-eabihf + - thumbv8r-none-eabihf + steps: + - name: Checkout + uses: actions/checkout@v4 + - name: Install Just + uses: taiki-e/install-action@just + - name: Install Rust + run: | + rustup install nightly-2026-01-26 + rustup component add rust-src --toolchain nightly-2026-01-26 + rustup default nightly-2026-01-26 + - name: Build + run: | + just build-tier3 ${{ matrix.target }} + + # These targets need build-std, and have no atomics so we have to skip + # the 'critical-section-multi-core' feature build-tier3-no-atomics: runs-on: ubuntu-24.04 needs: setup @@ -62,9 +89,9 @@ jobs: uses: taiki-e/install-action@just - name: Install Rust run: | - rustup install nightly-2025-10-29 - rustup component add rust-src --toolchain nightly-2025-10-29 - rustup default nightly-2025-10-29 + rustup install nightly-2026-01-26 + rustup component add rust-src --toolchain nightly-2026-01-26 + rustup default nightly-2026-01-26 - name: Build run: | just build-tier3-no-atomics ${{ matrix.target }} @@ -92,7 +119,7 @@ jobs: # Gather all the above build jobs together for the purposes of getting an overall pass-fail build-all: runs-on: ubuntu-24.04 - needs: [build-tier2, build-tier3-no-atomics, build-arm-targets] + needs: [build-tier2, build-tier3-no-atomics, build-tier3, build-arm-targets] steps: - run: /bin/true diff --git a/.gitignore b/.gitignore index 75337a3..a139b23 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,5 @@ examples/mps3-an536/target-d32 examples/versatileab/target examples/versatileab/target-d32 Cargo.lock +**/.DS_Store + diff --git a/aarch32-cpu/src/lib.rs b/aarch32-cpu/src/lib.rs index 2ffdb32..27c2510 100644 --- a/aarch32-cpu/src/lib.rs +++ b/aarch32-cpu/src/lib.rs @@ -37,13 +37,85 @@ pub mod pmsav8; /// Generate an SVC call with the given argument. /// -/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your Svc handler +/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler /// saves and restores SPSR_svc correctly. #[macro_export] macro_rules! svc { - ($r0:expr) => { + ($num:expr) => { { + let retval: u32; unsafe { - core::arch::asm!("svc {arg}", arg = const $r0, out("lr") _); + core::arch::asm!("svc {arg}", arg = const $num, lateout("r0") retval, out("lr") _); } - } + retval + } } +} + +/// Generate an SVC call with the given argument, plus setup r0 with the given value +/// +/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler +/// saves and restores SPSR_svc correctly. +#[macro_export] +macro_rules! svc1 { + ($num:expr, $arg0:expr) => { { + let retval: u32; + let arg0: u32 = $arg0; + unsafe { + core::arch::asm!("svc {arg}", arg = const $num, inout("r0") arg0 => retval, out("lr") _); + } + retval + } } +} + +/// Generate an SVC call with the given argument, plus setup r0-r1 with the given values +/// +/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler +/// saves and restores SPSR_svc correctly. +#[macro_export] +macro_rules! svc2 { + ($num:expr, $arg0:expr, $arg1:expr) => { { + let retval: u32; + let arg0: u32 = $arg0; + let arg1: u32 = $arg1; + unsafe { + core::arch::asm!("svc {arg}", arg = const $num, inout("r0") arg0 => retval, in("r1") arg1, out("lr") _); + } + retval + } } +} + +/// Generate an SVC call with the given argument, plus setup r0-r2 with the given values +/// +/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler +/// saves and restores SPSR_svc correctly. +#[macro_export] +macro_rules! svc3 { + ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr) => { { + let retval: u32; + let arg0: u32 = $arg0; + let arg1: u32 = $arg1; + let arg2: u32 = $arg2; + unsafe { + core::arch::asm!("svc {arg}", arg = const $num, inout("r0") arg0 => retval, in("r1") arg1, in("r2") arg2, out("lr") _); + } + retval + } } +} + +/// Generate an SVC call with the given argument, plus setup r0-r3 with the given values +/// +/// Safe to call even in Supervisor (SupervisorCall) mode, as long as your SVC handler +/// saves and restores SPSR_svc correctly. +#[macro_export] +macro_rules! svc4 { + ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr) => { { + let retval: u32; + let arg0: u32 = $arg0; + let arg1: u32 = $arg1; + let arg2: u32 = $arg2; + let arg3: u32 = $arg3; + unsafe { + core::arch::asm!("svc {arg}", arg = const $num, inout("r0") arg0 => retval, in("r1") arg1, in("r2") arg2, in("r3") arg3, out("lr") _); + } + retval + } } } diff --git a/aarch32-cpu/src/register/cpsr.rs b/aarch32-cpu/src/register/cpsr.rs index 8fab4af..718f0e3 100644 --- a/aarch32-cpu/src/register/cpsr.rs +++ b/aarch32-cpu/src/register/cpsr.rs @@ -75,7 +75,11 @@ impl Cpsr { /// `thumb*` targets, as Thumb-1 cannot do an MRS. #[cfg_attr(not(feature = "check-asm"), inline)] #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] pub fn read() -> Self { @@ -108,7 +112,11 @@ impl Cpsr { /// `thumb*` targets, as Thumb-1 cannot do an MSR. #[cfg_attr(not(feature = "check-asm"), inline)] #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] pub unsafe fn write(_value: Self) { diff --git a/aarch32-cpu/src/register/mod.rs b/aarch32-cpu/src/register/mod.rs index 7dac1a3..f8ba885 100644 --- a/aarch32-cpu/src/register/mod.rs +++ b/aarch32-cpu/src/register/mod.rs @@ -225,7 +225,11 @@ pub trait SysRegRead: SysReg { /// may have side-effects. #[cfg_attr(not(feature = "check-asm"), inline)] #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] unsafe fn read_raw() -> u32 { @@ -261,7 +265,11 @@ pub trait SysRegWrite: SysReg { /// writing valid data here. #[cfg_attr(not(feature = "check-asm"), inline)] #[cfg_attr( - any(arm_architecture = "v4t", arm_architecture = "v5te"), + any( + arm_architecture = "v4t", + arm_architecture = "v5te", + arm_architecture = "v6" + ), instruction_set(arm::a32) )] unsafe fn write_raw(_value: u32) { diff --git a/aarch32-rt-macros/src/lib.rs b/aarch32-rt-macros/src/lib.rs index 4feb8ef..cef6030 100644 --- a/aarch32-rt-macros/src/lib.rs +++ b/aarch32-rt-macros/src/lib.rs @@ -301,7 +301,8 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok VectorKind::Interrupt => Exception::Irq, }; - let block = f.block; + let func_name = f.sig.ident.clone(); + let block = f.block.clone(); let (ref cfgs, ref attrs) = extract_cfgs(f.attrs.clone()); let handler = match exception { @@ -387,7 +388,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok ) } } - // extern "C" fn _svc_handler(addr: usize); + // extern "C" fn _svc_handler(arg: u32, args: &Frame) -> u32 Exception::SupervisorCall => { let tramp_ident = Ident::new("__aarch32_rt_svc_handler", Span::call_site()); quote!( @@ -395,8 +396,10 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok #(#attrs)* #[doc(hidden)] #[export_name = "_svc_handler"] - pub unsafe extern "C" fn #tramp_ident(arg: u32) { - #block + pub unsafe extern "C" fn #tramp_ident(arg: u32, frame: &aarch32_rt::Frame) -> u32 { + #f + + #func_name(arg, frame) } ) } diff --git a/aarch32-rt/src/arch_v4/abort.rs b/aarch32-rt/src/arch_v4/abort.rs index bca1038..f740b20 100644 --- a/aarch32-rt/src/arch_v4/abort.rs +++ b/aarch32-rt/src/arch_v4/abort.rs @@ -5,72 +5,79 @@ core::arch::global_asm!( // Work around https://github.com/rust-lang/rust/issues/127269 .fpu vfp2 - .section .text._asm_default_data_abort_handler // Called from the vector table when we have an undefined exception. // Saves state and calls a C-compatible handler like // `extern "C" fn _data_abort_handler(addr: usize);` - .global _asm_default_data_abort_handler + .section .text._asm_default_data_abort_handler .arm + .global _asm_default_data_abort_handler .type _asm_default_data_abort_handler, %function _asm_default_data_abort_handler: - // Subtract 8 from the stored LR, see p.1214 of the ARMv7-A architecture manual. - subs lr, lr, #8 - // state save from compiled code - stmfd sp!, {{ r0 }} - mrs r0, spsr - stmfd sp!, {{ r0 }} + sub lr, lr, #8 // Subtract 8 from LR, see p.1214 of the ARMv7-A architecture manual. + push {{ r12 }} // Save preserved register R12 - can now use it + mrs r12, spsr // grab SPSR + push {{ r12 }} // save SPSR value + mov r12, sp // align SP down to eight byte boundary using R12 + and r12, r12, 7 // + sub sp, r12 // SP now aligned - only push 64-bit values from here + push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding) "#, - crate::save_context!(), + crate::save_fpu_context!(), r#" - // Pass the faulting instruction address to the handler. - mov r0, lr - // call C handler - bl _data_abort_handler - // if we get back here, assume they returned a new LR in r0 - mov lr, r0 + mov r0, lr // Pass the faulting instruction address to the handler. + bl _data_abort_handler // call C handler + mov lr, r0 // if we get back here, assume they returned a new LR in r0 "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // Return from the asm handler - ldmia sp!, {{ r0 }} - msr spsr, r0 - ldmia sp!, {{ r0 }} - movs pc, lr + pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount + add sp, r12 // restore SP alignment using R12 + pop {{ r12 }} // restore SPSR using R12 + msr spsr_cxsf, r12 // + pop {{ r12 }} // restore R12 + movs pc, lr // return from exception .size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler + "# +); + +core::arch::global_asm!( + r#" + // Work around https://github.com/rust-lang/rust/issues/127269 + .fpu vfp2 - .section .text._asm_default_prefetch_abort_handler // Called from the vector table when we have a prefetch abort. // Saves state and calls a C-compatible handler like // `extern "C" fn _prefetch_abort_handler(addr: usize);` - .global _asm_default_prefetch_abort_handler + .section .text._asm_default_prefetch_abort_handler .arm + .global _asm_default_prefetch_abort_handler .type _asm_default_prefetch_abort_handler, %function _asm_default_prefetch_abort_handler: - // Subtract 4 from the stored LR, see p.1212 of the ARMv7-A architecture manual. - subs lr, lr, #4 - // state save from compiled code - stmfd sp!, {{ r0 }} - mrs r0, spsr - stmfd sp!, {{ r0 }} + sub lr, lr, #4 // Subtract 4 from LR, see p.1212 of the ARMv7-A architecture manual. + push {{ r12 }} // Save preserved register R12 - can now use it + mrs r12, spsr // grab SPSR + push {{ r12 }} // save SPSR value + mov r12, sp // align SP down to eight byte boundary using R12 + and r12, r12, 7 // + sub sp, r12 // SP now aligned - only push 64-bit values from here + push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding) "#, - crate::save_context!(), + crate::save_fpu_context!(), r#" - // Pass the faulting instruction address to the handler. - mov r0, lr - // call C handler - bl _prefetch_abort_handler - // if we get back here, assume they returned a new LR in r0 - mov lr, r0 + mov r0, lr // Pass the faulting instruction address to the handler. + bl _prefetch_abort_handler // call C handler + mov lr, r0 // if we get back here, assume they returned a new LR in r0 "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // Return from the asm handler - ldmia sp!, {{ r0 }} - msr spsr, r0 - ldmia sp!, {{ r0 }} - movs pc, lr + pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount + add sp, r12 // restore SP alignment using R12 + pop {{ r12 }} // restore SPSR using R12 + msr spsr_cxsf, r12 // + pop {{ r12 }} // restore R12 + movs pc, lr // return from exception .size _asm_default_prefetch_abort_handler, . - _asm_default_prefetch_abort_handler "#, ); diff --git a/aarch32-rt/src/arch_v4/interrupt.rs b/aarch32-rt/src/arch_v4/interrupt.rs index 3a9a19d..5a2c344 100644 --- a/aarch32-rt/src/arch_v4/interrupt.rs +++ b/aarch32-rt/src/arch_v4/interrupt.rs @@ -8,42 +8,36 @@ core::arch::global_asm!( // Work around https://github.com/rust-lang/rust/issues/127269 .fpu vfp2 - .section .text._asm_default_irq_handler - // Called from the vector table when we have an interrupt. // Saves state and calls a C-compatible handler like // `extern "C" fn _irq_handler();` - .global _asm_default_irq_handler + .section .text._asm_default_irq_handler .arm + .global _asm_default_irq_handler .type _asm_default_irq_handler, %function _asm_default_irq_handler: - // make sure we jump back to the right place - sub lr, lr, 4 - // save our LR - stmfd sp!, {{ lr }} - // The hardware has copied the interrupted task's CPSR to SPSR_irq - mrs lr, spsr - stmfd sp!, {{ lr }} - // switch to system mode so we can handle another interrupt - // (because if we interrupt irq mode we trash our own shadow registers) - msr cpsr_c, {sys_mode} - // save state to the system stack (adjusting SP for alignment) - "#, - crate::save_context!(), + sub lr, lr, 4 // make sure we jump back to the right place + push {{ lr }} // save adjusted LR to IRQ stack + mrs lr, spsr // The hardware has copied the interrupted task's CPSR to SPSR_irq - grab it and + push {{ lr }} // save it to IRQ stack using LR + msr cpsr_c, {sys_mode} // switch to system mode so we can handle another interrupt (because if we interrupt irq mode we trash our own shadow registers) + mov lr, sp // align SP down to eight byte boundary using LR + and lr, lr, 7 // + sub sp, lr // SP now aligned - only push 64-bit values from here + push {{ r0-r3, r12, lr }} // push alignment amount (in LR) and preserved registers + "#, + crate::save_fpu_context!(), r#" - // call C handler (they may choose to re-enable interrupts) - bl _irq_handler - // restore from the system stack + bl _irq_handler // call C handler (they may choose to re-enable interrupts) "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // switch back to IRQ mode (with IRQ masked) - msr cpsr_c, {irq_mode} - // load and restore SPSR - ldmia sp!, {{ lr }} - msr spsr, lr - // return - ldmfd sp!, {{ pc }}^ + pop {{ r0-r3, r12, lr }} // restore alignment amount (in LR) and preserved registers + add sp, lr // restore SP alignment using LR + msr cpsr_c, {irq_mode} // switch back to IRQ mode (with IRQ masked) + ldmia sp!, {{ lr }} // load and restore SPSR using LR + msr spsr, lr // + ldmfd sp!, {{ pc }}^ // return from exception .size _asm_default_irq_handler, . - _asm_default_irq_handler "#, // sys mode with IRQ masked diff --git a/aarch32-rt/src/arch_v4/svc.rs b/aarch32-rt/src/arch_v4/svc.rs index 91dc019..7b7ad6a 100644 --- a/aarch32-rt/src/arch_v4/svc.rs +++ b/aarch32-rt/src/arch_v4/svc.rs @@ -1,4 +1,4 @@ -//! Abort handler for Armv4 to Armv6 +//! SVC handler for Armv4 to Armv6 #[cfg(target_arch = "arm")] core::arch::global_asm!( @@ -6,39 +6,48 @@ core::arch::global_asm!( // Work around https://github.com/rust-lang/rust/issues/127269 .fpu vfp2 - .section .text._asm_default_svc_handler // Called from the vector table when we have an software interrupt. // Saves state and calls a C-compatible handler like - // `extern "C" fn _svc_handler(svc: u32);` - .global _asm_default_svc_handler + // `extern "C" fn _svc_handler(arg: u32, frame: &Frame) -> u32;` + .section .text._asm_default_svc_handler .arm + .global _asm_default_svc_handler .type _asm_default_svc_handler, %function _asm_default_svc_handler: - stmfd sp!, {{ r0, lr }} - mrs r0, spsr - stmfd sp!, {{ r0 }} + push {{ r12, lr }} // save LR and R12 - can now use R12 (but leave LR alone for SVC code lookup) + mrs r12, spsr // grab SPSR using R12 + push {{ r12 }} // save SPSR value + mov r12, sp // align SP down to eight byte boundary using R12 + and r12, r12, 7 // + sub sp, r12 // SP now aligned - only push 64-bit values from here + push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding) + mov r12, sp // save SP for integer frame "#, - crate::save_context!(), + crate::save_fpu_context!(), r#" - mrs r0, spsr // Load processor status that was banked on entry - tst r0, {t_bit} // SVC occurred from Thumb state? + mrs r0, spsr // Load processor status that was banked on entry + tst r0, {t_bit} // SVC occurred from Thumb state? beq 1f - ldrh r0, [lr,#-2] // Yes: Load halfword and... - bic r0, r0, #0xFF00 // ...extract comment field + ldrh r0, [lr,#-2] // Yes: Load halfword and... + bic r0, r0, #0xFF00 // ...r0 now contains SVC number b 2f 1: - ldr r0, [lr,#-4] // No: Load word and... - bic r0, r0, #0xFF000000 // ...extract comment field + ldr r0, [lr,#-4] // No: Load word and... + bic r0, r0, #0xFF000000 // ...r0 now contains SVC number 2: - // r0 now contains SVC number + mov r1, r12 // pass the stacked integer registers in r1 bl _svc_handler + mov lr, r0 // move r0 out of the way - restore_fpu_context will trash it "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - ldmfd sp!, {{ r0 }} - msr spsr_cxsf, r0 - ldmfd sp!, {{ r0, pc }}^ + pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount + mov r0, lr // replace R0 with return value from _svc_handler + add sp, r12 // restore SP alignment using R12 + pop {{ lr }} // restore SPSR using LR + msr spsr_cxsf, lr // + ldmfd sp!, {{ r12, pc }}^ // restore R12 and return from exception .size _asm_default_svc_handler, . - _asm_default_svc_handler "#, t_bit = const { crate::Cpsr::new_with_raw_value(0).with_t(true).raw_value() }, diff --git a/aarch32-rt/src/arch_v4/undefined.rs b/aarch32-rt/src/arch_v4/undefined.rs index 9297ee1..02cb09a 100644 --- a/aarch32-rt/src/arch_v4/undefined.rs +++ b/aarch32-rt/src/arch_v4/undefined.rs @@ -16,39 +16,32 @@ core::arch::global_asm!( .global _asm_default_undefined_handler .type _asm_default_undefined_handler, %function _asm_default_undefined_handler: - // state save from compiled code - stmfd sp!, {{ r0 }} - mrs r0, spsr - stmfd sp!, {{ r0 }} - // First adjust LR for two purposes: Passing the faulting instruction to the C handler, - // and to return to the failing instruction after the C handler returns. - // Load processor status for the calling code - mrs r0, spsr - // Was the code that triggered the exception in Thumb state? - tst r0, {t_bit} - // Subtract 2 in Thumb Mode, 4 in Arm Mode - see p.1206 of the ARMv7-A architecture manual. - ite eq - subeq lr, lr, #4 - subne lr, lr, #2 - // now do our standard exception save (which saves the 'wrong' R0) + push {{ r12 }} // save R12 - can now use it + mrs r12, spsr // grab SPSR using R12 + push {{ r12 }} // save SPSR value + tst r12, {t_bit} // Was the code that triggered the exception in Thumb state? + ite eq // Adjust LR to point to faulting instruction - see p.1206 of the ARMv7-A architecture manual. + subeq lr, lr, #4 // Subtract 4 in Arm Mode + subne lr, lr, #2 // Subtract 2 in Thumb Mode + mov r12, sp // align SP down to eight byte boundary using R12 + and r12, r12, 7 // + sub sp, r12 // SP now aligned - only push 64-bit values from here + push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding) "#, - crate::save_context!(), + crate::save_fpu_context!(), r#" - // Pass the faulting instruction address to the handler. - mov r0, lr - // call C handler - bl _undefined_handler - // if we get back here, assume they returned a new LR in r0 - mov lr, r0 - // do our standard restore (with the 'wrong' R0) + mov r0, lr // Pass the faulting instruction address to the handler. + bl _undefined_handler // call C handler + mov lr, r0 // if we get back here, assume they returned a new LR in r0 "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // Return from the asm handler - ldmia sp!, {{ r0 }} - msr spsr, r0 - ldmia sp!, {{ r0 }} - movs pc, lr + pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount + add sp, r12 // restore SP alignment using R12 + pop {{ r12 }} // restore SPSR using R12 + msr spsr_cxsf, r12 // + pop {{ r12 }} // restore R12 + movs pc, lr // return from exception .size _asm_default_undefined_handler, . - _asm_default_undefined_handler "#, t_bit = const { crate::Cpsr::new_with_raw_value(0).with_t(true).raw_value() }, diff --git a/aarch32-rt/src/arch_v7/abort.rs b/aarch32-rt/src/arch_v7/abort.rs index f08591e..8a2093d 100644 --- a/aarch32-rt/src/arch_v7/abort.rs +++ b/aarch32-rt/src/arch_v7/abort.rs @@ -13,57 +13,67 @@ core::arch::global_asm!( .global _asm_default_data_abort_handler .type _asm_default_data_abort_handler, %function _asm_default_data_abort_handler: - // Subtract 8 from the stored LR, see p.1214 of the ARMv7-A architecture manual. - subs lr, lr, #8 - // state save from compiled code - srsfd sp!, #{abt_mode} + sub lr, lr, #8 // Subtract 8 from LR, see p.1214 of the ARMv7-A architecture manual. + srsfd sp!, #{abt_mode} // store return state to ABT stack + push {{ r12 }} // Save preserved register R12 - can now use it + mov r12, sp // align SP down to eight byte boundary using R12 + and r12, r12, 7 // + sub sp, r12 // SP now aligned - only push 64-bit values from here + push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding) "#, - crate::save_context!(), + crate::save_fpu_context!(), r#" - // Pass the faulting instruction address to the handler. - mov r0, lr - // call C handler - bl _data_abort_handler - // if we get back here, assume they returned a new LR in r0 - mov lr, r0 + mov r0, lr // Pass the faulting instruction address to the handler. + bl _data_abort_handler // call C handler + mov lr, r0 // if we get back here, assume they returned a new LR in r0 "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // overwrite the saved LR with the one from the C handler - str lr, [sp] - // Return from the asm handler - rfefd sp! + pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount + add sp, r12 // restore SP alignment using R12 + pop {{ r12 }} // restore R12 + str lr, [sp] // overwrite the saved LR with the one from the C handler + rfefd sp! // return from exception .size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler + "#, + abt_mode = const crate::ProcessorMode::Abt as u8, +); +core::arch::global_asm!( + r#" + // Work around https://github.com/rust-lang/rust/issues/127269 + .fpu vfp3 .section .text._asm_default_prefetch_abort_handler // Called from the vector table when we have a prefetch abort. // Saves state and calls a C-compatible handler like // `extern "C" fn _prefetch_abort_handler(addr: usize);` .global _asm_default_prefetch_abort_handler + .arm .type _asm_default_prefetch_abort_handler, %function _asm_default_prefetch_abort_handler: - // Subtract 4 from the stored LR, see p.1212 of the ARMv7-A architecture manual. - subs lr, lr, #4 - // state save from compiled code - srsfd sp!, #{abt_mode} + sub lr, lr, #4 // Subtract 8 from LR, see p.1212 of the ARMv7-A architecture manual. + srsfd sp!, #{abt_mode} // store return state to ABT stack + push {{ r12 }} // save R12 - can now use it + mov r12, sp // align SP down to eight byte boundary using R12 + and r12, r12, 7 // + sub sp, r12 // SP now aligned - only push 64-bit values from here + push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding) "#, - crate::save_context!(), + crate::save_fpu_context!(), r#" - // Pass the faulting instruction address to the handler. - mov r0, lr - // call C handler - bl _prefetch_abort_handler - // if we get back here, assume they returned a new LR in r0 - mov lr, r0 + mov r0, lr // Pass the faulting instruction address to the handler. + bl _prefetch_abort_handler // call C handler + mov lr, r0 // if we get back here, assume they returned a new LR in r0 "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // overwrite the saved LR with the one from the C handler - str lr, [sp] - // Return from the asm handler - rfefd sp! + pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount + add sp, r12 // restore SP alignment using R12 + pop {{ r12 }} // restore R12 + str lr, [sp] // overwrite the saved LR with the one from the C handler + rfefd sp! // return from exception .size _asm_default_prefetch_abort_handler, . - _asm_default_prefetch_abort_handler - "#, + "#, abt_mode = const crate::ProcessorMode::Abt as u8, ); diff --git a/aarch32-rt/src/arch_v7/interrupt.rs b/aarch32-rt/src/arch_v7/interrupt.rs index bd3869c..dab9b3c 100644 --- a/aarch32-rt/src/arch_v7/interrupt.rs +++ b/aarch32-rt/src/arch_v7/interrupt.rs @@ -1,4 +1,4 @@ -//! IRQ handler for Armv7 and higher +//! IRQ handler for for Armv7 and higher #[cfg(target_arch = "arm")] core::arch::global_asm!( @@ -14,33 +14,26 @@ core::arch::global_asm!( .global _asm_default_irq_handler .type _asm_default_irq_handler, %function _asm_default_irq_handler: - // make sure we jump back to the right place - sub lr, lr, 4 - // The hardware has copied CPSR to SPSR_irq and LR to LR_irq for us. - // Now push SPSR_irq and LR_irq to the SYS stack (because that's the - // mode we're in when we pop) - srsfd sp!, #{sys_mode} - // switch to system mode so we can handle another interrupt - // (because if we interrupt irq mode we trash our own shadow registers) - cps #{sys_mode} - // we also need to save LR, so we can be re-entrant - push {{lr}} - // save state to the system stack (adjusting SP for alignment) - "#, - crate::save_context!(), + sub lr, lr, 4 // make sure we jump back to the right place + srsfd sp!, #{sys_mode} // store return state to SYS stack + cps #{sys_mode} // switch to system mode so we can handle another interrupt (because if we interrupt irq mode we trash our own shadow registers) + push {{ lr }} // save adjusted LR to SYS stack + mov lr, sp // align SP down to eight byte boundary using LR + and lr, lr, 7 // + sub sp, lr // SP now aligned - only push 64-bit values from here + push {{ r0-r3, r12, lr }} // push alignment amount (in LR) and preserved registers + "#, + crate::save_fpu_context!(), r#" - // call C handler - bl _irq_handler - // restore from the system stack + bl _irq_handler // call C handler (they may choose to re-enable interrupts) "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // restore LR - pop {{lr}} - // pop CPSR and LR from the stack (which also restores the mode) - rfefd sp! + pop {{ r0-r3, r12, lr }} // restore alignment amount (in LR) and preserved registers + add sp, lr // restore SP alignment using LR + pop {{ lr }} // restore adjusted LR + rfefd sp! // return from exception .size _asm_default_irq_handler, . - _asm_default_irq_handler - "#, sys_mode = const crate::ProcessorMode::Sys as u8, ); diff --git a/aarch32-rt/src/arch_v7/svc.rs b/aarch32-rt/src/arch_v7/svc.rs index 3a906e1..f269ce3 100644 --- a/aarch32-rt/src/arch_v7/svc.rs +++ b/aarch32-rt/src/arch_v7/svc.rs @@ -6,38 +6,43 @@ core::arch::global_asm!( // Work around https://github.com/rust-lang/rust/issues/127269 .fpu vfp3 - .section .text._asm_default_svc_handler - // Called from the vector table when we have an software interrupt. // Saves state and calls a C-compatible handler like - // `extern "C" fn _svc_handler(svc: u32);` + // `extern "C" fn _svc_handler(arg: u32, frame: &Frame) -> u32;` + .section .text._asm_default_svc_handler + .arm .global _asm_default_svc_handler .type _asm_default_svc_handler, %function _asm_default_svc_handler: - // state save from compiled code - srsfd sp!, #{svc_mode} + srsfd sp!, #{svc_mode} // store return state to SVC stack + push {{ r12, lr }} // save LR and R12 - can now use R12 (but leave LR alone for SVC code lookup) + mov r12, sp // align SP down to eight byte boundary using R12 + and r12, r12, 7 // + sub sp, r12 // SP now aligned - only push 64-bit values from here + push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding) + mov r12, sp // save SP for integer frame "#, - crate::save_context!(), + crate::save_fpu_context!(), r#" - mrs r0, spsr // Load processor status that was banked on entry - tst r0, {t_bit} // SVC occurred from Thumb state? - ldrhne r0, [lr,#-2] // Yes: Load halfword and... - bicne r0, r0, #0xFF00 // ...extract comment field - ldreq r0, [lr,#-4] // No: Load word and... - biceq r0, r0, #0xFF000000 // ...extract comment field - // r0 now contains SVC number + mrs r0, spsr // Load processor status that was banked on entry + tst r0, {t_bit} // SVC occurred from Thumb state? + ldrhne r0, [lr,#-2] // Yes: Load halfword and... + bicne r0, r0, #0xFF00 // ...extract comment field + ldreq r0, [lr,#-4] // No: Load word and... + biceq r0, r0, #0xFF000000 // ...extract comment field + mov r1, r12 // pass the stacked integer registers in r1 bl _svc_handler + mov lr, r0 // move r0 out of the way - restore_fpu_context will trash it "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // Return from the asm handler - rfefd sp! + pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount + mov r0, lr // replace R0 with return value from _svc_handler + add sp, r12 // restore SP alignment using R12 + pop {{ r12, lr }} // restore R12 and LR + rfefd sp! // return from exception .size _asm_default_svc_handler, . - _asm_default_svc_handler "#, svc_mode = const crate::ProcessorMode::Svc as u8, - t_bit = const { - crate::Cpsr::new_with_raw_value(0) - .with_t(true) - .raw_value() - }, + t_bit = const { crate::Cpsr::new_with_raw_value(0).with_t(true).raw_value() }, ); diff --git a/aarch32-rt/src/arch_v7/undefined.rs b/aarch32-rt/src/arch_v7/undefined.rs index 9fb0c6b..03e1312 100644 --- a/aarch32-rt/src/arch_v7/undefined.rs +++ b/aarch32-rt/src/arch_v7/undefined.rs @@ -15,46 +15,33 @@ core::arch::global_asm!( .global _asm_default_undefined_handler .type _asm_default_undefined_handler, %function _asm_default_undefined_handler: - // state save from compiled code - srsfd sp!, #{und_mode} - // to work out what mode we're in, we need R0 - push {{r0}} - // First adjust LR for two purposes: Passing the faulting instruction to the C handler, - // and to return to the failing instruction after the C handler returns. - // Load processor status for the calling code - mrs r0, spsr - // Was the code that triggered the exception in Thumb state? - tst r0, {t_bit} - // Subtract 2 in Thumb Mode, 4 in Arm Mode - see p.1206 of the ARMv7-A architecture manual. - ite eq - subeq lr, lr, #4 - subne lr, lr, #2 - // now do our standard exception save (which saves the 'wrong' R0) + srsfd sp!, #{und_mode} // store return state to UND stack + push {{ r12 }} // Save preserved register R12 - can now use it + mrs r12, spsr // Read SPSR into R12 + tst r12, {t_bit} // Was the code that triggered the exception in Thumb state? + ite eq // Adjust LR to point to faulting instruction - see p.1206 of the ARMv7-A architecture manual. + subeq lr, lr, #4 // Subtract 4 in Arm Mode + subne lr, lr, #2 // Subtract 2 in Thumb Mode + mov r12, sp // align SP down to eight byte boundary using R12 + and r12, r12, 7 // + sub sp, r12 // SP now aligned - only push 64-bit values from here + push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding) "#, - crate::save_context!(), + crate::save_fpu_context!(), r#" - // Pass the faulting instruction address to the handler. - mov r0, lr - // call C handler - bl _undefined_handler - // if we get back here, assume they returned a new LR in r0 - mov lr, r0 - // do our standard restore (with the 'wrong' R0) + mov r0, lr // Pass the faulting instruction address to the handler. + bl _undefined_handler // call C handler + mov lr, r0 // if we get back here, assume they returned a new LR in r0 "#, - crate::restore_context!(), + crate::restore_fpu_context!(), r#" - // get the R0 we saved early - pop {{r0}} - // overwrite the saved LR with the one from the C handler - str lr, [sp] - // Return from the asm handler - rfefd sp! + pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount + add sp, r12 // restore SP alignment using R12 + pop {{ r12 }} // restore R12 + str lr, [sp] // overwrite the saved LR with the one from the C handler + rfefd sp! // return from exception .size _asm_default_undefined_handler, . - _asm_default_undefined_handler "#, und_mode = const crate::ProcessorMode::Und as u8, - t_bit = const { - crate::Cpsr::new_with_raw_value(0) - .with_t(true) - .raw_value() - }, + t_bit = const { crate::Cpsr::new_with_raw_value(0).with_t(true).raw_value() }, ); diff --git a/aarch32-rt/src/lib.rs b/aarch32-rt/src/lib.rs index 60ceca0..1cbf9f2 100644 --- a/aarch32-rt/src/lib.rs +++ b/aarch32-rt/src/lib.rs @@ -193,14 +193,16 @@ //! The symbol `_svc_handler` should be an `extern "C"` function. It is called //! in SVC mode when an [Supervisor Call Exception] occurs. //! -//! [Supervisor CalL Exception]: +//! [Supervisor Call Exception]: //! https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/Exception-descriptions/Supervisor-Call--SVC--exception?lang=en //! //! Returning from this function will cause execution to resume at the function //! the triggered the exception, immediately after the SVC instruction. You //! cannot control where execution resumes. The function is passed the literal //! integer argument to the `svc` instruction, which is extracted from the -//! machine code for you by the default assembly trampoline. +//! machine code for you by the default assembly trampoline, along with +//! registers r0 through r7, in the form of a reference to a `Frame` +//! structure. //! //! Our linker script PROVIDEs a default `_svc_handler` symbol which is an alias //! for the `_default_handler` function. You can override it by defining your @@ -208,8 +210,9 @@ //! //! ```rust //! #[unsafe(no_mangle)] -//! extern "C" fn _svc_handler(svc: u32) { +//! extern "C" fn _svc_handler(arg: u32, frame: &aarch32_rt::Frame) -> u32 { //! // do stuff here +//! todo!() //! } //! ``` //! @@ -220,8 +223,9 @@ //! use aarch32_rt::exception; //! //! #[exception(SupervisorCall)] -//! fn my_svc_handler(arg: u32) { +//! fn svc_handler(arg: u32, frame: &aarch32_rt::Frame) -> u32 { //! // do stuff here +//! todo!() //! } //! ``` //! @@ -546,83 +550,74 @@ core::arch::global_asm!( "# ); -/// This macro expands to code for saving context on entry to an exception -/// handler. It ensures the stack pointer is 8 byte aligned on exit. +/// Arguments stacked on interrupt /// -/// EABI specifies R4 - R11 as callee-save, and so we don't preserve them -/// because any C function we call to handle the exception will -/// preserve/restore them itself as required. +/// This struct is very carefully designed to match the layout of the +/// registers pushed to the stack in our SVC handler. +#[derive(Debug, Clone, PartialEq, Eq)] +#[repr(C)] +pub struct Frame { + pub r0: u32, + pub r1: u32, + pub r2: u32, + pub r3: u32, +} + +/// This macro expands to code for saving FPU context on entry to an exception +/// handler. It pushes a multiple of eight bytes to preserve AAPCS alignment. +/// It may damage R0-R3. /// -/// It should match `restore_context!`. +/// It should match `restore_fpu_context!` /// /// On entry to this block, we assume that we are in exception context. #[cfg(not(any(target_abi = "eabihf", feature = "eabi-fpu")))] #[macro_export] -macro_rules! save_context { +macro_rules! save_fpu_context { () => { - r#" - // save preserved registers (and gives us some working area) - push {{ r0-r3 }} - // align SP down to eight byte boundary - mov r0, sp - and r0, r0, 7 - sub sp, r0 - // push alignment amount, and final preserved register - push {{ r0, r12 }} - "# + "" }; } /// This macro expands to code for restoring context on exit from an exception /// handler. /// -/// It should match `save_context!`. +/// It should match `save_fpu_context!`. #[cfg(not(any(target_abi = "eabihf", feature = "eabi-fpu")))] #[macro_export] -macro_rules! restore_context { +macro_rules! restore_fpu_context { () => { - r#" - // restore alignment amount, and preserved register - pop {{ r0, r12 }} - // restore pre-alignment SP - add sp, r0 - // restore more preserved registers - pop {{ r0-r3 }} - "# + "" }; } -/// This macro expands to code for restoring context on exit from an exception -/// handler. It saves FPU state, assuming 16 DP registers (a 'D16' or 'D16SP' +/// This macro expands to code for saving FPU context on entry to an exception +/// handler. It pushes a multiple of eight bytes to preserve AAPCS alignment. +/// It may damage R0-R3. +/// +/// It should match `restore_fpu_context!` +/// +/// On entry to this block, we assume that we are in exception context. +/// +/// This version saves FPU state, assuming 16 DP registers (a 'D16' or 'D16SP' /// FPU configuration). Note that SP-only FPUs still have DP registers /// - each DP register holds two SP values. /// -/// EABI specifies R4 - R11 and D8-D15 as callee-save, and so we don't +/// EABI specifies D8-D15 as callee-save, and so we don't /// preserve them because any C function we call to handle the exception will /// preserve/restore them itself as required. -/// -/// It should match `restore_context!`. #[cfg(all( any(target_abi = "eabihf", feature = "eabi-fpu"), not(feature = "fpu-d32") ))] #[macro_export] -macro_rules! save_context { +macro_rules! save_fpu_context { () => { r#" - // save preserved registers (and gives us some working area) - push {{ r0-r3 }} // save all D16 FPU context, except D8-D15 vpush {{ d0-d7 }} vmrs r0, FPSCR vmrs r1, FPEXC push {{ r0-r1 }} - // align SP down to eight byte boundary - mov r0, sp - and r0, r0, 7 - sub sp, r0 - // push alignment amount, and final preserved register - push {{ r0, r12 }} "# }; } @@ -631,58 +626,49 @@ macro_rules! save_context { /// handler. It restores FPU state, assuming 16 DP registers (a 'D16' or /// 'D16SP' FPU configuration). /// -/// It should match `save_context!`. +/// It should match `save_fpu_context!`. #[cfg(all( any(target_abi = "eabihf", feature = "eabi-fpu"), not(feature = "fpu-d32") ))] #[macro_export] -macro_rules! restore_context { +macro_rules! restore_fpu_context { () => { r#" - // restore alignment amount, and preserved register - pop {{ r0, r12 }} - // restore pre-alignment SP - add sp, r0 // restore all D16 FPU context, except D8-D15 pop {{ r0-r1 }} vmsr FPEXC, r1 vmsr FPSCR, r0 vpop {{ d0-d7 }} - // restore more preserved registers - pop {{ r0-r3 }} "# }; } -/// This macro expands to code for saving context on entry to an exception -/// handler. It saves FPU state assuming 32 DP registers (a 'D32' FPU +/// This macro expands to code for saving FPU context on entry to an exception +/// handler. It pushes a multiple of eight bytes to preserve AAPCS alignment. +/// It may damage R0-R3. +/// +/// It should match `restore_fpu_context!` +/// +/// On entry to this block, we assume that we are in exception context. +/// +/// This version saves FPU state assuming 32 DP registers (a 'D32' FPU /// configuration). /// -/// EABI specifies R4 - R11 and D8-D15 as callee-save, and so we don't +/// EABI specifies D8-D15 as callee-save, and so we don't /// preserve them because any C function we call to handle the exception will /// preserve/restore them itself as required. -/// -/// It should match `restore_context!`. #[cfg(all(any(target_abi = "eabihf", feature = "eabi-fpu"), feature = "fpu-d32"))] #[macro_export] -macro_rules! save_context { +macro_rules! save_fpu_context { () => { r#" - // save preserved registers (and gives us some working area) - push {{ r0-r3 }} // save all D32 FPU context, except D8-D15 vpush {{ d0-d7 }} vpush {{ d16-d31 }} vmrs r0, FPSCR vmrs r1, FPEXC push {{ r0-r1 }} - // align SP down to eight byte boundary - mov r0, sp - and r0, r0, 7 - sub sp, r0 - // push alignment amount, and final preserved register - push {{ r0, r12 }} "# }; } @@ -691,24 +677,18 @@ macro_rules! save_context { /// handler. It restores FPU state, assuming 32 DP registers (a 'D32' FPU /// configuration). /// -/// It should match `save_context!`. +/// It should match `save_fpu_context!`. #[cfg(all(any(target_abi = "eabihf", feature = "eabi-fpu"), feature = "fpu-d32"))] #[macro_export] -macro_rules! restore_context { +macro_rules! restore_fpu_context { () => { r#" - // restore alignment amount, and preserved register - pop {{ r0, r12 }} - // restore pre-alignment SP - add sp, r0 // restore all D32 FPU context, except D8-D15 pop {{ r0-r1 }} vmsr FPEXC, r1 vmsr FPSCR, r0 vpop {{ d16-d31 }} vpop {{ d0-d7 }} - // restore more preserved registers - pop {{ r0-r3 }} "# }; } @@ -804,8 +784,8 @@ core::arch::global_asm!( // Initialises stacks, .data and .bss .section .text._init_segments - .global _init_segments .arm + .global _init_segments .type _init_segments, %function _init_segments: // Initialise .bss diff --git a/arm-targets/src/lib.rs b/arm-targets/src/lib.rs index bd71463..7b02726 100644 --- a/arm-targets/src/lib.rs +++ b/arm-targets/src/lib.rs @@ -216,15 +216,21 @@ impl Arch { Some(Arch::Armv8MBase) } else if target.starts_with("thumbv8m.main-") { Some(Arch::Armv8MMain) - } else if target.starts_with("armv7r-") || target.starts_with("armebv7r") { + } else if target.starts_with("armv7r-") + || target.starts_with("armebv7r-") + || target.starts_with("thumbv7r-") + { Some(Arch::Armv7R) - } else if target.starts_with("armv8r-") { + } else if target.starts_with("armv8r-") || target.starts_with("thumbv8r-") { Some(Arch::Armv8R) - } else if target.starts_with("armv7a-") { + } else if target.starts_with("armv7a-") || target.starts_with("thumbv7a-") { Some(Arch::Armv7A) } else if target.starts_with("aarch64-") || target.starts_with("aarch64be-") { Some(Arch::Armv8A) - } else if target.starts_with("arm-") { + } else if target.starts_with("arm-") + || target.starts_with("armv6-") + || target.starts_with("thumbv6-") + { // If not specified, assume Armv6 Some(Arch::Armv6) } else { @@ -404,6 +410,26 @@ mod test { assert_eq!(target_info.abi(), Some(Abi::Eabi)); } + #[test] + fn armv6_none_eabi() { + let target = "armv6-none-eabi"; + let target_info = process_target(target); + assert_eq!(target_info.isa(), Some(Isa::A32)); + assert_eq!(target_info.arch(), Some(Arch::Armv6)); + assert_eq!(target_info.profile(), Some(Profile::Legacy)); + assert_eq!(target_info.abi(), Some(Abi::Eabi)); + } + + #[test] + fn armv6_none_eabihf() { + let target = "armv6-none-eabihf"; + let target_info = process_target(target); + assert_eq!(target_info.isa(), Some(Isa::A32)); + assert_eq!(target_info.arch(), Some(Arch::Armv6)); + assert_eq!(target_info.profile(), Some(Profile::Legacy)); + assert_eq!(target_info.abi(), Some(Abi::EabiHf)); + } + #[test] fn arm_unknown_linux_gnueabi() { let target = "arm-unknown-linux-gnueabi"; @@ -484,6 +510,16 @@ mod test { assert_eq!(target_info.abi(), Some(Abi::EabiHf)); } + #[test] + fn thumbv8r_none_eabihf() { + let target = "thumbv8r-none-eabihf"; + let target_info = process_target(target); + assert_eq!(target_info.isa(), Some(Isa::T32)); + assert_eq!(target_info.arch(), Some(Arch::Armv8R)); + assert_eq!(target_info.profile(), Some(Profile::R)); + assert_eq!(target_info.abi(), Some(Abi::EabiHf)); + } + #[test] fn armv7a_none_eabi() { let target = "armv7a-none-eabi"; diff --git a/examples/mps3-an536/reference/abt-exception-a32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/abt-exception-a32-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..d521f0b --- /dev/null +++ b/examples/mps3-an536/reference/abt-exception-a32-thumbv8r-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/mps3-an536/reference/abt-exception-t32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/abt-exception-t32-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..0067a8b --- /dev/null +++ b/examples/mps3-an536/reference/abt-exception-t32-thumbv8r-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0010 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/mps3-an536/reference/el2_hello-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/el2_hello-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..bf0ed13 --- /dev/null +++ b/examples/mps3-an536/reference/el2_hello-thumbv8r-none-eabihf.out @@ -0,0 +1,27 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +Region 0: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 1: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 2: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 3: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 4: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 5: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 6: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 7: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 8: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 9: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 10: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 11: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 12: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 13: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 14: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +Region 15: El2Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL10, no_exec: false, mair: 0, enable: false } +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/el2_hello.rs", + line: 28, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/mps3-an536/reference/fpu-test-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/fpu-test-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/mps3-an536/reference/fpu-test-thumbv8r-none-eabihf.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) ..............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +Sine wave test (f64)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/mps3-an536/reference/generic_timer-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/generic_timer-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..bd2c08a --- /dev/null +++ b/examples/mps3-an536/reference/generic_timer-thumbv8r-none-eabihf.out @@ -0,0 +1,26 @@ +Found PERIPHBASE 0xf0000000 +Creating GIC driver @ 0xf0000000 / 0xf0100000 +Calling git.setup(0) +cntfrq = 62.500 MHz +Using physical timer ************************ +Print five, every 100ms... +i = 0 +i = 1 +i = 2 +i = 3 +i = 4 +Waiting for 31250000 physical ticks to count up... +Matched! physical +Waiting for 31250000 physical ticks to count down... +physical countdown hit zero! +Using virtual timer ************************ +Print five, every 100ms... +i = 0 +i = 1 +i = 2 +i = 3 +i = 4 +Waiting for 31250000 virtual ticks to count up... +Matched! virtual +Waiting for 31250000 virtual ticks to count down... +virtual countdown hit zero! diff --git a/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out index d44bcd5..1c3bdd6 100644 --- a/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out +++ b/examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out @@ -3,8 +3,8 @@ Creating GIC driver @ 0xf0000000 / 0xf0100000 Calling git.setup(0) Configure Timer Interrupt... Enabling interrupts... -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) } -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } > IRQ - Timer fired, resetting < IRQ diff --git a/examples/mps3-an536/reference/generic_timer_irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/generic_timer_irq-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..1c3bdd6 --- /dev/null +++ b/examples/mps3-an536/reference/generic_timer_irq-thumbv8r-none-eabihf.out @@ -0,0 +1,48 @@ +Found PERIPHBASE 0xf0000000 +Creating GIC driver @ 0xf0000000 / 0xf0100000 +Calling git.setup(0) +Configure Timer Interrupt... +Enabling interrupts... +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 0 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 1 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 2 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 3 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 4 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 5 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 6 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 7 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 8 + > IRQ + - Timer fired, resetting + < IRQ +Main loop wake up 9 +Timer IRQ test completed OK diff --git a/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out index db56b21..05e6eea 100644 --- a/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out +++ b/examples/mps3-an536/reference/gic-map-armv8r-none-eabihf.out @@ -5,8 +5,8 @@ Configure low-prio SGI... Configure high-prio SGI... gic.enable_interrupt() Enabling interrupts... -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) } -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } Send lo-prio SGI > IRQ - handle_interrupt_with_id(SGI 3) diff --git a/examples/mps3-an536/reference/gic-map-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-map-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..05e6eea --- /dev/null +++ b/examples/mps3-an536/reference/gic-map-thumbv8r-none-eabihf.out @@ -0,0 +1,20 @@ +Found PERIPHBASE 0xf0000000 +Creating GIC driver @ 0xf0000000 / 0xf0100000 +Calling git.setup(0) +Configure low-prio SGI... +Configure high-prio SGI... +gic.enable_interrupt() +Enabling interrupts... +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +Send lo-prio SGI +> IRQ +- handle_interrupt_with_id(SGI 3) +- got SGI 3, sending hi-prio SGI 4 +> IRQ +- handle_interrupt_with_id(SGI 4) +- got hi-prio SGI 4! +< IRQ +- finished sending hi-prio! +< IRQ +IRQ test completed OK diff --git a/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out index bd00a91..bde2935 100644 --- a/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out +++ b/examples/mps3-an536/reference/gic-priority-ceiling-armv8r-none-eabihf.out @@ -5,8 +5,8 @@ Configure low-prio SGI... Configure high-prio SGI... gic.enable_interrupt() Enabling interrupts... -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) } -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } Send lo-prio SGI > IRQ - IRQ Handling SGI 3 diff --git a/examples/mps3-an536/reference/gic-priority-ceiling-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-priority-ceiling-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..bde2935 --- /dev/null +++ b/examples/mps3-an536/reference/gic-priority-ceiling-thumbv8r-none-eabihf.out @@ -0,0 +1,23 @@ +Found PERIPHBASE 0xf0000000 +Creating GIC driver @ 0xf0000000 / 0xf0100000 +Calling git.setup(0) +Configure low-prio SGI... +Configure high-prio SGI... +gic.enable_interrupt() +Enabling interrupts... +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +Send lo-prio SGI +> IRQ +- IRQ Handling SGI 3 + - Low prio! + - Pre lock exit + - HIGH PRIO SHOULD RUN AFTER THIS +> IRQ +- IRQ Handling SGI 4 + - High prio! +< IRQ + - HIGH PRIO SHOULD RUN BEFORE THIS + - Post lock exit +< IRQ +IRQ test completed OK diff --git a/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out index db56b21..05e6eea 100644 --- a/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out +++ b/examples/mps3-an536/reference/gic-static-section-irq-armv8r-none-eabihf.out @@ -5,8 +5,8 @@ Configure low-prio SGI... Configure high-prio SGI... gic.enable_interrupt() Enabling interrupts... -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) } -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } Send lo-prio SGI > IRQ - handle_interrupt_with_id(SGI 3) diff --git a/examples/mps3-an536/reference/gic-static-section-irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-static-section-irq-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..05e6eea --- /dev/null +++ b/examples/mps3-an536/reference/gic-static-section-irq-thumbv8r-none-eabihf.out @@ -0,0 +1,20 @@ +Found PERIPHBASE 0xf0000000 +Creating GIC driver @ 0xf0000000 / 0xf0100000 +Calling git.setup(0) +Configure low-prio SGI... +Configure high-prio SGI... +gic.enable_interrupt() +Enabling interrupts... +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +Send lo-prio SGI +> IRQ +- handle_interrupt_with_id(SGI 3) +- got SGI 3, sending hi-prio SGI 4 +> IRQ +- handle_interrupt_with_id(SGI 4) +- got hi-prio SGI 4! +< IRQ +- finished sending hi-prio! +< IRQ +IRQ test completed OK diff --git a/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out index ab68c14..94023e1 100644 --- a/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out +++ b/examples/mps3-an536/reference/gic-unified-irq-armv8r-none-eabihf.out @@ -5,8 +5,8 @@ Configure low-prio SGI... Configure high-prio SGI... gic.enable_interrupt() Enabling interrupts... -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) } -CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } Send lo-prio SGI > IRQ - IRQ Handling SGI 3 diff --git a/examples/mps3-an536/reference/gic-unified-irq-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/gic-unified-irq-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..94023e1 --- /dev/null +++ b/examples/mps3-an536/reference/gic-unified-irq-thumbv8r-none-eabihf.out @@ -0,0 +1,19 @@ +Found PERIPHBASE 0xf0000000 +Creating GIC driver @ 0xf0000000 / 0xf0100000 +Calling git.setup(0) +Configure low-prio SGI... +Configure high-prio SGI... +gic.enable_interrupt() +Enabling interrupts... +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } +Send lo-prio SGI +> IRQ +- IRQ Handling SGI 3 +- IRQ got SGI 3, sending hi-prio SGI 4 +> IRQ +- IRQ Handling SGI 4 +< IRQ +- IRQ finished sending hi-prio! +< IRQ +IRQ test completed OK diff --git a/examples/mps3-an536/reference/hello-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/hello-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..3d5180e --- /dev/null +++ b/examples/mps3-an536/reference/hello-thumbv8r-none-eabihf.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 20, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/mps3-an536/reference/prefetch-exception-a32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/prefetch-exception-a32-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..0443a50 --- /dev/null +++ b/examples/mps3-an536/reference/prefetch-exception-a32-thumbv8r-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0010 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0010 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/mps3-an536/reference/prefetch-exception-t32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/prefetch-exception-t32-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..94da556 --- /dev/null +++ b/examples/mps3-an536/reference/prefetch-exception-t32-thumbv8r-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0010 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0010 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/mps3-an536/reference/registers-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/registers-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..ffd2137 --- /dev/null +++ b/examples/mps3-an536/reference/registers-thumbv8r-none-eabihf.out @@ -0,0 +1,39 @@ +MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xd13 rev=0x3 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) } +IMP_CBAR { 0xf0000000 } +Vbar(8000000) +PMSA-v8 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false } +Region 0: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 1: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 2: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 3: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 4: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 5: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 6: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 7: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 8: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 9: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 10: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 11: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 12: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 13: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 14: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 15: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 0: El1Region { range: 0x0..=0x3fffffff, shareability: OuterShareable, access: ReadWrite, no_exec: true, mair: 0, enable: true } +Region 1: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 2: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 3: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 4: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 5: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 6: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 7: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 8: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 9: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 10: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 11: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 12: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 13: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 14: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +Region 15: El1Region { range: 0x0..=0x3f, shareability: NonShareable, access: ReadWriteNoEL0, no_exec: false, mair: 0, enable: false } +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=1 RR=0 V=0 I=0 Z=1 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=1 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..7fe30b8 --- /dev/null +++ b/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf.out @@ -0,0 +1 @@ +CPU 1 is missing?! diff --git a/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf_smp2.out b/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf_smp2.out new file mode 100644 index 0000000..7fe30b8 --- /dev/null +++ b/examples/mps3-an536/reference/smp_test-thumbv8r-none-eabihf_smp2.out @@ -0,0 +1 @@ +CPU 1 is missing?! diff --git a/examples/mps3-an536/reference/svc-a32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/svc-a32-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..fe4deb8 --- /dev/null +++ b/examples/mps3-an536/reference/svc-a32-thumbv8r-none-eabihf.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 diff --git a/examples/mps3-an536/reference/svc-t32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/svc-t32-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..c9edfeb --- /dev/null +++ b/examples/mps3-an536/reference/svc-t32-thumbv8r-none-eabihf.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 diff --git a/examples/mps3-an536/reference/syscall-armv8r-none-eabihf.out b/examples/mps3-an536/reference/syscall-armv8r-none-eabihf.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/mps3-an536/reference/syscall-armv8r-none-eabihf.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/mps3-an536/reference/syscall-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/syscall-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/mps3-an536/reference/syscall-thumbv8r-none-eabihf.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/mps3-an536/reference/undef-exception-a32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/undef-exception-a32-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/mps3-an536/reference/undef-exception-a32-thumbv8r-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/mps3-an536/reference/undef-exception-t32-thumbv8r-none-eabihf.out b/examples/mps3-an536/reference/undef-exception-t32-thumbv8r-none-eabihf.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/mps3-an536/reference/undef-exception-t32-thumbv8r-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/mps3-an536/rust-toolchain.toml b/examples/mps3-an536/rust-toolchain.toml index 92667db..7e4d9e6 100644 --- a/examples/mps3-an536/rust-toolchain.toml +++ b/examples/mps3-an536/rust-toolchain.toml @@ -1,5 +1,5 @@ [toolchain] -channel = "nightly-2026-01-02" +channel = "nightly-2026-01-26" targets = [ "armv8r-none-eabihf", ] diff --git a/examples/mps3-an536/src/bin/generic_timer_irq.rs b/examples/mps3-an536/src/bin/generic_timer_irq.rs index 98cad0a..165bca1 100644 --- a/examples/mps3-an536/src/bin/generic_timer_irq.rs +++ b/examples/mps3-an536/src/bin/generic_timer_irq.rs @@ -44,11 +44,11 @@ fn main() -> ! { ); println!("Enabling interrupts..."); - dump_cpsr(); + dump_sctlr(); unsafe { aarch32_cpu::interrupt::enable(); } - dump_cpsr(); + dump_sctlr(); let mut count: u32 = 0; loop { @@ -63,9 +63,9 @@ fn main() -> ! { } } -fn dump_cpsr() { - let cpsr = aarch32_cpu::register::Cpsr::read(); - println!("CPSR: {:?}", cpsr); +fn dump_sctlr() { + let sctlr = aarch32_cpu::register::Sctlr::read(); + println!("{:?}", sctlr); } #[irq] diff --git a/examples/mps3-an536/src/bin/gic-map.rs b/examples/mps3-an536/src/bin/gic-map.rs index 8be088c..f1caa4a 100644 --- a/examples/mps3-an536/src/bin/gic-map.rs +++ b/examples/mps3-an536/src/bin/gic-map.rs @@ -80,11 +80,11 @@ fn main() -> ! { }); println!("Enabling interrupts..."); - dump_cpsr(); + dump_sctlr(); unsafe { aarch32_cpu::interrupt::enable(); } - dump_cpsr(); + dump_sctlr(); // Send it println!("Send lo-prio SGI"); @@ -109,9 +109,9 @@ fn main() -> ! { semihosting::process::exit(0); } -fn dump_cpsr() { - let cpsr = aarch32_cpu::register::Cpsr::read(); - println!("CPSR: {:?}", cpsr); +fn dump_sctlr() { + let sctlr = aarch32_cpu::register::Sctlr::read(); + println!("{:?}", sctlr); } /// Handles the low-prio SGI diff --git a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs index e0fc815..9ea98a7 100644 --- a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs +++ b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs @@ -61,11 +61,11 @@ fn main() -> ! { .unwrap(); println!("Enabling interrupts..."); - dump_cpsr(); + dump_sctlr(); unsafe { aarch32_cpu::interrupt::enable(); } - dump_cpsr(); + dump_sctlr(); // Send it println!("Send lo-prio SGI"); @@ -90,9 +90,9 @@ fn main() -> ! { semihosting::process::exit(0); } -fn dump_cpsr() { - let cpsr = aarch32_cpu::register::Cpsr::read(); - println!("CPSR: {:?}", cpsr); +fn dump_sctlr() { + let sctlr = aarch32_cpu::register::Sctlr::read(); + println!("{:?}", sctlr); } // This function doesn't need to be unsafe - I'm just checking you can apply the unsafe diff --git a/examples/mps3-an536/src/bin/gic-static-section-irq.rs b/examples/mps3-an536/src/bin/gic-static-section-irq.rs index 18717d3..79e807c 100644 --- a/examples/mps3-an536/src/bin/gic-static-section-irq.rs +++ b/examples/mps3-an536/src/bin/gic-static-section-irq.rs @@ -58,11 +58,11 @@ fn main() -> ! { .unwrap(); println!("Enabling interrupts..."); - dump_cpsr(); + dump_sctlr(); unsafe { aarch32_cpu::interrupt::enable(); } - dump_cpsr(); + dump_sctlr(); // Send it println!("Send lo-prio SGI"); @@ -87,9 +87,9 @@ fn main() -> ! { semihosting::process::exit(0); } -fn dump_cpsr() { - let cpsr = aarch32_cpu::register::Cpsr::read(); - println!("CPSR: {:?}", cpsr); +fn dump_sctlr() { + let sctlr = aarch32_cpu::register::Sctlr::read(); + println!("{:?}", sctlr); } #[unsafe(link_section = ".irq_entries")] diff --git a/examples/mps3-an536/src/bin/gic-unified-irq.rs b/examples/mps3-an536/src/bin/gic-unified-irq.rs index 0cb00c2..844c7b6 100644 --- a/examples/mps3-an536/src/bin/gic-unified-irq.rs +++ b/examples/mps3-an536/src/bin/gic-unified-irq.rs @@ -58,11 +58,11 @@ fn main() -> ! { .unwrap(); println!("Enabling interrupts..."); - dump_cpsr(); + dump_sctlr(); unsafe { aarch32_cpu::interrupt::enable(); } - dump_cpsr(); + dump_sctlr(); // Send it println!("Send lo-prio SGI"); @@ -87,9 +87,9 @@ fn main() -> ! { semihosting::process::exit(0); } -fn dump_cpsr() { - let cpsr = aarch32_cpu::register::Cpsr::read(); - println!("CPSR: {:?}", cpsr); +fn dump_sctlr() { + let sctlr = aarch32_cpu::register::Sctlr::read(); + println!("{:?}", sctlr); } #[irq] diff --git a/examples/mps3-an536/src/bin/smp_test.rs b/examples/mps3-an536/src/bin/smp_test.rs index 9c57a79..1a2448a 100644 --- a/examples/mps3-an536/src/bin/smp_test.rs +++ b/examples/mps3-an536/src/bin/smp_test.rs @@ -264,6 +264,7 @@ core::arch::global_asm!( // // Pass in stack top in r0. .section .text._stack_setup + .arm .global _stack_setup .type _stack_setup, %function _stack_setup: diff --git a/examples/mps3-an536/src/bin/svc-a32.rs b/examples/mps3-an536/src/bin/svc-a32.rs index cade824..c7ed246 100644 --- a/examples/mps3-an536/src/bin/svc-a32.rs +++ b/examples/mps3-an536/src/bin/svc-a32.rs @@ -16,17 +16,28 @@ fn main() -> ! { let y = x + 1; let z = (y as f64) * 1.5; println!("x = {}, y = {}, z = {:0.3}", x, y, z); - aarch32_cpu::svc!(0xABCDEF); + do_svc1(); println!("x = {}, y = {}, z = {:0.3}", x, y, z); semihosting::process::exit(0); } /// This is our SVC exception handler #[exception(SupervisorCall)] -fn svc_handler(arg: u32) { +fn svc_handler(arg: u32, _frame: &aarch32_rt::Frame) -> u32 { println!("In svc_handler, with arg=0x{:06x}", arg); if arg == 0xABCDEF { // test nested SVC calls - aarch32_cpu::svc!(0x456789); + do_svc2(); } + 0 +} + +#[instruction_set(arm::a32)] +fn do_svc1() { + aarch32_cpu::svc!(0xABCDEF); +} + +#[instruction_set(arm::a32)] +fn do_svc2() { + aarch32_cpu::svc!(0x456789); } diff --git a/examples/mps3-an536/src/bin/svc-t32.rs b/examples/mps3-an536/src/bin/svc-t32.rs index 47e7471..c774dc6 100644 --- a/examples/mps3-an536/src/bin/svc-t32.rs +++ b/examples/mps3-an536/src/bin/svc-t32.rs @@ -16,51 +16,28 @@ fn main() -> ! { let y = x + 1; let z = (y as f64) * 1.5; println!("x = {}, y = {}, z = {:0.3}", x, y, z); - unsafe { - svc12_from_t32(); - } + do_svc1(); println!("x = {}, y = {}, z = {:0.3}", x, y, z); semihosting::process::exit(0); } /// This is our SVC exception handler #[exception(SupervisorCall)] -fn svc_handler(arg: u32) { +fn svc_handler(arg: u32, _frame: &aarch32_rt::Frame) -> u32 { println!("In svc_handler, with arg=0x{:06x}", arg); if arg == 0x12 { // test nested SVC calls - unsafe { - svc34_from_t32(); - } + do_svc2(); } + 0 } -// These functions are written in assembly -extern "C" { - fn svc12_from_t32(); - fn svc34_from_t32(); +#[instruction_set(arm::t32)] +fn do_svc1() { + aarch32_cpu::svc!(0x12); } -core::arch::global_asm!( - r#" - // fn svc12_from_t32(); - .thumb - .global svc12_from_t32 - .type svc12_from_t32, %function - svc12_from_t32: - push {{ r7, lr }} - svc 0x12 - pop {{ r7, pc }} - .size svc12_from_t32, . - svc12_from_t32 - - // fn svc34_from_t32(); - .thumb - .global svc34_from_t32 - .type svc34_from_t32, %function - svc34_from_t32: - push {{ r7, lr }} - svc 0x34 - pop {{ r7, pc }} - .size svc34_from_t32, . - svc34_from_t32 -"# -); +#[instruction_set(arm::t32)] +fn do_svc2() { + aarch32_cpu::svc!(0x34); +} diff --git a/examples/mps3-an536/src/bin/syscall.rs b/examples/mps3-an536/src/bin/syscall.rs new file mode 100644 index 0000000..d9b0ceb --- /dev/null +++ b/examples/mps3-an536/src/bin/syscall.rs @@ -0,0 +1,62 @@ +//! Syscall example +//! +//! * Syscall 0xF0 takes no arguments and returns: 0x1000_0000 +//! * Syscall 0xF1 takes one argument and returns: 0x1000_0000 + (arg0) +//! * Syscall 0xF2 takes two arguments and returns: 0x1000_0000 + (arg0) + (arg1 << 4) +//! * Syscall 0xF3 takes three arguments and returns: 0x1000_0000 + (arg0) + (arg1 << 4) + (arg2 << 8) +//! * Syscall 0xF4 takes four arguments and returns: 0x1000_0000 + (arg0) + (arg1 << 4) + (arg2 << 8) + (arg3 << 12) + +#![no_std] +#![no_main] + +use aarch32_rt::{entry, exception}; +use mps3_an536 as _; +use semihosting::println; + +/// The entry-point to the Rust application. +/// +/// It is called by the start-up. +#[entry] +fn main() -> ! { + let x = 1; + let y = x + 1; + let z = (y as f64) * 1.5; + println!("x = {}, y = {}, z = {:0.3}", x, y, z); + + let retval = aarch32_cpu::svc4!(0xF4, 0xE000_0001, 0xE000_0002, 0xE000_0003, 0xE000_0004); + if retval != 0xF000_4321 { + panic!("Wanted 0xF000_4321, got {:08x}", retval); + } + let retval = aarch32_cpu::svc3!(0xF3, 0xE000_0001, 0xE000_0002, 0xE000_0003); + if retval != 0xF000_0321 { + panic!("Wanted 0xF000_0321, got {:08x}", retval); + } + let retval = aarch32_cpu::svc2!(0xF2, 0xE000_0001, 0xE000_0002); + if retval != 0xF000_0021 { + panic!("Wanted 0xF000_0021, got {:08x}", retval); + } + let retval = aarch32_cpu::svc1!(0xF1, 0xE000_0001); + if retval != 0xF000_0001 { + panic!("Wanted 0xF000_0001, got {:08x}", retval); + } + let retval = aarch32_cpu::svc!(0xF0); + if retval != 0x1000_0000 { + panic!("Wanted 0x1000_0000, got {:08x}", retval); + } + println!("Syscalls all look OK, printing local variables..."); + println!("x = {}, y = {}, z = {:0.3}", x, y, z); + semihosting::process::exit(0); +} + +/// This is our syscall handler +#[exception(SupervisorCall)] +fn svc_handler(arg: u32, frame: &aarch32_rt::Frame) -> u32 { + match arg { + 0xF0 => 0x1000_0000, + 0xF1 => 0x1000_0000 + frame.r0, + 0xF2 => 0x1000_0000 + frame.r0 + (frame.r1 << 4), + 0xF3 => 0x1000_0000 + frame.r0 + (frame.r1 << 4) + (frame.r2 << 8), + 0xF4 => 0x1000_0000 + frame.r0 + (frame.r1 << 4) + (frame.r2 << 8) + (frame.r3 << 12), + _ => 0xDEADC0DE, + } +} diff --git a/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-armv6-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabi.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-thumbv7a-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabi.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-thumbv7r-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-armv6-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabi.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-thumbv7a-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabi.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-thumbv7r-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/fpu-test-armv6-none-eabi.out b/examples/versatileab/reference/fpu-test-armv6-none-eabi.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-armv6-none-eabi.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o 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.......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) ..............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +Sine wave test (f64)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) 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..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/fpu-test-armv6-none-eabihf.out b/examples/versatileab/reference/fpu-test-armv6-none-eabihf.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-armv6-none-eabihf.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) ..............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +Sine wave test (f64)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/fpu-test-thumbv7a-none-eabi.out b/examples/versatileab/reference/fpu-test-thumbv7a-none-eabi.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-thumbv7a-none-eabi.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o 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.........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) ..............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +Sine wave test (f64)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) 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...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/fpu-test-thumbv7a-none-eabihf.out b/examples/versatileab/reference/fpu-test-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-thumbv7a-none-eabihf.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o 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.........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) ..............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +Sine wave test (f64)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/fpu-test-thumbv7r-none-eabi.out b/examples/versatileab/reference/fpu-test-thumbv7r-none-eabi.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-thumbv7r-none-eabi.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o 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.........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) ..............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +Sine wave test (f64)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/fpu-test-thumbv7r-none-eabihf.out b/examples/versatileab/reference/fpu-test-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-thumbv7r-none-eabihf.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o 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.........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) ..............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +Sine wave test (f64)... +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o +( 0.0000) ..............................o +( 0.1253) .................................o +( 0.2487) .....................................o +( 0.3681) .........................................o +( 0.4818) ............................................o +( 0.5878) ...............................................o +( 0.6845) ..................................................o +( 0.7705) .....................................................o +( 0.8443) .......................................................o +( 0.9048) .........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/hello-armv6-none-eabi.out b/examples/versatileab/reference/hello-armv6-none-eabi.out new file mode 100644 index 0000000..59aae22 --- /dev/null +++ b/examples/versatileab/reference/hello-armv6-none-eabi.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 19, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/hello-armv6-none-eabihf.out b/examples/versatileab/reference/hello-armv6-none-eabihf.out new file mode 100644 index 0000000..59aae22 --- /dev/null +++ b/examples/versatileab/reference/hello-armv6-none-eabihf.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 19, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/hello-thumbv7a-none-eabi.out b/examples/versatileab/reference/hello-thumbv7a-none-eabi.out new file mode 100644 index 0000000..59aae22 --- /dev/null +++ b/examples/versatileab/reference/hello-thumbv7a-none-eabi.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 19, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/hello-thumbv7a-none-eabihf.out b/examples/versatileab/reference/hello-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..59aae22 --- /dev/null +++ b/examples/versatileab/reference/hello-thumbv7a-none-eabihf.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 19, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/hello-thumbv7r-none-eabi.out b/examples/versatileab/reference/hello-thumbv7r-none-eabi.out new file mode 100644 index 0000000..59aae22 --- /dev/null +++ b/examples/versatileab/reference/hello-thumbv7r-none-eabi.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 19, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/hello-thumbv7r-none-eabihf.out b/examples/versatileab/reference/hello-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..59aae22 --- /dev/null +++ b/examples/versatileab/reference/hello-thumbv7r-none-eabihf.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 19, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/interrupt-armv6-none-eabi.out b/examples/versatileab/reference/interrupt-armv6-none-eabi.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-armv6-none-eabi.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/interrupt-armv6-none-eabihf.out b/examples/versatileab/reference/interrupt-armv6-none-eabihf.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-armv6-none-eabihf.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/interrupt-thumbv7a-none-eabi.out b/examples/versatileab/reference/interrupt-thumbv7a-none-eabi.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-thumbv7a-none-eabi.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/interrupt-thumbv7a-none-eabihf.out b/examples/versatileab/reference/interrupt-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-thumbv7a-none-eabihf.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/interrupt-thumbv7r-none-eabi.out b/examples/versatileab/reference/interrupt-thumbv7r-none-eabi.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-thumbv7r-none-eabi.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/interrupt-thumbv7r-none-eabihf.out b/examples/versatileab/reference/interrupt-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..51b9aea --- /dev/null +++ b/examples/versatileab/reference/interrupt-thumbv7r-none-eabihf.out @@ -0,0 +1,15 @@ +Setting up interrupts... +Firing interrupt... +> interrupt_handler() +> soft_handler1() +> interrupt_handler() +> soft_handler2() +< soft_handler2() +< interrupt_handler() +< soft_handler1() +< interrupt_handler() +Got interrupted :) +> interrupt_handler() +catchall_handler() fired +< interrupt_handler() +catch all works. All done! diff --git a/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-armv6-none-eabihf.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabi.out new file mode 100644 index 0000000..1929eee --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..1929eee --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv7a-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabi.out new file mode 100644 index 0000000..1929eee --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..1929eee --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv7r-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-armv6-none-eabihf.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabi.out new file mode 100644 index 0000000..2b5664f --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..2b5664f --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv7a-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabi.out new file mode 100644 index 0000000..2b5664f --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..2b5664f --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv7r-none-eabihf.out @@ -0,0 +1,14 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +IFAR (Faulting Address Register): Ifar(0) +caught bkpt_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/registers-armv6-none-eabi.out b/examples/versatileab/reference/registers-armv6-none-eabi.out new file mode 100644 index 0000000..f24dd0c --- /dev/null +++ b/examples/versatileab/reference/registers-armv6-none-eabi.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xb76 rev=0x7 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(410fb767) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/registers-armv6-none-eabihf.out b/examples/versatileab/reference/registers-armv6-none-eabihf.out new file mode 100644 index 0000000..f24dd0c --- /dev/null +++ b/examples/versatileab/reference/registers-armv6-none-eabihf.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xb76 rev=0x7 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(410fb767) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/registers-thumbv7a-none-eabi.out b/examples/versatileab/reference/registers-thumbv7a-none-eabi.out new file mode 100644 index 0000000..27fdee0 --- /dev/null +++ b/examples/versatileab/reference/registers-thumbv7a-none-eabi.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xc08 rev=0x0 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(0) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/registers-thumbv7a-none-eabihf.out b/examples/versatileab/reference/registers-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..27fdee0 --- /dev/null +++ b/examples/versatileab/reference/registers-thumbv7a-none-eabihf.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x41 variant=0x0 arch=0xf part_no=0xc08 rev=0x0 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(0) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=1 FI=0 DZ=1 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/registers-thumbv7r-none-eabi.out b/examples/versatileab/reference/registers-thumbv7r-none-eabi.out new file mode 100644 index 0000000..6d58047 --- /dev/null +++ b/examples/versatileab/reference/registers-thumbv7r-none-eabi.out @@ -0,0 +1,38 @@ +MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(c0000000) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after +PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false } +DRegion 0: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } } +DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } diff --git a/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out b/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..6d58047 --- /dev/null +++ b/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out @@ -0,0 +1,38 @@ +MIDR { implementer=0x41 variant=0x1 arch=0xf part_no=0xc15 rev=0x3 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(c0000000) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after +PMSA-v7 MPUIR: Mpuir { iregions: 0, dregions: 16, non_unified: false } +DRegion 0: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } } +DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 4: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 5: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 6: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 7: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 8: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 9: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 10: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 11: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } +DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered } diff --git a/examples/versatileab/reference/svc-a32-armv6-none-eabi.out b/examples/versatileab/reference/svc-a32-armv6-none-eabi.out new file mode 100644 index 0000000..fe4deb8 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-armv6-none-eabi.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out b/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out new file mode 100644 index 0000000..fe4deb8 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-armv6-none-eabihf.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-a32-thumbv7a-none-eabi.out b/examples/versatileab/reference/svc-a32-thumbv7a-none-eabi.out new file mode 100644 index 0000000..fe4deb8 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-thumbv7a-none-eabi.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-a32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/svc-a32-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..fe4deb8 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-thumbv7a-none-eabihf.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-a32-thumbv7r-none-eabi.out b/examples/versatileab/reference/svc-a32-thumbv7r-none-eabi.out new file mode 100644 index 0000000..fe4deb8 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-thumbv7r-none-eabi.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-a32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/svc-a32-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..fe4deb8 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-thumbv7r-none-eabihf.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0xabcdef +In svc_handler, with arg=0x456789 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-t32-armv6-none-eabi.out b/examples/versatileab/reference/svc-t32-armv6-none-eabi.out new file mode 100644 index 0000000..c9edfeb --- /dev/null +++ b/examples/versatileab/reference/svc-t32-armv6-none-eabi.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out b/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out new file mode 100644 index 0000000..c9edfeb --- /dev/null +++ b/examples/versatileab/reference/svc-t32-armv6-none-eabihf.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-t32-thumbv7a-none-eabi.out b/examples/versatileab/reference/svc-t32-thumbv7a-none-eabi.out new file mode 100644 index 0000000..c9edfeb --- /dev/null +++ b/examples/versatileab/reference/svc-t32-thumbv7a-none-eabi.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-t32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/svc-t32-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..c9edfeb --- /dev/null +++ b/examples/versatileab/reference/svc-t32-thumbv7a-none-eabihf.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-t32-thumbv7r-none-eabi.out b/examples/versatileab/reference/svc-t32-thumbv7r-none-eabi.out new file mode 100644 index 0000000..c9edfeb --- /dev/null +++ b/examples/versatileab/reference/svc-t32-thumbv7r-none-eabi.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/svc-t32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/svc-t32-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..c9edfeb --- /dev/null +++ b/examples/versatileab/reference/svc-t32-thumbv7r-none-eabihf.out @@ -0,0 +1,4 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-armv4t-none-eabi.out b/examples/versatileab/reference/syscall-armv4t-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-armv4t-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-armv5te-none-eabi.out b/examples/versatileab/reference/syscall-armv5te-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-armv5te-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-armv6-none-eabi.out b/examples/versatileab/reference/syscall-armv6-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-armv6-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-armv6-none-eabihf.out b/examples/versatileab/reference/syscall-armv6-none-eabihf.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-armv6-none-eabihf.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-armv7a-none-eabi.out b/examples/versatileab/reference/syscall-armv7a-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-armv7a-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-armv7a-none-eabihf.out b/examples/versatileab/reference/syscall-armv7a-none-eabihf.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-armv7a-none-eabihf.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-armv7r-none-eabi.out b/examples/versatileab/reference/syscall-armv7r-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-armv7r-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-armv7r-none-eabihf.out b/examples/versatileab/reference/syscall-armv7r-none-eabihf.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-armv7r-none-eabihf.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-thumbv4t-none-eabi.out b/examples/versatileab/reference/syscall-thumbv4t-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-thumbv4t-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-thumbv5te-none-eabi.out b/examples/versatileab/reference/syscall-thumbv5te-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-thumbv5te-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-thumbv7a-none-eabi.out b/examples/versatileab/reference/syscall-thumbv7a-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-thumbv7a-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-thumbv7a-none-eabihf.out b/examples/versatileab/reference/syscall-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-thumbv7a-none-eabihf.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-thumbv7r-none-eabi.out b/examples/versatileab/reference/syscall-thumbv7r-none-eabi.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-thumbv7r-none-eabi.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/syscall-thumbv7r-none-eabihf.out b/examples/versatileab/reference/syscall-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..4055ecd --- /dev/null +++ b/examples/versatileab/reference/syscall-thumbv7r-none-eabihf.out @@ -0,0 +1,3 @@ +x = 1, y = 2, z = 3.000 +Syscalls all look OK, printing local variables... +x = 1, y = 2, z = 3.000 diff --git a/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-armv6-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabi.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-thumbv7a-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabi.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-thumbv7r-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-armv6-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabi.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabihf.out b/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabihf.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-thumbv7a-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabi.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabihf.out b/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabihf.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-thumbv7r-none-eabihf.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/rust-toolchain.toml b/examples/versatileab/rust-toolchain.toml index cf1e917..1373346 100644 --- a/examples/versatileab/rust-toolchain.toml +++ b/examples/versatileab/rust-toolchain.toml @@ -1,5 +1,5 @@ [toolchain] -channel = "nightly-2026-01-02" +channel = "nightly-2026-01-26" targets = [ "armv7r-none-eabi", "armv7r-none-eabihf", diff --git a/examples/versatileab/src/bin/prefetch-exception-a32.rs b/examples/versatileab/src/bin/prefetch-exception-a32.rs index 0dd67aa..b1c913a 100644 --- a/examples/versatileab/src/bin/prefetch-exception-a32.rs +++ b/examples/versatileab/src/bin/prefetch-exception-a32.rs @@ -63,7 +63,8 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize { if cfg!(not(any( arm_architecture = "v4t", - arm_architecture = "v5te" + arm_architecture = "v5te", + arm_architecture = "v6" ))) { let ifar = Ifar::read(); println!("IFAR (Faulting Address Register): {:?}", ifar); diff --git a/examples/versatileab/src/bin/prefetch-exception-t32.rs b/examples/versatileab/src/bin/prefetch-exception-t32.rs index ab9631c..996b5f9 100644 --- a/examples/versatileab/src/bin/prefetch-exception-t32.rs +++ b/examples/versatileab/src/bin/prefetch-exception-t32.rs @@ -63,7 +63,8 @@ unsafe fn prefetch_abort_handler(addr: usize) -> usize { if cfg!(not(any( arm_architecture = "v4t", - arm_architecture = "v5te" + arm_architecture = "v5te", + arm_architecture = "v6" ))) { let ifar = Ifar::read(); println!("IFAR (Faulting Address Register): {:?}", ifar); diff --git a/examples/versatileab/src/bin/svc-a32.rs b/examples/versatileab/src/bin/svc-a32.rs index b660067..49c4425 100644 --- a/examples/versatileab/src/bin/svc-a32.rs +++ b/examples/versatileab/src/bin/svc-a32.rs @@ -23,12 +23,13 @@ fn main() -> ! { /// This is our SVC exception handler #[exception(SupervisorCall)] -fn svc_handler(arg: u32) { +fn svc_handler(arg: u32, _frame: &aarch32_rt::Frame) -> u32 { println!("In svc_handler, with arg=0x{:06x}", arg); if arg == 0xABCDEF { // test nested SVC calls do_svc2(); } + 0 } #[instruction_set(arm::a32)] diff --git a/examples/versatileab/src/bin/svc-t32.rs b/examples/versatileab/src/bin/svc-t32.rs index 6b22c17..86017d1 100644 --- a/examples/versatileab/src/bin/svc-t32.rs +++ b/examples/versatileab/src/bin/svc-t32.rs @@ -16,51 +16,28 @@ fn main() -> ! { let y = x + 1; let z = (y as f64) * 1.5; println!("x = {}, y = {}, z = {:0.3}", x, y, z); - unsafe { - svc12_from_t32(); - } + do_svc1(); println!("x = {}, y = {}, z = {:0.3}", x, y, z); semihosting::process::exit(0); } /// This is our SVC exception handler #[exception(SupervisorCall)] -fn svc_handler(arg: u32) { +fn svc_handler(arg: u32, _frame: &aarch32_rt::Frame) -> u32 { println!("In svc_handler, with arg=0x{:06x}", arg); if arg == 0x12 { // test nested SVC calls - unsafe { - svc34_from_t32(); - } + do_svc2(); } + 0 } -// These functions are written in assembly -extern "C" { - fn svc12_from_t32(); - fn svc34_from_t32(); +#[instruction_set(arm::t32)] +fn do_svc1() { + aarch32_cpu::svc!(0x12); } -core::arch::global_asm!( - r#" - // fn svc12_from_t32(); - .thumb - .global svc12_from_t32 - .type svc12_from_t32, %function - svc12_from_t32: - push {{ r7, lr }} - svc 0x12 - pop {{ r7, pc }} - .size svc12_from_t32, . - svc12_from_t32 - - // fn svc34_from_t32(); - .thumb - .global svc34_from_t32 - .type svc34_from_t32, %function - svc34_from_t32: - push {{ r7, lr }} - svc 0x34 - pop {{ r7, pc }} - .size svc34_from_t32, . - svc34_from_t32 -"# -); +#[instruction_set(arm::t32)] +fn do_svc2() { + aarch32_cpu::svc!(0x34); +} diff --git a/examples/versatileab/src/bin/syscall.rs b/examples/versatileab/src/bin/syscall.rs new file mode 100644 index 0000000..1316e4b --- /dev/null +++ b/examples/versatileab/src/bin/syscall.rs @@ -0,0 +1,62 @@ +//! Syscall example +//! +//! * Syscall 0xF0 takes no arguments and returns: 0x1000_0000 +//! * Syscall 0xF1 takes one argument and returns: 0x1000_0000 + (arg0) +//! * Syscall 0xF2 takes two arguments and returns: 0x1000_0000 + (arg0) + (arg1 << 4) +//! * Syscall 0xF3 takes three arguments and returns: 0x1000_0000 + (arg0) + (arg1 << 4) + (arg2 << 8) +//! * Syscall 0xF4 takes four arguments and returns: 0x1000_0000 + (arg0) + (arg1 << 4) + (arg2 << 8) + (arg3 << 12) + +#![no_std] +#![no_main] + +use aarch32_rt::{entry, exception}; +use semihosting::println; +use versatileab as _; + +/// The entry-point to the Rust application. +/// +/// It is called by the start-up. +#[entry] +fn main() -> ! { + let x = 1; + let y = x + 1; + let z = (y as f64) * 1.5; + println!("x = {}, y = {}, z = {:0.3}", x, y, z); + + let retval = aarch32_cpu::svc4!(0xF4, 0xE000_0001, 0xE000_0002, 0xE000_0003, 0xE000_0004); + if retval != 0xF000_4321 { + panic!("Wanted 0xF000_4321, got {:08x}", retval); + } + let retval = aarch32_cpu::svc3!(0xF3, 0xE000_0001, 0xE000_0002, 0xE000_0003); + if retval != 0xF000_0321 { + panic!("Wanted 0xF000_0321, got {:08x}", retval); + } + let retval = aarch32_cpu::svc2!(0xF2, 0xE000_0001, 0xE000_0002); + if retval != 0xF000_0021 { + panic!("Wanted 0xF000_0021, got {:08x}", retval); + } + let retval = aarch32_cpu::svc1!(0xF1, 0xE000_0001); + if retval != 0xF000_0001 { + panic!("Wanted 0xF000_0001, got {:08x}", retval); + } + let retval = aarch32_cpu::svc!(0xF0); + if retval != 0x1000_0000 { + panic!("Wanted 0x1000_0000, got {:08x}", retval); + } + println!("Syscalls all look OK, printing local variables..."); + println!("x = {}, y = {}, z = {:0.3}", x, y, z); + semihosting::process::exit(0); +} + +/// This is our syscall handler +#[exception(SupervisorCall)] +fn svc_handler(arg: u32, frame: &aarch32_rt::Frame) -> u32 { + match arg { + 0xF0 => 0x1000_0000, + 0xF1 => 0x1000_0000 + frame.r0, + 0xF2 => 0x1000_0000 + frame.r0 + (frame.r1 << 4), + 0xF3 => 0x1000_0000 + frame.r0 + (frame.r1 << 4) + (frame.r2 << 8), + 0xF4 => 0x1000_0000 + frame.r0 + (frame.r1 << 4) + (frame.r2 << 8) + (frame.r3 << 12), + _ => 0xDEADC0DE, + } +} diff --git a/justfile b/justfile index 52e7f3c..f25f54a 100644 --- a/justfile +++ b/justfile @@ -34,21 +34,35 @@ build-all: \ (build-tier3-no-atomics "thumbv4t-none-eabi") \ (build-tier3-no-atomics "armv5te-none-eabi") \ (build-tier3-no-atomics "thumbv5te-none-eabi") \ + (build-tier3-no-atomics "armv6-none-eabi") \ + (build-tier3-no-atomics "thumbv6-none-eabi") \ + (build-tier3-no-atomics "armv6-none-eabihf") \ (build-tier2 "armv7r-none-eabi") \ + (build-tier3 "thumbv7r-none-eabi") \ (build-tier2 "armv7r-none-eabihf") \ + (build-tier3 "thumbv7r-none-eabihf") \ (build-tier2 "armv7a-none-eabi") \ + (build-tier3 "thumbv7a-none-eabi") \ (build-tier2 "armv7a-none-eabihf") \ + (build-tier3 "thumbv7a-none-eabihf") \ (build-tier2 "armv8r-none-eabihf") \ + (build-tier3 "thumbv8r-none-eabihf") \ # Build the arm-targets library build-arm-targets: cd arm-targets && cargo build {{verbose}} -# Builds our workspace with various features, building core from source +# Builds our workspace with various features, building core from source, but skipping anything that requires atomics build-tier3-no-atomics target: cargo build --target {{target}} -Zbuild-std=core {{verbose}} cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-single-core, check-asm" {{verbose}} +# Builds our workspace with various features, building core from source +build-tier3 target: + cargo build --target {{target}} -Zbuild-std=core {{verbose}} + cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-multi-core, check-asm" {{verbose}} + cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-single-core, check-asm" {{verbose}} + # Builds our workspace with various features build-tier2 target: cargo build --target {{target}} {{verbose}} @@ -61,11 +75,19 @@ build-all-examples: \ (build-versatileab-tier3 "thumbv4t-none-eabi") \ (build-versatileab-tier3 "armv5te-none-eabi") \ (build-versatileab-tier3 "thumbv5te-none-eabi") \ + (build-versatileab-tier3 "armv6-none-eabi") \ + (build-versatileab-tier3 "armv6-none-eabihf") \ (build-versatileab-tier2 "armv7r-none-eabi") \ + (build-versatileab-tier3 "thumbv7r-none-eabi") \ (build-versatileab-tier2 "armv7r-none-eabihf") \ + (build-versatileab-tier3 "thumbv7r-none-eabihf") \ (build-versatileab-tier2 "armv7a-none-eabi") \ + (build-versatileab-tier3 "thumbv7a-none-eabi") \ (build-versatileab-tier2 "armv7a-none-eabihf") \ + (build-versatileab-tier3 "thumbv7a-none-eabihf") \ (build-mps3-tier2 "armv8r-none-eabihf") \ + (build-mps3-tier3 "thumbv8r-none-eabihf") \ + # (build-versatileab-tier3 "thumbv6-none-eabi") \ # Builds the Versatile AB examples, building core from source build-versatileab-tier3 target: @@ -75,6 +97,10 @@ build-versatileab-tier3 target: build-versatileab-tier2 target: cd examples/versatileab && cargo build --target={{target}} {{verbose}} +# Builds the MPS3-AN536 examples, building core from source +build-mps3-tier3 target: + cd examples/mps3-an536 && cargo build --target={{target}} -Zbuild-std=core {{verbose}} + # Builds the MPS3-AN536 examples, assuming core has been prebuilt build-mps3-tier2 target: cd examples/mps3-an536 && cargo build --target={{target}} {{verbose}} @@ -141,13 +167,23 @@ test-qemu: ./tests.sh examples/versatileab thumbv4t-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1 ./tests.sh examples/versatileab armv5te-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1 ./tests.sh examples/versatileab thumbv5te-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1 + ./tests.sh examples/versatileab armv6-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1 + ./tests.sh examples/versatileab armv6-none-eabihf -Zbuild-std=core {{verbose}} || FAIL=1 + # ./tests.sh examples/versatileab thumbv6-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1 ./tests.sh examples/versatileab armv7r-none-eabi {{verbose}} || FAIL=1 + ./tests.sh examples/versatileab thumbv7r-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1 ./tests.sh examples/versatileab armv7r-none-eabihf {{verbose}} || FAIL=1 + ./tests.sh examples/versatileab thumbv7r-none-eabihf -Zbuild-std=core {{verbose}} || FAIL=1 ./tests.sh examples/versatileab armv7a-none-eabi {{verbose}} || FAIL=1 + ./tests.sh examples/versatileab thumbv7a-none-eabi -Zbuild-std=core {{verbose}} || FAIL=1 ./tests.sh examples/versatileab armv7a-none-eabihf {{verbose}} || FAIL=1 + ./tests.sh examples/versatileab thumbv7a-none-eabihf -Zbuild-std=core {{verbose}} || FAIL=1 RUSTFLAGS=-Ctarget-feature=+d32 ./tests.sh examples/versatileab armv7a-none-eabihf --features=fpu-d32 --target-dir=target-d32 {{verbose}} || FAIL=1 + RUSTFLAGS=-Ctarget-feature=+d32 ./tests.sh examples/versatileab thumbv7a-none-eabihf -Zbuild-std=core --features=fpu-d32 --target-dir=target-d32 {{verbose}} || FAIL=1 ./tests.sh examples/mps3-an536 armv8r-none-eabihf {{verbose}} || FAIL=1 + ./tests.sh examples/mps3-an536 thumbv8r-none-eabihf -Zbuild-std=core {{verbose}} || FAIL=1 RUSTFLAGS=-Ctarget-cpu=cortex-r52 ./tests.sh examples/mps3-an536 armv8r-none-eabihf --features=fpu-d32 --target-dir=target-d32 {{verbose}} || FAIL=1 + RUSTFLAGS=-Ctarget-cpu=cortex-r52 ./tests.sh examples/mps3-an536 thumbv8r-none-eabihf -Zbuild-std=core --features=fpu-d32 --target-dir=target-d32 {{verbose}} || FAIL=1 if [ "${FAIL}" == "1" ]; then exit 1; fi # Run the special SMP test diff --git a/tests.sh b/tests.sh index 2e947c4..20d14d6 100755 --- a/tests.sh +++ b/tests.sh @@ -38,6 +38,10 @@ my_diff() { # output # - Fix the CRLF line endings in the files on disk, because git adds them to # text files. + if [ "${UPDATE_OUT}" == "1" ]; then + # echo "Copying $file_b to $file_a... in $(pwd)" + cp $file_b $file_a + fi if [ ! -f $1 ]; then echo "File $1 is missing?!" return 1 @@ -47,9 +51,6 @@ my_diff() { else diff <(cat $file_a | tr -d '\r') <(cat $file_b | sed 's~\\\\~/~g') result=$? - if [ "${UPDATE_OUT}" == "1" ]; then - cp $file_b $file_a - fi return $result fi }