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DE10_NANO_SOC_FB.ipregen.rpt
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DE10_NANO_SOC_FB.ipregen.rpt
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IP Upgrade report for DE10_NANO_SOC_FB
Sun May 31 10:35:57 2020
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. IP Upgrade Summary
3. Successfully Upgraded IP Components
4. IP Upgrade Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------+
; IP Upgrade Summary ;
+------------------------------+---------------------------------------------+
; IP Components Upgrade Status ; Passed - Sun May 31 10:35:57 2020 ;
; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
; Revision Name ; DE10_NANO_SOC_FB ;
; Top-level Entity Name ; DE10_TOP ;
; Family ; Cyclone V ;
+------------------------------+---------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Successfully Upgraded IP Components ;
+-------------+----------------+---------+-------------------------------------+----------------------+-------------------------------------+---------+
; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ;
+-------------+----------------+---------+-------------------------------------+----------------------+-------------------------------------+---------+
; soc_system ; Qsys ; 18.1 ; soc_system/synthesis/soc_system.qip ; soc_system.qsys ; soc_system/synthesis/soc_system.qip ; ;
+-------------+----------------+---------+-------------------------------------+----------------------+-------------------------------------+---------+
+---------------------+
; IP Upgrade Messages ;
+---------------------+
Info (11902): Backing up file "soc_system.qsys" to "soc_system.BAK.qsys"
Info (11902): Backing up file "soc_system/synthesis/soc_system.vhd" to "soc_system.BAK.vhd"
Info (11837): Started upgrading IP component Qsys with file "soc_system.qsys"
Info: 2020.05.31.10:34:32 Info: Starting to upgrade the IP cores in the Platform Designer system
Info: 2020.05.31.10:34:32 Info: Finished upgrading the ip cores
Info: 2020.05.31.10:34:47 Info: Saving generation log to /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system
Info: 2020.05.31.10:34:47 Info: Starting: Create block symbol file (.bsf)
Info: 2020.05.31.10:34:47 Info: Loading de10-sky-tracker
Info: 2020.05.31.10:34:47 Info: Reading input file
Info: 2020.05.31.10:34:47 Info: Adding ILC [interrupt_latency_counter 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module ILC
Info: 2020.05.31.10:34:47 Info: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Info: 2020.05.31.10:34:47 Info: Parameterizing module alt_vip_itc_0
Info: 2020.05.31.10:34:47 Info: Adding alt_vip_vfr_hdmi [alt_vip_vfr 14.0]
Info: 2020.05.31.10:34:47 Info: Parameterizing module alt_vip_vfr_hdmi
Info: 2020.05.31.10:34:47 Info: Adding button_pio [altera_avalon_pio 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module button_pio
Info: 2020.05.31.10:34:47 Info: Adding clk_0 [clock_source 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module clk_0
Info: 2020.05.31.10:34:47 Info: Adding clock_bridge_0 [altera_clock_bridge 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module clock_bridge_0
Info: 2020.05.31.10:34:47 Info: Adding dipsw_pio [altera_avalon_pio 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module dipsw_pio
Info: 2020.05.31.10:34:47 Info: Adding f2sdram_only_master [altera_jtag_avalon_master 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module f2sdram_only_master
Info: 2020.05.31.10:34:47 Info: Adding fpga_only_master [altera_jtag_avalon_master 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module fpga_only_master
Info: 2020.05.31.10:34:47 Info: Adding hps_0 [altera_hps 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module hps_0
Info: 2020.05.31.10:34:47 Info: Adding hps_only_master [altera_jtag_avalon_master 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module hps_only_master
Info: 2020.05.31.10:34:47 Info: Adding jtag_uart [altera_avalon_jtag_uart 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module jtag_uart
Info: 2020.05.31.10:34:47 Info: Adding led_pio [altera_avalon_pio 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module led_pio
Info: 2020.05.31.10:34:47 Info: Adding mm_bridge_0 [altera_avalon_mm_bridge 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module mm_bridge_0
Info: 2020.05.31.10:34:47 Info: Adding sysid_qsys [altera_avalon_sysid_qsys 18.1]
Info: 2020.05.31.10:34:47 Info: Parameterizing module sysid_qsys
Info: 2020.05.31.10:34:47 Info: Building connections
Info: 2020.05.31.10:34:47 Info: Parameterizing connections
Info: 2020.05.31.10:34:47 Info: Validating
Info: 2020.05.31.10:34:52 Info: Done reading input file
Warning: 2020.05.31.10:34:53 Warning: soc_system.alt_vip_vfr_hdmi: The module properties SIMULATION_MODEL_IN_VERILOG and SIMULATION_MODEL_IN_VHDL can not both be set when using the SIMULATION file property: src_hdl/alt_vipvfr131_vfr.v, src_hdl/alt_vipvfr131_vfr_controller.v, src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v, src_hdl/alt_vipvfr131_prc.v, src_hdl/alt_vipvfr131_prc_core.v, src_hdl/alt_vipvfr131_prc_read_master.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_package.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_master.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_unpack_data.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_slave.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_stream_output.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_general_fifo.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_one_bit_delay.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_logic_fifo.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl
Info: 2020.05.31.10:34:53 Info: soc_system.button_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: 2020.05.31.10:34:53 Info: soc_system.dipsw_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: 2020.05.31.10:34:53 Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0 m = 63
Info: 2020.05.31.10:34:53 Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
Info: 2020.05.31.10:34:53 Info: soc_system.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: 2020.05.31.10:34:53 Info: soc_system.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: 2020.05.31.10:34:53 Info: soc_system.sysid_qsys: Time stamp will be automatically updated when this component is generated.
Warning: 2020.05.31.10:34:53 Warning: soc_system.alt_vip_vfr_hdmi: Interrupt sender alt_vip_vfr_hdmi.interrupt_sender is not connected to an interrupt receiver
Info: 2020.05.31.10:34:53 Info: qsys-generate succeeded.
Info: 2020.05.31.10:34:53 Info: Finished: Create block symbol file (.bsf)
Info: 2020.05.31.10:34:53 Info:
Info: 2020.05.31.10:34:53 Info: Starting: Create HDL design files for synthesis
Info: 2020.05.31.10:34:53 Info: Loading de10-sky-tracker
Info: 2020.05.31.10:34:53 Info: Reading input file
Info: 2020.05.31.10:34:53 Info: Adding ILC [interrupt_latency_counter 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module ILC
Info: 2020.05.31.10:34:53 Info: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Info: 2020.05.31.10:34:53 Info: Parameterizing module alt_vip_itc_0
Info: 2020.05.31.10:34:53 Info: Adding alt_vip_vfr_hdmi [alt_vip_vfr 14.0]
Info: 2020.05.31.10:34:53 Info: Parameterizing module alt_vip_vfr_hdmi
Info: 2020.05.31.10:34:53 Info: Adding button_pio [altera_avalon_pio 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module button_pio
Info: 2020.05.31.10:34:53 Info: Adding clk_0 [clock_source 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module clk_0
Info: 2020.05.31.10:34:53 Info: Adding clock_bridge_0 [altera_clock_bridge 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module clock_bridge_0
Info: 2020.05.31.10:34:53 Info: Adding dipsw_pio [altera_avalon_pio 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module dipsw_pio
Info: 2020.05.31.10:34:53 Info: Adding f2sdram_only_master [altera_jtag_avalon_master 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module f2sdram_only_master
Info: 2020.05.31.10:34:53 Info: Adding fpga_only_master [altera_jtag_avalon_master 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module fpga_only_master
Info: 2020.05.31.10:34:53 Info: Adding hps_0 [altera_hps 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module hps_0
Info: 2020.05.31.10:34:53 Info: Adding hps_only_master [altera_jtag_avalon_master 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module hps_only_master
Info: 2020.05.31.10:34:53 Info: Adding jtag_uart [altera_avalon_jtag_uart 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module jtag_uart
Info: 2020.05.31.10:34:53 Info: Adding led_pio [altera_avalon_pio 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module led_pio
Info: 2020.05.31.10:34:53 Info: Adding mm_bridge_0 [altera_avalon_mm_bridge 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module mm_bridge_0
Info: 2020.05.31.10:34:53 Info: Adding sysid_qsys [altera_avalon_sysid_qsys 18.1]
Info: 2020.05.31.10:34:53 Info: Parameterizing module sysid_qsys
Info: 2020.05.31.10:34:53 Info: Building connections
Info: 2020.05.31.10:34:53 Info: Parameterizing connections
Info: 2020.05.31.10:34:53 Info: Validating
Info: 2020.05.31.10:34:58 Info: Done reading input file
Warning: 2020.05.31.10:34:59 Warning: soc_system.alt_vip_vfr_hdmi: The module properties SIMULATION_MODEL_IN_VERILOG and SIMULATION_MODEL_IN_VHDL can not both be set when using the SIMULATION file property: src_hdl/alt_vipvfr131_vfr.v, src_hdl/alt_vipvfr131_vfr_controller.v, src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v, src_hdl/alt_vipvfr131_prc.v, src_hdl/alt_vipvfr131_prc_core.v, src_hdl/alt_vipvfr131_prc_read_master.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_package.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_master.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_unpack_data.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_avalon_mm_slave.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_stream_output.v, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_general_fifo.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_one_bit_delay.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl/alt_vipvfr131_common_logic_fifo.vhd, /opt/intelFPGA/lite/18.1/ip/altera/frame_reader/common_hdl
Info: 2020.05.31.10:34:59 Info: soc_system.button_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2020.05.31.10:34:59 Info: soc_system.dipsw_pio: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: 2020.05.31.10:34:59 Info: soc_system.hps_0: HPS Main PLL counter settings: n = 0 m = 63
Info: 2020.05.31.10:34:59 Info: soc_system.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
Info: 2020.05.31.10:34:59 Info: soc_system.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
2020.05.31.10:34:59 Info: soc_system.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: 2020.05.31.10:34:59 Info: soc_system.sysid_qsys: Time stamp will be automatically updated when this component is generated.
Warning: 2020.05.31.10:34:59 Warning: soc_system.alt_vip_vfr_hdmi: Interrupt sender alt_vip_vfr_hdmi.interrupt_sender is not connected to an interrupt receiver
Info: 2020.05.31.10:35:16 Info: soc_system: Generating soc_system "soc_system" for QUARTUS_SYNTH
Info: 2020.05.31.10:35:19 Info: Interconnect is inserted between master hps_0.h2f_lw_axi_master and slave mm_bridge_0.s0 because the master is of type axi and the slave is of type avalon.
Info: 2020.05.31.10:35:20 Info: Inserting clock-crossing logic between cmd_demux.src2 and cmd_mux_002.sink0
Info: 2020.05.31.10:35:20 Info: Inserting clock-crossing logic between rsp_demux_002.src0 and rsp_mux.sink2
Info: 2020.05.31.10:35:20 Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has address signal 32 bit wide, but the slave is 27 bit wide.
Info: 2020.05.31.10:35:20 Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has readdata signal 32 bit wide, but the slave is 256 bit wide.
Info: 2020.05.31.10:35:20 Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has writedata signal 32 bit wide, but the slave is 256 bit wide.
Info: 2020.05.31.10:35:20 Info: Interconnect is inserted between master f2sdram_only_master.master and slave hps_0.f2h_sdram0_data because the master has byteenable signal 4 bit wide, but the slave is 32 bit wide.
Warning: 2020.05.31.10:35:20 Warning: hps_0.f2h_irq0: Cannot connect clock for irq_mapper_001.sender
Warning: 2020.05.31.10:35:20 Warning: hps_0.f2h_irq0: Cannot connect reset for irq_mapper_001.sender
Warning: 2020.05.31.10:35:20 Warning: hps_0.f2h_irq1: Cannot connect clock for irq_mapper_002.sender
Warning: 2020.05.31.10:35:20 Warning: hps_0.f2h_irq1: Cannot connect reset for irq_mapper_002.sender
Info: 2020.05.31.10:35:23 Info: ILC: "soc_system" instantiated interrupt_latency_counter "ILC"
Warning: 2020.05.31.10:35:24 Warning: Can't contact license server "[email protected]" -- this server will be ignored.
Warning: 2020.05.31.10:35:24 Warning: Can't contact license server "[email protected]" -- this server will be ignored.
Warning: 2020.05.31.10:35:25 Warning: Can't contact license server "[email protected]" -- this server will be ignored.
Warning: 2020.05.31.10:35:26 Warning: Can't contact license server "[email protected]" -- this server will be ignored.
Info: 2020.05.31.10:35:26 Info: alt_vip_itc_0: "soc_system" instantiated alt_vip_itc "alt_vip_itc_0"
Warning: 2020.05.31.10:35:27 Warning: Can't contact license server "[email protected]" -- this server will be ignored.
Warning: 2020.05.31.10:35:27 Warning: Can't contact license server "[email protected]" -- this server will be ignored.
Warning: 2020.05.31.10:35:27 Warning: Can't contact license server "[email protected]" -- this server will be ignored.
Warning: 2020.05.31.10:35:28 Warning: Can't contact license server "[email protected]" -- this server will be ignored.
Info: 2020.05.31.10:35:28 Info: alt_vip_vfr_hdmi: "soc_system" instantiated alt_vip_vfr "alt_vip_vfr_hdmi"
Info: 2020.05.31.10:35:28 Info: button_pio: Starting RTL generation for module 'soc_system_button_pio'
Info: 2020.05.31.10:35:28 Info: button_pio: Generation command is [exec /opt/intelFPGA/lite/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/lite/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_button_pio --dir=/tmp/alt8413_117280363047037072.dir/0007_button_pio_gen/ --quartus_dir=/opt/intelFPGA/lite/18.1/quartus --verilog --config=/tmp/alt8413_117280363047037072.dir/0007_button_pio_gen/
Info: 2020.05.31.10:35:28 Info: button_pio: Done RTL generation for module 'soc_system_button_pio'
Info: 2020.05.31.10:35:28 Info: button_pio: "soc_system" instantiated altera_avalon_pio "button_pio"
Info: 2020.05.31.10:35:28 Info: dipsw_pio: Starting RTL generation for module 'soc_system_dipsw_pio'
Info: 2020.05.31.10:35:28 Info: dipsw_pio: Generation command is [exec /opt/intelFPGA/lite/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/lite/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_dipsw_pio --dir=/tmp/alt8413_117280363047037072.dir/0008_dipsw_pio_gen/ --quartus_dir=/opt/intelFPGA/lite/18.1/quartus --verilog --config=/tmp/alt8413_117280363047037072.dir/0008_dipsw_pio_gen/
Info: 2020.05.31.10:35:29 Info: dipsw_pio: Done RTL generation for module 'soc_system_dipsw_pio'
Info: 2020.05.31.10:35:29 Info: dipsw_pio: "soc_system" instantiated altera_avalon_pio "dipsw_pio"
Info: 2020.05.31.10:35:29 Info: f2sdram_only_master: "soc_system" instantiated altera_jtag_avalon_master "f2sdram_only_master"
Info: 2020.05.31.10:35:29 Info: hps_0: "Running for module: hps_0"
Info: 2020.05.31.10:35:29 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 63
Info: 2020.05.31.10:35:29 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
Info: 2020.05.31.10:35:30 Info: hps_0: "soc_system" instantiated altera_hps "hps_0"
Info: 2020.05.31.10:35:30 Info: jtag_uart: Starting RTL generation for module 'soc_system_jtag_uart'
Info: 2020.05.31.10:35:30 Info: jtag_uart: Generation command is [exec /opt/intelFPGA/lite/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/lite/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=soc_system_jtag_uart --dir=/tmp/alt8413_117280363047037072.dir/0009_jtag_uart_gen/ --quartus_dir=/opt/intelFPGA/lite/18.1/quartus --verilog --config=/tmp/alt8413_117280363047037072.dir/0009_jtag_uart_gen/
Info: 2020.05.31.10:35:30 Info: jtag_uart: Done RTL generation for module 'soc_system_jtag_uart'
Info: 2020.05.31.10:35:30 Info: jtag_uart: "soc_system" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: 2020.05.31.10:35:30 Info: led_pio: Starting RTL generation for module 'soc_system_led_pio'
Info: 2020.05.31.10:35:30 Info: led_pio: Generation command is [exec /opt/intelFPGA/lite/18.1/quartus/linux64/perl/bin/perl -I /opt/intelFPGA/lite/18.1/quartus/linux64/perl/lib -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin/europa -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA/lite/18.1/quartus/sopc_builder/bin -I /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA/lite/18.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=soc_system_led_pio --dir=/tmp/alt8413_117280363047037072.dir/0010_led_pio_gen/ --quartus_dir=/opt/intelFPGA/lite/18.1/quartus --verilog --config=/tmp/alt8413_117280363047037072.dir/0010_led_pio_gen/
Info: 2020.05.31.10:35:30 Info: led_pio: Done RTL generation for module 'soc_system_led_pio'
Info: 2020.05.31.10:35:30 Info: led_pio: "soc_system" instantiated altera_avalon_pio "led_pio"
Info: 2020.05.31.10:35:30 Info: mm_bridge_0: "soc_system" instantiated altera_avalon_mm_bridge "mm_bridge_0"
Info: 2020.05.31.10:35:30 Info: sysid_qsys: "soc_system" instantiated altera_avalon_sysid_qsys "sysid_qsys"
Info: 2020.05.31.10:35:31 Info: mm_interconnect_0: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: 2020.05.31.10:35:31 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:31 Info: mm_interconnect_1: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: 2020.05.31.10:35:31 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:31 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:31 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:31 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:31 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:31 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:31 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:32 Info: mm_interconnect_2: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_2"
Info: 2020.05.31.10:35:32 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: 2020.05.31.10:35:32 Info: mm_interconnect_3: "soc_system" instantiated altera_mm_interconnect "mm_interconnect_3"
Info: 2020.05.31.10:35:32 Info: irq_mapper: "soc_system" instantiated altera_irq_mapper "irq_mapper"
Info: 2020.05.31.10:35:32 Info: irq_mapper_001: "soc_system" instantiated altera_irq_mapper "irq_mapper_001"
Info: 2020.05.31.10:35:32 Info: irq_mapper_002: "soc_system" instantiated altera_irq_mapper "irq_mapper_002"
Info: 2020.05.31.10:35:32 Info: rst_controller: "soc_system" instantiated altera_reset_controller "rst_controller"
Info: 2020.05.31.10:35:32 Info: jtag_phy_embedded_in_jtag_master: "f2sdram_only_master" instantiated altera_jtag_dc_streaming "jtag_phy_embedded_in_jtag_master"
Info: 2020.05.31.10:35:32 Info: timing_adt: "f2sdram_only_master" instantiated timing_adapter "timing_adt"
Info: 2020.05.31.10:35:32 Info: fifo: "f2sdram_only_master" instantiated altera_avalon_sc_fifo "fifo"
Info: 2020.05.31.10:35:32 Info: b2p: "f2sdram_only_master" instantiated altera_avalon_st_bytes_to_packets "b2p"
Info: 2020.05.31.10:35:32 Info: p2b: "f2sdram_only_master" instantiated altera_avalon_st_packets_to_bytes "p2b"
Info: 2020.05.31.10:35:32 Info: transacto: "f2sdram_only_master" instantiated altera_avalon_packets_to_master "transacto"
Info: 2020.05.31.10:35:32 Info: b2p_adapter: "f2sdram_only_master" instantiated channel_adapter "b2p_adapter"
Info: 2020.05.31.10:35:32 Info: p2b_adapter: "f2sdram_only_master" instantiated channel_adapter "p2b_adapter"
Info: 2020.05.31.10:35:32 Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
Info: 2020.05.31.10:35:32 Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
Info: 2020.05.31.10:35:32 Info: alt_vip_vfr_hdmi_avalon_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "alt_vip_vfr_hdmi_avalon_master_translator"
Info: 2020.05.31.10:35:32 Info: alt_vip_vfr_hdmi_avalon_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "alt_vip_vfr_hdmi_avalon_master_agent"
Info: 2020.05.31.10:35:32 Info: hps_0_f2h_axi_slave_agent: "mm_interconnect_0" instantiated altera_merlin_axi_slave_ni "hps_0_f2h_axi_slave_agent"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: 2020.05.31.10:35:32 Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: 2020.05.31.10:35:32 Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: 2020.05.31.10:35:32 Info: alt_vip_vfr_hdmi_avalon_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "alt_vip_vfr_hdmi_avalon_master_limiter"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: hps_0_f2h_axi_slave_wr_burst_adapter: "mm_interconnect_0" instantiated altera_merlin_burst_adapter "hps_0_f2h_axi_slave_wr_burst_adapter"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: 2020.05.31.10:35:32 Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: 2020.05.31.10:35:32 Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: 2020.05.31.10:35:32 Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: hps_only_master_master_cmd_width_adapter: "mm_interconnect_0" instantiated altera_merlin_width_adapter "hps_only_master_master_cmd_width_adapter"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: mm_bridge_0_s0_translator: "mm_interconnect_1" instantiated altera_merlin_slave_translator "mm_bridge_0_s0_translator"
Info: 2020.05.31.10:35:32 Info: hps_0_h2f_lw_axi_master_agent: "mm_interconnect_1" instantiated altera_merlin_axi_master_ni "hps_0_h2f_lw_axi_master_agent"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: mm_bridge_0_s0_agent: "mm_interconnect_1" instantiated altera_merlin_slave_agent "mm_bridge_0_s0_agent"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
Info: 2020.05.31.10:35:32 Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
Info: 2020.05.31.10:35:32 Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: 2020.05.31.10:35:32 Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: 2020.05.31.10:35:32 Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: 2020.05.31.10:35:32 Info: router: "mm_interconnect_2" instantiated altera_merlin_router "router"
Info: 2020.05.31.10:35:32 Info: router_001: "mm_interconnect_2" instantiated altera_merlin_router "router_001"
Info: 2020.05.31.10:35:32 Info: router_002: "mm_interconnect_2" instantiated altera_merlin_router "router_002"
Info: 2020.05.31.10:35:32 Info: router_004: "mm_interconnect_2" instantiated altera_merlin_router "router_004"
Info: 2020.05.31.10:35:32 Info: cmd_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: 2020.05.31.10:35:32 Info: cmd_demux_001: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: 2020.05.31.10:35:32 Info: cmd_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "cmd_mux"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: cmd_mux_002: "mm_interconnect_2" instantiated altera_merlin_multiplexer "cmd_mux_002"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: rsp_demux: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: 2020.05.31.10:35:32 Info: rsp_demux_002: "mm_interconnect_2" instantiated altera_merlin_demultiplexer "rsp_demux_002"
Info: 2020.05.31.10:35:32 Info: rsp_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: rsp_mux_001: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: crosser: "mm_interconnect_2" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: router: "mm_interconnect_3" instantiated altera_merlin_router "router"
Info: 2020.05.31.10:35:32 Info: router_001: "mm_interconnect_3" instantiated altera_merlin_router "router_001"
Info: 2020.05.31.10:35:32 Info: cmd_demux: "mm_interconnect_3" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: 2020.05.31.10:35:32 Info: cmd_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "cmd_mux"
2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: rsp_mux: "mm_interconnect_3" instantiated altera_merlin_multiplexer "rsp_mux"
Info: 2020.05.31.10:35:32 Info: Reusing file /media/2TB/workspace/rsarwar/work/de10-nano/de10-sky-tracker/soc_system/synthesis/submodules
Info: 2020.05.31.10:35:32 Info: avalon_st_adapter: "mm_interconnect_3" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: 2020.05.31.10:35:50 Info: border: "hps_io" instantiated altera_interface_generator "border"
Info: 2020.05.31.10:35:50 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: 2020.05.31.10:35:50 Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: 2020.05.31.10:35:50 Info: soc_system: Done "soc_system" with 75 modules, 178 files
Info: 2020.05.31.10:35:50 Info: qsys-generate succeeded.
Info: 2020.05.31.10:35:50 Info: Finished: Create HDL design files for synthesis
Info (11131): Completed upgrading IP component Qsys with file "soc_system.qsys"
Info (23030): Evaluation of Tcl script /opt/intelFPGA/lite/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 17 warnings
Info: Peak virtual memory: 1122 megabytes
Info: Processing ended: Sun May 31 10:36:04 2020
Info: Elapsed time: 00:01:57
Info: Total CPU time (on all processors): 00:04:58