Optimisations of ALU and CPU + start of clmul[rh] support

rob-ng15 · rob-ng15 · commit 7492fd0c64e2 · 2023-04-03T07:33:13.000+01:00
Port (and correct) clmul support from RV32, expand to 64 bits, detect in cpu_functionblocks.si and pass to cpuexecuteSLOWPATH.

Simplify wait state generator and result/frd/FPUnewflags in cpuexecuteFPU.

Remove a wait state in the CPU fetch unit, plus simplify blocks.

Simplify blocks in CPU load unit.
diff --git a/README.md b/README.md
@@ -100,12 +100,16 @@ The image displayed below, shows our PAWS, for whom the project is named. From l
 
 
 ## OUTRUN (DEMO)
-An implementation of https://www.lexaloffle.com/bbs/?tid=35767 using the GPU and DrawList2D from the PAWSv2 library, and the floating-point unit. The car is a pixelblock sprite ported from http://www.dizionariovideogiochi.it/doku.php?id=out_run with no animation. The cityscape and clouds are drawn on the two tilemaps. There are vehicles running in front of the cityscape that are just visible in one frame of the demonstration using sprites. Press FIRE2 to exit.
+An implementation of https://www.lexaloffle.com/bbs/?tid=35767 using the GPU and DrawList2D from the PAWSv2 library, and the floating-point unit. The car is a pixelblock sprite ported from https://www.spriters-resource.com/genesis_32x_scd/outrun/sheet/25458/ with no animation. The cityscape and clouds are drawn on the two tilemaps. There are vehicles running in front of the cityscape that are just visible in one frame of the demonstration using sprites. Press FIRE2 to exit.
 <br>
 ![OUTRUN](Reference/Graphics/OUTRUN-1.jpg)
 ![OUTRUN](Reference/Graphics/OUTRUN-2.jpg)
 ![OUTRUN](Reference/Graphics/OUTRUN-3.jpg)
 
+A full view of the cityscape backdrop (forced, not normally available), showing the background sprites.
+
+![OUTRUN Full view of the cityscape](Reference/Graphics/OUTRUN-4.jpg)
+
 ## PACMAN (GAMES)
 A conversion of https://github.com/floooh/pacman.c to the PAWSv2 graphics, sound and input system.
 <br>
diff --git a/RV32/ALU.si b/RV32/ALU.si
@@ -386,7 +386,7 @@ unit aluCLMUL(
     uint6   stopat <:: function3[0,1] ? 32 : 31;
     uint6   count = uninitialised;
     uint1   update = uninitialised;
-    uint32  resultNEXT <:: result ^ ( ( function3[1,1] ) ? ( sourceReg1 >> ( ( function3[0,1] ? 31 : 32 ) - count ) ) : ( sourceReg1 << count ) );
+    uint324  resultNEXT <:: result ^ ( ( function3[1,1] ) ? ( sourceReg1 >> ( ( function3[0,1] ? 32 : 31 ) - count ) ) : ( sourceReg1 << count ) );
     update := 0;
 
     algorithm <autorun> {
diff --git a/RV64/ALU.si b/RV64/ALU.si
@@ -345,6 +345,40 @@ unit aludivision(
                             function3[1,1] ? sourceReg1 : 64hffffffffffffffff;                                            // DIVIDE BY ZERO, dividend if remainder, -1 if quotient
 }
 
+// ALU FOR CARRYLESS MULTIPLY FROM B-EXTENSION
+unit alucarrylessmultiply(
+    input   uint1   start,
+    output  uint1   busy(0),
+    input   uint2   function3,
+    input   uint64  sourceReg1,
+    input   uint64  sourceReg2,
+    output  uint64  result
+) <reginputs> {
+    uint64  resultNEXT <:: result ^ ( ( function3[1,1] ) ? ( sourceReg1 >> ( ( function3[0,1] ? 64 : 63 ) - count ) ) : ( sourceReg1 << count ) );
+    uint7   startat <:: &function3;
+    uint7   stopat <:: function3[0,1] ? 64 : 63;
+    uint7   count = uninitialised;
+    uint1   update = uninitialised;
+    update := 0;
+
+    algorithm <autorun> {
+        while(1) {
+            if( start ) { busy = 1; while( count != stopat ) { update = 1; } busy = 0; }
+        }
+    }
+
+    always_after {
+        if( start ) {
+            result = 0; count = start;
+        } else {
+            if( update ) {
+                if( sourceReg2[ count, 1 ] ) { result = resultNEXT; }
+                count = count + 1;
+            }
+        }
+    }
+}
+
 // INTEGER COMPARISONS
 unit integercomparisons(
     input   uint64  sourceReg1,
diff --git a/RV64/CPU.si b/RV64/CPU.si
@@ -110,6 +110,7 @@ unit PAWSCPU(
         memoryinput <: memoryinput,
         incCSRinstret <: COMMIT,
         isALUM <: RV64CONTROL.IS_ALUM,
+        isALUCLM <: RV64CONTROL.IS_ALUCLM,
         isCSR <: RV64CONTROL.IS_CSR,
         isATOMIC <: RV64CONTROL.IS_ATOMIC,
         FPUnewflags <: EXECUTEFPU.FPUnewflags,
@@ -372,6 +373,7 @@ unit cpuexecuteSLOWPATH(
     input   uint1   isCSR,
     input   uint1   isATOMIC,
     input   uint1   isALUM,
+    input   uint1   isALUCLM,
     output  uint8   FPUflags,
     input   uint5   FPUnewflags,
     input   uint1   CSRupdateFPUflags
@@ -530,31 +532,20 @@ unit cpuexecuteFPU(
     FPUCALC.start := fpucalc & start; CSRupdateFPUflags := 0;
 
     algorithm <autorun> {
-        // PROVIDE WAIT STATE FOR APPROPRIATE OPERATION
         while(1) {
             if( start ) {
-                onehot( operation ) {
-                    default: {}                                                                                                  // FPU COMPARE, MIN/MAX, CLASS, MOVE, CONVERT
-                    case 2: { while( FPUCALC.busy ) {} }                                                                        // FPU CALCULATIONS
-                }
+                busy = 1;
+                if( operation[2,1] ) { while( FPUCALC.busy ) {} }                                                               // WAIT STATE FOR CALCULATIONS
                 busy = 0;
                 CSRupdateFPUflags = 1;
             }
         }
     }
 
-    // COLLECT THE APPROPRIATE RESULT
     always_after {
-        { if( start ) { busy = 1; } }
-        {
-            onehot( operation ) {
-                case 0: { result = FPUFAST.result; }
-                case 1: { result = convertresult; }
-                case 2: { result = FPUCALC.result; }
-            }
-        }
-        { frd = fpuconvert ? ( |converttype[0,2] ) : fpucalc ? 1 : FPUFAST.frd; }
-        { FPUnewflags = fpuconvert ? convertflags : fpucalc ? FPUCALC.FPUnewflags : FPUFAST.FPUnewflags; }
+        result = operation[0,1] ? FPUFAST.result : operation[1,1] ? convertresult : FPUCALC.result;                                // COLLECT THE APPROPRIATE RESULT
+        frd = fpuconvert ? ( |converttype[0,2] ) : fpucalc ? 1 : FPUFAST.frd;                                                      // WRITE TO F REGISTERS FOR TO FLOAT CONVERSIONS, CALCULATIONS AND SOME SINGLE CYCLE
+        FPUnewflags = fpuconvert ? convertflags : fpucalc ? FPUCALC.FPUnewflags : FPUFAST.FPUnewflags;                             // OUTPUT NEW FPU FLAGS
     }
 }
 
@@ -581,21 +572,24 @@ unit fetch(
         while(1) {
             if( start ) {
                 busy = 1;
-                while( memorybusy ) {} ++:
-                switch( readdata[0,2] ) {                                               // EXPAND COMPRESSED INSTRUCTION
-                    case 2b00: { instruction = { COMPRESSED00.i32, 2b11 }; }            // OR KEEP 32 BIT INSTRUCTION
-                    case 2b01: { instruction = { COMPRESSED01.i32, 2b11 }; }
-                    case 2b10: { instruction = { COMPRESSED10.i32, 2b11 }; }
-                    default: { instruction = readdata; }
-                }
-                compressed = ( ~&readdata[0,2] );                        // SET COMPRESSED FLAGS
+                while( memorybusy ) {}
                 busy = 0;
             }
         }
     }
+
+    always_after {
+        switch( readdata[0,2] ) {                                               // EXPAND COMPRESSED INSTRUCTION
+            case 2b00: { instruction = { COMPRESSED00.i32, 2b11 }; }            // OR KEEP 32 BIT INSTRUCTION
+            case 2b01: { instruction = { COMPRESSED01.i32, 2b11 }; }
+            case 2b10: { instruction = { COMPRESSED10.i32, 2b11 }; }
+            default: { instruction = readdata; }
+        }
+        compressed = ( ~&readdata[0,2] );                        // SET COMPRESSED FLAGS
+    }
 }
 
-// LOAD UNIT - INCLUDING SIGN EXTENSION FOR 8/16 BIT SIGNED LOADS
+// LOAD UNITS - INCLUDING SIGN EXTENSION FOR 8/16 BIT SIGNED LOADS
 unit load(
     input   uint1   start,
     output! uint1   busy(0),
@@ -610,16 +604,19 @@ unit load(
 ) <reginputs> {
     // SIGN FOR 8, 16, 32 BIT LOADS
     uint1   sign <:: ~dounsigned & ( accesssize[1,1] ? readdata[31,1] : accesssize[0,1] ? readdata[15,1] : readdata[ { byteaccess, 3b111 }, 1 ] );
-    uint64  signextend <:: accesssize[1,1] ? { {32{sign}}, readdata } :                                                         // 32 BIT
-                           accesssize[0,1] ? { {48{sign}}, readdata[0,16] } :                                                   // 16 BIT
-                                             { {56{sign}}, readdata[ { byteaccess, 3b000 }, 8 ] };                              // 8 BIT
     readmemory := start;
 
     algorithm <autorun> {
         while(1) {
-            if( start ) { busy = 1; while( memorybusy ) {} ++: memoryinput = signextend; busy = 0; }
+            if( start ) { busy = 1; while( memorybusy ) {} ++: busy = 0; }
         }
     }
+
+    always_after {
+        memoryinput = accesssize[1,1] ? { {32{sign}}, readdata } :                                                              // 32 BIT
+                      accesssize[0,1] ? { {48{sign}}, readdata[0,16] } :                                                        // 16 BIT
+                                        { {56{sign}}, readdata[ { byteaccess, 3b000 }, 8 ] };                                   // 8 BIT
+    }
 }
 unit load64(
     input   uint1   start,
@@ -645,7 +642,8 @@ unit load64(
         }
     }
 }
-// STORE UNIT FOR NON-FAST STORES ( to BRAM/SDRAM or 32 bit )
+
+// STORE UNITS
 unit store(
     input   uint1   start,
     output! uint1   busy(0),
diff --git a/RV64/SOFTWARE/PAWS/TEST/RISCV.P64 b/RV64/SOFTWARE/PAWS/TEST/RISCV.P64
diff --git a/RV64/SOFTWARE/c/riscv-tests/makefile b/RV64/SOFTWARE/c/riscv-tests/makefile
@@ -0,0 +1,9 @@
+CFLAGSEXTRA=
+include ../makefile-lto.inc
+
+PROJECT=RISCV
+PROJECTTYPE=TEST
+PRJSRC=$(wildcard *.c) $(wildcard *.cpp) $(wildcard *.s) $(wildcard *.h)
+PRJOBJ=riscv-tests.o
+
+include ../makefile-paws.inc
diff --git a/RV64/SOFTWARE/c/riscv-tests/riscv-tests.c b/RV64/SOFTWARE/c/riscv-tests/riscv-tests.c
@@ -0,0 +1,150 @@
+#include <stdio.h>
+#include <math.h>
+#include <PAWSlibrary.h>
+
+// https://github.com/riscv-software-src/riscv-tests/blob/master/isa/macros/scalar/test_macros.h
+#define qNaNh 0x7e00
+#define sNaNh 0x7c01
+#define nINFf 0xFF800000
+#define pINFf 0x7F800000
+#define qNaNf 0x7fc00000
+#define sNaNf 0x7f800001
+#define qNaN 0x7ff8000000000000
+#define sNaN 0x7ff0000000000001
+
+union single_bitstream {
+    float single_float;
+    int bitstream;
+};
+
+struct singe_inputs {
+    int operation;
+    union single_bitstream op1;
+    union single_bitstream op2;
+    union single_bitstream result;
+};
+
+struct singe_inputs single_test_inputs[] = {
+    { 1, 2.5f, 1.0f, 3.5f },
+    { 1, -1235.1f, 1.1f, -1234.0f },
+    { 1, 3.14159265f, 0.00000001f, 3.14159265f },
+    { 2, 2.5f, 1.0f, 1.5f },
+    { 2, -1235.1f, -1.1f, -1234.0f },
+    { 2, 3.14159265f, 0.00000001f, 3.14159265f },
+    { 2, pINFf, nINFf, qNaNf },
+    { 3, 2.5f, 1.0f, 2.5f },
+    { 3, -1235.1f, -1.1f, 1358.61f },
+    { 3, 3.14159265f, 0.00000001f, 3.14159265e-8f },
+    { 4, 3.14159265f, 2.71828182f, 1.1557273520668288f },
+    { 4, -1234.0f, 1235.1f, -0.9991093838555584f },
+    { 4, 3.14159265f, 1.0f, 3.14159265f },
+    { 5, 3.14159265f, 0, 1.7724538498928541f },
+    { 5, 10000.0f, 0, 100.0f },
+    { 5,-1.0f, 0, qNaNf },
+    { 5, 171.0f, 0, 13.076696f },
+    { -1, -1, -1, -1 }
+};
+int single_test_inputs_overrides[][3] = {
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {pINFf, nINFf, qNaNf},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+    {0,0,qNaNf},
+    {0,0,0},
+    {0,0,0},
+    {0,0,0},
+};
+
+int single_tests( void ) {
+    int test = 0;
+    union single_bitstream result;
+
+    printf("\n");
+    printf("Single-Precision Floating-Point Test");
+    printf("\n");
+
+    while( single_test_inputs[ test ].operation != -1 ) {
+        if( single_test_inputs_overrides[test][0] ) { single_test_inputs[test].op1.bitstream = single_test_inputs_overrides[test][0]; }
+        if( single_test_inputs_overrides[test][1] ) { single_test_inputs[test].op2.bitstream = single_test_inputs_overrides[test][1]; }
+        if( single_test_inputs_overrides[test][2] ) { single_test_inputs[test].result.bitstream = single_test_inputs_overrides[test][2]; }
+        test++;
+    }
+
+    test = 0;
+    while( single_test_inputs[ test ].operation != -1 ) {
+        switch( single_test_inputs[ test ].operation ) {
+            case 1:
+                result.single_float = single_test_inputs[test].op1.single_float + single_test_inputs[test].op2.single_float;
+                printf("fadd.s %8.8f + %8.8f\n",
+                        single_test_inputs[test].op1.single_float,single_test_inputs[test].op2.single_float);
+                printf("    -> %8.8f ( %8.8f )\n",result.single_float,single_test_inputs[test].result.single_float);
+                printf("    -> 0x%8x ( 0x%8x )",result.bitstream,single_test_inputs[test].result.bitstream);
+                break;
+            case 2:
+                result.single_float = single_test_inputs[test].op1.single_float - single_test_inputs[test].op2.single_float;
+                printf("fsub.s %8.8f - %8.8f\n",
+                        single_test_inputs[test].op1.single_float,single_test_inputs[test].op2.single_float);
+                printf("    -> %8.8f ( %8.8f )\n",result.single_float,single_test_inputs[test].result.single_float);
+                printf("    -> 0x%8x ( 0x%8x )",result.bitstream,single_test_inputs[test].result.bitstream);
+                break;
+            case 3:
+                result.single_float = single_test_inputs[test].op1.single_float * single_test_inputs[test].op2.single_float;
+                printf("fmul.s %8.8f * %8.8f\n",
+                        single_test_inputs[test].op1.single_float,single_test_inputs[test].op2.single_float);
+                printf("    -> %8.8f ( %8.8f )\n",result.single_float,single_test_inputs[test].result.single_float);
+                printf("    -> 0x%8x ( 0x%8x )",result.bitstream,single_test_inputs[test].result.bitstream);
+                break;
+            case 4:
+                result.single_float = single_test_inputs[test].op1.single_float / single_test_inputs[test].op2.single_float;
+                printf("fdiv.s %8.8f / %8.8f\n",
+                        single_test_inputs[test].op1.single_float,single_test_inputs[test].op2.single_float);
+                printf("    -> %8.8f ( %8.8f )\n",result.single_float,single_test_inputs[test].result.single_float);
+                printf("    -> 0x%8x ( 0x%8x )",result.bitstream,single_test_inputs[test].result.bitstream);
+                break;
+            case 5:
+                result.single_float = sqrtf(single_test_inputs[test].op1.single_float);
+                printf("fsqrt.s %8.8f\n",
+                        single_test_inputs[test].op1.single_float);
+                printf("    -> %8.8f ( %8.8f )\n",result.single_float,single_test_inputs[test].result.single_float);
+                printf("    -> 0x%8x ( 0x%8x )",result.bitstream,single_test_inputs[test].result.bitstream);
+                break;
+        }
+        switch( single_test_inputs[ test ].operation ) {
+            case 1:
+            case 2:
+            case 3:
+            case 4:
+            case 5:
+                if( result.single_float == single_test_inputs[test].result.single_float )
+                    printf(" PASS\n");
+                else
+                    printf(" FAIL\n");
+                break;
+        }
+        printf("\n");
+        test++;
+    }
+}
+
+int main( void ) {
+    // CODE GOES HERE
+    printf("PAWS Risc-V Test Suite\n");
+    printf("Ported from https://github.com/riscv-software-src/riscv-tests\n");
+
+    single_tests();
+
+    sleep1khz( 4000, 0 );
+}
+
+// EXIT WILL RETURN TO BIOS
diff --git a/RV64/ULX3S/BUILD_ulx3s/PAWSv2-64.bit b/RV64/ULX3S/BUILD_ulx3s/PAWSv2-64.bit
diff --git a/RV64/cpu_functionblocks.si b/RV64/cpu_functionblocks.si
@@ -21,6 +21,7 @@ unit control(
     output  uint1   IS_AUIPCLUI,
     output  uint1   IS_JAL,
     output  uint1   IS_ALUM,
+    output  uint1   IS_ALUCLM,
     output  uint1   IS_CSR,
     output  uint1   IS_ATOMIC,
     output  uint1   IS_FPU,
@@ -66,6 +67,7 @@ unit control(
         IS_AUIPCLUI :> IS_AUIPCLUI,
         IS_JAL :> IS_JAL,
         IS_ALUM :> IS_ALUM,
+        IS_ALUCLM :> IS_ALUCLM,
         IS_CSR :> IS_CSR,
         IS_ATOMIC :> IS_ATOMIC,
         IS_LOAD :> IS_LOAD,
@@ -244,6 +246,7 @@ unit controlflags(
     output  uint1   IS_JAL,
     output  uint1   IS_BRANCH,
     output  uint1   IS_ALUM,
+    output  uint1   IS_ALUCLM,
     output  uint1   IS_CSR,
     output  uint1   IS_ATOMIC,
     output  uint1   IS_FPU,
@@ -267,6 +270,7 @@ unit controlflags(
     IS_FAST := 1; IS_ALU := 0; IS_ALU32 := 0; IS_ALU32SIGNX := 1; IS_FPU := 0; IS_FASTFPU := 0;
     IS_AUIPCLUI := 0; IS_JAL := 0; IS_BRANCH := 0; IS_CSR := 0; IS_ATOMIC := 0; IS_LOAD := 0; IS_STORE := 0; IS_FENCE := 0;
     IS_ALUM := REGREG & ( function7 == 7b0000001 );
+    IS_ALUCLM := REGREG & ( function7 == 7b0000101 );
 
     always_after {
         // DETERMINE CPU CONTROL FLAGS
@@ -283,7 +287,7 @@ unit controlflags(
             case 5b00011: { IS_FENCE = 1; writeRegister = 0;}                                                                   // FENCE[I]
             case 5b11100: { IS_CSR = 1; IS_FAST = 0; }                                                                          // CSR ECALL EBBREAK
             case 5b00100: { IS_ALU = 1; }                                                                                       // REGISTER-IMMEDIATE ALU
-            case 5b01100: { IS_ALU = 1; IS_FAST = ~( IS_ALUM & function3[2,1] ); }                                              // REGISTER-REGISTER ALU ( FAST NOT DIVIDE )
+            case 5b01100: { IS_ALU = 1; IS_FAST = ~( IS_ALUM & function3[2,1] ); }                                              // REGISTER-REGISTER ALU ( FAST NOT DIVIDE OR CLMUL )
             case 5b00110: {
                 IS_ALU = 1; IS_ALU32 = 1;                                                                                       // REGISTER-IMMEDIATE ALU 32BIT
                 switch( function3 ) {
diff --git a/Reference/Graphics/OUTRUN-4.jpg b/Reference/Graphics/OUTRUN-4.jpg
