Committing old changes

Author: kaiwetlesen

aes256.v

@@ -14,11 +14,13 @@
  * limitations under the License.
  */
 
-module aes_256 (clk, state, key, out);
+module aes_256 (clk, state, key, out, start, finish);
     input          clk;
     input  [127:0] state;
     input  [255:0] key;
     output [127:0] out;
+    input  start;
+    output finish;
 
     reg    [127:0] s0;
     reg    [255:0] k0, k0a, k1;

block_transfer_unit.v

@@ -159,10 +159,10 @@ module fifo #(parameter WSIZE = 32, parameter FIFOLEN = 1024) (
     output reg [WSIZE - 1:0] data_out,
     input write_en,
     input read_en,
-	output reg [WSIZE - 1:0] read_count,
-	output reg [WSIZE - 1:0] write_count,
     output fifo_full,
     output fifo_empty,
+    output reg [WSIZE - 1:0] write_count,
+    output reg [WSIZE - 1:0] read_count,
     input reset,
     input clock
     );
@@ -191,40 +191,39 @@ module fifo #(parameter WSIZE = 32, parameter FIFOLEN = 1024) (
 
     reg [WSIZE - 1:0] fifo_mem[FIFOLEN - 1:0]; // MSB used to tell if there's a word there or not
 
-	initial begin
-		read_addr <= 'd0;
-		write_addr <= 'd0;
-		read_count <= 'd0;
-		write_count <= 'd0;
-	end
+    initial begin
+        read_addr <= 'd0;
+        write_addr <= 'd0;
+        read_count <= 'd0;
+        write_count <= 'd0;
+    end
 
-    always @(posedge trigger_write, posedge reset) begin
-		if (reset) begin
-			write_addr <= 'd0;
-			write_count <= 'd0;
-		end
+    // For some reason this triggers a synchronization warning, it
+    // can be safely ignored IMHO.
+    always @(posedge trigger_write, posedge reset)
+        if (reset) begin
+            write_addr <= 'd0;
+            write_count <= 'd0;
+        end
         else if (trigger_write && !fifo_full && !reset) begin
             fifo_mem[write_addr[ADDRLEN - 1:0]] <= data_in;
-            write_addr <= write_addr + 1;
-			write_count <= write_count + 'd1;
+            write_addr <= write_addr + 'd1;
+            write_count <= write_count + 'd1;
         end
-        // else Let the user pick it up via the signal wire
-    end
+        // Else let the user pick it up via the signal wire
 
-    always @(posedge trigger_read, posedge reset) begin
-		if (reset) begin
-			read_addr <= 'd0;
-			read_count <= 'd0;
-		end
-        else 
-        if (trigger_read && !fifo_empty && !reset) begin
+    always @(posedge trigger_read, posedge reset)
+        if (reset) begin
+            read_addr <= 'd0;
+            read_count <= 'd0;
+        end
+        else if (trigger_read && !fifo_empty && !reset) begin
             data_out <= fifo_mem[read_addr[ADDRLEN - 1:0]];
             read_addr <= read_addr + 'd1;
-			read_count <= read_count + 'd1;
+            read_count <= read_count + 'd1;
         end
-        // Leave existing data on the output buffer, signal to clue the user
-    end
+        // Else leave existing data on the output buffer, signal to clue the user
 
     assign fifo_empty = (write_addr - read_addr) == 0;
     assign fifo_full  = (write_addr - read_addr) == FIFOLEN;
-endmodule
+endmodule

cp2_tb.v

@@ -35,16 +35,16 @@ module cp2_tb();
     reg we = 0;
     reg clk = 0;
     reg rst = 0;
-    reg [31:0] dout = 32'b0;
+    wire [31:0] dout;
 
-    cptwo u1 (.clk(clk), .addr(addr), .din(din), .we(we), .dout(dout), .int(int));
+    aes256_coprocessor u1 (.clock(clk), .addr(addr), .data_in(din), .write_en(we), .data_out(dout), .interrupt(int));
 
 
 
     initial begin
         addr = 4'b0000;
         //write 1 to everything except int and run
-        din = 8'hFF7FFFFE
+        din = 32'hFF7FFFFE;
         we = 1;
         bounce();
 
@@ -53,12 +53,12 @@ module cp2_tb();
 
         //test that it was not written to
         //empty, full, empty, full, empty, full, empty, full, zero[22:2], reset, run
-        if(dout != {1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 21'b0, 1'b0, 1'b0})
+        /*if(dout != {1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 21'b0, 1'b0, 1'b0})
             begin
                 $display "Flag error";
                 $stop;
             end
-        
+        */
         //test to see if we works
 
 

round.v

@@ -15,18 +15,29 @@
  */
 
 /* one AES round for every two clock cycles */
-module one_round (clk, state_in, key, state_out);
+module one_round (clk, state_in, key, state_out, tracker_in, tracker_out);
     input              clk;
     input      [127:0] state_in, key;
     output reg [127:0] state_out;
+    /* Tracking pins */
+    input      tracker_in;
+    output     tracker_out;
+    
     wire       [31:0]  s0,  s1,  s2,  s3,
                        z0,  z1,  z2,  z3,
                        p00, p01, p02, p03,
                        p10, p11, p12, p13,
                        p20, p21, p22, p23,
                        p30, p31, p32, p33,
                        k0,  k1,  k2,  k3;
- 
+    /* Tracking logic */
+    reg cycle1, cycle2;
+    always @(clk) begin
+        cycle1 <= tracker_in;
+        cycle2 <= cycle1;
+    end
+    assign tracker_out = cycle2;
+    
     assign {k0, k1, k2, k3} = key;
 
     assign {s0, s1, s2, s3} = state_in;
@@ -47,19 +58,28 @@ module one_round (clk, state_in, key, state_out);
 endmodule
 
 /* AES final round for every two clock cycles */
-module final_round (clk, state_in, key_in, state_out);
+module final_round (clk, state_in, key_in, state_out, tracker_in, tracker_out);
     input              clk;
     input      [127:0] state_in;
     input      [127:0] key_in;
     output reg [127:0] state_out;
+    input       tracker_in;
+    output      tracker_out;
     wire [31:0] s0,  s1,  s2,  s3,
                 z0,  z1,  z2,  z3,
                 k0,  k1,  k2,  k3;
     wire [7:0]  p00, p01, p02, p03,
                 p10, p11, p12, p13,
                 p20, p21, p22, p23,
                 p30, p31, p32, p33;
- 
+     /* Tracking logic */
+    reg cycle1, cycle2;
+    always @(clk) begin
+        cycle1 <= tracker_in;
+        cycle2 <= cycle1;
+    end
+    assign tracker_out = cycle2;
+    
     assign {k0, k1, k2, k3} = key_in;
 
     assign {s0, s1, s2, s3} = state_in;

table.v

@@ -28,7 +28,7 @@ module table_lookup (clk, state, p0, p1, p2, p3);
         t3 (clk, b3, p3);
 endmodule
 
-/* substitue four bytes in a word */
+/* substitute four bytes in a word */
 module S4 (clk, in, out);
     input clk;
     input [31:0] in;

test_benches.v

@@ -56,16 +56,75 @@ module fifo_tb();
     end
 endmodule
 
+module block_to_word_disassembler_tb();
+    reg [127:0] block_in;
+    wire [31:0] word_out;
+    
+    reg block_in_ready, word_out_hold;
+    wire word_ready, pull_block;
+    
+    reg clock, reset;
+    
+    block_to_word_disassembler btw_dis_DUT(.block_in(block_in), .word_out(word_out),
+        .block_in_ready(block_in_ready), .word_out_hold(word_out_hold),
+        .word_ready(word_ready), .pull_block(pull_block),
+        .clock(clock), .reset(reset));
+    
+    
+    parameter BLOCK_1 = 128'h0123_0ABC__0456_0DEF__0789_1ABC__1123_1DEF;
+    parameter BLOCK_2 = 128'h0ABC_0123__0DEF_0456__1ABC_0789__1DEF_1123;
+    parameter BLOCK_3 = 128'h1111_2222__3333_4444__5555_6666__1212_3434;
+    
+    initial begin
+        hit_reset;
+        
+        block_in = BLOCK_1;
+        block_in_ready = 1'b1;
+        
+        tick; tick; tick; tick;
+         block_in = BLOCK_2;
+         tick;
+        
+        tick; tick; tick;
+         word_out_hold = 1'b1;
+         tick;
+         word_out_hold = 1'b0;
+         tick; tick;
+        
+        tick; tick; tick; tick; tick;
+    end
+    
+    task tick;
+        begin
+            #1 clock = 1'b1;
+            #1 clock = 1'b0;
+        end
+    endtask
+    
+    task hit_reset;
+        begin
+            block_in = 128'b0;
+            word_out_hold = 1'b0;
+            block_in_ready = 1'b0;
+            clock = 1'b0;
+            reset = 1'b0;
+            
+            #1 reset = 1'b1;
+            #1 reset = 1'b0;
+        end
+    endtask
+endmodule
 
-module block_transfer_unit_tb();
+
+module word_to_block_assembler_tb();
     reg [31:0] word_in;
     wire [127:0] block_out;
     reg word_in_ready, block_out_hold;
     wire block_ready, pull_word;
 
     reg clock, reset;
 
-    word_to_block_assembler #(.WSIZE(32)) (
+    word_to_block_assembler #(.WSIZE(32)) wtb_assembler_dut (
         .word_in(word_in),
         .word_in_ready(word_in_ready),
         .block_out_hold(block_out_hold),
@@ -78,18 +137,23 @@ module block_transfer_unit_tb();
     initial begin
         hit_reset;
 
-        word_in = 32'hA0B0_C0D1;
+        word_in = 32'h0000_C0D1;
         word_in_ready = 1'b1;
         tick;
 
-        word_in = 32'hB0A0_D0C1;
+        word_in = 32'h0000_D0C1;
         tick;
 
-        word_in = 32'hC0D0_E0F1;
+        word_in = 32'h0000_E0F1;
         tick;
 
-        word_in = 32'hD0C0_F0E1;
+        word_in = 32'h0000_F0E1;
         tick;
+        block_out_hold = 1'b1;
+        tick;tick;tick;tick;tick; // just some random clocks to check and see what happens
+        block_out_hold = 1'b0;
+        tick;tick;tick;
+        $stop();
     end
 
     task tick;