Merge branch 'master' into kaiw

Author: Kai M. Wetlesen

CP2.v

@@ -27,7 +27,7 @@ module CP2(
 	output wire [31:0] rdData_cpu,
 
 	output reg        we_dma, 
-	output reg [19:0] addr_dma, 
+	output reg [31:0] addr_dma, 
 	input  wire[31:0] wrData_dma,
 	output reg [31:0] rdData_dma,
 
@@ -146,17 +146,17 @@ module CP2(
 		end // END rst
 		else begin
 			if(we_cpu)  reg_cpu[addr_cpu] = (addr_cpu==0)? {wrData_cpu[31:25], reg_cpu[0][24], wrData_cpu[23:0] } : wrData_cpu;
-		end
+/*		end
 	end
 
 
-    always @ (posedge clk) begin
+    always @ (posedge clk) begin*/
         case(state_dma)
             idle	  : state_dma = reg_cpu[0][30] ? dmaSet : idle; // WHILE go !=1  
             dmaSet    : begin
                         reg_cpu[0][24]<= 1;
                         //self.clk = clk*1;				// reset clk
-                        addr_dma  <= reg_cpu[1][19:0]; 
+                        addr_dma  <= reg_cpu[1][31:0]; 
                         we_dma     = 0;
                         i          = 0;
                         length     = 0;
@@ -207,7 +207,7 @@ module CP2(
 
             dmaWriteA : begin
                         we_dma    <= 1;
-                        addr_dma  <= reg_cpu[1][19:0]; 
+                        addr_dma  <= reg_cpu[1][31:0]; 
                         state_dma  = dmaWriteB;	                  end         
             dmaWriteB : begin
                         rdData_dma = r00[i];
@@ -233,9 +233,9 @@ module CP2(
                         state_dma  = idle; 	                      end	    
             default    : state_dma = idle;        		            
         endcase // ENDCASE STATE_DMA
-    end 
+/*    end 
     
-    always @ (posedge clk) begin
+    always @ (posedge clk) begin*/
         case(state_aes)
             idle	  : state_aes = reg_cpu[0][30] ? loadKeyA : idle;
             loadKeyA  :begin
@@ -308,7 +308,7 @@ module CP2(
             default   : state_aes = idle;
         endcase // ENDCASE AES_STATE 
     end
-
+end
 endmodule
 
 

CPzero.v

@@ -2,8 +2,6 @@ module CPzero
 (input clk, rst, we1, alu_trap, [4:0] addr, [5:0] interrupt, [31:0] wd, pcp4,  
  output exl, iv, [31:0] rd1);
 
-    
-    
     // if need full space then use the following line.
     // reg [32:0] rf [0:31];
     reg [31:0] rf [0:15];
@@ -13,12 +11,16 @@ module CPzero
     // external flag assigns
     assign iv  = rf[13][23];            // handler location, which location to select (180|200)
     assign exl = rf[12][1];             // external flag to CU for any interrupt
-    always @ (posedge exl) begin        // capture pc+4 Return addr when INT flag is set
-        rf[14] = pcp4;
+    always @ (posedge exl /*or (addr == 5'b01110)*/) begin        // capture pc+4 Return addr when INT flag is set
+/*        if(we1 && (addr == 5'b01110)) begin
+            rf[addr] <= wd;
+        end else if(exl) begin*/
+            rf[14] <= pcp4;
+//        end
     end
 
  //MUST BE UNCOMMENTED TO RUN TESTBENCH.   
-/*    always @ (posedge rst) begin
+ /*   always @ (posedge rst) begin
         // MIPS ISA leaves most of the values within this module as 
         // undefined on startup. To allow functional verification in the 
         //testbench, used register files 12-14 are initilized to zero
@@ -48,7 +50,8 @@ module CPzero
     end
 
 
-/*    always @ (interrupt) begin
+/*
+    always @ (interrupt) begin
         // set INT flags
         if (rf[12][0] == 1) begin             
             rf[13][10] <= (interrupt[0] & rf[12][10]);
@@ -182,11 +185,10 @@ end
                             rf[addr][8] <= wd[8];
                         end       
                     end
-                5'b01110:                          //reg 14
-                    if(we1) begin
-                        rf[addr] <= wd;
-                    end   
-                 
+                //5'b01110:                          //reg 14
+                //    if(we1) begin
+                //        rf[addr] <= wd;
+                //    end
             endcase // END case(addr)
     //end of interrupt logic
     //end

constraints.xdc

@@ -16,7 +16,7 @@ set_property -dict { PACKAGE_PIN E22  IOSTANDARD LVCMOS33} [get_ports { INT[0] }
 set_property -dict { PACKAGE_PIN F21  IOSTANDARD LVCMOS33} [get_ports { INT[1] }]; #IO_25_16 Sch=sw[1]
 set_property -dict { PACKAGE_PIN G21  IOSTANDARD LVCMOS33} [get_ports { INT[2] }]; #IO_L24P_T3_16 Sch=sw[2]
 set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS33} [get_ports { INT[3] }]; #IO_L24N_T3_16 Sch=sw[3]
-set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS33} [get_ports { INT[4] }]; #IO_L6P_T0_15 Sch=sw[4]
+#set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS33} [get_ports { INT[4] }]; #IO_L6P_T0_15 Sch=sw[4]
 
 #test unit
 set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { pc_current }]; #IO_L15P_T2_DQS_13 Sch=led[0]