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jgvillyjgvilly
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Finished integration of CP0 and added SLTI and BNE
1 parent cb05144 commit b2f78ed

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7 files changed

+170
-73
lines changed

7 files changed

+170
-73
lines changed

‎CPzero.v

+54-8
Original file line numberDiff line numberDiff line change
@@ -91,12 +91,58 @@ always @ (rf[13][15:8], rf[12][0]) begin
9191
end
9292
end
9393
*/
94+
wire [5:0] TEMP;
95+
assign TEMP[0] = rf[12][10] ? interrupt[0] : 0;
96+
assign TEMP[1] = rf[12][11] ? interrupt[1] : 0;
97+
assign TEMP[2] = rf[12][12] ? interrupt[2] : 0;
98+
assign TEMP[3] = rf[12][13] ? interrupt[3] : 0;
99+
assign TEMP[4] = rf[12][14] ? interrupt[4] : 0;
100+
assign TEMP[5] = rf[12][15] ? interrupt[5] : 0;
101+
102+
always @ (TEMP, clk)
103+
begin
104+
if(rf[12][0] == 1)begin
105+
if(TEMP[0] == 1) rf[13][10] = TEMP[0];
106+
if(TEMP[1] == 1) rf[13][11] = TEMP[1];
107+
if(TEMP[2] == 1) rf[13][12] = TEMP[2];
108+
if(TEMP[3] == 1) rf[13][13] = TEMP[3];
109+
if(TEMP[4] == 1) rf[13][14] = TEMP[4];
110+
if(TEMP[5] == 1) rf[13][15] = TEMP[5];
111+
end
112+
113+
if(rf[12][10] == 0) rf[13][10] = 0;
114+
if(rf[12][11] == 0) rf[13][11] = 0;
115+
if(rf[12][12] == 0) rf[13][12] = 0;
116+
if(rf[12][13] == 0) rf[13][13] = 0;
117+
if(rf[12][14] == 0) rf[13][14] = 0;
118+
if(rf[12][15] == 0) rf[13][15] = 0;
119+
120+
end
121+
122+
/*
123+
always @(interrupt) begin
124+
125+
if (rf[12][10])
126+
if(interrupt[0]) rf[13][10] <= 1'b1;
127+
if (rf[12][11])
128+
if(interrupt[1]) rf[13][11] <= 1'b1;
129+
if (rf[12][12])
130+
if(interrupt[2]) rf[13][12] <= 1'b1;
131+
if (rf[12][13])
132+
if(interrupt[3]) rf[13][13] <= 1'b1;
133+
if (rf[12][14])
134+
if(interrupt[4]) rf[13][14] <= 1'b1;
135+
if (rf[12][15])
136+
if(interrupt[5]) rf[13][15] <= 1'b1;
137+
138+
end*/
94139

95-
always @ (posedge clk or posedge interrupt) begin
140+
always @ (posedge clk) begin
141+
//always @ (posedge clk) begin
96142

97-
if (interrupt) begin
143+
//if (interrupt) begin
98144
// set INT flags
99-
if (rf[12][10])
145+
/*if (rf[12][10])
100146
if(interrupt[0]) rf[13][10] <= 1'b1;
101147
if (rf[12][11])
102148
if(interrupt[1]) rf[13][11] <= 1'b1;
@@ -107,8 +153,8 @@ end
107153
if (rf[12][14])
108154
if(interrupt[4]) rf[13][14] <= 1'b1;
109155
if (rf[12][15])
110-
if(interrupt[5]) rf[13][15] <= 1'b1;
111-
end else begin
156+
if(interrupt[5]) rf[13][15] <= 1'b1;*/
157+
//end else begin
112158

113159

114160

@@ -118,12 +164,12 @@ end
118164
// clear int flags
119165
if((rf[12][ 8]) == 0) rf[13][ 8] <= 1'b0;
120166
if((rf[12][ 9]) == 0) rf[13][ 9] <= 1'b0;
121-
if((rf[12][10]) == 0) rf[13][10] <= 1'b0;
167+
/*if((rf[12][10]) == 0) rf[13][10] <= 1'b0;
122168
if((rf[12][11]) == 0) rf[13][11] <= 1'b0;
123169
if((rf[12][12]) == 0) rf[13][12] <= 1'b0;
124170
if((rf[12][13]) == 0) rf[13][13] <= 1'b0;
125171
if((rf[12][14]) == 0) rf[13][14] <= 1'b0;
126-
if((rf[12][15]) == 0) rf[13][15] <= 1'b0;
172+
if((rf[12][15]) == 0) rf[13][15] <= 1'b0;*/
127173
//rf[12][1] = rf[13][15:8] ? 1'b1 : 0; // Set EXL flag to CU
128174

129175
// Write/Read to reg
@@ -158,7 +204,7 @@ end
158204
end
159205
endcase // END case(addr)
160206
//end of interrupt logic
161-
end
207+
//end
162208
end
163209

164210
endmodule

‎memfile.dat

+24-16
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,34 @@
11
20040005
2+
2002000f
3+
00021300
4+
20420f01
5+
28830001
26
20050009
37
20060002
4-
200E00FF
5-
200F00FF
6-
01CF6826
7-
000E6826
8+
200e00ff
9+
200f00ff
10+
28990006
11+
40806000
12+
40826000
13+
40806800
14+
40807000
15+
01cf6826
16+
000e6826
817
00063040
918
00063040
1019
00063042
1120
00063042
12-
00E63822
13-
00A43020
14-
00A43822
15-
00073843
16-
00A44024
17-
00A44825
18-
0085502A
19-
AC040004
20-
8C0B0004
21-
0C000018
21+
00e63822
22+
00a43020
23+
00a43822
24+
00a44024
25+
00a44825
26+
0085502a
27+
ac040004
28+
8c0b0004
29+
0c000020
2230
00850019
2331
00006810
2432
00007012
25-
200C0007
26-
03E00008
33+
200c0007
34+
03e00008

‎mips.v

+17-14
Original file line numberDiff line numberDiff line change
@@ -10,33 +10,33 @@ module mips
1010
//wire [31:0] pc_current, alu_out, wd_dm;
1111
//end of wires for testing
1212

13-
wire pc_src, link, jump_reg ,reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, zero, dm2reg, weCP0, weCP2, IV, EXL;
13+
wire pc_src, link, jump_reg ,reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, zero, NE, dm2reg, weCP0, weCP2, IV, EXL, hold, holdACK;
1414
wire [1:0] jump, prossSel;
1515
wire [3:0] alu_ctrl;
1616
wire [4:0] cpop;
1717
datapath DP (.clk(clk), .rst(rst), .pc_src(pc_src), .jump(jump), .link(link), .jump_reg(jump_reg) ,.reg_dst(reg_dst), .we_reg(we_reg),
1818
.alu_src(alu_src), .we_hi(we_hi), .we_lo(we_lo), .hi2reg(hi2reg), .lo2reg(lo2reg), .dm2reg(dm2reg), .alu_ctrl(alu_ctrl),
1919
.instr(instr[25:0]), .rd_dm(rd_dm), .zero(zero), .pc_current(pc_current), .alu_out(alu_out), .wd_dm(wd_dm), .prossSel(prossSel), .weCP0(weCP0), .weCP2(weCP2),
20-
.IV(IV), .EXL(EXL), .interrupt(INT));
20+
.IV(IV), .EXL(EXL), .interrupt(INT), .hold(hold), .holdACK(holdACK), .NE(NE));
2121

2222
controlunit CU (.zero(zero), .op(instr[31:26]), .funct(instr[5:0]), .pc_src(pc_src), .jump(jump),
2323
.link(link), .jump_reg(jump_reg) ,.reg_dst(reg_dst), .we_reg(we_reg), .alu_src(alu_src), .we_hi(we_hi), .we_lo(we_lo),
2424
.hi2reg(hi2reg), .lo2reg(lo2reg), .we_dm(we_dm), .dm2reg(dm2reg), .alu_ctrl(alu_ctrl), .prossSel(prossSel), .weCP0(weCP0), .weCP2(weCP2), .cpop(instr[25:21]),
25-
.IV(IV), .EXL(EXL));
25+
.IV(IV), .EXL(EXL), .hold(hold), .holdACK(holdACK), .NE(NE));
2626
endmodule
2727

2828
module datapath
29-
(input clk, rst, pc_src, link, jump_reg, reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, dm2reg, weCP0, weCP2,
29+
(input clk, rst, pc_src, link, jump_reg, reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, dm2reg, weCP0, weCP2, holdACK,
3030
input [1:0] jump, prossSel,
3131
input [3:0] alu_ctrl,
3232
input [4:0] interrupt,
3333
input [25:0] instr,
3434
input [31:0] rd_dm,
35-
output zero, IV, EXL,
35+
output zero, NE, IV, EXL, hold,
3636
output [31:0] pc_current, alu_out, wd_dm);
3737
wire trap, CP2rdy;
3838
wire [4:0] wa_rf, jal_rf;
39-
wire [31:0] CPALU, pc_pre, pc_next, pc_plus4, jra, jta, sext_imm, ba, bta, alu_pa, alu_pb, hi_dat, lo_dat, hi_res, lo_res, wd_rf, wd_rf_res,CPzerod, CPtwod;
39+
wire [31:0] CPALU, pc_pre, pc_next, pc_plus4, jra, jta, sext_imm, ba, bta, alu_pa, alu_pb, hi_dat, lo_dat, hi_res, lo_res, wd_rf, wd_rf_res,CPzerod, CPtwod, pc_plus8;
4040
wire [63:0] product;
4141
assign jta = {pc_plus4[31:28], instr[25:0], 2'b00};
4242
assign ba = {sext_imm[29:0], 2'b00};
@@ -47,6 +47,8 @@ module datapath
4747
mux4 #(32) pc_jmp_mux (.sel(jump), .a(pc_pre), .b(jta), .c(32'h180), .d(32'h200), .y(pc_next));
4848
dreg #(32) pc_reg (.clk(clk), .rst(rst), .en(1), .d(pc_next), .q(pc_current));
4949
adder #(32) pc_add4 (.a(pc_current), .b(4), .y(pc_plus4));
50+
//added for logic of CP0
51+
adder #(32) pc_add8 (.a(pc_plus4), .b(4), .y(pc_plus8));
5052
adder #(32) pc_add_bra (.a(pc_plus4), .b(ba), .y(bta));
5153
signext se (.a(instr[15:0]), .y(sext_imm));
5254
// RF Logic
@@ -56,15 +58,15 @@ module datapath
5658
regfile #(32) rf (.clk(clk), .we(we_reg), .wa(jal_rf), .ra1(instr[25:21]), .ra2(instr[20:16]), .wd(wd_rf_res), .rd1(alu_pa), .rd2(wd_dm));
5759
// ALU Logic and CP0 Logic
5860
mux2 #(32) alu_pb_mux (.sel(alu_src), .a(wd_dm), .b(sext_imm), .y(alu_pb));
59-
alu #(32) alu (.op(alu_ctrl), .a(alu_pa), .b(alu_pb), .shiftamount(instr[10:6]), .zero(zero), .y(alu_out), .trap(trap));
61+
alu #(32) alu (.op(alu_ctrl), .a(alu_pa), .b(alu_pb), .shiftamount(instr[10:6]), .zero(zero), .y(alu_out), .trap(trap), .NE(NE));
6062
multi #(32) multi (.a(alu_pa), .b(alu_pb), .h(product[63:32]), .l(product[31:0]));
6163
dreg #(32) high (.clk(clk), .rst(rst), .en(we_hi), .d(product[63:32]), .q(hi_dat));
6264
dreg #(32) low (.clk(clk), .rst(rst), .en(we_lo), .d(product[31:0]), .q(lo_dat));
6365
mux2 #(32) wd_rf_mux (.sel(dm2reg), .a(CPALU), .b(rd_dm), .y(wd_rf));
6466
mux2 #(32) hi_mux (.sel(hi2reg), .a(wd_rf), .b(hi_dat), .y(hi_res));
6567
mux2 #(32) lo_mux (.sel(lo2reg), .a(hi_res), .b(lo_dat), .y(lo_res));
6668
mux4 #(32) pross_mux (.sel(prossSel), .a(alu_out), .b(CPzerod), .c(32'b0), .d(32'b0), .y(CPALU));
67-
CPzero CP0 (.clk(clk), .rst(rst), .we1(weCP0), .alu_trap(trap), .addr(instr[20:16]), .interrupt({interrupt, CP2rdy}), .wd(wd_dm), .pcp4(pc_current), .exl(EXL), .iv(IV), .rd1(CPzerod));
69+
CPzero CP0 (.clk(clk), .rst(rst), .we1(weCP0), .alu_trap(trap), .addr(instr[15:11]), .interrupt({interrupt, 1'b0/*CP2rdy*/}), .wd(wd_dm), .pcp4(pc_plus4), .exl(EXL), .iv(IV), .rd1(CPzerod));
6870
//aes256_coprocessor CP2 (.data_in(wd_dm), .addr(instr[20:16]), .write_en(weCP2), .data_out(CPtwod), .clock(clk), .interrupt(CP2rdy));
6971

7072

@@ -74,16 +76,17 @@ endmodule
7476

7577

7678
module controlunit
77-
(input zero, IV, EXL,
79+
(input zero, IV, EXL, hold, NE,
7880
input [4:0] cpop,
7981
input [5:0] op, funct,
80-
output pc_src, link, jump_reg, reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, we_dm, dm2reg, weCP0, weCP2,
82+
output pc_src, link, jump_reg, reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, we_dm, dm2reg, weCP0, weCP2, holdACK,
8183
output [1:0] jump, prossSel,
8284
output [3:0] alu_ctrl);
83-
wire branch;
84-
wire [1:0] alu_op;
85-
assign pc_src = branch & zero;
86-
maindec MD (.op(op), .branch(branch), .jump(jump), .link(link), .reg_dst(reg_dst), .we_reg(we_reg), .alu_src(alu_src), .we_dm(we_dm), .dm2reg(dm2reg), .alu_op(alu_op), .prossSel(prossSel), .weCP0(weCP0), .weCP2(weCP2), .cpop(cpop), .IV(IV), .EXL(EXL));
85+
wire branch, BNE;
86+
wire [2:0] alu_op;
87+
assign pc_src = (branch & zero) | (BNE & NE);
88+
maindec MD (.op(op), .branch(branch), .jump(jump), .link(link), .reg_dst(reg_dst), .we_reg(we_reg), .alu_src(alu_src), .we_dm(we_dm), .dm2reg(dm2reg), .alu_op(alu_op), .prossSel(prossSel), .weCP0(weCP0), .weCP2(weCP2),
89+
.cpop(cpop), .IV(IV), .EXL(EXL), .hold(hold), .holdACK(holdACK), .BNE(BNE));
8790
auxdec AD (.alu_op(alu_op), .funct(funct), .jump_reg(jump_reg), .we_hi(we_hi), .we_lo(we_lo), .hi2reg(hi2reg), .lo2reg(lo2reg), .alu_ctrl(alu_ctrl));
8891

8992
endmodule

‎mipscore_tb.v

+17-3
Original file line numberDiff line numberDiff line change
@@ -3,23 +3,37 @@ module mipscore_tb();
33

44
reg clk, rst= 0;
55
wire [31:0] pc_current, instr, alu_out, wd_dm, rd_dm;
6+
integer INT;
67

78
mips_top u1 (.clk(clk), .rst(rst),
89
.pc_current(pc_current), .instr(instr),
9-
.alu_out(alu_out), .wd_dm(wd_dm), .rd_dm(rd_dm));
10+
.alu_out(alu_out), .wd_dm(wd_dm), .rd_dm(rd_dm), .INT(INT[4:0]));
1011
initial begin
12+
INT = 5'b00000;
1113
rst = 0;
1214
bounce();
1315
rst = 1;
1416
bounce();
1517
rst = 0;
1618

17-
while(pc_current != 32'h0000005C)
19+
//while(pc_current != 32'h0000005C)
20+
repeat (150)
1821
begin
1922
bounce();
2023
end
2124
//$stop;
22-
25+
26+
INT[4] = 1'b1;
27+
#5;
28+
//bounce();
29+
#5;
30+
INT = 0;
31+
32+
repeat (10)
33+
begin
34+
bounce();
35+
end
36+
2337
$display ("Test Done");
2438
$stop;
2539

‎parts.v

+43-27
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,9 @@ module signext
3232
endmodule
3333

3434
module alu #(parameter wide = 8)
35-
(input [3:0] op, [wide-1:0] a, b, [4:0] shiftamount, output zero, reg trap, reg [wide-1:0] y);
35+
(input [3:0] op, [wide-1:0] a, b, [4:0] shiftamount, output zero, NE, reg trap, reg [wide-1:0] y);
3636
assign zero = (y == 'h0);
37+
assign NE = (a != b);
3738
always @ (op, a, b)
3839
case (op)
3940
4'b0000: begin y = a & b; trap = 0; end
@@ -84,60 +85,75 @@ module dmem #(parameter wide = 8)
8485
endmodule
8586

8687
module maindec
87-
(input EXL, IV, [5:0] op, [4:0] cpop, output reg branch, link, reg_dst, we_reg, alu_src, we_dm, dm2reg, weCP0, weCP2, reg [1:0] prossSel, alu_op, jump);
88-
reg [14:0] ctrl;
89-
always @ (ctrl) {branch, jump, link, reg_dst, we_reg, alu_src, we_dm, dm2reg, alu_op, prossSel, weCP0, weCP2} = ctrl;
88+
(input EXL, hold, IV, [5:0] op, [4:0] cpop, output reg holdACK, branch, link, reg_dst, we_reg, alu_src, we_dm, dm2reg, weCP0, weCP2, BNE, reg [1:0] prossSel, jump, reg [2:0] alu_op);
89+
reg [16:0] ctrl;
90+
always @ (ctrl) {branch, jump, link, reg_dst, we_reg, alu_src, we_dm, dm2reg, alu_op, prossSel, weCP0, weCP2, BNE} = ctrl;
9091

91-
always @ (op)
92+
always @ (op, EXL)
9293
//interrupt logic
9394
if(EXL == 1)
9495
begin
95-
ctrl[12:11] = IV ? 2'b11 : 2'b10;
96+
ctrl[15:14] = IV ? 2'b11 : 2'b10;
9697
end else
9798
begin
9899
//put hold accept logic here
99-
//if(hold) //holdACK == hold 1 ? 0;
100-
//else begin
100+
if(hold) holdACK = hold ? 1'b1 : 1'b0;
101+
else begin
101102
case (op)
102-
6'b000000: ctrl = 15'b0_00_0_1_1_0_0_0_10_00_0_0; // R-Type
103-
6'b100011: ctrl = 15'b0_00_0_0_1_1_0_1_00_00_0_0; // LW
104-
6'b101011: ctrl = 15'b0_00_0_0_0_1_1_0_00_00_0_0; // SW
105-
6'b000100: ctrl = 15'b1_00_0_0_0_0_0_0_01_00_0_0; // BEQ
106-
6'b001000: ctrl = 15'b0_00_0_0_1_1_0_0_00_00_0_0; // ADDI
107-
6'b000010: ctrl = 15'b0_01_0_0_0_0_0_0_00_00_0_0; // J
108-
6'b000011: ctrl = 15'b0_01_1_0_1_0_0_0_00_00_0_0; // JAL
109-
/*6'b010000: //MFC0/MTC0
103+
6'b000000: ctrl = 17'b0_00_0_1_1_0_0_0_010_00_0_0_0; // R-Type
104+
6'b100011: ctrl = 17'b0_00_0_0_1_1_0_1_000_00_0_0_0; // LW
105+
6'b101011: ctrl = 17'b0_00_0_0_0_1_1_0_000_00_0_0_0; // SW
106+
6'b000100: ctrl = 17'b1_00_0_0_0_0_0_0_001_00_0_0_0; // BEQ
107+
6'b001000: ctrl = 17'b0_00_0_0_1_1_0_0_000_00_0_0_0; // ADDI
108+
6'b000010: ctrl = 17'b0_01_0_0_0_0_0_0_000_00_0_0_0; // J
109+
6'b000011: ctrl = 17'b0_01_1_0_1_0_0_0_000_00_0_0_0; // JAL
110+
6'b001010: ctrl = 17'b0_00_0_0_1_1_0_0_011_00_0_0_0; // SLTI, untested
111+
6'b000101: ctrl = 17'b0_00_0_0_0_0_0_0_001_00_0_0_1;//BNE
112+
6'b010000: //MFC0/MTC0
110113
begin
111114
if(cpop == 5'b00000)
112115
begin
113116
//MFC0
114-
ctrl = 15'b0_00_0_0_1_0_0_0_00_01_0_0;
117+
ctrl = 17'b0_00_0_0_1_0_0_0_000_01_0_0_0;
115118
end else if(cpop == 5'b00100)
116119
begin
117120
//MTC0
118-
ctrl = 15'b0_00_0_0_0_0_0_0_00_00_1_0;
121+
ctrl = 17'b0_00_0_0_0_0_0_0_000_00_1_0_0;
119122
end
120-
end*/
121-
//6'b010010 //MTC2/MFC2
122-
default: ctrl = 15'bx;
123+
end
124+
6'b010010: //MTC2/MFC2
125+
begin
126+
if(cpop == 5'b00000)
127+
begin
128+
//MFC2
129+
ctrl = 17'b0_00_0_0_1_0_0_0_000_10_0_0_0;
130+
end else if(cpop == 5'b00100)
131+
begin
132+
//MTC2
133+
ctrl = 17'b0_00_0_0_0_0_0_0_000_00_0_1_0;
134+
end
135+
//end of MXC2
136+
end
137+
default: ctrl = 17'bx;
123138
endcase
124139
//end of hold logic
125-
//end
140+
end
141+
//end of logic
126142
end
127143

128144
endmodule
129145

130146
module auxdec
131-
(input [1:0] alu_op, [5:0] funct, output reg jump_reg, we_hi, we_lo, hi2reg, lo2reg, reg [3:0] alu_ctrl);
147+
(input [2:0] alu_op, [5:0] funct, output reg jump_reg, we_hi, we_lo, hi2reg, lo2reg, reg [3:0] alu_ctrl);
132148
reg [8:0] ctrl;
133149
//adjusting alucontrol
134150
always @ (ctrl) {jump_reg, we_hi, we_lo, hi2reg, lo2reg, alu_ctrl} = ctrl;
135151
always @ (alu_op, funct)
136152
case (alu_op)
137-
2'b00: ctrl = 9'b0_0_0_0_0_0010; // add
138-
2'b01: ctrl = 9'b0_0_0_0_0_0110; // sub
139-
2'b11: ctrl = 9'b0_0_0_0_0_0000; //SLTI
140-
default: case (funct)
153+
3'b000: ctrl = 9'b0_0_0_0_0_0010; // add
154+
3'b001: ctrl = 9'b0_0_0_0_0_0110; // sub
155+
3'b011: ctrl = 9'b0_0_0_0_0_0111; //SLTI
156+
3'b010: case (funct)
141157
6'b100000: ctrl = 9'b0_0_0_0_0_0010; // ADD
142158
6'b100010: ctrl = 9'b0_0_0_0_0_0110; // SUB
143159
6'b100100: ctrl = 9'b0_0_0_0_0_0000; // AND

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