First Commit

Author: rlucus

README.md

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+20040005
+20050009
+00A43020
+00A43822
+00A44024
+00A44825
+0085502A
+AC040000
+8C0B0000
+0C00000D
+00850019
+00006810
+00007012
+200C0007
+03E00008

memfile.dat

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+module mips
+(input         clk, rst,
+ input  [31:0] instr, rd_dm,
+ output        we_dm,
+ output [31:0] pc_current, alu_out, wd_dm);    
+    wire       pc_src, jump, link, jump_reg ,reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, zero, dm2reg;
+    wire [2:0] alu_ctrl;
+    datapath    DP (clk, rst, pc_src, jump, link, jump_reg ,reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, dm2reg, alu_ctrl, instr[25:0], rd_dm, zero, pc_current, alu_out, wd_dm);
+    controlunit CU (zero, instr[31:26], instr[5:0], pc_src, jump, link, jump_reg ,reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, we_dm, dm2reg, alu_ctrl);
+endmodule
+
+module datapath
+(input         clk, rst, pc_src, jump, link, jump_reg, reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, dm2reg,
+ input  [2:0]  alu_ctrl,
+ input  [25:0] instr, 
+ input  [31:0] rd_dm,
+ output        zero,
+ output [31:0] pc_current, alu_out, wd_dm);
+    wire [4:0]  wa_rf, jal_rf;
+    wire [31:0] pc_pre, pc_next, pc_plus4, jra, jta, sext_imm, ba, bta, alu_pa, alu_pb, hi_dat, lo_dat, hi_res, lo_res, wd_rf, wd_rf_res;
+    wire [63:0] product;
+    assign jta = {pc_plus4[31:28], instr[25:0], 2'b00};
+    assign ba  = {sext_imm[29:0], 2'b00};
+    // Next PC Logic
+    mux2    #(32) pc_jr_mux  (jump_reg, pc_plus4, alu_pa, jra);
+    mux2    #(32) pc_src_mux (pc_src, jra, bta, pc_pre);
+    mux2    #(32) pc_jmp_mux (jump, pc_pre, jta, pc_next);
+    dreg    #(32) pc_reg     (clk, rst, 1, pc_next, pc_current);
+    adder   #(32) pc_add4    (pc_current, 4, pc_plus4);
+    adder   #(32) pc_add_bra (pc_plus4, ba, bta);
+    signext       se         (instr[15:0], sext_imm);
+    // RF Logic
+    mux2    #(5)  rf_wa_mux  (reg_dst, instr[20:16], instr[15:11], wa_rf);
+    mux2    #(5)  rf_jal_mux (link, wa_rf, 31, jal_rf);
+    mux2    #(32) rf_wd_mux  (link, lo_res, pc_plus4, wd_rf_res);
+    regfile #(32) rf         (clk, we_reg, jal_rf, instr[25:21], instr[20:16], wd_rf_res, alu_pa, wd_dm);
+    // ALU Logic
+    mux2    #(32) alu_pb_mux (alu_src, wd_dm, sext_imm, alu_pb);
+    alu     #(32) alu        (alu_ctrl, alu_pa, alu_pb, zero, alu_out);
+    multi   #(32) multi      (alu_pa, alu_pb, product[63:32], product[31:0]);
+    dreg    #(32) high       (clk, rst, we_hi, product[63:32], hi_dat);
+    dreg    #(32) low        (clk, rst, we_lo, product[31:0], lo_dat);
+    mux2    #(32) wd_rf_mux  (dm2reg, alu_out, rd_dm, wd_rf);
+    mux2    #(32) hi_mux     (hi2reg, wd_rf, hi_dat, hi_res);
+    mux2    #(32) lo_mux     (lo2reg, hi_res, lo_dat, lo_res);
+endmodule
+
+module controlunit
+(input        zero,
+ input  [5:0] op, funct,
+ output       pc_src, jump, link, jump_reg, reg_dst, we_reg, alu_src, we_hi, we_lo, hi2reg, lo2reg, we_dm, dm2reg,
+ output [2:0] alu_ctrl);
+    wire       branch;
+    wire [1:0] alu_op;
+    assign pc_src = branch & zero;
+    maindec MD (op, branch, jump, link, reg_dst, we_reg, alu_src, we_dm, dm2reg, alu_op);
+    auxdec  AD (alu_op, funct, jump_reg ,we_hi, we_lo, hi2reg, lo2reg, alu_ctrl);
+endmodule

mips.v

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+module mips_top
+(input clk, rst, output [31:0] pc_current, instr, alu_out, wd_dm, rd_dm);
+    wire we_dm;
+    mips      MIPS (clk, rst, instr, rd_dm, we_dm, pc_current, alu_out, wd_dm);
+    imem #(32)IMEM (pc_current[7:2], instr);
+    dmem #(32)DMEM (clk, we_dm, alu_out[5:0], wd_dm, rd_dm);
+endmodule

mips_top.v

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+module mux2 #(parameter wide = 8)
+(input sel, [wide-1:0] a, b, output [wide-1:0] y);
+    assign y = sel ? b : a;
+endmodule
+
+module adder #(parameter wide = 8)
+(input [wide-1:0] a, b, output [wide-1:0] y);
+    assign y = a + b;
+endmodule
+
+module multi #(parameter wide = 8)
+(input [wide-1:0] a, b, output [wide-1:0] h, l);
+    assign {h, l} = a * b;
+endmodule
+
+module signext
+(input [15:0] a, output [31:0] y);
+    assign y = {{16{a[15]}}, a};
+endmodule
+
+module alu #(parameter wide = 8)
+(input [2:0] op, [wide-1:0] a, b, output zero, reg [wide-1:0] y);
+    assign zero = (y == 'h0);
+    always @ (op, a, b)
+        case (op)
+            3'b000: y = a & b;
+            3'b001: y = a | b;
+            3'b010: y = a + b;
+            3'b110: y = a - b;
+            3'b111: y = (a < b) ? 1 : 0;
+            default: y = 'hx;
+        endcase
+endmodule
+
+module dreg #(parameter wide = 8)
+(input clk, rst, en, [wide-1:0] d, output reg [wide-1:0] q);
+    always @ (posedge clk, posedge rst)
+    begin
+        if (rst) q <= 0;
+        else     q <= en ? d : q;
+    end
+endmodule
+
+module regfile #(parameter wide = 8)
+(input clk, we, [4:0] wa, ra1, ra2, [wide-1:0] wd, output [wide-1:0] rd1, rd2);
+    reg [wide-1:0] rf [0:31];
+    always @ (posedge clk) if (we) rf[wa] <= wd;
+    assign rd1 = (ra1) ? rf[ra1] : 0;
+    assign rd2 = (ra2) ? rf[ra2] : 0;
+endmodule
+
+module imem #(parameter wide = 8)
+(input [5:0] a, output [wide-1:0] y);
+    reg [wide-1:0] rom [0:63];
+    initial $readmemh ("memfile.dat", rom);
+    assign y = rom[a];
+endmodule
+
+module dmem #(parameter wide = 8)
+(input clk, we, [5:0] a, [wide-1:0] d, output [wide-1:0] q);
+    reg [wide-1:0] ram [0:63];
+    always @ (posedge clk) if (we) ram[a] <= d;
+    assign q = ram[a];
+endmodule
+
+module maindec
+(input [5:0] op, output reg branch, jump, link, reg_dst, we_reg, alu_src, we_dm, dm2reg, reg [1:0] alu_op);
+    reg [9:0] ctrl;
+    always @ (ctrl) {branch, jump, link, reg_dst, we_reg, alu_src, we_dm, dm2reg, alu_op} = ctrl;
+    always @ (op)
+        case (op)
+            6'b000000: ctrl = 10'b0_0_0_1_1_0_0_0_10; // R-Type
+            6'b100011: ctrl = 10'b0_0_0_0_1_1_0_1_00; // LW
+            6'b101011: ctrl = 10'b0_0_0_0_0_1_1_0_00; // SW
+            6'b000100: ctrl = 10'b1_0_0_0_0_0_0_0_01; // BEQ
+            6'b001000: ctrl = 10'b0_0_0_0_1_1_0_0_00; // ADDI
+            6'b000010: ctrl = 10'b0_1_0_0_0_0_0_0_00; // J
+            6'b000011: ctrl = 10'b0_1_1_0_1_0_0_0_00; // JAL
+            default: ctrl = 10'bx;
+        endcase
+endmodule
+
+module auxdec
+(input [1:0] alu_op, [5:0] funct, output reg jump_reg, we_hi, we_lo, hi2reg, lo2reg, reg [2:0] alu_ctrl);
+    reg [7:0] ctrl;
+    always @ (ctrl) {jump_reg, we_hi, we_lo, hi2reg, lo2reg, alu_ctrl} = ctrl;
+    always @ (alu_op, funct)
+        case (alu_op)
+            2'b00: ctrl = 8'b0_00_00_010; // add
+            2'b01: ctrl = 8'b0_00_00_110; // sub
+            default: case (funct)
+                6'b100000: ctrl = 8'b0_00_00_010; // ADD
+                6'b100010: ctrl = 8'b0_00_00_110; // SUB
+                6'b100100: ctrl = 8'b0_00_00_000; // AND
+                6'b100101: ctrl = 8'b0_00_00_001; // OR
+                6'b101010: ctrl = 8'b0_00_00_111; // SLT
+                6'b011001: ctrl = 8'b0_11_00_000; // MULTU
+                6'b010000: ctrl = 8'b0_00_10_000; // MFHI
+                6'b010010: ctrl = 8'b0_00_01_000; // MFLO
+                6'b001000: ctrl = 8'b1_00_00_000; // JR
+                default: ctrl = 8'bx;
+            endcase
+        endcase
+endmodule