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Commit 0efb5fd

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Merge branch 'clean-2.26' into riscv-binutils-2.26
This closes with the following two pull requests: #6 #9
2 parents eb764ce + 1c375ad commit 0efb5fd

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2 files changed

+105
-63
lines changed

2 files changed

+105
-63
lines changed

gdb/riscv-tdep.c

+100-58
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ struct riscv_frame_cache
6565
struct trad_frame_saved_reg *saved_regs;
6666
};
6767

68-
static const char * const riscv_gdb_reg_names[RISCV_NUM_REGS] =
68+
static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
6969
{
7070
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
7171
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
@@ -76,10 +76,6 @@ static const char * const riscv_gdb_reg_names[RISCV_NUM_REGS] =
7676
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7777
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7878
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
79-
80-
#define DECLARE_CSR(name, num) #name,
81-
#include "opcode/riscv-opc.h"
82-
#undef DECLARE_CSR
8379
};
8480

8581
struct register_alias
@@ -156,6 +152,9 @@ static const struct register_alias riscv_register_aliases[] =
156152
{ "ft9", 62 },
157153
{ "ft10", 63 },
158154
{ "ft11", 64 },
155+
#define DECLARE_CSR(name, num) { #name, (num) + 65 },
156+
#include "opcode/riscv-opc.h"
157+
#undef DECLARE_CSR
159158
};
160159

161160
static const gdb_byte *
@@ -189,22 +188,41 @@ value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
189188
}
190189

191190
static const char *
192-
riscv_register_name (struct gdbarch *gdbarch,
193-
int regnum)
191+
register_name (struct gdbarch *gdbarch,
192+
int regnum,
193+
int prefer_alias)
194194
{
195195
int i;
196+
static char buf[20];
196197

197198
if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
198199
return tdesc_register_name (gdbarch, regnum);
199-
else if (regnum >= 0 && regnum < RISCV_LAST_REGNUM)
200+
/* Prefer to use the alias. */
201+
if (prefer_alias &&
202+
regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM)
200203
{
201204
for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
202205
if (regnum == riscv_register_aliases[i].regnum)
203206
return riscv_register_aliases[i].name;
207+
}
208+
209+
if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
204210
return riscv_gdb_reg_names[regnum];
211+
212+
if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
213+
{
214+
sprintf(buf, "csr%d", regnum - RISCV_FIRST_CSR_REGNUM);
215+
return buf;
205216
}
206-
else
207-
return NULL;
217+
218+
return NULL;
219+
}
220+
221+
static const char *
222+
riscv_register_name (struct gdbarch *gdbarch,
223+
int regnum)
224+
{
225+
return register_name(gdbarch, regnum, 0);
208226
}
209227

210228
static void
@@ -510,12 +528,12 @@ riscv_print_register_formatted (struct ui_file *file, struct frame_info *frame,
510528

511529
if (!deprecated_frame_register_read (frame, regnum, raw_buffer))
512530
{
513-
fprintf_filtered (file, "%-15s[Invalid]",
514-
riscv_register_name (gdbarch, regnum));
531+
fprintf_filtered (file, "%-15s[Invalid]\n",
532+
register_name (gdbarch, regnum, 1));
515533
return;
516534
}
517535

518-
fprintf_filtered (file, "%-15s", riscv_register_name (gdbarch, regnum));
536+
fprintf_filtered (file, "%-15s", register_name (gdbarch, regnum, 1));
519537
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
520538
offset = register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
521539
else
@@ -586,41 +604,7 @@ riscv_print_register_formatted (struct ui_file *file, struct frame_info *frame,
586604
&opts, 0, file);
587605
}
588606
}
589-
}
590-
591-
static void
592-
riscv_print_registers_info (struct gdbarch *gdbarch,
593-
struct ui_file *file,
594-
struct frame_info *frame,
595-
int regnum,
596-
int all)
597-
{
598-
if (regnum != -1)
599-
{
600-
/* Print one specified register. */
601-
gdb_assert (regnum < RISCV_LAST_REGNUM);
602-
if ('\0' == *(riscv_register_name (gdbarch, regnum)))
603-
error (_("Not a valid register for the current processor type"));
604-
riscv_print_register_formatted (file, frame, regnum);
605-
fprintf_filtered (file, "\n");
606-
}
607-
else
608-
for (regnum = 0; regnum < RISCV_LAST_REGNUM; ++regnum)
609-
{
610-
if ('\0' == *(riscv_register_name (gdbarch, regnum)))
611-
error (_("Not a valid register for the current processor type"));
612-
613-
/* Zero never changes, so might as well hide by default. */
614-
if (regnum == RISCV_ZERO_REGNUM && !all)
615-
continue;
616-
617-
/* Only show the main integer register set by default. */
618-
if (all || regnum < RISCV_FIRST_FP_REGNUM)
619-
{
620-
riscv_print_register_formatted (file, frame, regnum);
621-
fprintf_filtered (file, "\n");
622-
}
623-
}
607+
fprintf_filtered (file, "\n");
624608
}
625609

626610
static int
@@ -630,14 +614,24 @@ riscv_register_reggroup_p (struct gdbarch *gdbarch,
630614
{
631615
int float_p;
632616
int raw_p;
617+
unsigned int i;
618+
619+
/* Used by 'info registers' and 'info registers <groupname>'. */
633620

634621
if (gdbarch_register_name (gdbarch, regnum) == NULL
635622
|| gdbarch_register_name (gdbarch, regnum)[0] == '\0')
636623
return 0;
637624

638-
if (reggroup == all_reggroup)
639-
return 1;
640-
else if (reggroup == float_reggroup)
625+
if (reggroup == all_reggroup) {
626+
if (regnum < RISCV_FIRST_CSR_REGNUM)
627+
return 1;
628+
/* Only include CSRs that have aliases. */
629+
for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) {
630+
if (regnum == riscv_register_aliases[i].regnum)
631+
return 1;
632+
}
633+
return 0;
634+
} else if (reggroup == float_reggroup)
641635
return (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
642636
|| (regnum == RISCV_CSR_FCSR_REGNUM
643637
|| regnum == RISCV_CSR_FFLAGS_REGNUM
@@ -646,14 +640,55 @@ riscv_register_reggroup_p (struct gdbarch *gdbarch,
646640
return regnum < RISCV_FIRST_FP_REGNUM;
647641
else if (reggroup == restore_reggroup || reggroup == save_reggroup)
648642
return regnum <= RISCV_LAST_FP_REGNUM;
649-
else if (reggroup == system_reggroup)
650-
return regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM;
651-
else if (reggroup == vector_reggroup)
643+
else if (reggroup == system_reggroup) {
644+
/* Only include CSRs that have aliases. */
645+
if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
646+
return 0;
647+
for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i) {
648+
if (regnum == riscv_register_aliases[i].regnum)
649+
return 1;
650+
}
651+
return 0;
652+
} else if (reggroup == vector_reggroup)
652653
return 0;
653654
else
654655
internal_error (__FILE__, __LINE__, _("unhandled reggroup"));
655656
}
656657

658+
static void
659+
riscv_print_registers_info (struct gdbarch *gdbarch,
660+
struct ui_file *file,
661+
struct frame_info *frame,
662+
int regnum,
663+
int all)
664+
{
665+
/* Use by 'info all-registers'. */
666+
struct reggroup *reggroup;
667+
668+
if (regnum != -1)
669+
{
670+
/* Print one specified register. */
671+
gdb_assert (regnum < RISCV_LAST_REGNUM);
672+
if (NULL == register_name (gdbarch, regnum, 1))
673+
error (_("Not a valid register for the current processor type"));
674+
riscv_print_register_formatted (file, frame, regnum);
675+
return;
676+
}
677+
678+
if (all)
679+
reggroup = all_reggroup;
680+
else
681+
reggroup = general_reggroup;
682+
for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
683+
{
684+
/* Zero never changes, so might as well hide by default. */
685+
if (regnum == RISCV_ZERO_REGNUM && !all)
686+
continue;
687+
if (riscv_register_reggroup_p(gdbarch, regnum, reggroup))
688+
riscv_print_register_formatted (file, frame, regnum);
689+
}
690+
}
691+
657692
static ULONGEST
658693
riscv_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr)
659694
{
@@ -718,7 +753,7 @@ riscv_scan_prologue (struct gdbarch *gdbarch,
718753
int seen_sp_adjust = 0;
719754
int load_immediate_bytes = 0;
720755

721-
/* Can be called when there's no process, and hence when there's no THIS_FRAME. */
756+
/* Can be called when there's no process, and hence when there's no THIS_FRAME. */
722757
if (this_frame != NULL)
723758
sp = get_frame_register_signed (this_frame, RISCV_SP_REGNUM);
724759
else
@@ -1115,7 +1150,7 @@ riscv_gdbarch_init (struct gdbarch_info info,
11151150
set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
11161151
set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
11171152
set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
1118-
set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FIRST_FP_REGNUM);
1153+
set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
11191154

11201155
/* Functions to supply register information. */
11211156
set_gdbarch_register_name (gdbarch, riscv_register_name);
@@ -1157,8 +1192,15 @@ riscv_gdbarch_init (struct gdbarch_info info,
11571192
tdesc_data = tdesc_data_alloc ();
11581193

11591194
valid_p = 1;
1160-
for (i = RISCV_ZERO_REGNUM; i < RISCV_LAST_REGNUM; ++i)
1161-
valid_p &= tdesc_numbered_register (feature, tdesc_data, i, riscv_gdb_reg_names[i]);
1195+
for (i = RISCV_ZERO_REGNUM; i <= RISCV_LAST_FP_REGNUM; ++i)
1196+
valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1197+
riscv_gdb_reg_names[i]);
1198+
for (i = RISCV_FIRST_CSR_REGNUM; i <= RISCV_LAST_CSR_REGNUM; ++i)
1199+
{
1200+
char buf[20];
1201+
sprintf (buf, "csr%d", i - RISCV_FIRST_CSR_REGNUM);
1202+
valid_p &= tdesc_numbered_register (feature, tdesc_data, i, buf);
1203+
}
11621204

11631205
if (!valid_p)
11641206
tdesc_data_cleanup (tdesc_data);

gdb/riscv-tdep.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -71,17 +71,17 @@ enum {
7171
RISCV_FA1_REGNUM = 50,
7272
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
7373

74-
#define RISCV_FIRST_CSR_REGNUM RISCV_LAST_FP_REGNUM + 1
75-
#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM,
74+
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
75+
#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num,
7676
#include "opcode/riscv-opc.h"
7777
#undef DECLARE_CSR
78-
#define RISCV_LAST_CSR_REGNUM RISCV_LAST_REGNUM - 1
78+
RISCV_LAST_CSR_REGNUM = 4160,
7979

8080
/* Leave this as the last enum. */
81-
RISCV_LAST_REGNUM
81+
RISCV_NUM_REGS
8282
};
8383

84-
#define RISCV_NUM_REGS (RISCV_LAST_REGNUM)
84+
#define RISCV_LAST_REGNUM (RISCV_NUM_REGS - 1)
8585

8686
/* RISC-V specific per-architecture information. */
8787
struct gdbarch_tdep

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