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Misaligned fetch bit must be excluded for RVC #12

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as-sc opened this issue Feb 5, 2019 · 1 comment

as-sc commented Feb 5, 2019

riscv-test-env/p/riscv_test.h

Line 160 in 6f31769

(1 << CAUSE_MISALIGNED_FETCH) | \

as-sc mentioned this issue

Misaligned fetch bit must be excluded for RVC riscv-non-isa/riscv-arch-test#42

Closed

pdonahue-ventana mentioned this issue

Assumptions about medeleg WARL behavior #17

Closed

Contributor

pdonahue-ventana commented Feb 24, 2020

#18 fixes this so I think that this issue can be closed by someone with permission to do so.

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