mtimecmp is memory-mapped but stimecmp is not

[omerguzelelectronicguy]

In the section of stimecmp, it is not mentioned that stimecmp is memory-mapped. However, mtimecmp is. I wonder the reason for chosing one of them is memory mapped and the other one not. In the riscv aclint spec, there is only mtimecmp but the memory region was 2-times of the Machine-level Software Interrupt Device. I thought stimecmp or the supervisor timer interrupts will be driven from aclint in the future release, just like mtimecmp is. Am I missing a specific reason?

[aswaterman]

See the Sstc extension: https://github.com/riscv/riscv-isa-manual/blob/main/src/sstc.adoc

[omerguzelelectronicguy]

@aswaterman Thanks for the answer. I already read that part of the spec (read again). I understand the reason for adding stimecmp. It is to have timer interrupt for supervisor level without the help of the mahcine mode timer interrupts. I didn't understand why it is a CSR rather than a memory-mapped register like mtimecmp. Is the STIMECMP register placed as CSR because CSR instructions are faster than memory instructions?