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csrs.cc
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csrs.cc
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// See LICENSE for license details.
// For std::any_of
#include <algorithm>
#include "csrs.h"
// For processor_t:
#include "processor.h"
#include "mmu.h"
// For get_field():
#include "decode_macros.h"
// For trap_virtual_instruction and trap_illegal_instruction:
#include "trap.h"
// For require():
#include "insn_macros.h"
// For CSR_DCSR_V:
#include "debug_defines.h"
// STATE macro used by require_privilege() macro:
#undef STATE
#define STATE (*state)
// implement class csr_t
csr_t::csr_t(processor_t* const proc, const reg_t addr):
proc(proc),
state(proc->get_state()),
address(addr),
csr_priv(get_field(addr, 0x300)),
csr_read_only(get_field(addr, 0xC00) == 3) {
}
void csr_t::verify_permissions(insn_t insn, bool write) const {
// Check permissions. Raise virtual-instruction exception if V=1,
// privileges are insufficient, and the CSR belongs to supervisor or
// hypervisor. Raise illegal-instruction exception otherwise.
unsigned priv = state->prv == PRV_S && !state->v ? PRV_HS : state->prv;
if ((csr_priv == PRV_S && !proc->extension_enabled('S')) ||
(csr_priv == PRV_HS && !proc->extension_enabled('H')))
throw trap_illegal_instruction(insn.bits());
if (write && csr_read_only)
throw trap_illegal_instruction(insn.bits());
if (priv < csr_priv) {
if (state->v && csr_priv <= PRV_HS)
throw trap_virtual_instruction(insn.bits());
throw trap_illegal_instruction(insn.bits());
}
}
csr_t::~csr_t() {
}
void csr_t::write(const reg_t val) noexcept {
const bool success = unlogged_write(val);
if (success) {
log_write();
}
}
void csr_t::log_write() const noexcept {
log_special_write(address, written_value());
}
void csr_t::log_special_write(const reg_t UNUSED address, const reg_t UNUSED val) const noexcept {
if (proc->get_log_commits_enabled())
proc->get_state()->log_reg_write[((address) << 4) | 4] = {val, 0};
}
reg_t csr_t::written_value() const noexcept {
return read();
}
// implement class basic_csr_t
basic_csr_t::basic_csr_t(processor_t* const proc, const reg_t addr, const reg_t init):
csr_t(proc, addr),
val(init) {
}
bool basic_csr_t::unlogged_write(const reg_t val) noexcept {
this->val = val;
return true;
}
// implement class pmpaddr_csr_t
pmpaddr_csr_t::pmpaddr_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
val(0),
cfg(0),
pmpidx(address - CSR_PMPADDR0) {
}
void pmpaddr_csr_t::verify_permissions(insn_t insn, bool write) const {
csr_t::verify_permissions(insn, write);
// If n_pmp is zero, that means pmp is not implemented hence raise
// trap if it tries to access the csr. I would prefer to implement
// this by not instantiating any pmpaddr_csr_t for these regs, but
// n_pmp can change after reset() is run.
if (proc->n_pmp == 0)
throw trap_illegal_instruction(insn.bits());
}
reg_t pmpaddr_csr_t::read() const noexcept {
if ((cfg & PMP_A) >= PMP_NAPOT)
return val | (~proc->pmp_tor_mask() >> 1);
return val & proc->pmp_tor_mask();
}
bool pmpaddr_csr_t::unlogged_write(const reg_t val) noexcept {
// If no PMPs are configured, disallow access to all. Otherwise,
// allow access to all, but unimplemented ones are hardwired to
// zero. Note that n_pmp can change after reset(); otherwise I would
// implement this in state_t::reset() by instantiating the correct
// number of pmpaddr_csr_t.
if (proc->n_pmp == 0)
return false;
const bool lock_bypass = state->mseccfg->get_rlb();
const bool locked = !lock_bypass && (cfg & PMP_L);
if (pmpidx < proc->n_pmp && !locked && !next_locked_and_tor()) {
this->val = val & ((reg_t(1) << (MAX_PADDR_BITS - PMP_SHIFT)) - 1);
}
else
return false;
proc->get_mmu()->flush_tlb();
return true;
}
bool pmpaddr_csr_t::next_locked_and_tor() const noexcept {
if (pmpidx+1 >= state->max_pmp) return false; // this is the last entry
const bool lock_bypass = state->mseccfg->get_rlb();
const bool next_locked = !lock_bypass && (state->pmpaddr[pmpidx+1]->cfg & PMP_L);
const bool next_tor = (state->pmpaddr[pmpidx+1]->cfg & PMP_A) == PMP_TOR;
return next_locked && next_tor;
}
reg_t pmpaddr_csr_t::tor_paddr() const noexcept {
return (val & proc->pmp_tor_mask()) << PMP_SHIFT;
}
reg_t pmpaddr_csr_t::tor_base_paddr() const noexcept {
if (pmpidx == 0) return 0; // entry 0 always uses 0 as base
return state->pmpaddr[pmpidx-1]->tor_paddr();
}
reg_t pmpaddr_csr_t::napot_mask() const noexcept {
bool is_na4 = (cfg & PMP_A) == PMP_NA4;
reg_t mask = (val << 1) | (!is_na4) | ~proc->pmp_tor_mask();
return ~(mask & ~(mask + 1)) << PMP_SHIFT;
}
bool pmpaddr_csr_t::match4(reg_t addr) const noexcept {
if ((cfg & PMP_A) == 0) return false;
bool is_tor = (cfg & PMP_A) == PMP_TOR;
if (is_tor) return tor_base_paddr() <= addr && addr < tor_paddr();
// NAPOT or NA4:
return ((addr ^ tor_paddr()) & napot_mask()) == 0;
}
bool pmpaddr_csr_t::subset_match(reg_t addr, reg_t len) const noexcept {
if ((addr | len) & (len - 1))
abort();
reg_t base = tor_base_paddr();
reg_t tor = tor_paddr();
if ((cfg & PMP_A) == 0) return false;
bool is_tor = (cfg & PMP_A) == PMP_TOR;
bool begins_after_lower = addr >= base;
bool begins_after_upper = addr >= tor;
bool ends_before_lower = (addr & -len) < (base & -len);
bool ends_before_upper = (addr & -len) < (tor & -len);
bool tor_homogeneous = ends_before_lower || begins_after_upper ||
(begins_after_lower && ends_before_upper);
bool mask_homogeneous = ~(napot_mask() << 1) & len;
bool napot_homogeneous = mask_homogeneous || ((addr ^ tor) / len) != 0;
return !(is_tor ? tor_homogeneous : napot_homogeneous);
}
bool pmpaddr_csr_t::access_ok(access_type type, reg_t mode, bool hlvx) const noexcept {
const bool cfgx = cfg & PMP_X;
const bool cfgw = cfg & PMP_W;
const bool cfgr = cfg & PMP_R;
const bool cfgl = cfg & PMP_L;
const bool prvm = mode == PRV_M;
const bool typer = type == LOAD;
const bool typex = type == FETCH;
const bool typew = type == STORE;
const bool normal_rwx = (typer && cfgr && (!hlvx || cfgx)) || (typew && cfgw) || (typex && cfgx);
const bool mseccfg_mml = state->mseccfg->get_mml();
if (mseccfg_mml) {
if (cfgx && cfgw && cfgr && cfgl) {
// Locked Shared data region: Read only on both M and S/U mode.
return typer && !hlvx;
} else {
const bool mml_shared_region = !cfgr && cfgw;
const bool mml_chk_normal = (prvm == cfgl) && normal_rwx;
const bool mml_chk_shared =
(!cfgl && cfgx && ((typer && !hlvx) || typew)) ||
(!cfgl && !cfgx && ((typer && !hlvx) || (typew && prvm))) ||
(cfgl && typex) ||
(cfgl && typer && cfgx && prvm);
return mml_shared_region ? mml_chk_shared : mml_chk_normal;
}
} else {
const bool m_bypass = (prvm && !cfgl);
return m_bypass || normal_rwx;
}
}
// implement class pmpcfg_csr_t
pmpcfg_csr_t::pmpcfg_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr) {
}
void pmpcfg_csr_t::verify_permissions(insn_t insn, bool write) const {
csr_t::verify_permissions(insn, write);
// If n_pmp is zero, that means pmp is not implemented hence raise
// trap if it tries to access the csr. I would prefer to implement
// this by not instantiating any pmpcfg_csr_t for these regs, but
// n_pmp can change after reset() is run.
if (proc->n_pmp == 0)
throw trap_illegal_instruction(insn.bits());
}
reg_t pmpcfg_csr_t::read() const noexcept {
reg_t cfg_res = 0;
for (size_t i0 = (address - CSR_PMPCFG0) * 4, i = i0; i < i0 + proc->get_xlen() / 8 && i < state->max_pmp; i++)
cfg_res |= reg_t(state->pmpaddr[i]->cfg) << (8 * (i - i0));
return cfg_res;
}
bool pmpcfg_csr_t::unlogged_write(const reg_t val) noexcept {
if (proc->n_pmp == 0)
return false;
bool write_success = false;
const bool rlb = state->mseccfg->get_rlb();
const bool mml = state->mseccfg->get_mml();
for (size_t i0 = (address - CSR_PMPCFG0) * 4, i = i0; i < i0 + proc->get_xlen() / 8; i++) {
if (i < proc->n_pmp) {
const bool locked = (state->pmpaddr[i]->cfg & PMP_L);
if (rlb || !locked) {
uint8_t cfg = (val >> (8 * (i - i0))) & (PMP_R | PMP_W | PMP_X | PMP_A | PMP_L);
// Drop R=0 W=1 when MML = 0
// Remove the restriction when MML = 1
if (!mml) {
cfg &= ~PMP_W | ((cfg & PMP_R) ? PMP_W : 0);
}
// Disallow A=NA4 when granularity > 4
if (proc->lg_pmp_granularity != PMP_SHIFT && (cfg & PMP_A) == PMP_NA4)
cfg |= PMP_NAPOT;
/*
* Adding a rule with executable privileges that either is M-mode-only or a locked Shared-Region
* is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged.
* This restriction can be temporarily lifted e.g. during the boot process, by setting mseccfg.RLB.
*/
const bool cfgx = cfg & PMP_X;
const bool cfgw = cfg & PMP_W;
const bool cfgr = cfg & PMP_R;
if (rlb || !(mml && ((cfg & PMP_L) // M-mode-only or a locked Shared-Region
&& !(cfgx && cfgw && cfgr) // RWX = 111 is allowed
&& (cfgx || (cfgw && !cfgr)) // X=1 or RW=01 is not allowed
))) {
state->pmpaddr[i]->cfg = cfg;
}
}
write_success = true;
}
}
proc->get_mmu()->flush_tlb();
return write_success;
}
// implement class mseccfg_csr_t
mseccfg_csr_t::mseccfg_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
void mseccfg_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled(EXT_SMEPMP) &&
!proc->extension_enabled(EXT_SMMPM) &&
!proc->extension_enabled(EXT_ZICFILP) &&
!proc->extension_enabled(EXT_ZKR))
throw trap_illegal_instruction(insn.bits());
}
bool mseccfg_csr_t::get_mml() const noexcept {
return (read() & MSECCFG_MML);
}
bool mseccfg_csr_t::get_mmwp() const noexcept {
return (read() & MSECCFG_MMWP);
}
bool mseccfg_csr_t::get_rlb() const noexcept {
return (read() & MSECCFG_RLB);
}
bool mseccfg_csr_t::get_useed() const noexcept {
return (read() & MSECCFG_USEED);
}
bool mseccfg_csr_t::get_sseed() const noexcept {
return (read() & MSECCFG_SSEED);
}
bool mseccfg_csr_t::unlogged_write(const reg_t val) noexcept {
if (proc->n_pmp == 0)
return false;
// pmpcfg.L is 1 in any rule or entry (including disabled entries)
const bool pmplock_recorded = std::any_of(state->pmpaddr, state->pmpaddr + proc->n_pmp,
[](const pmpaddr_csr_t_p & c) { return c->is_locked(); } );
reg_t new_val = read();
// When RLB is 0 and pmplock_recorded, RLB is locked to 0.
// Otherwise set the RLB bit according val
if (!(pmplock_recorded && (read() & MSECCFG_RLB) == 0)) {
new_val &= ~MSECCFG_RLB;
new_val |= (val & MSECCFG_RLB);
}
new_val |= (val & MSECCFG_MMWP); //MMWP is sticky
new_val |= (val & MSECCFG_MML); //MML is sticky
if (proc->extension_enabled(EXT_ZKR)) {
uint64_t mask = MSECCFG_USEED | MSECCFG_SSEED;
new_val = (new_val & ~mask) | (val & mask);
}
proc->get_mmu()->flush_tlb();
if (proc->extension_enabled(EXT_ZICFILP)) {
new_val &= ~MSECCFG_MLPE;
new_val |= (val & MSECCFG_MLPE);
}
if (proc->extension_enabled(EXT_SMMPM)) {
const reg_t pmm_reserved = 1; // Reserved value of mseccfg.PMM
reg_t pmm = get_field(val, MSECCFG_PMM);
new_val = set_field(new_val, MSECCFG_PMM, pmm != pmm_reserved ? pmm : 0);
}
return basic_csr_t::unlogged_write(new_val);
}
// implement class virtualized_csr_t
virtualized_csr_t::virtualized_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt):
csr_t(proc, orig->address),
orig_csr(orig),
virt_csr(virt) {
}
reg_t virtualized_csr_t::read() const noexcept {
return readvirt(state->v);
}
reg_t virtualized_csr_t::readvirt(bool virt) const noexcept {
return virt ? virt_csr->read() : orig_csr->read();
}
bool virtualized_csr_t::unlogged_write(const reg_t val) noexcept {
if (state->v)
virt_csr->write(val);
else
orig_csr->write(val);
return false; // virt_csr or orig_csr has already logged
}
// implement class epc_csr_t
epc_csr_t::epc_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
val(0) {
}
reg_t epc_csr_t::read() const noexcept {
return val & proc->pc_alignment_mask();
}
bool epc_csr_t::unlogged_write(const reg_t val) noexcept {
this->val = val & ~(reg_t)1;
return true;
}
// implement class tvec_csr_t
tvec_csr_t::tvec_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
val(0) {
}
reg_t tvec_csr_t::read() const noexcept {
return val;
}
bool tvec_csr_t::unlogged_write(const reg_t val) noexcept {
this->val = val & ~(reg_t)2;
return true;
}
// implement class cause_csr_t
cause_csr_t::cause_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
reg_t cause_csr_t::read() const noexcept {
reg_t val = basic_csr_t::read();
// When reading, the interrupt bit needs to adjust to xlen. Spike does
// not generally support dynamic xlen, but this code was (partly)
// there since at least 2015 (ea58df8 and c4350ef).
if (proc->get_isa().get_max_xlen() > proc->get_xlen()) // Move interrupt bit to top of xlen
return val | ((val >> (proc->get_isa().get_max_xlen()-1)) << (proc->get_xlen()-1));
return val;
}
// implement class base_status_csr_t
base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
has_page(proc->extension_enabled_const('S') && proc->supports_impl(IMPL_MMU)),
sstatus_write_mask(compute_sstatus_write_mask()),
sstatus_read_mask(sstatus_write_mask | SSTATUS_UBE | SSTATUS_UXL
| (proc->get_const_xlen() == 32 ? SSTATUS32_SD : SSTATUS64_SD)) {
}
reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept {
// If a configuration has FS bits, they will always be accessible no
// matter the state of misa.
const bool has_fs = (proc->extension_enabled('S') || proc->extension_enabled('F')) && !proc->extension_enabled(EXT_ZFINX);
// Implementations w/o V may still have mstatus.vs,
const bool has_vs = proc->any_vector_extensions();
return 0
| (proc->extension_enabled('S') ? (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP) : 0)
| (has_page ? (SSTATUS_SUM | SSTATUS_MXR) : 0)
| (has_fs ? SSTATUS_FS : 0)
| (proc->any_custom_extensions() ? SSTATUS_XS : 0)
| (has_vs ? SSTATUS_VS : 0)
| (proc->extension_enabled(EXT_ZICFILP) ? SSTATUS_SPELP : 0)
| (proc->extension_enabled(EXT_SSDBLTRP) ? SSTATUS_SDT : 0)
;
}
reg_t base_status_csr_t::adjust_sd(const reg_t val) const noexcept {
// This uses get_const_xlen() instead of get_xlen() not only because
// the variable is static, so it's only called once, but also
// because the SD bit moves when XLEN changes, which means we would
// need to call adjust_sd() on every read, instead of on every
// write.
static const reg_t sd_bit = proc->get_const_xlen() == 64 ? SSTATUS64_SD : SSTATUS32_SD;
if (((val & SSTATUS_FS) == SSTATUS_FS) ||
((val & SSTATUS_VS) == SSTATUS_VS) ||
((val & SSTATUS_XS) == SSTATUS_XS)) {
return val | sd_bit;
}
return val & ~sd_bit;
}
void base_status_csr_t::maybe_flush_tlb(const reg_t newval) noexcept {
if ((newval ^ read()) &
(MSTATUS_MPP | MSTATUS_MPRV
| (has_page ? (MSTATUS_MXR | MSTATUS_SUM) : 0)
))
proc->get_mmu()->flush_tlb();
}
namespace {
int xlen_to_uxl(int xlen) {
if (xlen == 32)
return 1;
if (xlen == 64)
return 2;
abort();
}
}
// implement class vsstatus_csr_t
vsstatus_csr_t::vsstatus_csr_t(processor_t* const proc, const reg_t addr):
base_status_csr_t(proc, addr),
val(proc->get_state()->mstatus->read() & sstatus_read_mask) {
}
bool vsstatus_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t hDTE = (state->henvcfg->read() & HENVCFG_DTE);
const reg_t adj_write_mask = sstatus_write_mask & ~(hDTE ? 0 : SSTATUS_SDT);
reg_t newval = (this->val & ~adj_write_mask) | (val & adj_write_mask);
newval = (newval & SSTATUS_SDT) ? (newval & ~SSTATUS_SIE) : newval;
if (state->v) maybe_flush_tlb(newval);
this->val = adjust_sd(newval);
return true;
}
reg_t vsstatus_csr_t::read() const noexcept {
const reg_t hDTE = state->henvcfg->read() & HENVCFG_DTE;
const reg_t adj_read_mask = sstatus_read_mask & ~(hDTE ? 0 : SSTATUS_SDT);
return this->val & adj_read_mask;
}
// implement class sstatus_proxy_csr_t
sstatus_proxy_csr_t::sstatus_proxy_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus):
base_status_csr_t(proc, addr),
mstatus(mstatus) {
}
bool sstatus_proxy_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t mDTE = (state->menvcfg->read() & MENVCFG_DTE);
const reg_t adj_write_mask = sstatus_write_mask & ~(mDTE ? 0 : SSTATUS_SDT);
reg_t new_mstatus = (mstatus->read() & ~adj_write_mask) | (val & adj_write_mask);
new_mstatus = (new_mstatus & SSTATUS_SDT) ? (new_mstatus & ~SSTATUS_SIE) : new_mstatus;
// On RV32 this will only log the low 32 bits, so make sure we're
// not modifying anything in the upper 32 bits.
assert((adj_write_mask & 0xffffffffU) == adj_write_mask);
mstatus->write(new_mstatus);
return false; // avoid double logging: already logged by mstatus->write()
}
reg_t sstatus_proxy_csr_t::read() const noexcept {
const reg_t mDTE = state->menvcfg->read() & MENVCFG_DTE;
const reg_t adj_read_mask = sstatus_read_mask & ~(mDTE ? 0 : SSTATUS_SDT);
return mstatus->read() & adj_read_mask;
}
// implement class mstatus_csr_t
mstatus_csr_t::mstatus_csr_t(processor_t* const proc, const reg_t addr):
base_status_csr_t(proc, addr),
val(compute_mstatus_initial_value()) {
}
bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept {
const bool has_mpv = proc->extension_enabled('H');
const bool has_gva = has_mpv;
const reg_t mask = sstatus_write_mask
| MSTATUS_MIE | MSTATUS_MPIE
| (proc->extension_enabled('U') ? MSTATUS_MPRV : 0)
| MSTATUS_MPP | MSTATUS_TW
| (proc->extension_enabled('S') ? MSTATUS_TSR : 0)
| (has_page ? MSTATUS_TVM : 0)
| (has_gva ? MSTATUS_GVA : 0)
| (has_mpv ? MSTATUS_MPV : 0)
| (proc->extension_enabled(EXT_SMDBLTRP) ? MSTATUS_MDT : 0)
| (proc->extension_enabled(EXT_ZICFILP) ? (MSTATUS_SPELP | MSTATUS_MPELP) : 0)
| (proc->extension_enabled(EXT_SSDBLTRP) ? SSTATUS_SDT : 0)
;
const reg_t requested_mpp = proc->legalize_privilege(get_field(val, MSTATUS_MPP));
const reg_t adjusted_val = set_field(val, MSTATUS_MPP, requested_mpp);
reg_t new_mstatus = (read() & ~mask) | (adjusted_val & mask);
new_mstatus = (new_mstatus & MSTATUS_MDT) ? (new_mstatus & ~MSTATUS_MIE) : new_mstatus;
new_mstatus = (new_mstatus & MSTATUS_SDT) ? (new_mstatus & ~MSTATUS_SIE) : new_mstatus;
maybe_flush_tlb(new_mstatus);
this->val = adjust_sd(new_mstatus);
return true;
}
reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept {
const reg_t big_endian_bits = (proc->extension_enabled_const('U') ? MSTATUS_UBE : 0)
| (proc->extension_enabled_const('S') ? MSTATUS_SBE : 0)
| MSTATUS_MBE;
return 0
| set_field((reg_t)0, MSTATUS_MPP, proc->extension_enabled_const('U') ? PRV_U : PRV_M)
| (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0)
| (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0)
| (proc->get_mmu()->is_target_big_endian() ? big_endian_bits : 0)
| (proc->extension_enabled(EXT_SMDBLTRP) ? MSTATUS_MDT : 0)
| 0; // initial value for mstatus
}
// implement class mnstatus_csr_t
mnstatus_csr_t::mnstatus_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
bool mnstatus_csr_t::unlogged_write(const reg_t val) noexcept {
// NMIE can be set but not cleared
const reg_t mask = (~read() & MNSTATUS_NMIE)
| (proc->extension_enabled('H') ? MNSTATUS_MNPV : 0)
| MNSTATUS_MNPP;
const reg_t requested_mnpp = proc->legalize_privilege(get_field(val, MNSTATUS_MNPP));
const reg_t adjusted_val = set_field(val, MNSTATUS_MNPP, requested_mnpp);
const reg_t new_mnstatus = (read() & ~mask) | (adjusted_val & mask);
return basic_csr_t::unlogged_write(new_mnstatus);
}
// implement class rv32_low_csr_t
rv32_low_csr_t::rv32_low_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig):
csr_t(proc, addr),
orig(orig) {
}
reg_t rv32_low_csr_t::read() const noexcept {
return orig->read() & 0xffffffffU;
}
void rv32_low_csr_t::verify_permissions(insn_t insn, bool write) const {
orig->verify_permissions(insn, write);
}
bool rv32_low_csr_t::unlogged_write(const reg_t val) noexcept {
return orig->unlogged_write((orig->written_value() >> 32 << 32) | (val & 0xffffffffU));
}
reg_t rv32_low_csr_t::written_value() const noexcept {
return orig->written_value() & 0xffffffffU;
}
// implement class rv32_high_csr_t
rv32_high_csr_t::rv32_high_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig):
csr_t(proc, addr),
orig(orig) {
}
reg_t rv32_high_csr_t::read() const noexcept {
return (orig->read() >> 32) & 0xffffffffU;
}
void rv32_high_csr_t::verify_permissions(insn_t insn, bool write) const {
orig->verify_permissions(insn, write);
}
bool rv32_high_csr_t::unlogged_write(const reg_t val) noexcept {
return orig->unlogged_write((orig->written_value() << 32 >> 32) | ((val & 0xffffffffU) << 32));
}
reg_t rv32_high_csr_t::written_value() const noexcept {
return (orig->written_value() >> 32) & 0xffffffffU;
}
// implement class sstatus_csr_t
sstatus_csr_t::sstatus_csr_t(processor_t* const proc, sstatus_proxy_csr_t_p orig, vsstatus_csr_t_p virt):
virtualized_csr_t(proc, orig, virt),
orig_sstatus(orig),
virt_sstatus(virt) {
}
void sstatus_csr_t::dirty(const reg_t dirties) {
// As an optimization, return early if already dirty.
if ((orig_sstatus->read() & dirties) == dirties) {
if (likely(!state->v || (virt_sstatus->read() & dirties) == dirties))
return;
}
// Catch problems like #823 where P-extension instructions were not
// checking for mstatus.VS!=Off:
if (!enabled(dirties)) abort();
orig_sstatus->write(orig_sstatus->read() | dirties);
if (state->v) {
virt_sstatus->write(virt_sstatus->read() | dirties);
}
}
bool sstatus_csr_t::enabled(const reg_t which) {
if ((orig_sstatus->read() & which) != 0) {
if (!state->v || (virt_sstatus->read() & which) != 0)
return true;
}
return false;
}
// implement class misa_csr_t
misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa):
basic_csr_t(proc, addr, max_isa),
max_isa(max_isa),
write_mask(max_isa & (0 // allow MABFDQCHV bits in MISA to be modified
| (1L << ('M' - 'A'))
| (1L << ('A' - 'A'))
| (1L << ('B' - 'A'))
| (1L << ('F' - 'A'))
| (1L << ('D' - 'A'))
| (1L << ('Q' - 'A'))
| (1L << ('C' - 'A'))
| (1L << ('H' - 'A'))
| (1L << ('V' - 'A'))
)
) {
}
reg_t misa_csr_t::dependency(const reg_t val, const char feature, const char depends_on) const noexcept {
return (val & (1L << (depends_on - 'A'))) ? val : (val & ~(1L << (feature - 'A')));
}
bool misa_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t old_misa = read();
// the write is ignored if increasing IALIGN would misalign the PC
if (!(val & (1L << ('C' - 'A'))) && (old_misa & (1L << ('C' - 'A'))) && (state->pc & 2))
return false;
reg_t adjusted_val = val;
adjusted_val = dependency(adjusted_val, 'D', 'F');
adjusted_val = dependency(adjusted_val, 'Q', 'D');
adjusted_val = dependency(adjusted_val, 'V', 'D');
const bool prev_h = old_misa & (1L << ('H' - 'A'));
const reg_t new_misa = (adjusted_val & write_mask) | (old_misa & ~write_mask);
const bool new_h = new_misa & (1L << ('H' - 'A'));
proc->set_extension_enable(EXT_ZCA, (new_misa & (1L << ('C' - 'A'))) || !proc->get_isa().extension_enabled('C'));
proc->set_extension_enable(EXT_ZCF, (new_misa & (1L << ('F' - 'A'))) && proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZCD, (new_misa & (1L << ('D' - 'A'))) && proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZCB, proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZCMP, proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZCMT, proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZFH, new_misa & (1L << ('F' - 'A')));
proc->set_extension_enable(EXT_ZFHMIN, new_misa & (1L << ('F' - 'A')));
proc->set_extension_enable(EXT_ZVFH, (new_misa & (1L << ('V' - 'A'))) && proc->extension_enabled(EXT_ZFHMIN));
proc->set_extension_enable(EXT_ZVFHMIN, new_misa & (1L << ('V' - 'A')));
proc->set_extension_enable(EXT_ZAAMO, (new_misa & (1L << ('A' - 'A'))) || !proc->get_isa().extension_enabled('A'));
proc->set_extension_enable(EXT_ZALRSC, (new_misa & (1L << ('A' - 'A'))) || !proc->get_isa().extension_enabled('A'));
proc->set_extension_enable(EXT_ZBA, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
proc->set_extension_enable(EXT_ZBB, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
proc->set_extension_enable(EXT_ZBS, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
// update the hypervisor-only bits in MEDELEG and other CSRs
if (!new_h && prev_h) {
reg_t hypervisor_exceptions = 0
| (1 << CAUSE_VIRTUAL_SUPERVISOR_ECALL)
| (1 << CAUSE_FETCH_GUEST_PAGE_FAULT)
| (1 << CAUSE_LOAD_GUEST_PAGE_FAULT)
| (1 << CAUSE_VIRTUAL_INSTRUCTION)
| (1 << CAUSE_STORE_GUEST_PAGE_FAULT)
;
state->medeleg->write(state->medeleg->read() & ~hypervisor_exceptions);
if (state->mnstatus) state->mnstatus->write(state->mnstatus->read() & ~MNSTATUS_MNPV);
const reg_t new_mstatus = state->mstatus->read() & ~(MSTATUS_GVA | MSTATUS_MPV);
state->mstatus->write(new_mstatus);
if (state->mstatush) state->mstatush->write(new_mstatus >> 32); // log mstatush change
state->mie->write_with_mask(MIP_HS_MASK, 0); // also takes care of hie, sie
state->mip->write_with_mask(MIP_HS_MASK, 0); // also takes care of hip, sip, hvip
state->hstatus->write(0);
for (reg_t i = 0; i < N_HPMCOUNTERS; ++i) {
const reg_t new_mevent = state->mevent[i]->read() & ~(MHPMEVENT_VUINH | MHPMEVENT_VSINH);
state->mevent[i]->write(new_mevent);
}
}
return basic_csr_t::unlogged_write(new_misa);
}
bool misa_csr_t::extension_enabled_const(unsigned char ext) const noexcept {
assert(!(1 & (write_mask >> (ext - 'A'))));
return extension_enabled(ext);
}
// implement class mip_or_mie_csr_t
mip_or_mie_csr_t::mip_or_mie_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
val(0) {
}
reg_t mip_or_mie_csr_t::read() const noexcept {
return val;
}
void mip_or_mie_csr_t::write_with_mask(const reg_t mask, const reg_t val) noexcept {
this->val = (this->val & ~mask) | (val & mask);
log_write();
}
bool mip_or_mie_csr_t::unlogged_write(const reg_t val) noexcept {
write_with_mask(write_mask(), val);
return false; // avoid double logging: already logged by write_with_mask()
}
mip_csr_t::mip_csr_t(processor_t* const proc, const reg_t addr):
mip_or_mie_csr_t(proc, addr) {
}
reg_t mip_csr_t::read() const noexcept {
return val | state->hvip->basic_csr_t::read();
}
void mip_csr_t::backdoor_write_with_mask(const reg_t mask, const reg_t val) noexcept {
this->val = (this->val & ~mask) | (val & mask);
}
reg_t mip_csr_t::write_mask() const noexcept {
// MIP_STIP is writable unless SSTC exists and STCE is set in MENVCFG
const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | ((state->menvcfg->read() & MENVCFG_STCE) ? 0 : MIP_STIP) | MIP_SEIP : 0;
const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0;
const reg_t vssip_int = proc->extension_enabled('H') ? MIP_VSSIP : 0;
const reg_t hypervisor_ints = proc->extension_enabled('H') ? MIP_HS_MASK : 0;
// We must mask off sgeip, vstip, and vseip. All three of these
// bits are aliases for the same bits in hip. The hip spec says:
// * sgeip is read-only -- write hgeip instead
// * vseip is read-only -- write hvip instead
// * vstip is read-only -- write hvip instead
return (supervisor_ints | hypervisor_ints | lscof_int) &
(MIP_SEIP | MIP_SSIP | MIP_STIP | MIP_LCOFIP | vssip_int);
}
mie_csr_t::mie_csr_t(processor_t* const proc, const reg_t addr):
mip_or_mie_csr_t(proc, addr) {
}
reg_t mie_csr_t::write_mask() const noexcept {
const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | MIP_STIP | MIP_SEIP : 0;
const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0;
const reg_t hypervisor_ints = proc->extension_enabled('H') ? MIP_HS_MASK : 0;
const reg_t coprocessor_ints = (reg_t)proc->any_custom_extensions() << IRQ_COP;
const reg_t delegable_ints = supervisor_ints | coprocessor_ints | lscof_int;
const reg_t all_ints = delegable_ints | hypervisor_ints | MIP_MSIP | MIP_MTIP | MIP_MEIP;
return all_ints;
}
// implement class generic_int_accessor_t
generic_int_accessor_t::generic_int_accessor_t(state_t* const state,
const reg_t read_mask,
const reg_t ip_write_mask,
const reg_t ie_write_mask,
const mask_mode_t mask_mode,
const int shiftamt):
state(state),
read_mask(read_mask),
ip_write_mask(ip_write_mask),
ie_write_mask(ie_write_mask),
mask_mideleg(mask_mode == MIDELEG),
mask_hideleg(mask_mode == HIDELEG),
shiftamt(shiftamt) {
}
reg_t generic_int_accessor_t::ip_read() const noexcept {
return (state->mip->read() & deleg_mask() & read_mask) >> shiftamt;
}
void generic_int_accessor_t::ip_write(const reg_t val) noexcept {
const reg_t mask = deleg_mask() & ip_write_mask;
state->mip->write_with_mask(mask, val << shiftamt);
}
reg_t generic_int_accessor_t::ie_read() const noexcept {
return (state->mie->read() & deleg_mask() & read_mask) >> shiftamt;
}
void generic_int_accessor_t::ie_write(const reg_t val) noexcept {
const reg_t mask = deleg_mask() & ie_write_mask;
state->mie->write_with_mask(mask, val << shiftamt);
}
reg_t generic_int_accessor_t::deleg_mask() const {
const reg_t hideleg_mask = mask_hideleg ? state->hideleg->read() : (reg_t)~0;
const reg_t mideleg_mask = mask_mideleg ? state->mideleg->read() : (reg_t)~0;
return hideleg_mask & mideleg_mask;
}
// implement class mip_proxy_csr_t
mip_proxy_csr_t::mip_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr):
csr_t(proc, addr),
accr(accr) {
}
reg_t mip_proxy_csr_t::read() const noexcept {
return accr->ip_read();
}
bool mip_proxy_csr_t::unlogged_write(const reg_t val) noexcept {
accr->ip_write(val);
return false; // accr has already logged
}
// implement class mie_proxy_csr_t
mie_proxy_csr_t::mie_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr):
csr_t(proc, addr),
accr(accr) {
}
reg_t mie_proxy_csr_t::read() const noexcept {
return accr->ie_read();
}
bool mie_proxy_csr_t::unlogged_write(const reg_t val) noexcept {
accr->ie_write(val);
return false; // accr has already logged
}
// implement class mideleg_csr_t
mideleg_csr_t::mideleg_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
reg_t mideleg_csr_t::read() const noexcept {
reg_t val = basic_csr_t::read();
if (proc->extension_enabled('H')) return val | MIDELEG_FORCED_MASK;
// No need to clear MIDELEG_FORCED_MASK because those bits can never
// get set in val.
return val;
}
void mideleg_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled('S'))
throw trap_illegal_instruction(insn.bits());
}
bool mideleg_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | MIP_STIP | MIP_SEIP : 0;
const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0;
const reg_t coprocessor_ints = (reg_t)proc->any_custom_extensions() << IRQ_COP;
const reg_t delegable_ints = supervisor_ints | coprocessor_ints | lscof_int;
return basic_csr_t::unlogged_write(val & delegable_ints);
}
// implement class medeleg_csr_t
medeleg_csr_t::medeleg_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0),
hypervisor_exceptions(0
| (1 << CAUSE_VIRTUAL_SUPERVISOR_ECALL)
| (1 << CAUSE_FETCH_GUEST_PAGE_FAULT)
| (1 << CAUSE_LOAD_GUEST_PAGE_FAULT)
| (1 << CAUSE_VIRTUAL_INSTRUCTION)
| (1 << CAUSE_STORE_GUEST_PAGE_FAULT)
) {
}
void medeleg_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled('S'))
throw trap_illegal_instruction(insn.bits());
}
bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t mask = 0
| (1 << CAUSE_MISALIGNED_FETCH)
| (1 << CAUSE_FETCH_ACCESS)
| (1 << CAUSE_ILLEGAL_INSTRUCTION)
| (1 << CAUSE_BREAKPOINT)
| (1 << CAUSE_MISALIGNED_LOAD)
| (1 << CAUSE_LOAD_ACCESS)
| (1 << CAUSE_MISALIGNED_STORE)
| (1 << CAUSE_STORE_ACCESS)
| (1 << CAUSE_USER_ECALL)
| (1 << CAUSE_SUPERVISOR_ECALL)
| (1 << CAUSE_FETCH_PAGE_FAULT)
| (1 << CAUSE_LOAD_PAGE_FAULT)
| (1 << CAUSE_STORE_PAGE_FAULT)
| (proc->extension_enabled('H') ? hypervisor_exceptions : 0)
| (1 << CAUSE_SOFTWARE_CHECK_FAULT)
| (1 << CAUSE_HARDWARE_ERROR_FAULT)
;
return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask));
}
// implement class masked_csr_t
masked_csr_t::masked_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init):
basic_csr_t(proc, addr, init),
mask(mask) {
}
bool masked_csr_t::unlogged_write(const reg_t val) noexcept {
return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask));
}
envcfg_csr_t::envcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask,
const reg_t init):
masked_csr_t(proc, addr, mask, init) {
// In unlogged_write() we WARLize this field for all three of [msh]envcfg
assert(MENVCFG_CBIE == SENVCFG_CBIE && MENVCFG_CBIE == HENVCFG_CBIE);
}
bool envcfg_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t cbie_reserved = 2; // Reserved value of xenvcfg.CBIE
reg_t adjusted_val = get_field(val, MENVCFG_CBIE) != cbie_reserved ? val : set_field(val, MENVCFG_CBIE, 0);
const reg_t pmm_reserved = 1; // Reserved value of xseccfg.PMM
const reg_t pmm = get_field(adjusted_val, MENVCFG_PMM);
adjusted_val = set_field(adjusted_val, MENVCFG_PMM, pmm != pmm_reserved ? pmm : 0);
if (get_field(adjusted_val, MENVCFG_PMM) != get_field(read(), MENVCFG_PMM))
proc->get_mmu()->flush_tlb();
return masked_csr_t::unlogged_write(adjusted_val);
}
// implement class henvcfg_csr_t
henvcfg_csr_t::henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg):
envcfg_csr_t(proc, addr, mask, init),
menvcfg(menvcfg) {
}
// implement class base_atp_csr_t and family
base_atp_csr_t::base_atp_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
bool base_atp_csr_t::unlogged_write(const reg_t val) noexcept {