Merge pull request #37 from riscv-rust/ehv1

Update `embedded-hal` dependencies

Author: almindor

.cargo/config.toml

@@ -1,5 +1,9 @@
 [target.'cfg(all(target_arch = "riscv32", target_os = "none"))']
+runner = "qemu-system-riscv32 -machine sifive_e,revb=true -nographic -semihosting-config enable=on,target=native -kernel" # Uncomment for QEMU
+# runner = "riscv64-unknown-elf-gdb -q -x hifive1-examples/gdb_init" # Uncomment for hardware (no semihosting)
+# runner = "riscv64-unknown-elf-gdb -q -x hifive1-examples/gdb_init_sh" # Uncomment for hardware (semihosting)
 rustflags = [
+    # "-C", "link-arg=-Thifive1-link.x",
     "--cfg", "portable_atomic_target_feature=\"zaamo\"",
 ]
 

.github/workflows/clippy.yaml

@@ -31,7 +31,7 @@ jobs:
     - name: Run clippy (direct mode)
       run: cargo clippy --features board-${{ matrix.board }} -- $CLIPPY_PARAMS
     - name: Run clippy (vectored mode)
-      run: cargo clippy --features virq,board-${{ matrix.board }} -- $CLIPPY_PARAMS
+      run: cargo clippy --features v-trap,board-${{ matrix.board }} -- $CLIPPY_PARAMS
 
    # Job to check that all the lint checks succeeded
   clippy-check:

.github/workflows/e310x-hal.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.72.0
-        toolchain: [ stable, nightly, 1.72.0 ]
+        # All generated code should be running on stable now, MRSV is 1.76.0
+        toolchain: [ stable, nightly, 1.76.0 ]
         include:
           # Nightly is only for reference and allowed to fail
           - toolchain: nightly

.github/workflows/e310x.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.72.0
-        toolchain: [ stable, nightly, 1.72.0 ]
+        # All generated code should be running on stable now, MRSV is 1.76.0
+        toolchain: [ stable, nightly, 1.76.0 ]
         include:
           # Nightly is only for reference and allowed to fail
           - toolchain: nightly

.github/workflows/hifive1.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.72.0
-        toolchain: [nightly, stable, 1.72.0]
+        # All generated code should be running on stable now, MRSV is 1.76.0
+        toolchain: [nightly, stable, 1.76.0]
         board: [hifive1, hifive1-revb, redv, lofive, lofive-r1]
         include:
           # Nightly is only for reference and allowed to fail
@@ -29,7 +29,7 @@ jobs:
       - name: Build (direct)
         run: cargo build --package hifive1 --features board-${{ matrix.board }}
       - name: Build (vectored)
-        run: cargo build --package hifive1 --features board-${{ matrix.board }},virq
+        run: cargo build --package hifive1 --features board-${{ matrix.board }},v-trap
 
   # On MacOS and Ubuntu, we at least make sure that the crate builds and links.
   # On Windows, linking fails when the rt feature is enabled.
@@ -48,5 +48,5 @@ jobs:
       - name: Build (direct)
         run: cargo test --package hifive1 --features board-${{ matrix.board }}
       - name: Build (vectored)
-        run: cargo test --package hifive1 --features board-${{ matrix.board }},virq
+        run: cargo test --package hifive1 --features board-${{ matrix.board }},v-trap
 

e310x-hal/CHANGELOG.md

@@ -8,11 +8,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [Unreleased]
 
 ### Changed
+- Fix `StatefulOutputPin::is_set_high`. It now reads from `output_val`
+- UART traits are implemented now from `embedded-hal-nb` 1.0.0
+- Update `embedded-hal` to 1.0.0
+- Update `riscv` to 0.12.1
+- Remove `virq` feature. Now interrupts are handled by `e310x`
 - Apply clippy changes
 - Use `portable-atomic` with `zaamo` feature to use native `amo*` operations.
 - Official target is now `riscv32imc-unknown-none-elf`, as it does not fully support the A extension.
 - Update `e310x` dependency and adapt code
-- Bump MSRV to 1.72.0 to ensure a correct behavior of portable-atomic
+- Bump MSRV to 1.76.0
 
 ## [v0.10.0] - 2023-03-28
 

e310x-hal/Cargo.toml

@@ -1,25 +1,27 @@
 [package]
 name = "e310x-hal"
-version = "0.11.0"
+version = "0.12.0"
 authors = ["David Craven <[email protected]>"]
 repository = "https://github.com/riscv-rust/e310x"
 categories = ["embedded", "hardware-support", "no-std"]
 description = "HAL for the E310x family of microcontrollers."
 keywords = ["riscv", "e310", "hal"]
 license = "ISC"
 edition = "2021"
-rust-version = "1.72"
+rust-version = "1.76"
 
 [dependencies]
-embedded-hal = { version = "0.2.6", features = ["unproven"] }
+embedded-hal = "1.0.0"
+embedded-hal-nb = "1.0.0"
+embedded-io = "0.6.1"
+e310x = { path = "../e310x", version = "0.12.0", features = ["rt", "critical-section"] }
 nb = "1.0.0"
-riscv = { version = "0.10.1", features = ["critical-section-single-hart"] }
-e310x = { path = "../e310x", version = "0.11.0", features = ["rt", "critical-section"] }
 portable-atomic = { version = "1.9", default-features = false}
+riscv = { version = "0.12.1", features = ["critical-section-single-hart"] }
 
 [features]
 g002 = ["e310x/g002"]
-virq = []
+v-trap = ["e310x/v-trap"]
 
 [package.metadata.docs.rs]
-features = ["g002", "virq"]
+features = ["g002"]

e310x-hal/src/clock.rs

@@ -1,7 +1,6 @@
 //! Clock configuration
-use crate::core::clint::MTIME;
 use crate::time::Hertz;
-use e310x::{Aonclk as AONCLK, Prci as PRCI};
+use e310x::{Aonclk as AONCLK, Prci as PRCI, CLINT};
 use riscv::interrupt;
 use riscv::register::mcycle;
 
@@ -229,7 +228,7 @@ impl CoreClk {
         };
 
         // Calculate the desired vco frequency
-        let target_vco_freq = pllout_freq * q;
+        let target_vco_freq: u32 = pllout_freq * q;
         assert!((VCO_MIN..=VCO_MAX).contains(&target_vco_freq));
 
         // Calculate PLL F ratio
@@ -291,9 +290,9 @@ impl CoreClk {
         // Need to wait 100 us
         // RTC is running at 32kHz.
         // So wait 4 ticks of RTC.
-        let mtime = MTIME;
-        let time = mtime.mtime() + 4;
-        while mtime.mtime() < time {}
+        let mtime = CLINT::mtimer().mtime;
+        let time = mtime.read() + 4;
+        while mtime.read() < time {}
         // Now it is safe to check for PLL Lock
         while !prci.pllcfg().read().lock().bit_is_set() {}
 
@@ -385,19 +384,19 @@ impl Clocks {
 
     /// Measure the coreclk frequency by counting the number of aonclk ticks.
     fn _measure_coreclk(&self, min_ticks: u64) -> Hertz {
-        let mtime = MTIME;
+        let mtime = CLINT::mtimer().mtime;
         interrupt::free(|| {
             // Don't start measuring until we see an mtime tick
-            while mtime.mtime() == mtime.mtime() {}
+            while mtime.read() == mtime.read() {}
 
             let start_cycle = mcycle::read64();
-            let start_time = mtime.mtime();
+            let start_time = mtime.read();
 
             // Wait for min_ticks to pass
-            while start_time + min_ticks > mtime.mtime() {}
+            while start_time + min_ticks > mtime.read() {}
 
             let end_cycle = mcycle::read64();
-            let end_time = mtime.mtime();
+            let end_time = mtime.read();
 
             let delta_cycle: u64 = end_cycle - start_cycle;
             let delta_time: u64 = end_time - start_time;

e310x-hal/src/core/clint.rs

@@ -1,26 +1,18 @@
 //! E31 core peripherals
 
-pub mod clint;
 pub mod counters;
-pub mod plic;
+
+pub use e310x::{CLINT, PLIC};
 
 /// Core peripherals
 pub struct CorePeripherals {
-    /// Core-Local Interruptor
-    pub clint: clint::Clint,
-
-    /// Platform-Level Interrupt Controller
-    pub plic: plic::Plic,
-
     /// Performance counters
     pub counters: counters::PerformanceCounters,
 }
 
 impl CorePeripherals {
-    pub(crate) fn new(clint: e310x::Clint, plic: e310x::Plic) -> Self {
+    pub(crate) fn new() -> Self {
         Self {
-            clint: clint.into(),
-            plic: plic.into(),
             counters: counters::PerformanceCounters::new(),
         }
     }
@@ -31,7 +23,6 @@ impl CorePeripherals {
     ///
     /// Using this function may break the guarantees of the singleton pattern.
     pub unsafe fn steal() -> Self {
-        let p = e310x::Peripherals::steal();
-        Self::new(p.clint, p.plic)
+        Self::new()
     }
 }