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drm/i915: Add 'render basic' Gen8+ OA unit configs
Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic render metrics on Broadwell, Cherryview and Skylake. These are autogenerated from an internal XML description of metric sets. Signed-off-by: Robert Bragg <[email protected]>
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‎drivers/gpu/drm/i915/Makefile

+4-1
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,10 @@ i915-y += i915_vgpu.o
9595

9696
# perf code
9797
i915-y += i915_perf.o \
98-
i915_oa_hsw.o
98+
i915_oa_hsw.o \
99+
i915_oa_bdw.o \
100+
i915_oa_chv.o \
101+
i915_oa_skl.o
99102

100103
# legacy horrors
101104
i915-y += i915_dma.o

‎drivers/gpu/drm/i915/i915_drv.h

+2
Original file line numberDiff line numberDiff line change
@@ -2062,6 +2062,8 @@ struct drm_i915_private {
20622062
int mux_regs_len;
20632063
const struct i915_oa_reg *b_counter_regs;
20642064
int b_counter_regs_len;
2065+
const struct i915_oa_reg *flex_regs;
2066+
int flex_regs_len;
20652067

20662068
struct {
20672069
struct drm_i915_gem_object *obj;

‎drivers/gpu/drm/i915/i915_oa_bdw.c

+355
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,355 @@
1+
/*
2+
* Autogenerated file, DO NOT EDIT manually!
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*
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* Copyright (c) 2015 Intel Corporation
5+
*
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* Permission is hereby granted, free of charge, to any person obtaining a
7+
* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10+
* and/or sell copies of the Software, and to permit persons to whom the
11+
* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
15+
* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
24+
*
25+
*/
26+
27+
#include <linux/sysfs.h>
28+
29+
#include "i915_drv.h"
30+
31+
enum metric_set_id {
32+
METRIC_SET_ID_RENDER_BASIC = 1,
33+
};
34+
35+
int i915_oa_n_builtin_metric_sets_bdw = 1;
36+
37+
static const struct i915_oa_reg b_counter_config_render_basic[] = {
38+
{ 0x2710, 0x00000000 },
39+
{ 0x2714, 0x00800000 },
40+
{ 0x2720, 0x00000000 },
41+
{ 0x2724, 0x00800000 },
42+
};
43+
44+
static const struct i915_oa_reg flex_eu_config_render_basic[] = {
45+
{ 0xE458, 0x00005004 },
46+
{ 0xE558, 0x00010003 },
47+
{ 0xE658, 0x00012011 },
48+
{ 0xE758, 0x00015014 },
49+
{ 0xE45c, 0x00051050 },
50+
{ 0xE55c, 0x00053052 },
51+
{ 0xE65c, 0x00055054 },
52+
};
53+
54+
static const struct i915_oa_reg mux_config_render_basic_1_0_slices_0x01[] = {
55+
{ 0x9888, 0x143F000F },
56+
{ 0x9888, 0x14110014 },
57+
{ 0x9888, 0x14310014 },
58+
{ 0x9888, 0x14BF000F },
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{ 0x9888, 0x13837BE0 },
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{ 0x9888, 0x3B800060 },
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{ 0x9888, 0x3D800005 },
62+
{ 0x9888, 0x005C4000 },
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{ 0x9888, 0x065C8000 },
64+
{ 0x9888, 0x085CC000 },
65+
{ 0x9888, 0x003D8000 },
66+
{ 0x9888, 0x183D0800 },
67+
{ 0x9888, 0x0A3F0023 },
68+
{ 0x9888, 0x103F0000 },
69+
{ 0x9888, 0x00584000 },
70+
{ 0x9888, 0x08584000 },
71+
{ 0x9888, 0x0A5A4000 },
72+
{ 0x9888, 0x005B4000 },
73+
{ 0x9888, 0x0E5B8000 },
74+
{ 0x9888, 0x185B2400 },
75+
{ 0x9888, 0x0A1D4000 },
76+
{ 0x9888, 0x0C1F0800 },
77+
{ 0x9888, 0x0E1FAA00 },
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{ 0x9888, 0x00384000 },
79+
{ 0x9888, 0x0E384000 },
80+
{ 0x9888, 0x16384000 },
81+
{ 0x9888, 0x18380001 },
82+
{ 0x9888, 0x00392000 },
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{ 0x9888, 0x06398000 },
84+
{ 0x9888, 0x0839A000 },
85+
{ 0x9888, 0x0A391000 },
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{ 0x9888, 0x00104000 },
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{ 0x9888, 0x08104000 },
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{ 0x9888, 0x00110030 },
89+
{ 0x9888, 0x08110031 },
90+
{ 0x9888, 0x10110000 },
91+
{ 0x9888, 0x00134000 },
92+
{ 0x9888, 0x16130020 },
93+
{ 0x9888, 0x06308000 },
94+
{ 0x9888, 0x08308000 },
95+
{ 0x9888, 0x06311800 },
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{ 0x9888, 0x08311880 },
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{ 0x9888, 0x10310000 },
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{ 0x9888, 0x0E334000 },
99+
{ 0x9888, 0x16330080 },
100+
{ 0x9888, 0x0ABF1180 },
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{ 0x9888, 0x10BF0000 },
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{ 0x9888, 0x0ADA8000 },
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{ 0x9888, 0x0A9D8000 },
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{ 0x9888, 0x109F0002 },
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{ 0x9888, 0x0AB94000 },
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{ 0x9888, 0x0D888000 },
107+
{ 0x9888, 0x018A8000 },
108+
{ 0x9888, 0x0F8A8000 },
109+
{ 0x9888, 0x198A8000 },
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{ 0x9888, 0x1B8A00A0 },
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{ 0x9888, 0x238B0020 },
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{ 0x9888, 0x258B2550 },
113+
{ 0x9888, 0x198C1000 },
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{ 0x9888, 0x0B8D8000 },
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{ 0x9888, 0x1F85AA80 },
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{ 0x9888, 0x2185AAA0 },
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{ 0x9888, 0x2385002A },
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{ 0x9888, 0x0D831021 },
119+
{ 0x9888, 0x0F83572F },
120+
{ 0x9888, 0x01835680 },
121+
{ 0x9888, 0x038315AC },
122+
{ 0x9888, 0x0583002A },
123+
{ 0x9888, 0x11830000 },
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{ 0x9888, 0x19835400 },
125+
{ 0x9888, 0x1B830001 },
126+
{ 0x9888, 0x07830000 },
127+
{ 0x9888, 0x09830000 },
128+
{ 0x9888, 0x0184C000 },
129+
{ 0x9888, 0x07848000 },
130+
{ 0x9888, 0x0984C000 },
131+
{ 0x9888, 0x0B84C000 },
132+
{ 0x9888, 0x0D84C000 },
133+
{ 0x9888, 0x0F84C000 },
134+
{ 0x9888, 0x0384C000 },
135+
{ 0x9888, 0x05844000 },
136+
{ 0x9888, 0x1B80C137 },
137+
{ 0x9888, 0x1D80C147 },
138+
{ 0x9888, 0x21800000 },
139+
{ 0x9888, 0x1180C000 },
140+
{ 0x9888, 0x17808000 },
141+
{ 0x9888, 0x1980C000 },
142+
{ 0x9888, 0x1F80C000 },
143+
{ 0x9888, 0x1380C000 },
144+
{ 0x9888, 0x15804000 },
145+
{ 0x0D24, 0x00000000 },
146+
{ 0x9888, 0x4D801110 },
147+
{ 0x9888, 0x4F800331 },
148+
{ 0x9888, 0x43800802 },
149+
{ 0x9888, 0x51800000 },
150+
{ 0x9888, 0x45801465 },
151+
{ 0x9888, 0x53801111 },
152+
{ 0x9888, 0x478014A5 },
153+
{ 0x9888, 0x31800000 },
154+
{ 0x9888, 0x3F8014A5 },
155+
{ 0x9888, 0x41800005 },
156+
};
157+
158+
static const struct i915_oa_reg mux_config_render_basic_1_1_slices_0x02[] = {
159+
{ 0x9888, 0x143F000F },
160+
{ 0x9888, 0x14BF000F },
161+
{ 0x9888, 0x14910014 },
162+
{ 0x9888, 0x14B10014 },
163+
{ 0x9888, 0x13837BE0 },
164+
{ 0x9888, 0x3B800060 },
165+
{ 0x9888, 0x3D800005 },
166+
{ 0x9888, 0x0A3F0023 },
167+
{ 0x9888, 0x103F0000 },
168+
{ 0x9888, 0x0A5A4000 },
169+
{ 0x9888, 0x0A1D4000 },
170+
{ 0x9888, 0x0E1F8000 },
171+
{ 0x9888, 0x0A391000 },
172+
{ 0x9888, 0x00DC4000 },
173+
{ 0x9888, 0x06DC8000 },
174+
{ 0x9888, 0x08DCC000 },
175+
{ 0x9888, 0x00BD8000 },
176+
{ 0x9888, 0x18BD0800 },
177+
{ 0x9888, 0x0ABF1180 },
178+
{ 0x9888, 0x10BF0000 },
179+
{ 0x9888, 0x00D84000 },
180+
{ 0x9888, 0x08D84000 },
181+
{ 0x9888, 0x0ADA8000 },
182+
{ 0x9888, 0x00DB4000 },
183+
{ 0x9888, 0x0EDB8000 },
184+
{ 0x9888, 0x18DB2400 },
185+
{ 0x9888, 0x0A9D8000 },
186+
{ 0x9888, 0x0C9F0800 },
187+
{ 0x9888, 0x0E9F2A00 },
188+
{ 0x9888, 0x109F0002 },
189+
{ 0x9888, 0x00B84000 },
190+
{ 0x9888, 0x0EB84000 },
191+
{ 0x9888, 0x16B84000 },
192+
{ 0x9888, 0x18B80001 },
193+
{ 0x9888, 0x00B92000 },
194+
{ 0x9888, 0x06B98000 },
195+
{ 0x9888, 0x08B9A000 },
196+
{ 0x9888, 0x0AB94000 },
197+
{ 0x9888, 0x00904000 },
198+
{ 0x9888, 0x08904000 },
199+
{ 0x9888, 0x00910030 },
200+
{ 0x9888, 0x08910031 },
201+
{ 0x9888, 0x10910000 },
202+
{ 0x9888, 0x00934000 },
203+
{ 0x9888, 0x16930020 },
204+
{ 0x9888, 0x06B08000 },
205+
{ 0x9888, 0x08B08000 },
206+
{ 0x9888, 0x06B11800 },
207+
{ 0x9888, 0x08B11880 },
208+
{ 0x9888, 0x10B10000 },
209+
{ 0x9888, 0x0EB34000 },
210+
{ 0x9888, 0x16B30080 },
211+
{ 0x9888, 0x01888000 },
212+
{ 0x9888, 0x0D88B800 },
213+
{ 0x9888, 0x1B8A0080 },
214+
{ 0x9888, 0x238B0040 },
215+
{ 0x9888, 0x258B26A0 },
216+
{ 0x9888, 0x018C4000 },
217+
{ 0x9888, 0x0F8C4000 },
218+
{ 0x9888, 0x178C2000 },
219+
{ 0x9888, 0x198C1100 },
220+
{ 0x9888, 0x018D2000 },
221+
{ 0x9888, 0x078D8000 },
222+
{ 0x9888, 0x098DA000 },
223+
{ 0x9888, 0x0B8D8000 },
224+
{ 0x9888, 0x1F85AA80 },
225+
{ 0x9888, 0x2185AAA0 },
226+
{ 0x9888, 0x2385002A },
227+
{ 0x9888, 0x0D831021 },
228+
{ 0x9888, 0x0F83572F },
229+
{ 0x9888, 0x01835680 },
230+
{ 0x9888, 0x038315AC },
231+
{ 0x9888, 0x0583002A },
232+
{ 0x9888, 0x11830000 },
233+
{ 0x9888, 0x19835400 },
234+
{ 0x9888, 0x1B830001 },
235+
{ 0x9888, 0x07830000 },
236+
{ 0x9888, 0x09830000 },
237+
{ 0x9888, 0x0184C000 },
238+
{ 0x9888, 0x07848000 },
239+
{ 0x9888, 0x0984C000 },
240+
{ 0x9888, 0x0B84C000 },
241+
{ 0x9888, 0x0D84C000 },
242+
{ 0x9888, 0x0F84C000 },
243+
{ 0x9888, 0x0384C000 },
244+
{ 0x9888, 0x05844000 },
245+
{ 0x9888, 0x1B80C137 },
246+
{ 0x9888, 0x1D80C147 },
247+
{ 0x9888, 0x21800000 },
248+
{ 0x9888, 0x1180C000 },
249+
{ 0x9888, 0x17808000 },
250+
{ 0x9888, 0x1980C000 },
251+
{ 0x9888, 0x1F80C000 },
252+
{ 0x9888, 0x1380C000 },
253+
{ 0x9888, 0x15804000 },
254+
{ 0x0D24, 0x00000000 },
255+
{ 0x9888, 0x4D805550 },
256+
{ 0x9888, 0x4F800335 },
257+
{ 0x9888, 0x43800802 },
258+
{ 0x9888, 0x51800400 },
259+
{ 0x9888, 0x458004A1 },
260+
{ 0x9888, 0x53805555 },
261+
{ 0x9888, 0x47800421 },
262+
{ 0x9888, 0x31800000 },
263+
{ 0x9888, 0x3F800421 },
264+
{ 0x9888, 0x41800841 },
265+
};
266+
267+
static int select_render_basic_config(struct drm_i915_private *dev_priv)
268+
{
269+
if (INTEL_INFO(dev_priv)->slice_mask & 0x01) {
270+
dev_priv->perf.oa.mux_regs =
271+
mux_config_render_basic_1_0_slices_0x01;
272+
dev_priv->perf.oa.mux_regs_len =
273+
ARRAY_SIZE(mux_config_render_basic_1_0_slices_0x01);
274+
} else if (INTEL_INFO(dev_priv)->slice_mask & 0x02) {
275+
dev_priv->perf.oa.mux_regs =
276+
mux_config_render_basic_1_1_slices_0x02;
277+
dev_priv->perf.oa.mux_regs_len =
278+
ARRAY_SIZE(mux_config_render_basic_1_1_slices_0x02);
279+
} else {
280+
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set");
281+
return -EINVAL;
282+
}
283+
284+
dev_priv->perf.oa.b_counter_regs =
285+
b_counter_config_render_basic;
286+
dev_priv->perf.oa.b_counter_regs_len =
287+
ARRAY_SIZE(b_counter_config_render_basic);
288+
289+
dev_priv->perf.oa.flex_regs =
290+
flex_eu_config_render_basic;
291+
dev_priv->perf.oa.flex_regs_len =
292+
ARRAY_SIZE(flex_eu_config_render_basic);
293+
294+
return 0;
295+
}
296+
297+
int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv)
298+
{
299+
dev_priv->perf.oa.mux_regs = NULL;
300+
dev_priv->perf.oa.mux_regs_len = 0;
301+
dev_priv->perf.oa.b_counter_regs = NULL;
302+
dev_priv->perf.oa.b_counter_regs_len = 0;
303+
dev_priv->perf.oa.flex_regs = NULL;
304+
dev_priv->perf.oa.flex_regs_len = 0;
305+
306+
switch (dev_priv->perf.oa.metrics_set) {
307+
case METRIC_SET_ID_RENDER_BASIC:
308+
return select_render_basic_config(dev_priv);
309+
default:
310+
return -ENODEV;
311+
}
312+
}
313+
314+
static ssize_t
315+
show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
316+
{
317+
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
318+
}
319+
320+
static struct device_attribute dev_attr_render_basic_id = {
321+
.attr = { .name = "id", .mode = S_IRUGO },
322+
.show = show_render_basic_id,
323+
.store = NULL,
324+
};
325+
326+
static struct attribute *attrs_render_basic[] = {
327+
&dev_attr_render_basic_id.attr,
328+
NULL,
329+
};
330+
331+
static struct attribute_group group_render_basic = {
332+
.name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7",
333+
.attrs = attrs_render_basic,
334+
};
335+
336+
int
337+
i915_perf_init_sysfs_bdw(struct drm_i915_private *dev_priv)
338+
{
339+
int ret;
340+
341+
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
342+
if (ret)
343+
goto error_render_basic;
344+
345+
return 0;
346+
347+
error_render_basic:
348+
return ret;
349+
}
350+
351+
void
352+
i915_perf_deinit_sysfs_bdw(struct drm_i915_private *dev_priv)
353+
{
354+
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
355+
}

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