-
Notifications
You must be signed in to change notification settings - Fork 3
/
Copy pathblock_1.veryl
380 lines (380 loc) · 15.4 KB
/
block_1.veryl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
import rggen::rggen_rtl_pkg::*;
pub module block_1 #(
param ADDRESS_WIDTH: u32 = 7,
param PRE_DECODE: bool = false,
param BASE_ADDRESS: bit<ADDRESS_WIDTH> = '0,
param ERROR_STATUS: bool = false,
param DEFAULT_READ_DATA: bit<32> = '0,
param INSERT_SLICER: bool = false
)(
i_clk: input clock,
i_rst: input reset,
apb_if: modport rggen::rggen_apb_if::slave,
o_register_file_0_register_0_bit_field_0: output logic<8>,
o_register_file_0_register_1_bit_field_0: output logic<8>,
o_register_file_1_register_0_bit_field_0: output logic<2, 8>,
o_register_file_1_register_1_bit_field_0: output logic<2, 8>,
o_register_file_2_register_file_0_register_0_bit_field_0: output logic<2, 2, 3, 2, 4>,
o_register_file_2_register_file_0_register_0_bit_field_1: output logic<2, 2, 3, 2, 4>,
o_register_file_2_register_file_0_register_0_bit_field_2: output logic<2, 2, 3, 2, 4>,
o_register_file_2_register_file_0_register_1_bit_field_0: output logic<2, 2>
){
inst register_if: rggen::rggen_register_if[20]#(ADDRESS_WIDTH: 7, BUS_WIDTH: 32, VALUE_WIDTH: 32);
inst u_adapter: rggen::rggen_apb_adapter #(
ADDRESS_WIDTH: ADDRESS_WIDTH,
LOCAL_ADDRESS_WIDTH: 7,
BUS_WIDTH: 32,
REGISTERS: 20,
PRE_DECODE: PRE_DECODE,
BASE_ADDRESS: BASE_ADDRESS,
BYTE_SIZE: 128,
ERROR_STATUS: ERROR_STATUS,
DEFAULT_READ_DATA: DEFAULT_READ_DATA,
INSERT_SLICER: INSERT_SLICER
)(
i_clk: i_clk,
i_rst: i_rst,
apb_if: apb_if,
register_if: register_if
);
:g_register_file_0 {
:g_register_0 {
inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32);
inst u_register: rggen::rggen_default_register #(
READABLE: true,
WRITABLE: true,
ADDRESS_WIDTH: 7,
OFFSET_ADDRESS: 7'h00,
BUS_WIDTH: 32,
DATA_WIDTH: 32,
VALUE_WIDTH: 32,
VALID_BITS: 32'h000000ff
)(
i_clk: i_clk,
i_rst: i_rst,
register_if: register_if[0],
bit_field_if: bit_field_if
);
:g_bit_field_0 {
const INITIAL_VALUE: bit<8> = 8'h00;
inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8);
always_comb {
bit_field_sub_if.valid = bit_field_if.valid;
bit_field_sub_if.read_mask = bit_field_if.read_mask[0+:8];
bit_field_sub_if.write_mask = bit_field_if.write_mask[0+:8];
bit_field_sub_if.write_data = bit_field_if.write_data[0+:8];
bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data;
bit_field_if.value[0+:8] = bit_field_sub_if.value;
}
inst u_bit_field: rggen::rggen_bit_field #(
WIDTH: 8,
INITIAL_VALUE: INITIAL_VALUE,
SW_WRITE_ONCE: false,
TRIGGER: false
)(
i_clk: i_clk,
i_rst: i_rst,
bit_field_if: bit_field_sub_if,
o_write_trigger: _,
o_read_trigger: _,
o_value: o_register_file_0_register_0_bit_field_0
);
}
}
:g_register_1 {
inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32);
inst u_register: rggen::rggen_default_register #(
READABLE: true,
WRITABLE: true,
ADDRESS_WIDTH: 7,
OFFSET_ADDRESS: 7'h04,
BUS_WIDTH: 32,
DATA_WIDTH: 32,
VALUE_WIDTH: 32,
VALID_BITS: 32'h000000ff
)(
i_clk: i_clk,
i_rst: i_rst,
register_if: register_if[1],
bit_field_if: bit_field_if
);
:g_bit_field_0 {
const INITIAL_VALUE: bit<8> = 8'h00;
inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8);
always_comb {
bit_field_sub_if.valid = bit_field_if.valid;
bit_field_sub_if.read_mask = bit_field_if.read_mask[0+:8];
bit_field_sub_if.write_mask = bit_field_if.write_mask[0+:8];
bit_field_sub_if.write_data = bit_field_if.write_data[0+:8];
bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data;
bit_field_if.value[0+:8] = bit_field_sub_if.value;
}
inst u_bit_field: rggen::rggen_bit_field #(
WIDTH: 8,
INITIAL_VALUE: INITIAL_VALUE,
SW_WRITE_ONCE: false,
TRIGGER: false
)(
i_clk: i_clk,
i_rst: i_rst,
bit_field_if: bit_field_sub_if,
o_write_trigger: _,
o_read_trigger: _,
o_value: o_register_file_0_register_1_bit_field_0
);
}
}
}
:g_register_file_1 {
:g_register_0 {
for i in 0..2 :g {
inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32);
var indirect_match: logic<2>;
assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8);
assign indirect_match[1] = register_if[1].value[0+:8] == 8'h00;
inst u_register: rggen::rggen_indirect_register #(
READABLE: true,
WRITABLE: true,
ADDRESS_WIDTH: 7,
OFFSET_ADDRESS: 7'h10,
BUS_WIDTH: 32,
DATA_WIDTH: 32,
VALUE_WIDTH: 32,
VALID_BITS: 32'h000000ff,
INDIRECT_MATCH_WIDTH: 2
)(
i_clk: i_clk,
i_rst: i_rst,
register_if: register_if[2+i],
i_indirect_match: indirect_match,
bit_field_if: bit_field_if
);
:g_bit_field_0 {
const INITIAL_VALUE: bit<8> = 8'h00;
inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8);
always_comb {
bit_field_sub_if.valid = bit_field_if.valid;
bit_field_sub_if.read_mask = bit_field_if.read_mask[0+:8];
bit_field_sub_if.write_mask = bit_field_if.write_mask[0+:8];
bit_field_sub_if.write_data = bit_field_if.write_data[0+:8];
bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data;
bit_field_if.value[0+:8] = bit_field_sub_if.value;
}
inst u_bit_field: rggen::rggen_bit_field #(
WIDTH: 8,
INITIAL_VALUE: INITIAL_VALUE,
SW_WRITE_ONCE: false,
TRIGGER: false
)(
i_clk: i_clk,
i_rst: i_rst,
bit_field_if: bit_field_sub_if,
o_write_trigger: _,
o_read_trigger: _,
o_value: o_register_file_1_register_0_bit_field_0[i]
);
}
}
}
:g_register_1 {
for i in 0..2 :g {
inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32);
var indirect_match: logic<2>;
assign indirect_match[0] = register_if[0].value[0+:8] == (i as 8);
assign indirect_match[1] = register_if[1].value[0+:8] == 8'h01;
inst u_register: rggen::rggen_indirect_register #(
READABLE: true,
WRITABLE: true,
ADDRESS_WIDTH: 7,
OFFSET_ADDRESS: 7'h10,
BUS_WIDTH: 32,
DATA_WIDTH: 32,
VALUE_WIDTH: 32,
VALID_BITS: 32'h000000ff,
INDIRECT_MATCH_WIDTH: 2
)(
i_clk: i_clk,
i_rst: i_rst,
register_if: register_if[4+i],
i_indirect_match: indirect_match,
bit_field_if: bit_field_if
);
:g_bit_field_0 {
const INITIAL_VALUE: bit<8> = 8'h00;
inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 8);
always_comb {
bit_field_sub_if.valid = bit_field_if.valid;
bit_field_sub_if.read_mask = bit_field_if.read_mask[0+:8];
bit_field_sub_if.write_mask = bit_field_if.write_mask[0+:8];
bit_field_sub_if.write_data = bit_field_if.write_data[0+:8];
bit_field_if.read_data[0+:8] = bit_field_sub_if.read_data;
bit_field_if.value[0+:8] = bit_field_sub_if.value;
}
inst u_bit_field: rggen::rggen_bit_field #(
WIDTH: 8,
INITIAL_VALUE: INITIAL_VALUE,
SW_WRITE_ONCE: false,
TRIGGER: false
)(
i_clk: i_clk,
i_rst: i_rst,
bit_field_if: bit_field_sub_if,
o_write_trigger: _,
o_read_trigger: _,
o_value: o_register_file_1_register_1_bit_field_0[i]
);
}
}
}
}
:g_register_file_2 {
for i in 0..2 :g {
:g_register_file_0 {
:g_register_0 {
for j in 0..2 :g {
for k in 0..3 :g {
inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32);
inst u_register: rggen::rggen_default_register #(
READABLE: true,
WRITABLE: true,
ADDRESS_WIDTH: 7,
OFFSET_ADDRESS: 7'h20+(32*i as 7)+(4*(3*j+k) as 7),
BUS_WIDTH: 32,
DATA_WIDTH: 32,
VALUE_WIDTH: 32,
VALID_BITS: 32'h00ffffff
)(
i_clk: i_clk,
i_rst: i_rst,
register_if: register_if[6+7*i+3*j+k],
bit_field_if: bit_field_if
);
:g_bit_field_0 {
for l in 0..2 :g {
const INITIAL_VALUE: bit<4> = 4'h0;
inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4);
always_comb {
bit_field_sub_if.valid = bit_field_if.valid;
bit_field_sub_if.read_mask = bit_field_if.read_mask[0+4*l+:4];
bit_field_sub_if.write_mask = bit_field_if.write_mask[0+4*l+:4];
bit_field_sub_if.write_data = bit_field_if.write_data[0+4*l+:4];
bit_field_if.read_data[0+4*l+:4] = bit_field_sub_if.read_data;
bit_field_if.value[0+4*l+:4] = bit_field_sub_if.value;
}
inst u_bit_field: rggen::rggen_bit_field #(
WIDTH: 4,
INITIAL_VALUE: INITIAL_VALUE,
SW_WRITE_ONCE: false,
TRIGGER: false
)(
i_clk: i_clk,
i_rst: i_rst,
bit_field_if: bit_field_sub_if,
o_write_trigger: _,
o_read_trigger: _,
o_value: o_register_file_2_register_file_0_register_0_bit_field_0[i][j][k][l]
);
}
}
:g_bit_field_1 {
for l in 0..2 :g {
const INITIAL_VALUE: bit<4> = 4'h0;
inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4);
always_comb {
bit_field_sub_if.valid = bit_field_if.valid;
bit_field_sub_if.read_mask = bit_field_if.read_mask[8+4*l+:4];
bit_field_sub_if.write_mask = bit_field_if.write_mask[8+4*l+:4];
bit_field_sub_if.write_data = bit_field_if.write_data[8+4*l+:4];
bit_field_if.read_data[8+4*l+:4] = bit_field_sub_if.read_data;
bit_field_if.value[8+4*l+:4] = bit_field_sub_if.value;
}
inst u_bit_field: rggen::rggen_bit_field #(
WIDTH: 4,
INITIAL_VALUE: INITIAL_VALUE,
SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_HIGH
)(
i_clk: i_clk,
i_rst: i_rst,
bit_field_if: bit_field_sub_if,
i_sw_write_enable: register_if[0].value[0+:1],
o_value: o_register_file_2_register_file_0_register_0_bit_field_1[i][j][k][l]
);
}
}
:g_bit_field_2 {
for l in 0..2 :g {
const INITIAL_VALUE: bit<4> = 4'h0;
inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 4);
always_comb {
bit_field_sub_if.valid = bit_field_if.valid;
bit_field_sub_if.read_mask = bit_field_if.read_mask[16+4*l+:4];
bit_field_sub_if.write_mask = bit_field_if.write_mask[16+4*l+:4];
bit_field_sub_if.write_data = bit_field_if.write_data[16+4*l+:4];
bit_field_if.read_data[16+4*l+:4] = bit_field_sub_if.read_data;
bit_field_if.value[16+4*l+:4] = bit_field_sub_if.value;
}
inst u_bit_field: rggen::rggen_bit_field #(
WIDTH: 4,
INITIAL_VALUE: INITIAL_VALUE,
SW_WRITE_ENABLE_POLARITY: rggen_polarity::ACTIVE_LOW
)(
i_clk: i_clk,
i_rst: i_rst,
bit_field_if: bit_field_sub_if,
i_sw_write_enable: register_if[6+7*i+6].value[0+1*l+:1],
o_value: o_register_file_2_register_file_0_register_0_bit_field_2[i][j][k][l]
);
}
}
}
}
}
:g_register_1 {
inst bit_field_if: rggen::rggen_bit_field_if#(WIDTH: 32);
inst u_register: rggen::rggen_default_register #(
READABLE: true,
WRITABLE: true,
ADDRESS_WIDTH: 7,
OFFSET_ADDRESS: 7'h20+(32*i as 7)+7'h18,
BUS_WIDTH: 32,
DATA_WIDTH: 32,
VALUE_WIDTH: 32,
VALID_BITS: 32'h00000003
)(
i_clk: i_clk,
i_rst: i_rst,
register_if: register_if[6+7*i+6],
bit_field_if: bit_field_if
);
:g_bit_field_0 {
for j in 0..2 :g {
const INITIAL_VALUE: bit = 1'h0;
inst bit_field_sub_if: rggen::rggen_bit_field_if#(WIDTH: 1);
always_comb {
bit_field_sub_if.valid = bit_field_if.valid;
bit_field_sub_if.read_mask = bit_field_if.read_mask[0+1*j+:1];
bit_field_sub_if.write_mask = bit_field_if.write_mask[0+1*j+:1];
bit_field_sub_if.write_data = bit_field_if.write_data[0+1*j+:1];
bit_field_if.read_data[0+1*j+:1] = bit_field_sub_if.read_data;
bit_field_if.value[0+1*j+:1] = bit_field_sub_if.value;
}
inst u_bit_field: rggen::rggen_bit_field #(
WIDTH: 1,
INITIAL_VALUE: INITIAL_VALUE,
SW_WRITE_ONCE: false,
TRIGGER: false
)(
i_clk: i_clk,
i_rst: i_rst,
bit_field_if: bit_field_sub_if,
o_write_trigger: _,
o_read_trigger: _,
o_value: o_register_file_2_register_file_0_register_1_bit_field_0[i][j]
);
}
}
}
}
}
}
}