Add PIC18F45K50 config and init

Author: qwertymodo

apps/common/hardware.c

@@ -49,6 +49,49 @@ _CONFIG3(WPFP_WPFP255 & SOSCSEL_SOSC & WUTSEL_LEG & ALTPMP_ALPMPDIS & WPDIS_WPDI
 #pragma config IOL1WAY = OFF
 #pragma config WPDIS = OFF /* This pragma seems backwards */
 
+#elif _18F24K50 || _18F25K50 || _18F45K50
+#pragma config PLLSEL   = PLL3X     // PLL Selection (3x clock multiplier)
+#pragma config CFGPLLEN = OFF       // PLL Enable Configuration bit (PLL Disabled (firmware controlled))
+#pragma config CPUDIV   = NOCLKDIV  // CPU System Clock Postscaler (CPU uses system clock (no divide))
+#pragma config LS48MHZ  = SYS48X8   // Low Speed USB mode with 48 MHz system clock (System clock at 48 MHz, USB clock divider is set to 8)
+#pragma config FOSC     = INTOSCIO  // Oscillator Selection (Internal oscillator)
+#pragma config PCLKEN   = OFF       // Primary Oscillator Shutdown (Primary oscillator shutdown firmware controlled)
+#pragma config FCMEN    = OFF       // Fail-Safe Clock Monitor (Fail-Safe Clock Monitor disabled)
+#pragma config IESO     = OFF       // Internal/External Oscillator Switchover (Oscillator Switchover mode disabled)
+#pragma config nPWRTEN  = OFF       // Power-up Timer Enable (Power up timer disabled)
+#pragma config BOREN    = SBORDIS   // Brown-out Reset Enable (BOR enabled in hardware (SBOREN is ignored))
+#pragma config BORV     = 190       // Brown-out Reset Voltage (BOR set to 1.9V nominal)
+#pragma config nLPBOR   = ON        // Low-Power Brown-out Reset (Low-Power Brown-out Reset enabled)
+#pragma config WDTEN    = SWON      // Watchdog Timer Enable bits (WDT controlled by firmware (SWDTEN enabled))
+#pragma config WDTPS    = 32768     // Watchdog Timer Postscaler (1:32768)
+#pragma config CCP2MX   = RC1       // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
+#pragma config PBADEN   = OFF       // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
+#pragma config T3CMX    = RC0       // Timer3 Clock Input MUX bit (T3CKI function is on RC0)
+#pragma config SDOMX    = RC7       // SDO Output MUX bit (SDO function is on RC7)
+#pragma config MCLRE    = ON        // Master Clear Reset Pin Enable (MCLR pin enabled; RE3 input disabled)
+#pragma config STVREN   = ON        // Stack Full/Underflow Reset (Stack full/underflow will cause Reset)
+#pragma config LVP      = OFF       // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
+#pragma config ICPRT    = OFF       // Dedicated In-Circuit Debug/Programming Port Enable (ICPORT disabled)
+#pragma config XINST    = OFF       // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled)
+#pragma config CP0      = OFF       // Block 0 Code Protect (Block 0 is not code-protected)
+#pragma config CP1      = OFF       // Block 1 Code Protect (Block 1 is not code-protected)
+#pragma config CP2      = OFF       // Block 2 Code Protect (Block 2 is not code-protected)
+#pragma config CP3      = OFF       // Block 3 Code Protect (Block 3 is not code-protected)
+#pragma config CPB      = OFF       // Boot Block Code Protect (Boot block is not code-protected)
+#pragma config CPD      = OFF       // Data EEPROM Code Protect (Data EEPROM is not code-protected)
+#pragma config WRT0     = OFF       // Block 0 Write Protect (Block 0 (0800-1FFFh) is not write-protected)
+#pragma config WRT1     = OFF       // Block 1 Write Protect (Block 1 (2000-3FFFh) is not write-protected)
+#pragma config WRT2     = OFF       // Block 2 Write Protect (Block 2 (04000-5FFFh) is not write-protected)
+#pragma config WRT3     = OFF       // Block 3 Write Protect (Block 3 (06000-7FFFh) is not write-protected)
+#pragma config WRTC     = OFF       // Configuration Registers Write Protect (Configuration registers (300000-3000FFh) are not write-protected)
+#pragma config WRTB     = OFF       // Boot Block Write Protect (Boot block (0000-7FFh) is not write-protected)
+#pragma config WRTD     = OFF       // Data EEPROM Write Protect (Data EEPROM is not write-protected)
+#pragma config EBTR0    = OFF       // Block 0 Table Read Protect (Block 0 is not protected from table reads executed in other blocks)
+#pragma config EBTR1    = OFF       // Block 1 Table Read Protect (Block 1 is not protected from table reads executed in other blocks)
+#pragma config EBTR2    = OFF       // Block 2 Table Read Protect (Block 2 is not protected from table reads executed in other blocks)
+#pragma config EBTR3    = OFF       // Block 3 Table Read Protect (Block 3 is not protected from table reads executed in other blocks)
+#pragma config EBTRB    = OFF       // Boot Block Table Read Protect (Boot block is not protected from table reads executed in other blocks)
+
 #elif _16F1459 || _16F1454
 #pragma config FOSC = INTOSC
 #pragma config WDTE = OFF
@@ -208,8 +251,15 @@ void hardware_init(void)
 #elif _18F46J50
 	unsigned int pll_startup = 600;
 	OSCTUNEbits.PLLEN = 1;
-	while (pll_startup--)
-		;
+	while (pll_startup--);
+        
+#elif _18F24K50 || _18F25K50 || _18F45K50
+    OSCTUNE = 0x80; //3X PLL ratio mode selected
+    OSCCON = 0x70;  //Switch to 16MHz HFINTOSC
+    OSCCON2 = 0x10; //Enable PLL, SOSC, PRI OSC drivers turned off
+    while(OSCCON2bits.PLLRDY != 1);   //Wait for PLL lock
+    ACTCON = 0x90;  //Enable active clock tuning for USB operation
+    
 #elif _16F1459 || _16F1454
 	OSCCONbits.IRCF = 0b1111; /* 0b1111 = 16MHz HFINTOSC postscalar */
 

usb/src/usb_hal.h

@@ -186,14 +186,14 @@ struct buffer_descriptor {
 #define SFR_USB_STALL_IF         UIRbits.STALLIF
 #define SFR_USB_TOKEN_IF         UIRbits.TRNIF
 #define SFR_USB_SOF_IF           UIRbits.SOFIF
-#define SFR_USB_IF               PIR2bits.USBIF
+#define SFR_USB_IF               USBIF
 
 #define SFR_USB_INTERRUPT_EN     UIE
 #define SFR_TRANSFER_IE          UIEbits.TRNIE
 #define SFR_STALL_IE             UIEbits.STALLIE
 #define SFR_RESET_IE             UIEbits.URSTIE
 #define SFR_SOF_IE               UIEbits.SOFIE
-#define SFR_USB_IE               PIE2bits.USBIE
+#define SFR_USB_IE               USBIE
 
 #define SFR_USB_EXTENDED_INTERRUPT_EN UEIE
 
@@ -285,7 +285,7 @@ struct buffer_descriptor {
 #define BDN_LENGTH(REG) (REG.BDnCNT)
 #endif
 
-#ifdef _18F46J50
+#if _18F46J50 || _18F45K50
 #define BD_ADDR 0x400
 //#undef BUFFER_ADDR
 #else