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midend: Add RT midend (#24)
* Add first version of the real-time (RT) midend #24 --------- Co-authored-by: Alessandro Ottaviano <[email protected]>
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Diff for: ‎Bender.yml

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@@ -53,6 +53,7 @@ sources:
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files:
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# Level 0
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- src/midend/idma_nd_midend.sv
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- src/midend/idma_rt_midend.sv
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# Frontends (without inst64)
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- target: rtl
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# Level 0
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- src/frontend/desc64/idma_desc64_synth_pkg.sv
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- src/midend/idma_nd_midend_synth.sv
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- src/midend/idma_rt_midend_synth_pkg.sv
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# Level 1
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- src/frontend/desc64/idma_desc64_synth.sv
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- src/midend/idma_rt_midend_synth.sv
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# Testbenches
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- target: test
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- test/future/TLToAXI4.v
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- test/future/tb_idma_improved_fifo.sv
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- test/midend/tb_idma_nd_midend.sv
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- test/midend/tb_idma_rt_midend.sv
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# Level 1
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- test/future/idma_obi2axi_bridge.sv
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- test/future/idma_tilelink2axi_bridge.sv

Diff for: ‎idma.mk

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@@ -241,6 +241,11 @@ IDMA_RTL_DOC_ALL += $(IDMA_DOC_FIG_DIR)/graph/idma_desc64_synth.png
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IDMA_RTL_DOC_ALL += $(IDMA_HTML_DIR)/idma_desc64_synth/index.html
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IDMA_PICKLE_ALL += $(IDMA_PICKLE_DIR)/idma_desc64_synth.sv
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# RT midend
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IDMA_RTL_DOC_ALL += $(IDMA_DOC_FIG_DIR)/graph/idma_rt_midend_synth.png
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IDMA_RTL_DOC_ALL += $(IDMA_HTML_DIR)/idma_rt_midend_synth/index.html
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IDMA_PICKLE_ALL += $(IDMA_PICKLE_DIR)/idma_rt_midend_synth.sv
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# --------------
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# QuestaSim

Diff for: ‎jobs/jobs.json

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@@ -151,5 +151,15 @@
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"proc_id" : "rw_axi",
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"testbench" : "tb_idma_desc64_bench",
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"synth_top" : "idma_desc64_synth"
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},
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"rt_midend": {
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"jobs" : {
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"simple" : "jobs.json"
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},
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"params" : {
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},
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"proc_id" : "rw_axi",
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"testbench" : "tb_idma_rt_midend",
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"synth_top" : "idma_rt_midend_synth"
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}
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}

Diff for: ‎src/midend/idma_rt_midend.sv

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@@ -0,0 +1,229 @@
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// Copyright 2023 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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// Authors:
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// - Thomas Benz <[email protected]>
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/// RT midend for the iDMA
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module idma_rt_midend #(
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/// Number of parallel events
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parameter int unsigned NumEvents = 32'd1,
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/// The width of the event counters (count multiple of clock period)
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parameter int unsigned EventCntWidth = 32'd32,
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/// Number of outstanding DMA events
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parameter int unsigned NumOutstanding = 32'd2,
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/// Address type
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parameter type addr_t = logic,
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/// ND iDMA request type
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parameter type idma_nd_req_t = logic,
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/// iDMA response type
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parameter type idma_rsp_t = logic,
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/// *DO NOT OVERWRITE*: Derived event counter type.
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parameter type event_cnt_t = logic [EventCntWidth-1:0]
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)(
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/// Clock
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input logic clk_i,
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/// Asynchronous reset, active low
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input logic rst_ni,
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/// The threshold an event is triggered
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input event_cnt_t [NumEvents-1:0] event_counts_i,
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/// The source address of the event
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input addr_t [NumEvents-1:0] src_addr_i,
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/// The destination address of the event
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input addr_t [NumEvents-1:0] dst_addr_i,
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/// The length of the event
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input addr_t [NumEvents-1:0] length_i,
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/// The source stride of the event
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input addr_t [NumEvents-1:0] src_1d_stride_i,
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/// The destination stride of the event
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input addr_t [NumEvents-1:0] dst_1d_stride_i,
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/// The number of repetitions of the event
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input addr_t [NumEvents-1:0] num_1d_reps_i,
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/// The source stride of the event
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input addr_t [NumEvents-1:0] src_2d_stride_i,
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/// The destination stride of the event
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input addr_t [NumEvents-1:0] dst_2d_stride_i,
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/// The number of repetitions of the event
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input addr_t [NumEvents-1:0] num_2d_reps_i,
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/// Enable the given event
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input logic [NumEvents-1:0] event_ena_i,
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/// Current state of the counters (debugging)
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output event_cnt_t [NumEvents-1:0] event_counts_o,
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/// ND iDMA request
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output idma_nd_req_t nd_req_o,
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/// ND iDMA request valid
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output logic nd_req_valid_o,
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/// ND iDMA request ready
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input logic nd_req_ready_i,
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/// iDMA 1D response
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input idma_rsp_t burst_rsp_i,
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/// iDMA 1D response valid
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input logic burst_rsp_valid_i,
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/// iDMA 1D response ready
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output logic burst_rsp_ready_o,
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/// Bypass: ND iDMA request
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input idma_nd_req_t nd_req_i,
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/// Bypass: ND iDMA request valid
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input logic nd_req_valid_i,
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/// Bypass: ND iDMA request ready
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output logic nd_req_ready_o,
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/// Bypass: iDMA 1D response
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output idma_rsp_t burst_rsp_o,
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/// Bypass: iDMA 1D response valid
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output logic burst_rsp_valid_o,
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/// Bypass: iDMA 1D response ready
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input logic burst_rsp_ready_i
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);
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typedef struct packed {
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idma_nd_req_t req;
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logic src;
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} ext_arb_t;
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// signals around the external arbiter
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ext_arb_t ext_req, int_req, out_req;
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// the choice signal
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logic choice, choice_head;
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// counter overflow -> event is valid
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logic [NumEvents-1:0] event_valid;
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// handshake the event
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logic [NumEvents-1:0] event_ready;
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// clear signal for the counter
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logic [NumEvents-1:0] cnt_load;
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// enable signal for the counter
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logic [NumEvents-1:0] cnt_ena;
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// each counter assembles the struct
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idma_nd_req_t [NumEvents-1:0] idma_nd_req;
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// internal request and its handshake signals
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idma_nd_req_t idma_nd_req_int;
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logic nd_req_valid_int;
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logic nd_req_ready_int;
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// internal response stub
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idma_rsp_t int_rsp;
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logic int_valid;
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// generate the counters timing the events and assemble the transfers
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for (genvar c = 0; c < NumEvents; c++) begin : gen_counters
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// counter instance
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counter #(
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.WIDTH ( EventCntWidth ),
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.STICKY_OVERFLOW ( 1'b0 )
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) i_counter (
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.clk_i,
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.rst_ni,
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.clear_i ( 1'b0 ),
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.en_i ( cnt_ena [c] ),
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.load_i ( cnt_load [c] ),
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.down_i ( 1'b1 ),
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.d_i ( event_counts_i [c] ),
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.q_o ( event_counts_o [c] ),
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.overflow_o ( event_valid [c] )
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);
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// n-d assignment
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assign idma_nd_req[c].d_req[0].reps = num_1d_reps_i [c];
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assign idma_nd_req[c].d_req[0].src_strides = src_1d_stride_i [c];
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assign idma_nd_req[c].d_req[0].dst_strides = dst_1d_stride_i [c];
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assign idma_nd_req[c].d_req[1].reps = num_1d_reps_i [c];
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assign idma_nd_req[c].d_req[1].src_strides = src_1d_stride_i [c];
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assign idma_nd_req[c].d_req[1].dst_strides = dst_1d_stride_i [c];
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// 1D assignment
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assign idma_nd_req[c].burst_req.length = length_i [c];
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assign idma_nd_req[c].burst_req.src_addr = src_addr_i [c];
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assign idma_nd_req[c].burst_req.dst_addr = dst_addr_i [c];
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assign idma_nd_req[c].burst_req.opt = '0;
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end
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// clear on handshake
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assign cnt_load = event_ready & event_valid;
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// disable counters if they are valid
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assign cnt_ena = event_ena_i & ~(event_valid);
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// arbitrates the events
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stream_arbiter #(
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.DATA_T ( idma_nd_req_t ),
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.N_INP ( NumEvents ),
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.ARBITER ( "rr" )
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) i_stream_arbiter (
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.clk_i,
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.rst_ni,
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.inp_data_i ( idma_nd_req ),
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.inp_valid_i ( event_valid ),
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.inp_ready_o ( event_ready ),
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.oup_data_o ( idma_nd_req_int ),
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.oup_valid_o ( nd_req_valid_int ),
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.oup_ready_i ( nd_req_ready_int )
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);
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// arbitrates the events
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stream_arbiter #(
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.DATA_T ( ext_arb_t ),
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.N_INP ( 32'd2 ),
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.ARBITER ( "rr" )
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) i_stream_arbiter_bypass (
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.clk_i,
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.rst_ni,
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.inp_data_i ( { ext_req, int_req } ),
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.inp_valid_i ( { nd_req_valid_i, nd_req_valid_int } ),
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.inp_ready_o ( { nd_req_ready_o, nd_req_ready_int } ),
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.oup_data_o ( out_req ),
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.oup_valid_o ( nd_req_valid_o ),
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.oup_ready_i ( nd_req_ready_i )
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);
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// assemble arbiter inputs
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assign ext_req.req = nd_req_i;
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assign ext_req.src = 1'b1;
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assign int_req.req = idma_nd_req_int;
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assign int_req.src = 1'b0;
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// arbiters outputs
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assign nd_req_o = out_req.req;
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assign choice = out_req.src;
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// safe the choice in a fifo
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stream_fifo #(
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.FALL_THROUGH ( 1'b0 ),
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.DATA_WIDTH ( 32'd1 ),
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.DEPTH ( NumOutstanding )
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) i_stream_fifo (
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.clk_i,
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.rst_ni,
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.flush_i ( 1'b0 ),
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.testmode_i ( 1'b0 ),
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.usage_o ( /* NC */ ),
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.data_i ( choice ),
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.valid_i ( nd_req_valid_i & nd_req_ready_o ),
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.ready_o ( /* HACK: NC */ ),
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.data_o ( choice_head ),
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.valid_o ( /* HACK: NC */ ),
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.ready_i ( burst_rsp_valid_o & burst_rsp_ready_i )
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);
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// arbitration of responses
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stream_demux #(
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.N_OUP ( 32'd2 )
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) i_stream_demux (
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.inp_valid_i ( burst_rsp_valid_i ),
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.inp_ready_o ( burst_rsp_ready_o ),
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.oup_sel_i ( choice_head ),
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.oup_valid_o ( { burst_rsp_valid_o, int_valid } ),
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.oup_ready_i ( { burst_rsp_ready_i, 1'b1 } )
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);
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assign burst_rsp_o = burst_rsp_i;
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endmodule

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