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micprogthommythomaso
micprog
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thommythomaso
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Update axi and pulp_open axi_to_mem mapping #11 
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‎Bender.yml

+1-2
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ package:
1111
dependencies:
1212
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 }
1313
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
14-
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.35.1 }
14+
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.37.0 }
1515
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
1616

1717
export_include_dirs:
@@ -72,7 +72,6 @@ sources:
7272
# Systems
7373
- target: all(pulp, not(mchan))
7474
files:
75-
- src/systems/pulpopen/idma_axi_to_mem.sv
7675
- src/systems/pulpopen/dmac_wrap.sv
7776

7877
- target: cva6

‎src/systems/pulpopen/dmac_wrap.sv

+36-80
Original file line numberDiff line numberDiff line change
@@ -119,8 +119,7 @@ module dmac_wrap #(
119119
`AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t)
120120
// BUS definitions
121121
mst_req_t tcdm_req, soc_req;
122-
mem_req_t tcdm_read_req, tcdm_write_req;
123-
mst_resp_t soc_rsp, tcdm_read_rsp, tcdm_write_rsp;
122+
mst_resp_t soc_rsp;
124123
mst_resp_t tcdm_rsp;
125124
slv_req_t [NUM_STREAMS-1:0] dma_req;
126125
slv_resp_t [NUM_STREAMS-1:0] dma_rsp;
@@ -242,7 +241,7 @@ module dmac_wrap #(
242241
localparam logic [1:0][31:0] RepWidths = '{default: 32'd32};
243242

244243
idma_nd_midend #(
245-
.NumDim ( 32'd2 ),
244+
.NumDim ( NumDim ),
246245
.addr_t ( addr_t ),
247246
.idma_req_t ( idma_req_t ),
248247
.idma_rsp_t ( idma_rsp_t ),
@@ -388,92 +387,49 @@ module dmac_wrap #(
388387
.clk_i ( clk_i ),
389388
.rst_ni ( rst_ni ),
390389
.test_i ( test_mode_i ),
391-
.slv_ports_req_i ( dma_req ),
392-
.slv_ports_resp_o ( dma_rsp ),
390+
.slv_ports_req_i ( dma_req ),
391+
.slv_ports_resp_o ( dma_rsp ),
393392
.mst_ports_req_o ( { tcdm_req, soc_req } ),
394393
.mst_ports_resp_i ( { tcdm_rsp, soc_rsp } ),
395394
.addr_map_i ( addr_map ),
396395
.en_default_mst_port_i ( '0 ),
397396
.default_mst_port_i ( '0 )
398397
);
399398

400-
// split AXI bus in read and write
401-
always_comb begin : proc_tcdm_axi_rw_split
402-
`AXI_SET_R_STRUCT(tcdm_rsp.r, tcdm_read_rsp.r)
403-
tcdm_rsp.r_valid = tcdm_read_rsp.r_valid;
404-
tcdm_rsp.ar_ready = tcdm_read_rsp.ar_ready;
405-
`AXI_SET_B_STRUCT(tcdm_rsp.b, tcdm_write_rsp.b)
406-
tcdm_rsp.b_valid = tcdm_write_rsp.b_valid;
407-
tcdm_rsp.w_ready = tcdm_write_rsp.w_ready;
408-
tcdm_rsp.aw_ready = tcdm_write_rsp.aw_ready;
409-
410-
tcdm_write_req = '0;
411-
`AXI_SET_AW_STRUCT(tcdm_write_req.aw, tcdm_req.aw)
412-
tcdm_write_req.aw.addr = tcdm_req.aw.addr[ADDR_WIDTH-1:0];
413-
tcdm_write_req.aw_valid = tcdm_req.aw_valid;
414-
`AXI_SET_W_STRUCT(tcdm_write_req.w, tcdm_req.w)
415-
tcdm_write_req.w_valid = tcdm_req.w_valid;
416-
tcdm_write_req.b_ready = tcdm_req.b_ready;
417-
418-
tcdm_read_req = '0;
419-
`AXI_SET_AR_STRUCT(tcdm_read_req.ar, tcdm_req.ar)
420-
tcdm_read_req.ar.addr = tcdm_req.ar.addr[ADDR_WIDTH-1:0];
421-
tcdm_read_req.ar_valid = tcdm_req.ar_valid;
422-
tcdm_read_req.r_ready = tcdm_req.r_ready;
423-
end
424-
425-
logic tcdm_master_we_0, tcdm_master_we_1, tcdm_master_we_2, tcdm_master_we_3;
426-
427399
localparam int unsigned TcdmFifoDepth = 1;
428400

429-
idma_axi_to_mem #(
430-
.axi_req_t ( mem_req_t ),
431-
.axi_resp_t ( mst_resp_t ),
432-
.AddrWidth ( ADDR_WIDTH ),
433-
.DataWidth ( AXI_DATA_WIDTH ),
434-
.IdWidth ( MstIdxWidth ),
435-
.NumBanks ( 2 ),
436-
.BufDepth ( TcdmFifoDepth )
437-
) i_axi_to_mem_read (
438-
.clk_i ( clk_i ),
439-
.rst_ni ( rst_ni ),
440-
.busy_o ( ),
441-
.axi_req_i ( tcdm_read_req ),
442-
.axi_resp_o ( tcdm_read_rsp ),
443-
.mem_req_o ( { tcdm_master[0].req, tcdm_master[1].req } ),
444-
.mem_gnt_i ( { tcdm_master[0].gnt, tcdm_master[1].gnt } ),
445-
.mem_addr_o ( { tcdm_master[0].add, tcdm_master[1].add } ),
446-
.mem_wdata_o ( { tcdm_master[0].data, tcdm_master[1].data } ),
447-
.mem_strb_o ( { tcdm_master[0].be, tcdm_master[1].be } ),
448-
// .mem_atop_o ( ),
449-
.mem_we_o ( { tcdm_master_we_0, tcdm_master_we_1 } ),
450-
.mem_rvalid_i ( { tcdm_master[0].r_valid, tcdm_master[1].r_valid } ),
451-
.mem_rdata_i ( { tcdm_master[0].r_data, tcdm_master[1].r_data } )
452-
);
453-
454-
idma_axi_to_mem #(
455-
.axi_req_t ( mem_req_t ),
456-
.axi_resp_t ( mst_resp_t ),
457-
.AddrWidth ( ADDR_WIDTH ),
458-
.DataWidth ( AXI_DATA_WIDTH ),
459-
.IdWidth ( MstIdxWidth ),
460-
.NumBanks ( 2 ),
461-
.BufDepth ( TcdmFifoDepth )
462-
) i_axi_to_mem_write (
463-
.clk_i ( clk_i ),
464-
.rst_ni ( rst_ni ),
465-
.busy_o ( ),
466-
.axi_req_i ( tcdm_write_req ),
467-
.axi_resp_o ( tcdm_write_rsp ),
468-
.mem_req_o ( { tcdm_master[2].req, tcdm_master[3].req } ),
469-
.mem_gnt_i ( { tcdm_master[2].gnt, tcdm_master[3].gnt } ),
470-
.mem_addr_o ( { tcdm_master[2].add, tcdm_master[3].add } ),
471-
.mem_wdata_o ( { tcdm_master[2].data, tcdm_master[3].data } ),
472-
.mem_strb_o ( { tcdm_master[2].be, tcdm_master[3].be } ),
473-
// .mem_atop_o ( ),
474-
.mem_we_o ( { tcdm_master_we_2, tcdm_master_we_3 } ),
475-
.mem_rvalid_i ( { tcdm_master[2].r_valid, tcdm_master[3].r_valid } ),
476-
.mem_rdata_i ( { tcdm_master[2].r_data, tcdm_master[3].r_data } )
401+
axi_to_mem_split #(
402+
.axi_req_t ( mem_req_t ),
403+
.axi_resp_t ( mst_resp_t ),
404+
.AddrWidth ( ADDR_WIDTH ),
405+
.AxiDataWidth ( AXI_DATA_WIDTH ),
406+
.IdWidth ( MstIdxWidth ),
407+
.MemDataWidth ( DATA_WIDTH ),
408+
.BufDepth ( TcdmFifoDepth ),
409+
.HideStrb ( 1'b1 )
410+
) i_axi_to_mem (
411+
.clk_i,
412+
.rst_ni,
413+
.busy_o (),
414+
.axi_req_i ( tcdm_req ),
415+
.axi_resp_o ( tcdm_rsp ),
416+
.mem_req_o ( { tcdm_master[0].req, tcdm_master[1].req,
417+
tcdm_master[2].req, tcdm_master[3].req } ),
418+
.mem_gnt_i ( { tcdm_master[0].gnt, tcdm_master[1].gnt,
419+
tcdm_master[2].gnt, tcdm_master[3].gnt } ),
420+
.mem_addr_o ( { tcdm_master[0].add, tcdm_master[1].add,
421+
tcdm_master[2].add, tcdm_master[3].add } ),
422+
.mem_wdata_o ( { tcdm_master[0].data, tcdm_master[1].data,
423+
tcdm_master[2].data, tcdm_master[3].data } ),
424+
.mem_strb_o ( { tcdm_master[0].be, tcdm_master[1].be,
425+
tcdm_master[2].be, tcdm_master[3].be } ),
426+
.mem_atop_o ( ),
427+
.mem_we_o ( { tcdm_master_we_0, tcdm_master_we_1,
428+
tcdm_master_we_2, tcdm_master_we_3 } ),
429+
.mem_rvalid_i ( { tcdm_master[0].r_valid, tcdm_master[1].r_valid,
430+
tcdm_master[2].r_valid, tcdm_master[3].r_valid } ),
431+
.mem_rdata_i ( { tcdm_master[0].r_data, tcdm_master[1].r_data,
432+
tcdm_master[2].r_data, tcdm_master[3].r_data } )
477433
);
478434

479435
// tie-off TCDM master port

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