From 09fd4045f90ec9b25fa83b6b5a3a9f1fdfece965 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Mon, 6 Jan 2020 11:23:56 -0800 Subject: [PATCH 1/2] Update gold files for bit const codegen --- tests/test_syntax/gold/ArrayOfBitsSeq.v | 30 +++++++++---------- tests/test_syntax/gold/CustomEnv.v | 4 +-- tests/test_syntax/gold/RdPtr.v | 2 +- tests/test_syntax/gold/RegisterMode.v | 6 ++-- tests/test_syntax/gold/RegisterModeARST.v | 6 ++-- tests/test_syntax/gold/TestBasic.v | 4 +-- tests/test_syntax/gold/TestBasicARST.v | 4 +-- tests/test_syntax/gold/TestCall.v | 6 ++-- tests/test_syntax/gold/TestShiftRegister.v | 4 +-- .../test_syntax/gold/TestShiftRegisterARST.v | 4 +-- tests/test_verilog/gold/test_pad.v | 2 +- 11 files changed, 36 insertions(+), 36 deletions(-) diff --git a/tests/test_syntax/gold/ArrayOfBitsSeq.v b/tests/test_syntax/gold/ArrayOfBitsSeq.v index d6ecf532b..503258b51 100644 --- a/tests/test_syntax/gold/ArrayOfBitsSeq.v +++ b/tests/test_syntax/gold/ArrayOfBitsSeq.v @@ -91,21 +91,21 @@ wire [1023:0] reg_PR_inst7_out; wire [1023:0] reg_PR_inst8_out; wire [1023:0] reg_PR_inst9_out; ArrayOfBitsSeq_comb ArrayOfBitsSeq_comb_inst0(.I_0(I_0), .I_1(I_1), .I_10(I_10), .I_11(I_11), .I_12(I_12), .I_13(I_13), .I_14(I_14), .I_2(I_2), .I_3(I_3), .I_4(I_4), .I_5(I_5), .I_6(I_6), .I_7(I_7), .I_8(I_8), .I_9(I_9), .O0_0(ArrayOfBitsSeq_comb_inst0_O0_0), .O0_1(ArrayOfBitsSeq_comb_inst0_O0_1), .O0_10(ArrayOfBitsSeq_comb_inst0_O0_10), .O0_11(ArrayOfBitsSeq_comb_inst0_O0_11), .O0_12(ArrayOfBitsSeq_comb_inst0_O0_12), .O0_13(ArrayOfBitsSeq_comb_inst0_O0_13), .O0_14(ArrayOfBitsSeq_comb_inst0_O0_14), .O0_2(ArrayOfBitsSeq_comb_inst0_O0_2), .O0_3(ArrayOfBitsSeq_comb_inst0_O0_3), .O0_4(ArrayOfBitsSeq_comb_inst0_O0_4), .O0_5(ArrayOfBitsSeq_comb_inst0_O0_5), .O0_6(ArrayOfBitsSeq_comb_inst0_O0_6), .O0_7(ArrayOfBitsSeq_comb_inst0_O0_7), .O0_8(ArrayOfBitsSeq_comb_inst0_O0_8), .O0_9(ArrayOfBitsSeq_comb_inst0_O0_9), .O1_0(ArrayOfBitsSeq_comb_inst0_O1_0), .O1_1(ArrayOfBitsSeq_comb_inst0_O1_1), .O1_10(ArrayOfBitsSeq_comb_inst0_O1_10), .O1_11(ArrayOfBitsSeq_comb_inst0_O1_11), .O1_12(ArrayOfBitsSeq_comb_inst0_O1_12), .O1_13(ArrayOfBitsSeq_comb_inst0_O1_13), .O1_14(ArrayOfBitsSeq_comb_inst0_O1_14), .O1_2(ArrayOfBitsSeq_comb_inst0_O1_2), .O1_3(ArrayOfBitsSeq_comb_inst0_O1_3), .O1_4(ArrayOfBitsSeq_comb_inst0_O1_4), .O1_5(ArrayOfBitsSeq_comb_inst0_O1_5), .O1_6(ArrayOfBitsSeq_comb_inst0_O1_6), .O1_7(ArrayOfBitsSeq_comb_inst0_O1_7), .O1_8(ArrayOfBitsSeq_comb_inst0_O1_8), .O1_9(ArrayOfBitsSeq_comb_inst0_O1_9), .self_register_array_O_0(reg_PR_inst0_out), .self_register_array_O_1(reg_PR_inst1_out), .self_register_array_O_10(reg_PR_inst10_out), .self_register_array_O_11(reg_PR_inst11_out), .self_register_array_O_12(reg_PR_inst12_out), .self_register_array_O_13(reg_PR_inst13_out), .self_register_array_O_14(reg_PR_inst14_out), .self_register_array_O_2(reg_PR_inst2_out), .self_register_array_O_3(reg_PR_inst3_out), .self_register_array_O_4(reg_PR_inst4_out), .self_register_array_O_5(reg_PR_inst5_out), .self_register_array_O_6(reg_PR_inst6_out), .self_register_array_O_7(reg_PR_inst7_out), .self_register_array_O_8(reg_PR_inst8_out), .self_register_array_O_9(reg_PR_inst9_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_0), .out(reg_PR_inst0_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_1), .out(reg_PR_inst1_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst10(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_10), .out(reg_PR_inst10_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst11(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_11), .out(reg_PR_inst11_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst12(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_12), .out(reg_PR_inst12_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst13(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_13), .out(reg_PR_inst13_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst14(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_14), .out(reg_PR_inst14_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst2(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_2), .out(reg_PR_inst2_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst3(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_3), .out(reg_PR_inst3_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst4(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_4), .out(reg_PR_inst4_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst5(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_5), .out(reg_PR_inst5_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst6(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_6), .out(reg_PR_inst6_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst7(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_7), .out(reg_PR_inst7_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst8(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_8), .out(reg_PR_inst8_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst9(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_9), .out(reg_PR_inst9_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_0), .out(reg_PR_inst0_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_1), .out(reg_PR_inst1_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst10(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_10), .out(reg_PR_inst10_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst11(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_11), .out(reg_PR_inst11_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst12(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_12), .out(reg_PR_inst12_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst13(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_13), .out(reg_PR_inst13_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst14(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_14), .out(reg_PR_inst14_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst2(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_2), .out(reg_PR_inst2_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst3(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_3), .out(reg_PR_inst3_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst4(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_4), .out(reg_PR_inst4_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst5(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_5), .out(reg_PR_inst5_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst6(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_6), .out(reg_PR_inst6_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst7(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_7), .out(reg_PR_inst7_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst8(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_8), .out(reg_PR_inst8_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .width(1024)) reg_PR_inst9(.arst(ASYNCRESET), .clk(CLK), .in(ArrayOfBitsSeq_comb_inst0_O0_9), .out(reg_PR_inst9_out)); assign O_0 = ArrayOfBitsSeq_comb_inst0_O1_0; assign O_1 = ArrayOfBitsSeq_comb_inst0_O1_1; assign O_10 = ArrayOfBitsSeq_comb_inst0_O1_10; diff --git a/tests/test_syntax/gold/CustomEnv.v b/tests/test_syntax/gold/CustomEnv.v index 33f7099ea..5b173c66b 100644 --- a/tests/test_syntax/gold/CustomEnv.v +++ b/tests/test_syntax/gold/CustomEnv.v @@ -24,8 +24,8 @@ wire [1:0] TestBasic_comb_inst0_O2; wire [1:0] reg_PR_inst0_out; wire [1:0] reg_PR_inst1_out; TestBasic_comb TestBasic_comb_inst0(.I(I), .O0(TestBasic_comb_inst0_O0), .O1(TestBasic_comb_inst0_O1), .O2(TestBasic_comb_inst0_O2), .self_x_O(reg_PR_inst0_out), .self_y_O(reg_PR_inst1_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h2), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_PR_inst0_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h0), .width(2)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O1), .out(reg_PR_inst1_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h2), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_PR_inst0_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h0), .width(2)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O1), .out(reg_PR_inst1_out)); assign O = TestBasic_comb_inst0_O2; endmodule diff --git a/tests/test_syntax/gold/RdPtr.v b/tests/test_syntax/gold/RdPtr.v index e8528fd5c..a1dfc152f 100644 --- a/tests/test_syntax/gold/RdPtr.v +++ b/tests/test_syntax/gold/RdPtr.v @@ -36,7 +36,7 @@ wire [9:0] RdPtr_comb_inst0_O0; wire [9:0] RdPtr_comb_inst0_O1; wire [9:0] reg_PR_inst0_out; RdPtr_comb RdPtr_comb_inst0(.O0(RdPtr_comb_inst0_O0), .O1(RdPtr_comb_inst0_O1), .read(read), .self_rd_ptr_O(reg_PR_inst0_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(10'h000), .width(10)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(RdPtr_comb_inst0_O0), .out(reg_PR_inst0_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(10'h000), .width(10)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(RdPtr_comb_inst0_O0), .out(reg_PR_inst0_out)); assign O = RdPtr_comb_inst0_O1; endmodule diff --git a/tests/test_syntax/gold/RegisterMode.v b/tests/test_syntax/gold/RegisterMode.v index 0b29d9c55..4b28a9d68 100644 --- a/tests/test_syntax/gold/RegisterMode.v +++ b/tests/test_syntax/gold/RegisterMode.v @@ -38,7 +38,7 @@ wire [3:0] Register_comb_inst0_O0; wire [3:0] Register_comb_inst0_O1; wire [3:0] reg_P_inst0_out; Register_comb Register_comb_inst0(.O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .en(en), .self_value_O(reg_P_inst0_out), .value(value)); -coreir_reg #(.clk_posedge(1), .init(4'h0), .width(4)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out)); +coreir_reg #(.clk_posedge(1'b1), .init(4'h0), .width(4)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out)); assign O = Register_comb_inst0_O1; endmodule @@ -110,8 +110,8 @@ Mux2_x4 Mux2_x4_inst6(.I0(value), .I1(value), .O(Mux2_x4_inst6_O), .S(eq_inst9_o Mux2_x4 Mux2_x4_inst7(.I0(self_register_O), .I1(value), .O(Mux2_x4_inst7_O), .S(eq_inst11_out)); Mux2_x4 Mux2_x4_inst8(.I0(self_register_O), .I1(self_register_O), .O(Mux2_x4_inst8_O), .S(eq_inst12_out)); Mux2_x4 Mux2_x4_inst9(.I0(Mux2_x4_inst6_O), .I1(value), .O(Mux2_x4_inst9_O), .S(eq_inst13_out)); -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); -corebit_const #(.value(1)) bit_const_1_None(.out(bit_const_1_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b1)) bit_const_1_None(.out(bit_const_1_None_out)); coreir_const #(.value(2'h0), .width(2)) const_0_2(.out(const_0_2_out)); coreir_const #(.value(2'h1), .width(2)) const_1_2(.out(const_1_2_out)); coreir_eq #(.width(2)) eq_inst0(.in0(mode), .in1(const_1_2_out), .out(eq_inst0_out)); diff --git a/tests/test_syntax/gold/RegisterModeARST.v b/tests/test_syntax/gold/RegisterModeARST.v index f0a511b01..724451391 100644 --- a/tests/test_syntax/gold/RegisterModeARST.v +++ b/tests/test_syntax/gold/RegisterModeARST.v @@ -41,7 +41,7 @@ wire [3:0] Register_comb_inst0_O0; wire [3:0] Register_comb_inst0_O1; wire [3:0] reg_PR_inst0_out; Register_comb Register_comb_inst0(.O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .en(en), .self_value_O(reg_PR_inst0_out), .value(value)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(4'h0), .width(4)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(Register_comb_inst0_O0), .out(reg_PR_inst0_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(4'h0), .width(4)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(Register_comb_inst0_O0), .out(reg_PR_inst0_out)); assign O = Register_comb_inst0_O1; endmodule @@ -113,8 +113,8 @@ Mux2_x4 Mux2_x4_inst6(.I0(value), .I1(value), .O(Mux2_x4_inst6_O), .S(eq_inst9_o Mux2_x4 Mux2_x4_inst7(.I0(self_register_O), .I1(value), .O(Mux2_x4_inst7_O), .S(eq_inst11_out)); Mux2_x4 Mux2_x4_inst8(.I0(self_register_O), .I1(self_register_O), .O(Mux2_x4_inst8_O), .S(eq_inst12_out)); Mux2_x4 Mux2_x4_inst9(.I0(Mux2_x4_inst6_O), .I1(value), .O(Mux2_x4_inst9_O), .S(eq_inst13_out)); -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); -corebit_const #(.value(1)) bit_const_1_None(.out(bit_const_1_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b1)) bit_const_1_None(.out(bit_const_1_None_out)); coreir_const #(.value(2'h0), .width(2)) const_0_2(.out(const_0_2_out)); coreir_const #(.value(2'h1), .width(2)) const_1_2(.out(const_1_2_out)); coreir_eq #(.width(2)) eq_inst0(.in0(mode), .in1(const_1_2_out), .out(eq_inst0_out)); diff --git a/tests/test_syntax/gold/TestBasic.v b/tests/test_syntax/gold/TestBasic.v index f62c5abfd..098f6f8cd 100644 --- a/tests/test_syntax/gold/TestBasic.v +++ b/tests/test_syntax/gold/TestBasic.v @@ -21,8 +21,8 @@ wire [1:0] TestBasic_comb_inst0_O2; wire [1:0] reg_P_inst0_out; wire [1:0] reg_P_inst1_out; TestBasic_comb TestBasic_comb_inst0(.I(I), .O0(TestBasic_comb_inst0_O0), .O1(TestBasic_comb_inst0_O1), .O2(TestBasic_comb_inst0_O2), .self_x_O(reg_P_inst0_out), .self_y_O(reg_P_inst1_out)); -coreir_reg #(.clk_posedge(1), .init(2'h0), .width(2)) reg_P_inst0(.clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_P_inst0_out)); -coreir_reg #(.clk_posedge(1), .init(2'h0), .width(2)) reg_P_inst1(.clk(CLK), .in(TestBasic_comb_inst0_O1), .out(reg_P_inst1_out)); +coreir_reg #(.clk_posedge(1'b1), .init(2'h0), .width(2)) reg_P_inst0(.clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_P_inst0_out)); +coreir_reg #(.clk_posedge(1'b1), .init(2'h0), .width(2)) reg_P_inst1(.clk(CLK), .in(TestBasic_comb_inst0_O1), .out(reg_P_inst1_out)); assign O = TestBasic_comb_inst0_O2; endmodule diff --git a/tests/test_syntax/gold/TestBasicARST.v b/tests/test_syntax/gold/TestBasicARST.v index 80ac59026..40d1e0511 100644 --- a/tests/test_syntax/gold/TestBasicARST.v +++ b/tests/test_syntax/gold/TestBasicARST.v @@ -24,8 +24,8 @@ wire [1:0] TestBasic_comb_inst0_O2; wire [1:0] reg_PR_inst0_out; wire [1:0] reg_PR_inst1_out; TestBasic_comb TestBasic_comb_inst0(.I(I), .O0(TestBasic_comb_inst0_O0), .O1(TestBasic_comb_inst0_O1), .O2(TestBasic_comb_inst0_O2), .self_x_O(reg_PR_inst0_out), .self_y_O(reg_PR_inst1_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h0), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_PR_inst0_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h0), .width(2)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O1), .out(reg_PR_inst1_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h0), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O0), .out(reg_PR_inst0_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h0), .width(2)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(TestBasic_comb_inst0_O1), .out(reg_PR_inst1_out)); assign O = TestBasic_comb_inst0_O2; endmodule diff --git a/tests/test_syntax/gold/TestCall.v b/tests/test_syntax/gold/TestCall.v index 6a92278a7..2c3718550 100644 --- a/tests/test_syntax/gold/TestCall.v +++ b/tests/test_syntax/gold/TestCall.v @@ -17,7 +17,7 @@ endmodule module TestCall_comb (input [1:0] I, output [1:0] O0, output [2:0] O1, output [2:0] O2, input [1:0] self_x_O, input [2:0] self_y_O); wire bit_const_0_None_out; -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); assign O0 = I; assign O1 = {bit_const_0_None_out,self_x_O[1],self_x_O[0]}; assign O2 = self_y_O; @@ -30,8 +30,8 @@ wire [2:0] TestCall_comb_inst0_O2; wire [1:0] reg_PR_inst0_out; wire [2:0] reg_PR_inst1_out; TestCall_comb TestCall_comb_inst0(.I(I), .O0(TestCall_comb_inst0_O0), .O1(TestCall_comb_inst0_O1), .O2(TestCall_comb_inst0_O2), .self_x_O(reg_PR_inst0_out), .self_y_O(reg_PR_inst1_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h0), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestCall_comb_inst0_O0), .out(reg_PR_inst0_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(3'h0), .width(3)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(TestCall_comb_inst0_O1), .out(reg_PR_inst1_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h0), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(TestCall_comb_inst0_O0), .out(reg_PR_inst0_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(3'h0), .width(3)) reg_PR_inst1(.arst(ASYNCRESET), .clk(CLK), .in(TestCall_comb_inst0_O1), .out(reg_PR_inst1_out)); assign O = TestCall_comb_inst0_O2; endmodule diff --git a/tests/test_syntax/gold/TestShiftRegister.v b/tests/test_syntax/gold/TestShiftRegister.v index 46d6bdd37..a757d4903 100644 --- a/tests/test_syntax/gold/TestShiftRegister.v +++ b/tests/test_syntax/gold/TestShiftRegister.v @@ -24,7 +24,7 @@ wire [1:0] Register_comb_inst0_O0; wire [1:0] Register_comb_inst0_O1; wire [1:0] reg_P_inst0_out; Register_comb Register_comb_inst0(.I(I), .O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .self_value_O(reg_P_inst0_out)); -coreir_reg #(.clk_posedge(1), .init(2'h1), .width(2)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out)); +coreir_reg #(.clk_posedge(1'b1), .init(2'h1), .width(2)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out)); assign O = Register_comb_inst0_O1; endmodule @@ -33,7 +33,7 @@ wire [1:0] Register_comb_inst0_O0; wire [1:0] Register_comb_inst0_O1; wire [1:0] reg_P_inst0_out; Register_comb Register_comb_inst0(.I(I), .O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .self_value_O(reg_P_inst0_out)); -coreir_reg #(.clk_posedge(1), .init(2'h0), .width(2)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out)); +coreir_reg #(.clk_posedge(1'b1), .init(2'h0), .width(2)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out)); assign O = Register_comb_inst0_O1; endmodule diff --git a/tests/test_syntax/gold/TestShiftRegisterARST.v b/tests/test_syntax/gold/TestShiftRegisterARST.v index afad5acb0..91582164d 100644 --- a/tests/test_syntax/gold/TestShiftRegisterARST.v +++ b/tests/test_syntax/gold/TestShiftRegisterARST.v @@ -27,7 +27,7 @@ wire [1:0] Register_comb_inst0_O0; wire [1:0] Register_comb_inst0_O1; wire [1:0] reg_PR_inst0_out; Register_comb Register_comb_inst0(.I(I), .O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .self_value_O(reg_PR_inst0_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h1), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(Register_comb_inst0_O0), .out(reg_PR_inst0_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h1), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(Register_comb_inst0_O0), .out(reg_PR_inst0_out)); assign O = Register_comb_inst0_O1; endmodule @@ -36,7 +36,7 @@ wire [1:0] Register_comb_inst0_O0; wire [1:0] Register_comb_inst0_O1; wire [1:0] reg_PR_inst0_out; Register_comb Register_comb_inst0(.I(I), .O0(Register_comb_inst0_O0), .O1(Register_comb_inst0_O1), .self_value_O(reg_PR_inst0_out)); -coreir_reg_arst #(.arst_posedge(1), .clk_posedge(1), .init(2'h0), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(Register_comb_inst0_O0), .out(reg_PR_inst0_out)); +coreir_reg_arst #(.arst_posedge(1'b1), .clk_posedge(1'b1), .init(2'h0), .width(2)) reg_PR_inst0(.arst(ASYNCRESET), .clk(CLK), .in(Register_comb_inst0_O0), .out(reg_PR_inst0_out)); assign O = Register_comb_inst0_O1; endmodule diff --git a/tests/test_verilog/gold/test_pad.v b/tests/test_verilog/gold/test_pad.v index ac813849c..9cfa89a0a 100644 --- a/tests/test_verilog/gold/test_pad.v +++ b/tests/test_verilog/gold/test_pad.v @@ -8,7 +8,7 @@ wire PRWDWUWSWCDGH_V_inst0_C; wire PRWDWUWSWCDGH_V_inst0_PAD; wire bit_const_0_None_out; PRWDWUWSWCDGH_V PRWDWUWSWCDGH_V_inst0(.C(PRWDWUWSWCDGH_V_inst0_C), .DS0(bit_const_0_None_out), .DS1(bit_const_0_None_out), .DS2(bit_const_0_None_out), .I(bit_const_0_None_out), .IE(bit_const_0_None_out), .OEN(bit_const_0_None_out), .PAD(PRWDWUWSWCDGH_V_inst0_PAD), .PD(bit_const_0_None_out), .PU(bit_const_0_None_out), .RTE(bit_const_0_None_out), .SL(bit_const_0_None_out), .ST(bit_const_0_None_out)); -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); assign pad = PRWDWUWSWCDGH_V_inst0_PAD; endmodule From 0fa290092cecd4d0fa15423cfbb2c7e4b91f82c3 Mon Sep 17 00:00:00 2001 From: Lenny Truong Date: Fri, 10 Jan 2020 17:14:48 -0800 Subject: [PATCH 2/2] Update golds --- tests/test_type/gold/TestBits1ext.v | 2 +- tests/test_type/gold/TestBits3ext.v | 2 +- tests/test_type/gold/TestSInt3adc.v | 2 +- tests/test_type/gold/TestSInt7adc.v | 2 +- tests/test_type/gold/TestUInt1adc.v | 2 +- tests/test_type/gold/TestUInt3adc.v | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/test_type/gold/TestBits1ext.v b/tests/test_type/gold/TestBits1ext.v index 2a41c9491..f37efab9b 100644 --- a/tests/test_type/gold/TestBits1ext.v +++ b/tests/test_type/gold/TestBits1ext.v @@ -4,7 +4,7 @@ endmodule module TestExt (input [0:0] I, output [3:0] O); wire bit_const_0_None_out; -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); assign O = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,I[0]}; endmodule diff --git a/tests/test_type/gold/TestBits3ext.v b/tests/test_type/gold/TestBits3ext.v index 3f65fc399..8dbb9614c 100644 --- a/tests/test_type/gold/TestBits3ext.v +++ b/tests/test_type/gold/TestBits3ext.v @@ -4,7 +4,7 @@ endmodule module TestExt (input [2:0] I, output [5:0] O); wire bit_const_0_None_out; -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); assign O = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,I[2],I[1],I[0]}; endmodule diff --git a/tests/test_type/gold/TestSInt3adc.v b/tests/test_type/gold/TestSInt3adc.v index f1cbe4b2e..868b77859 100644 --- a/tests/test_type/gold/TestSInt3adc.v +++ b/tests/test_type/gold/TestSInt3adc.v @@ -10,7 +10,7 @@ module TestBinary (input CIN, output COUT, input [2:0] I0, input [2:0] I1, outpu wire bit_const_0_None_out; wire [3:0] magma_Bits_4_add_inst0_out; wire [3:0] magma_Bits_4_add_inst1_out; -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); coreir_add #(.width(4)) magma_Bits_4_add_inst0(.in0({I0[2],I0[2],I0[1],I0[0]}), .in1({I1[2],I1[2],I1[1],I1[0]}), .out(magma_Bits_4_add_inst0_out)); coreir_add #(.width(4)) magma_Bits_4_add_inst1(.in0(magma_Bits_4_add_inst0_out), .in1({bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,CIN}), .out(magma_Bits_4_add_inst1_out)); assign COUT = magma_Bits_4_add_inst1_out[3]; diff --git a/tests/test_type/gold/TestSInt7adc.v b/tests/test_type/gold/TestSInt7adc.v index 0adb6188a..acee1ebab 100644 --- a/tests/test_type/gold/TestSInt7adc.v +++ b/tests/test_type/gold/TestSInt7adc.v @@ -10,7 +10,7 @@ module TestBinary (input CIN, output COUT, input [6:0] I0, input [6:0] I1, outpu wire bit_const_0_None_out; wire [7:0] magma_Bits_8_add_inst0_out; wire [7:0] magma_Bits_8_add_inst1_out; -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); coreir_add #(.width(8)) magma_Bits_8_add_inst0(.in0({I0[6],I0[6],I0[5],I0[4],I0[3],I0[2],I0[1],I0[0]}), .in1({I1[6],I1[6],I1[5],I1[4],I1[3],I1[2],I1[1],I1[0]}), .out(magma_Bits_8_add_inst0_out)); coreir_add #(.width(8)) magma_Bits_8_add_inst1(.in0(magma_Bits_8_add_inst0_out), .in1({bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,CIN}), .out(magma_Bits_8_add_inst1_out)); assign COUT = magma_Bits_8_add_inst1_out[7]; diff --git a/tests/test_type/gold/TestUInt1adc.v b/tests/test_type/gold/TestUInt1adc.v index 7d2f42b70..51cf28720 100644 --- a/tests/test_type/gold/TestUInt1adc.v +++ b/tests/test_type/gold/TestUInt1adc.v @@ -10,7 +10,7 @@ module TestBinary (input CIN, output COUT, input [0:0] I0, input [0:0] I1, outpu wire bit_const_0_None_out; wire [1:0] magma_Bits_2_add_inst0_out; wire [1:0] magma_Bits_2_add_inst1_out; -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); coreir_add #(.width(2)) magma_Bits_2_add_inst0(.in0({bit_const_0_None_out,I0[0]}), .in1({bit_const_0_None_out,I1[0]}), .out(magma_Bits_2_add_inst0_out)); coreir_add #(.width(2)) magma_Bits_2_add_inst1(.in0(magma_Bits_2_add_inst0_out), .in1({bit_const_0_None_out,CIN}), .out(magma_Bits_2_add_inst1_out)); assign COUT = magma_Bits_2_add_inst1_out[1]; diff --git a/tests/test_type/gold/TestUInt3adc.v b/tests/test_type/gold/TestUInt3adc.v index b37bf0d80..9b06bc385 100644 --- a/tests/test_type/gold/TestUInt3adc.v +++ b/tests/test_type/gold/TestUInt3adc.v @@ -10,7 +10,7 @@ module TestBinary (input CIN, output COUT, input [2:0] I0, input [2:0] I1, outpu wire bit_const_0_None_out; wire [3:0] magma_Bits_4_add_inst0_out; wire [3:0] magma_Bits_4_add_inst1_out; -corebit_const #(.value(0)) bit_const_0_None(.out(bit_const_0_None_out)); +corebit_const #(.value(1'b0)) bit_const_0_None(.out(bit_const_0_None_out)); coreir_add #(.width(4)) magma_Bits_4_add_inst0(.in0({bit_const_0_None_out,I0[2],I0[1],I0[0]}), .in1({bit_const_0_None_out,I1[2],I1[1],I1[0]}), .out(magma_Bits_4_add_inst0_out)); coreir_add #(.width(4)) magma_Bits_4_add_inst1(.in0(magma_Bits_4_add_inst0_out), .in1({bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,CIN}), .out(magma_Bits_4_add_inst1_out)); assign COUT = magma_Bits_4_add_inst1_out[3];