diff --git a/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/AnalyzerGuru.java b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/AnalyzerGuru.java index f62e2bfbe45..d2310f2d709 100644 --- a/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/AnalyzerGuru.java +++ b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/AnalyzerGuru.java @@ -19,7 +19,7 @@ /* * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved. - * Portions Copyright (c) 2017-2018, Chris Fraire . + * Portions Copyright (c) 2017-2019, Chris Fraire . */ package org.opengrok.indexer.analysis; @@ -102,6 +102,7 @@ import org.opengrok.indexer.analysis.tcl.TclAnalyzerFactory; import org.opengrok.indexer.analysis.uue.UuencodeAnalyzerFactory; import org.opengrok.indexer.analysis.vb.VBAnalyzerFactory; +import org.opengrok.indexer.analysis.verilog.VerilogAnalyzerFactory; import org.opengrok.indexer.configuration.Project; import org.opengrok.indexer.configuration.RuntimeEnvironment; import org.opengrok.indexer.history.Annotation; @@ -293,7 +294,8 @@ public class AnalyzerGuru { new PascalAnalyzerFactory(), new AdaAnalyzerFactory(), new RubyAnalyzerFactory(), - new EiffelAnalyzerFactory() + new EiffelAnalyzerFactory(), + new VerilogAnalyzerFactory() }; for (AnalyzerFactory analyzer : analyzers) { diff --git a/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/Consts.java b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/Consts.java new file mode 100644 index 00000000000..77ad0c28559 --- /dev/null +++ b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/Consts.java @@ -0,0 +1,330 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2019, Chris Fraire . + */ + +package org.opengrok.indexer.analysis.verilog; + +import java.util.HashSet; +import java.util.Set; + +/** + * Represents a container for a set of SystemVerilog keywords. + */ +public class Consts { + + public static final Set kwd = new HashSet<>(); + + static { + kwd.add("accept_on"); // IEEE 1800-2017 + kwd.add("alias"); // IEEE 1800-2017 + kwd.add("always"); // IEEE 1800-2017 + kwd.add("always_comb"); // IEEE 1800-2017 + kwd.add("always_ff"); // IEEE 1800-2017 + kwd.add("always_latch"); // IEEE 1800-2017 + kwd.add("and"); // IEEE 1800-2017 + kwd.add("assert"); // IEEE 1800-2017 + kwd.add("assign"); // IEEE 1800-2017 + kwd.add("assume"); // IEEE 1800-2017 + kwd.add("automatic"); // IEEE 1800-2017 + kwd.add("before"); // IEEE 1800-2017 + kwd.add("begin"); // IEEE 1800-2017 + kwd.add("bind"); // IEEE 1800-2017 + kwd.add("bins"); // IEEE 1800-2017 + kwd.add("binsof"); // IEEE 1800-2017 + kwd.add("bit"); // IEEE 1800-2017 + kwd.add("break"); // IEEE 1800-2017 + kwd.add("buf"); // IEEE 1800-2017 + kwd.add("bufif0"); // IEEE 1800-2017 + kwd.add("bufif1"); // IEEE 1800-2017 + kwd.add("byte"); // IEEE 1800-2017 + kwd.add("case"); // IEEE 1800-2017 + kwd.add("casex"); // IEEE 1800-2017 + kwd.add("casez"); // IEEE 1800-2017 + kwd.add("cell"); // IEEE 1800-2017 + kwd.add("chandle"); // IEEE 1800-2017 + kwd.add("checker"); // IEEE 1800-2017 + kwd.add("class"); // IEEE 1800-2017 + kwd.add("clocking"); // IEEE 1800-2017 + kwd.add("cmos"); // IEEE 1800-2017 + kwd.add("config"); // IEEE 1800-2017 + kwd.add("const"); // IEEE 1800-2017 + kwd.add("constraint"); // IEEE 1800-2017 + kwd.add("context"); // IEEE 1800-2017 + kwd.add("continue"); // IEEE 1800-2017 + kwd.add("cover"); // IEEE 1800-2017 + kwd.add("covergroup"); // IEEE 1800-2017 + kwd.add("coverpoint"); // IEEE 1800-2017 + kwd.add("cross"); // IEEE 1800-2017 + kwd.add("deassign"); // IEEE 1800-2017 + kwd.add("default"); // IEEE 1800-2017 + kwd.add("defparam"); // IEEE 1800-2017 + kwd.add("design"); // IEEE 1800-2017 + kwd.add("disable"); // IEEE 1800-2017 + kwd.add("dist"); // IEEE 1800-2017 + kwd.add("do"); // IEEE 1800-2017 + kwd.add("edge"); // IEEE 1800-2017 + kwd.add("else"); // IEEE 1800-2017 + kwd.add("end"); // IEEE 1800-2017 + kwd.add("endcase"); // IEEE 1800-2017 + kwd.add("endchecker"); // IEEE 1800-2017 + kwd.add("endclass"); // IEEE 1800-2017 + kwd.add("endclocking"); // IEEE 1800-2017 + kwd.add("endconfig"); // IEEE 1800-2017 + kwd.add("endfunction"); // IEEE 1800-2017 + kwd.add("endgenerate"); // IEEE 1800-2017 + kwd.add("endgroup"); // IEEE 1800-2017 + kwd.add("endinterface"); // IEEE 1800-2017 + kwd.add("endmodule"); // IEEE 1800-2017 + kwd.add("endpackage"); // IEEE 1800-2017 + kwd.add("endprimitive"); // IEEE 1800-2017 + kwd.add("endprogram"); // IEEE 1800-2017 + kwd.add("endproperty"); // IEEE 1800-2017 + kwd.add("endspecify"); // IEEE 1800-2017 + kwd.add("endsequence"); // IEEE 1800-2017 + kwd.add("endtable"); // IEEE 1800-2017 + kwd.add("endtask"); // IEEE 1800-2017 + kwd.add("enum"); // IEEE 1800-2017 + kwd.add("event"); // IEEE 1800-2017 + kwd.add("eventually"); // IEEE 1800-2017 + kwd.add("expect"); // IEEE 1800-2017 + kwd.add("export"); // IEEE 1800-2017 + kwd.add("extends"); // IEEE 1800-2017 + kwd.add("extern"); // IEEE 1800-2017 + kwd.add("final"); // IEEE 1800-2017 + kwd.add("first_match"); // IEEE 1800-2017 + kwd.add("for"); // IEEE 1800-2017 + kwd.add("force"); // IEEE 1800-2017 + kwd.add("foreach"); // IEEE 1800-2017 + kwd.add("forever"); // IEEE 1800-2017 + kwd.add("fork"); // IEEE 1800-2017 + kwd.add("forkjoin"); // IEEE 1800-2017 + kwd.add("function"); // IEEE 1800-2017 + kwd.add("generate"); // IEEE 1800-2017 + kwd.add("genvar"); // IEEE 1800-2017 + kwd.add("global"); // IEEE 1800-2017 + kwd.add("highz0"); // IEEE 1800-2017 + kwd.add("highz1"); // IEEE 1800-2017 + kwd.add("if"); // IEEE 1800-2017 + kwd.add("iff"); // IEEE 1800-2017 + kwd.add("ifnone"); // IEEE 1800-2017 + kwd.add("ignore_bins"); // IEEE 1800-2017 + kwd.add("illegal_bins"); // IEEE 1800-2017 + kwd.add("implements"); // IEEE 1800-2017 + kwd.add("implies"); // IEEE 1800-2017 + kwd.add("import"); // IEEE 1800-2017 + kwd.add("incdir"); // IEEE 1800-2017 + kwd.add("include"); // IEEE 1800-2017 + kwd.add("initial"); // IEEE 1800-2017 + kwd.add("inout"); // IEEE 1800-2017 + kwd.add("input"); // IEEE 1800-2017 + kwd.add("inside"); // IEEE 1800-2017 + kwd.add("instance"); // IEEE 1800-2017 + kwd.add("int"); // IEEE 1800-2017 + kwd.add("integer"); // IEEE 1800-2017 + kwd.add("interconnect"); // IEEE 1800-2017 + kwd.add("interface"); // IEEE 1800-2017 + kwd.add("intersect"); // IEEE 1800-2017 + kwd.add("join"); // IEEE 1800-2017 + kwd.add("join_any"); // IEEE 1800-2017 + kwd.add("join_none"); // IEEE 1800-2017 + kwd.add("large"); // IEEE 1800-2017 + kwd.add("let"); // IEEE 1800-2017 + kwd.add("liblist"); // IEEE 1800-2017 + kwd.add("library"); // IEEE 1800-2017 + kwd.add("local"); // IEEE 1800-2017 + kwd.add("localparam"); // IEEE 1800-2017 + kwd.add("logic"); // IEEE 1800-2017 + kwd.add("longint"); // IEEE 1800-2017 + kwd.add("macromodule"); // IEEE 1800-2017 + kwd.add("matches"); // IEEE 1800-2017 + kwd.add("medium"); // IEEE 1800-2017 + kwd.add("modport"); // IEEE 1800-2017 + kwd.add("module"); // IEEE 1800-2017 + kwd.add("nand"); // IEEE 1800-2017 + kwd.add("negedge"); // IEEE 1800-2017 + kwd.add("nettype"); // IEEE 1800-2017 + kwd.add("new"); // IEEE 1800-2017 + kwd.add("nexttime"); // IEEE 1800-2017 + kwd.add("nmos"); // IEEE 1800-2017 + kwd.add("nor"); // IEEE 1800-2017 + kwd.add("noshowcancelled"); // IEEE 1800-2017 + kwd.add("not"); // IEEE 1800-2017 + kwd.add("notif0"); // IEEE 1800-2017 + kwd.add("notif1"); // IEEE 1800-2017 + kwd.add("null"); // IEEE 1800-2017 + kwd.add("or"); // IEEE 1800-2017 + kwd.add("output"); // IEEE 1800-2017 + kwd.add("package"); // IEEE 1800-2017 + kwd.add("packed"); // IEEE 1800-2017 + kwd.add("parameter"); // IEEE 1800-2017 + kwd.add("pmos"); // IEEE 1800-2017 + kwd.add("posedge"); // IEEE 1800-2017 + kwd.add("primitive"); // IEEE 1800-2017 + kwd.add("priority"); // IEEE 1800-2017 + kwd.add("program"); // IEEE 1800-2017 + kwd.add("property"); // IEEE 1800-2017 + kwd.add("protected"); // IEEE 1800-2017 + kwd.add("pull0"); // IEEE 1800-2017 + kwd.add("pull1"); // IEEE 1800-2017 + kwd.add("pulldown"); // IEEE 1800-2017 + kwd.add("pullup"); // IEEE 1800-2017 + kwd.add("pulsestyle_ondetect"); // IEEE 1800-2017 + kwd.add("pulsestyle_onevent"); // IEEE 1800-2017 + kwd.add("pure"); // IEEE 1800-2017 + kwd.add("rand"); // IEEE 1800-2017 + kwd.add("randc"); // IEEE 1800-2017 + kwd.add("randcase"); // IEEE 1800-2017 + kwd.add("randsequence"); // IEEE 1800-2017 + kwd.add("rcmos"); // IEEE 1800-2017 + kwd.add("real"); // IEEE 1800-2017 + kwd.add("realtime"); // IEEE 1800-2017 + kwd.add("ref"); // IEEE 1800-2017 + kwd.add("reg"); // IEEE 1800-2017 + kwd.add("reject_on"); // IEEE 1800-2017 + kwd.add("release"); // IEEE 1800-2017 + kwd.add("repeat"); // IEEE 1800-2017 + kwd.add("restrict"); // IEEE 1800-2017 + kwd.add("return"); // IEEE 1800-2017 + kwd.add("rnmos"); // IEEE 1800-2017 + kwd.add("rpmos"); // IEEE 1800-2017 + kwd.add("rtran"); // IEEE 1800-2017 + kwd.add("rtranif0"); // IEEE 1800-2017 + kwd.add("rtranif1"); // IEEE 1800-2017 + kwd.add("s_always"); // IEEE 1800-2017 + kwd.add("s_eventually"); // IEEE 1800-2017 + kwd.add("s_nexttime"); // IEEE 1800-2017 + kwd.add("s_until"); // IEEE 1800-2017 + kwd.add("s_until_with"); // IEEE 1800-2017 + kwd.add("scalared"); // IEEE 1800-2017 + kwd.add("sequence"); // IEEE 1800-2017 + kwd.add("shortint"); // IEEE 1800-2017 + kwd.add("shortreal"); // IEEE 1800-2017 + kwd.add("showcancelled"); // IEEE 1800-2017 + kwd.add("signed"); // IEEE 1800-2017 + kwd.add("small"); // IEEE 1800-2017 + kwd.add("soft"); // IEEE 1800-2017 + kwd.add("solve"); // IEEE 1800-2017 + kwd.add("specify"); // IEEE 1800-2017 + kwd.add("specparam"); // IEEE 1800-2017 + kwd.add("static"); // IEEE 1800-2017 + kwd.add("string"); // IEEE 1800-2017 + kwd.add("strong"); // IEEE 1800-2017 + kwd.add("strong0"); // IEEE 1800-2017 + kwd.add("strong1"); // IEEE 1800-2017 + kwd.add("struct"); // IEEE 1800-2017 + kwd.add("super"); // IEEE 1800-2017 + kwd.add("supply0"); // IEEE 1800-2017 + kwd.add("supply1"); // IEEE 1800-2017 + kwd.add("sync_accept_on"); // IEEE 1800-2017 + kwd.add("sync_reject_on"); // IEEE 1800-2017 + kwd.add("table"); // IEEE 1800-2017 + kwd.add("tagged"); // IEEE 1800-2017 + kwd.add("task"); // IEEE 1800-2017 + kwd.add("this"); // IEEE 1800-2017 + kwd.add("throughout"); // IEEE 1800-2017 + kwd.add("time"); // IEEE 1800-2017 + kwd.add("timeprecision"); // IEEE 1800-2017 + kwd.add("timeunit"); // IEEE 1800-2017 + kwd.add("tran"); // IEEE 1800-2017 + kwd.add("tranif0"); // IEEE 1800-2017 + kwd.add("tranif1"); // IEEE 1800-2017 + kwd.add("tri"); // IEEE 1800-2017 + kwd.add("tri0"); // IEEE 1800-2017 + kwd.add("tri1"); // IEEE 1800-2017 + kwd.add("triand"); // IEEE 1800-2017 + kwd.add("trior"); // IEEE 1800-2017 + kwd.add("trireg"); // IEEE 1800-2017 + kwd.add("type"); // IEEE 1800-2017 + kwd.add("typedef"); // IEEE 1800-2017 + kwd.add("union"); // IEEE 1800-2017 + kwd.add("unique"); // IEEE 1800-2017 + kwd.add("unique0"); // IEEE 1800-2017 + kwd.add("unsigned"); // IEEE 1800-2017 + kwd.add("until"); // IEEE 1800-2017 + kwd.add("until_with"); // IEEE 1800-2017 + kwd.add("untyped"); // IEEE 1800-2017 + kwd.add("use"); // IEEE 1800-2017 + kwd.add("uwire"); // IEEE 1800-2017 + kwd.add("var"); // IEEE 1800-2017 + kwd.add("vectored"); // IEEE 1800-2017 + kwd.add("virtual"); // IEEE 1800-2017 + kwd.add("void"); // IEEE 1800-2017 + kwd.add("wait"); // IEEE 1800-2017 + kwd.add("wait_order"); // IEEE 1800-2017 + kwd.add("wand"); // IEEE 1800-2017 + kwd.add("weak"); // IEEE 1800-2017 + kwd.add("weak0"); // IEEE 1800-2017 + kwd.add("weak1"); // IEEE 1800-2017 + kwd.add("while"); // IEEE 1800-2017 + kwd.add("wildcard"); // IEEE 1800-2017 + kwd.add("wire"); // IEEE 1800-2017 + kwd.add("with"); // IEEE 1800-2017 + kwd.add("within"); // IEEE 1800-2017 + kwd.add("wor"); // IEEE 1800-2017 + kwd.add("xnor"); // IEEE 1800-2017 + kwd.add("xor"); // IEEE 1800-2017 + kwd.add("`__FILE__"); // IEEE 1800-2017 + kwd.add("`__LINE__"); // IEEE 1800-2017 + kwd.add("`begin_keywords"); // IEEE 1800-2017 + kwd.add("`celldefine"); // IEEE 1800-2017 + kwd.add("`default_decay_time"); // IEEE 1800-2017 + kwd.add("`default_nettype"); // IEEE 1800-2017 + kwd.add("`default_trireg_strength"); // IEEE 1800-2017 + kwd.add("`define"); // IEEE 1800-2017 + kwd.add("`delay_mode_distributed"); // IEEE 1800-2017 + kwd.add("`delay_mode_path"); // IEEE 1800-2017 + kwd.add("`delay_mode_unit"); // IEEE 1800-2017 + kwd.add("`delay_mode_zero"); // IEEE 1800-2017 + kwd.add("`else"); // IEEE 1800-2017 + kwd.add("`elsif"); // IEEE 1800-2017 + kwd.add("`end_keywords"); // IEEE 1800-2017 + kwd.add("`endcelldefine"); // IEEE 1800-2017 + kwd.add("`endif"); // IEEE 1800-2017 + kwd.add("`ifdef"); // IEEE 1800-2017 + kwd.add("`ifndef"); // IEEE 1800-2017 + kwd.add("`include"); // IEEE 1800-2017 + kwd.add("`line"); // IEEE 1800-2017 + kwd.add("`nounconnected_drive"); // IEEE 1800-2017 + kwd.add("`pragma"); // IEEE 1800-2017 + kwd.add("`resetall"); // IEEE 1800-2017 + kwd.add("`timescale"); // IEEE 1800-2017 + kwd.add("`unconnected_drive"); // IEEE 1800-2017 + kwd.add("`undef"); // IEEE 1800-2017 + kwd.add("`undefineall"); // IEEE 1800-2017 +// kwd.add("$setup"); // IEEE 1800-2017 +// kwd.add("$fullskew"); // IEEE 1800-2017 +// kwd.add("$hold"); // IEEE 1800-2017 +// kwd.add("$nochange"); // IEEE 1800-2017 +// kwd.add("$period"); // IEEE 1800-2017 +// kwd.add("$recovery"); // IEEE 1800-2017 +// kwd.add("$recrem"); // IEEE 1800-2017 +// kwd.add("$removal"); // IEEE 1800-2017 +// kwd.add("$setuphold"); // IEEE 1800-2017 +// kwd.add("$skew"); // IEEE 1800-2017 +// kwd.add("$timeskew"); // IEEE 1800-2017 +// kwd.add("$width"); // IEEE 1800-2017 + } + + /** private to enforce static */ + private Consts() { + } +} diff --git a/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogAnalyzer.java b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogAnalyzer.java new file mode 100644 index 00000000000..d9b977532b2 --- /dev/null +++ b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogAnalyzer.java @@ -0,0 +1,67 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2019, Chris Fraire . + */ + +package org.opengrok.indexer.analysis.verilog; + +import org.opengrok.indexer.analysis.AbstractAnalyzer; +import org.opengrok.indexer.analysis.FileAnalyzerFactory; +import org.opengrok.indexer.analysis.JFlexTokenizer; +import org.opengrok.indexer.analysis.JFlexXref; +import org.opengrok.indexer.analysis.plain.AbstractSourceCodeAnalyzer; + +import java.io.Reader; + +/** + * Represents an analyzer for the SystemVerilog language. + */ +public class VerilogAnalyzer extends AbstractSourceCodeAnalyzer { + + /** + * Creates a new instance of {@link VerilogAnalyzer}. + * @param factory instance + */ + protected VerilogAnalyzer(FileAnalyzerFactory factory) { + super(factory, new JFlexTokenizer(new VerilogSymbolTokenizer( + AbstractAnalyzer.DUMMY_READER))); + } + + /** + * Gets a version number to be used to tag processed documents so that + * re-analysis can be re-done later if a stored version number is different + * from the current implementation. + * @return 20190117_04 + */ + @Override + protected int getSpecializedVersionNo() { + return 20190117_04; // Edit comment above too! + } + + /** + * Creates a wrapped {@link VerilogXref} instance. + * @return a defined instance + */ + @Override + protected JFlexXref newXref(Reader reader) { + return new JFlexXref(new VerilogXref(reader)); + } +} diff --git a/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogAnalyzerFactory.java b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogAnalyzerFactory.java new file mode 100644 index 00000000000..2055ca9f31f --- /dev/null +++ b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogAnalyzerFactory.java @@ -0,0 +1,56 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2019, Chris Fraire . + */ + +package org.opengrok.indexer.analysis.verilog; + +import org.opengrok.indexer.analysis.AbstractAnalyzer.Genre; +import org.opengrok.indexer.analysis.FileAnalyzer; +import org.opengrok.indexer.analysis.FileAnalyzerFactory; + +/** + * Represents a factory to create {@link VerilogAnalyzer} instances. + */ +public class VerilogAnalyzerFactory extends FileAnalyzerFactory { + + private static final String NAME = "Verilog"; + + private static final String[] SUFFIXES = {"SV", "SVH", "V", "VH"}; + + /** + * Initializes a factory instance to associate a file extensions ".sv", + * ".svh", ".v", and ".vh" with {@link VerilogAnalyzer}. + */ + public VerilogAnalyzerFactory() { + super(null, null, SUFFIXES, null, null, "text/plain", Genre.PLAIN, + NAME); + } + + /** + * Creates a new {@link VerilogAnalyzer} instance. + * @return a defined instance + */ + @Override + protected FileAnalyzer newAnalyzer() { + return new VerilogAnalyzer(this); + } +} diff --git a/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogLexer.java b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogLexer.java new file mode 100644 index 00000000000..48502a92e0c --- /dev/null +++ b/opengrok-indexer/src/main/java/org/opengrok/indexer/analysis/verilog/VerilogLexer.java @@ -0,0 +1,57 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2019, Chris Fraire . + */ + +package org.opengrok.indexer.analysis.verilog; + +import org.opengrok.indexer.analysis.JFlexJointLexer; +import org.opengrok.indexer.analysis.JFlexSymbolMatcher; +import org.opengrok.indexer.analysis.Resettable; + +/** + * Represents an abstract base class for SystemVerilog lexers. + */ +@SuppressWarnings("Duplicates") +abstract class VerilogLexer extends JFlexSymbolMatcher + implements JFlexJointLexer, Resettable { + + /** + * Calls {@link #phLOC()} if the yystate is not COMMENT or SCOMMENT. + */ + public void chkLOC() { + if (yystate() != COMMENT() && yystate() != SCOMMENT()) { + phLOC(); + } + } + + /** + * Subclasses must override to get the constant value created by JFlex to + * represent COMMENT. + */ + abstract int COMMENT(); + + /** + * Subclasses must override to get the constant value created by JFlex to + * represent SCOMMENT. + */ + abstract int SCOMMENT(); +} diff --git a/opengrok-indexer/src/main/java/org/opengrok/indexer/index/IndexDatabase.java b/opengrok-indexer/src/main/java/org/opengrok/indexer/index/IndexDatabase.java index f79baf4b69b..8837c50d168 100644 --- a/opengrok-indexer/src/main/java/org/opengrok/indexer/index/IndexDatabase.java +++ b/opengrok-indexer/src/main/java/org/opengrok/indexer/index/IndexDatabase.java @@ -19,7 +19,7 @@ /* * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved. - * Portions Copyright (c) 2017-2018, Chris Fraire . + * Portions Copyright (c) 2017-2019, Chris Fraire . */ package org.opengrok.indexer.index; @@ -1810,8 +1810,9 @@ private IndexAnalysisSettings readAnalysisSettings() throws IOException { private boolean xrefExistsFor(String path) { RuntimeEnvironment env = RuntimeEnvironment.getInstance(); - if (!whatXrefFile(path, env.isCompressXref()).exists()) { - LOGGER.log(Level.FINEST, "Missing {0}", path); + File xrefFile = whatXrefFile(path, env.isCompressXref()); + if (!xrefFile.exists()) { + LOGGER.log(Level.FINEST, "Missing {0}", xrefFile); return false; } diff --git a/opengrok-indexer/src/main/java/org/opengrok/indexer/index/Indexer.java b/opengrok-indexer/src/main/java/org/opengrok/indexer/index/Indexer.java index 6dc7ca19ca8..263817af073 100644 --- a/opengrok-indexer/src/main/java/org/opengrok/indexer/index/Indexer.java +++ b/opengrok-indexer/src/main/java/org/opengrok/indexer/index/Indexer.java @@ -20,12 +20,13 @@ /* * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. * Portions Copyright 2011 Jens Elkner. - * Portions Copyright (c) 2017-2018, Chris Fraire . + * Portions Copyright (c) 2017-2019, Chris Fraire . */ package org.opengrok.indexer.index; import java.io.File; import java.io.IOException; +import java.io.PrintStream; import java.lang.reflect.Field; import java.lang.reflect.InvocationTargetException; import java.net.URI; @@ -92,6 +93,10 @@ public final class Indexer { public static final char PATH_SEPARATOR ='/'; public static String PATH_SEPARATOR_STRING =Character.toString(PATH_SEPARATOR); + private static final String HELP_OPT_1 = "--help"; + private static final String HELP_OPT_2 = "-?"; + private static final String HELP_OPT_3 = "-h"; + private static final Indexer index = new Indexer(); private static Configuration cfg = null; private static boolean checkIndexVersion = false; @@ -141,12 +146,11 @@ public static void main(String[] argv) { try { argv = parseOptions(argv); if (help) { - status = 1; - System.err.println(helpUsage); + PrintStream helpStream = status != 0 ? System.err : System.out; + helpStream.println(helpUsage); if (helpDetailed) { - System.err.println(AnalyzerGuruHelp.getUsage()); - System.err.println( - ConfigurationHelp.getSamples()); + helpStream.println(AnalyzerGuruHelp.getUsage()); + helpStream.println(ConfigurationHelp.getSamples()); } System.exit(status); } @@ -402,7 +406,7 @@ public static WebAddress parseWebAddress(String webAddr) { * @throws ParseException if parsing failed */ public static String[] parseOptions(String[] argv) throws ParseException { - String[] usage = {"--help"}; + String[] usage = {HELP_OPT_1}; String program = "opengrok.jar"; final String[] ON_OFF = {ON, OFF}; final String[] REMOTE_REPO_CHOICES = {ON, OFF, DIRBASED, UIONLY}; @@ -410,13 +414,22 @@ public static String[] parseOptions(String[] argv) throws ParseException { if (argv.length == 0) { argv = usage; // will force usage output - status = 1; + status = 1; // with non-zero EXIT STATUS } + /* + * Pre-match any of the --help options so that some possible exception- + * generating args handlers (e.g. -R) can be short-circuited. + */ + help = Arrays.stream(argv).anyMatch(s -> HELP_OPT_1.equals(s) || + HELP_OPT_2.equals(s) || HELP_OPT_3.equals(s)); + OptionParser configure = OptionParser.scan(parser -> { parser.on("-R configPath").Do(cfgFile -> { try { - cfg = Configuration.read(new File((String)cfgFile)); + if (!help) { + cfg = Configuration.read(new File((String) cfgFile)); + } } catch(IOException e) { die(e.getMessage()); } @@ -430,7 +443,8 @@ public static String[] parseOptions(String[] argv) throws ParseException { parser.setPrologue( String.format("\nUsage: java -jar %s [options] [subDir1 [...]]\n", program)); - parser.on("-?", "-h", "--help", "Display this usage summary.").Do(v -> { + parser.on(HELP_OPT_3, Indexer.HELP_OPT_2, HELP_OPT_1, + "Display this usage summary.").Do(v -> { help = true; helpUsage = parser.getUsage(); }); diff --git a/opengrok-indexer/src/main/java/org/opengrok/indexer/search/Results.java b/opengrok-indexer/src/main/java/org/opengrok/indexer/search/Results.java index 332dd8dff3d..9dc2fab2258 100644 --- a/opengrok-indexer/src/main/java/org/opengrok/indexer/search/Results.java +++ b/opengrok-indexer/src/main/java/org/opengrok/indexer/search/Results.java @@ -20,7 +20,7 @@ /* * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. * Portions Copyright 2011 Jens Elkner. - * Portions Copyright (c) 2017-2018, Chris Fraire . + * Portions Copyright (c) 2017-2019, Chris Fraire . */ package org.opengrok.indexer.search; @@ -276,7 +276,7 @@ private static void printPlain(PrintPlainFinalArgs fargs, Document doc, fargs.morePrefix, true, fargs.tabSize); if (!didPresentNew) { - /** + /* * Fall back to the old view, which re-analyzes text using * PlainLinetokenizer. E.g., when source code is updated (thus * affecting timestamps) but re-indexing is not yet complete. @@ -295,12 +295,15 @@ private static void printPlain(PrintPlainFinalArgs fargs, Document doc, } boolean isDefSearch = fargs.shelp.builder.isDefSearch(); // SRCROOT is read with UTF-8 as a default. + File sourceFile = new File(fargs.shelp.sourceRoot, rpath); try (Reader r = IOUtils.createBOMStrippedReader(new FileInputStream( - new File(fargs.shelp.sourceRoot, rpath)), - StandardCharsets.UTF_8.name())) { + sourceFile), StandardCharsets.UTF_8.name())) { fargs.shelp.sourceContext.getContext(r, fargs.out, fargs.xrefPrefix, fargs.morePrefix, rpath, tags, true, isDefSearch, null, scopes); + } catch (IOException ex) { + LOGGER.log(Level.WARNING, String.format("No context for %s", + sourceFile, ex)); } } } diff --git a/opengrok-indexer/src/main/resources/analysis/verilog/VerilogProductions.lexh b/opengrok-indexer/src/main/resources/analysis/verilog/VerilogProductions.lexh new file mode 100644 index 00000000000..702d0a05a25 --- /dev/null +++ b/opengrok-indexer/src/main/resources/analysis/verilog/VerilogProductions.lexh @@ -0,0 +1,180 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2019, Chris Fraire . + */ + +IdentifierAnyChar = [A-Za-z_$0-9] +CompilerDirective = \` [A-Za-z_]+ +EscapedIdentifier = \\[^\s]+ +SimpleIdentifier = [A-Za-z_] {IdentifierAnyChar}* +SystemTaskFunctionIdentifier = "$" {IdentifierAnyChar}+ + +Number = {Sign}? ({Integer} | {Real}) +Integer = ({Decimal_integer} | {Hexadecimal} | {Binary} | {Octal}) +Decimal_integer = ({UnsignedNumber} | + {NzUnsignedNumber}? {DecimalBase} ({UnsignedNumber} | [XxZz\?]) _*) +Hexadecimal = {Size}? {HexBase} {HEXDIG} ("_" | {HEXDIG})* +Binary = {Size}? {BinaryBase} {BINDIG} ("_" | {BINDIG})* +Octal = {Size}? {OctalBase} {OCTDIG} ("_" | {OCTDIG})* +Real = ({FixedPointNumber} | + {UnsignedNumber} ("." {UnsignedNumber})? [Ee] {Sign}? {UnsignedNumber}) +UnbasedUnsized = \' [01XxZz] +Time = ({UnsignedNumber} | {FixedPointNumber}) + ("s" | "fs" | "ms" | "ns" | "ps" | "us") +UnsignedNumber = {DIGIT} ("_" | {DIGIT})* +NzUnsignedNumber = [1-9] ("_" | {DIGIT})* +FixedPointNumber = {UnsignedNumber} "." {UnsignedNumber} +BasePrefix = \' [Ss]? +DecimalBase = {BasePrefix} [Dd] +HexBase = {BasePrefix} [Hh] +BinaryBase = {BasePrefix} [Bb] +OctalBase = {BasePrefix} [Oo] +DIGIT = [0-9] +HEXDIG = [0-9a-fA-FXxZz\?] +BINDIG = [01XxZz\?] +OCTDIG = [0-7XxZz\?] +Size = {NzUnsignedNumber} +Sign = [\+\-] + +Delay = "#" ({UnsignedNumber} | {Real} | {Time} | "1step") + +/* + * COMMENT : block comment + * SCOMMENT : single-line comment + * STRING : string literal + */ +%state COMMENT SCOMMENT STRING + +%% + { + {SimpleIdentifier} | {SystemTaskFunctionIdentifier} | + {CompilerDirective} { + chkLOC(); + if (offerSymbol(yytext(), 0, false) && returnOnSymbol()) { + return yystate(); + } + } + + {EscapedIdentifier} { + chkLOC(); + String id = yytext().substring(1); + offer("\\"); + if (offerSymbol(id, 1, true) && returnOnSymbol()) { + return yystate(); + } + } + + {Number} | {UnbasedUnsized} | {Time} | {Delay} { + chkLOC(); + onDisjointSpanChanged(HtmlConsts.NUMBER_CLASS, yychar); + offer(yytext()); + onDisjointSpanChanged(null, yychar); + } + + "/*" { + yypush(COMMENT); + onDisjointSpanChanged(HtmlConsts.COMMENT_CLASS, yychar); + offer(yytext()); + } + + "//" { + yypush(SCOMMENT); + onDisjointSpanChanged(HtmlConsts.COMMENT_CLASS, yychar); + offer(yytext()); + } + + \" { + chkLOC(); + yypush(STRING); + onDisjointSpanChanged(HtmlConsts.STRING_CLASS, yychar); + offer(yytext()); + } +} + + { + /* + * Nesting of block comments is not recognized by SystemVerilog. + */ + + "*/" { + offer(yytext()); + onDisjointSpanChanged(null, yychar); + yypop(); + } + + {WhspChar}*{EOL} { + onDisjointSpanChanged(null, yychar); + onEndOfLineMatched(yytext(), yychar); + onDisjointSpanChanged(HtmlConsts.COMMENT_CLASS, yychar); + } +} + + { + {WhspChar}*{EOL} { + onDisjointSpanChanged(null, yychar); + yypop(); + onEndOfLineMatched(yytext(), yychar); + } +} + + { + \" { + chkLOC(); + offer(yytext()); + onDisjointSpanChanged(null, yychar); + yypop(); + } + + \\[\"\\] { + chkLOC(); + offer(yytext()); + } + + {WhspChar}*{EOL} { + onDisjointSpanChanged(null, yychar); + onEndOfLineMatched(yytext(), yychar); + onDisjointSpanChanged(HtmlConsts.STRING_CLASS, yychar); + } +} + + { + {WhspChar}*{EOL} { + onEndOfLineMatched(yytext(), yychar); + } + + \s { + offer(yytext()); + } + + [^] { + chkLOC(); + offer(yytext()); + } +} + + { + {BrowseableURI} { + chkLOC(); + if (takeAllContent()) { + onUriMatched(yytext(), yychar); + } + } +} diff --git a/opengrok-indexer/src/main/resources/analysis/verilog/VerilogSymbolTokenizer.lex b/opengrok-indexer/src/main/resources/analysis/verilog/VerilogSymbolTokenizer.lex new file mode 100644 index 00000000000..342f2c77cbd --- /dev/null +++ b/opengrok-indexer/src/main/resources/analysis/verilog/VerilogSymbolTokenizer.lex @@ -0,0 +1,117 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2019, Chris Fraire . + */ + +package org.opengrok.indexer.analysis.verilog; + +import java.io.IOException; +import org.opengrok.indexer.web.HtmlConsts; +%% +%public +%class VerilogSymbolTokenizer +%extends VerilogLexer +%init{ + yyline = 1; +%init} +%unicode +%int +%char +%include CommonLexer.lexh +%{ + private String lastSymbol; + + /** + * Resets the Verilog tracked state; {@inheritDoc} + */ + @Override + public void reset() { + super.reset(); + lastSymbol = null; + } + + @Override + public void offer(String value) throws IOException { + // noop + } + + @Override + public boolean offerSymbol(String value, int captureOffset, + boolean ignoreKwd) throws IOException { + if (ignoreKwd || !Consts.kwd.contains(value)) { + lastSymbol = value; + onSymbolMatched(value, yychar + captureOffset); + return true; + } else { + lastSymbol = null; + } + return false; + } + + @Override + public void skipSymbol() { + lastSymbol = null; + } + + @Override + public void offerKeyword(String value) throws IOException { + lastSymbol = null; + } + + @Override + public void startNewLine() throws IOException { + // noop + } + + @Override + public void disjointSpan(String className) throws IOException { + // noop + } + + @Override + public void phLOC() { + // noop + } + + protected boolean takeAllContent() { + return false; + } + + protected boolean returnOnSymbol() { + return lastSymbol != null; + } + + /** + * Gets the constant value created by JFlex to represent COMMENT. + */ + @Override + int COMMENT() { return COMMENT; } + + /** + * Gets the constant value created by JFlex to represent SCOMMENT. + */ + @Override + int SCOMMENT() { return SCOMMENT; } +%} + +%include Common.lexh +%include CommonURI.lexh +%include VerilogProductions.lexh diff --git a/opengrok-indexer/src/main/resources/analysis/verilog/VerilogXref.lex b/opengrok-indexer/src/main/resources/analysis/verilog/VerilogXref.lex new file mode 100644 index 00000000000..21885deb69d --- /dev/null +++ b/opengrok-indexer/src/main/resources/analysis/verilog/VerilogXref.lex @@ -0,0 +1,97 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2019, Chris Fraire . + */ + +package org.opengrok.indexer.analysis.verilog; + +import java.io.IOException; +import java.util.Set; +import org.opengrok.indexer.web.HtmlConsts; +%% +%public +%class VerilogXref +%extends VerilogLexer +%char +%init{ + yyline = 1; +%init} +%unicode +%int +%include CommonLexer.lexh +%include CommonXref.lexh +%{ + @Override + public void offer(String value) throws IOException { + onNonSymbolMatched(value, yychar); + } + + @Override + public boolean offerSymbol(String value, int captureOffset, + boolean ignoreKwd) throws IOException { + Set keywords = ignoreKwd ? null : Consts.kwd; + return onFilteredSymbolMatched(value, yychar, keywords, true); + } + + @Override + public void skipSymbol() { + // noop + } + + @Override + public void offerKeyword(String value) throws IOException { + onKeywordMatched(value, yychar); + } + + @Override + public void startNewLine() throws IOException { + onEndOfLineMatched("\n", yychar); + } + + @Override + public void disjointSpan(String className) throws IOException { + onDisjointSpanChanged(className, yychar); + } + + protected boolean takeAllContent() { + return true; + } + + protected boolean returnOnSymbol() { + return false; + } + + /** + * Gets the constant value created by JFlex to represent COMMENT. + */ + @Override + int COMMENT() { return COMMENT; } + + /** + * Gets the constant value created by JFlex to represent SCOMMENT. + */ + @Override + int SCOMMENT() { return SCOMMENT; } +%} + +%include Common.lexh +%include CommonURI.lexh +%include VerilogProductions.lexh diff --git a/opengrok-indexer/src/test/java/org/opengrok/indexer/analysis/verilog/VerilogSymbolTokenizerTest.java b/opengrok-indexer/src/test/java/org/opengrok/indexer/analysis/verilog/VerilogSymbolTokenizerTest.java new file mode 100644 index 00000000000..f6d18ad930c --- /dev/null +++ b/opengrok-indexer/src/test/java/org/opengrok/indexer/analysis/verilog/VerilogSymbolTokenizerTest.java @@ -0,0 +1,71 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2010, 2018, Oracle and/or its affiliates. All rights reserved. + * Portions Copyright (c) 2017, 2019, Chris Fraire . + */ + +package org.opengrok.indexer.analysis.verilog; + +import java.io.BufferedReader; +import java.io.InputStream; +import java.io.InputStreamReader; +import java.nio.charset.StandardCharsets; +import java.util.ArrayList; +import java.util.List; + +import org.junit.Test; +import static org.junit.Assert.assertNotNull; +import static org.opengrok.indexer.util.CustomAssertions.assertSymbolStream; + +/** + * Tests the {@link VerilogSymbolTokenizer} class. + */ +public class VerilogSymbolTokenizerTest { + + /** + * Test sample.v v. samplesymbols.txt + * @throws Exception thrown on error + */ + @Test + public void testVerilogSymbolStream() throws Exception { + InputStream vRes = getClass().getClassLoader().getResourceAsStream( + "analysis/verilog/sample.v"); + assertNotNull("despite sample.v as resource,", vRes); + InputStream symRes = getClass().getClassLoader().getResourceAsStream( + "analysis/verilog/samplesymbols.txt"); + assertNotNull("despite samplesymbols.txt as resource,", symRes); + + List expectedSymbols = new ArrayList<>(); + try (BufferedReader symRead = new BufferedReader(new InputStreamReader( + symRes, StandardCharsets.UTF_8))) { + String line; + while ((line = symRead.readLine()) != null) { + int hashOffset = line.indexOf('#'); + if (hashOffset != -1) { + line = line.substring(0, hashOffset); + } + expectedSymbols.add(line.trim()); + } + } + + assertSymbolStream(VerilogSymbolTokenizer.class, vRes, expectedSymbols); + } +} diff --git a/opengrok-indexer/src/test/java/org/opengrok/indexer/analysis/verilog/VerilogXrefTest.java b/opengrok-indexer/src/test/java/org/opengrok/indexer/analysis/verilog/VerilogXrefTest.java new file mode 100644 index 00000000000..b15416311d7 --- /dev/null +++ b/opengrok-indexer/src/test/java/org/opengrok/indexer/analysis/verilog/VerilogXrefTest.java @@ -0,0 +1,145 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * See LICENSE.txt included in this distribution for the specific + * language governing permissions and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at LICENSE.txt. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2012, 2018, Oracle and/or its affiliates. All rights reserved. + * Portions Copyright (c) 2017, 2019, Chris Fraire . + */ + +package org.opengrok.indexer.analysis.verilog; + +import org.junit.Test; +import org.opengrok.indexer.analysis.AbstractAnalyzer; +import org.opengrok.indexer.analysis.CtagsReader; +import org.opengrok.indexer.analysis.Definitions; +import org.opengrok.indexer.analysis.WriteXrefArgs; +import org.opengrok.indexer.analysis.Xrefer; + +import java.io.BufferedReader; +import java.io.ByteArrayOutputStream; +import java.io.IOException; +import java.io.InputStream; +import java.io.InputStreamReader; +import java.io.PrintStream; +import java.io.StringWriter; +import java.io.Writer; +import java.nio.charset.StandardCharsets; + +import static org.junit.Assert.assertEquals; +import static org.junit.Assert.assertNotNull; +import static org.opengrok.indexer.util.CustomAssertions.assertLinesEqual; +import static org.opengrok.indexer.util.StreamUtils.copyStream; + +/** + * Tests the {@link VerilogXref} class. + */ +public class VerilogXrefTest { + + @Test + public void sampleTest() throws IOException { + writeAndCompare("analysis/verilog/sample.v", + "analysis/verilog/sample_xref.html", + getTagsDefinitions(), 81); + } + + @Test + public void shouldCloseTruncatedStringSpan() throws IOException { + writeAndCompare("analysis/verilog/truncated.v", + "analysis/verilog/truncated_xref.html", + null, 1); + } + + private void writeAndCompare(String sourceResource, String resultResource, + Definitions defs, int expLOC) throws IOException { + + ByteArrayOutputStream bytesOut = new ByteArrayOutputStream(); + + InputStream sourceRes = getClass().getClassLoader().getResourceAsStream( + sourceResource); + assertNotNull(sourceResource + " should get-as-stream", sourceRes); + int actLOC = writeVerilogXref(new PrintStream(bytesOut), sourceRes, defs); + sourceRes.close(); + + InputStream resRes = getClass().getClassLoader().getResourceAsStream( + resultResource); + assertNotNull(resultResource + " should get-as-stream", resRes); + byte[] expectedBytes = copyStream(resRes); + resRes.close(); + bytesOut.close(); + + String outStr = new String(bytesOut.toByteArray(), StandardCharsets.UTF_8); + String[] gotten = outStr.split("\n"); + + String expStr = new String(expectedBytes, StandardCharsets.UTF_8); + String[] expected = expStr.split("\n"); + + assertLinesEqual("Verilog xref", expected, gotten); + assertEquals("Verilog LOC", expLOC, actLOC); + } + + private int writeVerilogXref(PrintStream oss, InputStream iss, + Definitions defs) throws IOException { + + oss.print(getHtmlBegin()); + + Writer sw = new StringWriter(); + VerilogAnalyzerFactory fac = new VerilogAnalyzerFactory(); + AbstractAnalyzer analyzer = fac.getAnalyzer(); + analyzer.setScopesEnabled(true); + analyzer.setFoldingEnabled(true); + WriteXrefArgs writeArgs = new WriteXrefArgs( + new InputStreamReader(iss, StandardCharsets.UTF_8), sw); + writeArgs.setDefs(defs); + Xrefer xref = analyzer.writeXref(writeArgs); + oss.print(sw.toString()); + + oss.print(getHtmlEnd()); + return xref.getLOC(); + } + + private Definitions getTagsDefinitions() throws IOException { + InputStream res = getClass().getClassLoader().getResourceAsStream( + "analysis/verilog/sampletags"); + assertNotNull("though sampletags should stream,", res); + + BufferedReader in = new BufferedReader(new InputStreamReader( + res, StandardCharsets.UTF_8)); + + CtagsReader rdr = new CtagsReader(); + String line; + while ((line = in.readLine()) != null) { + rdr.readLine(line); + } + return rdr.getDefinitions(); + } + + private static String getHtmlBegin() { + return "\n" + + "\n" + + "\n" + + "\n" + + "sampleFile - OpenGrok cross reference" + + " for /sampleFile\n"; + } + + private static String getHtmlEnd() { + return "\n" + + "\n"; + } +} diff --git a/opengrok-indexer/src/test/resources/analysis/verilog/sample.v b/opengrok-indexer/src/test/resources/analysis/verilog/sample.v new file mode 100644 index 00000000000..0594fbd35d0 --- /dev/null +++ b/opengrok-indexer/src/test/resources/analysis/verilog/sample.v @@ -0,0 +1,155 @@ +/* + * MIT License + * + * Copyright (c) 2018 SCARV Project - + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +// +// SCARV Project +// +// University of Bristol +// +// RISC-V Cryptographic Instruction Set Extension +// +// Reference Implementation +// +// + +localparam \SCARV_COP_INSN_SUCCESS = 3'b000; +localparam SCARV_COP_INSN_ABORT = 3'b001; +localparam SCARV_COP_INSN_BAD_INS = 3'b010; +localparam SCARV_COP_INSN_BAD_LAD = 3'b100; +localparam SCARV_COP_INSN_BAD_SAD = 3'b101; +localparam SCARV_COP_INSN_LD_ERR = 3'b110; +localparam SCARV_COP_INSN_ST_ERR = 3'b111; +localparam \module = 3'b111; + +localparam SCARV_COP_ICLASS_PACKED_ARITH = 4'b0001; +localparam SCARV_COP_ICLASS_TWIDDLE = 4'b0010; +localparam SCARV_COP_ICLASS_LOADSTORE = 4'b0011; +localparam SCARV_COP_ICLASS_RANDOM = 4'b0100; +localparam SCARV_COP_ICLASS_MOVE = 4'b0101; +localparam SCARV_COP_ICLASS_MP = 4'b0110; +localparam SCARV_COP_ICLASS_BITWISE = 4'b0111; +localparam SCARV_COP_ICLASS_AES = 4'b1000; +localparam SCARV_COP_ICLASS_SHA3 = 4'b1001; + +localparam SCARV_COP_SCLASS_SHA3_XY = 5'b11000; +localparam SCARV_COP_SCLASS_SHA3_X1 = 5'b11001; +localparam SCARV_COP_SCLASS_SHA3_X2 = 5'b11010; +localparam SCARV_COP_SCLASS_SHA3_X4 = 5'b11100; +localparam SCARV_COP_SCLASS_SHA3_YX = 5'b11011; + +localparam SCARV_COP_SCLASS_SCATTER_B = 5'd0 ; +localparam SCARV_COP_SCLASS_GATHER_B = 5'd1 ; +localparam SCARV_COP_SCLASS_SCATTER_H = 5'd2 ; +localparam SCARV_COP_SCLASS_GATHER_H = 5'd3 ; +localparam SCARV_COP_SCLASS_ST_W = 5'd4 ; +localparam SCARV_COP_SCLASS_LD_W = 5'd5 ; +localparam SCARV_COP_SCLASS_ST_H = 5'd6 ; +localparam SCARV_COP_SCLASS_LH_CR = 5'd7 ; +localparam SCARV_COP_SCLASS_ST_B = 5'd8 ; +localparam SCARV_COP_SCLASS_LB_CR = 5'd9 ; + +`ifdef FORMAL +`include "fml_common.vh" +`endif + +// +// module: scarv_cop_cprs +// +// The general purpose register file used by the COP. +// +module scarv_cop_cprs ( + +input wire g_clk , // Global clock +output wire g_clk_req , // Clock request +input wire g_resetn , // Synchronous active low reset. + +`ifdef FORMAL +`VTX_REGISTER_PORTS_OUT(cprs_snoop) +`endif + +input wire crs1_ren , // Port 1 read enable +input wire [ 3:0] crs1_addr , // Port 1 address +output wire [31:0] crs1_rdata , // Port 1 read data + +input wire crs2_ren , // Port 2 read enable +input wire [ 3:0] crs2_addr , // Port 2 address +output wire [31:0] crs2_rdata , // Port 2 read data + +input wire crs3_ren , // Port 3 read enable +input wire [ 3:0] crs3_addr , // Port 3 address +output wire [31:0] crs3_rdata , // Port 3 read data + +input wire [ 3:0] crd_wen , // Port 4 write enable +input wire [ 3:0] crd_addr , // Port 4 address +input wire [31:0] crd_wdata // Port 4 write data + +); + +// Only need a clock when doing a write. +assign g_clk_req = crd_wen; + +// Storage for the registers +reg [31:0] cprs [15:0]; + +`ifdef FORMAL +`VTX_REGISTER_PORTS_ASSIGNR(cprs_snoop,cprs) +`endif + +// +// Read port logic +// + +assign crs1_rdata = {32{crs1_ren}} & cprs[crs1_addr]; +assign crs2_rdata = {32{crs2_ren}} & cprs[crs2_addr]; +assign crs3_rdata = {32{crs3_ren}} & cprs[crs3_addr]; + +// +// Generate logic for each register. +// +genvar i; +generate for (i = 0; i < 16; i = i + 1) begin : gen_cprs + + always @(posedge g_clk) begin + + if(!g_resetn) begin + `ifdef FORMAL + // If running the yosys formal flow, allow initial + // register values to be any constant value. + #1 cprs[i] <= $anyconst; + `else + #1step cprs[i] <= 32'b0; + `endif + + end else if((|crd_wen) && (crd_addr == i)) begin + if(crd_wen[3]) cprs[i][31:24] <= crd_wdata[31:24]; + if(crd_wen[2]) cprs[i][23:16] <= crd_wdata[23:16]; + if(crd_wen[1]) cprs[i][15: 8] <= crd_wdata[15: 8]; + if(crd_wen[0]) cprs[i][ 7: 0] <= crd_wdata[ 7: 0]; + end + + end + +end endgenerate + +endmodule diff --git a/opengrok-indexer/src/test/resources/analysis/verilog/sample_xref.html b/opengrok-indexer/src/test/resources/analysis/verilog/sample_xref.html new file mode 100644 index 00000000000..06711aa5c1a --- /dev/null +++ b/opengrok-indexer/src/test/resources/analysis/verilog/sample_xref.html @@ -0,0 +1,163 @@ + + + + +sampleFile - OpenGrok cross reference for /sampleFile +1/* +2 * MIT License +3 * +4 * Copyright (c) 2018 SCARV Project - <info@scarv.org> +5 * +6 * Permission is hereby granted, free of charge, to any person obtaining a copy +7 * of this software and associated documentation files (the "Software"), to deal +8 * in the Software without restriction, including without limitation the rights +9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +10 * copies of the Software, and to permit persons to whom the Software is +11 * furnished to do so, subject to the following conditions: +12 * +13 * The above copyright notice and this permission notice shall be included in all +14 * copies or substantial portions of the Software. +15 * +16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +22 * SOFTWARE. +23 */ +24 +25// +26// SCARV Project +27// +28// University of Bristol +29// +30// RISC-V Cryptographic Instruction Set Extension +31// +32// Reference Implementation +33// +34// +35 +36localparam \SCARV_COP_INSN_SUCCESS = 3'b000; +37localparam SCARV_COP_INSN_ABORT = 3'b001; +38localparam SCARV_COP_INSN_BAD_INS = 3'b010; +39localparam SCARV_COP_INSN_BAD_LAD = 3'b100; +40localparam SCARV_COP_INSN_BAD_SAD = 3'b101; +41localparam SCARV_COP_INSN_LD_ERR = 3'b110; +42localparam SCARV_COP_INSN_ST_ERR = 3'b111; +43localparam \module = 3'b111; +44 +45localparam SCARV_COP_ICLASS_PACKED_ARITH = 4'b0001; +46localparam SCARV_COP_ICLASS_TWIDDLE = 4'b0010; +47localparam SCARV_COP_ICLASS_LOADSTORE = 4'b0011; +48localparam SCARV_COP_ICLASS_RANDOM = 4'b0100; +49localparam SCARV_COP_ICLASS_MOVE = 4'b0101; +50localparam SCARV_COP_ICLASS_MP = 4'b0110; +51localparam SCARV_COP_ICLASS_BITWISE = 4'b0111; +52localparam SCARV_COP_ICLASS_AES = 4'b1000; +53localparam SCARV_COP_ICLASS_SHA3 = 4'b1001; +54 +55localparam SCARV_COP_SCLASS_SHA3_XY = 5'b11000; +56localparam SCARV_COP_SCLASS_SHA3_X1 = 5'b11001; +57localparam SCARV_COP_SCLASS_SHA3_X2 = 5'b11010; +58localparam SCARV_COP_SCLASS_SHA3_X4 = 5'b11100; +59localparam SCARV_COP_SCLASS_SHA3_YX = 5'b11011; +60 +61localparam SCARV_COP_SCLASS_SCATTER_B = 5'd0 ; +62localparam SCARV_COP_SCLASS_GATHER_B = 5'd1 ; +63localparam SCARV_COP_SCLASS_SCATTER_H = 5'd2 ; +64localparam SCARV_COP_SCLASS_GATHER_H = 5'd3 ; +65localparam SCARV_COP_SCLASS_ST_W = 5'd4 ; +66localparam SCARV_COP_SCLASS_LD_W = 5'd5 ; +67localparam SCARV_COP_SCLASS_ST_H = 5'd6 ; +68localparam SCARV_COP_SCLASS_LH_CR = 5'd7 ; +69localparam SCARV_COP_SCLASS_ST_B = 5'd8 ; +70localparam SCARV_COP_SCLASS_LB_CR = 5'd9 ; +71 +72`ifdef FORMAL +73`include "fml_common.vh" +74`endif +75 +76// +77// module: scarv_cop_cprs +78// +79// The general purpose register file used by the COP. +80// +81module scarv_cop_cprs ( +82 +83input wire g_clk , // Global clock +84output wire g_clk_req , // Clock request +85input wire g_resetn , // Synchronous active low reset. +86 +87`ifdef FORMAL +88`VTX_REGISTER_PORTS_OUT(cprs_snoop) +89`endif +90 +91input wire crs1_ren , // Port 1 read enable +92input wire [ 3:0] crs1_addr , // Port 1 address +93output wire [31:0] crs1_rdata , // Port 1 read data +94 +95input wire crs2_ren , // Port 2 read enable +96input wire [ 3:0] crs2_addr , // Port 2 address +97output wire [31:0] crs2_rdata , // Port 2 read data +98 +99input wire crs3_ren , // Port 3 read enable +100input wire [ 3:0] crs3_addr , // Port 3 address +101output wire [31:0] crs3_rdata , // Port 3 read data +102 +103input wire [ 3:0] crd_wen , // Port 4 write enable +104input wire [ 3:0] crd_addr , // Port 4 address +105input wire [31:0] crd_wdata // Port 4 write data +106 +107); +108 +109// Only need a clock when doing a write. +110assign g_clk_req = crd_wen; +111 +112// Storage for the registers +113reg [31:0] cprs [15:0]; +114 +115`ifdef FORMAL +116`VTX_REGISTER_PORTS_ASSIGNR(cprs_snoop,cprs) +117`endif +118 +119// +120// Read port logic +121// +122 +123assign crs1_rdata = {32{crs1_ren}} & cprs[crs1_addr]; +124assign crs2_rdata = {32{crs2_ren}} & cprs[crs2_addr]; +125assign crs3_rdata = {32{crs3_ren}} & cprs[crs3_addr]; +126 +127// +128// Generate logic for each register. +129// +130genvar i; +131generate for (i = 0; i < 16; i = i + 1) begin : gen_cprs +132 +133 always @(posedge g_clk) begin +134 +135 if(!g_resetn) begin +136 `ifdef FORMAL +137 // If running the yosys formal flow, allow initial +138 // register values to be any constant value. +139 #1 cprs[i] <= $anyconst; +140 `else +141 #1step cprs[i] <= 32'b0; +142 `endif +143 +144 end else if((|crd_wen) && (crd_addr == i)) begin +145 if(crd_wen[3]) cprs[i][31:24] <= crd_wdata[31:24]; +146 if(crd_wen[2]) cprs[i][23:16] <= crd_wdata[23:16]; +147 if(crd_wen[1]) cprs[i][15: 8] <= crd_wdata[15: 8]; +148 if(crd_wen[0]) cprs[i][ 7: 0] <= crd_wdata[ 7: 0]; +149 end +150 +151 end +152 +153end endgenerate +154 +155endmodule +156 + diff --git a/opengrok-indexer/src/test/resources/analysis/verilog/samplesymbols.txt b/opengrok-indexer/src/test/resources/analysis/verilog/samplesymbols.txt new file mode 100644 index 00000000000..e9c7adb0de5 --- /dev/null +++ b/opengrok-indexer/src/test/resources/analysis/verilog/samplesymbols.txt @@ -0,0 +1,104 @@ +SCARV_COP_INSN_SUCCESS # 36:localparam \SCARV_COP_INSN_SUCCESS = 3'b000; +SCARV_COP_INSN_ABORT +SCARV_COP_INSN_BAD_INS +SCARV_COP_INSN_BAD_LAD +SCARV_COP_INSN_BAD_SAD +SCARV_COP_INSN_LD_ERR +SCARV_COP_INSN_ST_ERR +module +SCARV_COP_ICLASS_PACKED_ARITH +SCARV_COP_ICLASS_TWIDDLE +SCARV_COP_ICLASS_LOADSTORE +SCARV_COP_ICLASS_RANDOM +SCARV_COP_ICLASS_MOVE +SCARV_COP_ICLASS_MP +SCARV_COP_ICLASS_BITWISE +SCARV_COP_ICLASS_AES +SCARV_COP_ICLASS_SHA3 +SCARV_COP_SCLASS_SHA3_XY +SCARV_COP_SCLASS_SHA3_X1 +SCARV_COP_SCLASS_SHA3_X2 +SCARV_COP_SCLASS_SHA3_X4 +SCARV_COP_SCLASS_SHA3_YX +SCARV_COP_SCLASS_SCATTER_B +SCARV_COP_SCLASS_GATHER_B +SCARV_COP_SCLASS_SCATTER_H +SCARV_COP_SCLASS_GATHER_H +SCARV_COP_SCLASS_ST_W +SCARV_COP_SCLASS_LD_W +SCARV_COP_SCLASS_ST_H +SCARV_COP_SCLASS_LH_CR +SCARV_COP_SCLASS_ST_B +SCARV_COP_SCLASS_LB_CR +FORMAL +scarv_cop_cprs # 81:module scarv_cop_cprs ( +g_clk +g_clk_req +g_resetn +FORMAL +`VTX_REGISTER_PORTS_OUT +cprs_snoop +crs1_ren +crs1_addr +crs1_rdata +crs2_ren +crs2_addr +crs2_rdata +crs3_ren +crs3_addr +crs3_rdata +crd_wen +crd_addr +crd_wdata +g_clk_req # 110:assign g_clk_req = crd_wen; +crd_wen +cprs +FORMAL +`VTX_REGISTER_PORTS_ASSIGNR +cprs_snoop +cprs +crs1_rdata +crs1_ren +cprs +crs1_addr +crs2_rdata +crs2_ren +cprs +crs2_addr +crs3_rdata +crs3_ren +cprs +crs3_addr +i # 131:generate for (i = 0; i < 16; i = i + 1... +i +i +i +i +gen_cprs +g_clk +g_resetn +FORMAL +cprs +i +$anyconst +cprs +i +crd_wen +crd_addr +i +crd_wen +cprs +i +crd_wdata +crd_wen +cprs +i +crd_wdata +crd_wen +cprs +i +crd_wdata +crd_wen +cprs +i +crd_wdata diff --git a/opengrok-indexer/src/test/resources/analysis/verilog/sampletags b/opengrok-indexer/src/test/resources/analysis/verilog/sampletags new file mode 100644 index 00000000000..fa3c8bca59a --- /dev/null +++ b/opengrok-indexer/src/test/resources/analysis/verilog/sampletags @@ -0,0 +1,56 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 0 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_PROGRAM_AUTHOR Universal Ctags Team // +!_TAG_PROGRAM_NAME Universal Ctags /Derived from Exuberant Ctags/ +!_TAG_PROGRAM_URL https://ctags.io/ /official site/ +!_TAG_PROGRAM_VERSION 0.0.0 /6f7654b9/ +!_TAG_OUTPUT_MODE u-ctags /u-ctags or e-ctags/ +SCARV_COP_INSN_ABORT grok.v /^localparam SCARV_COP_INSN_ABORT = 3'b001;$/;" constant line:37 +SCARV_COP_INSN_BAD_INS grok.v /^localparam SCARV_COP_INSN_BAD_INS = 3'b010;$/;" constant line:38 +SCARV_COP_INSN_BAD_LAD grok.v /^localparam SCARV_COP_INSN_BAD_LAD = 3'b100;$/;" constant line:39 +SCARV_COP_INSN_BAD_SAD grok.v /^localparam SCARV_COP_INSN_BAD_SAD = 3'b101;$/;" constant line:40 +SCARV_COP_INSN_LD_ERR grok.v /^localparam SCARV_COP_INSN_LD_ERR = 3'b110;$/;" constant line:41 +SCARV_COP_INSN_ST_ERR grok.v /^localparam SCARV_COP_INSN_ST_ERR = 3'b111;$/;" constant line:42 +SCARV_COP_ICLASS_PACKED_ARITH grok.v /^localparam SCARV_COP_ICLASS_PACKED_ARITH = 4'b0001;$/;" constant line:45 +SCARV_COP_ICLASS_TWIDDLE grok.v /^localparam SCARV_COP_ICLASS_TWIDDLE = 4'b0010;$/;" constant line:46 +SCARV_COP_ICLASS_LOADSTORE grok.v /^localparam SCARV_COP_ICLASS_LOADSTORE = 4'b0011;$/;" constant line:47 +SCARV_COP_ICLASS_RANDOM grok.v /^localparam SCARV_COP_ICLASS_RANDOM = 4'b0100;$/;" constant line:48 +SCARV_COP_ICLASS_MOVE grok.v /^localparam SCARV_COP_ICLASS_MOVE = 4'b0101;$/;" constant line:49 +SCARV_COP_ICLASS_MP grok.v /^localparam SCARV_COP_ICLASS_MP = 4'b0110;$/;" constant line:50 +SCARV_COP_ICLASS_BITWISE grok.v /^localparam SCARV_COP_ICLASS_BITWISE = 4'b0111;$/;" constant line:51 +SCARV_COP_ICLASS_AES grok.v /^localparam SCARV_COP_ICLASS_AES = 4'b1000;$/;" constant line:52 +SCARV_COP_ICLASS_SHA3 grok.v /^localparam SCARV_COP_ICLASS_SHA3 = 4'b1001;$/;" constant line:53 +SCARV_COP_SCLASS_SHA3_XY grok.v /^localparam SCARV_COP_SCLASS_SHA3_XY = 5'b11000;$/;" constant line:55 +SCARV_COP_SCLASS_SHA3_X1 grok.v /^localparam SCARV_COP_SCLASS_SHA3_X1 = 5'b11001;$/;" constant line:56 +SCARV_COP_SCLASS_SHA3_X2 grok.v /^localparam SCARV_COP_SCLASS_SHA3_X2 = 5'b11010;$/;" constant line:57 +SCARV_COP_SCLASS_SHA3_X4 grok.v /^localparam SCARV_COP_SCLASS_SHA3_X4 = 5'b11100;$/;" constant line:58 +SCARV_COP_SCLASS_SHA3_YX grok.v /^localparam SCARV_COP_SCLASS_SHA3_YX = 5'b11011;$/;" constant line:59 +SCARV_COP_SCLASS_SCATTER_B grok.v /^localparam SCARV_COP_SCLASS_SCATTER_B = 5'd0 ;$/;" constant line:61 +SCARV_COP_SCLASS_GATHER_B grok.v /^localparam SCARV_COP_SCLASS_GATHER_B = 5'd1 ;$/;" constant line:62 +SCARV_COP_SCLASS_SCATTER_H grok.v /^localparam SCARV_COP_SCLASS_SCATTER_H = 5'd2 ;$/;" constant line:63 +SCARV_COP_SCLASS_GATHER_H grok.v /^localparam SCARV_COP_SCLASS_GATHER_H = 5'd3 ;$/;" constant line:64 +SCARV_COP_SCLASS_ST_W grok.v /^localparam SCARV_COP_SCLASS_ST_W = 5'd4 ;$/;" constant line:65 +SCARV_COP_SCLASS_LD_W grok.v /^localparam SCARV_COP_SCLASS_LD_W = 5'd5 ;$/;" constant line:66 +SCARV_COP_SCLASS_ST_H grok.v /^localparam SCARV_COP_SCLASS_ST_H = 5'd6 ;$/;" constant line:67 +SCARV_COP_SCLASS_LH_CR grok.v /^localparam SCARV_COP_SCLASS_LH_CR = 5'd7 ;$/;" constant line:68 +SCARV_COP_SCLASS_ST_B grok.v /^localparam SCARV_COP_SCLASS_ST_B = 5'd8 ;$/;" constant line:69 +SCARV_COP_SCLASS_LB_CR grok.v /^localparam SCARV_COP_SCLASS_LB_CR = 5'd9 ;$/;" constant line:70 +scarv_cop_cprs grok.v /^module scarv_cop_cprs ($/;" module line:81 +g_clk grok.v /^input wire g_clk , \/\/ Global clock$/;" port line:83 module:scarv_cop_cprs +g_clk_req grok.v /^output wire g_clk_req , \/\/ Clock request$/;" port line:84 module:scarv_cop_cprs +g_resetn grok.v /^input wire g_resetn , \/\/ Synchronous active low reset.$/;" port line:85 module:scarv_cop_cprs +crs1_ren grok.v /^input wire crs1_ren , \/\/ Port 1 read enable$/;" port line:91 module:scarv_cop_cprs +crs1_addr grok.v /^input wire [ 3:0] crs1_addr , \/\/ Port 1 address$/;" port line:92 module:scarv_cop_cprs +crs1_rdata grok.v /^output wire [31:0] crs1_rdata , \/\/ Port 1 read data$/;" port line:93 module:scarv_cop_cprs +crs2_ren grok.v /^input wire crs2_ren , \/\/ Port 2 read enable$/;" port line:95 module:scarv_cop_cprs +crs2_addr grok.v /^input wire [ 3:0] crs2_addr , \/\/ Port 2 address$/;" port line:96 module:scarv_cop_cprs +crs2_rdata grok.v /^output wire [31:0] crs2_rdata , \/\/ Port 2 read data$/;" port line:97 module:scarv_cop_cprs +crs3_ren grok.v /^input wire crs3_ren , \/\/ Port 3 read enable$/;" port line:99 module:scarv_cop_cprs +crs3_addr grok.v /^input wire [ 3:0] crs3_addr , \/\/ Port 3 address$/;" port line:100 module:scarv_cop_cprs +crs3_rdata grok.v /^output wire [31:0] crs3_rdata , \/\/ Port 3 read data$/;" port line:101 module:scarv_cop_cprs +crd_wen grok.v /^input wire [ 3:0] crd_wen , \/\/ Port 4 write enable$/;" port line:103 module:scarv_cop_cprs +crd_addr grok.v /^input wire [ 3:0] crd_addr , \/\/ Port 4 address$/;" port line:104 module:scarv_cop_cprs +crd_wdata grok.v /^input wire [31:0] crd_wdata \/\/ Port 4 write data$/;" port line:105 module:scarv_cop_cprs +cprs grok.v /^reg [31:0] cprs [15:0];$/;" register line:113 module:scarv_cop_cprs +i grok.v /^genvar i;$/;" register line:130 module:scarv_cop_cprs +gen_cprs grok.v /^generate for (i = 0; i < 16; i = i + 1) begin : gen_cprs$/;" block line:131 module:scarv_cop_cprs diff --git a/opengrok-indexer/src/test/resources/analysis/verilog/truncated.v b/opengrok-indexer/src/test/resources/analysis/verilog/truncated.v new file mode 100644 index 00000000000..92c47e04fee --- /dev/null +++ b/opengrok-indexer/src/test/resources/analysis/verilog/truncated.v @@ -0,0 +1 @@ + "oops this is tru \ No newline at end of file diff --git a/opengrok-indexer/src/test/resources/analysis/verilog/truncated_xref.html b/opengrok-indexer/src/test/resources/analysis/verilog/truncated_xref.html new file mode 100644 index 00000000000..6bb41e4bc20 --- /dev/null +++ b/opengrok-indexer/src/test/resources/analysis/verilog/truncated_xref.html @@ -0,0 +1,7 @@ + + + + +sampleFile - OpenGrok cross reference for /sampleFile +1 "oops this is tru +