diff --git a/.editorconfig b/.editorconfig index 25d429466d..f36e411b9b 100644 --- a/.editorconfig +++ b/.editorconfig @@ -6,8 +6,8 @@ root = true end_of_line = lf insert_final_newline = true trim_trailing_whitespace = true -max_line_length = off +max_line_length = 100 # 4 space indentation [*.{sv, svh, v, vhd}] indent_style = space -indent_size = 4 +indent_size = 2 diff --git a/.gitignore b/.gitignore index 7c8ee7b21d..a3ab691843 100644 --- a/.gitignore +++ b/.gitignore @@ -22,4 +22,12 @@ build/ *.vcd *.log *.out +*.jou +*.o +uart work-ver/* +fpga/work-fpga +stdout/ +work-dpi/ +tb/riscv-isa-sim/ +work-*/* diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index daa6a1154c..cce67309b5 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,12 +1,12 @@ before_script: - # paths to local or network installations (the riscv toolchain and + # paths to local or network installations (the riscv toolchain and # verilator are not built in the ci job as in travis) - export QUESTASIM_HOME=/usr/pack/modelsim-10.6b-kgf/questasim/ - export QUESTASIM_VERSION=-10.6b - export QUESTASIM_FLAGS=-noautoldlibpath - export CXX=g++-7.2.0 CC=gcc-7.2.0 - - export RISCV=/usr/scratch2/larain1/gitlabci/riscv_install - - export VERILATOR_ROOT=/usr/scratch2/larain1/gitlabci/verilator-3.924 + - export RISCV=/scratch2/gitlabci/riscv_install + - export VERILATOR_ROOT=/scratch2/gitlabci/verilator-3.924 # setup dependent paths - export PATH=${RISCV}/bin:$VERILATOR_ROOT/bin:${PATH} - export LIBRARY_PATH=$RISCV/lib @@ -15,16 +15,23 @@ before_script: - export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include:/usr/pack/gcc-7.2.0-af/linux-x64/include # number of parallel jobs to use for make commands and simulation - export NUM_JOBS=4 + - which java + - java -version + - which git + - git --version - ci/make-tmp.sh - - git submodule update --init --recursive - + - git submodule init + - git submodule update --recursive + variables: GIT_SUBMODULE_STRATEGY: recursive stages: - build - - test_std + - standard + - serpent +################################### # prepare build: stage: build @@ -32,29 +39,171 @@ build: - ci/build-riscv-tests.sh - ci/get-torture.sh - make clean - - make torture-gen + # this currently does not work with the current runner version... + #- make torture-gen artifacts: paths: - - tmp + - tmp + +################################### +# tests with standard cache system + +# rv64ui-p-* and rv64ui-v-* tests +asm-quest: + stage: standard + script: + - make -j${NUM_JOBS} run-asm-tests batch-mode=1 + dependencies: + - build + +amo-quest: + stage: standard + script: + - make -j${NUM_JOBS} run-amo-tests batch-mode=1 + dependencies: + - build + +bench-quest: + stage: standard + script: + - make -j${NUM_JOBS} run-benchmarks batch-mode=1 + dependencies: + - build + +# rv64ui-p-* tests +asm1-ver: + stage: standard + script: + - make -j${NUM_JOBS} run-asm-tests1-verilator + dependencies: + - build + +# rv64ui-v-* tests +asm2-ver: + stage: standard + script: + - make -j${NUM_JOBS} run-asm-tests2-verilator + dependencies: + - build + +# rv64um-*-* tests +mul-ver: + stage: standard + script: + - make -j${NUM_JOBS} run-mul-verilator + dependencies: + - build + +# atomics +amo-ver: + stage: standard + script: + - make -j${NUM_JOBS} run-amo-verilator + dependencies: + - build + +bench-ver: + stage: standard + script: + - make -j${NUM_JOBS} run-benchmarks-verilator + dependencies: + - build + +bench-ver: + stage: standard + script: + - make -j${NUM_JOBS} run-benchmarks-verilator + dependencies: + - build + +# torture: +# stage: standard +# script: +# - make torture-rtest batch-mode=1 +# - make torture-rtest-verilator +# dependencies: +# - build + +serdiv-quest: + stage: standard + script: + - cd tb/tb_serdiv/ + - make simc + - "grep 'CI: PASSED' summary.rep" + dependencies: + - build + +################################### +# tests with serpent cache system + +# rv64ui-p-* and rv64ui-v-* tests +s-asm-quest: + stage: serpent + script: + - make -j${NUM_JOBS} run-asm-tests defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1 + dependencies: + - build -# rv64ui-p-* and rv64ui-v-* tests -run-asm-tests-questa: - stage: test_std +s-bench-quest: + stage: serpent script: - - make -j${NUM_JOBS} run-asm-tests + - make -j${NUM_JOBS} run-benchmarks defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1 dependencies: - build -run-benchmarks-questa: - stage: test_std +# rv64ui-p-* tests +s-asm1-ver: + stage: serpent script: - - make -j${NUM_JOBS} run-benchmarks + - make -j${NUM_JOBS} run-asm-tests1-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS dependencies: - - build + - build + +# rv64ui-v-* tests +s-asm2-ver: + stage: serpent + script: + - make -j${NUM_JOBS} run-asm-tests2-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS + dependencies: + - build + +# rv64um-*-* tests +mul-ver: + stage: standard + script: + - make -j${NUM_JOBS} run-mul-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS + dependencies: + - build + +s-bench-ver: + stage: serpent + script: + - make -j${NUM_JOBS} run-benchmarks-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS + dependencies: + - build + +s-icache-quest: + stage: serpent + script: + - cd tb/tb_serpent_icache/ + - make simc + - "grep 'CI: PASSED' summary.rep" -torture: - stage: test_std +s-dcache-quest: + stage: serpent script: - - make torture-rtest + - cd tb/tb_serpent_dcache/ + - make simc + - "grep 'CI: PASSED' RD0_summary.rep" + - "grep 'CI: PASSED' RD1_summary.rep" + - "grep 'CI: PASSED' TB_MEM_summary.rep" dependencies: - build + +# s-torture: +# stage: serpent +# script: +# - make torture-rtest defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1 +# - make torture-rtest-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS +# dependencies: +# - build diff --git a/.gitmodules b/.gitmodules index d25c969d3f..724e91b65d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,21 +4,36 @@ [submodule "src/axi_node"] path = src/axi_node url = https://github.com/pulp-platform/axi_node.git -[submodule "src/fpu"] - path = src/fpu - url = https://github.com/pulp-platform/fpnew.git [submodule "src/fpga-support"] path = src/fpga-support url = https://github.com/pulp-platform/fpga-support.git [submodule "src/common_cells"] path = src/common_cells - url = https://github.com/pulp-platform/common_cells.git + url = https://github.com/pulp-platform/common_cells.git [submodule "src/axi"] path = src/axi url = https://github.com/pulp-platform/axi.git +[submodule "src/register_interface"] + path = src/register_interface + url = https://github.com/pulp-platform/register_interface.git +[submodule "fpga/src/apb_uart"] + path = fpga/src/apb_uart + url = https://github.com/pulp-platform/apb_uart.git +[submodule "fpga/src/apb_node"] + path = fpga/src/apb_node + url = https://github.com/pulp-platform/apb_node.git +[submodule "fpga/src/axi2apb"] + path = fpga/src/axi2apb + url = https://github.com/pulp-platform/axi2apb.git +[submodule "fpga/src/axi_slice"] + path = fpga/src/axi_slice + url = https://github.com/pulp-platform/axi_slice.git [submodule "src/fpu_div_sqrt_mvp"] path = src/fpu_div_sqrt_mvp url = https://github.com/pulp-platform/fpu_div_sqrt_mvp.git [submodule "src/tech_cells_generic"] path = src/tech_cells_generic url = https://github.com/pulp-platform/tech_cells_generic.git +[submodule "src/fpu"] + path = src/fpu + url = https://github.com/pulp-platform/fpnew.git diff --git a/.travis.yml b/.travis.yml index f98b7a6827..fb8c733eda 100644 --- a/.travis.yml +++ b/.travis.yml @@ -30,6 +30,8 @@ addons: - python-pexpect - libusb-1.0-0-dev - default-jdk + - zlib1g-dev + - valgrind env: global: - RISCV="/home/travis/riscv_install" @@ -75,26 +77,66 @@ jobs: name: run riscv benchmarks script: - ci/build-riscv-tests.sh - - make -j${NUM_JOBS} run-benchmarks-verilator + - make -j${NUM_JOBS} run-benchmarks-verilator # rv64ui-p-* tests - stage: test name: run asm tests1 script: - ci/build-riscv-tests.sh - - make -j${NUM_JOBS} run-asm-tests1-verilator + - make -j${NUM_JOBS} run-asm-tests1-verilator # rv64ui-v-* tests - stage: test name: run asm tests2 script: - ci/build-riscv-tests.sh - - make -j${NUM_JOBS} run-asm-tests2-verilator + - make -j${NUM_JOBS} run-asm-tests2-verilator + # rv64um-*-* tests + - stage: test + name: run mul tests + script: + - ci/build-riscv-tests.sh + - make -j${NUM_JOBS} run-mul-verilator + # amo tests + - stage: test + name: run amo tests + script: + - ci/build-riscv-tests.sh + - make -j${NUM_JOBS} run-amo-verilator - stage: test name: run torture script: - ci/get-torture.sh - make clean - make torture-gen - - make torture-rtest-verilator + - make torture-rtest-verilator + + - stage: test + name: run riscv benchmarks (serpent) + script: + - ci/build-riscv-tests.sh + - make -j${NUM_JOBS} run-benchmarks-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS + # rv64ui-p-* tests + - stage: test + name: run asm tests1 (serpent) + script: + - ci/build-riscv-tests.sh + - make -j${NUM_JOBS} run-asm-tests1-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS + # rv64ui-v-* tests + - stage: test + name: run asm tests2 (serpent) + script: + - ci/build-riscv-tests.sh + - make -j${NUM_JOBS} run-asm-tests2-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS + + - stage: test + name: run torture (serpent) + script: + - ci/get-torture.sh + - make clean + - make torture-gen defines=PITON_ARIANE+AXI64_CACHE_PORTS + - make torture-rtest-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS + + # extra time during long builds install: travis_wait diff --git a/Bender.yml b/Bender.yml index 5b169a76d1..a6b8f15926 100644 --- a/Bender.yml +++ b/Bender.yml @@ -7,7 +7,7 @@ dependencies: axi_mem_if: { git: "https://github.com/pulp-platform/axi_mem_if.git", version: 0.2.0 } axi_node: { git: "https://github.com/pulp-platform/axi_node.git", version: 1.1.1 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.1.1 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.7.5 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.8.0 } fpga-support: { git: "https://github.com/pulp-platform/fpga-support.git", version: 0.3.2 } sources: @@ -73,10 +73,10 @@ sources: - src/issue_read_operands.sv - src/issue_stage.sv - src/load_unit.sv - - src/lsu_arbiter.sv - - src/lsu.sv + - src/load_store_unit.sv - src/mmu.sv - src/mult.sv + - src/serdiv.sv - src/perf_counters.sv - src/ptw.sv - src/ariane_regfile_ff.sv diff --git a/CHANGELOG.md b/CHANGELOG.md index 483e014ede..9a2a96e955 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,10 +6,25 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## [Unreleased] +### 4.0.0 + ### Added +- Preliminary support for A-Extension +- Preliminary FP support +- Preliminary support for OpenPiton cache system - Commit log feature -- Support for A-Extension +- Provisioned `aw_top` signal for close to memory atomics +- FPGA Support +- Misc bug-fixes +- Platform Level Interrupt Controller (PLIC) +- FPGA Bootrom with capability to boot from SD Card + +### Changed + +- core_id / cluster_id inputs have been merged to hard_id input (interface changes) +- The three AXI ports have been merged into one (interface changes) +- [Bugfix] Wrong flagging of memory in machine mode if high bits (63-38) are not equal #136 ### 3.0.0 diff --git a/Flist.ariane b/Flist.ariane new file mode 100644 index 0000000000..70f8bc7f6d --- /dev/null +++ b/Flist.ariane @@ -0,0 +1,157 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: File list for OpenPiton flow +// src/fpu_div_sqrt_mvp/hdl/fpu_ff.sv +// src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv +// src/fpu_div_sqrt_mvp/hdl/control_mvp.sv +// src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv +// src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv +// src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv +// src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv +// src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv +// src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv +// src/fpu/src/pkg/fpnew_pkg.vhd +// src/fpu/src/pkg/fpnew_fmts_pkg.vhd +// src/fpu/src/pkg/fpnew_comps_pkg.vhd +// src/fpu/src/pkg/fpnew_pkg_constants.vhd +// src/fpu/src/utils/fp_pipe.vhd +// src/fpu/src/utils/fp_rounding.vhd +// src/fpu/src/utils/fp_arbiter.vhd +// src/fpu/src/ops/fma_core.vhd +// src/fpu/src/ops/fp_fma.vhd +// src/fpu/src/ops/fp_divsqrt_multi.vhd +// src/fpu/src/ops/fp_noncomp.vhd +// src/fpu/src/ops/fp_f2fcasts_fmt.vhd +// src/fpu/src/ops/fp_f2icasts_fmt.vhd +// src/fpu/src/ops/fp_i2fcasts_fmt.vhd +// src/fpu/src/subunits/addmul_fmt_slice.vhd +// src/fpu/src/subunits/addmul_block.vhd +// src/fpu/src/subunits/divsqrt_multifmt_slice.vhd +// src/fpu/src/subunits/divsqrt_block.vhd +// src/fpu/src/subunits/noncomp_fmt_slice.vhd +// src/fpu/src/subunits/noncomp_block.vhd +// src/fpu/src/subunits/conv_fmt_slice.vhd +// src/fpu/src/subunits/conv_ifmt_slice.vhd +// src/fpu/src/subunits/conv_block.vhd +// src/fpu/src/fpnew.vhd +// src/fpu/src/fpnew_top.vhd +src/axi/src/axi_pkg.sv +src/debug/dm_pkg.sv +include/riscv_pkg.sv +include/ariane_pkg.sv +include/ariane_axi_pkg.sv +include/serpent_cache_pkg.sv +//include/std_cache_pkg.sv +include/axi_intf.sv +src/util/instruction_tracer_pkg.sv +src/util/instruction_tracer_if.sv +src/util/sram.sv +src/util/axi_master_connect.sv +src/util/axi_master_connect_rev.sv +src/util/axi_slave_connect.sv +src/util/axi_slave_connect_rev.sv +src/common_cells/src/fifo_v1.sv +src/common_cells/src/fifo_v2.sv +src/common_cells/src/fifo_v3.sv +src/common_cells/src/lfsr_8bit.sv +src/common_cells/src/lzc.sv +src/common_cells/src/rrarbiter.sv +src/common_cells/src/rstgen_bypass.sv +src/common_cells/src/sync_wedge.sv +src/common_cells/src/cdc_2phase.sv +src/common_cells/src/pipe_reg_simple.sv +src/fpga-support/rtl/SyncSpRamBeNx64.sv +src/axi_mem_if/src/axi2mem.sv +src/tech_cells_generic/src/cluster_clock_inverter.sv +src/tech_cells_generic/src/pulp_clock_mux2.sv +src/axi_adapter.sv +src/alu.sv +src/fpu_wrap.sv +src/ariane.sv +src/branch_unit.sv +src/compressed_decoder.sv +src/controller.sv +src/csr_buffer.sv +src/csr_regfile.sv +src/decoder.sv +src/ex_stage.sv +src/frontend/btb.sv +src/frontend/bht.sv +src/frontend/ras.sv +src/frontend/instr_scan.sv +src/frontend/frontend.sv +src/id_stage.sv +src/instr_realigner.sv +src/issue_read_operands.sv +src/issue_stage.sv +src/load_unit.sv +src/load_store_unit.sv +src/mmu.sv +src/mult.sv +src/multiplier.sv +src/serdiv.sv +src/perf_counters.sv +src/ptw.sv +src/ariane_regfile_ff.sv +src/re_name.sv +src/scoreboard.sv +src/store_buffer.sv +src/amo_buffer.sv +src/store_unit.sv +src/tlb.sv +src/commit_stage.sv +src/cache_subsystem/serpent_dcache_ctrl.sv +src/cache_subsystem/serpent_dcache_mem.sv +src/cache_subsystem/serpent_dcache_missunit.sv +src/cache_subsystem/serpent_dcache_wbuffer.sv +src/cache_subsystem/serpent_dcache.sv +src/cache_subsystem/serpent_icache.sv +src/cache_subsystem/serpent_l15_adapter.sv +src/cache_subsystem/serpent_cache_subsystem.sv +src/debug/debug_rom/debug_rom.sv +src/debug/dm_csrs.sv +src/clint/clint.sv +src/clint/axi_lite_interface.sv +src/debug/dm_mem.sv +src/debug/dm_top.sv +src/debug/dmi_cdc.sv +src/debug/dmi_jtag.sv +src/debug/dm_sba.sv +src/debug/dmi_jtag_tap.sv +openpiton/ariane_verilog_wrap.sv +openpiton/serpent_peripherals.sv +bootrom/bootrom.sv +src/plic/plic.sv +src/plic/plic_claim_complete_tracker.sv +src/plic/plic_comparator.sv +src/plic/plic_find_max.sv +src/plic/plic_gateway.sv +src/plic/plic_interface.sv +src/plic/plic_target_slice.sv +fpga/src/axi2apb/src/axi2apb_wrap.sv +fpga/src/axi2apb/src/axi2apb.sv +fpga/src/axi2apb/src/axi2apb_64_32.sv +fpga/src/axi_slice/src/axi_w_buffer.sv +fpga/src/axi_slice/src/axi_b_buffer.sv +fpga/src/axi_slice/src/axi_slice_wrap.sv +fpga/src/axi_slice/src/axi_slice.sv +fpga/src/axi_slice/src/axi_single_slice.sv +fpga/src/axi_slice/src/axi_ar_buffer.sv +fpga/src/axi_slice/src/axi_r_buffer.sv +fpga/src/axi_slice/src/axi_aw_buffer.sv +src/register_interface/src/apb_to_reg.sv +src/register_interface/src/reg_intf.sv \ No newline at end of file diff --git a/Makefile b/Makefile old mode 100755 new mode 100644 index 60c36208e9..dfa15ec96a --- a/Makefile +++ b/Makefile @@ -25,7 +25,12 @@ defines ?= # test name for torture runs (binary name) test-location ?= output/test # set to either nothing or -log -torture-logs := -log +torture-logs := +# custom elf bin to run with sim or sim-verilator +elf-bin ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv +# root path +mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) +root-dir := $(dir $(mkfile_path)) ifndef RISCV $(error RISCV not set - please point your RISCV variable to your RISCV installation) @@ -37,27 +42,38 @@ ariane_pkg := include/riscv_pkg.sv \ src/debug/dm_pkg.sv \ include/ariane_pkg.sv \ include/std_cache_pkg.sv \ + include/serpent_cache_pkg.sv \ src/axi/src/axi_pkg.sv \ + src/register_interface/src/reg_intf.sv \ include/axi_intf.sv \ + tb/ariane_soc_pkg.sv \ + include/ariane_axi_pkg.sv \ src/fpu/src/pkg/fpnew_pkg.vhd \ src/fpu/src/pkg/fpnew_fmts_pkg.vhd \ src/fpu/src/pkg/fpnew_comps_pkg.vhd \ src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \ src/fpu/src/pkg/fpnew_pkg_constants.vhd +ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg)) # utility modules util := $(wildcard src/util/*.svh) \ src/util/instruction_tracer_pkg.sv \ src/util/instruction_tracer_if.sv \ src/tech_cells_generic/src/cluster_clock_gating.sv \ + tb/common/mock_uart.sv \ src/util/sram.sv - +util := $(addprefix $(root-dir), $(util)) # Test packages test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \ $(wildcard tb/test/*/*_pkg.sv*) # DPI dpi := $(patsubst tb/dpi/%.cc,${dpi-library}/%.o,$(wildcard tb/dpi/*.cc)) dpi_hdr := $(wildcard tb/dpi/*.h) +dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr)) +CFLAGS := -I$(QUESTASIM_HOME)/include \ + -Itb/riscv-isa-sim/install/include/spike \ + -std=c++11 -I../tb/dpi + # this list contains the standalone components src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ $(wildcard src/fpu/src/utils/*.vhd) \ @@ -66,65 +82,126 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ $(filter-out src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \ $(wildcard src/fpu_div_sqrt_mvp/hdl/*.sv)) \ $(wildcard src/frontend/*.sv) \ - $(wildcard src/cache_subsystem/*.sv) \ + $(filter-out src/cache_subsystem/std_no_dcache.sv, \ + $(wildcard src/cache_subsystem/*.sv)) \ $(wildcard bootrom/*.sv) \ $(wildcard src/clint/*.sv) \ + $(wildcard fpga/src/axi2apb/src/*.sv) \ + $(wildcard fpga/src/axi_slice/src/*.sv) \ + $(wildcard src/plic/*.sv) \ $(wildcard src/axi_node/src/*.sv) \ $(wildcard src/axi_mem_if/src/*.sv) \ $(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \ $(wildcard src/debug/debug_rom/*.sv) \ + src/register_interface/src/apb_to_reg.sv \ + src/axi/src/axi_multicut.sv \ src/fpu/src/fpnew.vhd \ src/fpu/src/fpnew_top.vhd \ src/common_cells/src/deprecated/generic_fifo.sv \ src/common_cells/src/deprecated/pulp_sync.sv \ src/common_cells/src/deprecated/find_first_one.sv \ src/common_cells/src/rstgen_bypass.sv \ + src/common_cells/src/rstgen.sv \ + src/common_cells/src/stream_mux.sv \ + src/common_cells/src/stream_demux.sv \ + src/common_cells/src/stream_arbiter.sv \ + src/util/axi_master_connect.sv \ + src/util/axi_slave_connect.sv \ + src/util/axi_master_connect_rev.sv \ + src/util/axi_slave_connect_rev.sv \ src/axi/src/axi_cut.sv \ src/axi/src/axi_join.sv \ + src/axi/src/axi_delayer.sv \ + src/axi/src/axi_to_axi_lite.sv \ src/fpga-support/rtl/SyncSpRamBeNx64.sv \ src/common_cells/src/sync.sv \ src/common_cells/src/cdc_2phase.sv \ src/common_cells/src/spill_register.sv \ src/common_cells/src/sync_wedge.sv \ + src/common_cells/src/edge_detect.sv \ + src/common_cells/src/fifo_v3.sv \ src/common_cells/src/fifo_v2.sv \ src/common_cells/src/fifo_v1.sv \ src/common_cells/src/lzc.sv \ src/common_cells/src/rrarbiter.sv \ + src/common_cells/src/ready_valid_delay.sv \ src/common_cells/src/lfsr_8bit.sv \ + src/common_cells/src/lfsr_16bit.sv \ + src/common_cells/src/counter.sv \ + src/common_cells/src/pipe_reg_simple.sv \ src/tech_cells_generic/src/cluster_clock_inverter.sv \ src/tech_cells_generic/src/pulp_clock_mux2.sv \ tb/ariane_testharness.sv \ + tb/ariane_peripherals.sv \ + tb/common/uart.sv \ tb/common/SimDTM.sv \ tb/common/SimJTAG.sv -# root path -root-dir := $(shell pwd) +src := $(addprefix $(root-dir), $(src)) + +uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd) +uart_src := $(addprefix $(root-dir), $(uart_src)) + +fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) +fpga_src := $(addprefix $(root-dir), $(fpga_src)) + # look for testbenches tbs := tb/ariane_tb.sv tb/ariane_testharness.sv # RISCV asm tests and benchmark setup (used for CI) # there is a definesd test-list with selected CI tests -riscv-test-dir := tmp/riscv-tests/build/isa/ -riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/ -riscv-asm-tests-list := ci/riscv-asm-tests.list -riscv-benchmarks-list := ci/riscv-benchmarks.list -riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-) -riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-) -# preset which runs a single test -riscv-test ?= rv64ui-p-add +riscv-test-dir := tmp/riscv-tests/build/isa/ +riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/ +riscv-asm-tests-list := ci/riscv-asm-tests.list +riscv-amo-tests-list := ci/riscv-amo-tests.list +riscv-mul-tests-list := ci/riscv-mul-tests.list +riscv-benchmarks-list := ci/riscv-benchmarks.list +riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-) +riscv-amo-tests := $(shell xargs printf '\n%s' < $(riscv-amo-tests-list) | cut -b 1-) +riscv-mul-tests := $(shell xargs printf '\n%s' < $(riscv-mul-tests-list) | cut -b 1-) +riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-) # Search here for include files (e.g.: non-standalone components) incdir := # Compile and sim flags -compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines) +compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines) +uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW +questa-flags += -t 1ns -64 -coverage -classdebug $(gui-sim) $(QUESTASIM_FLAGS) compile_flag_vhd += -64 -nologo -quiet -2008 -uvm-flags += +UVM_NO_RELNOTES + # Iterate over all include directories and write them with +incdir+ prefixed # +incdir+ works for Verilator and QuestaSim list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir)) # RISCV torture setup riscv-torture-dir := tmp/riscv-torture -riscv-torture-bin := java -Xmx1G -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar +# old java flags -Xmx1G -Xss8M -XX:MaxPermSize=128M +# -XshowSettings -Xdiag +riscv-torture-bin := java -jar sbt-launch.jar + +# if defined, calls the questa targets in batch mode +ifdef batch-mode + questa-flags += -c + questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" + questa-cmd += -do " log -r /*; run -all;" +else + questa-cmd := -do " log -r /*; run -all;" +endif +# we want to preload the memories +ifdef preload + questa-cmd += +PRELOAD=$(preload) + elf-bin = none + # tandem verify with spike, this requires pre-loading + ifdef tandem + compile_flag += +define+TANDEM + questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so + endif +endif +# remote bitbang is enabled +ifdef rbb + questa-cmd += +jtag_rbb_enable=1 +else + questa-cmd += +jtag_rbb_enable=0 +endif # Build the TB and module using QuestaSim build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so @@ -132,78 +209,83 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ari vopt$(questa_version) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis # src files -$(library)/.build-srcs: $(ariane_pkg) $(util) $(src) $(library) +$(library)/.build-srcs: $(util) $(library) vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583 vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg)) vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583 # Suppress message that always_latch may not be checked thoroughly by QuestaSim. + vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src)) vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src)) vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583 touch $(library)/.build-srcs # build TBs -$(library)/.build-tb: $(dpi) $(tbs) +$(library)/.build-tb: $(dpi) # Compile top level - vlog$(questa_version) -sv $(tbs) -work $(library) + vlog$(questa_version) $(compile_flag) -sv $(tbs) -work $(library) touch $(library)/.build-tb $(library): - vlib${questa_version} ${library} + vlib${questa_version} $(library) # compile DPIs $(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr) mkdir -p $(dpi-library) - $(CXX) -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o $@ $< + $(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@ $(dpi-library)/ariane_dpi.so: $(dpi) mkdir -p $(dpi-library) # Compile C-code and generate .so file $(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -lfesvr +# single test runs on Questa can be started by calling make , e.g. make towers.riscv +# the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list +# if you want to run in batch mode, use make batch-mode=1 +# alternatively you can call make sim elf-bin= in order to load an arbitrary binary sim: build - vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; log -r /*; run -all; exit" \ - ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options) - -simc: build - vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all; exit" \ - ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options) - -simc-log: build - vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; log -r /*; run -all; exit" \ - ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options) + vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + +BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log $(riscv-asm-tests): build - vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ - -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ - ${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log + vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log + +$(riscv-amo-tests): build + vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log + +$(riscv-mul-tests): build + vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + +BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log $(riscv-benchmarks): build - vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ - -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ - ${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log + vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \ + +BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log # can use -jX to run ci tests in parallel using X processes run-asm-tests: $(riscv-asm-tests) $(MAKE) check-asm-tests +run-amo-tests: $(riscv-amo-tests) + $(MAKE) check-amo-tests + +run-mul-tests: $(riscv-mul-tests) + $(MAKE) check-mul-tests + check-asm-tests: ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }') +check-amo-tests: + ci/check-tests.sh tmp/riscv-amo-tests- $(shell wc -l $(riscv-amo-tests-list) | awk -F " " '{ print $1 }') + +check-mul-tests: + ci/check-tests.sh tmp/riscv-mul-tests- $(shell wc -l $(riscv-mul-tests-list) | awk -F " " '{ print $1 }') + # can use -jX to run ci tests in parallel using X processes run-benchmarks: $(riscv-benchmarks) $(MAKE) check-benchmarks @@ -231,29 +313,43 @@ verilate_command := $(verilator) -Wno-lint \ $(if $(DEBUG),--trace-structs --trace,) \ -LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr" \ - -CFLAGS "-std=c++11 -I../tb/dpi" -Wall --cc --vpi \ + -CFLAGS "$(CFLAGS)" -Wall --cc --vpi \ $(list_incdir) --top-module ariane_testharness \ --Mdir $(ver-library) -O3 \ - --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc + --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \ + tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc # User Verilator, at some point in the future this will be auto-generated verilate: + @echo "[Verilator] Building Model" $(verilate_command) cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk +sim-verilator: verilate + $(ver-library)/Variane_testharness $(elf-bin) + $(addsuffix -verilator,$(riscv-asm-tests)): verilate $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@) -run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) +$(addsuffix -verilator,$(riscv-amo-tests)): verilate + $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@) + +$(addsuffix -verilator,$(riscv-mul-tests)): verilate + $(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@) + +$(addsuffix -verilator,$(riscv-benchmarks)): verilate + $(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@) + +run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(riscv-mul-tests)) # split into two halfs for travis jobs (otherwise they will time out) run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% ,$(riscv-asm-tests))) run-asm-tests2-verilator: $(addsuffix -verilator, $(filter-out rv64ui-v-% ,$(riscv-asm-tests))) +run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests)) -$(addsuffix -verilator,$(riscv-benchmarks)): verilate - $(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@) +run-mul-verilator: $(addsuffix -verilator, $(riscv-mul-tests)) run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks)) @@ -265,43 +361,35 @@ torture-itest: cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S' torture-rtest: build - cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) defines=$(defines) test-location=$(test-location)" > call.sh && chmod +x call.sh + cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=$(test-location)" > call.sh && chmod +x call.sh cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a $(test-location).S' | tee $(test-location).log make check-torture test-location=$(test-location) torture-dummy: build - cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture defines=$(defines) test-location=\$${@: -1}" > call.sh + cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh torture-rnight: build - cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) defines=$(defines) test-location=\$${@: -1}" > call.sh && chmod +x call.sh + cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh && chmod +x call.sh cd $(riscv-torture-dir) && $(riscv-torture-bin) 'overnight/run -r ./call.sh -g none' | tee output/overnight.log $(MAKE) check-torture torture-rtest-verilator: verilate - cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture-verilator defines=$(defines)" > call.sh && chmod +x call.sh + cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture-verilator batch-mode=1 defines=$(defines)" > call.sh && chmod +x call.sh cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log $(MAKE) check-torture run-torture: build - vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-torture-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ - -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ - ${top_level}_optimized +permissive-off \ - +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options) + vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \ + +BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options) run-torture-log: build - vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \ - +BASEDIR=$(riscv-torture-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \ - $(QUESTASIM_FLAGS) \ - -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ - -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; log -r /*; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \ - ${top_level}_optimized +permissive-off \ - +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options) + vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \ + +BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ + ${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options) cp vsim.wlf $(riscv-torture-dir)/$(test-location).wlf - cp trace_core_00_0.log $(riscv-torture-dir)/$(test-location).trace - cp trace_core_00_0_commit.log $(riscv-torture-dir)/$(test-location).commit + cp trace_hart_0000.log $(riscv-torture-dir)/$(test-location).trace + cp trace_hart_0000_commit.log $(riscv-torture-dir)/$(test-location).commit cp transcript $(riscv-torture-dir)/$(test-location).transcript run-torture-verilator: verilate @@ -311,13 +399,25 @@ check-torture: grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig +fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(util) $(uart_src) + @echo "[FPGA] Generate sources" + @echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl + @echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl + @echo read_verilog -sv {$(util)} >> fpga/scripts/add_sources.tcl + @echo read_verilog -sv {$(src)} >> fpga/scripts/add_sources.tcl + @echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl + @echo "[FPGA] Generate Bitstream" + cd fpga && make BOARD="genesys2" XILINX_PART="xc7k325tffg900-2" XILINX_BOARD="digilentinc.com:genesys2:part0:1.1" CLK_PERIOD_NS="20" + +.PHONY: fpga + clean: rm -rf $(riscv-torture-dir)/output/test* rm -rf $(library)/ $(dpi-library)/ $(ver-library)/ rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb .PHONY: - build sim simc verilate clean \ + build sim sim-verilate clean \ $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \ $(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) \ check-benchmarks check-asm-tests \ diff --git a/README.md b/README.md index 766e0dcfd0..8f36fd891d 100644 --- a/README.md +++ b/README.md @@ -8,10 +8,32 @@ It has configurable size, separate TLBs, a hardware PTW and branch-prediction (b ![](docs/img/ariane_overview.png) -## Getting Started +Table of Contents +================= + + * [Ariane RISC-V CPU](#ariane-risc-v-cpu) + * [Table of Contents](#table-of-contents) + * [Getting Started](#getting-started) + * [Running User-Space Applications](#running-user-space-applications) + * [FPU Support](#fpu-support) + * [FPGA Emulation](#fpga-emulation) + * [Programming the Memory Configuration File](#programming-the-memory-configuration-file) + * [Preparing the SD Card](#preparing-the-sd-card) + * [Generating a Bitstream](#generating-a-bitstream) + * [Debugging](#debugging) + * [Preliminary Support for OpenPiton Cache System](#preliminary-support-for-openpiton-cache-system) + * [Planned Improvements](#planned-improvements) + * [Going Beyond](#going-beyond) + * [CI Testsuites and Randomized Constrained Testing with Torture](#ci-testsuites-and-randomized-constrained-testing-with-torture) + * [Re-generating the Bootcode (ZSBL)](#re-generating-the-bootcode-zsbl) + * [Contributing](#contributing) + * [Acknowledgements](#acknowledgements) + +Created by [gh-md-toc](https://github.com/ekalinin/github-markdown-toc) +## Getting Started -Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools). Make sure that your `RISCV` environment variable points to your RISC-V installation (see the RISC-V tools and related projects for futher information). +Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools). Make sure that your `RISCV` environment variable points to your RISC-V installation (see the RISC-V tools and related projects for further information). Checkout the repository and initialize all submodules ``` @@ -19,12 +41,11 @@ $ git clone https://github.com/pulp-platform/ariane.git $ git submodule update --init --recursive ``` -The testbench relies on `riscv-fesvr` which can be found [here](https://github.com/riscv/riscv-fesvr). Follow the README there and make sure that your compiler and linker is aware of the library (e.g.: add it to your path if it is in a non-default directory). - Build the Verilator model of Ariane by using the Makefile: ``` $ make verilate ``` + To build the verilator model with support for vcd files run ``` $ make verilate DEBUG=1 @@ -41,7 +62,7 @@ The Verilator testbench makes use of the `riscv-fesvr`. This means that you can Both, the Verilator model as well as the Questa simulation will produce trace logs. The Verilator trace is more basic but you can feed the log to `spike-dasm` to resolve instructions to mnemonics. Unfortunately value inspection is currently not possible for the Verilator trace file. ``` -$ spike-dasm < trace_core_00_0.dasm > logfile.txt +$ spike-dasm < trace_hart_00_0.dasm > logfile.txt ``` ### Running User-Space Applications @@ -76,7 +97,7 @@ $ work-ver/Variane_testharness $RISCV/riscv64-unknown-elf/bin/pk hello.elf If you want to use QuestaSim to run it you can use the following command: ``` -$ make simc riscv-test-dir=$RISCV/riscv64-unknown-elf/bin riscv-test=pk target-options=hello.elf +$ make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf batch-mode=1 ``` > Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files. @@ -87,11 +108,142 @@ $ make simc riscv-test-dir=$RISCV/riscv64-unknown-elf/bin riscv-test=pk target-o ## FPGA Emulation -Coming. +We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/pulp-platform/ariane/releases). + +Tested on Vivado 2018.2. The FPGA SoC currently contains the following peripherals: + +- DDR3 memory controller +- SPI controller to conncet to an SDCard +- Ethernet controller +- JTAG port (see debugging section below) +- Bootrom containing zero stage bootloader and device tree. + +![](docs/img/fpga_bd.png) + +> The ethernet controller and the corresponding network connection is still work in progress and not functional at the moment. Expect some updates soon-ish. + +### Programming the Memory Configuration File + +- Open Vivado +- Open the hardware manager and open the target board (Genesys II - `xc7k325t`) +- Tools - Add Configuration Memory Device +- Select the following Spansion SPI flash `s25fl256xxxxxx0` +- Add `ariane_xilinx.mcs` +- Press Ok. Flashing will take a couple of minutes. +- Right click on the FPGA device - Boot from Configuration Memory Device (or press the program button on the FPGA) + +### Preparing the SD Card + +The first stage bootloader will boot from SD Card by default. Get yourself a suitable SD Card (we use [this](https://www.amazon.com/Kingston-Digital-Mobility-MBLY10G2-32GB/dp/B00519BEQO) one). Either grab a pre-built Linux image from [here](https://github.com/pulp-platform/ariane-sdk/releases) or generate the Linux image yourself following the README in the [ariane-sdk repository](https://github.com/pulp-platform/ariane-sdk). Prepare the SD Card by following the "Booting from SD card" section in the ariane-sdk repository. + +Connect a terminal to the USB serial device opened by the FTDI chip e.g.: +``` +$ screen /dev/ttyUSB0 115200 +``` + +Default baudrate set by the bootlaoder and Linux is `115200`. + +After you've inserted the SD Card and programmed the FPGA you can connect to the serial port of the FPGA and should see the bootloader and afterwards Linux booting. Default username is `root`, no password required. + +### Generating a Bitstream + +To generate the FPGA bitstream (and memory configuration) yourself for the Genesys II board run: + +``` +$ make fpga +``` + +This will produce a bitstream file and memory configuration file (in `fpga/work-fpga`) which you can permanently flash by running the above commands. + +### Debugging + +You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD, both to be used with Olimex Debug adapter. The JTAG port is mapped to PMOD `JC` on the Genesys 2 board. You will need to connect the following wires to your debug adapter: + +![](https://reference.digilentinc.com/_media/genesys2/fig_16.png) + +| Pin | Nr. | +|----------|-----| +| `tck` | JC1 | +| `tdi` | JC2 | +| `tdo` | JC3 | +| `tms` | JC4 | +| `trst_n` | JC7 | + + +``` +$ openocd -f fpga/ariane_tiny.cfg +Open On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32) +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +adapter speed: 1000 kHz +Info : auto-selecting first available session transport "jtag". To override use 'transport select '. +Info : clock speed 1000 kHz +Info : TAP riscv.cpu does not have IDCODE +Info : datacount=2 progbufsize=12 +Info : Examined RISC-V core; found 1 harts +Info : hart 0: XLEN=64, misa=0x8000000000141105 +Info : Listening on port 3333 for gdb connections +Ready for Remote Connections +Info : Listening on port 6666 for tcl connections +Info : Listening on port 4444 for telnet connections +Info : accepting 'gdb' connection on tcp/3333 +``` + +Then you will be able to either connect through `telnet` or with `gdb`: + +``` +$ riscv64-unknown-elf-gdb /path/to/elf +(gdb) target remote localhost:3333 +(gdb) load +Loading section .text, size 0x6508 lma 0x80000000 +Loading section .rodata, size 0x900 lma 0x80006508 +(gdb) b putchar +(gdb) c +Continuing. + +Program received signal SIGTRAP, Trace/breakpoint trap. +0x0000000080009126 in putchar (s=72) at lib/qprintf.c:69 +69 uart_sendchar(s); +(gdb) si +0x000000008000912a 69 uart_sendchar(s); +(gdb) p/x $mepc +$1 = 0xfffffffffffdb5ee +``` + +You can read or write device memory by using: +``` +(gdb) x/i 0x1000 + 0x1000: lui t0,0x4 +(gdb) set {int} 0x1000 = 22 +(gdb) set $pc = 0x1000 +``` + +If you are on an Ubuntu based system you need to add the following udev rule to `/etc/udev/rules.d/olimex-arm-usb-tiny-h.rules` + +>``` +> SUBSYSTEM=="usb", ACTION=="add", ATTRS{idProduct}=="002a", ATTRS{idVendor}=="15ba", MODE="664", GROUP="plugdev" +>``` + +### Preliminary Support for OpenPiton Cache System + +Ariane has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/serpent_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics. + +The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the README in that repository to see how to use Ariane in the OpenPiton setting. + +To activate the different cache system, compile your code with the macro `PITON_ARIANE`. + +> For testing purposes, this L1 cache subsystem also supports AXI memory plugs in order to verify it within the Ariane CI environment. In order to use this feature, the macro `AXI64_CACHE_PORTS` has to be defined. Note however, that atomics are not supported in this configuration. + +> Note that OpenPiton support is currently WIP, and although simple C programs run on one or several OpenPiton tiles, advanced features such as cache coherency are not fully verified yet. + +Also, we are working on SMP Linux support on that platform - stay tuned! ## Planned Improvements -> Atomics are implemented for a single core environment. They will semantically fail in a multi-core setup. +Check-out the issue tab which also loosely tracks planned improvements. + +> Atomics are implemented for a single core environment. They will semantically fail in a multi-core setup (unless you are using the serpent flavor of Ariane in combination with the OpenPiton cache subsystem, see previous section). ## Going Beyond @@ -99,10 +251,10 @@ The core has been developed with a full licensed version of QuestaSim. If you ha To specify the test to run use (e.g.: you want to run `rv64ui-p-sraw` inside the `tmp/risc-tests/build/isa` folder: ``` -$ make sim riscv-test=tmp/risc-tests/build/isa/rv64ui-p-sraw +$ make sim elf-bin=path/to/rv64ui-p-sraw ``` -If you call `simc` instead of `sim` it will run without the GUI. QuestaSim uses `riscv-fesvr` for communication as well. +If you call `sim` with `batch-mode=1` it will run without the GUI. QuestaSim uses `riscv-fesvr` for communication as well. ### CI Testsuites and Randomized Constrained Testing with Torture @@ -132,7 +284,8 @@ Ariane can dump a trace-log in Questa which can be easily diffed against Spike w ```verilog localparam bit ENABLE_SPIKE_COMMIT_LOG = 1'b1; ``` -This will dump a file called `trace_core_*_*_commit.log`. +This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file. +This will dump a file called `trace_hart_*_*_commit.log`. This can be helpful for debugging long traces (e.g.: torture traces). To compile Spike with the commit log feature do: @@ -145,7 +298,32 @@ $ make $ [sudo] make install ``` + + +### Re-generating the Bootcode (ZSBL) + +The zero stage bootloader (ZSBL) for RTL simulation lives in `bootrom/` while the bootcode for the FPGA is in `fpga/src/bootrom`. The RTL bootcode simply jumps to the base of the DRAM where the FSBL takes over. For the FPGA the ZSBL performs additional housekeeping. Both bootloader pass the hartid as well as address to the device tree in argumen register `a0` and `a1` respectively. + +To re-generate the bootcode you can use the existing makefile within those directories. To generate the SystemVerilog files you will need the `bitstring` python package installed on your system. + # Contributing Check out the [contribution guide](CONTRIBUTING.md) +# Acknowledgements + +Thanks to Gian Marti, Thomas Kramer and Thomas E. Benz for implementing the PLIC. diff --git a/bootrom/.gitignore b/bootrom/.gitignore index 509925305d..b553ec26ea 100644 --- a/bootrom/.gitignore +++ b/bootrom/.gitignore @@ -1 +1,3 @@ *.elf +*.img +*.dtb diff --git a/bootrom/Makefile b/bootrom/Makefile index 99b5460097..faedc68d9f 100644 --- a/bootrom/Makefile +++ b/bootrom/Makefile @@ -1,8 +1,9 @@ -bootrom_img = bootrom.img +bootrom_img = bootrom.img bootrom.sv GCC=riscv64-unknown-elf-gcc OBJCOPY=riscv64-unknown-elf-objcopy DTB=ariane.dtb +PYTHON=python all: $(bootrom_img) @@ -18,5 +19,8 @@ all: $(bootrom_img) %.dtb: %.dts dtc -I dts $< -O dtb -o $@ +%.sv: %.img + $(PYTHON) ./gen_rom.py $< + clean: rm $(bootrom_img) $(DTB) diff --git a/bootrom/ariane.dts b/bootrom/ariane.dts index 7519ac1437..7ceb4bc1f8 100644 --- a/bootrom/ariane.dts +++ b/bootrom/ariane.dts @@ -5,18 +5,23 @@ #size-cells = <2>; compatible = "eth,ariane-bare-dev"; model = "eth,ariane-bare"; + // chosen { + // stdout-path = "/soc/uart@10000000:115200"; + // }; cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <10000000>; + timebase-frequency = <32768>; // 32.768 kHz CPU0: cpu@0 { + clock-frequency = <50000000>; // 50 MHz device_type = "cpu"; reg = <0>; status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imc"; + compatible = "eth, ariane", "riscv"; + riscv,isa = "rv64imacsu"; mmu-type = "riscv,sv39"; - clock-frequency = <1000000000>; + tlb-split; + // HLIC - hart local interrupt controller CPU0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; @@ -26,7 +31,7 @@ }; memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x1000000>; + reg = <0x0 0x80000000 0x0 0x1800000>; }; soc { #address-cells = <2>; @@ -35,11 +40,35 @@ ranges; clint@2000000 { compatible = "riscv,clint0"; - interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>; reg = <0x0 0x2000000 0x0 0xc0000>; + reg-names = "control"; + }; + PLIC0: interrupt-controller@c000000 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0", "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <2>; + }; + debug-controller@0 { + compatible = "riscv,debug-013"; + interrupts-extended = <&CPU0_intc 65535>; + reg = <0x0 0x0 0x0 0x1000>; + reg-names = "control"; + }; + uart@10000000 { + compatible = "ns16750"; + reg = <0x0 0x10000000 0x0 0x1000>; + clock-frequency = <50000000>; + current-speed = <115200>; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <2>; // regs are spaced on 32 bit boundary + reg-io-width = <4>; // only 32-bit access are supported }; - }; - htif { - compatible = "ucb,htif0"; }; }; diff --git a/bootrom/bootrom.h b/bootrom/bootrom.h new file mode 100644 index 0000000000..8814605688 --- /dev/null +++ b/bootrom/bootrom.h @@ -0,0 +1,458 @@ +// Auto-generated code + +const int reset_vec_size = 452; + +uint32_t reset_vec[reset_vec_size] = { + 0x0010041b, + 0x01f41413, + 0xf1402573, + 0x00000597, + 0x07458593, + 0x00008402, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xf1402573, + 0x00000597, + 0x03c58593, + 0x10500073, + 0x0000bff5, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xedfe0dd0, + 0x8f060000, + 0x38000000, + 0x54050000, + 0x28000000, + 0x11000000, + 0x10000000, + 0x00000000, + 0x3b010000, + 0x1c050000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01000000, + 0x00000000, + 0x03000000, + 0x04000000, + 0x00000000, + 0x02000000, + 0x03000000, + 0x04000000, + 0x0f000000, + 0x02000000, + 0x03000000, + 0x14000000, + 0x1b000000, + 0x2c687465, + 0x61697261, + 0x622d656e, + 0x2d657261, + 0x00766564, + 0x03000000, + 0x10000000, + 0x26000000, + 0x2c687465, + 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0x1b000000, + 0x63736972, + 0x6c632c76, + 0x30746e69, + 0x00000000, + 0x03000000, + 0x10000000, + 0xbe000000, + 0x01000000, + 0x03000000, + 0x01000000, + 0x07000000, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x00000002, + 0x00000000, + 0x00000c00, + 0x03000000, + 0x08000000, + 0xd2000000, + 0x746e6f63, + 0x006c6f72, + 0x02000000, + 0x01000000, + 0x65746e69, + 0x70757272, + 0x6f632d74, + 0x6f72746e, + 0x72656c6c, + 0x30306340, + 0x30303030, + 0x00000000, + 0x03000000, + 0x04000000, + 0x00000000, + 0x00000000, + 0x03000000, + 0x04000000, + 0x83000000, + 0x01000000, + 0x03000000, + 0x1e000000, + 0x1b000000, + 0x69666973, + 0x702c6576, + 0x2d63696c, + 0x2e302e31, + 0x69720030, + 0x2c766373, + 0x63696c70, + 0x00000030, + 0x03000000, + 0x00000000, + 0x94000000, + 0x03000000, + 0x10000000, + 0xbe000000, + 0x01000000, + 0x0b000000, + 0x01000000, + 0x09000000, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x0000000c, + 0x00000000, + 0x00000004, + 0x03000000, + 0x04000000, + 0xdc000000, + 0x07000000, + 0x03000000, + 0x04000000, + 0xef000000, + 0x02000000, + 0x03000000, + 0x04000000, + 0xa9000000, + 0x02000000, + 0x03000000, + 0x04000000, + 0xaf000000, + 0x02000000, + 0x02000000, + 0x01000000, + 0x75626564, + 0x6f632d67, + 0x6f72746e, + 0x72656c6c, + 0x00003040, + 0x03000000, + 0x10000000, + 0x1b000000, + 0x63736972, + 0x65642c76, + 0x2d677562, + 0x00333130, + 0x03000000, + 0x08000000, + 0xbe000000, + 0x01000000, + 0xffff0000, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00100000, + 0x03000000, + 0x08000000, + 0xd2000000, + 0x746e6f63, + 0x006c6f72, + 0x02000000, + 0x01000000, + 0x74726175, + 0x30303140, + 0x30303030, + 0x00000030, + 0x03000000, + 0x08000000, + 0x1b000000, + 0x3631736e, + 0x00303537, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x00000010, + 0x00000000, + 0x00100000, + 0x03000000, + 0x04000000, + 0x3f000000, + 0x80f0fa02, + 0x03000000, + 0x04000000, + 0xfa000000, + 0x00c20100, + 0x03000000, + 0x04000000, + 0x08010000, + 0x02000000, + 0x03000000, + 0x04000000, + 0x19010000, + 0x01000000, + 0x03000000, + 0x04000000, + 0x24010000, + 0x02000000, + 0x03000000, + 0x04000000, + 0x2e010000, + 0x04000000, + 0x02000000, + 0x02000000, + 0x02000000, + 0x09000000, + 0x64646123, + 0x73736572, + 0x6c65632d, + 0x2300736c, + 0x657a6973, + 0x6c65632d, + 0x6300736c, + 0x61706d6f, + 0x6c626974, + 0x6f6d0065, + 0x006c6564, + 0x656d6974, + 0x65736162, + 0x6572662d, + 0x6e657571, + 0x63007963, + 0x6b636f6c, + 0x6572662d, + 0x6e657571, + 0x64007963, + 0x63697665, + 0x79745f65, + 0x72006570, + 0x73006765, + 0x75746174, + 0x69720073, + 0x2c766373, + 0x00617369, + 0x2d756d6d, + 0x65707974, + 0x626c7400, + 0x6c70732d, + 0x23007469, + 0x65746e69, + 0x70757272, + 0x65632d74, + 0x00736c6c, + 0x65746e69, + 0x70757272, + 0x6f632d74, + 0x6f72746e, + 0x72656c6c, + 0x6e696c00, + 0x702c7875, + 0x646e6168, + 0x7200656c, + 0x65676e61, + 0x6e690073, + 0x72726574, + 0x73747075, + 0x7478652d, + 0x65646e65, + 0x65720064, + 0x616e2d67, + 0x0073656d, + 0x63736972, + 0x616d2c76, + 0x72702d78, + 0x69726f69, + 0x72007974, + 0x76637369, + 0x65646e2c, + 0x75630076, + 0x6e657272, + 0x70732d74, + 0x00646565, + 0x65746e69, + 0x70757272, + 0x61702d74, + 0x746e6572, + 0x746e6900, + 0x75727265, + 0x00737470, + 0x2d676572, + 0x66696873, + 0x65720074, + 0x6f692d67, + 0x6469772d, + 0x00006874 +}; diff --git a/bootrom/bootrom.img b/bootrom/bootrom.img index e15ccba055..05c3a8da67 100644 Binary files a/bootrom/bootrom.img and b/bootrom/bootrom.img differ diff --git a/bootrom/bootrom.sv b/bootrom/bootrom.sv index 8add90eafd..62cb4ceff2 100644 --- a/bootrom/bootrom.sv +++ b/bootrom/bootrom.sv @@ -1,10 +1,10 @@ /* Copyright 2018 ETH Zurich and University of Bologna. * Copyright and related rights are licensed under the Solderpad Hardware - * License, Version 0.51 (the “License”); you may not use this file except in + * License, Version 0.51 (the "License"); you may not use this file except in * compliance with the License. You may obtain a copy of the License at * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law * or agreed to in writing, software, hardware and materials distributed under - * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR * CONDITIONS OF ANY KIND, either express or implied. See the License for the * specific language governing permissions and limitations under the License. * @@ -20,110 +20,193 @@ module bootrom ( input logic [63:0] addr_i, output logic [63:0] rdata_o ); - localparam int RomSize = 143; + localparam int RomSize = 226; const logic [RomSize-1:0][63:0] mem = { - 64'h00646564_6e657478, - 64'h652d7374_70757272, - 64'h65746e69_00736567, - 64'h6e617200_656c646e, - 64'h6168702c_78756e69, - 64'h6c007265_6c6c6f72, - 64'h746e6f63_2d747075, + 64'h00006874_6469772d, + 64'h6f692d67_65720074, + 64'h66696873_2d676572, + 64'h00737470_75727265, + 64'h746e6900_746e6572, + 64'h61702d74_70757272, + 64'h65746e69_00646565, + 64'h70732d74_6e657272, + 64'h75630076_65646e2c, + 64'h76637369_72007974, + 64'h69726f69_72702d78, + 64'h616d2c76_63736972, + 64'h0073656d_616e2d67, + 64'h65720064_65646e65, + 64'h7478652d_73747075, 64'h72726574_6e690073, - 64'h6c6c6563_2d747075, - 64'h72726574_6e692300, - 64'h79636e65_75716572, - 64'h662d6b63_6f6c6300, - 64'h65707974_2d756d6d, - 64'h00617369_2c766373, - 64'h69720073_75746174, - 64'h73006765_72006570, - 64'h79745f65_63697665, - 64'h64007963_6e657571, - 64'h6572662d_65736162, - 64'h656d6974_006c6564, - 64'h6f6d0065_6c626974, - 64'h61706d6f_6300736c, - 64'h6c65632d_657a6973, - 64'h2300736c_6c65632d, - 64'h73736572_64646123, - 64'h09000000_02000000, - 64'h02000000_00000030, - 64'h66697468_2c626375, - 64'h1b000000_0a000000, - 64'h03000000_00000000, - 64'h66697468_01000000, + 64'h65676e61_7200656c, + 64'h646e6168_702c7875, + 64'h6e696c00_72656c6c, + 64'h6f72746e_6f632d74, + 64'h70757272_65746e69, + 64'h00736c6c_65632d74, + 64'h70757272_65746e69, + 64'h23007469_6c70732d, + 64'h626c7400_65707974, + 64'h2d756d6d_00617369, + 64'h2c766373_69720073, + 64'h75746174_73006765, + 64'h72006570_79745f65, + 64'h63697665_64007963, + 64'h6e657571_6572662d, + 64'h6b636f6c_63007963, + 64'h6e657571_6572662d, + 64'h65736162_656d6974, + 64'h006c6564_6f6d0065, + 64'h6c626974_61706d6f, + 64'h6300736c_6c65632d, + 64'h657a6973_2300736c, + 64'h6c65632d_73736572, + 64'h64646123_09000000, 64'h02000000_02000000, - 64'h00000c00_00000000, - 64'h00000002_00000000, - 64'h4b000000_10000000, - 64'h03000000_07000000, - 64'h01000000_03000000, - 64'h01000000_b4000000, + 64'h02000000_04000000, + 64'h2e010000_04000000, + 64'h03000000_02000000, + 64'h24010000_04000000, + 64'h03000000_01000000, + 64'h19010000_04000000, + 64'h03000000_02000000, + 64'h08010000_04000000, + 64'h03000000_00c20100, + 64'hfa000000_04000000, + 64'h03000000_80f0fa02, + 64'h3f000000_04000000, + 64'h03000000_00100000, + 64'h00000000_00000010, + 64'h00000000_5b000000, 64'h10000000_03000000, - 64'h00000000_30746e69, - 64'h6c632c76_63736972, - 64'h1b000000_0d000000, + 64'h00303537_3631736e, + 64'h1b000000_08000000, 64'h03000000_00000030, - 64'h30303030_30324074, - 64'h6e696c63_01000000, - 64'had000000_00000000, - 64'h03000000_00007375, - 64'h622d656c_706d6973, - 64'h00636f73_2d657261, - 64'h622d656e_61697261, - 64'h2c687465_1b000000, - 64'h1f000000_03000000, - 64'h02000000_0f000000, + 64'h30303030_30303140, + 64'h74726175_01000000, + 64'h02000000_006c6f72, + 64'h746e6f63_d2000000, + 64'h08000000_03000000, + 64'h00100000_00000000, + 64'h00000000_00000000, + 64'h5b000000_10000000, + 64'h03000000_ffff0000, + 64'h01000000_be000000, + 64'h08000000_03000000, + 64'h00333130_2d677562, + 64'h65642c76_63736972, + 64'h1b000000_10000000, + 64'h03000000_00003040, + 64'h72656c6c_6f72746e, + 64'h6f632d67_75626564, + 64'h01000000_02000000, + 64'h02000000_af000000, 64'h04000000_03000000, - 64'h02000000_00000000, + 64'h02000000_a9000000, + 64'h04000000_03000000, + 64'h02000000_ef000000, + 64'h04000000_03000000, + 64'h07000000_dc000000, 64'h04000000_03000000, - 64'h00636f73_01000000, - 64'h02000000_00000001, - 64'h00000000_00000080, - 64'h00000000_4b000000, + 64'h00000004_00000000, + 64'h0000000c_00000000, + 64'h5b000000_10000000, + 64'h03000000_09000000, + 64'h01000000_0b000000, + 64'h01000000_be000000, 64'h10000000_03000000, - 64'h00007972_6f6d656d, - 64'h3f000000_07000000, - 64'h03000000_00303030, - 64'h30303030_38407972, - 64'h6f6d656d_01000000, - 64'h02000000_02000000, - 64'h02000000_01000000, - 64'ha5000000_04000000, - 64'h03000000_01000000, - 64'h9f000000_04000000, - 64'h03000000_00006374, - 64'h6e692d75_70632c76, - 64'h63736972_1b000000, - 64'h0f000000_03000000, - 64'h8a000000_00000000, + 64'h94000000_00000000, + 64'h03000000_00000030, + 64'h63696c70_2c766373, + 64'h69720030_2e302e31, + 64'h2d63696c_702c6576, + 64'h69666973_1b000000, + 64'h1e000000_03000000, + 64'h01000000_83000000, + 64'h04000000_03000000, + 64'h00000000_00000000, + 64'h04000000_03000000, + 64'h00000000_30303030, + 64'h30306340_72656c6c, + 64'h6f72746e_6f632d74, + 64'h70757272_65746e69, + 64'h01000000_02000000, + 64'h006c6f72_746e6f63, + 64'hd2000000_08000000, + 64'h03000000_00000c00, + 64'h00000000_00000002, + 64'h00000000_5b000000, + 64'h10000000_03000000, + 64'h07000000_01000000, 64'h03000000_01000000, - 64'h79000000_04000000, + 64'hbe000000_10000000, 64'h03000000_00000000, - 64'h72656c6c_6f72746e, - 64'h6f632d74_70757272, - 64'h65746e69_01000000, - 64'h00ca9a3b_69000000, + 64'h30746e69_6c632c76, + 64'h63736972_1b000000, + 64'h0d000000_03000000, + 64'h00000030_30303030, + 64'h30324074_6e696c63, + 64'h01000000_b7000000, + 64'h00000000_03000000, + 64'h00007375_622d656c, + 64'h706d6973_00636f73, + 64'h2d657261_622d656e, + 64'h61697261_2c687465, + 64'h1b000000_1f000000, + 64'h03000000_02000000, + 64'h0f000000_04000000, + 64'h03000000_02000000, + 64'h00000000_04000000, + 64'h03000000_00636f73, + 64'h01000000_02000000, + 64'h00008001_00000000, + 64'h00000080_00000000, + 64'h5b000000_10000000, + 64'h03000000_00007972, + 64'h6f6d656d_4f000000, + 64'h07000000_03000000, + 64'h00303030_30303030, + 64'h38407972_6f6d656d, + 64'h01000000_02000000, + 64'h02000000_02000000, + 64'h01000000_af000000, + 64'h04000000_03000000, + 64'h01000000_a9000000, + 64'h04000000_03000000, + 64'h00006374_6e692d75, + 64'h70632c76_63736972, + 64'h1b000000_0f000000, + 64'h03000000_94000000, + 64'h00000000_03000000, + 64'h01000000_83000000, 64'h04000000_03000000, + 64'h00000000_72656c6c, + 64'h6f72746e_6f632d74, + 64'h70757272_65746e69, + 64'h01000000_79000000, + 64'h00000000_03000000, 64'h00003933_76732c76, - 64'h63736972_60000000, + 64'h63736972_70000000, 64'h0b000000_03000000, - 64'h00636d69_34367672, - 64'h56000000_08000000, - 64'h03000000_00000076, - 64'h63736972_1b000000, - 64'h06000000_03000000, + 64'h00007573_63616d69, + 64'h34367672_66000000, + 64'h0b000000_03000000, + 64'h00000076_63736972, + 64'h00656e61_69726120, + 64'h2c687465_1b000000, + 64'h12000000_03000000, 64'h00000000_79616b6f, - 64'h4f000000_05000000, + 64'h5f000000_05000000, 64'h03000000_00000000, - 64'h4b000000_04000000, + 64'h5b000000_04000000, 64'h03000000_00757063, + 64'h4f000000_04000000, + 64'h03000000_80f0fa02, 64'h3f000000_04000000, 64'h03000000_00000030, 64'h40757063_01000000, - 64'h80969800_2c000000, + 64'h00800000_2c000000, 64'h04000000_03000000, 64'h00000000_0f000000, 64'h04000000_03000000, @@ -145,11 +228,11 @@ module bootrom ( 64'h00000000_01000000, 64'h00000000_00000000, 64'h00000000_00000000, - 64'hf8020000_c8000000, + 64'h1c050000_3b010000, 64'h00000000_10000000, 64'h11000000_28000000, - 64'h30030000_38000000, - 64'hf8030000_edfe0dd0, + 64'h54050000_38000000, + 64'h8f060000_edfe0dd0, 64'h00000000_00000000, 64'h00000000_00000000, 64'h00000000_00000000, @@ -176,5 +259,7 @@ module bootrom ( end end - assign rdata_o = mem[addr_q]; + // this prevents spurious Xes from propagating into + // the speculative fetch stage of the core + assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0; endmodule diff --git a/bootrom/encoding.h b/bootrom/encoding.h new file mode 100644 index 0000000000..8d9aaf64e7 --- /dev/null +++ b/bootrom/encoding.h @@ -0,0 +1,1475 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_DSCRATCH0 CSR_DSCRATCH +#define CSR_DSCRATCH1 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(dscratch0, CSR_DSCRATCH0) +DECLARE_CSR(dscratch1, CSR_DSCRATCH1) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/bootrom/gen_rom.py b/bootrom/gen_rom.py index 5314c3f1eb..481bc6e2f5 100755 --- a/bootrom/gen_rom.py +++ b/bootrom/gen_rom.py @@ -4,6 +4,7 @@ import argparse import os.path import sys +from bitstring import ConstBitStream, BitArray, BitStream parser = argparse.ArgumentParser(description='Convert binary file to verilog rom') parser.add_argument('filename', metavar='filename', nargs=1, @@ -22,11 +23,11 @@ license = """\ /* Copyright 2018 ETH Zurich and University of Bologna. * Copyright and related rights are licensed under the Solderpad Hardware - * License, Version 0.51 (the “License”); you may not use this file except in + * License, Version 0.51 (the "License"); you may not use this file except in * compliance with the License. You may obtain a copy of the License at * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law * or agreed to in writing, software, hardware and materials distributed under - * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR * CONDITIONS OF ANY KIND, either express or implied. See the License for the * specific language governing permissions and limitations under the License. * @@ -48,7 +49,7 @@ localparam int RomSize = $size; const logic [RomSize-1:0][63:0] mem = { - $content +$content }; logic [$$clog2(RomSize)-1:0] addr_q; @@ -59,54 +60,69 @@ end end - assign rdata_o = mem[addr_q]; + // this prevents spurious Xes from propagating into + // the speculative fetch stage of the core + assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0; endmodule """ -rom = [] - -with open(filename + ".img", "rb") as f: - byte = True; - while byte: - word = "" - # read 64-bit a.k.a 8 byte - for i in range(0, 8): - byte = f.read(1) - if i == 4: - word = "_" + word - if byte: - word = byte.hex() + word - # fill up with zeros if unaligned - else: - pass - # word += "00"; - - if word != "_": - word = "64'h" + word - # print(word) - rom.append(word) - f.close() +c_var = """\ +// Auto-generated code +const int reset_vec_size = $size; -rom.reverse() +uint32_t reset_vec[reset_vec_size] = { +$content +}; +""" -# open file for writing -with open(filename + ".sv", "w") as f: +def read_bin(): + s = ConstBitStream(filename=filename + ".img") + rom = [] + try: + while True: + rom.append(s.read("hex:8")) + except Exception as e: + pass + + # align to 64 bit + align = (int(len(rom) / 8) + 1) * 8; + + for i in range(len(rom), align): + rom.append("00") + + return rom + +rom = read_bin() + +""" Generate C header file for simulator +""" +with open(filename + ".h", "w") as f: + rom_str = "" + # process in junks of 32 bit (4 byte) + for i in range(0, int(len(rom)/4)): + rom_str += " 0x" + "".join(rom[i*4:i*4+4][::-1]) + ",\n" + + # remove the trailing comma + rom_str = rom_str[:-2] - # some string preparations + s = Template(c_var) + f.write(s.substitute(filename=filename, size=int(len(rom)/4), content=rom_str)) + + f.close() + +""" Generate SystemVerilog bootcode for FPGA and ASIC +""" +with open(filename + ".sv", "w") as f: rom_str = "" - i = 0 - for r in rom: - i += 1 - rom_str += r + ",\n "; + # process in junks of 64 bit (8 byte) + for i in reversed(range(int(len(rom)/8))): + rom_str += " 64'h" + "".join(rom[i*8+4:i*8+8][::-1]) + "_" + "".join(rom[i*8:i*8+4][::-1]) + ",\n" - rom_str.rstrip() - # strip the last whitespace - rom_str = rom_str[:-10] + # remove the trailing comma + rom_str = rom_str[:-2] - # write files f.write(license) s = Template(module) - f.write(s.substitute(filename=filename, size=i, content=rom_str)) + f.write(s.substitute(filename=filename, size=int(len(rom)/8), content=rom_str)) - f.close() diff --git a/ci/build-riscv-tests.sh b/ci/build-riscv-tests.sh index 2c335cbccc..2b37b276b5 100755 --- a/ci/build-riscv-tests.sh +++ b/ci/build-riscv-tests.sh @@ -1,7 +1,7 @@ #!/bin/bash set -e ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) -VERSION="294bfce8a1ca2fc501b8939292146e44f813a2b8" +VERSION="7cc76ea83b4f827596158c8ba0763e93da65de8f" cd $ROOT/tmp diff --git a/ci/check-tests.sh b/ci/check-tests.sh index e7b6e52a8c..2325d7f6da 100755 --- a/ci/check-tests.sh +++ b/ci/check-tests.sh @@ -2,7 +2,7 @@ # check simulation output (only for questasim flow) # # $1 simulation output file basename -# $2 list file containing the test names +# $2 number of tests to check # ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) diff --git a/ci/default.config b/ci/default.config index f405d4d8e6..393f419e6f 100644 --- a/ci/default.config +++ b/ci/default.config @@ -1,7 +1,7 @@ -torture.generator.nseqs 1000 +torture.generator.nseqs 200 torture.generator.memsize 1024 torture.generator.fprnd 0 -torture.generator.amo true +torture.generator.amo false torture.generator.mul true torture.generator.divider true torture.generator.segment true @@ -46,7 +46,7 @@ torture.testrun.dump false torture.testrun.vec false torture.overnight.errors 1 -torture.overnight.minutes 1 +torture.overnight.minutes 100000 torture.overnight.outdir output/failedtests torture.overnight.email your@email.address diff --git a/ci/get-torture.sh b/ci/get-torture.sh index 22ec2100c6..549c4b5d8e 100755 --- a/ci/get-torture.sh +++ b/ci/get-torture.sh @@ -17,5 +17,6 @@ git submodule update --init --recursive # copy ariane specific config cp config/default.config config/default.config.bak cp $ROOT/ci/default.config config/default.config +git checkout ./output/Makefile git apply $ROOT/ci/torture_make.patch diff --git a/ci/gitlab-ci-emul.sh b/ci/gitlab-ci-emul.sh index 1417d89cab..95a302bbf2 100755 --- a/ci/gitlab-ci-emul.sh +++ b/ci/gitlab-ci-emul.sh @@ -19,7 +19,9 @@ sudo apt install \ texinfo \ python-pexpect \ libusb-1.0-0-dev \ - default-jdk + default-jdk \ + zlib1g-dev \ + valgrind # customize your paths here source ci/path-setup.sh @@ -40,13 +42,13 @@ make clean make torture-gen # run asm tests on verilator -make -j${NUM_JOBS} verilate -make -j${NUM_JOBS} run-asm-tests-verilator -make -j${NUM_JOBS} run-benchmarks-verilator -make -j${NUM_JOBS} torture-rtest-verilator +make -j${NUM_JOBS} verilate +make -j${NUM_JOBS} run-asm-tests-verilator +make -j${NUM_JOBS} run-benchmarks-verilator +make -j${NUM_JOBS} torture-rtest-verilator # run asm tests on questa -make -j${NUM_JOBS} build -make -j${NUM_JOBS} run-asm-tests -make -j${NUM_JOBS} run-benchmarks -make -j${NUM_JOBS} torture-rtest +make -j${NUM_JOBS} build batch-mode=1 +make -j${NUM_JOBS} run-asm-tests batch-mode=1 +make -j${NUM_JOBS} run-benchmarks batch-mode=1 +make -j${NUM_JOBS} torture-rtest batch-mode=1 diff --git a/ci/install-dtc.sh b/ci/install-dtc.sh index 60dd0d62ed..c5f84ed6cc 100755 --- a/ci/install-dtc.sh +++ b/ci/install-dtc.sh @@ -9,7 +9,7 @@ if [ -z ${NUM_JOBS} ]; then NUM_JOBS=1 fi -if [ ! -e "$RISCV/dtc/dtc" ]; then +if [ ! -e "$RISCV/bin/dtc" ]; then echo "Installing DTC" git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git cd dtc diff --git a/ci/install-verilator.sh b/ci/install-verilator.sh index 7c523463a0..fcea099609 100755 --- a/ci/install-verilator.sh +++ b/ci/install-verilator.sh @@ -10,7 +10,9 @@ fi if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then echo "Installing Verilator" wget https://www.veripool.org/ftp/verilator-3.924.tgz - tar xzf verilator*.t*gz && cd verilator-* + tar xzf verilator*.t*gz + rm verilator*.t*gz + cd verilator-* mkdir -p $VERILATOR_ROOT # copy scripts autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS} diff --git a/ci/path-setup.sh b/ci/path-setup.sh index 66394262af..c77e20945f 100644 --- a/ci/path-setup.sh +++ b/ci/path-setup.sh @@ -5,7 +5,7 @@ export CI_BUILD_DIR=$TOP/ariane-repo #customize this to your setup export QUESTASIM_HOME= export QUESTASIM_VERSION= -export QUESTASIM_FLAGS= +export QUESTASIM_FLAGS=-noautoldlibpath export CXX=g++-7 CC=gcc-7 # where to install the tools diff --git a/ci/riscv-amo-tests.list b/ci/riscv-amo-tests.list new file mode 100644 index 0000000000..e5df5a759f --- /dev/null +++ b/ci/riscv-amo-tests.list @@ -0,0 +1,38 @@ +rv64ua-p-amoadd_d +rv64ua-p-amoadd_w +rv64ua-p-amoor_d +rv64ua-p-amoor_w +rv64ua-p-amoand_d +rv64ua-p-amoand_w +rv64ua-p-amoswap_d +rv64ua-p-amoswap_w +rv64ua-p-amoxor_d +rv64ua-p-amoxor_w +rv64ua-p-amomax_d +rv64ua-p-amomaxu_d +rv64ua-p-amomaxu_w +rv64ua-p-amomax_w +rv64ua-p-amomin_d +rv64ua-p-amomin_w +rv64ua-p-amominu_d +rv64ua-p-amominu_w +rv64ua-p-lrsc +rv64ua-v-amoadd_d +rv64ua-v-amoadd_w +rv64ua-v-amoor_d +rv64ua-v-amoor_w +rv64ua-v-amoand_d +rv64ua-v-amoand_w +rv64ua-v-amoswap_d +rv64ua-v-amoswap_w +rv64ua-v-amoxor_d +rv64ua-v-amoxor_w +rv64ua-v-amomax_d +rv64ua-v-amomaxu_d +rv64ua-v-amomaxu_w +rv64ua-v-amomax_w +rv64ua-v-amomin_d +rv64ua-v-amomin_w +rv64ua-v-amominu_d +rv64ua-v-amominu_w +rv64ua-v-lrsc diff --git a/ci/riscv-asm-tests.list b/ci/riscv-asm-tests.list index e03f7c3925..97e1765509 100644 --- a/ci/riscv-asm-tests.list +++ b/ci/riscv-asm-tests.list @@ -101,67 +101,3 @@ rv64ui-v-ld rv64ui-v-lh rv64ui-v-lhu rv64ui-v-lui -rv64um-p-mul -rv64um-p-mulh -rv64um-p-mulhsu -rv64um-p-mulhu -rv64um-p-div -rv64um-p-divu -rv64um-p-rem -rv64um-p-remu -rv64um-p-mulw -rv64um-p-divw -rv64um-p-divuw -rv64um-p-remw -rv64um-p-remuw -rv64um-v-mul -rv64um-v-mulh -rv64um-v-mulhsu -rv64um-v-mulhu -rv64um-v-div -rv64um-v-divu -rv64um-v-rem -rv64um-v-remu -rv64um-v-mulw -rv64um-v-divw -rv64um-v-divuw -rv64um-v-remw -rv64um-v-remuw -rv64ua-p-amoadd_d -rv64ua-p-amoadd_w -rv64ua-p-amoor_d -rv64ua-p-amoor_w -rv64ua-p-amoand_d -rv64ua-p-amoand_w -rv64ua-p-amoswap_d -rv64ua-p-amoswap_w -rv64ua-p-amoxor_d -rv64ua-p-amoxor_w -rv64ua-p-amomax_d -rv64ua-p-amomaxu_d -rv64ua-p-amomaxu_w -rv64ua-p-amomax_w -rv64ua-p-amomin_d -rv64ua-p-amomin_w -rv64ua-p-amominu_d -rv64ua-p-amominu_w -rv64ua-p-lrsc -rv64ua-v-amoadd_d -rv64ua-v-amoadd_w -rv64ua-v-amoor_d -rv64ua-v-amoor_w -rv64ua-v-amoand_d -rv64ua-v-amoand_w -rv64ua-v-amoswap_d -rv64ua-v-amoswap_w -rv64ua-v-amoxor_d -rv64ua-v-amoxor_w -rv64ua-v-amomax_d -rv64ua-v-amomaxu_d -rv64ua-v-amomaxu_w -rv64ua-v-amomax_w -rv64ua-v-amomin_d -rv64ua-v-amomin_w -rv64ua-v-amominu_d -rv64ua-v-amominu_w -rv64ua-v-lrsc diff --git a/ci/riscv-mul-tests.list b/ci/riscv-mul-tests.list new file mode 100644 index 0000000000..b7493ee310 --- /dev/null +++ b/ci/riscv-mul-tests.list @@ -0,0 +1,26 @@ +rv64um-p-mul +rv64um-p-mulh +rv64um-p-mulhsu +rv64um-p-mulhu +rv64um-p-div +rv64um-p-divu +rv64um-p-rem +rv64um-p-remu +rv64um-p-mulw +rv64um-p-divw +rv64um-p-divuw +rv64um-p-remw +rv64um-p-remuw +rv64um-v-mul +rv64um-v-mulh +rv64um-v-mulhsu +rv64um-v-mulhu +rv64um-v-div +rv64um-v-divu +rv64um-v-rem +rv64um-v-remu +rv64um-v-mulw +rv64um-v-divw +rv64um-v-divuw +rv64um-v-remw +rv64um-v-remuw diff --git a/ci/torture_make.patch b/ci/torture_make.patch index 35114604c4..4c4bb9d338 100644 --- a/ci/torture_make.patch +++ b/ci/torture_make.patch @@ -4,38 +4,38 @@ index cf1214f..c81bccc 100644 +++ b/output/Makefile @@ -20,9 +20,9 @@ extra_files = #-------------------------------------------------------------------- - + RISCV_GCC = riscv64-unknown-elf-gcc -RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha +RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=rv64imc RISCV_OBJDUMP = riscv64-unknown-elf-objdump --disassemble-all --section=.text --section=.data --section=.bss -RISCV_SIM = spike --extension=hwacha -+RISCV_SIM = spike - ++RISCV_SIM = spike + #------------------------------------------------------------ # Build assembly tests @@ -38,9 +38,6 @@ $(asm_tests_dump): %.dump: % $(asm_tests_bin): %: %.S $(extra_files) $(RISCV_GCC) $(RISCV_GCC_OPTS) -I../env/p -T../env/p/link.ld $< -o $@ - + -$(asm_tests_hex): %.hex: % $(extra_files) - elf2hex 16 16384 $< > $@ - $(asm_tests_sig): %.sig: % $(RISCV_SIM) +signature=$@ $< - + @@ -51,12 +48,12 @@ run: $(asm_tests_sig) echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \ $(asm_tests_sig); echo; - + -junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) $(asm_tests_hex) -+junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) - ++junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) + #------------------------------------------------------------ # Default - + -all: $(asm_tests_dump) $(asm_tests_hex) -+all: $(asm_tests_dump) - ++all: $(asm_tests_dump) + #------------------------------------------------------------ # Clean up diff --git a/ci/travis-ci-emul.sh b/ci/travis-ci-emul.sh index bb6d9df22c..0208a36973 100644 --- a/ci/travis-ci-emul.sh +++ b/ci/travis-ci-emul.sh @@ -19,7 +19,9 @@ sudo apt install \ texinfo \ python-pexpect \ libusb-1.0-0-dev \ - default-jdk + default-jdk \ + zlib1g-dev \ + valgrind # customize your paths here source ci/path-setup.sh @@ -40,7 +42,7 @@ make clean make torture-gen # run asm tests on verilator -make -j${NUM_JOBS} verilate -make -j${NUM_JOBS} run-asm-tests-verilator -make -j${NUM_JOBS} run-benchmarks-verilator -make -j${NUM_JOBS} torture-rtest-verilator +make -j${NUM_JOBS} verilate +make -j${NUM_JOBS} run-asm-tests-verilator +make -j${NUM_JOBS} run-benchmarks-verilator +make -j${NUM_JOBS} torture-rtest-verilator diff --git a/docs/Gemfile b/docs/Gemfile index 6ac80f68b5..78232a780a 100644 --- a/docs/Gemfile +++ b/docs/Gemfile @@ -1,7 +1,7 @@ source "https://rubygems.org" ruby RUBY_VERSION -gem "jekyll", "3.4.3" +gem "jekyll", "3.6.3" # to use GitHub Pages # gem "github-pages", group: :jekyll_plugins diff --git a/docs/Gemfile.lock b/docs/Gemfile.lock index 26ea18f51c..91fd8ec8e2 100644 --- a/docs/Gemfile.lock +++ b/docs/Gemfile.lock @@ -1,55 +1,61 @@ GEM remote: https://rubygems.org/ specs: - addressable (2.5.1) - public_suffix (~> 2.0, >= 2.0.2) + addressable (2.5.2) + public_suffix (>= 2.0.2, < 4.0) colorator (1.1.0) - ffi (1.9.18) + ffi (1.9.25) forwardable-extended (2.6.0) - jekyll (3.4.3) + jekyll (3.6.3) addressable (~> 2.4) colorator (~> 1.0) jekyll-sass-converter (~> 1.0) jekyll-watch (~> 1.1) - kramdown (~> 1.3) - liquid (~> 3.0) + kramdown (~> 1.14) + liquid (~> 4.0) mercenary (~> 0.3.3) pathutil (~> 0.9) - rouge (~> 1.7) + rouge (>= 1.7, < 3) safe_yaml (~> 1.0) - jekyll-feed (0.9.2) + jekyll-feed (0.11.0) jekyll (~> 3.3) - jekyll-redirect-from (0.12.1) + jekyll-redirect-from (0.14.0) jekyll (~> 3.3) - jekyll-sass-converter (1.5.0) + jekyll-sass-converter (1.5.2) sass (~> 3.4) - jekyll-seo-tag (2.2.2) + jekyll-seo-tag (2.5.0) jekyll (~> 3.3) - jekyll-sitemap (1.1.1) + jekyll-sitemap (1.2.0) jekyll (~> 3.3) - jekyll-watch (1.5.0) - listen (~> 3.0, < 3.1) - kramdown (1.13.2) - liquid (3.0.6) - listen (3.0.8) + jekyll-watch (1.5.1) + listen (~> 3.0) + kramdown (1.17.0) + liquid (4.0.1) + listen (3.1.5) rb-fsevent (~> 0.9, >= 0.9.4) rb-inotify (~> 0.9, >= 0.9.7) + ruby_dep (~> 1.2) mercenary (0.3.6) - pathutil (0.14.0) + pathutil (0.16.2) forwardable-extended (~> 2.6) - public_suffix (2.0.5) - rb-fsevent (0.9.8) - rb-inotify (0.9.8) - ffi (>= 0.5.0) - rouge (1.11.1) + public_suffix (3.0.3) + rb-fsevent (0.10.3) + rb-inotify (0.9.10) + ffi (>= 0.5.0, < 2) + rouge (2.2.1) + ruby_dep (1.5.0) safe_yaml (1.0.4) - sass (3.4.23) + sass (3.7.2) + sass-listen (~> 4.0.0) + sass-listen (4.0.0) + rb-fsevent (~> 0.9, >= 0.9.4) + rb-inotify (~> 0.9, >= 0.9.7) PLATFORMS ruby DEPENDENCIES - jekyll (= 3.4.3) + jekyll (= 3.6.3) jekyll-feed jekyll-redirect-from jekyll-seo-tag @@ -60,4 +66,4 @@ RUBY VERSION ruby 2.4.1p111 BUNDLED WITH - 1.16.1 + 1.17.1 diff --git a/docs/img/fpga_bd.pdf b/docs/img/fpga_bd.pdf new file mode 100644 index 0000000000..c1d202c605 Binary files /dev/null and b/docs/img/fpga_bd.pdf differ diff --git a/docs/img/fpga_bd.png b/docs/img/fpga_bd.png new file mode 100644 index 0000000000..86d3b2df75 Binary files /dev/null and b/docs/img/fpga_bd.png differ diff --git a/failedtests/.gitignore b/failedtests/.gitignore deleted file mode 100644 index f558273855..0000000000 --- a/failedtests/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -# Ignore all -* -# Unignore all with extensions -!*.* -# Ignore files with specific extension -*.hex -*.dump -*.sig -*.stats -*.dasm diff --git a/failedtests/Makefile b/failedtests/Makefile deleted file mode 100755 index b016372286..0000000000 --- a/failedtests/Makefile +++ /dev/null @@ -1,72 +0,0 @@ -#======================================================================= -# UCB VLSI FLOW: Makefile for riscv-tests -#----------------------------------------------------------------------- -# Yunsup Lee (yunsup@cs.berkeley.edu) -# - -default: all - -#-------------------------------------------------------------------- -# Sources -#-------------------------------------------------------------------- - -asm_tests = $(wildcard *.S) - -extra_files = - -#-------------------------------------------------------------------- -# Build rules -#-------------------------------------------------------------------- - -RISCV_GCC = riscv64-unknown-elf-gcc -RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=rv64i -RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy -RISCV_OBJDUMP = riscv64-unknown-elf-objdump --disassemble-all --section=.text --section=.data --section=.bss -RISCV_SIM = spike - -#------------------------------------------------------------ -# Build assembly tests - -asm_tests_bin = $(patsubst %.S, %, $(asm_tests)) -asm_tests_verilog = $(addsuffix .v, $(asm_tests_bin)) -asm_tests_dump = $(addsuffix .dump, $(asm_tests_bin)) -asm_tests_sig = $(addsuffix .sig, $(asm_tests_bin)) -asm_tests_hex = $(addsuffix .hex, $(asm_tests_bin)) - -$(asm_tests_dump): %.dump: % - $(RISCV_OBJDUMP) $< > $@ - -$(asm_tests_verilog): %.v: % - $(RISCV_OBJCOPY) -O verilog $< $@ - -$(asm_tests_bin): %: %.S $(extra_files) - $(RISCV_GCC) $(RISCV_GCC_OPTS) -I../riscv-torture/env/p -T../riscv-torture/env/p/link.ld $< -o $@ - -$(asm_tests_hex): %.hex: % $(extra_files) - elf2hex 8 16384 $< 2147483648 > $@ - -$(asm_tests_sig): %.sig: % - $(RISCV_SIM) +signature=$@ $< - -new: - cd ..; make gen - -run: $(asm_tests_sig) - echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \ - $(asm_tests_sig); echo; - -junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) $(asm_tests_hex) - -#------------------------------------------------------------ -# Default - -all: $(asm_tests_dump) $(asm_tests_hex) - -#------------------------------------------------------------ -# Clean up - -clean: - rm -rf $(junk) - -clean-all: clean - rm -rf test*.S test*.stats test*.hex test*.out test*.dump test test_1* test_pseg_* schad* failedtests/* diff --git a/failedtests/failed_tests.md b/failedtests/failed_tests.md deleted file mode 100644 index 670486d9e6..0000000000 --- a/failedtests/failed_tests.md +++ /dev/null @@ -1,10 +0,0 @@ -# Failed Test Report - -## VMA Tests - -* test_1498676631701: - * Found bug in misaligned exception of half word access when another LSU request was incoming - -* test_1498880354372: - * Found bug in `sfence.vma`, pipeline wasn't flushing due to wrong assignment on the no store pending signal, coming from the store buffer - * Found bug in accidental exception taken in the MMU: Even though the LSU didn't place a request on the MMU the MMU was propagating a misaligned exception signal. The solution was masking it by the `lsu_req` signal. diff --git a/failedtests/test_1498676631701.S b/failedtests/test_1498676631701.S deleted file mode 100644 index e1d20bb035..0000000000 --- a/failedtests/test_1498676631701.S +++ /dev/null @@ -1,742 +0,0 @@ -// random assembly code generated by RISC-V torture test generator -// nseqs = 200 -// memsize = 1024 - -#include "riscv_test.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - j test_start - -crash_backward: - RVTEST_FAIL - -test_start: - -xreg_init: - la x31, xreg_init_data - ld x0, 0(x31) - ld x1, 8(x31) - ld x2, 16(x31) - ld x3, 24(x31) - ld x4, 32(x31) - ld x5, 40(x31) - ld x6, 48(x31) - ld x7, 56(x31) - ld x8, 64(x31) - ld x9, 72(x31) - ld x10, 80(x31) - ld x11, 88(x31) - ld x12, 96(x31) - ld x13, 104(x31) - ld x14, 112(x31) - ld x15, 120(x31) - ld x16, 128(x31) - ld x17, 136(x31) - ld x18, 144(x31) - ld x19, 152(x31) - ld x20, 160(x31) - ld x21, 168(x31) - ld x22, 176(x31) - ld x23, 184(x31) - ld x24, 192(x31) - ld x25, 200(x31) - ld x26, 208(x31) - ld x27, 216(x31) - ld x28, 224(x31) - ld x29, 232(x31) - ld x30, 240(x31) - ld x31, 248(x31) - - j pseg_0 - -pseg_0: - addi x3, x0, 1 - addi x2, x0, 1 - subw x15, x5, x31 - sll x2, x2, 63 - addi x19, x0, 2015 - addi x26, x0, 1527 - sllw x1, x15, x15 - addi x25, x0, 1492 - addi x17, x0, 1 - addi x9, x0, -946 - addi x12, x26, 1211 - addi x8, x0, -315 - sra x18, x9, x9 - sll x17, x17, 63 - addi x14, x0, 1825 - srlw x30, x25, x8 - lui x31, 955643 - addi x7, x0, -1 - srlw x13, x14, x14 - or x21, x19, x19 - xor x7, x7, x17 - addi x29, x0, -1 - addi x11, x0, 1 - xor x29, x29, x2 - bge x26, x12, crash_forward - and x20, x15, x7 - sll x3, x3, 63 - or x6, x30, x17 - addi x10, x0, -1 - and x5, x16, x29 - or x23, x24, x2 - xor x10, x10, x3 - and x4, x2, x10 - sll x11, x11, 63 - addi x22, x0, -1 - xor x22, x22, x11 - and x28, x31, x22 - or x16, x22, x11 - or x27, x24, x3 - addi x13, x0, 1 - srl x24, x23, x11 - addi x7, x0, 792 - sltiu x15, x15, 1387 - la x9, test_memory-969 - addi x8, x0, -893 - addi x26, x8, -920 - sll x13, x13, 63 - addi x12, x0, -1 - xor x12, x12, x13 - la x11, test_memory+2198 - lbu x29, -1285(x11) - la x6, test_memory+348 - xori x31, x31, 1641 - and x17, x31, x12 - la x2, test_memory+2555 - addi x25, x0, -199 - addi x24, x0, -456 - addi x1, x25, -1246 - xor x27, x10, x17 - lwu x19, 1949(x9) - addw x15, x4, x4 - addi x23, x0, 259 - or x20, x3, x13 - sltu x10, x23, x23 - sw x26, -1759(x2) - addi x18, x0, -335 - addi x3, x0, 1 - sra x28, x24, x24 - addi x4, x0, -1896 - sll x3, x3, 63 - addi x5, x0, -1 - addi x11, x0, -1058 - sra x30, x7, x18 - sltu x31, x4, x4 - srlw x29, x11, x11 - xor x5, x5, x3 - and x16, x9, x5 - xori x29, x30, -1166 - sltiu x10, x29, 1519 - srl x31, x27, x18 - or x24, x13, x13 - slli x15, x15, 60 - addi x23, x0, -1478 - addi x18, x0, -1056 - la x9, test_memory-1460 - la x11, test_memory+1562 - or x22, x16, x3 - la x7, test_memory+2339 - sltu x2, x18, x18 - and x8, x18, x14 - la x27, test_memory+1707 - la x19, test_memory+1427 - la x12, test_memory+2473 - sb x25, -1915(x12) - addi x28, x26, -1654 - ld x26, -1155(x27) - slt x30, x23, x23 - sw x15, 1472(x9) - slt x13, x4, x4 - addi x29, x0, 1325 - lwu x17, -1354(x11) - addi x10, x0, -697 - lw x20, -1807(x7) - sltu x4, x29, x10 - sw x8, -1219(x19) - la x14, test_memory+986 - sllw x1, x17, x17 - sh x17, -610(x14) - addi x18, x0, 1 - addi x28, x0, 1891 - addi x9, x0, 1 - addi x17, x0, -563 - addi x27, x0, 1 - addi x2, x0, 61 - addi x19, x2, 391 - sll x18, x18, 63 - addw x12, x14, x14 - la x20, test_memory+2801 - sll x9, x9, 63 - addi x5, x0, 0 - sub x7, x28, x17 - srlw x12, x28, x22 - addi x10, x0, 0 - addi x30, x0, -1 - lwu x29, -1861(x20) - addi x4, x0, -1 - blt x5, x10, crash_forward - xor x30, x30, x18 - slliw x11, x6, 7 - addi x26, x0, -1336 - addw x23, x26, x26 - bgeu x2, x19, crash_forward - and x31, x26, x30 - la x10, test_memory+1884 - lbu x21, 29(x6) - addi x5, x0, 1389 - sll x27, x27, 63 - lui x2, 647240 - sltiu x26, x30, 623 - addi x19, x0, 1799 - addi x20, x19, 1856 - add x11, x24, x20 - subw x7, x6, x23 - addi x21, x0, 1 - la x16, test_memory+2554 - sll x21, x21, 63 - addi x17, x0, -1548 - addi x29, x17, -1821 - lw x23, -1804(x10) - addi x24, x0, -1 - or x22, x14, x18 - xor x4, x4, x9 - la x8, test_memory+2269 - addi x11, x0, -662 - blt x31, x22, crash_backward - xor x24, x24, x27 - addi x6, x0, -1 - xor x6, x6, x21 - addi x20, x0, -1309 - and x1, x28, x4 - addi x26, x0, 643 - or x3, x0, x9 - and x14, x5, x6 - or x12, x5, x5 - addi x29, x0, 1 - blt x1, x3, crash_forward - sll x29, x29, 63 - sra x23, x6, x5 - sll x7, x11, x26 - addi x17, x0, -1 - xor x17, x17, x29 - and x12, x16, x17 - addi x2, x0, 204 - or x28, x14, x21 - lui x5, 598486 - srlw x19, x20, x2 - and x15, x12, x24 - or x30, x6, x29 - lbu x25, -1917(x16) - beq x14, x28, crash_backward - addi x4, x0, -971 - sw x2, -1633(x8) - addi x9, x0, 1 - la x18, test_memory-1534 - or x13, x3, x27 - sra x6, x29, x28 - addw x31, x30, x30 - addi x22, x0, 1855 - addi x21, x0, 1 - la x25, test_memory+1201 - addi x20, x0, -1341 - lb x10, 1765(x18) - sll x9, x9, 63 - la x30, test_memory+451 - addi x7, x0, -1 - sll x21, x21, 63 - la x8, test_memory+378 - addi x11, x0, 1810 - addi x14, x0, 1736 - or x26, x4, x11 - addi x19, x14, 1505 - addi x16, x0, -1 - sw x24, -78(x8) - addi x31, x0, 663 - sb x1, 186(x30) - bge x14, x19, crash_forward - subw x12, x31, x31 - xor x7, x7, x9 - xor x16, x16, x21 - addi x23, x22, 38 - lbu x5, -899(x25) - and x28, x26, x16 - or x2, x28, x21 - and x3, x10, x7 - addi x11, x0, 1 - addi x19, x0, 1301 - addi x27, x0, 1 - addi x8, x0, 1877 - sltiu x22, x21, -1343 - sll x11, x11, 63 - la x12, test_memory+155 - or x1, x20, x9 - lw x26, -15(x12) - sll x27, x27, 63 - addi x5, x0, 1917 - addi x18, x8, 1755 - la x3, test_memory-584 - bltu x10, x10, crash_forward - add x14, x19, x5 - addi x4, x0, -1 - la x9, test_memory+2152 - xor x4, x4, x27 - addi x10, x0, -1 - addi x13, x0, 706 - lh x12, -1984(x9) - and x31, x27, x4 - or x25, x22, x27 - xor x17, x20, x13 - addi x7, x0, -714 - addi x1, x0, -827 - ld x22, 760(x3) - addi x22, x0, 1 - la x13, test_memory+181 - la x3, test_memory-1079 - bltu x0, x0, crash_backward - xor x10, x10, x11 - bltu x7, x7, crash_forward - addi x24, x0, 1 - sll x22, x22, 63 - addi x5, x0, 1364 - lb x16, 720(x13) - addi x8, x0, 574 - la x20, test_memory-620 - addi x19, x0, 1959 - srlw x21, x8, x19 - lhu x28, 692(x20) - sd x5, 1975(x3) - sll x24, x24, 63 - sraw x26, x7, x1 - addi x6, x0, -1 - xor x6, x6, x24 - and x30, x8, x10 - and x29, x19, x6 - la x18, test_memory-540 - sd x21, 924(x18) - or x15, x22, x24 - addi x1, x0, -721 - bgeu x29, x15, crash_forward - addi x31, x0, 2038 - addi x27, x0, -1504 - or x23, x1, x11 - sll x18, x15, x24 - addi x14, x0, -1 - sllw x12, x5, x5 - srlw x26, x31, x27 - addi x4, x0, 1 - xor x14, x14, x22 - la x20, test_memory-1039 - sll x4, x4, 63 - addi x3, x0, -1472 - la x10, test_memory-353 - lw x11, 969(x10) - addi x6, x0, 1 - sll x6, x6, 63 - lhu x28, 1635(x20) - and x2, x3, x14 - addi x23, x0, 823 - addi x12, x0, 909 - slt x18, x23, x12 - addw x27, x30, x30 - addi x31, x0, -1 - addi x21, x1, -1950 - addi x29, x0, -1478 - addi x7, x0, -880 - xor x31, x31, x6 - addi x25, x0, -1 - addi x26, x29, -527 - or x17, x9, x22 - and x24, x19, x31 - bge x26, x29, crash_forward - xor x25, x25, x4 - addi x9, x0, -1695 - and x13, x3, x7 - sllw x8, x9, x9 - or x15, x24, x6 - and x19, x0, x25 - or x16, x18, x4 - bltu x16, x19, crash_backward - andi x9, x18, 1474 - addi x12, x0, 1 - la x29, test_memory+1837 - sll x12, x12, 63 - addi x8, x0, 1892 - la x21, test_memory+1241 - addi x14, x0, 1 - addi x11, x0, -1745 - addi x26, x0, 1675 - subw x19, x28, x28 - addi x22, x0, -640 - lwu x1, -889(x21) - addi x20, x0, -1 - sltu x30, x8, x22 - slliw x31, x23, 28 - la x4, test_memory-1760 - xor x20, x20, x12 - addi x27, x26, 565 - and x16, x18, x20 - addi x2, x0, 216 - addi x25, x2, 197 - bgeu x2, x25, crash_backward - addi x19, x3, 0 - or x23, x16, x12 - addi x28, x0, 54 - addi x31, x19, 0 - addi x7, x0, 248 - addi x21, x0, -821 - add x1, x3, x3 - sra x18, x21, x21 - addi x10, x0, -1105 - addi x2, x0, -1367 - addi x25, x0, -378 - addi x22, x0, 27 - la x13, test_memory+779 - or x24, x10, x10 - or x6, x11, x28 - sh x0, 1836(x4) - sll x14, x14, 63 - sw x24, -327(x13) - lh x15, -1761(x29) - addw x9, x21, x21 - srlw x30, x7, x25 - subw x8, x2, x22 - addi x5, x0, -1 - xor x5, x5, x14 - and x3, x16, x5 - or x17, x23, x14 - addi x4, x0, 1269 - la x8, test_memory+1864 - addi x16, x0, -1644 - sltiu x1, x5, -375 - la x10, test_memory+1496 - slt x31, x0, x26 - sra x25, x4, x4 - addi x15, x0, 0 - addi x3, x0, -734 - la x20, test_memory+589 - addi x12, x0, 686 - addi x26, x0, -813 - srl x14, x3, x3 - addi x9, x0, -1191 - slli x13, x16, 13 - lwu x29, 123(x20) - sllw x5, x12, x12 - addi x23, x0, 0 - sraw x24, x12, x12 - addi x6, x29, 0 - addw x3, x29, x29 - slt x27, x14, x0 - addi x1, x0, -1372 - sw x16, -1512(x8) - addi x21, x6, 0 - addw x18, x9, x9 - addi x31, x0, -1326 - addi x29, x0, -494 - bne x15, x23, crash_backward - bne x6, x21, crash_forward - add x12, x0, x30 - addi x28, x16, -380 - la x2, test_memory+394 - la x9, test_memory-518 - and x4, x31, x31 - xor x30, x26, x26 - la x25, test_memory+139 - addi x31, x0, 2009 - addi x7, x0, 1892 - la x17, test_memory+1714 - addi x27, x0, -1318 - lh x22, -356(x2) - ld x18, 958(x9) - sra x5, x1, x29 - lb x20, 406(x25) - addi x14, x14, 0 - addi x4, x0, -581 - sub x15, x31, x31 - srl x12, x4, x4 - sh x15, -1260(x17) - lh x19, -1068(x10) - addi x13, x15, 0 - sra x11, x7, x7 - addi x2, x0, -745 - addi x26, x0, -1309 - sllw x6, x4, x26 - andi x30, x10, -293 - sraiw x29, x19, 17 - la x1, test_memory+2545 - lui x21, 506506 - addi x7, x0, -399 - addi x8, x0, -464 - addi x3, x13, 0 - addi x25, x0, -26 - ld x15, -1745(x1) - srl x24, x27, x8 - addi x23, x14, 0 - la x5, test_memory+945 - addi x4, x0, 1427 - blt x13, x3, crash_backward - addw x18, x2, x2 - addi x21, x0, 383 - addi x13, x0, 1428 - addi x30, x0, -1564 - sll x11, x27, x27 - bne x14, x23, crash_forward - ld x20, -657(x5) - or x19, x30, x30 - srlw x3, x13, x13 - addi x3, x0, 1 - bgeu x28, x16, crash_forward - addi x1, x0, 2045 - addi x24, x0, -1897 - addi x29, x0, 0 - addi x27, x1, 1619 - sll x9, x26, x4 - addi x15, x0, 1 - addi x17, x0, -187 - addi x6, x0, 0 - addi x19, x0, 57 - sub x18, x21, x24 - addi x22, x25, -1450 - sra x16, x4, x10 - sra x10, x7, x17 - addi x12, x0, 2021 - sll x15, x15, 63 - addi x14, x0, -1 - addi x13, x0, 1464 - xor x14, x14, x15 - bltu x29, x6, crash_forward - blt x27, x1, crash_forward - and x11, x29, x14 - xor x9, x19, x19 - sllw x31, x12, x12 - bltu x0, x0, crash_forward - sll x3, x3, 63 - addi x12, x0, 1454 - or x8, x18, x15 - addi x6, x0, -740 - xor x21, x6, x6 - sraw x2, x13, x13 - addi x26, x0, 1 - addi x20, x0, -1 - add x16, x12, x12 - blt x0, x0, crash_backward - addi x22, x0, 1 - blt x11, x8, crash_forward - xor x20, x20, x3 - la x24, test_memory+1896 - sll x26, x26, 63 - and x30, x13, x20 - addi x28, x0, -1 - sll x22, x22, 63 - addi x7, x0, -1 - or x23, x15, x3 - xor x28, x28, x26 - and x5, x15, x28 - addi x25, x0, 1022 - or x4, x13, x26 - xor x7, x7, x22 - lwu x9, -1468(x24) - addi x10, x0, -1821 - and x29, x25, x10 - and x31, x31, x7 - or x17, x29, x22 - bge x17, x31, crash_forward - j reg_dump - -reg_dump: - la x1, loop_count - lw x2, 0(x1) - addi x3, x2, -1 - sw x3, 0(x1) - bnez x2, pseg_0 - la x1, xreg_output_data - sd x0, 0(x1) - sd x2, 16(x1) - sd x3, 24(x1) - sd x4, 32(x1) - sd x5, 40(x1) - sd x6, 48(x1) - sd x7, 56(x1) - sd x8, 64(x1) - sd x9, 72(x1) - sd x10, 80(x1) - sd x11, 88(x1) - sd x12, 96(x1) - sd x13, 104(x1) - sd x14, 112(x1) - sd x15, 120(x1) - sd x16, 128(x1) - sd x17, 136(x1) - sd x18, 144(x1) - sd x20, 160(x1) - sd x21, 168(x1) - sd x22, 176(x1) - sd x23, 184(x1) - sd x25, 200(x1) - sd x26, 208(x1) - sd x28, 224(x1) - sd x29, 232(x1) - sd x30, 240(x1) - sd x31, 248(x1) - - j test_end - -crash_forward: - RVTEST_FAIL - -test_end: - RVTEST_PASS - -RVTEST_CODE_END - - - .data - -hidden_data: - .align 8 -xreg_init_data: -reg_x0_init: .dword 0xffffffffffffff82 -reg_x1_init: .dword 0x75b609608964d156 -reg_x2_init: .dword 0xb9c3da7ac1e3eb8f -reg_x3_init: .dword 0x7f6377f979066dad -reg_x4_init: .dword 0x0800000000000009 -reg_x5_init: .dword 0xffffffffffffff88 -reg_x6_init: .dword 0xa2e849dd61710192 -reg_x7_init: .dword 0xc7c98485479382e1 -reg_x8_init: .dword 0xffffffffffffff86 -reg_x9_init: .dword 0xffffffffffffff80 -reg_x10_init: .dword 0xffffffff80000005 -reg_x11_init: .dword 0x610ae01c2c1cf73a -reg_x12_init: .dword 0xffffffffffffff80 -reg_x13_init: .dword 0x302e8a6544a5321f -reg_x14_init: .dword 0xffffffffffffff83 -reg_x15_init: .dword 0xba90dd1ff64de384 -reg_x16_init: .dword 0xffffffffffffffff -reg_x17_init: .dword 0xffffffff80000005 -reg_x18_init: .dword 0x7ce461945846c309 -reg_x19_init: .dword 0x5dfac35f6bc1748e -reg_x20_init: .dword 0x0000000000000000 -reg_x21_init: .dword 0x0800000000000008 -reg_x22_init: .dword 0xb096e5f42905a093 -reg_x23_init: .dword 0xffffffffffff8000 -reg_x24_init: .dword 0xbf1cd3b072a79670 -reg_x25_init: .dword 0x7bf96f3fca9e5f04 -reg_x26_init: .dword 0x0000000000000000 -reg_x27_init: .dword 0xd1abc73f98de4801 -reg_x28_init: .dword 0xffffffffffffffff -reg_x29_init: .dword 0x115d26a2d75ac58f -reg_x30_init: .dword 0x0000000000000000 -reg_x31_init: .dword 0x1befeebed3a1b5cb - -RVTEST_DATA_BEGIN - - .align 8 -xreg_output_data: -reg_x0_output: .dword 0xf9da5fc85f384e60 -reg_x1_output: .dword 0x2362df40e3520391 -reg_x2_output: .dword 0xdf9395839d811f14 -reg_x3_output: .dword 0x6529213c2dfa1a96 -reg_x4_output: .dword 0xf9a276d7d8faf165 -reg_x5_output: .dword 0xf898dfad009dd12f -reg_x6_output: .dword 0xa67afea29b66a252 -reg_x7_output: .dword 0xe2fc4a60b03f4b3b -reg_x8_output: .dword 0xe2004060d78d0476 -reg_x9_output: .dword 0x765cb95084946f58 -reg_x10_output: .dword 0x7c068ea018257769 -reg_x11_output: .dword 0xbde4fa370c04e6f2 -reg_x12_output: .dword 0x8b2d14abb0841165 -reg_x13_output: .dword 0x4ca26363ce399a7b -reg_x14_output: .dword 0xe44ad78bfdce3f2c -reg_x15_output: .dword 0x66c3bfd05e712dfb -reg_x16_output: .dword 0x11f65231b9fefe29 -reg_x17_output: .dword 0xf7d26872b00141cb -reg_x18_output: .dword 0x1c6e20eccaf214d5 -reg_x19_output: .dword 0x83531ed1e7a47b9c -reg_x20_output: .dword 0x8b9c7021593fed5c -reg_x21_output: .dword 0x2e017cdb9fb19bbe -reg_x22_output: .dword 0x82562239bb29f67f -reg_x23_output: .dword 0x2db20df62458229f -reg_x24_output: .dword 0xee91e0de6971aebc -reg_x25_output: .dword 0xba146552c3c34a91 -reg_x26_output: .dword 0x4d628d60b4f2bdab -reg_x27_output: .dword 0xf24fc58924cc59cf -reg_x28_output: .dword 0xde43c47cde7abfaa -reg_x29_output: .dword 0xd80a2d6129f190c1 -reg_x30_output: .dword 0xbefe6941fcdfa7bc -reg_x31_output: .dword 0x5912ddee35d7387e - -// Memory Blocks - .align 8 -test_memory: - .dword 0xe3566b4b61ffdbae, 0x92e6ade076ec9593 - .dword 0x41123c31ec656e7b, 0xc7d5be18f926c302 - .dword 0x9cffa8448af81cf1, 0x79f7637fab5fb98d - .dword 0xdfa10678b0bff093, 0x75925a14da080733 - .dword 0xa368f39e3a74acc1, 0x406c95462ebdfafb - .dword 0x2a1a0cd464b46a16, 0xf6d74180644548ef - .dword 0x26435d3c9a7e0411, 0x7f80cb082c866a6b - .dword 0xd02972f2ae323cf6, 0xa55ffe0a62ed3e97 - .dword 0xcdf74f3c3628bbf6, 0xe0a893f274f2af31 - .dword 0x3d11a5fc6714498d, 0xc5eac1f9d5155d8f - .dword 0x091a2069a443ee2b, 0x6a849d037e419be4 - .dword 0x0bd79705be84d716, 0xd8a566a7b6e936c1 - .dword 0xbb1376ca4843258e, 0x8890178fd80fd2df - .dword 0x6dcbc59eaec60c31, 0xf1cbbb045598e31b - .dword 0x341c7a11bf45dea0, 0xaac56fc15e707ac1 - .dword 0x843a1a469960f763, 0x5151220e64f8800c - .dword 0x7602d62ca95e9809, 0x07b3530ebeb802ed - .dword 0x3d4a90f359fd2793, 0xb1af815b55e2bc0b - .dword 0x0c598db9a17b7312, 0x20bc06cd6c2af80b - .dword 0x7b5cb38b2662d48f, 0xef357f977cb07310 - .dword 0x2a019c8a6092642a, 0x25790e9bf702e885 - .dword 0x2d67e46c20699785, 0xba6e12fd6f575b19 - .dword 0x51346a253af2f362, 0x387d22f3d47b590b - .dword 0x862a78e594d5b38a, 0x017b5fe0a301c0a7 - .dword 0x867a0c4660df8cf0, 0xe4ee77a20ad8c90f - .dword 0xaf31a3bd8065ee16, 0x9d7ee726b931533e - .dword 0xf235595a8dd061b0, 0xc9b35243e09bc74a - .dword 0x2c042fae1a93f786, 0x9a6904c91cbf01e9 - .dword 0xdfafcb061c01d79e, 0x9c2af0cea2521635 - .dword 0xa0fa09e0d3c96399, 0x20c9be538749e7b3 - .dword 0x3bcf309dc4308a5d, 0x29acc009ceb7e091 - .dword 0xd88a9c776b0b31f4, 0xa27ce16ac7e7482e - .dword 0x10df31aeaba4dbb3, 0xec47e2107d1afde0 - .dword 0xb11bf9077d5de69e, 0x6c4b7242ac259bf0 - .dword 0x0018a075c4f0140b, 0x1c7d04d19e3246e9 - .dword 0x149cd31837643284, 0x27dc6a263cb4ad12 - .dword 0x64d09c64f1fd12f1, 0xe6ec8892cbdafa38 - .dword 0x3a734aa59ffa2bf6, 0x2a8ec5ef9744c3b0 - .dword 0xa07984a4c8568f9a, 0x9232f669b86e309b - .dword 0x3b8a86a448cf1728, 0xa716e4948f6ee26b - .dword 0x09dfba8f52c4e959, 0xee6dc6c2f2a061a6 - .dword 0x6f891f74103fbeb2, 0xf8f93598e8b812ea - .dword 0x1d4c3431ada5882b, 0x5d2277dd9f1cf830 - .dword 0x217a597005f35c11, 0x4a3c37966c01c254 - .dword 0xd676ded0e59dcd2c, 0x1d81f44efd4ff6d4 - .dword 0xe9742f6571fd1024, 0xc4ebc6ba52f92dd7 - .dword 0x9072d162128b9320, 0x4e42497c090fac71 - .dword 0x60042d137483ebaf, 0x5b47bb458457df25 - .dword 0x62fe4f0f42d53eeb, 0x4388ae224f1878aa - .dword 0xef6d19adb23387db, 0xf2b7d80fe40738f2 - .dword 0xb7e099b96d7b6019, 0x649dd8d1168ca067 - .dword 0x3dff726007f72eb4, 0x66df09018a791377 - .dword 0xbe3f94704b8de157, 0xc266a66b55ea3252 - .dword 0x0c16b4c54ec193aa, 0x6b67f1980ec768f2 - .dword 0x751735fbabe6c8f8, 0xfcdb10a88628fb5b - .dword 0x6785796cce631c11, 0xcc64cb662f6d1224 - .dword 0x413ccb578e4c8971, 0xdaf574964af28b35 - .dword 0xc57a5e5d1cb0b7a1, 0xee5c94900da992d1 - .dword 0x66980a31155de1dc, 0x2dd42912132648d6 - .dword 0xeb27c18dcc7d48f6, 0xb85f8e50dfe1f643 - .dword 0x477bf36b28e94e79, 0x35076550491b96fb - .dword 0x8cb84b6d7e279e11, 0x43bd0b747790bbc8 - .dword 0x0049859c74920929, 0xbf457758665408a2 - .dword 0x315a495899bef8d5, 0xc6348ede3796d330 - -.align 8 -loop_count: .word 0x40 - -RVTEST_DATA_END diff --git a/failedtests/test_1498880354372.S b/failedtests/test_1498880354372.S deleted file mode 100644 index 19a3e5a14d..0000000000 --- a/failedtests/test_1498880354372.S +++ /dev/null @@ -1,678 +0,0 @@ -// random assembly code generated by RISC-V torture test generator -// nseqs = 200 -// memsize = 1024 - -#include "riscv_test.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - j test_start - -crash_backward: - RVTEST_FAIL - -test_start: - -xreg_init: - la x31, xreg_init_data - ld x0, 0(x31) - ld x1, 8(x31) - ld x2, 16(x31) - ld x3, 24(x31) - ld x4, 32(x31) - ld x5, 40(x31) - ld x6, 48(x31) - ld x7, 56(x31) - ld x8, 64(x31) - ld x9, 72(x31) - ld x10, 80(x31) - ld x11, 88(x31) - ld x12, 96(x31) - ld x13, 104(x31) - ld x14, 112(x31) - ld x15, 120(x31) - ld x16, 128(x31) - ld x17, 136(x31) - ld x18, 144(x31) - ld x19, 152(x31) - ld x20, 160(x31) - ld x21, 168(x31) - ld x22, 176(x31) - ld x23, 184(x31) - ld x24, 192(x31) - ld x25, 200(x31) - ld x26, 208(x31) - ld x27, 216(x31) - ld x28, 224(x31) - ld x29, 232(x31) - ld x30, 240(x31) - ld x31, 248(x31) - - j pseg_0 - -pseg_0: - addi x24, x0, -441 - blt x22, x22, crash_backward - la x14, test_memory+1548 - or x27, x7, x6 - xor x18, x24, x2 - sub x21, x18, x18 - addi x15, x0, -1015 - addi x26, x0, -792 - xor x30, x25, x8 - la x12, test_memory-1349 - addi x20, x0, 1 - sll x20, x20, 63 - addi x23, x0, 1 - sra x25, x26, x26 - addi x8, x0, -1535 - addi x9, x0, -1298 - sraiw x19, x23, 19 - addi x3, x0, 1 - sll x3, x3, 63 - sll x23, x23, 63 - lhu x4, 1355(x12) - addi x1, x24, -774 - addi x7, x0, -1 - sllw x26, x8, x8 - bne x0, x0, crash_forward - sra x22, x15, x9 - xori x25, x14, 1318 - add x13, x8, x8 - xor x7, x7, x3 - and x16, x20, x7 - slli x29, x28, 7 - addi x21, x0, -42 - addi x2, x0, -1 - addi x26, x0, 1 - sra x27, x9, x0 - lh x6, -722(x14) - xor x2, x2, x23 - addi x10, x0, -1 - sll x26, x26, 63 - or x5, x13, x3 - addi x9, x0, 1697 - addi x18, x0, -1754 - xor x10, x10, x20 - and x28, x4, x2 - and x17, x3, x10 - or x11, x28, x23 - addi x12, x0, 1783 - blt x16, x5, crash_forward - addi x15, x0, -1 - la x1, test_memory+2168 - addi x5, x0, -786 - sltu x25, x9, x28 - lw x13, -1828(x1) - srlw x30, x21, x18 - addi x16, x0, 1139 - addi x19, x0, 753 - addi x27, x0, 0 - sub x14, x10, x7 - subw x29, x9, x9 - or x31, x13, x20 - slt x4, x12, x19 - sllw x7, x5, x16 - addi x6, x0, 0 - slt x5, x6, x1 - addi x19, x0, -202 - addi x7, x0, -623 - and x24, x4, x14 - la x23, test_memory+2884 - addi x18, x0, 0 - sra x5, x2, x2 - addi x13, x0, 0 - la x17, test_memory+772 - addi x16, x4, 0 - xor x15, x15, x26 - and x8, x22, x15 - slt x3, x11, x12 - or x22, x8, x26 - sraw x12, x7, x7 - addi x31, x0, 0 - addi x10, x0, 940 - addi x1, x16, 0 - addi x29, x0, 100 - bltu x16, x1, crash_forward - la x28, test_memory+362 - la x5, test_memory+1494 - addi x14, x0, 539 - addi x2, x10, 1554 - slt x30, x19, x19 - srliw x26, x20, 9 - or x18, x22, x28 - addi x7, x0, 1569 - addi x8, x0, -1120 - sll x4, x19, x24 - sh x12, -1106(x5) - addi x22, x0, 1271 - addi x6, x0, -1232 - add x13, x1, x1 - subw x2, x0, x0 - addi x25, x0, 628 - addi x10, x8, -1580 - ori x13, x5, -2000 - bgeu x10, x8, crash_forward - addi x13, x0, 439 - addw x4, x4, x9 - xor x21, x29, x29 - lwu x24, -384(x17) - addi x26, x0, 1903 - addi x18, x13, 649 - sub x15, x6, x6 - slt x16, x22, x22 - bltu x18, x13, crash_forward - xor x9, x14, x25 - addi x19, x0, 1509 - addi x3, x0, -360 - addi x10, x0, -1325 - sltu x2, x26, x26 - addi x8, x10, -756 - and x12, x21, x2 - addi x4, x0, 186 - sb x9, 557(x28) - addi x20, x0, 0 - addi x14, x0, 1210 - la x18, test_memory+906 - sll x27, x19, x3 - xor x9, x14, x14 - addi x16, x0, -474 - blt x3, x3, crash_backward - lb x11, -1969(x23) - ld x22, -274(x18) - addi x27, x0, -821 - la x24, test_memory+1776 - addi x17, x16, -1119 - addw x2, x11, x11 - srli x6, x31, 22 - addi x8, x0, -1236 - addi x5, x0, -1905 - la x25, test_memory-641 - addi x1, x0, 501 - addi x13, x5, -1118 - bge x17, x16, crash_backward - sb x6, 1591(x25) - addi x19, x0, 1 - sll x19, x19, 63 - subw x3, x18, x0 - srl x15, x19, x15 - sltiu x12, x20, 885 - slt x28, x27, x8 - blt x5, x13, crash_backward - sltu x29, x14, x17 - lhu x26, -1716(x24) - sub x21, x4, x4 - la x10, test_memory+682 - slt x30, x7, x1 - sb x26, -40(x10) - addi x9, x0, -1 - xor x9, x9, x19 - la x7, test_memory+1982 - and x18, x31, x9 - sltu x27, x20, x16 - addi x28, x0, 1 - addi x1, x3, 0 - la x4, test_memory-640 - sraw x31, x19, x19 - lui x5, 187465 - addi x15, x0, 1934 - srl x11, x14, x17 - srl x23, x15, x15 - addi x8, x1, 0 - addi x10, x0, -73 - srlw x3, x10, x10 - addi x23, x0, 1 - or x14, x30, x19 - addi x29, x0, 0 - la x12, test_memory-1333 - lbu x2, -1285(x7) - lh x25, 1172(x4) - addi x22, x0, 1373 - sh x15, 1861(x12) - addi x20, x0, 0 - sll x28, x28, 63 - sll x23, x23, 63 - addi x31, x0, -1 - addi x17, x0, 1325 - addi x6, x0, -366 - srl x26, x6, x6 - xor x31, x31, x23 - addi x2, x0, -867 - addi x24, x0, 1 - addi x26, x29, 0 - addi x15, x2, -1208 - addi x20, x26, 0 - slti x6, x19, -537 - beq x2, x15, crash_forward - addi x13, x0, -1 - sub x21, x22, x17 - srlw x5, x30, x30 - bltu x26, x20, crash_forward - addi x8, x0, 374 - xor x13, x13, x28 - and x30, x2, x13 - sll x3, x8, x8 - addw x11, x30, x30 - sll x24, x24, 63 - and x14, x17, x17 - or x16, x30, x28 - la x20, test_memory+940 - sb x27, -753(x20) - and x27, x1, x31 - addi x18, x0, 1373 - blt x24, x24, crash_forward - addi x4, x18, 915 - bltu x25, x25, crash_forward - la x15, test_memory-1197 - addi x7, x0, -1 - xor x7, x7, x24 - addi x5, x0, -1960 - sb x18, 2029(x15) - addi x6, x0, 1 - and x29, x27, x7 - addi x26, x5, -1919 - or x10, x30, x23 - sltu x22, x20, x20 - addi x9, x0, 735 - addi x17, x0, 1 - addi x8, x0, -388 - or x12, x17, x24 - sll x17, x17, 63 - sll x6, x6, 63 - la x15, test_memory-1613 - sltu x10, x20, x7 - sllw x28, x0, x25 - addi x1, x0, -1 - addi x20, x0, 983 - addi x31, x0, -594 - slliw x26, x13, 11 - addi x4, x0, 1582 - sra x5, x20, x4 - xor x1, x1, x6 - lwu x22, 1793(x15) - la x16, test_memory+423 - sllw x2, x9, x8 - addi x27, x0, -1211 - addi x11, x0, -1 - and x19, x20, x1 - la x30, test_memory-1140 - slt x23, x31, x27 - lhu x14, 27(x16) - or x21, x24, x6 - addi x24, x15, 0 - sll x22, x3, x1 - addi x9, x0, -261 - bltu x0, x0, crash_backward - addw x15, x29, x29 - addi x19, x0, -1403 - addi x12, x24, 0 - addi x14, x0, -1979 - addi x18, x0, 1821 - srl x15, x7, x7 - sltu x28, x9, x9 - addi x29, x0, 1442 - la x16, test_memory+379 - lh x2, -367(x16) - addi x6, x0, 1892 - addi x4, x0, -640 - slli x27, x12, 31 - addi x20, x6, 642 - lh x13, 1658(x30) - addi x1, x0, -1456 - la x16, test_memory+494 - addi x2, x22, 1049 - addi x7, x0, -449 - subw x21, x19, x18 - sll x10, x4, x7 - xori x9, x16, 1035 - addi x5, x29, 0 - slti x28, x0, -1164 - srl x15, x31, x15 - xori x31, x28, 67 - sh x29, -220(x16) - addi x9, x0, -931 - addi x21, x0, 237 - srl x19, x9, x19 - la x2, test_memory-1139 - add x22, x29, x1 - addi x28, x0, -2032 - srl x6, x15, x15 - addi x23, x5, 0 - srl x24, x9, x21 - la x30, test_memory-570 - subw x5, x11, x20 - addi x27, x0, -1649 - lbu x20, 1545(x30) - addi x18, x0, -1125 - addi x7, x0, -988 - or x4, x18, x18 - addi x26, x0, 1915 - la x31, test_memory+1869 - addi x24, x0, 110 - sll x13, x28, x27 - subw x8, x14, x26 - slt x16, x22, x22 - xor x11, x11, x17 - lwu x10, 1379(x2) - addi x23, x0, 1214 - lwu x1, -1729(x31) - sraw x5, x28, x28 - addi x31, x0, 1 - sll x22, x23, x23 - addi x28, x0, 1849 - xor x12, x7, x7 - sll x31, x31, 63 - addi x19, x0, -667 - addi x6, x19, -952 - and x25, x6, x11 - addi x9, x0, 1753 - addi x8, x0, -247 - slti x15, x24, 844 - addiw x2, x29, -505 - bne x0, x0, crash_backward - addi x27, x0, -1 - blt x19, x6, crash_forward - addi x10, x0, 1 - addi x14, x0, 1 - la x4, test_memory+1223 - sll x10, x10, 63 - addi x22, x0, -1 - sll x14, x14, 63 - xor x27, x27, x31 - sraw x7, x27, x20 - or x21, x24, x9 - lbu x16, -289(x4) - addw x30, x28, x8 - and x13, x9, x27 - or x3, x25, x17 - addi x26, x0, -1 - sltu x29, x15, x3 - xor x22, x22, x10 - srli x5, x1, 17 - xor x26, x26, x14 - bgeu x25, x3, crash_forward - or x1, x13, x31 - and x20, x28, x26 - or x18, x20, x14 - and x15, x24, x22 - blt x20, x18, crash_forward - or x12, x15, x10 - addi x13, x0, -956 - srl x1, x12, x12 - addi x31, x0, 1998 - sll x29, x13, x31 - addi x25, x0, 0 - la x5, test_memory+1974 - sub x11, x8, x29 - addi x7, x0, 1083 - addi x3, x0, 1 - addi x13, x0, 0 - addi x12, x0, 1 - sll x12, x12, 63 - la x18, test_memory+1514 - sd x16, -1346(x18) - or x8, x26, x26 - sraw x16, x7, x7 - addi x10, x0, 547 - lwu x15, -1802(x5) - add x19, x22, x22 - srl x17, x19, x19 - addi x30, x0, -1 - xor x30, x30, x12 - addi x8, x0, 1139 - la x20, test_memory+1047 - sll x3, x3, 63 - addi x27, x0, -757 - addi x29, x0, -1 - addi x7, x0, 1 - bltu x25, x13, crash_forward - addi x21, x0, -1493 - addi x23, x10, 1036 - addi x14, x0, -738 - bne x0, x0, crash_forward - la x6, test_memory+2381 - and x2, x27, x14 - and x11, x24, x30 - addi x16, x0, 0 - xor x29, x29, x3 - ld x26, -191(x20) - addi x9, x0, 1927 - addi x15, x0, 0 - blt x23, x10, crash_forward - xor x19, x8, x8 - srlw x4, x21, x9 - addi x25, x0, -1105 - and x28, x26, x29 - or x22, x23, x12 - bltu x22, x11, crash_forward - bltu x16, x15, crash_forward - addi x1, x0, 1126 - and x13, x25, x1 - sll x7, x7, 63 - and x11, x8, x9 - addw x21, x27, x27 - and x8, x23, x4 - xor x19, x2, x2 - sub x2, x23, x3 - addi x13, x0, 1905 - addi x5, x0, -1 - lw x24, -1777(x6) - xor x23, x22, x22 - addi x12, x0, 1 - addi x25, x0, -1455 - xor x5, x5, x7 - and x17, x27, x5 - or x31, x28, x3 - sub x20, x25, x25 - or x18, x17, x7 - addi x26, x0, -854 - beq x28, x31, crash_backward - sll x12, x12, 63 - bltu x18, x17, crash_backward - srl x15, x13, x26 - addi x22, x0, -1 - addi x30, x0, 304 - addi x16, x0, 1624 - xor x22, x22, x12 - slt x10, x30, x16 - and x9, x27, x22 - or x14, x9, x12 - j reg_dump - -reg_dump: - la x1, loop_count - lw x2, 0(x1) - addi x3, x2, -1 - sw x3, 0(x1) - bnez x2, pseg_0 - la x1, xreg_output_data - sd x0, 0(x1) - sd x2, 16(x1) - sd x3, 24(x1) - sd x4, 32(x1) - sd x5, 40(x1) - sd x7, 56(x1) - sd x8, 64(x1) - sd x9, 72(x1) - sd x10, 80(x1) - sd x11, 88(x1) - sd x12, 96(x1) - sd x13, 104(x1) - sd x14, 112(x1) - sd x15, 120(x1) - sd x16, 128(x1) - sd x17, 136(x1) - sd x18, 144(x1) - sd x19, 152(x1) - sd x20, 160(x1) - sd x21, 168(x1) - sd x22, 176(x1) - sd x23, 184(x1) - sd x24, 192(x1) - sd x25, 200(x1) - sd x26, 208(x1) - sd x27, 216(x1) - sd x28, 224(x1) - sd x29, 232(x1) - sd x30, 240(x1) - sd x31, 248(x1) - - j test_end - -crash_forward: - RVTEST_FAIL - -test_end: - RVTEST_PASS - -RVTEST_CODE_END - - - .data - -hidden_data: - .align 8 -xreg_init_data: -reg_x0_init: .dword 0xff92ffc2ca0bbe7b -reg_x1_init: .dword 0x166649dc02ff3f4f -reg_x2_init: .dword 0xffffffffffffffff -reg_x3_init: .dword 0xe0ae5d9fdd4809b8 -reg_x4_init: .dword 0x11309b6128ec1610 -reg_x5_init: .dword 0x0000000000000000 -reg_x6_init: .dword 0xeb59007640bc57dc -reg_x7_init: .dword 0xedb999fdec848259 -reg_x8_init: .dword 0x81e0012642fd86f9 -reg_x9_init: .dword 0x0000000000000000 -reg_x10_init: .dword 0x1b803d493f09b644 -reg_x11_init: .dword 0x0000000000000005 -reg_x12_init: .dword 0x0000000000000000 -reg_x13_init: .dword 0x118963d6f1549a11 -reg_x14_init: .dword 0xb3ab4dc53714316c -reg_x15_init: .dword 0x0000000000000000 -reg_x16_init: .dword 0x409e57b75f96bfc8 -reg_x17_init: .dword 0x2846e77e62c716da -reg_x18_init: .dword 0x2b16f36ebe2875d0 -reg_x19_init: .dword 0xffffffffffffff80 -reg_x20_init: .dword 0x0000000000000000 -reg_x21_init: .dword 0x1ed4f77fb27dd3dc -reg_x22_init: .dword 0x0000000000000001 -reg_x23_init: .dword 0xe5973f36dbfb7072 -reg_x24_init: .dword 0x93f22207eeadece8 -reg_x25_init: .dword 0x4c54a10a1fb7c234 -reg_x26_init: .dword 0x12b9c4f9efee6177 -reg_x27_init: .dword 0x39f6a8aabab7b7b8 -reg_x28_init: .dword 0xffffffff80000003 -reg_x29_init: .dword 0x0800000000000007 -reg_x30_init: .dword 0x027bd1a95f66eb34 -reg_x31_init: .dword 0xffffffffffffffff - -RVTEST_DATA_BEGIN - - .align 8 -xreg_output_data: -reg_x0_output: .dword 0xd08d4f4137a984b9 -reg_x1_output: .dword 0xdf827c90a30532bc -reg_x2_output: .dword 0xaa13f8047e432244 -reg_x3_output: .dword 0x2319744405965cfc -reg_x4_output: .dword 0x9a821ea2984f0e6b -reg_x5_output: .dword 0xc5fc6106a4903a5a -reg_x6_output: .dword 0x2043d910ce73b8d1 -reg_x7_output: .dword 0x888f3402d080648b -reg_x8_output: .dword 0x18e23e25962fb70d -reg_x9_output: .dword 0x3fdc45bd116fa5c3 -reg_x10_output: .dword 0xdca844d6538585d1 -reg_x11_output: .dword 0xe06bea68095f987a -reg_x12_output: .dword 0xcc59e2a4e03fb84d -reg_x13_output: .dword 0xc1107773ae9bff73 -reg_x14_output: .dword 0xd69a1d5a763e39d5 -reg_x15_output: .dword 0x81f48e6a577b19f9 -reg_x16_output: .dword 0xeb3403f26e2385c0 -reg_x17_output: .dword 0x1ac2c0faf918786b -reg_x18_output: .dword 0xed45c2d6c7c2f993 -reg_x19_output: .dword 0x009ae254894a14fb -reg_x20_output: .dword 0x698c4751041fa55f -reg_x21_output: .dword 0xbafa99b7d1c7b4b2 -reg_x22_output: .dword 0xc701263c7bdd3e67 -reg_x23_output: .dword 0x13040a489b78d4b6 -reg_x24_output: .dword 0x6ce3b9faf6fb1805 -reg_x25_output: .dword 0xd3e6a425dd5da7cf -reg_x26_output: .dword 0x3d61ababe5cb46cd -reg_x27_output: .dword 0xb2db72b93ecbe827 -reg_x28_output: .dword 0x06a25b9ca59651f2 -reg_x29_output: .dword 0xda677c5179008151 -reg_x30_output: .dword 0x203bdcfcc77e16e8 -reg_x31_output: .dword 0x04ac06edf493568c - -// Memory Blocks - .align 8 -test_memory: - .dword 0x384f78d65438c34b, 0x64b5d65be46aa947 - .dword 0x74f6ec399d6708ff, 0x8439b7825d9fe3e8 - .dword 0x138ad5bbd3d6f097, 0xf33decfaca9fccc8 - .dword 0xdade06227336edfa, 0x471550e523ec6582 - .dword 0x3f10a857a5d31b43, 0x970a3ff8a286fa6d - .dword 0x685974a63830bde9, 0xe464a1dbfb6d2666 - .dword 0x495263251afa7a1f, 0xba57a2b478fbced2 - .dword 0x2839916dfbf1d87d, 0xb618f1fc92b75be2 - .dword 0xf86e4f9542c101e0, 0x892c9a9b9628b119 - .dword 0x597d8854f6d1d58d, 0xb50dc832f072aa0b - .dword 0x368ff88c5dfdbd9c, 0x990e0db7183c1f66 - .dword 0xb73fe9e8c33be593, 0x26ca013fa6c6b836 - .dword 0x510364e2eea9b751, 0x782b41200dcb0b64 - .dword 0x59b30debb7a3c22d, 0xb0dd36367a36d57f - .dword 0xff8521e66c63705e, 0xbd9b2782d27246be - .dword 0x345745d5e2f82e9c, 0x2b1372fc959dad45 - .dword 0x10991dd61bb8ea07, 0x0d84ffa37088ffa7 - .dword 0xd0d4df4fc7b50848, 0xb6f93cd1293b0bac - .dword 0xa6f25267847a3df5, 0x454e42d492f64d53 - .dword 0xa923f6b993f6e739, 0x3869e8c15f05b219 - .dword 0xab353f448996c6b4, 0xad27e382227bcc7b - .dword 0x6eec19a63f324ea0, 0x48224230e2b33bba - .dword 0x749f34883346d834, 0x9d94dba902074bdd - .dword 0xa145b959a8706d4c, 0x1e918158d82811fc - .dword 0xb25c6d42d2840849, 0x80c40b5a7ddd88ba - .dword 0x0d476d518a336e36, 0xc26291c2ff417113 - .dword 0x4e96f9fa4312072b, 0x78d7673be9affb57 - .dword 0x390905bcdb6458f6, 0xfb77a8d0f02b7c75 - .dword 0x5b887b25b79a07f7, 0x3d72770799efb37c - .dword 0x44066dfafeec824a, 0x28522c33cfb5635f - .dword 0x1a18abb2a99ab92b, 0xf42a240adcef44f8 - .dword 0x7b0c5f24f5dc8c96, 0x1920e8759755954f - .dword 0xd0d2bb823d2ecd2e, 0xe0afd7a7d8a5c41b - .dword 0xb918e284a242f85f, 0x80ee977210d00688 - .dword 0x793b79e7a6ec12c6, 0xcad1e9d43a24d23a - .dword 0xb1d9a4190b1444cf, 0x62aab6d5f1b08491 - .dword 0x40d2502ce85d1d9f, 0xe1ab5f987413ba2e - .dword 0x6db215157bc6a035, 0x1d06aea8170b1ab6 - .dword 0x7a470c0d85d77ecb, 0xb49cf992e1c19cd5 - .dword 0x92735e5e4c832881, 0x5d6147bdbe348685 - .dword 0xe2ae7a3baeb08d3d, 0x93e9927584a0ad90 - .dword 0x8f30230f1a0ebbcc, 0x4f3a7243bb64bc53 - .dword 0x0dbfd0daaf12be4d, 0x4c0fcd853a3c7ec4 - .dword 0x64d612f836cc58ce, 0xd2e95c3a1b757bb5 - .dword 0x6364ea0468f58e37, 0xb83b151d38fd5e59 - .dword 0x90774d1a287b0f66, 0x638ed7f4522ef407 - .dword 0x58274e42fff9f89b, 0x1965e9285a4ac23e - .dword 0x8f6d922c18918116, 0x997e129812d478e8 - .dword 0x71440f18da2d80fe, 0x79077daa38dec4e2 - .dword 0x90c147193758f185, 0xe3959aa334e346bc - .dword 0x3470717a95f5cb48, 0x9f66a938725cb1bd - .dword 0x2a7e47803429e6fb, 0x2742b66493355729 - .dword 0x5a9968509ba6c445, 0x4eec237c6b7ca1c5 - .dword 0x54e08833176c5ae8, 0x74290a7fa7fa459a - .dword 0x7c27def87f855a24, 0x870e13b2ce5e27f9 - .dword 0x808289b7fd3d7a5d, 0xdda8906cc43843bf - .dword 0xf493d3c17f38c4fb, 0x8aaeef2d9ad40dda - .dword 0x57f79acb69dcf691, 0xd9bbdcf625c71e0b - .dword 0xea50426f03ec5f40, 0x4709a7d408bb1fed - .dword 0xa07beada3343e55d, 0x39e8b6bcdaf75035 - .dword 0x3f59debd38a40e51, 0x81852a9eacae0a3a - .dword 0xb8a46c87458731c1, 0xf03cfcb4575729b8 - .dword 0xadf29ed672853aee, 0xe4092e1b47a844d0 - .dword 0x67388829d9e79c5d, 0x5791dca2d9480252 - -.align 8 -loop_count: .word 0x40 - -RVTEST_DATA_END diff --git a/fpga/.gitignore b/fpga/.gitignore index c7bcdbac20..284dfa6775 100644 --- a/fpga/.gitignore +++ b/fpga/.gitignore @@ -1,9 +1,13 @@ .* !.gitignore +/reports +scripts/add_sources.tcl vivado* *.cache *.hw *.ip_user_files +*.sim *.runs *.srcs -*.xpr \ No newline at end of file +*.xpr +*.mif \ No newline at end of file diff --git a/fpga/Makefile b/fpga/Makefile new file mode 100644 index 0000000000..c2813b7601 --- /dev/null +++ b/fpga/Makefile @@ -0,0 +1,45 @@ +VIVADO ?= vivado +VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl + +work-dir := work-fpga +bit := $(work-dir)/ariane_xilinx.bit +mcs := $(work-dir)/ariane_xilinx.mcs +ip-dir := xilinx +ips := xlnx_axi_clock_converter.xci \ + xlnx_axi_dwidth_converter.xci \ + xlnx_axi_quad_spi.xci \ + xlnx_axi_gpio.xci \ + xlnx_clk_gen.xci \ + xlnx_axi_ethernetlite.xci \ + xlnx_mig_7_ddr3.xci + +ips := $(addprefix $(work-dir)/, $(ips)) +ips-target := $(join $(addsuffix /ip/, $(addprefix $(ip-dir)/, $(basename $(ips)))), $(ips)) + +all: $(mcs) + +# Generate mcs from bitstream +$(mcs): $(bit) + $(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^ + +$(bit): $(ips) + mkdir -p $(work-dir) + $(VIVADO) $(VIVADOFLAGS) -source scripts/run.tcl + cp ariane.runs/impl_1/ariane_xilinx* ./$(work-dir) + +$(ips): %.xci : + mkdir -p $(work-dir) + @echo Generating $(@F) + @cd $(ip-dir)/$(basename $(@F)) && make clean && make + @cp $(ip-dir)/$(basename $(@F))/ip/$(@F) $@ + +mcs: $(mcs) + +program: + $(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl + +clean: + rm -rf *.log *.jou *.str *.mif *.xpr $(work-dir) ariane.cache ariane.hw ariane.ip_user_files + +.PHONY: + clean diff --git a/fpga/ariane.cfg b/fpga/ariane.cfg new file mode 100644 index 0000000000..2edcec0e9e --- /dev/null +++ b/fpga/ariane.cfg @@ -0,0 +1,29 @@ +adapter_khz 1000 + +interface ftdi +# ftdi_device_desc "Olimex Ltd. ARM-USB-OCD-H JTAG+RS232" +ftdi_vid_pid 0x15ba 0x002b + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 + +# prefer to use sba for system bus access +riscv set_prefer_sba off + +init +halt +echo "Ready for Remote Connections" diff --git a/fpga/ariane.xdc b/fpga/ariane.xdc deleted file mode 100644 index 329269aeeb..0000000000 --- a/fpga/ariane.xdc +++ /dev/null @@ -1,33 +0,0 @@ -set_property PACKAGE_PIN AM13 [get_ports sys_rst] -set_property IOSTANDARD LVCMOS33 [get_ports sys_rst] -set_property PACKAGE_PIN A20 [get_ports tck] -set_property IOSTANDARD LVCMOS33 [get_ports tck] -set_property PACKAGE_PIN B20 [get_ports tdi] -set_property PACKAGE_PIN A22 [get_ports tdo] -set_property PACKAGE_PIN A21 [get_ports tms] -set_property PACKAGE_PIN B21 [get_ports trst_n] -set_property IOSTANDARD LVCMOS33 [get_ports tdi] -set_property IOSTANDARD LVCMOS33 [get_ports tdo] -set_property IOSTANDARD LVCMOS33 [get_ports tms] -set_property IOSTANDARD LVCMOS33 [get_ports trst_n] -# accept sub-optimal placement -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF_inst/O] - - -create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck] -set_input_jitter tck 15.000 - -#################################################################################### -# Constraints from file : 'axi_clock_converter_0_clocks.xdc' -#################################################################################### - -set_max_delay -datapath_only -from [get_clocks tck] -to [get_clocks mmcm_clkout0] 5.000 -set_max_delay -datapath_only -from [get_clocks mmcm_clkout0] -to [get_clocks tck] 5.000 - -set_max_delay -datapath_only -from [get_clocks tck] -to [get_clocks c0_sys_clk_p] 5.000 -set_max_delay -datapath_only -from [get_clocks c0_sys_clk_p] -to [get_clocks tck] 5.000 - -set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] -set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] -set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -connect_debug_port dbg_hub/clk [get_nets clk_1] diff --git a/fpga/ariane_tiny.cfg b/fpga/ariane_tiny.cfg new file mode 100644 index 0000000000..dc5d3d273d --- /dev/null +++ b/fpga/ariane_tiny.cfg @@ -0,0 +1,29 @@ +adapter_khz 1000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 + +# prefer to use sba for system bus access +riscv set_prefer_sba off + +init +halt +echo "Ready for Remote Connections" diff --git a/fpga/ariane_xilinx.sv b/fpga/ariane_xilinx.sv deleted file mode 100644 index a48a78a872..0000000000 --- a/fpga/ariane_xilinx.sv +++ /dev/null @@ -1,543 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module ariane_xilinx ( - input logic c0_sys_clk_p, // Clock - input logic c0_sys_clk_n, // Clock - input logic sys_rst, // active high reset - output logic c0_ddr4_act_n, - output logic [16:0] c0_ddr4_adr, - output logic [1:0] c0_ddr4_ba, - output logic [0:0] c0_ddr4_bg, - output logic [0:0] c0_ddr4_cke, - output logic [0:0] c0_ddr4_odt, - output logic [0:0] c0_ddr4_cs_n, - output logic [0:0] c0_ddr4_ck_t, - output logic [0:0] c0_ddr4_ck_c, - output logic c0_ddr4_reset_n, - inout logic [1:0] c0_ddr4_dm_dbi_n, - inout logic [15:0] c0_ddr4_dq, - inout logic [1:0] c0_ddr4_dqs_c, - inout logic [1:0] c0_ddr4_dqs_t, - input logic tck, - input logic tms, - input logic trst_n, - input logic tdi, - output logic tdo -); - -localparam logic [63:0] RomBase = 64'h10000; -localparam NBSlave = 4; // debug, Instruction fetch, data bypass, data -localparam NBMaster = 3; // debug, ROM, RAM - -localparam logic [63:0] CacheStartAddr = 64'h8000_0000; -localparam AxiAddrWidth = 64; -localparam AxiDataWidth = 64; -localparam AxiIdWidthMaster = 2; -localparam AxiIdWidthSlaves = AxiIdWidthMaster + $clog2(NBSlave); // 4 -localparam AxiUserWidth = 1; - -AXI_BUS #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMaster ), - .AXI_USER_WIDTH ( AxiUserWidth ) -) slave[NBSlave-1:0](); - -AXI_BUS #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMaster ), - .AXI_USER_WIDTH ( AxiUserWidth ) -) slave_slice[NBSlave-1:0](); - -AXI_BUS #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) -) master[NBMaster-1:0](); - -// disable test-enable -logic test_en; -logic ndmreset; -logic ndmreset_n; -logic debug_req; -logic clk; -logic rst_n; - -// DDR -logic c0_ddr4_ui_clk; -logic c0_init_calib_complete; // left open -logic c0_ddr4_ui_clk_sync_rst; -logic addn_ui_clkout1; - -logic [3:0] s_axi_awid; -logic [31:0] s_axi_awaddr; -logic [7:0] s_axi_awlen; -logic [2:0] s_axi_awsize; -logic [1:0] s_axi_awburst; -logic [0:0] s_axi_awlock; -logic [3:0] s_axi_awcache; -logic [2:0] s_axi_awprot; -logic [3:0] s_axi_awregion; -logic [3:0] s_axi_awqos; -logic s_axi_awvalid; -logic s_axi_awready; -logic [63:0] s_axi_wdata; -logic [7:0] s_axi_wstrb; -logic s_axi_wlast; -logic s_axi_wvalid; -logic s_axi_wready; -logic [3:0] s_axi_bid; -logic [1:0] s_axi_bresp; -logic s_axi_bvalid; -logic s_axi_bready; -logic [3:0] s_axi_arid; -logic [31:0] s_axi_araddr; -logic [7:0] s_axi_arlen; -logic [2:0] s_axi_arsize; -logic [1:0] s_axi_arburst; -logic [0:0] s_axi_arlock; -logic [3:0] s_axi_arcache; -logic [2:0] s_axi_arprot; -logic [3:0] s_axi_arregion; -logic [3:0] s_axi_arqos; -logic s_axi_arvalid; -logic s_axi_arready; -logic [3:0] s_axi_rid; -logic [63:0] s_axi_rdata; -logic [1:0] s_axi_rresp; -logic s_axi_rlast; -logic s_axi_rvalid; -logic s_axi_rready; - -logic [31:0] m_axi_awaddr; -logic [7:0] m_axi_awlen; -logic [2:0] m_axi_awsize; -logic [1:0] m_axi_awburst; -logic [0:0] m_axi_awlock; -logic [3:0] m_axi_awcache; -logic [2:0] m_axi_awprot; -logic [3:0] m_axi_awregion; -logic [3:0] m_axi_awqos; -logic m_axi_awvalid; -logic m_axi_awready; -logic [127:0] m_axi_wdata; -logic [15:0] m_axi_wstrb; -logic m_axi_wlast; -logic m_axi_wvalid; -logic m_axi_wready; -logic [1:0] m_axi_bresp; -logic m_axi_bvalid; -logic m_axi_bready; -logic [31:0] m_axi_araddr; -logic [7:0] m_axi_arlen; -logic [2:0] m_axi_arsize; -logic [1:0] m_axi_arburst; -logic [0:0] m_axi_arlock; -logic [3:0] m_axi_arcache; -logic [2:0] m_axi_arprot; -logic [3:0] m_axi_arregion; -logic [3:0] m_axi_arqos; -logic m_axi_arvalid; -logic m_axi_arready; -logic [127:0] m_axi_rdata; -logic [1:0] m_axi_rresp; -logic m_axi_rlast; -logic m_axi_rvalid; -logic m_axi_rready; - -logic debug_req_valid; -logic debug_req_ready; -logic [6:0] debug_req_bits_addr; -logic [1:0] debug_req_bits_op; -logic [31:0] debug_req_bits_data; -logic debug_resp_valid; -logic debug_resp_ready; -logic [1:0] debug_resp_bits_resp; -logic [31:0] debug_resp_bits_data; - -assign clk = addn_ui_clkout1; -assign rst_n = ~c0_ddr4_ui_clk_sync_rst; -assign test_en = 1'b0; -assign ndmreset_n = ~ndmreset ; - -// Slice the AXI Masters (slave ports on the XBar) -for (genvar i = 0; i < NBSlave; i++) begin : slave_cut_gen - axi_cut #( - .ADDR_WIDTH ( AxiAddrWidth ), - .DATA_WIDTH ( AxiDataWidth ), - .ID_WIDTH ( AxiIdWidthMaster ), - .USER_WIDTH ( AxiUserWidth ) - ) i_axi_cut ( - .clk_i ( clk ), - .rst_ni ( ndmreset_n ), - .in ( slave_slice[i] ), - .out ( slave[i] ) - ); -end - -// --------------- -// AXI Xbar -// --------------- -axi_node_intf_wrap #( - // three ports from Ariane (instruction, data and bypass) - .NB_SLAVE ( NBSlave ), - .NB_MASTER ( NBMaster ), // debug unit, memory unit - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_USER_WIDTH ( AxiUserWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMaster ) -) i_axi_xbar ( - .clk ( clk ), - .rst_n ( ndmreset_n ), - .test_en_i ( test_en ), - .slave ( slave ), - .master ( master ), - .start_addr_i ( {64'h0, RomBase, CacheStartAddr} ), - .end_addr_i ( {64'hFFF, RomBase + 64'hFFFF, CacheStartAddr + 2**24} ) -); - -dm::dmi_req_t debug_req;; -dm::dmi_resp_t debug_resp; - -// --------------- -// Debug Module -// --------------- -dmi_jtag i_dmi_jtag ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .dmi_rst_no ( ), // keep open - .dmi_req_valid_o ( debug_req_valid ), - .dmi_req_ready_i ( debug_req_ready ), - .dmi_req_o ( debug_req ), - .dmi_resp_valid_i ( debug_resp_valid ), - .dmi_resp_ready_o ( debug_resp_ready ), - .dmi_resp_i ( debug_resp ), - .tck_i ( tck ), - .tms_i ( tms ), - .trst_ni ( trst_n ), - .td_i ( tdi ), - .td_o ( tdo ), - .tdo_oe_o ( ) -); - -// debug module -dm_top #( - // current implementation only supports 1 hart - .NrHarts ( 1 ), - .AxiIdWidth ( AxiIdWidthSlaves ), - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiUserWidth ( AxiUserWidth ) -) i_dm_top ( - .clk_i ( clk ), - .rst_ni ( rst_n ), // PoR - .testmode_i ( test_en ), - .ndmreset_o ( ndmreset ), - .dmactive_o ( ), // active debug session - .debug_req_o ( debug_req ), - .unavailable_i ( '0 ), - .axi_master ( slave_slice[3] ), - .axi_slave ( master[2] ), - .dmi_rst_ni ( rst_n ), - .dmi_req_valid_i ( debug_req_valid ), - .dmi_req_ready_o ( debug_req_ready ), - .dmi_req_i ( debug_req ), - .dmi_resp_valid_o ( debug_resp_valid ), - .dmi_resp_ready_i ( debug_resp_ready ), - .dmi_resp_o ( debug_resp ) -); - -// --------------- -// Core -// --------------- -ariane #( - .CACHE_START_ADDR ( CacheStartAddr ), - .AXI_ID_WIDTH ( AxiIdWidthMaster ), - .AXI_USER_WIDTH ( AxiUserWidth ) -) i_ariane ( - .clk_i ( clk ), - .rst_ni ( ndmreset_n ), - .boot_addr_i ( RomBase ), // start fetching from ROM - .core_id_i ( '0 ), - .cluster_id_i ( '0 ), - .irq_i ( '0 ), - .ipi_i ( '0 ), - .time_irq_i ( '0 ), - .debug_req_i ( debug_req ), - .data_if ( slave_slice[2] ), - .bypass_if ( slave_slice[1] ), - .instr_if ( slave_slice[0] ) -); - -// --------------- -// ROM -// --------------- -logic rom_req; -logic [AxiAddrWidth-1:0] rom_addr; -logic [AxiDataWidth-1:0] rom_rdata; - -axi2mem #( - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_USER_WIDTH ( AxiUserWidth ) -) i_axi2rom ( - .clk_i ( clk ), - .rst_ni ( ndmreset_n ), - .slave ( master[1] ), - .req_o ( rom_req ), - .we_o ( ), - .addr_o ( rom_addr ), - .be_o ( ), - .data_o ( ), - .data_i ( rom_rdata ) -); - -bootrom i_bootrom ( - .clk_i ( clk ), - .req_i ( rom_req ), - .addr_i ( rom_addr ), - .rdata_o ( rom_rdata ) -); - -// DDR 4 Subsystem -axi_clock_converter_0 axi_clock_converter ( - .s_axi_aclk(clk), - .s_axi_aresetn(ndmreset_n), - .s_axi_awid(master[0].aw_id), - .s_axi_awaddr(master[0].aw_addr), - .s_axi_awlen(master[0].aw_len), - .s_axi_awsize(master[0].aw_size), - .s_axi_awburst(master[0].aw_burst), - .s_axi_awlock(master[0].aw_lock), - .s_axi_awcache(master[0].aw_cache), - .s_axi_awprot(master[0].aw_prot), - .s_axi_awregion(master[0].aw_region), - .s_axi_awqos(master[0].aw_qos), - .s_axi_awvalid(master[0].aw_valid), - .s_axi_awready(master[0].aw_ready), - .s_axi_wdata(master[0].w_data), - .s_axi_wstrb(master[0].w_strb), - .s_axi_wlast(master[0].w_last), - .s_axi_wvalid(master[0].w_valid), - .s_axi_wready(master[0].w_ready), - .s_axi_bid(master[0].b_id), - .s_axi_bresp(master[0].b_resp), - .s_axi_bvalid(master[0].b_valid), - .s_axi_bready(master[0].b_ready), - .s_axi_arid(master[0].ar_id), - .s_axi_araddr(master[0].ar_addr[31:0]), - .s_axi_arlen(master[0].ar_len), - .s_axi_arsize(master[0].ar_size), - .s_axi_arburst(master[0].ar_burst), - .s_axi_arlock(master[0].ar_lock), - .s_axi_arcache(master[0].ar_cache), - .s_axi_arprot(master[0].ar_prot), - .s_axi_arregion(master[0].ar_region), - .s_axi_arqos(master[0].ar_qos), - .s_axi_arvalid(master[0].ar_valid), - .s_axi_arready(master[0].ar_ready), - .s_axi_rid(master[0].r_id), - .s_axi_rdata(master[0].r_data), - .s_axi_rresp(master[0].r_resp), - .s_axi_rlast(master[0].r_last), - .s_axi_rvalid(master[0].r_valid), - .s_axi_rready(master[0].r_ready), - // to size converter - .m_axi_aclk(c0_ddr4_ui_clk), - .m_axi_aresetn(ndmreset_n), - .m_axi_awid(s_axi_awid), - .m_axi_awaddr(s_axi_awaddr), - .m_axi_awlen(s_axi_awlen), - .m_axi_awsize(s_axi_awsize), - .m_axi_awburst(s_axi_awburst), - .m_axi_awlock(s_axi_awlock), - .m_axi_awcache(s_axi_awcache), - .m_axi_awprot(s_axi_awprot), - .m_axi_awregion(s_axi_awregion), - .m_axi_awqos(s_axi_awqos), - .m_axi_awvalid(s_axi_awvalid), - .m_axi_awready(s_axi_awready), - .m_axi_wdata(s_axi_wdata), - .m_axi_wstrb(s_axi_wstrb), - .m_axi_wlast(s_axi_wlast), - .m_axi_wvalid(s_axi_wvalid), - .m_axi_wready(s_axi_wready), - .m_axi_bid(s_axi_bid), - .m_axi_bresp(s_axi_bresp), - .m_axi_bvalid(s_axi_bvalid), - .m_axi_bready(s_axi_bready), - .m_axi_arid(s_axi_arid), - .m_axi_araddr(s_axi_araddr), - .m_axi_arlen(s_axi_arlen), - .m_axi_arsize(s_axi_arsize), - .m_axi_arburst(s_axi_arburst), - .m_axi_arlock(s_axi_arlock), - .m_axi_arcache(s_axi_arcache), - .m_axi_arprot(s_axi_arprot), - .m_axi_arregion(s_axi_arregion), - .m_axi_arqos(s_axi_arqos), - .m_axi_arvalid(s_axi_arvalid), - .m_axi_arready(s_axi_arready), - .m_axi_rid(s_axi_rid), - .m_axi_rdata(s_axi_rdata), - .m_axi_rresp(s_axi_rresp), - .m_axi_rlast(s_axi_rlast), - .m_axi_rvalid(s_axi_rvalid), - .m_axi_rready(s_axi_rready) -); - -axi_dwidth_converter_0 axi_size_converter ( - .s_axi_aclk(c0_ddr4_ui_clk), - .s_axi_aresetn(ndmreset_n), - .s_axi_awid, - .s_axi_awaddr, - .s_axi_awlen, - .s_axi_awsize, - .s_axi_awburst, - .s_axi_awlock, - .s_axi_awcache, - .s_axi_awprot, - .s_axi_awregion, - .s_axi_awqos, - .s_axi_awvalid, - .s_axi_awready, - .s_axi_wdata, - .s_axi_wstrb, - .s_axi_wlast, - .s_axi_wvalid, - .s_axi_wready, - .s_axi_bid, - .s_axi_bresp, - .s_axi_bvalid, - .s_axi_bready, - .s_axi_arid, - .s_axi_araddr, - .s_axi_arlen, - .s_axi_arsize, - .s_axi_arburst, - .s_axi_arlock, - .s_axi_arcache, - .s_axi_arprot, - .s_axi_arregion, - .s_axi_arqos, - .s_axi_arvalid, - .s_axi_arready, - .s_axi_rid, - .s_axi_rdata, - .s_axi_rresp, - .s_axi_rlast, - .s_axi_rvalid, - .s_axi_rready, - .m_axi_awaddr, - .m_axi_awlen, - .m_axi_awsize, - .m_axi_awburst, - .m_axi_awlock, - .m_axi_awcache, - .m_axi_awprot, - .m_axi_awregion, - .m_axi_awqos, - .m_axi_awvalid, - .m_axi_awready, - .m_axi_wdata, - .m_axi_wstrb, - .m_axi_wlast, - .m_axi_wvalid, - .m_axi_wready, - .m_axi_bresp, - .m_axi_bvalid, - .m_axi_bready, - .m_axi_araddr, - .m_axi_arlen, - .m_axi_arsize, - .m_axi_arburst, - .m_axi_arlock, - .m_axi_arcache, - .m_axi_arprot, - .m_axi_arregion, - .m_axi_arqos, - .m_axi_arvalid, - .m_axi_arready, - .m_axi_rdata, - .m_axi_rresp, - .m_axi_rlast, - .m_axi_rvalid, - .m_axi_rready -); - -ddr4_0 ddr_i ( - .sys_rst, // input - .c0_sys_clk_p, - .c0_sys_clk_n, - .c0_ddr4_act_n, - .c0_ddr4_adr, - .c0_ddr4_ba, - .c0_ddr4_bg, - .c0_ddr4_cke, - .c0_ddr4_odt, - .c0_ddr4_cs_n, - .c0_ddr4_ck_t, - .c0_ddr4_ck_c, - .c0_ddr4_reset_n, - .c0_ddr4_dm_dbi_n, - .c0_ddr4_dq, - .c0_ddr4_dqs_c, - .c0_ddr4_dqs_t, - .c0_init_calib_complete, - .c0_ddr4_ui_clk, // 1/4 of PHY clock, 300/4 = 75 MHz - .c0_ddr4_ui_clk_sync_rst, - .addn_ui_clkout1, - .dbg_clk(), // output - .c0_ddr4_aresetn(ndmreset_n), - .c0_ddr4_s_axi_awid('0), - .c0_ddr4_s_axi_awaddr(m_axi_awaddr), - .c0_ddr4_s_axi_awlen(m_axi_awlen), - .c0_ddr4_s_axi_awsize(m_axi_awsize), - .c0_ddr4_s_axi_awburst(m_axi_awburst), - .c0_ddr4_s_axi_awlock(m_axi_awlock), - .c0_ddr4_s_axi_awcache(m_axi_awcache), - .c0_ddr4_s_axi_awprot(m_axi_awprot), - .c0_ddr4_s_axi_awqos(m_axi_awqos), - .c0_ddr4_s_axi_awvalid(m_axi_awvalid), - .c0_ddr4_s_axi_awready(m_axi_awready), - .c0_ddr4_s_axi_wdata(m_axi_wdata), - .c0_ddr4_s_axi_wstrb(m_axi_wstrb), - .c0_ddr4_s_axi_wlast(m_axi_wlast), - .c0_ddr4_s_axi_wvalid(m_axi_wvalid), - .c0_ddr4_s_axi_wready(m_axi_wready), - .c0_ddr4_s_axi_bready(m_axi_bready), - .c0_ddr4_s_axi_bid(), - .c0_ddr4_s_axi_bresp(m_axi_bresp), - .c0_ddr4_s_axi_bvalid(m_axi_bvalid), - .c0_ddr4_s_axi_arid('0), - .c0_ddr4_s_axi_araddr(m_axi_araddr), - .c0_ddr4_s_axi_arlen(m_axi_arlen), - .c0_ddr4_s_axi_arsize(m_axi_arsize), - .c0_ddr4_s_axi_arburst(m_axi_arburst), - .c0_ddr4_s_axi_arlock(m_axi_arlock), - .c0_ddr4_s_axi_arcache(m_axi_arcache), - .c0_ddr4_s_axi_arprot(m_axi_arprot), - .c0_ddr4_s_axi_arqos(m_axi_arqos), - .c0_ddr4_s_axi_arvalid(m_axi_arvalid), - .c0_ddr4_s_axi_arready(m_axi_arready), - .c0_ddr4_s_axi_rready(m_axi_rready), - .c0_ddr4_s_axi_rid(), - .c0_ddr4_s_axi_rdata(m_axi_rdata), - .c0_ddr4_s_axi_rresp(m_axi_rresp), - .c0_ddr4_s_axi_rlast(m_axi_rlast), - .c0_ddr4_s_axi_rvalid(m_axi_rvalid), - .dbg_bus() -); - -endmodule \ No newline at end of file diff --git a/fpga/constraints/ariane.xdc b/fpga/constraints/ariane.xdc new file mode 100644 index 0000000000..9ea40f9c03 --- /dev/null +++ b/fpga/constraints/ariane.xdc @@ -0,0 +1,12 @@ +## Common Ariane XDCs + +create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck] +set_input_jitter tck 1.000 + +set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 10.000 +set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 10.000 +set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 10.000 + + + + diff --git a/fpga/constraints/genesys-2.xdc b/fpga/constraints/genesys-2.xdc new file mode 100644 index 0000000000..a1f7315d5d --- /dev/null +++ b/fpga/constraints/genesys-2.xdc @@ -0,0 +1,94 @@ +\## Buttons +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports cpu_resetn] + +## PMOD Header JC +set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports tck] +set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33} [get_ports tdi] +set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVCMOS33} [get_ports tdo] +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS33} [get_ports tms] +set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports trst_n] + +## UART +set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports tx] +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports rx] + +# accept sub-optimal placement +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF] + +## LEDs +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {led[4]}] +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports {led[5]}] +set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports {led[6]}] +set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports {led[7]}] + +## Switches +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}] +set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}] +set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}] + +## Fan Control +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports fan_pwm] +#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac + +## Ethernet +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n +set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS15} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk +set_property -dict {PACKAGE_PIN AK14 IOSTANDARD LVCMOS15} [get_ports { eth_txctl }]; #IO_L20P_T3_33 Sch=eth_tx_en +set_property -dict {PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0] +set_property -dict {PACKAGE_PIN AK11 IOSTANDARD LVCMOS15} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1] +set_property -dict {PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2] +set_property -dict {PACKAGE_PIN AK10 IOSTANDARD LVCMOS15} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3] +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0] +set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS15} [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk +set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS15} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1] +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2] +set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3] +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS15} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS15} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio + +# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb +# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb + +############################################# +# Ethernet Constraints for 100 Mb/s +############################################# +# Copied from OpenPiton Project +# hint from here: https://forums.xilinx.com/t5/Timing-Analysis/XDC-constraints-Source-Synchronous-ADC-DDR/td-p/292807 +create_clock -period 40.000 -name eth_rxck_virt +# set_clock_groups -asynchronous -group [get_clocks chipset_clk_clk_mmcm] -group [get_clocks eth_rxck] +# conservatively assuming +/- 2ns skew of rxd/rxctl +create_clock -period 40.000 -name eth_rxck -waveform {2.000 22.000} [get_ports eth_rxck] + +# Input constraints +set_input_delay -clock [get_clocks eth_rxck_virt] -min -add_delay 0.000 [get_ports {eth_rxd[*]}] +set_input_delay -clock [get_clocks eth_rxck_virt] -max -add_delay 4.000 [get_ports {eth_rxd[*]}] +set_input_delay -clock [get_clocks eth_rxck_virt] -clock_fall -min -add_delay 0.000 [get_ports eth_rxctl] +set_input_delay -clock [get_clocks eth_rxck_virt] -clock_fall -max -add_delay 4.000 [get_ports eth_rxctl] +set_input_delay -clock [get_clocks eth_rxck_virt] -min -add_delay 0.000 [get_ports eth_rxctl] +set_input_delay -clock [get_clocks eth_rxck_virt] -max -add_delay 4.000 [get_ports eth_rxctl] + +# Output Constraints +create_generated_clock -name eth_txck_gen -source [get_pins i_ariane_peripherals/gen_ethernet.i_rgmii_to_mii_conv_xilinx/net_phy_txc_oddr/C] -multiply_by 1 [get_ports eth_txck] + +# Constraint RGMII interface +set_output_delay -clock eth_txck_gen 2.000 [get_ports eth_txctl] +set_output_delay -clock eth_txck_gen 2.000 [get_ports {eth_txd[*]}] + +## SD Card +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o] +set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports spi_ss] +set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports spi_miso] +set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi] + +# Genesys 2 has a quad SPI flash +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] diff --git a/fpga/constraints/vcu118.xdc b/fpga/constraints/vcu118.xdc new file mode 100644 index 0000000000..ea71aa8d25 --- /dev/null +++ b/fpga/constraints/vcu118.xdc @@ -0,0 +1,1990 @@ +############################################################################ +### VCU118 Rev2.0 XDC 12/08/2017 +############################################################################ +# Buttons +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS12} [get_ports cpu_reset] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73 +set_property PULLDOWN true [get_ports cpu_reset] +# PCIe +set_false_path -from [get_ports sys_rst_n] +set_property PULLUP true [get_ports sys_rst_n] +set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n] +set_property PACKAGE_PIN AM17 [get_ports sys_rst_n] +create_clock -name sys_clk -period 10 [get_ports sys_clk_p] + +set_property -dict {PACKAGE_PIN AC9} [get_ports sys_clk_p] +set_property -dict {PACKAGE_PIN AC8} [get_ports sys_clk_n] + +# JTAG +set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS12} [get_ports tck] ; # PMOD1_0 +set_property -dict {PACKAGE_PIN M30 IOSTANDARD LVCMOS12} [get_ports tdi] ; # PMOD1_1 +set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS12} [get_ports tdo] ; # PMOD1_2 +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS12} [get_ports tms] ; # PMOD1_3 +set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS12} [get_ports trst_n] ;# PMOD1_4 +# accept sub-optimal placement +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF_inst/O] + +set_property -dict {PACKAGE_PIN AW25 IOSTANDARD LVCMOS18} [get_ports tx] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64 +set_property -dict {PACKAGE_PIN BB21 IOSTANDARD LVCMOS18} [get_ports rx] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64 + +## SD Card **TODO(zarubaf)*** This is wrong for the VCU118 +set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS18} [get_ports spi_clk_o] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47 +set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS18} [get_ports spi_clk_o_2] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47 + +set_property -dict {PACKAGE_PIN BF16 IOSTANDARD LVCMOS18} [get_ports spi_ss] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property -dict {PACKAGE_PIN BF20 IOSTANDARD LVCMOS18} [get_ports spi_ss_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65 + +set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS18} [get_ports spi_miso] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS18} [get_ports spi_miso_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65 +set_property -dict {PACKAGE_PIN AN20 IOSTANDARD LVCMOS18} [get_ports spi_mosi_2] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65 + +# #Other net PACKAGE_PIN AE17 - DXN Bank 0 - DXN +# #Other net PACKAGE_PIN AE18 - DXP Bank 0 - DXP +# #Other net PACKAGE_PIN AD18 - GND Bank 0 - VREFP +# #Other net PACKAGE_PIN AC17 - GND Bank 0 - VREFN +# #Other net PACKAGE_PIN AC18 - SYSMON_VP Bank 0 - VP +# #Other net PACKAGE_PIN AD17 - SYSMON_VN Bank 0 - VN +# #Other net PACKAGE_PIN U10 - FPGA_M0 Bank 0 - M0_0 +# #Other net PACKAGE_PIN Y11 - FPGA_M1 Bank 0 - M1_0 +# #Other net PACKAGE_PIN AC12 - FPGA_INIT_B Bank 0 - INIT_B_0 +# #Other net PACKAGE_PIN W11 - FPGA_M2 Bank 0 - M2_0 +# #Other net PACKAGE_PIN AB11 - GND Bank 0 - RSVDGND +# #Other net PACKAGE_PIN AD12 - PUDC_B_PIN Bank 0 - PUDC_B_0 +# #Other net PACKAGE_PIN AG12 - POR_OVERRIDE_PIN Bank 0 - POR_OVERRIDE +# #Other net PACKAGE_PIN AE12 - FPGA_DONE Bank 0 - DONE_0 +# #Other net PACKAGE_PIN AH11 - FPGA_PROG_B Bank 0 - PROGRAM_B_0 +# #Other net PACKAGE_PIN AD13 - FPGA_TDO_FMC_TDI Bank 0 - TDO_0 +# #Other net PACKAGE_PIN AD15 - JTAG_TDI Bank 0 - TDI_0 +# #Other net PACKAGE_PIN AJ11 - QSPI0_CS_B Bank 0 - RDWR_FCS_B_0 +# #Other net PACKAGE_PIN AM11 - QSPI0_DQ2 Bank 0 - D02_0 +# #Other net PACKAGE_PIN AP11 - QSPI0_DQ0 Bank 0 - D00_MOSI_0 +# #Other net PACKAGE_PIN AL11 - QSPI0_DQ3 Bank 0 - D03_0 +# #Other net PACKAGE_PIN AN11 - QSPI0_DQ1 Bank 0 - D01_DIN_0 +# #Other net PACKAGE_PIN AF15 - JTAG_TMS Bank 0 - TMS_0 +# #Other net PACKAGE_PIN AF13 - QSPI_CCLK Bank 0 - CCLK_0 +# #Other net PACKAGE_PIN AE13 - JTAG_TCK Bank 0 - TCK_0 +# #Other net PACKAGE_PIN AT11 - FPGA_VBATT Bank 0 - VBATT +# set_property PACKAGE_PIN B25 [get_ports "RLD3_C3_72B_DM3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_48 +# set_property PACKAGE_PIN C25 [get_ports "RLD3_C3_72B_DQ71"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ71"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_48 +# set_property PACKAGE_PIN D26 [get_ports "RLD3_C3_72B_DQ70"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ70"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_48 +# set_property PACKAGE_PIN D25 [get_ports "RLD3_C3_72B_DQ69"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ69"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_48 +# set_property PACKAGE_PIN A26 [get_ports "RLD3_C3_72B_DQ68"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ68"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_48 +# set_property PACKAGE_PIN B26 [get_ports "RLD3_C3_72B_DQ67"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ67"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_48 +# set_property PACKAGE_PIN B27 [get_ports "RLD3_C3_72B_DQ66"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ66"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_48 +# set_property PACKAGE_PIN C27 [get_ports "RLD3_C3_72B_DQ65"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ65"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_48 +# set_property PACKAGE_PIN A28 [get_ports "RLD3_C3_72B_DQ64"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ64"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_48 +# set_property PACKAGE_PIN B28 [get_ports "RLD3_C3_72B_DQ63"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ63"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_48 +# set_property PACKAGE_PIN C28 [get_ports "RLD3_C3_72B_QK7_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_48 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK7_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_48 +# set_property PACKAGE_PIN D27 [get_ports "RLD3_C3_72B_QK7_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_48 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK7_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_48 +# #set_property PACKAGE_PIN A25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T3U_N12_48 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T3U_N12_48 +# #set_property PACKAGE_PIN H25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T2U_N12_48 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T2U_N12_48 +# set_property PACKAGE_PIN F25 [get_ports "RLD3_C3_72B_QVLD3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD3"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_48 +# set_property PACKAGE_PIN G25 [get_ports "RLD3_C3_72B_DQ62"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ62"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_48 +# set_property PACKAGE_PIN E27 [get_ports "RLD3_C3_72B_DQ61"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ61"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_48 +# set_property PACKAGE_PIN E26 [get_ports "RLD3_C3_72B_DQ60"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ60"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_48 +# set_property PACKAGE_PIN G28 [get_ports "RLD3_C3_72B_DQ59"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ59"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_48 +# set_property PACKAGE_PIN H28 [get_ports "RLD3_C3_72B_DQ58"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ58"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_48 +# set_property PACKAGE_PIN E28 [get_ports "RLD3_C3_72B_DQ57"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ57"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_48 +# set_property PACKAGE_PIN F28 [get_ports "RLD3_C3_72B_DQ56"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ56"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_48 +# set_property PACKAGE_PIN G27 [get_ports "RLD3_C3_72B_DQ55"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ55"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_48 +# set_property PACKAGE_PIN H27 [get_ports "RLD3_C3_72B_DQ54"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ54"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_48 +# set_property PACKAGE_PIN F26 [get_ports "RLD3_C3_72B_QK6_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_48 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK6_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_48 +# set_property PACKAGE_PIN G26 [get_ports "RLD3_C3_72B_QK6_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_48 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK6_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_48 +# set_property PACKAGE_PIN J27 [get_ports "RLD3_C3_72B_QVLD2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_48 +# set_property PACKAGE_PIN K27 [get_ports "RLD3_C3_72B_DQ53"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ53"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_48 +# set_property PACKAGE_PIN J26 [get_ports "RLD3_C3_72B_DQ52"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ52"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_48 +# set_property PACKAGE_PIN K26 [get_ports "RLD3_C3_72B_DQ51"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ51"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_48 +# set_property PACKAGE_PIN L25 [get_ports "RLD3_C3_72B_DQ50"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ50"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_48 +# set_property PACKAGE_PIN L24 [get_ports "RLD3_C3_72B_DQ49"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ49"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_48 +# set_property PACKAGE_PIN K28 [get_ports "RLD3_C3_72B_DQ48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_48 +# set_property PACKAGE_PIN L28 [get_ports "RLD3_C3_72B_DQ47"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ47"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_48 +# set_property PACKAGE_PIN L26 [get_ports "RLD3_C3_72B_DQ46"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ46"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_48 +# set_property PACKAGE_PIN M25 [get_ports "RLD3_C3_72B_DQ45"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ45"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_48 +# set_property PACKAGE_PIN M28 [get_ports "RLD3_C3_72B_QK5_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_48 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK5_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_48 +# set_property PACKAGE_PIN M27 [get_ports "RLD3_C3_72B_QK5_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_48 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK5_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_48 +# #set_property PACKAGE_PIN J25 [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T1U_N12_48 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T1U_N12_48 +# #set_property PACKAGE_PIN M26 [get_ports "VRP_48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_48 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_48"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_48 +# set_property PACKAGE_PIN N24 [get_ports "RLD3_C3_72B_DM2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM2"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_48 +# set_property PACKAGE_PIN P24 [get_ports "RLD3_C3_72B_DQ44"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ44"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_48 +# set_property PACKAGE_PIN N27 [get_ports "RLD3_C3_72B_DQ43"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ43"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_48 +# set_property PACKAGE_PIN P26 [get_ports "RLD3_C3_72B_DQ42"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ42"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_48 +# set_property PACKAGE_PIN N25 [get_ports "RLD3_C3_72B_DQ41"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ41"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_48 +# set_property PACKAGE_PIN P25 [get_ports "RLD3_C3_72B_DQ40"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ40"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_48 +# set_property PACKAGE_PIN P27 [get_ports "RLD3_C3_72B_DQ39"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ39"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_48 +# set_property PACKAGE_PIN R27 [get_ports "RLD3_C3_72B_DQ38"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ38"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_48 +# set_property PACKAGE_PIN R24 [get_ports "RLD3_C3_72B_DQ37"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ37"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_48 +# set_property PACKAGE_PIN T24 [get_ports "RLD3_C3_72B_DQ36"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_48 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ36"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_48 +# set_property PACKAGE_PIN R26 [get_ports "RLD3_C3_72B_QK4_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_48 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK4_N"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_48 +# set_property PACKAGE_PIN T26 [get_ports "RLD3_C3_72B_QK4_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_48 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK4_P"] ;# Bank 48 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_48 +# #Other net PACKAGE_PIN T25 - Bank 48 - VREF_48 +# set_property PACKAGE_PIN C29 [get_ports "RLD3_C3_72B_A1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_47 +# set_property PACKAGE_PIN D29 [get_ports "RLD3_C3_72B_A2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_47 +# set_property PACKAGE_PIN B30 [get_ports "RLD3_C3_72B_A3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_47 +# set_property PACKAGE_PIN C30 [get_ports "RLD3_C3_72B_A4"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A4"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_47 +# set_property PACKAGE_PIN A31 [get_ports "RLD3_C3_72B_A5"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A5"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_47 +# set_property PACKAGE_PIN A30 [get_ports "RLD3_C3_72B_A6"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A6"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_47 +# set_property PACKAGE_PIN A33 [get_ports "RLD3_C3_72B_A7"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A7"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_47 +# set_property PACKAGE_PIN B33 [get_ports "RLD3_C3_72B_A8"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A8"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_47 +# set_property PACKAGE_PIN B32 [get_ports "RLD3_C3_72B_A9"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A9"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_47 +# set_property PACKAGE_PIN B31 [get_ports "RLD3_C3_72B_A10"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A10"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_47 +# set_property PACKAGE_PIN C33 [get_ports "RLD3_C3_72B_A11"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A11"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_47 +# set_property PACKAGE_PIN C32 [get_ports "RLD3_C3_72B_A12"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A12"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_47 +# set_property PACKAGE_PIN A29 [get_ports "RLD3_C3_72B_A0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T3U_N12_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T3U_N12_47 +# set_property PACKAGE_PIN D30 [get_ports "RLD3_C3_72B_A13"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T2U_N12_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A13"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T2U_N12_47 +# set_property PACKAGE_PIN E29 [get_ports "RLD3_C3_72B_A14"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A14"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_47 +# set_property PACKAGE_PIN F29 [get_ports "RLD3_C3_72B_A15"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A15"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_47 +# set_property PACKAGE_PIN D32 [get_ports "RLD3_C3_72B_A16"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A16"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_47 +# set_property PACKAGE_PIN E32 [get_ports "RLD3_C3_72B_A17"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A17"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_47 +# set_property PACKAGE_PIN D31 [get_ports "RLD3_C3_72B_A18"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A18"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_47 +# set_property PACKAGE_PIN E31 [get_ports "RLD3_C3_72B_A19"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A19"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_47 +# set_property PACKAGE_PIN E33 [get_ports "RLD3_C3_72B_BA0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA0"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_47 +# set_property PACKAGE_PIN F33 [get_ports "RLD3_C3_72B_BA1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA1"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_47 +# set_property PACKAGE_PIN F30 [get_ports "RLD3_C3_72B_BA2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA2"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_47 +# set_property PACKAGE_PIN G30 [get_ports "RLD3_C3_72B_BA3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA3"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_47 +# set_property PACKAGE_PIN F31 [get_ports "SYSCLK1_300_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK1_300_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_47 +# set_property PACKAGE_PIN G31 [get_ports "SYSCLK1_300_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK1_300_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_47 +# set_property PACKAGE_PIN G32 [get_ports "USER_SI570_CLOCK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_CLOCK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_47 +# set_property PACKAGE_PIN H32 [get_ports "USER_SI570_CLOCK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_CLOCK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_47 +# set_property PACKAGE_PIN H30 [get_ports "RLD3_C3_72B_CK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_CK_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_47 +# set_property PACKAGE_PIN H29 [get_ports "RLD3_C3_72B_CK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_CK_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_47 +# set_property PACKAGE_PIN G33 [get_ports "RLD3_C3_72B_DK3_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_47 +# set_property PACKAGE_PIN H33 [get_ports "RLD3_C3_72B_DK3_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_47 +# set_property PACKAGE_PIN J30 [get_ports "RLD3_C3_72B_DK2_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK2_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_47 +# set_property PACKAGE_PIN J29 [get_ports "RLD3_C3_72B_DK2_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK2_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_47 +# set_property PACKAGE_PIN J32 [get_ports "RLD3_C3_72B_DK1_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK1_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_47 +# set_property PACKAGE_PIN K32 [get_ports "RLD3_C3_72B_DK1_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK1_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_47 +# set_property PACKAGE_PIN J31 [get_ports "RLD3_C3_72B_DK0_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK0_N"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_47 +# set_property PACKAGE_PIN K31 [get_ports "RLD3_C3_72B_DK0_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_47 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK0_P"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_47 +# set_property PACKAGE_PIN K29 [get_ports "RLD3_C3_72B_WE_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T1U_N12_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_WE_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T1U_N12_47 +# #set_property PACKAGE_PIN T29 [get_ports "VRP_47"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_47 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_47"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_47 +# set_property PACKAGE_PIN L30 [get_ports "RLD3_C3_72B_REF_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_REF_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_47 +# set_property PACKAGE_PIN L29 [get_ports "RLD3_C3_72B_RESET_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_47 +# set_property IOSTANDARD LVCMOS12 [get_ports "RLD3_C3_72B_RESET_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_47 +# set_property PACKAGE_PIN N29 [get_ports "RLD3_C3_72B_CS_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_CS_B"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_47 + +# set_property PACKAGE_PIN R28 [get_ports "RLD3_C3_72B_A20"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_47 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A20"] ;# Bank 47 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_47 +# #Other net PACKAGE_PIN T28 - 43N2999 Bank 47 - VREF_47 +# set_property PACKAGE_PIN A35 [get_ports "RLD3_C3_72B_DM1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_46 +# set_property PACKAGE_PIN A34 [get_ports "RLD3_C3_72B_DQ35"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ35"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_46 +# set_property PACKAGE_PIN A36 [get_ports "RLD3_C3_72B_DQ34"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ34"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_46 +# set_property PACKAGE_PIN B35 [get_ports "RLD3_C3_72B_DQ33"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ33"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_46 +# set_property PACKAGE_PIN B37 [get_ports "RLD3_C3_72B_DQ32"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ32"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_46 +# set_property PACKAGE_PIN B36 [get_ports "RLD3_C3_72B_DQ31"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ31"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_46 +# set_property PACKAGE_PIN C34 [get_ports "RLD3_C3_72B_DQ30"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ30"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_46 +# set_property PACKAGE_PIN D34 [get_ports "RLD3_C3_72B_DQ29"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ29"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_46 +# set_property PACKAGE_PIN C35 [get_ports "RLD3_C3_72B_DQ28"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ28"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_46 +# set_property PACKAGE_PIN D35 [get_ports "RLD3_C3_72B_DQ27"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ27"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_46 +# set_property PACKAGE_PIN C37 [get_ports "RLD3_C3_72B_QK3_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_46 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK3_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_46 +# set_property PACKAGE_PIN D37 [get_ports "RLD3_C3_72B_QK3_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_46 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK3_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_46 +# #set_property PACKAGE_PIN D36 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T3U_N12_46 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T3U_N12_46 +# #set_property PACKAGE_PIN C38 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T2U_N12_46 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T2U_N12_46 +# set_property PACKAGE_PIN A38 [get_ports "RLD3_C3_72B_QVLD1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_46 +# set_property PACKAGE_PIN B38 [get_ports "RLD3_C3_72B_DQ26"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ26"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_46 +# set_property PACKAGE_PIN C40 [get_ports "RLD3_C3_72B_DQ25"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ25"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_46 +# set_property PACKAGE_PIN D40 [get_ports "RLD3_C3_72B_DQ24"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ24"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_46 +# set_property PACKAGE_PIN A40 [get_ports "RLD3_C3_72B_DQ23"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ23"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_46 +# set_property PACKAGE_PIN A39 [get_ports "RLD3_C3_72B_DQ22"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ22"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_46 +# set_property PACKAGE_PIN B40 [get_ports "RLD3_C3_72B_DQ21"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ21"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_46 +# set_property PACKAGE_PIN C39 [get_ports "RLD3_C3_72B_DQ20"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ20"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_46 +# set_property PACKAGE_PIN E38 [get_ports "RLD3_C3_72B_DQ19"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ19"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_46 +# set_property PACKAGE_PIN E37 [get_ports "RLD3_C3_72B_DQ18"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ18"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_46 +# set_property PACKAGE_PIN D39 [get_ports "RLD3_C3_72B_QK2_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_46 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK2_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_46 +# set_property PACKAGE_PIN E39 [get_ports "RLD3_C3_72B_QK2_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_46 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK2_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_46 +# set_property PACKAGE_PIN G37 [get_ports "RLD3_C3_72B_QVLD0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_46 +# set_property PACKAGE_PIN G36 [get_ports "RLD3_C3_72B_DQ17"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ17"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_46 +# set_property PACKAGE_PIN F36 [get_ports "RLD3_C3_72B_DQ16"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ16"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_46 +# set_property PACKAGE_PIN F35 [get_ports "RLD3_C3_72B_DQ15"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ15"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_46 +# set_property PACKAGE_PIN G35 [get_ports "RLD3_C3_72B_DQ14"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ14"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_46 +# set_property PACKAGE_PIN H34 [get_ports "RLD3_C3_72B_DQ13"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ13"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_46 +# set_property PACKAGE_PIN H37 [get_ports "RLD3_C3_72B_DQ12"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ12"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_46 +# set_property PACKAGE_PIN J36 [get_ports "RLD3_C3_72B_DQ11"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ11"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_46 +# set_property PACKAGE_PIN H35 [get_ports "RLD3_C3_72B_DQ10"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ10"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_46 +# set_property PACKAGE_PIN J35 [get_ports "RLD3_C3_72B_DQ9"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ9"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_46 +# set_property PACKAGE_PIN E34 [get_ports "RLD3_C3_72B_QK1_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_46 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK1_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_46 +# set_property PACKAGE_PIN F34 [get_ports "RLD3_C3_72B_QK1_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_46 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK1_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_46 +# #set_property PACKAGE_PIN E36 [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T1U_N12_46 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T1U_N12_46 +# #set_property PACKAGE_PIN K38 [get_ports "VRP_46"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_46 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_46"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_46 +# set_property PACKAGE_PIN F39 [get_ports "RLD3_C3_72B_DM0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_46 +# set_property PACKAGE_PIN F38 [get_ports "RLD3_C3_72B_DQ8"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ8"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_46 +# set_property PACKAGE_PIN J37 [get_ports "RLD3_C3_72B_DQ7"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ7"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_46 +# set_property PACKAGE_PIN K37 [get_ports "RLD3_C3_72B_DQ6"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ6"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_46 +# set_property PACKAGE_PIN G38 [get_ports "RLD3_C3_72B_DQ5"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ5"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_46 +# set_property PACKAGE_PIN H38 [get_ports "RLD3_C3_72B_DQ4"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ4"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_46 +# set_property PACKAGE_PIN F40 [get_ports "RLD3_C3_72B_DQ3"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ3"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_46 +# set_property PACKAGE_PIN G40 [get_ports "RLD3_C3_72B_DQ2"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ2"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_46 +# set_property PACKAGE_PIN H40 [get_ports "RLD3_C3_72B_DQ1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ1"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_46 +# set_property PACKAGE_PIN H39 [get_ports "RLD3_C3_72B_DQ0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_46 +# set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ0"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_46 +# set_property PACKAGE_PIN J40 [get_ports "RLD3_C3_72B_QK0_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_46 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_N"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_46 +# set_property PACKAGE_PIN J39 [get_ports "RLD3_C3_72B_QK0_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_46 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_P"] ;# Bank 46 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_46 +# #Other net PACKAGE_PIN J34 - Bank 46 - VREF_46 +# set_property PACKAGE_PIN L35 [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_45 +# set_property PACKAGE_PIN M35 [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_45 +# set_property PACKAGE_PIN M32 [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_45 +# set_property PACKAGE_PIN N32 [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_45 +# set_property PACKAGE_PIN M33 [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_45 +# set_property PACKAGE_PIN N33 [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_45 +# set_property PACKAGE_PIN K33 [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_45 +# set_property PACKAGE_PIN L33 [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_45 +# set_property PACKAGE_PIN N35 [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_45 +# set_property PACKAGE_PIN N34 [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_45 +# set_property PACKAGE_PIN K34 [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_45 +# set_property PACKAGE_PIN L34 [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_45 +# #set_property PACKAGE_PIN K36 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_45 +# #set_property PACKAGE_PIN R36 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_45 +# set_property PACKAGE_PIN M38 [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_45 +# set_property PACKAGE_PIN N38 [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_45 +# set_property PACKAGE_PIN L36 [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_45 +# set_property PACKAGE_PIN M36 [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_45 +# set_property PACKAGE_PIN N37 [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_45 +# set_property PACKAGE_PIN P37 [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_45 +# #set_property PACKAGE_PIN L38 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_45 +# #set_property PACKAGE_PIN M37 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_45 +# set_property PACKAGE_PIN P36 [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_45 +# set_property PACKAGE_PIN P35 [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_45 +# set_property PACKAGE_PIN P34 [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_45 +# set_property PACKAGE_PIN R34 [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_45 +# #set_property PACKAGE_PIN R33 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_45 +# #set_property PACKAGE_PIN T33 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_45 +# set_property PACKAGE_PIN P32 [get_ports "USER_SMA_CLOCK_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_45 +# set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_45 +# set_property PACKAGE_PIN R32 [get_ports "USER_SMA_CLOCK_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_45 +# set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_45 +# set_property PACKAGE_PIN P31 [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_45 +# set_property PACKAGE_PIN R31 [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_45 +# #set_property PACKAGE_PIN W31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_45 +# #set_property PACKAGE_PIN Y31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_45 +# #set_property PACKAGE_PIN U32 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_45 +# #set_property PACKAGE_PIN U31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_45 +# #set_property PACKAGE_PIN T31 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_45 +# #set_property PACKAGE_PIN T30 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_45 +# #set_property PACKAGE_PIN V30 [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_45 +# #set_property PACKAGE_PIN Y33 [get_ports "VRP_45"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_45 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_45"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_45 +# set_property PACKAGE_PIN T35 [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_45 +# set_property PACKAGE_PIN T34 [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_45 +# set_property PACKAGE_PIN V34 [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_45 +# set_property PACKAGE_PIN V33 [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_45 +# set_property PACKAGE_PIN T36 [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_45 +# set_property PACKAGE_PIN U35 [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_45 +# set_property PACKAGE_PIN W34 [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_45 +# set_property PACKAGE_PIN Y34 [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_45 +# set_property PACKAGE_PIN U33 [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_45 +# set_property PACKAGE_PIN V32 [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_45 +# set_property PACKAGE_PIN W32 [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_45 +# set_property PACKAGE_PIN Y32 [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_45 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 45 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_45 +# #Other net PACKAGE_PIN U30 - VREF_45 Bank 45 - VREF_45 +# set_property PACKAGE_PIN AK13 [get_ports "FMC_HPC1_LA33_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA33_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_67 +# set_property PACKAGE_PIN AK14 [get_ports "FMC_HPC1_LA33_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA33_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_67 +# set_property PACKAGE_PIN AM12 [get_ports "FMC_HPC1_LA31_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA31_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_67 +# set_property PACKAGE_PIN AM13 [get_ports "FMC_HPC1_LA31_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA31_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_67 +# set_property PACKAGE_PIN AJ12 [get_ports "FMC_HPC1_LA32_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA32_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_67 +# set_property PACKAGE_PIN AJ13 [get_ports "FMC_HPC1_LA32_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA32_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_67 +# set_property PACKAGE_PIN AL12 [get_ports "FMC_HPC1_LA30_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA30_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_67 +# set_property PACKAGE_PIN AK12 [get_ports "FMC_HPC1_LA30_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA30_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_67 +# set_property PACKAGE_PIN AL15 [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA26_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_67 +# set_property PACKAGE_PIN AK15 [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA26_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_67 +# set_property PACKAGE_PIN AM14 [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA27_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_67 +# set_property PACKAGE_PIN AL14 [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA27_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_67 +# #set_property PACKAGE_PIN AM16 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_67 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_67 +# #set_property PACKAGE_PIN AR15 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_67 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_67 +# set_property PACKAGE_PIN AP15 [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA29_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_67 +# set_property PACKAGE_PIN AN15 [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA29_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_67 +# set_property PACKAGE_PIN AP16 [get_ports "FMC_HPC1_LA23_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA23_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_67 +# set_property PACKAGE_PIN AN16 [get_ports "FMC_HPC1_LA23_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA23_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_67 +# set_property PACKAGE_PIN AR12 [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_67 +# set_property PACKAGE_PIN AP12 [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA18_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_67 +# #set_property PACKAGE_PIN AN13 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_67 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_67 +# #set_property PACKAGE_PIN AN14 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_67 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_67 +# set_property PACKAGE_PIN AR13 [get_ports "FMC_HPC1_LA24_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA24_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_67 +# set_property PACKAGE_PIN AP13 [get_ports "FMC_HPC1_LA24_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA24_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_67 +# set_property PACKAGE_PIN AT14 [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA17_CC_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_67 +# set_property PACKAGE_PIN AR14 [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA17_CC_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_67 +# set_property PACKAGE_PIN AV13 [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_67 +# set_property PACKAGE_PIN AV14 [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_67 +# #set_property PACKAGE_PIN AU13 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_67 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_67 +# #set_property PACKAGE_PIN AU14 [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_67 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_67 +# set_property PACKAGE_PIN AY14 [get_ports "PMOD0_0_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_67 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_0_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_67 +# set_property PACKAGE_PIN AY15 [get_ports "PMOD0_1_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_67 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_1_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_67 +# set_property PACKAGE_PIN AW15 [get_ports "PMOD0_2_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_67 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_2_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_67 +# set_property PACKAGE_PIN AV15 [get_ports "PMOD0_3_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_67 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_3_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_67 +# set_property PACKAGE_PIN AV16 [get_ports "PMOD0_4_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_67 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_4_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_67 +# set_property PACKAGE_PIN AU16 [get_ports "PMOD0_5_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_67 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_5_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_67 +# set_property PACKAGE_PIN AT15 [get_ports "PMOD0_6_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_67 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_6_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_67 +# set_property PACKAGE_PIN AT16 [get_ports "PMOD0_7_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_67 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMOD0_7_LS"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_67 +# set_property PACKAGE_PIN AW16 [get_ports "10N8842"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_67 +# set_property IOSTANDARD LVCMOSxx [get_ports "10N8842"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_67 +# #set_property PACKAGE_PIN BA12 [get_ports "VRP_67"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_67 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_67"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_67 +# set_property PACKAGE_PIN AV11 [get_ports "FMC_HPC1_LA21_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA21_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_67 +# set_property PACKAGE_PIN AU11 [get_ports "FMC_HPC1_LA21_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA21_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_67 +# set_property PACKAGE_PIN AY13 [get_ports "FMC_HPC1_LA22_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA22_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_67 +# set_property PACKAGE_PIN AW13 [get_ports "FMC_HPC1_LA22_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA22_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_67 +# set_property PACKAGE_PIN AW10 [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA28_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_67 +# set_property PACKAGE_PIN AV10 [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA28_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_67 +# set_property PACKAGE_PIN AY10 [get_ports "FMC_HPC1_LA20_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA20_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_67 +# set_property PACKAGE_PIN AW11 [get_ports "FMC_HPC1_LA20_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA20_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_67 +# set_property PACKAGE_PIN AY12 [get_ports "FMC_HPC1_LA19_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA19_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_67 +# set_property PACKAGE_PIN AW12 [get_ports "FMC_HPC1_LA19_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA19_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_67 +# set_property PACKAGE_PIN AU12 [get_ports "FMC_HPC1_LA25_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA25_N"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_67 +# set_property PACKAGE_PIN AT12 [get_ports "FMC_HPC1_LA25_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_67 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA25_P"] ;# Bank 67 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_67 +# #Other net PACKAGE_PIN AL16 - VREF_67 Bank 67 - VREF_67 +# set_property PACKAGE_PIN BB12 [get_ports "FMC_HPC1_LA10_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA10_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_66 +# set_property PACKAGE_PIN BB13 [get_ports "FMC_HPC1_LA10_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA10_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_66 +# set_property PACKAGE_PIN BB14 [get_ports "FMC_HPC1_LA09_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA09_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_66 +# set_property PACKAGE_PIN BA14 [get_ports "FMC_HPC1_LA09_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA09_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_66 +# set_property PACKAGE_PIN BA15 [get_ports "FMC_HPC1_LA11_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA11_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_66 +# set_property PACKAGE_PIN BA16 [get_ports "FMC_HPC1_LA11_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA11_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_66 +# set_property PACKAGE_PIN BD15 [get_ports "FMC_HPC1_LA07_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA07_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_66 +# set_property PACKAGE_PIN BC15 [get_ports "FMC_HPC1_LA07_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA07_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_66 +# set_property PACKAGE_PIN BC16 [get_ports "FMC_HPC1_LA15_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA15_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_66 +# set_property PACKAGE_PIN BB16 [get_ports "FMC_HPC1_LA15_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA15_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_66 +# set_property PACKAGE_PIN BC13 [get_ports "FMC_HPC1_LA12_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA12_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_66 +# set_property PACKAGE_PIN BC14 [get_ports "FMC_HPC1_LA12_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA12_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_66 +# set_property PACKAGE_PIN BB11 [get_ports "10N8224"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_66 +# set_property IOSTANDARD LVCMOSxx [get_ports "10N8224"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_66 +# set_property PACKAGE_PIN BA10 [get_ports "10N9644"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_66 +# set_property IOSTANDARD LVCMOSxx [get_ports "10N9644"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_66 +# set_property PACKAGE_PIN AW7 [get_ports "FMC_HPC1_LA14_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA14_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_66 +# set_property PACKAGE_PIN AW8 [get_ports "FMC_HPC1_LA14_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA14_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_66 +# set_property PACKAGE_PIN AY7 [get_ports "FMC_HPC1_LA13_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA13_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_66 +# set_property PACKAGE_PIN AY8 [get_ports "FMC_HPC1_LA13_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA13_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_66 +# set_property PACKAGE_PIN AV8 [get_ports "FMC_HPC1_LA16_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA16_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_66 +# set_property PACKAGE_PIN AV9 [get_ports "FMC_HPC1_LA16_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA16_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_66 +# set_property PACKAGE_PIN BB7 [get_ports "FMC_HPC1_PRSNT_M2C_B_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_66 +# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_PRSNT_M2C_B_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_66 +# set_property PACKAGE_PIN BA7 [get_ports "FMC_HPC1_PG_M2C_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_66 +# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC1_PG_M2C_LS"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_66 +# #set_property PACKAGE_PIN BB8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_66 +# #set_property PACKAGE_PIN BB9 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_66 +# set_property PACKAGE_PIN BA9 [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA00_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_66 +# set_property PACKAGE_PIN AY9 [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA00_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_66 +# set_property PACKAGE_PIN BC8 [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_66 +# set_property PACKAGE_PIN BC9 [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_66 +# #set_property PACKAGE_PIN BD10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_66 +# #set_property PACKAGE_PIN BC10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_66 +# set_property PACKAGE_PIN BF9 [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA01_CC_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_66 +# set_property PACKAGE_PIN BF10 [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA01_CC_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_66 +# #set_property PACKAGE_PIN BE9 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_66 +# #set_property PACKAGE_PIN BE10 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_66 +# #set_property PACKAGE_PIN BE7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_66 +# #set_property PACKAGE_PIN BE8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_66 +# #set_property PACKAGE_PIN BD7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_66 +# #set_property PACKAGE_PIN BD8 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_66 +# #set_property PACKAGE_PIN BF7 [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_66 +# #set_property PACKAGE_PIN BD16 [get_ports "VRP_66"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_66 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_66 +# set_property PACKAGE_PIN BF15 [get_ports "FMC_HPC1_LA08_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA08_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_66 +# set_property PACKAGE_PIN BE15 [get_ports "FMC_HPC1_LA08_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA08_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_66 +# set_property PACKAGE_PIN BF14 [get_ports "FMC_HPC1_LA05_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA05_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_66 +# set_property PACKAGE_PIN BE14 [get_ports "FMC_HPC1_LA05_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA05_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_66 +# set_property PACKAGE_PIN BE13 [get_ports "FMC_HPC1_LA06_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA06_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_66 +# set_property PACKAGE_PIN BD13 [get_ports "FMC_HPC1_LA06_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA06_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_66 +# set_property PACKAGE_PIN BD11 [get_ports "FMC_HPC1_LA02_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA02_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_66 +# set_property PACKAGE_PIN BC11 [get_ports "FMC_HPC1_LA02_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA02_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_66 +# set_property PACKAGE_PIN BF11 [get_ports "FMC_HPC1_LA04_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA04_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_66 +# set_property PACKAGE_PIN BF12 [get_ports "FMC_HPC1_LA04_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA04_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_66 +# set_property PACKAGE_PIN BE12 [get_ports "FMC_HPC1_LA03_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA03_N"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_66 +# set_property PACKAGE_PIN BD12 [get_ports "FMC_HPC1_LA03_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_66 +# set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_LA03_P"] ;# Bank 66 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_66 +# #Other net PACKAGE_PIN BA11 - VREF_66 Bank 66 - VREF_66 +# #set_property PACKAGE_PIN AL19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_DOUT_CSO_B_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_DOUT_CSO_B_65 +# set_property PACKAGE_PIN AL20 [get_ports "FPGA_EMCCLK"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_EMCCLK_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_EMCCLK"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_EMCCLK_65 +# set_property PACKAGE_PIN AP17 [get_ports "SYSMON_SDA"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SDA"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +# set_property PACKAGE_PIN AP18 [get_ports "SYSMON_SCL"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_I2C_SCLK_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SCL"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_I2C_SCLK_65 +# set_property PACKAGE_PIN AM18 [get_ports "QSPI1_DQ1"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ1"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +# set_property PACKAGE_PIN AM19 [get_ports "QSPI1_DQ0"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ0"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +# set_property PACKAGE_PIN AP20 [get_ports "QSPI1_DQ3"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ3"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_D07_65 +# set_property PACKAGE_PIN AN20 [get_ports "QSPI1_DQ2"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_DQ2"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_D06_65 +# #set_property PACKAGE_PIN AN18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_D09_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_D09_65 +# #set_property PACKAGE_PIN AN19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_D08_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_D08_65 +# #set_property PACKAGE_PIN AR17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +# #set_property PACKAGE_PIN AR18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +# set_property PACKAGE_PIN AM17 [get_ports "PCIE_PERST_LS"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T3U_N12_PERSTN0_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_PERST_LS"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T3U_N12_PERSTN0_65 +# #set_property PACKAGE_PIN AW17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T2U_N12_CSI_ADV_B_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T2U_N12_CSI_ADV_B_65 +# #set_property PACKAGE_PIN AT19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_D13_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_D13_65 +# #set_property PACKAGE_PIN AT20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_D12_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_D12_65 +# #set_property PACKAGE_PIN AU17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_D15_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_D15_65 +# #set_property PACKAGE_PIN AT17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_D14_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_D14_65 +# #set_property PACKAGE_PIN AR19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +# #set_property PACKAGE_PIN AR20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +# #set_property PACKAGE_PIN AW20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_A03_D19_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_A03_D19_65 +# #set_property PACKAGE_PIN AV20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_A02_D18_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_A02_D18_65 +# #set_property PACKAGE_PIN AU18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_A05_D21_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_A05_D21_65 +# #set_property PACKAGE_PIN AU19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_A04_D20_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_A04_D20_65 +# #set_property PACKAGE_PIN AV18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +# #set_property PACKAGE_PIN AV19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +# #set_property PACKAGE_PIN AY18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_A09_D25_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_A09_D25_65 +# #set_property PACKAGE_PIN AW18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_A08_D24_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_A08_D24_65 +# #set_property PACKAGE_PIN BA19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11N_T1U_N9_GC_A11_D27_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11N_T1U_N9_GC_A11_D27_65 +# #set_property PACKAGE_PIN AY19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11P_T1U_N8_GC_A10_D26_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L11P_T1U_N8_GC_A10_D26_65 +# #set_property PACKAGE_PIN BB17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +# #set_property PACKAGE_PIN BA17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +# #set_property PACKAGE_PIN BC19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_A15_D31_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_A15_D31_65 +# #set_property PACKAGE_PIN BB19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_A14_D30_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_A14_D30_65 +# #set_property PACKAGE_PIN BC18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_A17_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_A17_65 +# #set_property PACKAGE_PIN BB18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_A16_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_A16_65 +# #set_property PACKAGE_PIN BA20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +# #set_property PACKAGE_PIN AY20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +# #set_property PACKAGE_PIN AY17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T1U_N12_SMBALERT_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T1U_N12_SMBALERT_65 +# #set_property PACKAGE_PIN BF21 [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_A28_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_A28_65 +# #set_property PACKAGE_PIN BD17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_A21_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_A21_65 +# #set_property PACKAGE_PIN BD18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_A20_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_A20_65 +# #set_property PACKAGE_PIN BD20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_A23_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_A23_65 +# #set_property PACKAGE_PIN BC20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_A22_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_A22_65 +# #set_property PACKAGE_PIN BE17 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +# #set_property PACKAGE_PIN BE18 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +# #set_property PACKAGE_PIN BF19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_A27_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_A27_65 +# #set_property PACKAGE_PIN BE19 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_A26_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_A26_65 +# set_property PACKAGE_PIN BF16 [get_ports "QSPI1_CS_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSPI1_CS_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_FWE_FCS2_B_65 +# set_property PACKAGE_PIN BF17 [get_ports "BPI_FLASH_OE_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_FOE_B_65 +# set_property IOSTANDARD LVCMOS18 [get_ports "BPI_FLASH_OE_B"] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_FOE_B_65 +# #set_property PACKAGE_PIN BF20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_RS1_65 +# #set_property PACKAGE_PIN BE20 [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_RS0_65 +# #set_property IOSTANDARD LVCMOSxx [get_ports ""] ;# Bank 65 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_RS0_65 +# #Other net PACKAGE_PIN AL17 - 8N8196 Bank 65 - VREF_65 +# set_property PACKAGE_PIN AM24 [get_ports "IIC_MAIN_SCL"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MAIN_SCL"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24N_T3U_N11_64 +# set_property PACKAGE_PIN AL24 [get_ports "IIC_MAIN_SDA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MAIN_SDA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L24P_T3U_N10_64 +# set_property PACKAGE_PIN AM21 [get_ports "QSFP1_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23N_T3U_N9_64 +# set_property PACKAGE_PIN AL21 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L23P_T3U_N8_64 +# set_property PACKAGE_PIN AM22 [get_ports "QSFP1_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_64 +# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_64 +# set_property PACKAGE_PIN AM23 [get_ports "QSFP1_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_64 +# set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_64 +# set_property PACKAGE_PIN AP21 [get_ports "QSFP1_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21N_T3L_N5_AD8N_64 +# set_property PACKAGE_PIN AN21 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L21P_T3L_N4_AD8P_64 +# set_property PACKAGE_PIN AN23 [get_ports "QSFP2_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_MODSELL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20N_T3L_N3_AD1N_64 +# set_property PACKAGE_PIN AN24 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L20P_T3L_N2_AD1P_64 +# set_property PACKAGE_PIN AP22 [get_ports "QSFP2_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_64 +# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_64 +# set_property PACKAGE_PIN AP23 [get_ports "QSFP2_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_64 +# set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_64 +# set_property PACKAGE_PIN AL25 [get_ports "IIC_MUX_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T3U_N12_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "IIC_MUX_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T3U_N12_64 +# set_property PACKAGE_PIN AT21 [get_ports "QSFP2_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T2U_N12_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_INTL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T2U_N12_64 +# set_property PACKAGE_PIN AT24 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18N_T2U_N11_AD2N_64 +# set_property PACKAGE_PIN AR24 [get_ports "PHY1_PDWN_B_I_INT_B_O"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_PDWN_B_I_INT_B_O"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L18P_T2U_N10_AD2P_64 +# set_property PACKAGE_PIN AR22 [get_ports "PHY1_GPIO_0"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_GPIO_0"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17N_T2U_N9_AD10N_64 +# set_property PACKAGE_PIN AR23 [get_ports "PHY1_MDIO"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_MDIO"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L17P_T2U_N8_AD10P_64 +# set_property PACKAGE_PIN AV24 [get_ports "PHY1_SGMII_OUT_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_64 +# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_OUT_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_64 +# set_property PACKAGE_PIN AU24 [get_ports "PHY1_SGMII_OUT_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_64 +# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_OUT_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_64 +# set_property PACKAGE_PIN AV21 [get_ports "PHY1_SGMII_IN_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_64 +# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_IN_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15N_T2L_N5_AD11N_64 +# set_property PACKAGE_PIN AU21 [get_ports "PHY1_SGMII_IN_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_64 +# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_IN_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L15P_T2L_N4_AD11P_64 +# set_property PACKAGE_PIN AV23 [get_ports "PHY1_MDC"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_MDC"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14N_T2L_N3_GC_64 +# set_property PACKAGE_PIN AU23 [get_ports "PHY1_CLKOUT"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_CLKOUT"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L14P_T2L_N2_GC_64 +# set_property PACKAGE_PIN AU22 [get_ports "PHY1_SGMII_CLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_64 +# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_CLK_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_64 +# set_property PACKAGE_PIN AT22 [get_ports "PHY1_SGMII_CLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_64 +# set_property IOSTANDARD LVDS [get_ports "PHY1_SGMII_CLK_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_64 +# set_property PACKAGE_PIN AW22 [get_ports "USER_SI570_CLOCK1_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_64 +# set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12N_T1U_N11_GC_64 +# set_property PACKAGE_PIN AW23 [get_ports "USER_SI570_CLOCK1_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_64 +# set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_P"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L12P_T1U_N10_GC_64 +# set_property PACKAGE_PIN BA22 [get_ports "QSFP1_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_64 +# set_property PACKAGE_PIN AY22 [get_ports "QSFP2_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP2_RESETL_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_64 +# set_property PACKAGE_PIN AY25 [get_ports "USB_UART_RTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_RTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9N_T1L_N5_AD12N_64 + +# set_property PACKAGE_PIN BB22 [get_ports "USB_UART_CTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_CTS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8P_T1L_N2_AD5P_64 +# set_property PACKAGE_PIN BA24 [get_ports "SYSCTLR_GPIO_7"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_7"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_64 +# set_property PACKAGE_PIN BA25 [get_ports "SYSCTLR_GPIO_6"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_6"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_64 +# set_property PACKAGE_PIN BA21 [get_ports "PHY1_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T1U_N12_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "PHY1_RESET_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T1U_N12_64 +# #set_property PACKAGE_PIN BC24 [get_ports "PCIE_WAKE_B_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_64 +# #set_property IOSTANDARD LVCMOS18 [get_ports "PCIE_WAKE_B_LS"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_T0U_N12_VRP_64 +# set_property PACKAGE_PIN BD21 [get_ports "SYSCTLR_GPIO_5"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_GPIO_5"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6N_T0U_N11_AD6N_64 +# set_property PACKAGE_PIN BC21 [get_ports "SI5328_RST_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "SI5328_RST_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L6P_T0U_N10_AD6P_64 +# set_property PACKAGE_PIN BB23 [get_ports "PMBUS_ALERT_FPGA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "PMBUS_ALERT_FPGA"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5N_T0U_N9_AD14N_64 +# set_property PACKAGE_PIN BB24 [get_ports "GPIO_SW_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_N"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L5P_T0U_N8_AD14P_64 +# set_property PACKAGE_PIN BF22 [get_ports "GPIO_SW_W"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_W"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_64 +# set_property PACKAGE_PIN BE22 [get_ports "GPIO_SW_S"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_S"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_64 +# set_property PACKAGE_PIN BE23 [get_ports "GPIO_SW_E"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_E"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3N_T0L_N5_AD15N_64 +# set_property PACKAGE_PIN BD23 [get_ports "GPIO_SW_C"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_SW_C"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L3P_T0L_N4_AD15P_64 +# set_property PACKAGE_PIN BD22 [get_ports "FIREFLY_MODPRS_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_MODPRS_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2N_T0L_N3_64 +# set_property PACKAGE_PIN BC23 [get_ports "FIREFLY_MODSEL_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_MODSEL_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L2P_T0L_N2_64 +# set_property PACKAGE_PIN BF24 [get_ports "FIREFLY_INT_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_INT_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1N_T0L_N1_DBC_64 +# set_property PACKAGE_PIN BE24 [get_ports "FIREFLY_RESET_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_64 +# set_property IOSTANDARD LVCMOS18 [get_ports "FIREFLY_RESET_LS_B"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L1P_T0L_N0_DBC_64 +# #Other net PACKAGE_PIN AL22 - 30N4994 Bank 64 - VREF_64 +# set_property PACKAGE_PIN AG33 [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_43 +# set_property PACKAGE_PIN AG32 [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_43 +# set_property PACKAGE_PIN AH31 [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_43 +# set_property PACKAGE_PIN AG31 [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43 +# set_property PACKAGE_PIN AH35 [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_43 +# set_property PACKAGE_PIN AG34 [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_43 +# set_property PACKAGE_PIN AH34 [get_ports "FMCP_HSPC_LA12_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA12_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_43 +# set_property PACKAGE_PIN AH33 [get_ports "FMCP_HSPC_LA12_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA12_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_43 +# set_property PACKAGE_PIN AJ36 [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43 +# set_property PACKAGE_PIN AJ35 [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43 +# set_property PACKAGE_PIN AK33 [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43 +# set_property PACKAGE_PIN AJ33 [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43 +# set_property PACKAGE_PIN AH30 [get_ports "9N9738"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_43 +# set_property IOSTANDARD LVCMOSxx [get_ports "9N9738"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_43 +# set_property PACKAGE_PIN AM31 [get_ports "9N9739"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_43 +# set_property IOSTANDARD LVCMOSxx [get_ports "9N9739"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_43 +# set_property PACKAGE_PIN AK30 [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_43 +# set_property PACKAGE_PIN AK29 [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_43 +# set_property PACKAGE_PIN AJ31 [get_ports "FMCP_HSPC_LA11_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA11_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_43 +# set_property PACKAGE_PIN AJ30 [get_ports "FMCP_HSPC_LA11_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA11_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_43 +# set_property PACKAGE_PIN AL31 [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43 +# set_property PACKAGE_PIN AL30 [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43 +# set_property PACKAGE_PIN AM29 [get_ports "FMCP_HSPC_Z_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_43 +# set_property IOSTANDARD LVCMOS18 [get_ports "FMCP_HSPC_Z_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_43 +# set_property PACKAGE_PIN AL29 [get_ports "FMC_VADJ_ON_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_43 +# set_property IOSTANDARD LVCMOS18 [get_ports "FMC_VADJ_ON_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_43 +# set_property PACKAGE_PIN AK32 [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_43 +# set_property PACKAGE_PIN AJ32 [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_43 +# set_property PACKAGE_PIN AM32 [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_43 +# set_property PACKAGE_PIN AL32 [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_43 +# set_property PACKAGE_PIN AM34 [get_ports "FMCP_HSPC_PG_M2C_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_PG_M2C_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_43 +# set_property PACKAGE_PIN AM33 [get_ports "FMCP_HSPC_H_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_43 +# set_property IOSTANDARD LVCMOS18 [get_ports "FMCP_HSPC_H_PRSNT_M2C_B_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_43 +# set_property PACKAGE_PIN AL34 [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_43 +# set_property PACKAGE_PIN AK34 [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_43 +# set_property PACKAGE_PIN AP33 [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_43 +# set_property PACKAGE_PIN AN33 [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_43 +# set_property PACKAGE_PIN AN36 [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_43 +# set_property PACKAGE_PIN AM36 [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_43 +# set_property PACKAGE_PIN AN35 [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_43 +# set_property PACKAGE_PIN AN34 [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_43 +# set_property PACKAGE_PIN AL36 [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_43 +# set_property PACKAGE_PIN AL35 [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_43 +# set_property PACKAGE_PIN AK35 [get_ports "VADJ_1V8_PGOOD_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_43 +# set_property IOSTANDARD LVCMOS18 [get_ports "VADJ_1V8_PGOOD_LS"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_43 +# #set_property PACKAGE_PIN AR34 [get_ports "VRP_43"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_43 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_43"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_43 +# set_property PACKAGE_PIN AT37 [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_43 +# set_property PACKAGE_PIN AR37 [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_43 +# set_property PACKAGE_PIN AP37 [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_43 +# set_property PACKAGE_PIN AP36 [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_43 +# set_property PACKAGE_PIN AT40 [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_43 +# set_property PACKAGE_PIN AT39 [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_43 +# set_property PACKAGE_PIN AR35 [get_ports "FMCP_HSPC_LA10_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA10_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43 +# set_property PACKAGE_PIN AP35 [get_ports "FMCP_HSPC_LA10_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA10_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43 +# set_property PACKAGE_PIN AT36 [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43 +# set_property PACKAGE_PIN AT35 [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43 +# set_property PACKAGE_PIN AR38 [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43 +# set_property PACKAGE_PIN AP38 [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43 +# #Other net PACKAGE_PIN AJ29 - VREF_43 Bank 43 - VREF_43 +# set_property PACKAGE_PIN AV39 [get_ports "DDR4_C2_DQ63"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ63"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_42 +# set_property PACKAGE_PIN AV38 [get_ports "DDR4_C2_DQ62"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ62"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_42 +# set_property PACKAGE_PIN AU39 [get_ports "DDR4_C2_DQ61"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ61"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_42 +# set_property PACKAGE_PIN AU38 [get_ports "DDR4_C2_DQ60"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ60"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_42 +# set_property PACKAGE_PIN AW38 [get_ports "DDR4_C2_DQS7_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_42 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS7_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_42 +# set_property PACKAGE_PIN AW37 [get_ports "DDR4_C2_DQS7_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_42 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS7_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_42 +# set_property PACKAGE_PIN AV40 [get_ports "DDR4_C2_DQ59"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ59"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_42 +# set_property PACKAGE_PIN AU40 [get_ports "DDR4_C2_DQ58"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ58"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_42 +# set_property PACKAGE_PIN AW36 [get_ports "DDR4_C2_DQ57"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ57"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_42 +# set_property PACKAGE_PIN AW35 [get_ports "DDR4_C2_DQ56"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ56"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_42 +# set_property PACKAGE_PIN AV36 [get_ports "GPIO_LED6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_42 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_42 +# set_property PACKAGE_PIN AV35 [get_ports "DDR4_C2_DM7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_42 +# set_property PACKAGE_PIN AU37 [get_ports "GPIO_LED5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T3U_N12_42 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T3U_N12_42 +# set_property PACKAGE_PIN AY35 [get_ports "DDR4_C2_TEN"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T2U_N12_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_TEN"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T2U_N12_42 +# set_property PACKAGE_PIN AY39 [get_ports "DDR4_C2_DQ55"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ55"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_42 +# set_property PACKAGE_PIN AY38 [get_ports "DDR4_C2_DQ54"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ54"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_42 +# set_property PACKAGE_PIN AY40 [get_ports "DDR4_C2_DQ53"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ53"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_42 +# set_property PACKAGE_PIN AW40 [get_ports "DDR4_C2_DQ52"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ52"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_42 +# set_property PACKAGE_PIN BA36 [get_ports "DDR4_C2_DQS6_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_42 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS6_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_42 +# set_property PACKAGE_PIN BA35 [get_ports "DDR4_C2_DQS6_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_42 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS6_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_42 +# set_property PACKAGE_PIN BA40 [get_ports "DDR4_C2_DQ51"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ51"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_42 +# set_property PACKAGE_PIN BA39 [get_ports "DDR4_C2_DQ50"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ50"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_42 +# set_property PACKAGE_PIN BB37 [get_ports "DDR4_C2_DQ49"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ49"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_42 +# set_property PACKAGE_PIN BB36 [get_ports "DDR4_C2_DQ48"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ48"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_42 +# set_property PACKAGE_PIN BA37 [get_ports "GPIO_LED7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_42 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED7"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_42 +# set_property PACKAGE_PIN AY37 [get_ports "DDR4_C2_DM6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM6"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_42 +# set_property PACKAGE_PIN BD38 [get_ports "DDR4_C2_DQ47"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ47"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_42 +# set_property PACKAGE_PIN BC38 [get_ports "DDR4_C2_DQ46"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ46"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_42 +# set_property PACKAGE_PIN BB39 [get_ports "DDR4_C2_DQ45"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ45"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_42 +# set_property PACKAGE_PIN BB38 [get_ports "DDR4_C2_DQ44"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ44"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_42 +# set_property PACKAGE_PIN BF39 [get_ports "DDR4_C2_DQS5_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_42 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS5_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_42 +# set_property PACKAGE_PIN BE39 [get_ports "DDR4_C2_DQS5_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_42 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS5_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_42 +# set_property PACKAGE_PIN BD40 [get_ports "DDR4_C2_DQ43"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ43"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_42 +# set_property PACKAGE_PIN BC39 [get_ports "DDR4_C2_DQ42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_42 +# set_property PACKAGE_PIN BE38 [get_ports "DDR4_C2_DQ41"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ41"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_42 +# set_property PACKAGE_PIN BD37 [get_ports "DDR4_C2_DQ40"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ40"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_42 +# set_property PACKAGE_PIN BF40 [get_ports "MAXIM_CABLE_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_42 +# set_property IOSTANDARD LVCMOS12 [get_ports "MAXIM_CABLE_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_42 +# set_property PACKAGE_PIN BE40 [get_ports "DDR4_C2_DM5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM5"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_42 +# set_property PACKAGE_PIN BC40 [get_ports "FAN_OT_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T1U_N12_42 +# set_property IOSTANDARD LVCMOS12 [get_ports "FAN_OT_LS_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T1U_N12_42 +# #set_property PACKAGE_PIN BB34 [get_ports "VRP_42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_42 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_42"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_42 +# set_property PACKAGE_PIN BF37 [get_ports "DDR4_C2_DQ39"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ39"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_42 +# set_property PACKAGE_PIN BF36 [get_ports "DDR4_C2_DQ38"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ38"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_42 +# set_property PACKAGE_PIN BE37 [get_ports "DDR4_C2_DQ37"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ37"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_42 +# set_property PACKAGE_PIN BD36 [get_ports "DDR4_C2_DQ36"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ36"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_42 +# set_property PACKAGE_PIN BF35 [get_ports "DDR4_C2_DQS4_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_42 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS4_C"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_42 +# set_property PACKAGE_PIN BE35 [get_ports "DDR4_C2_DQS4_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_42 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS4_T"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_42 +# set_property PACKAGE_PIN BC36 [get_ports "DDR4_C2_DQ35"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ35"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_42 +# set_property PACKAGE_PIN BC35 [get_ports "DDR4_C2_DQ34"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ34"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_42 +# set_property PACKAGE_PIN BF34 [get_ports "DDR4_C2_DQ33"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ33"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_42 +# set_property PACKAGE_PIN BE34 [get_ports "DDR4_C2_DQ32"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ32"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_42 +# set_property PACKAGE_PIN BD35 [get_ports "DDR4_C2_RESET_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_42 +# set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_C2_RESET_B"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_42 +# set_property PACKAGE_PIN BC34 [get_ports "DDR4_C2_DM4"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_42 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM4"] ;# Bank 42 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_42 +# #Other net PACKAGE_PIN AU36 - 5N11683 Bank 42 - VREF_42 +# set_property PACKAGE_PIN AM27 [get_ports "DDR4_C2_A0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_41 +# set_property PACKAGE_PIN AL27 [get_ports "DDR4_C2_A1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_41 +# set_property PACKAGE_PIN AP26 [get_ports "DDR4_C2_A2"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A2"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_41 +# set_property PACKAGE_PIN AP25 [get_ports "DDR4_C2_A3"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A3"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_41 +# set_property PACKAGE_PIN AN28 [get_ports "DDR4_C2_A4"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A4"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_41 +# set_property PACKAGE_PIN AM28 [get_ports "DDR4_C2_A5"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A5"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_41 +# set_property PACKAGE_PIN AP28 [get_ports "DDR4_C2_A6"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A6"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_41 +# set_property PACKAGE_PIN AP27 [get_ports "DDR4_C2_A7"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A7"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_41 +# set_property PACKAGE_PIN AN26 [get_ports "DDR4_C2_A8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_41 +# set_property PACKAGE_PIN AM26 [get_ports "DDR4_C2_A9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_41 +# set_property PACKAGE_PIN AR28 [get_ports "DDR4_C2_A10"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A10"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_41 +# set_property PACKAGE_PIN AR27 [get_ports "DDR4_C2_A11"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A11"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_41 +# set_property PACKAGE_PIN AN25 [get_ports "DDR4_C2_ACT_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T3U_N12_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ACT_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T3U_N12_41 +# set_property PACKAGE_PIN AV25 [get_ports "DDR4_C2_A12"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T2U_N12_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A12"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T2U_N12_41 +# set_property PACKAGE_PIN AT25 [get_ports "DDR4_C2_A13"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A13"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_41 +# set_property PACKAGE_PIN AR25 [get_ports "DDR4_C2_BA0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BA0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_41 +# set_property PACKAGE_PIN AU28 [get_ports "DDR4_C2_BA1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BA1"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_41 +# set_property PACKAGE_PIN AU27 [get_ports "DDR4_C2_BG0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_BG0"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_41 +# set_property PACKAGE_PIN AT27 [get_ports "DDR4_C2_CK_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_41 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_CK_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_41 +# set_property PACKAGE_PIN AT26 [get_ports "DDR4_C2_CK_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_41 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_CK_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_41 +# set_property PACKAGE_PIN AW28 [get_ports "DDR4_C2_CKE"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_CKE"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_41 +# set_property PACKAGE_PIN AV28 [get_ports "DDR4_C2_A14_WE_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A14_WE_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_41 +# set_property PACKAGE_PIN AV26 [get_ports "DDR4_C2_A16_RAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A16_RAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_41 +# set_property PACKAGE_PIN AU26 [get_ports "DDR4_C2_A15_CAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_A15_CAS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_41 +# set_property PACKAGE_PIN AW27 [get_ports "250MHZ_CLK2_N"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_41 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK2_N"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_41 +# set_property PACKAGE_PIN AW26 [get_ports "250MHZ_CLK2_P"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_41 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK2_P"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_41 +# set_property PACKAGE_PIN BB27 [get_ports "DDR4_C2_DQ79"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ79"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_41 +# set_property PACKAGE_PIN BA27 [get_ports "DDR4_C2_DQ78"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ78"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_41 +# set_property PACKAGE_PIN AY28 [get_ports "DDR4_C2_DQ77"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ77"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_41 +# set_property PACKAGE_PIN AY27 [get_ports "DDR4_C2_DQ76"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ76"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_41 +# set_property PACKAGE_PIN BB26 [get_ports "DDR4_C2_DQS9_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_41 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS9_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_41 +# set_property PACKAGE_PIN BA26 [get_ports "DDR4_C2_DQS9_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_41 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS9_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_41 +# set_property PACKAGE_PIN BC28 [get_ports "DDR4_C2_DQ75"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ75"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_41 +# set_property PACKAGE_PIN BB28 [get_ports "DDR4_C2_DQ74"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ74"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_41 +# set_property PACKAGE_PIN BC26 [get_ports "DDR4_C2_DQ73"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ73"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_41 +# set_property PACKAGE_PIN BC25 [get_ports "DDR4_C2_DQ72"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ72"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_41 +# set_property PACKAGE_PIN BB29 [get_ports "DDR4_C2_ODT"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ODT"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_41 +# set_property PACKAGE_PIN BA29 [get_ports "DDR4_C2_DM9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_DM9"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_41 +# set_property PACKAGE_PIN AY29 [get_ports "DDR4_C2_CS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T1U_N12_41 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_CS_B"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T1U_N12_41 +# #set_property PACKAGE_PIN BC29 [get_ports "VRP_41"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_41 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_41"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_41 +# set_property PACKAGE_PIN BD26 [get_ports "DDR4_C2_DQ71"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ71"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_41 +# set_property PACKAGE_PIN BD25 [get_ports "DDR4_C2_DQ70"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ70"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_41 +# set_property PACKAGE_PIN BE27 [get_ports "DDR4_C2_DQ69"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ69"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_41 +# set_property PACKAGE_PIN BD27 [get_ports "DDR4_C2_DQ68"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ68"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_41 +# set_property PACKAGE_PIN BF25 [get_ports "DDR4_C2_DQS8_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_41 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS8_C"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_41 +# set_property PACKAGE_PIN BE25 [get_ports "DDR4_C2_DQS8_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_41 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS8_T"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_41 +# set_property PACKAGE_PIN BE28 [get_ports "DDR4_C2_DQ67"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ67"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_41 +# set_property PACKAGE_PIN BD28 [get_ports "DDR4_C2_DQ66"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ66"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_41 +# set_property PACKAGE_PIN BF27 [get_ports "DDR4_C2_DQ65"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ65"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_41 +# set_property PACKAGE_PIN BF26 [get_ports "DDR4_C2_DQ64"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ64"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_41 +# set_property PACKAGE_PIN BF29 [get_ports "DDR4_C2_PAR"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_PAR"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_41 +# set_property PACKAGE_PIN BE29 [get_ports "DDR4_C2_DM8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_41 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM8"] ;# Bank 41 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_41 +# #Other net PACKAGE_PIN AL26 - 6N5608 Bank 41 - VREF_41 +# set_property PACKAGE_PIN AN31 [get_ports "DDR4_C2_DQ31"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ31"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_40 +# set_property PACKAGE_PIN AN30 [get_ports "DDR4_C2_DQ30"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ30"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_40 +# set_property PACKAGE_PIN AR30 [get_ports "DDR4_C2_DQ29"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ29"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_40 +# set_property PACKAGE_PIN AP30 [get_ports "DDR4_C2_DQ28"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ28"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_40 +# set_property PACKAGE_PIN AP32 [get_ports "DDR4_C2_DQS3_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_40 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS3_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_40 +# set_property PACKAGE_PIN AP31 [get_ports "DDR4_C2_DQS3_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_40 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS3_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_40 +# set_property PACKAGE_PIN AT30 [get_ports "DDR4_C2_DQ27"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ27"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_40 +# set_property PACKAGE_PIN AT29 [get_ports "DDR4_C2_DQ26"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ26"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_40 +# set_property PACKAGE_PIN AT34 [get_ports "DDR4_C2_DQ25"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ25"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_40 +# set_property PACKAGE_PIN AR33 [get_ports "DDR4_C2_DQ24"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ24"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_40 +# set_property PACKAGE_PIN AT32 [get_ports "GPIO_LED0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_40 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_40 +# set_property PACKAGE_PIN AR32 [get_ports "DDR4_C2_DM3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_40 +# set_property PACKAGE_PIN AR29 [get_ports "DDR4_C2_ALERT_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T3U_N12_40 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C2_ALERT_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T3U_N12_40 +# set_property PACKAGE_PIN AV34 [get_ports "GPIO_LED1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T2U_N12_40 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T2U_N12_40 +# set_property PACKAGE_PIN AV31 [get_ports "DDR4_C2_DQ23"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ23"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_40 +# set_property PACKAGE_PIN AU31 [get_ports "DDR4_C2_DQ22"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ22"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_40 +# set_property PACKAGE_PIN AU32 [get_ports "DDR4_C2_DQ21"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ21"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_40 +# set_property PACKAGE_PIN AT31 [get_ports "DDR4_C2_DQ20"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ20"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_40 +# set_property PACKAGE_PIN AV29 [get_ports "DDR4_C2_DQS2_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_40 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS2_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_40 +# set_property PACKAGE_PIN AU29 [get_ports "DDR4_C2_DQS2_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_40 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS2_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_40 +# set_property PACKAGE_PIN AU34 [get_ports "DDR4_C2_DQ19"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ19"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_40 +# set_property PACKAGE_PIN AU33 [get_ports "DDR4_C2_DQ18"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ18"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_40 +# set_property PACKAGE_PIN AW30 [get_ports "DDR4_C2_DQ17"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ17"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_40 +# set_property PACKAGE_PIN AV30 [get_ports "DDR4_C2_DQ16"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ16"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_40 +# set_property PACKAGE_PIN AW33 [get_ports "FAN_FAIL_LS_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_40 +# set_property IOSTANDARD LVCMOS12 [get_ports "FAN_FAIL_LS_B"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_40 +# set_property PACKAGE_PIN AV33 [get_ports "DDR4_C2_DM2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_40 +# set_property PACKAGE_PIN AY33 [get_ports "DDR4_C2_DQ15"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ15"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_40 +# set_property PACKAGE_PIN AY32 [get_ports "DDR4_C2_DQ14"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ14"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_40 +# set_property PACKAGE_PIN AW32 [get_ports "DDR4_C2_DQ13"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ13"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_40 +# set_property PACKAGE_PIN AW31 [get_ports "DDR4_C2_DQ12"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ12"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_40 +# set_property PACKAGE_PIN BA34 [get_ports "DDR4_C2_DQS1_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQS1_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_40 +# set_property PACKAGE_PIN AY34 [get_ports "DDR4_C2_DQS1_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQS1_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_40 +# set_property PACKAGE_PIN BA31 [get_ports "DDR4_C2_DQ11"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ11"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_40 +# set_property PACKAGE_PIN BA30 [get_ports "DDR4_C2_DQ10"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ10"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_40 +# set_property PACKAGE_PIN BB33 [get_ports "DDR4_C2_DQ9"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ9"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_40 +# set_property PACKAGE_PIN BA32 [get_ports "DDR4_C2_DQ8"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ8"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_40 +# set_property PACKAGE_PIN BB32 [get_ports "GPIO_LED3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_40 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_40 +# set_property PACKAGE_PIN BB31 [get_ports "DDR4_C2_DM1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_40 +# set_property PACKAGE_PIN AY30 [get_ports "GPIO_LED2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T1U_N12_40 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T1U_N12_40 +# #set_property PACKAGE_PIN BC30 [get_ports "VRP_40"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_40 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_40"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_40 +# set_property PACKAGE_PIN BD31 [get_ports "DDR4_C2_DQ7"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ7"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_40 +# set_property PACKAGE_PIN BC31 [get_ports "DDR4_C2_DQ6"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ6"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_40 +# set_property PACKAGE_PIN BD33 [get_ports "DDR4_C2_DQ5"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ5"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_40 +# set_property PACKAGE_PIN BC33 [get_ports "DDR4_C2_DQ4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_40 +# set_property PACKAGE_PIN BF31 [get_ports "DDR4_C2_DQS0_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_40 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS0_C"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_40 +# set_property PACKAGE_PIN BF30 [get_ports "DDR4_C2_DQS0_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_40 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C2_DQS0_T"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_40 +# set_property PACKAGE_PIN BE33 [get_ports "DDR4_C2_DQ3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ3"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_40 +# set_property PACKAGE_PIN BD32 [get_ports "DDR4_C2_DQ2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ2"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_40 +# set_property PACKAGE_PIN BE30 [get_ports "DDR4_C2_DQ1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ1"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_40 +# set_property PACKAGE_PIN BD30 [get_ports "DDR4_C2_DQ0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DQ0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_40 +# set_property PACKAGE_PIN BF32 [get_ports "GPIO_LED4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_40 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_LED4"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_40 +# set_property PACKAGE_PIN BE32 [get_ports "DDR4_C2_DM0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_40 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C2_DM0"] ;# Bank 40 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_40 +# #Other net PACKAGE_PIN AN29 - 5N11680 Bank 40 - VREF_40 +# set_property PACKAGE_PIN B20 [get_ports "DDR4_C1_DQ39"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ39"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_73 +# set_property PACKAGE_PIN C20 [get_ports "DDR4_C1_DQ38"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ38"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_73 +# set_property PACKAGE_PIN D19 [get_ports "DDR4_C1_DQ37"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ37"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_73 +# set_property PACKAGE_PIN D20 [get_ports "DDR4_C1_DQ36"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ36"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_73 +# set_property PACKAGE_PIN A18 [get_ports "DDR4_C1_DQS4_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_73 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS4_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_73 +# set_property PACKAGE_PIN A19 [get_ports "DDR4_C1_DQS4_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_73 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS4_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_73 +# set_property PACKAGE_PIN C18 [get_ports "DDR4_C1_DQ35"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ35"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_73 +# set_property PACKAGE_PIN C19 [get_ports "DDR4_C1_DQ34"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ34"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_73 +# set_property PACKAGE_PIN C17 [get_ports "DDR4_C1_DQ33"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ33"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_73 +# set_property PACKAGE_PIN D17 [get_ports "DDR4_C1_DQ32"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ32"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_73 +# set_property PACKAGE_PIN B17 [get_ports "GPIO_DIP_SW1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_73 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_73 +# set_property PACKAGE_PIN B18 [get_ports "DDR4_C1_DM4"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM4"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_73 +# set_property PACKAGE_PIN A20 [get_ports "DDR4_C1_TEN"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T3U_N12_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_TEN"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T3U_N12_73 +# set_property PACKAGE_PIN G16 [get_ports "GPIO_DIP_SW2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T2U_N12_73 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T2U_N12_73 +# set_property PACKAGE_PIN D16 [get_ports "DDR4_C1_DQ31"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ31"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_73 +# set_property PACKAGE_PIN E17 [get_ports "DDR4_C1_DQ30"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ30"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_73 +# set_property PACKAGE_PIN F20 [get_ports "DDR4_C1_DQ29"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ29"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_73 +# set_property PACKAGE_PIN G20 [get_ports "DDR4_C1_DQ28"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ28"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_73 +# set_property PACKAGE_PIN E16 [get_ports "DDR4_C1_DQS3_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_73 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS3_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_73 +# set_property PACKAGE_PIN F16 [get_ports "DDR4_C1_DQS3_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_73 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS3_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_73 +# set_property PACKAGE_PIN E18 [get_ports "DDR4_C1_DQ27"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ27"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_73 +# set_property PACKAGE_PIN E19 [get_ports "DDR4_C1_DQ26"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ26"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_73 +# set_property PACKAGE_PIN F18 [get_ports "DDR4_C1_DQ25"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ25"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_73 +# set_property PACKAGE_PIN F19 [get_ports "DDR4_C1_DQ24"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ24"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_73 +# set_property PACKAGE_PIN G17 [get_ports "5329N4285"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_73 +# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4285"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_73 +# set_property PACKAGE_PIN G18 [get_ports "DDR4_C1_DM3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_73 +# set_property PACKAGE_PIN H18 [get_ports "DDR4_C1_DQ23"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ23"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_73 +# set_property PACKAGE_PIN H19 [get_ports "DDR4_C1_DQ22"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ22"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_73 +# set_property PACKAGE_PIN H17 [get_ports "DDR4_C1_DQ21"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ21"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_73 +# set_property PACKAGE_PIN J17 [get_ports "DDR4_C1_DQ20"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ20"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_73 +# set_property PACKAGE_PIN J19 [get_ports "DDR4_C1_DQS2_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_73 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS2_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_73 +# set_property PACKAGE_PIN K19 [get_ports "DDR4_C1_DQS2_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_73 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS2_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_73 +# set_property PACKAGE_PIN K18 [get_ports "DDR4_C1_DQ19"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ19"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_73 +# set_property PACKAGE_PIN L18 [get_ports "DDR4_C1_DQ18"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ18"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_73 +# set_property PACKAGE_PIN K16 [get_ports "DDR4_C1_DQ17"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ17"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_73 +# set_property PACKAGE_PIN L16 [get_ports "DDR4_C1_DQ16"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ16"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_73 +# set_property PACKAGE_PIN J16 [get_ports "GPIO_DIP_SW3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_73 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW3"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_73 +# set_property PACKAGE_PIN K17 [get_ports "DDR4_C1_DM2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM2"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_73 +# #set_property PACKAGE_PIN T18 [get_ports "VRP_73"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_73 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_73"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_73 +# set_property PACKAGE_PIN M16 [get_ports "DDR4_C1_DQ15"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ15"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_73 +# set_property PACKAGE_PIN N17 [get_ports "DDR4_C1_DQ14"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ14"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_73 +# set_property PACKAGE_PIN N18 [get_ports "DDR4_C1_DQ13"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ13"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_73 +# set_property PACKAGE_PIN N19 [get_ports "DDR4_C1_DQ12"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ12"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_73 +# set_property PACKAGE_PIN P16 [get_ports "DDR4_C1_DQS1_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_73 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS1_C"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_73 +# set_property PACKAGE_PIN P17 [get_ports "DDR4_C1_DQS1_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_73 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS1_T"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_73 +# set_property PACKAGE_PIN M17 [get_ports "DDR4_C1_DQ11"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ11"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_73 +# set_property PACKAGE_PIN M18 [get_ports "DDR4_C1_DQ10"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ10"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_73 +# set_property PACKAGE_PIN P19 [get_ports "DDR4_C1_DQ9"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ9"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_73 +# set_property PACKAGE_PIN R19 [get_ports "DDR4_C1_DQ8"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ8"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_73 +# set_property PACKAGE_PIN R17 [get_ports "DDR4_C1_ALERT_B"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_ALERT_B"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_73 +# set_property PACKAGE_PIN R18 [get_ports "DDR4_C1_DM1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_73 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM1"] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_73 +# #Other net PACKAGE_PIN T19 - 5329N4282 Bank 73 - VREF_73 +# set_property PACKAGE_PIN A21 [get_ports "DDR4_C1_DQ71"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ71"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_72 +# set_property PACKAGE_PIN B21 [get_ports "DDR4_C1_DQ70"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ70"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_72 +# set_property PACKAGE_PIN B22 [get_ports "DDR4_C1_DQ69"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ69"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_72 +# set_property PACKAGE_PIN B23 [get_ports "DDR4_C1_DQ68"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ68"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_72 +# set_property PACKAGE_PIN C22 [get_ports "DDR4_C1_DQS8_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_72 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS8_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_72 +# set_property PACKAGE_PIN D22 [get_ports "DDR4_C1_DQS8_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_72 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS8_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_72 +# set_property PACKAGE_PIN C23 [get_ports "DDR4_C1_DQ67"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ67"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_72 +# set_property PACKAGE_PIN C24 [get_ports "DDR4_C1_DQ66"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ66"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_72 +# set_property PACKAGE_PIN A23 [get_ports "DDR4_C1_DQ65"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ65"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_72 +# set_property PACKAGE_PIN A24 [get_ports "DDR4_C1_DQ64"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ64"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_72 +# set_property PACKAGE_PIN D24 [get_ports "5329N4244"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_72 +# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4244"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_72 +# set_property PACKAGE_PIN E24 [get_ports "DDR4_C1_DM8"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM8"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_72 +# set_property PACKAGE_PIN D21 [get_ports "GPIO_DIP_SW4"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T3U_N12_72 +# set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW4"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T3U_N12_72 +# set_property PACKAGE_PIN H20 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T2U_N12_72 +# set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T2U_N12_72 +# set_property PACKAGE_PIN F23 [get_ports "DDR4_C1_DQ63"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ63"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_72 +# set_property PACKAGE_PIN F24 [get_ports "DDR4_C1_DQ62"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ62"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_72 +# set_property PACKAGE_PIN E21 [get_ports "DDR4_C1_DQ61"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ61"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_72 +# set_property PACKAGE_PIN F21 [get_ports "DDR4_C1_DQ60"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ60"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_72 +# set_property PACKAGE_PIN G23 [get_ports "DDR4_C1_DQS7_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_72 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS7_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_72 +# set_property PACKAGE_PIN H24 [get_ports "DDR4_C1_DQS7_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_72 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS7_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_72 +# set_property PACKAGE_PIN E22 [get_ports "DDR4_C1_DQ59"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ59"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_72 +# set_property PACKAGE_PIN E23 [get_ports "DDR4_C1_DQ58"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ58"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_72 +# set_property PACKAGE_PIN H22 [get_ports "DDR4_C1_DQ57"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ57"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_72 +# set_property PACKAGE_PIN H23 [get_ports "DDR4_C1_DQ56"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ56"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_72 +# set_property PACKAGE_PIN G21 [get_ports "5329N4246"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_72 +# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4246"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_72 +# set_property PACKAGE_PIN G22 [get_ports "DDR4_C1_DM7"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM7"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_72 +# set_property PACKAGE_PIN J22 [get_ports "DDR4_C1_DQ55"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ55"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_72 +# set_property PACKAGE_PIN K22 [get_ports "DDR4_C1_DQ54"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ54"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_72 +# set_property PACKAGE_PIN J21 [get_ports "DDR4_C1_DQ53"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ53"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_72 +# set_property PACKAGE_PIN K21 [get_ports "DDR4_C1_DQ52"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ52"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_72 +# set_property PACKAGE_PIN L20 [get_ports "DDR4_C1_DQS6_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_72 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS6_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_72 +# set_property PACKAGE_PIN M20 [get_ports "DDR4_C1_DQS6_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_72 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS6_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_72 +# set_property PACKAGE_PIN L21 [get_ports "DDR4_C1_DQ51"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ51"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_72 +# set_property PACKAGE_PIN M21 [get_ports "DDR4_C1_DQ50"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ50"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_72 +# set_property PACKAGE_PIN J24 [get_ports "DDR4_C1_DQ49"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ49"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_72 +# set_property PACKAGE_PIN K24 [get_ports "DDR4_C1_DQ48"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ48"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_72 +# set_property PACKAGE_PIN K23 [get_ports "5329N4248"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_72 +# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4248"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_72 +# set_property PACKAGE_PIN L23 [get_ports "DDR4_C1_DM6"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM6"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_72 +# set_property PACKAGE_PIN J20 [get_ports "5329N4257"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T1U_N12_72 +# set_property IOSTANDARD LVCMOSxx [get_ports "5329N4257"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T1U_N12_72 +# #set_property PACKAGE_PIN T21 [get_ports "VRP_72"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_72 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_72"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_72 +# set_property PACKAGE_PIN R23 [get_ports "DDR4_C1_DQ47"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ47"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_72 +# set_property PACKAGE_PIN T23 [get_ports "DDR4_C1_DQ46"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ46"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_72 +# set_property PACKAGE_PIN P22 [get_ports "DDR4_C1_DQ45"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ45"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_72 +# set_property PACKAGE_PIN R22 [get_ports "DDR4_C1_DQ44"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ44"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_72 +# set_property PACKAGE_PIN M22 [get_ports "DDR4_C1_DQS5_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_72 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS5_C"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_72 +# set_property PACKAGE_PIN N22 [get_ports "DDR4_C1_DQS5_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_72 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS5_T"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_72 +# set_property PACKAGE_PIN P21 [get_ports "DDR4_C1_DQ43"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ43"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_72 +# set_property PACKAGE_PIN R21 [get_ports "DDR4_C1_DQ42"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ42"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_72 +# set_property PACKAGE_PIN M23 [get_ports "DDR4_C1_DQ41"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ41"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_72 +# set_property PACKAGE_PIN N23 [get_ports "DDR4_C1_DQ40"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ40"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_72 +# set_property PACKAGE_PIN N20 [get_ports "DDR4_C1_RESET_B"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_72 +# set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_C1_RESET_B"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_72 +# set_property PACKAGE_PIN P20 [get_ports "DDR4_C1_DM5"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_72 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM5"] ;# Bank 72 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_72 +# #Other net PACKAGE_PIN T20 - 5329N4288 Bank 72 - VREF_72 +# set_property PACKAGE_PIN B15 [get_ports "DDR4_C1_A1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24N_T3U_N11_71 +# set_property PACKAGE_PIN B16 [get_ports "DDR4_C1_A2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L24P_T3U_N10_71 +# set_property PACKAGE_PIN C14 [get_ports "DDR4_C1_A3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23N_T3U_N9_71 +# set_property PACKAGE_PIN C15 [get_ports "DDR4_C1_A4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L23P_T3U_N8_71 +# set_property PACKAGE_PIN A13 [get_ports "DDR4_C1_A5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22N_T3U_N7_DBC_AD0N_71 +# set_property PACKAGE_PIN A14 [get_ports "DDR4_C1_A6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L22P_T3U_N6_DBC_AD0P_71 +# set_property PACKAGE_PIN A15 [get_ports "DDR4_C1_A7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21N_T3L_N5_AD8N_71 +# set_property PACKAGE_PIN A16 [get_ports "DDR4_C1_A8"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A8"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L21P_T3L_N4_AD8P_71 +# set_property PACKAGE_PIN B12 [get_ports "DDR4_C1_A9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20N_T3L_N3_AD1N_71 +# set_property PACKAGE_PIN C12 [get_ports "DDR4_C1_A10"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A10"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L20P_T3L_N2_AD1P_71 +# set_property PACKAGE_PIN B13 [get_ports "DDR4_C1_A11"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A11"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19N_T3L_N1_DBC_AD9N_71 +# set_property PACKAGE_PIN C13 [get_ports "DDR4_C1_A12"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A12"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L19P_T3L_N0_DBC_AD9P_71 +# set_property PACKAGE_PIN D14 [get_ports "DDR4_C1_A0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T3U_N12_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T3U_N12_71 +# set_property PACKAGE_PIN D15 [get_ports "DDR4_C1_A13"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T2U_N12_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A13"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T2U_N12_71 +# set_property PACKAGE_PIN H14 [get_ports "DDR4_C1_A14_WE_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A14_WE_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18N_T2U_N11_AD2N_71 +# set_property PACKAGE_PIN H15 [get_ports "DDR4_C1_A15_CAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A15_CAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L18P_T2U_N10_AD2P_71 +# set_property PACKAGE_PIN F15 [get_ports "DDR4_C1_A16_RAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_A16_RAS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17N_T2U_N9_AD10N_71 +# set_property PACKAGE_PIN G15 [get_ports "DDR4_C1_BA0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BA0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L17P_T2U_N8_AD10P_71 +# set_property PACKAGE_PIN E14 [get_ports "DDR4_C1_CK_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_CK_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16N_T2U_N7_QBC_AD3N_71 +# set_property PACKAGE_PIN F14 [get_ports "DDR4_C1_CK_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_CK_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L16P_T2U_N6_QBC_AD3P_71 +# set_property PACKAGE_PIN G13 [get_ports "DDR4_C1_BA1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BA1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15N_T2L_N5_AD11N_71 +# set_property PACKAGE_PIN H13 [get_ports "DDR4_C1_BG0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_BG0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L15P_T2L_N4_AD11P_71 +# set_property PACKAGE_PIN E13 [get_ports "DDR4_C1_ACT_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_ACT_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14N_T2L_N3_GC_71 +# set_property PACKAGE_PIN F13 [get_ports "DDR4_C1_CS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_CS_B"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L14P_T2L_N2_GC_71 +# set_property PACKAGE_PIN D12 [get_ports "250MHZ_CLK1_N"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK1_N"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71 +# set_property PACKAGE_PIN E12 [get_ports "250MHZ_CLK1_P"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 +# set_property IOSTANDARD DIFF_SSTL12 [get_ports "250MHZ_CLK1_P"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 +# set_property PACKAGE_PIN A11 [get_ports "DDR4_C1_DQ79"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ79"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12N_T1U_N11_GC_71 +# set_property PACKAGE_PIN B11 [get_ports "DDR4_C1_DQ78"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ78"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L12P_T1U_N10_GC_71 +# set_property PACKAGE_PIN B10 [get_ports "DDR4_C1_DQ77"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ77"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11N_T1U_N9_GC_71 +# set_property PACKAGE_PIN C10 [get_ports "DDR4_C1_DQ76"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ76"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L11P_T1U_N8_GC_71 +# set_property PACKAGE_PIN A8 [get_ports "DDR4_C1_DQS9_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_71 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS9_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10N_T1U_N7_QBC_AD4N_71 +# set_property PACKAGE_PIN A9 [get_ports "DDR4_C1_DQS9_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_71 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS9_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L10P_T1U_N6_QBC_AD4P_71 +# set_property PACKAGE_PIN B7 [get_ports "DDR4_C1_DQ75"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ75"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9N_T1L_N5_AD12N_71 +# set_property PACKAGE_PIN B8 [get_ports "DDR4_C1_DQ74"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ74"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L9P_T1L_N4_AD12P_71 +# set_property PACKAGE_PIN C7 [get_ports "DDR4_C1_DQ73"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ73"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8N_T1L_N3_AD5N_71 +# set_property PACKAGE_PIN D7 [get_ports "DDR4_C1_DQ72"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ72"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L8P_T1L_N2_AD5P_71 +# set_property PACKAGE_PIN C8 [get_ports "DDR4_C1_ODT"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_ODT"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7N_T1L_N1_QBC_AD13N_71 +# set_property PACKAGE_PIN C9 [get_ports "DDR4_C1_DM9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM9"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L7P_T1L_N0_QBC_AD13P_71 +# set_property PACKAGE_PIN A10 [get_ports "DDR4_C1_CKE"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T1U_N12_71 +# set_property IOSTANDARD SSTL12 [get_ports "DDR4_C1_CKE"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T1U_N12_71 +# #set_property PACKAGE_PIN D8 [get_ports "VRP_71"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_71 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_71"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_T0U_N12_VRP_71 +# set_property PACKAGE_PIN D9 [get_ports "DDR4_C1_DQ7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ7"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6N_T0U_N11_AD6N_71 +# set_property PACKAGE_PIN E9 [get_ports "DDR4_C1_DQ6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ6"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L6P_T0U_N10_AD6P_71 +# set_property PACKAGE_PIN G12 [get_ports "DDR4_C1_DQ5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ5"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5N_T0U_N9_AD14N_71 +# set_property PACKAGE_PIN H12 [get_ports "DDR4_C1_DQ4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ4"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L5P_T0U_N8_AD14P_71 +# set_property PACKAGE_PIN D10 [get_ports "DDR4_C1_DQS0_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_71 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS0_C"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4N_T0U_N7_DBC_AD7N_71 +# set_property PACKAGE_PIN D11 [get_ports "DDR4_C1_DQS0_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_71 +# set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_C1_DQS0_T"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L4P_T0U_N6_DBC_AD7P_71 +# set_property PACKAGE_PIN F9 [get_ports "DDR4_C1_DQ3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ3"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3N_T0L_N5_AD15N_71 +# set_property PACKAGE_PIN F10 [get_ports "DDR4_C1_DQ2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ2"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L3P_T0L_N4_AD15P_71 +# set_property PACKAGE_PIN E11 [get_ports "DDR4_C1_DQ1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ1"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2N_T0L_N3_71 +# set_property PACKAGE_PIN F11 [get_ports "DDR4_C1_DQ0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DQ0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L2P_T0L_N2_71 +# set_property PACKAGE_PIN G10 [get_ports "DDR4_C1_PAR"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_PAR"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1N_T0L_N1_DBC_71 +# set_property PACKAGE_PIN G11 [get_ports "DDR4_C1_DM0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_71 +# set_property IOSTANDARD POD12 [get_ports "DDR4_C1_DM0"] ;# Bank 71 VCCO - VCC1V2_FPGA - IO_L1P_T0L_N0_DBC_71 +# #Other net PACKAGE_PIN J15 - 7N8237 Bank 71 - VREF_71 +# set_property PACKAGE_PIN J12 [get_ports "FMCP_HSPC_HA22_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA22_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24N_T3U_N11_70 +# set_property PACKAGE_PIN K12 [get_ports "FMCP_HSPC_HA22_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA22_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L24P_T3U_N10_70 +# set_property PACKAGE_PIN K13 [get_ports "FMCP_HSPC_HA21_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA21_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23N_T3U_N9_70 +# set_property PACKAGE_PIN K14 [get_ports "FMCP_HSPC_HA21_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA21_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_70 +# set_property PACKAGE_PIN L11 [get_ports "FMCP_HSPC_HA14_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA14_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22N_T3U_N7_DBC_AD0N_70 +# set_property PACKAGE_PIN M11 [get_ports "FMCP_HSPC_HA14_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA14_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L22P_T3U_N6_DBC_AD0P_70 +# set_property PACKAGE_PIN J11 [get_ports "FMCP_HSPC_HA23_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA23_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21N_T3L_N5_AD8N_70 +# set_property PACKAGE_PIN K11 [get_ports "FMCP_HSPC_HA23_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA23_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L21P_T3L_N4_AD8P_70 +# set_property PACKAGE_PIN L13 [get_ports "FMCP_HSPC_HA19_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA19_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_70 +# set_property PACKAGE_PIN L14 [get_ports "FMCP_HSPC_HA19_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA19_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_70 +# set_property PACKAGE_PIN M12 [get_ports "FMCP_HSPC_HA15_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA15_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_70 +# set_property PACKAGE_PIN M13 [get_ports "FMCP_HSPC_HA15_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA15_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_70 +# set_property PACKAGE_PIN J14 [get_ports "30N3618"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_70 +# set_property IOSTANDARD LVCMOSxx [get_ports "30N3618"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T3U_N12_70 +# set_property PACKAGE_PIN N12 [get_ports "30N3617"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_70 +# set_property IOSTANDARD LVCMOSxx [get_ports "30N3617"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T2U_N12_70 +# set_property PACKAGE_PIN P12 [get_ports "FMCP_HSPC_HA11_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA11_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18N_T2U_N11_AD2N_70 +# set_property PACKAGE_PIN R12 [get_ports "FMCP_HSPC_HA11_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA11_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L18P_T2U_N10_AD2P_70 +# set_property PACKAGE_PIN L15 [get_ports "FMCP_HSPC_HA20_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA20_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17N_T2U_N9_AD10N_70 +# set_property PACKAGE_PIN M15 [get_ports "FMCP_HSPC_HA20_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA20_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L17P_T2U_N8_AD10P_70 +# set_property PACKAGE_PIN P11 [get_ports "FMCP_HSPC_HA17_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA17_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_70 +# set_property PACKAGE_PIN R11 [get_ports "FMCP_HSPC_HA17_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA17_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_70 +# set_property PACKAGE_PIN N15 [get_ports "FMCP_HSPC_HA18_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA18_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15N_T2L_N5_AD11N_70 +# set_property PACKAGE_PIN P15 [get_ports "FMCP_HSPC_HA18_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA18_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L15P_T2L_N4_AD11P_70 +# set_property PACKAGE_PIN P14 [get_ports "FMCP_HSPC_HA05_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA05_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14N_T2L_N3_GC_70 +# set_property PACKAGE_PIN R14 [get_ports "FMCP_HSPC_HA05_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA05_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L14P_T2L_N2_GC_70 +# set_property PACKAGE_PIN N13 [get_ports "FMCP_HSPC_HA00_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA00_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13N_T2L_N1_GC_QBC_70 +# set_property PACKAGE_PIN N14 [get_ports "FMCP_HSPC_HA00_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA00_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L13P_T2L_N0_GC_QBC_70 +# set_property PACKAGE_PIN T13 [get_ports "FMCP_HSPC_HA06_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA06_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12N_T1U_N11_GC_70 +# set_property PACKAGE_PIN U13 [get_ports "FMCP_HSPC_HA06_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA06_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L12P_T1U_N10_GC_70 +# set_property PACKAGE_PIN R13 [get_ports "FMCP_HSPC_HA16_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA16_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11N_T1U_N9_GC_70 +# set_property PACKAGE_PIN T14 [get_ports "FMCP_HSPC_HA16_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA16_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L11P_T1U_N8_GC_70 +# set_property PACKAGE_PIN T11 [get_ports "FMCP_HSPC_HA08_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA08_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10N_T1U_N7_QBC_AD4N_70 +# set_property PACKAGE_PIN U11 [get_ports "FMCP_HSPC_HA08_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA08_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L10P_T1U_N6_QBC_AD4P_70 +# set_property PACKAGE_PIN T15 [get_ports "FMCP_HSPC_HA12_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA12_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9N_T1L_N5_AD12N_70 +# set_property PACKAGE_PIN T16 [get_ports "FMCP_HSPC_HA12_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA12_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L9P_T1L_N4_AD12P_70 +# set_property PACKAGE_PIN U16 [get_ports "FMCP_HSPC_HA10_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA10_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8N_T1L_N3_AD5N_70 +# set_property PACKAGE_PIN V16 [get_ports "FMCP_HSPC_HA10_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA10_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L8P_T1L_N2_AD5P_70 +# set_property PACKAGE_PIN U15 [get_ports "FMCP_HSPC_HA01_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA01_CC_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7N_T1L_N1_QBC_AD13N_70 +# set_property PACKAGE_PIN V15 [get_ports "FMCP_HSPC_HA01_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA01_CC_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L7P_T1L_N0_QBC_AD13P_70 +# set_property PACKAGE_PIN R16 [get_ports "30N3619"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_70 +# set_property IOSTANDARD LVCMOSxx [get_ports "30N3619"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T1U_N12_70 +# #set_property PACKAGE_PIN W15 [get_ports "VRP_70"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_70 +# #set_property IOSTANDARD LVCMOSxx [get_ports "VRP_70"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_T0U_N12_VRP_70 +# set_property PACKAGE_PIN V14 [get_ports "FMCP_HSPC_HA09_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA09_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6N_T0U_N11_AD6N_70 +# set_property PACKAGE_PIN W14 [get_ports "FMCP_HSPC_HA09_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA09_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L6P_T0U_N10_AD6P_70 +# set_property PACKAGE_PIN Y12 [get_ports "FMCP_HSPC_HA02_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA02_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5N_T0U_N9_AD14N_70 +# set_property PACKAGE_PIN AA12 [get_ports "FMCP_HSPC_HA02_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA02_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L5P_T0U_N8_AD14P_70 +# set_property PACKAGE_PIN U12 [get_ports "FMCP_HSPC_HA13_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA13_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4N_T0U_N7_DBC_AD7N_70 +# set_property PACKAGE_PIN V13 [get_ports "FMCP_HSPC_HA13_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA13_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L4P_T0U_N6_DBC_AD7P_70 +# set_property PACKAGE_PIN V12 [get_ports "FMCP_HSPC_HA03_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA03_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_70 +# set_property PACKAGE_PIN W12 [get_ports "FMCP_HSPC_HA03_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA03_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_70 +# set_property PACKAGE_PIN Y14 [get_ports "FMCP_HSPC_HA07_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA07_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_70 +# set_property PACKAGE_PIN AA14 [get_ports "FMCP_HSPC_HA07_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA07_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_70 +# set_property PACKAGE_PIN Y13 [get_ports "FMCP_HSPC_HA04_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA04_N"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_70 +# set_property PACKAGE_PIN AA13 [get_ports "FMCP_HSPC_HA04_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_70 +# set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_HA04_P"] ;# Bank 70 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_70 +# #Other net PACKAGE_PIN AB13 - VREF_70 Bank 70 - VREF_70 +# set_property PACKAGE_PIN AV43 [get_ports "FMCP_HSPC_DP23_C2M_N"] ;# Bank 120 - MGTYTXN3_120 +# set_property PACKAGE_PIN AV42 [get_ports "FMCP_HSPC_DP23_C2M_P"] ;# Bank 120 - MGTYTXP3_120 +# set_property PACKAGE_PIN AU45 [get_ports "FMCP_HSPC_DP23_M2C_P"] ;# Bank 120 - MGTYRXP3_120 +# set_property PACKAGE_PIN AU46 [get_ports "FMCP_HSPC_DP23_M2C_N"] ;# Bank 120 - MGTYRXN3_120 +# set_property PACKAGE_PIN AM39 [get_ports "FMCP_HSPC_GBT1_5_N"] ;# Bank 120 - MGTREFCLK1N_120 +# set_property PACKAGE_PIN AM38 [get_ports "FMCP_HSPC_GBT1_5_P"] ;# Bank 120 - MGTREFCLK1P_120 +# set_property PACKAGE_PIN AY43 [get_ports "FMCP_HSPC_DP22_C2M_N"] ;# Bank 120 - MGTYTXN2_120 +# set_property PACKAGE_PIN AY42 [get_ports "FMCP_HSPC_DP22_C2M_P"] ;# Bank 120 - MGTYTXP2_120 +# set_property PACKAGE_PIN AW45 [get_ports "FMCP_HSPC_DP22_M2C_P"] ;# Bank 120 - MGTYRXP2_120 +# set_property PACKAGE_PIN AW46 [get_ports "FMCP_HSPC_DP22_M2C_N"] ;# Bank 120 - MGTYRXN2_120 +# set_property PACKAGE_PIN BB43 [get_ports "FMCP_HSPC_DP21_C2M_N"] ;# Bank 120 - MGTYTXN1_120 +# set_property PACKAGE_PIN BB42 [get_ports "FMCP_HSPC_DP21_C2M_P"] ;# Bank 120 - MGTYTXP1_120 +# set_property PACKAGE_PIN BA45 [get_ports "FMCP_HSPC_DP21_M2C_P"] ;# Bank 120 - MGTYRXP1_120 +# set_property PACKAGE_PIN BA46 [get_ports "FMCP_HSPC_DP21_M2C_N"] ;# Bank 120 - MGTYRXN1_120 +# set_property PACKAGE_PIN AN41 [get_ports "FMCP_HSPC_GBTCLK5_M2C_C_N"] ;# Bank 120 - MGTREFCLK0N_120 +# set_property PACKAGE_PIN AN40 [get_ports "FMCP_HSPC_GBTCLK5_M2C_C_P"] ;# Bank 120 - MGTREFCLK0P_120 +# set_property PACKAGE_PIN BD43 [get_ports "FMCP_HSPC_DP20_C2M_N"] ;# Bank 120 - MGTYTXN0_120 +# set_property PACKAGE_PIN BD42 [get_ports "FMCP_HSPC_DP20_C2M_P"] ;# Bank 120 - MGTYTXP0_120 +# set_property PACKAGE_PIN BC45 [get_ports "FMCP_HSPC_DP20_M2C_P"] ;# Bank 120 - MGTYRXP0_120 +# set_property PACKAGE_PIN BC46 [get_ports "FMCP_HSPC_DP20_M2C_N"] ;# Bank 120 - MGTYRXN0_120 +# set_property PACKAGE_PIN AL41 [get_ports "FMCP_HSPC_DP3_C2M_N"] ;# Bank 121 - MGTYTXN3_121 +# set_property PACKAGE_PIN AL40 [get_ports "FMCP_HSPC_DP3_C2M_P"] ;# Bank 121 - MGTYTXP3_121 +# set_property PACKAGE_PIN AJ45 [get_ports "FMCP_HSPC_DP3_M2C_P"] ;# Bank 121 - MGTYRXP3_121 +# set_property PACKAGE_PIN AJ46 [get_ports "FMCP_HSPC_DP3_M2C_N"] ;# Bank 121 - MGTYRXN3_121 +# set_property PACKAGE_PIN AH39 [get_ports "FMCP_HSPC_GBT1_0_N"] ;# Bank 121 - MGTREFCLK1N_121 +# set_property PACKAGE_PIN AH38 [get_ports "FMCP_HSPC_GBT1_0_P"] ;# Bank 121 - MGTREFCLK1P_121 +# set_property PACKAGE_PIN AM43 [get_ports "FMCP_HSPC_DP2_C2M_N"] ;# Bank 121 - MGTYTXN2_121 +# set_property PACKAGE_PIN AM42 [get_ports "FMCP_HSPC_DP2_C2M_P"] ;# Bank 121 - MGTYTXP2_121 +# set_property PACKAGE_PIN AL45 [get_ports "FMCP_HSPC_DP2_M2C_P"] ;# Bank 121 - MGTYRXP2_121 +# set_property PACKAGE_PIN AL46 [get_ports "FMCP_HSPC_DP2_M2C_N"] ;# Bank 121 - MGTYRXN2_121 +# #Other net PACKAGE_PIN BF42 - MGTAVTT_FPGA Bank 121 - MGTAVTTRCAL_LS +# set_property PACKAGE_PIN BF43 [get_ports "MGTRREF_121"] ;# Bank 121 - MGTRREF_LS +# set_property PACKAGE_PIN AP43 [get_ports "FMCP_HSPC_DP1_C2M_N"] ;# Bank 121 - MGTYTXN1_121 +# set_property PACKAGE_PIN AP42 [get_ports "FMCP_HSPC_DP1_C2M_P"] ;# Bank 121 - MGTYTXP1_121 +# set_property PACKAGE_PIN AN45 [get_ports "FMCP_HSPC_DP1_M2C_P"] ;# Bank 121 - MGTYRXP1_121 +# set_property PACKAGE_PIN AN46 [get_ports "FMCP_HSPC_DP1_M2C_N"] ;# Bank 121 - MGTYRXN1_121 +# set_property PACKAGE_PIN AK39 [get_ports "FMCP_HSPC_GBT0_0_N"] ;# Bank 121 - MGTREFCLK0N_121 +# set_property PACKAGE_PIN AK38 [get_ports "FMCP_HSPC_GBT0_0_P"] ;# Bank 121 - MGTREFCLK0P_121 +# set_property PACKAGE_PIN AT43 [get_ports "FMCP_HSPC_DP0_C2M_N"] ;# Bank 121 - MGTYTXN0_121 +# set_property PACKAGE_PIN AT42 [get_ports "FMCP_HSPC_DP0_C2M_P"] ;# Bank 121 - MGTYTXP0_121 +# set_property PACKAGE_PIN AR45 [get_ports "FMCP_HSPC_DP0_M2C_P"] ;# Bank 121 - MGTYRXP0_121 +# set_property PACKAGE_PIN AR46 [get_ports "FMCP_HSPC_DP0_M2C_N"] ;# Bank 121 - MGTYRXN0_121 +# set_property PACKAGE_PIN AE41 [get_ports "FMCP_HSPC_DP11_C2M_N"] ;# Bank 122 - MGTYTXN3_122 +# set_property PACKAGE_PIN AE40 [get_ports "FMCP_HSPC_DP11_C2M_P"] ;# Bank 122 - MGTYTXP3_122 +# set_property PACKAGE_PIN AD43 [get_ports "FMCP_HSPC_DP11_M2C_P"] ;# Bank 122 - MGTYRXP3_122 +# set_property PACKAGE_PIN AD44 [get_ports "FMCP_HSPC_DP11_M2C_N"] ;# Bank 122 - MGTYRXN3_122 +# set_property PACKAGE_PIN AD39 [get_ports "FMCP_HSPC_GBT1_2_N"] ;# Bank 122 - MGTREFCLK1N_122 +# set_property PACKAGE_PIN AD38 [get_ports "FMCP_HSPC_GBT1_2_P"] ;# Bank 122 - MGTREFCLK1P_122 +# set_property PACKAGE_PIN AG41 [get_ports "FMCP_HSPC_DP10_C2M_N"] ;# Bank 122 - MGTYTXN2_122 +# set_property PACKAGE_PIN AG40 [get_ports "FMCP_HSPC_DP10_C2M_P"] ;# Bank 122 - MGTYTXP2_122 +# set_property PACKAGE_PIN AE45 [get_ports "FMCP_HSPC_DP10_M2C_P"] ;# Bank 122 - MGTYRXP2_122 +# set_property PACKAGE_PIN AE46 [get_ports "FMCP_HSPC_DP10_M2C_N"] ;# Bank 122 - MGTYRXN2_122 +# set_property PACKAGE_PIN AJ41 [get_ports "FMCP_HSPC_DP9_C2M_N"] ;# Bank 122 - MGTYTXN1_122 +# set_property PACKAGE_PIN AJ40 [get_ports "FMCP_HSPC_DP9_C2M_P"] ;# Bank 122 - MGTYTXP1_122 +# set_property PACKAGE_PIN AF43 [get_ports "FMCP_HSPC_DP9_M2C_P"] ;# Bank 122 - MGTYRXP1_122 +# set_property PACKAGE_PIN AF44 [get_ports "FMCP_HSPC_DP9_M2C_N"] ;# Bank 122 - MGTYRXN1_122 +# set_property PACKAGE_PIN AF39 [get_ports "FMCP_HSPC_GBTCLK2_M2C_C_N"] ;# Bank 122 - MGTREFCLK0N_122 +# set_property PACKAGE_PIN AF38 [get_ports "FMCP_HSPC_GBTCLK2_M2C_C_P"] ;# Bank 122 - MGTREFCLK0P_122 +# set_property PACKAGE_PIN AK43 [get_ports "FMCP_HSPC_DP8_C2M_N"] ;# Bank 122 - MGTYTXN0_122 +# set_property PACKAGE_PIN AK42 [get_ports "FMCP_HSPC_DP8_C2M_P"] ;# Bank 122 - MGTYTXP0_122 +# set_property PACKAGE_PIN AG45 [get_ports "FMCP_HSPC_DP8_M2C_P"] ;# Bank 122 - MGTYRXP0_122 +# set_property PACKAGE_PIN AG46 [get_ports "FMCP_HSPC_DP8_M2C_N"] ;# Bank 122 - MGTYRXN0_122 +# set_property PACKAGE_PIN U41 [get_ports "FMCP_HSPC_DP15_C2M_N"] ;# Bank 125 - MGTYTXN3_125 +# set_property PACKAGE_PIN U40 [get_ports "FMCP_HSPC_DP15_C2M_P"] ;# Bank 125 - MGTYTXP3_125 +# set_property PACKAGE_PIN Y43 [get_ports "FMCP_HSPC_DP15_M2C_P"] ;# Bank 125 - MGTYRXP3_125 +# set_property PACKAGE_PIN Y44 [get_ports "FMCP_HSPC_DP15_M2C_N"] ;# Bank 125 - MGTYRXN3_125 +# set_property PACKAGE_PIN Y39 [get_ports "FMCP_HSPC_GBT1_3_N"] ;# Bank 125 - MGTREFCLK1N_125 +# set_property PACKAGE_PIN Y38 [get_ports "FMCP_HSPC_GBT1_3_P"] ;# Bank 125 - MGTREFCLK1P_125 +# set_property PACKAGE_PIN W41 [get_ports "FMCP_HSPC_DP14_C2M_N"] ;# Bank 125 - MGTYTXN2_125 +# set_property PACKAGE_PIN W40 [get_ports "FMCP_HSPC_DP14_C2M_P"] ;# Bank 125 - MGTYTXP2_125 +# set_property PACKAGE_PIN AA45 [get_ports "FMCP_HSPC_DP14_M2C_P"] ;# Bank 125 - MGTYRXP2_125 +# set_property PACKAGE_PIN AA46 [get_ports "FMCP_HSPC_DP14_M2C_N"] ;# Bank 125 - MGTYRXN2_125 +# set_property PACKAGE_PIN AA41 [get_ports "FMCP_HSPC_DP13_C2M_N"] ;# Bank 125 - MGTYTXN1_125 +# set_property PACKAGE_PIN AA40 [get_ports "FMCP_HSPC_DP13_C2M_P"] ;# Bank 125 - MGTYTXP1_125 +# set_property PACKAGE_PIN AB43 [get_ports "FMCP_HSPC_DP13_M2C_P"] ;# Bank 125 - MGTYRXP1_125 +# set_property PACKAGE_PIN AB44 [get_ports "FMCP_HSPC_DP13_M2C_N"] ;# Bank 125 - MGTYRXN1_125 +# set_property PACKAGE_PIN AB39 [get_ports "FMCP_HSPC_GBTCLK3_M2C_C_N"] ;# Bank 125 - MGTREFCLK0N_125 +# set_property PACKAGE_PIN AB38 [get_ports "FMCP_HSPC_GBTCLK3_M2C_C_P"] ;# Bank 125 - MGTREFCLK0P_125 +# set_property PACKAGE_PIN AC41 [get_ports "FMCP_HSPC_DP12_C2M_N"] ;# Bank 125 - MGTYTXN0_125 +# set_property PACKAGE_PIN AC40 [get_ports "FMCP_HSPC_DP12_C2M_P"] ;# Bank 125 - MGTYTXP0_125 +# set_property PACKAGE_PIN AC45 [get_ports "FMCP_HSPC_DP12_M2C_P"] ;# Bank 125 - MGTYRXP0_125 +# set_property PACKAGE_PIN AC46 [get_ports "FMCP_HSPC_DP12_M2C_N"] ;# Bank 125 - MGTYRXN0_125 +# set_property PACKAGE_PIN K43 [get_ports "FMCP_HSPC_DP7_C2M_N"] ;# Bank 126 - MGTYTXN3_126 +# set_property PACKAGE_PIN K42 [get_ports "FMCP_HSPC_DP7_C2M_P"] ;# Bank 126 - MGTYTXP3_126 +# set_property PACKAGE_PIN N45 [get_ports "FMCP_HSPC_DP7_M2C_P"] ;# Bank 126 - MGTYRXP3_126 +# set_property PACKAGE_PIN N46 [get_ports "FMCP_HSPC_DP7_M2C_N"] ;# Bank 126 - MGTYRXN3_126 +# set_property PACKAGE_PIN T39 [get_ports "FMCP_HSPC_GBT1_1_N"] ;# Bank 126 - MGTREFCLK1N_126 +# set_property PACKAGE_PIN T38 [get_ports "FMCP_HSPC_GBT1_1_P"] ;# Bank 126 - MGTREFCLK1P_126 +# set_property PACKAGE_PIN M43 [get_ports "FMCP_HSPC_DP6_C2M_N"] ;# Bank 126 - MGTYTXN2_126 +# set_property PACKAGE_PIN M42 [get_ports "FMCP_HSPC_DP6_C2M_P"] ;# Bank 126 - MGTYTXP2_126 +# set_property PACKAGE_PIN R45 [get_ports "FMCP_HSPC_DP6_M2C_P"] ;# Bank 126 - MGTYRXP2_126 +# set_property PACKAGE_PIN R46 [get_ports "FMCP_HSPC_DP6_M2C_N"] ;# Bank 126 - MGTYRXN2_126 +# #Other net PACKAGE_PIN L40 - MGTAVTT_FPGA Bank 126 - MGTAVTTRCAL_LN +# set_property PACKAGE_PIN L41 [get_ports "MGTRREF_126"] ;# Bank 126 - MGTRREF_LN +# set_property PACKAGE_PIN P43 [get_ports "FMCP_HSPC_DP5_C2M_N"] ;# Bank 126 - MGTYTXN1_126 +# set_property PACKAGE_PIN P42 [get_ports "FMCP_HSPC_DP5_C2M_P"] ;# Bank 126 - MGTYTXP1_126 +# set_property PACKAGE_PIN U45 [get_ports "FMCP_HSPC_DP5_M2C_P"] ;# Bank 126 - MGTYRXP1_126 +# set_property PACKAGE_PIN U46 [get_ports "FMCP_HSPC_DP5_M2C_N"] ;# Bank 126 - MGTYRXN1_126 +# set_property PACKAGE_PIN V39 [get_ports "FMCP_HSPC_GBT0_1_N"] ;# Bank 126 - MGTREFCLK0N_126 +# set_property PACKAGE_PIN V38 [get_ports "FMCP_HSPC_GBT0_1_P"] ;# Bank 126 - MGTREFCLK0P_126 +# set_property PACKAGE_PIN T43 [get_ports "FMCP_HSPC_DP4_C2M_N"] ;# Bank 126 - MGTYTXN0_126 +# set_property PACKAGE_PIN T42 [get_ports "FMCP_HSPC_DP4_C2M_P"] ;# Bank 126 - MGTYTXP0_126 +# set_property PACKAGE_PIN W45 [get_ports "FMCP_HSPC_DP4_M2C_P"] ;# Bank 126 - MGTYRXP0_126 +# set_property PACKAGE_PIN W46 [get_ports "FMCP_HSPC_DP4_M2C_N"] ;# Bank 126 - MGTYRXN0_126 +# set_property PACKAGE_PIN B43 [get_ports "FMCP_HSPC_DP19_C2M_N"] ;# Bank 127 - MGTYTXN3_127 +# set_property PACKAGE_PIN B42 [get_ports "FMCP_HSPC_DP19_C2M_P"] ;# Bank 127 - MGTYTXP3_127 +# set_property PACKAGE_PIN E45 [get_ports "FMCP_HSPC_DP19_M2C_P"] ;# Bank 127 - MGTYRXP3_127 +# set_property PACKAGE_PIN E46 [get_ports "FMCP_HSPC_DP19_M2C_N"] ;# Bank 127 - MGTYRXN3_127 +# set_property PACKAGE_PIN N41 [get_ports "FMCP_HSPC_GBT1_4_N"] ;# Bank 127 - MGTREFCLK1N_127 +# set_property PACKAGE_PIN N40 [get_ports "FMCP_HSPC_GBT1_4_P"] ;# Bank 127 - MGTREFCLK1P_127 +# set_property PACKAGE_PIN D43 [get_ports "FMCP_HSPC_DP18_C2M_N"] ;# Bank 127 - MGTYTXN2_127 +# set_property PACKAGE_PIN D42 [get_ports "FMCP_HSPC_DP18_C2M_P"] ;# Bank 127 - MGTYTXP2_127 +# set_property PACKAGE_PIN G45 [get_ports "FMCP_HSPC_DP18_M2C_P"] ;# Bank 127 - MGTYRXP2_127 +# set_property PACKAGE_PIN G46 [get_ports "FMCP_HSPC_DP18_M2C_N"] ;# Bank 127 - MGTYRXN2_127 +# set_property PACKAGE_PIN F43 [get_ports "FMCP_HSPC_DP17_C2M_N"] ;# Bank 127 - MGTYTXN1_127 +# set_property PACKAGE_PIN F42 [get_ports "FMCP_HSPC_DP17_C2M_P"] ;# Bank 127 - MGTYTXP1_127 +# set_property PACKAGE_PIN J45 [get_ports "FMCP_HSPC_DP17_M2C_P"] ;# Bank 127 - MGTYRXP1_127 +# set_property PACKAGE_PIN J46 [get_ports "FMCP_HSPC_DP17_M2C_N"] ;# Bank 127 - MGTYRXN1_127 +# set_property PACKAGE_PIN R41 [get_ports "FMCP_HSPC_GBTCLK4_M2C_C_N"] ;# Bank 127 - MGTREFCLK0N_127 +# set_property PACKAGE_PIN R40 [get_ports "FMCP_HSPC_GBTCLK4_M2C_C_P"] ;# Bank 127 - MGTREFCLK0P_127 +# set_property PACKAGE_PIN H43 [get_ports "FMCP_HSPC_DP16_C2M_N"] ;# Bank 127 - MGTYTXN0_127 +# set_property PACKAGE_PIN H42 [get_ports "FMCP_HSPC_DP16_C2M_P"] ;# Bank 127 - MGTYTXP0_127 +# set_property PACKAGE_PIN L45 [get_ports "FMCP_HSPC_DP16_M2C_P"] ;# Bank 127 - MGTYRXP0_127 +# set_property PACKAGE_PIN L46 [get_ports "FMCP_HSPC_DP16_M2C_N"] ;# Bank 127 - MGTYRXN0_127 +# set_property PACKAGE_PIN AW5 [get_ports "PCIE_TX12_P"] ;# Bank 224 - MGTYTXP3_224 +# set_property PACKAGE_PIN AT2 [get_ports "PCIE_RX12_P"] ;# Bank 224 - MGTYRXP3_224 +# set_property PACKAGE_PIN AT1 [get_ports "PCIE_RX12_N"] ;# Bank 224 - MGTYRXN3_224 +# set_property PACKAGE_PIN AW4 [get_ports "PCIE_TX12_N"] ;# Bank 224 - MGTYTXN3_224 +# set_property PACKAGE_PIN AN9 [get_ports "11N8666"] ;# Bank 224 - MGTREFCLK1P_224 +# set_property PACKAGE_PIN AN8 [get_ports "11N8667"] ;# Bank 224 - MGTREFCLK1N_224 +# set_property PACKAGE_PIN BA5 [get_ports "PCIE_TX13_P"] ;# Bank 224 - MGTYTXP2_224 +# set_property PACKAGE_PIN AV2 [get_ports "PCIE_RX13_P"] ;# Bank 224 - MGTYRXP2_224 +# set_property PACKAGE_PIN AV1 [get_ports "PCIE_RX13_N"] ;# Bank 224 - MGTYRXN2_224 +# set_property PACKAGE_PIN BA4 [get_ports "PCIE_TX13_N"] ;# Bank 224 - MGTYTXN2_224 +# set_property PACKAGE_PIN BC5 [get_ports "PCIE_TX14_P"] ;# Bank 224 - MGTYTXP1_224 +# set_property PACKAGE_PIN AY2 [get_ports "PCIE_RX14_P"] ;# Bank 224 - MGTYRXP1_224 +# set_property PACKAGE_PIN AY1 [get_ports "PCIE_RX14_N"] ;# Bank 224 - MGTYRXN1_224 +# set_property PACKAGE_PIN BC4 [get_ports "PCIE_TX14_N"] ;# Bank 224 - MGTYTXN1_224 +# set_property PACKAGE_PIN AR9 [get_ports "11N9044"] ;# Bank 224 - MGTREFCLK0P_224 +# set_property PACKAGE_PIN AR8 [get_ports "11N9045"] ;# Bank 224 - MGTREFCLK0N_224 +# set_property PACKAGE_PIN BE5 [get_ports "PCIE_TX15_P"] ;# Bank 224 - MGTYTXP0_224 +# set_property PACKAGE_PIN BB2 [get_ports "PCIE_RX15_P"] ;# Bank 224 - MGTYRXP0_224 +# set_property PACKAGE_PIN BB1 [get_ports "PCIE_RX15_N"] ;# Bank 224 - MGTYRXN0_224 +# set_property PACKAGE_PIN BE4 [get_ports "PCIE_TX15_N"] ;# Bank 224 - MGTYTXN0_224 +# set_property PACKAGE_PIN AP7 [get_ports "PCIE_TX8_P"] ;# Bank 225 - MGTYTXP3_225 +# set_property PACKAGE_PIN AJ4 [get_ports "PCIE_RX8_P"] ;# Bank 225 - MGTYRXP3_225 +# set_property PACKAGE_PIN AJ3 [get_ports "PCIE_RX8_N"] ;# Bank 225 - MGTYRXN3_225 +# set_property PACKAGE_PIN AP6 [get_ports "PCIE_TX8_N"] ;# Bank 225 - MGTYTXN3_225 +# set_property PACKAGE_PIN AJ9 [get_ports "MGT_SI570_CLOCK1_C_P"] ;# Bank 225 - MGTREFCLK1P_225 +# set_property PACKAGE_PIN AJ8 [get_ports "MGT_SI570_CLOCK1_C_N"] ;# Bank 225 - MGTREFCLK1N_225 +# set_property PACKAGE_PIN AR5 [get_ports "PCIE_TX9_P"] ;# Bank 225 - MGTYTXP2_225 +# set_property PACKAGE_PIN AK2 [get_ports "PCIE_RX9_P"] ;# Bank 225 - MGTYRXP2_225 +# set_property PACKAGE_PIN AK1 [get_ports "PCIE_RX9_N"] ;# Bank 225 - MGTYRXN2_225 +# set_property PACKAGE_PIN AR4 [get_ports "PCIE_TX9_N"] ;# Bank 225 - MGTYTXN2_225 +# set_property PACKAGE_PIN AT7 [get_ports "PCIE_TX10_P"] ;# Bank 225 - MGTYTXP1_225 +# set_property PACKAGE_PIN AM2 [get_ports "PCIE_RX10_P"] ;# Bank 225 - MGTYRXP1_225 +# set_property PACKAGE_PIN AM1 [get_ports "PCIE_RX10_N"] ;# Bank 225 - MGTYRXN1_225 +# set_property PACKAGE_PIN AT6 [get_ports "PCIE_TX10_N"] ;# Bank 225 - MGTYTXN1_225 +# set_property PACKAGE_PIN AL9 [get_ports "PCIE_CLK1_P"] ;# Bank 225 - MGTREFCLK0P_225 +# set_property PACKAGE_PIN AL8 [get_ports "PCIE_CLK1_N"] ;# Bank 225 - MGTREFCLK0N_225 +# set_property PACKAGE_PIN AU5 [get_ports "PCIE_TX11_P"] ;# Bank 225 - MGTYTXP0_225 +# set_property PACKAGE_PIN AP2 [get_ports "PCIE_RX11_P"] ;# Bank 225 - MGTYRXP0_225 +# set_property PACKAGE_PIN AP1 [get_ports "PCIE_RX11_N"] ;# Bank 225 - MGTYRXN0_225 +# set_property PACKAGE_PIN AU4 [get_ports "PCIE_TX11_N"] ;# Bank 225 - MGTYTXN0_225 +# set_property PACKAGE_PIN AH7 [get_ports "PCIE_TX4_P"] ;# Bank 226 - MGTYTXP3_226 +# set_property PACKAGE_PIN AE4 [get_ports "PCIE_RX4_P"] ;# Bank 226 - MGTYRXP3_226 +# set_property PACKAGE_PIN AE3 [get_ports "PCIE_RX4_N"] ;# Bank 226 - MGTYRXN3_226 +# set_property PACKAGE_PIN AH6 [get_ports "PCIE_TX4_N"] ;# Bank 226 - MGTYTXN3_226 +# set_property PACKAGE_PIN AE9 [get_ports "11N5839"] ;# Bank 226 - MGTREFCLK1P_226 +# set_property PACKAGE_PIN AE8 [get_ports "11N5838"] ;# Bank 226 - MGTREFCLK1N_226 +# set_property PACKAGE_PIN AK7 [get_ports "PCIE_TX5_P"] ;# Bank 226 - MGTYTXP2_226 +# set_property PACKAGE_PIN AF2 [get_ports "PCIE_RX5_P"] ;# Bank 226 - MGTYRXP2_226 +# set_property PACKAGE_PIN AF1 [get_ports "PCIE_RX5_N"] ;# Bank 226 - MGTYRXN2_226 +# set_property PACKAGE_PIN AK6 [get_ports "PCIE_TX5_N"] ;# Bank 226 - MGTYTXN2_226 +# set_property PACKAGE_PIN BD2 [get_ports "MGTRREF_226"] ;# Bank 226 - MGTRREF_RS +# #Other net PACKAGE_PIN BD3 - MGTAVTT_FPGA Bank 226 - MGTAVTTRCAL_RS +# set_property PACKAGE_PIN AM7 [get_ports "PCIE_TX6_P"] ;# Bank 226 - MGTYTXP1_226 +# set_property PACKAGE_PIN AG4 [get_ports "PCIE_RX6_P"] ;# Bank 226 - MGTYRXP1_226 +# set_property PACKAGE_PIN AG3 [get_ports "PCIE_RX6_N"] ;# Bank 226 - MGTYRXN1_226 +# set_property PACKAGE_PIN AM6 [get_ports "PCIE_TX6_N"] ;# Bank 226 - MGTYTXN1_226 +# set_property PACKAGE_PIN AG9 [get_ports "MGT226_CLK0_P"] ;# Bank 226 - MGTREFCLK0P_226 +# set_property PACKAGE_PIN AG8 [get_ports "MGT226_CLK0_N"] ;# Bank 226 - MGTREFCLK0N_226 +# set_property PACKAGE_PIN AN5 [get_ports "PCIE_TX7_P"] ;# Bank 226 - MGTYTXP0_226 +# set_property PACKAGE_PIN AH2 [get_ports "PCIE_RX7_P"] ;# Bank 226 - MGTYRXP0_226 +# set_property PACKAGE_PIN AH1 [get_ports "PCIE_RX7_N"] ;# Bank 226 - MGTYRXN0_226 +# set_property PACKAGE_PIN AN4 [get_ports "PCIE_TX7_N"] ;# Bank 226 - MGTYTXN0_226 +# set_property PACKAGE_PIN Y7 [get_ports "PCIE_TX0_P"] ;# Bank 227 - MGTYTXP3_227 +# set_property PACKAGE_PIN AA4 [get_ports "PCIE_RX0_P"] ;# Bank 227 - MGTYRXP3_227 +# set_property PACKAGE_PIN AA3 [get_ports "PCIE_RX0_N"] ;# Bank 227 - MGTYRXN3_227 +# set_property PACKAGE_PIN Y6 [get_ports "PCIE_TX0_N"] ;# Bank 227 - MGTYTXN3_227 +# set_property PACKAGE_PIN AA9 [get_ports "11N8774"] ;# Bank 227 - MGTREFCLK1P_227 +# set_property PACKAGE_PIN AA8 [get_ports "11N8775"] ;# Bank 227 - MGTREFCLK1N_227 +# set_property PACKAGE_PIN AB7 [get_ports "PCIE_TX1_P"] ;# Bank 227 - MGTYTXP2_227 +# set_property PACKAGE_PIN AB2 [get_ports "PCIE_RX1_P"] ;# Bank 227 - MGTYRXP2_227 +# set_property PACKAGE_PIN AB1 [get_ports "PCIE_RX1_N"] ;# Bank 227 - MGTYRXN2_227 +# set_property PACKAGE_PIN AB6 [get_ports "PCIE_TX1_N"] ;# Bank 227 - MGTYTXN2_227 +# set_property PACKAGE_PIN AD7 [get_ports "PCIE_TX2_P"] ;# Bank 227 - MGTYTXP1_227 +# set_property PACKAGE_PIN AC4 [get_ports "PCIE_RX2_P"] ;# Bank 227 - MGTYRXP1_227 +# set_property PACKAGE_PIN AC3 [get_ports "PCIE_RX2_N"] ;# Bank 227 - MGTYRXN1_227 +# set_property PACKAGE_PIN AD6 [get_ports "PCIE_TX2_N"] ;# Bank 227 - MGTYTXN1_227 +# set_property PACKAGE_PIN AC9 [get_ports "PCIE_CLK2_P"] ;# Bank 227 - MGTREFCLK0P_227 +# set_property PACKAGE_PIN AC8 [get_ports "PCIE_CLK2_N"] ;# Bank 227 - MGTREFCLK0N_227 +# set_property PACKAGE_PIN AF7 [get_ports "PCIE_TX3_P"] ;# Bank 227 - MGTYTXP0_227 +# set_property PACKAGE_PIN AD2 [get_ports "PCIE_RX3_P"] ;# Bank 227 - MGTYRXP0_227 +# set_property PACKAGE_PIN AD1 [get_ports "PCIE_RX3_N"] ;# Bank 227 - MGTYRXN0_227 +# set_property PACKAGE_PIN AF6 [get_ports "PCIE_TX3_N"] ;# Bank 227 - MGTYTXN0_227 +# set_property PACKAGE_PIN M7 [get_ports "QSFP1_TX4_P"] ;# Bank 231 - MGTYTXP3_231 +# set_property PACKAGE_PIN U4 [get_ports "QSFP1_RX4_P"] ;# Bank 231 - MGTYRXP3_231 +# set_property PACKAGE_PIN U3 [get_ports "QSFP1_RX4_N"] ;# Bank 231 - MGTYRXN3_231 +# set_property PACKAGE_PIN M6 [get_ports "QSFP1_TX4_N"] ;# Bank 231 - MGTYTXN3_231 +# set_property PACKAGE_PIN U9 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 231 - MGTREFCLK1P_231 +# set_property PACKAGE_PIN U8 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 231 - MGTREFCLK1N_231 +# set_property PACKAGE_PIN P7 [get_ports "QSFP1_TX3_P"] ;# Bank 231 - MGTYTXP2_231 +# set_property PACKAGE_PIN V2 [get_ports "QSFP1_RX3_P"] ;# Bank 231 - MGTYRXP2_231 +# set_property PACKAGE_PIN V1 [get_ports "QSFP1_RX3_N"] ;# Bank 231 - MGTYRXN2_231 +# set_property PACKAGE_PIN P6 [get_ports "QSFP1_TX3_N"] ;# Bank 231 - MGTYTXN2_231 +# set_property PACKAGE_PIN A4 [get_ports "MGTRREF_231"] ;# Bank 231 - MGTRREF_RN +# #Other net PACKAGE_PIN A5 - MGTAVTT_FPGA Bank 231 - MGTAVTTRCAL_RN +# set_property PACKAGE_PIN T7 [get_ports "QSFP1_TX2_P"] ;# Bank 231 - MGTYTXP1_231 +# set_property PACKAGE_PIN W4 [get_ports "QSFP1_RX2_P"] ;# Bank 231 - MGTYRXP1_231 +# set_property PACKAGE_PIN W3 [get_ports "QSFP1_RX2_N"] ;# Bank 231 - MGTYRXN1_231 +# set_property PACKAGE_PIN T6 [get_ports "QSFP1_TX2_N"] ;# Bank 231 - MGTYTXN1_231 +# set_property PACKAGE_PIN W9 [get_ports "QSFP_SI570_CLOCK_C_P"] ;# Bank 231 - MGTREFCLK0P_231 +# set_property PACKAGE_PIN W8 [get_ports "QSFP_SI570_CLOCK_C_N"] ;# Bank 231 - MGTREFCLK0N_231 +# set_property PACKAGE_PIN V7 [get_ports "QSFP1_TX1_P"] ;# Bank 231 - MGTYTXP0_231 +# set_property PACKAGE_PIN Y2 [get_ports "QSFP1_RX1_P"] ;# Bank 231 - MGTYRXP0_231 +# set_property PACKAGE_PIN Y1 [get_ports "QSFP1_RX1_N"] ;# Bank 231 - MGTYRXN0_231 +# set_property PACKAGE_PIN V6 [get_ports "QSFP1_TX1_N"] ;# Bank 231 - MGTYTXN0_231 +# set_property PACKAGE_PIN H7 [get_ports "QSFP2_TX4_P"] ;# Bank 232 - MGTYTXP3_232 +# set_property PACKAGE_PIN M2 [get_ports "QSFP2_RX4_P"] ;# Bank 232 - MGTYRXP3_232 +# set_property PACKAGE_PIN M1 [get_ports "QSFP2_RX4_N"] ;# Bank 232 - MGTYRXN3_232 +# set_property PACKAGE_PIN H6 [get_ports "QSFP2_TX4_N"] ;# Bank 232 - MGTYTXN3_232 +# set_property PACKAGE_PIN N9 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 232 - MGTREFCLK1P_232 +# set_property PACKAGE_PIN N8 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 232 - MGTREFCLK1N_232 +# set_property PACKAGE_PIN J5 [get_ports "QSFP2_TX3_P"] ;# Bank 232 - MGTYTXP2_232 +# set_property PACKAGE_PIN P2 [get_ports "QSFP2_RX3_P"] ;# Bank 232 - MGTYRXP2_232 +# set_property PACKAGE_PIN P1 [get_ports "QSFP2_RX3_N"] ;# Bank 232 - MGTYRXN2_232 +# set_property PACKAGE_PIN J4 [get_ports "QSFP2_TX3_N"] ;# Bank 232 - MGTYTXN2_232 +# set_property PACKAGE_PIN K7 [get_ports "QSFP2_TX2_P"] ;# Bank 232 - MGTYTXP1_232 +# set_property PACKAGE_PIN R4 [get_ports "QSFP2_RX2_P"] ;# Bank 232 - MGTYRXP1_232 +# set_property PACKAGE_PIN R3 [get_ports "QSFP2_RX2_N"] ;# Bank 232 - MGTYRXN1_232 +# set_property PACKAGE_PIN K6 [get_ports "QSFP2_TX2_N"] ;# Bank 232 - MGTYTXN1_232 +# set_property PACKAGE_PIN R9 [get_ports "MGT_SI570_CLOCK2_C_P"] ;# Bank 232 - MGTREFCLK0P_232 +# set_property PACKAGE_PIN R8 [get_ports "MGT_SI570_CLOCK2_C_N"] ;# Bank 232 - MGTREFCLK0N_232 +# set_property PACKAGE_PIN L5 [get_ports "QSFP2_TX1_P"] ;# Bank 232 - MGTYTXP0_232 +# set_property PACKAGE_PIN T2 [get_ports "QSFP2_RX1_P"] ;# Bank 232 - MGTYRXP0_232 +# set_property PACKAGE_PIN T1 [get_ports "QSFP2_RX1_N"] ;# Bank 232 - MGTYRXN0_232 +# set_property PACKAGE_PIN L4 [get_ports "QSFP2_TX1_N"] ;# Bank 232 - MGTYTXN0_232 +# set_property PACKAGE_PIN C5 [get_ports "FIREFLY_TX4_P"] ;# Bank 233 - MGTYTXP3_233 +# set_property PACKAGE_PIN D2 [get_ports "FIREFLY_RX4_P"] ;# Bank 233 - MGTYRXP3_233 +# set_property PACKAGE_PIN D1 [get_ports "FIREFLY_RX4_N"] ;# Bank 233 - MGTYRXN3_233 +# set_property PACKAGE_PIN C4 [get_ports "FIREFLY_TX4_N"] ;# Bank 233 - MGTYTXN3_233 +# set_property PACKAGE_PIN J9 [get_ports "MGT233_CLK1_P"] ;# Bank 233 - MGTREFCLK1P_233 +# set_property PACKAGE_PIN J8 [get_ports "MGT233_CLK1_N"] ;# Bank 233 - MGTREFCLK1N_233 +# set_property PACKAGE_PIN E5 [get_ports "FIREFLY_TX3_P"] ;# Bank 233 - MGTYTXP2_233 +# set_property PACKAGE_PIN F2 [get_ports "FIREFLY_RX3_P"] ;# Bank 233 - MGTYRXP2_233 +# set_property PACKAGE_PIN F1 [get_ports "FIREFLY_RX3_N"] ;# Bank 233 - MGTYRXN2_233 +# set_property PACKAGE_PIN E4 [get_ports "FIREFLY_TX3_N"] ;# Bank 233 - MGTYTXN2_233 +# set_property PACKAGE_PIN F7 [get_ports "FIREFLY_TX2_P"] ;# Bank 233 - MGTYTXP1_233 +# set_property PACKAGE_PIN H2 [get_ports "FIREFLY_RX2_P"] ;# Bank 233 - MGTYRXP1_233 +# set_property PACKAGE_PIN H1 [get_ports "FIREFLY_RX2_N"] ;# Bank 233 - MGTYRXN1_233 +# set_property PACKAGE_PIN F6 [get_ports "FIREFLY_TX2_N"] ;# Bank 233 - MGTYTXN1_233 +# set_property PACKAGE_PIN L9 [get_ports "MGT_SI570_CLOCK3_C_P"] ;# Bank 233 - MGTREFCLK0P_233 +# set_property PACKAGE_PIN L8 [get_ports "MGT_SI570_CLOCK3_C_N"] ;# Bank 233 - MGTREFCLK0N_233 +# set_property PACKAGE_PIN G5 [get_ports "FIREFLY_TX1_P"] ;# Bank 233 - MGTYTXP0_233 +# set_property PACKAGE_PIN K2 [get_ports "FIREFLY_RX1_P"] ;# Bank 233 - MGTYRXP0_233 +# set_property PACKAGE_PIN K1 [get_ports "FIREFLY_RX1_N"] ;# Bank 233 - MGTYRXN0_233 +# set_property PACKAGE_PIN G4 [get_ports "FIREFLY_TX1_N"] ;# Bank 233 - MGTYTXN0_233 diff --git a/fpga/scripts/program.tcl b/fpga/scripts/program.tcl new file mode 100644 index 0000000000..40321272f2 --- /dev/null +++ b/fpga/scripts/program.tcl @@ -0,0 +1,26 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Author: Florian Zaruba +# Description: Program Genesys II + +open_hw + +connect_hw_server -url localhost:3121 +open_hw_target {localhost:3121/xilinx_tcf/Digilent/200300A8CD43B} + +current_hw_device [get_hw_devices xc7k325t_0] +set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7k325t_0] +program_hw_devices [get_hw_devices xc7k325t_0] +refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0] diff --git a/fpga/scripts/prologue.tcl b/fpga/scripts/prologue.tcl new file mode 100644 index 0000000000..ab456860d0 --- /dev/null +++ b/fpga/scripts/prologue.tcl @@ -0,0 +1,25 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Author: Florian Zaruba + +set project ariane + +create_project $project . -force -part $::env(XILINX_PART) +set_property board_part $::env(XILINX_BOARD) [current_project] + +# set number of threads to 8 (maximum, unfortunately) +set_param general.maxThreads 8 + +set_msg_config -id {[Synth 8-5858]} -new_severity "info" diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl new file mode 100644 index 0000000000..73ce60c9c5 --- /dev/null +++ b/fpga/scripts/run.tcl @@ -0,0 +1,85 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Author: Florian Zaruba + +# hard-coded to Genesys 2 for the moment +add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc + +read_ip xilinx/xlnx_mig_7_ddr3/ip/xlnx_mig_7_ddr3.xci +read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci +read_ip xilinx/xlnx_axi_dwidth_converter/ip/xlnx_axi_dwidth_converter.xci +read_ip xilinx/xlnx_axi_ethernetlite/ip/xlnx_axi_ethernetlite.xci +read_ip xilinx/xlnx_axi_gpio/ip/xlnx_axi_gpio.xci +read_ip xilinx/xlnx_axi_quad_spi/ip/xlnx_axi_quad_spi.xci +read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci + +source scripts/add_sources.tcl + +set_property top ${project}_xilinx [current_fileset] + +if {$::env(BOARD) eq "genesys2"} { + read_verilog -sv {src/genesysii.svh} + set file "src/genesysii.svh" +} else { + exit 1 +} + +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj + +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 + +add_files -fileset constrs_1 -norecurse constraints/$project.xdc + +# synth_design -retiming -rtl -name rtl_1 -verilog_define SYNTHESIS -verilog_define +synth_design -rtl -name rtl_1 + +launch_runs synth_1 +wait_on_run synth_1 +open_run synth_1 + +exec mkdir -p reports/ +exec rm -rf reports/* + +check_timing -verbose -file reports/$project.check_timing.rpt +report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt +report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt +report_utilization -hierarchical -file reports/$project.utilization.rpt +report_cdc -file reports/$project.cdc.rpt +report_clock_interaction -file reports/$project.clock_interaction.rpt + +# set for RuntimeOptimized implementation +set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] +set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] + +launch_runs impl_1 +wait_on_run impl_1 +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 +open_run impl_1 + +# output Verilog netlist + SDC for timing simulation +write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v +write_verilog -force -mode timesim work-fpga/${project}_timesim.v +write_sdf -force work-fpga/${project}_timesim.sdf + +# reports +exec mkdir -p reports/ +exec rm -rf reports/* +check_timing -file reports/${project}.check_timing.rpt +report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt +report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt +report_utilization -hierarchical -file reports/${project}.utilization.rpt diff --git a/fpga/scripts/write_cfgmem.tcl b/fpga/scripts/write_cfgmem.tcl new file mode 100644 index 0000000000..c940e278e6 --- /dev/null +++ b/fpga/scripts/write_cfgmem.tcl @@ -0,0 +1,28 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Author: Florian Zaruba +# Description: Generate a memory configuration file from a bitstream (Genesys II only right now) + +if {$argc < 2 || $argc > 4} { + puts $argc + puts {Error: Invalid number of arguments} + puts {Usage: write_cfgmem.tcl mcsfile bitfile [datafile]} + exit 1 +} + +lassign $argv mcsfile bitfile + +# https://scholar.princeton.edu/jbalkind/blog/programming-genesys-2-qspi-spi-x4-flash +write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force diff --git a/fpga/sourceme.sh b/fpga/sourceme.sh new file mode 100644 index 0000000000..5a6d15683a --- /dev/null +++ b/fpga/sourceme.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +# genesys2 +if [ -z "${BOARD}" ]; then + export BOARD="genesys2" +fi + +if [ "$BOARD" = "genesys2" ]; then + echo -n "Configuring for " + echo "Genesys II" + export XILINX_PART="xc7k325tffg900-2" + export XILINX_BOARD="digilentinc.com:genesys2:part0:1.1" + export CLK_PERIOD_NS="20" +fi diff --git a/fpga/src/apb_node b/fpga/src/apb_node new file mode 160000 index 0000000000..157e5f00a3 --- /dev/null +++ b/fpga/src/apb_node @@ -0,0 +1 @@ +Subproject commit 157e5f00a37440d53f2e5b3aabfc9d454530e688 diff --git a/fpga/src/apb_uart b/fpga/src/apb_uart new file mode 160000 index 0000000000..ac3461ce23 --- /dev/null +++ b/fpga/src/apb_uart @@ -0,0 +1 @@ +Subproject commit ac3461ce23832e02903b9d2d7d4edd7fcb89bd92 diff --git a/fpga/src/ariane_peripherals_xilinx.sv b/fpga/src/ariane_peripherals_xilinx.sv new file mode 100644 index 0000000000..6090ac1fa7 --- /dev/null +++ b/fpga/src/ariane_peripherals_xilinx.sv @@ -0,0 +1,951 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Xilinx Peripehrals +module ariane_peripherals #( + parameter int AxiAddrWidth = -1, + parameter int AxiDataWidth = -1, + parameter int AxiIdWidth = -1, + parameter int AxiUserWidth = 1, + parameter bit InclUART = 1, + parameter bit InclSPI = 0, + parameter bit InclEthernet = 0, + parameter bit InclGPIO = 0 +) ( + input logic clk_i , // Clock + input logic clk_200MHz_i , + input logic rst_ni , // Asynchronous reset active low + AXI_BUS.in plic , + AXI_BUS.in uart , + AXI_BUS.in spi , + AXI_BUS.in gpio , + input logic eth_clk_i , + AXI_BUS.in ethernet , + output logic [1:0] irq_o , + // UART + input logic rx_i , + output logic tx_o , + // Ethernet + input wire eth_rxck , + input wire eth_rxctl , + input wire [3:0] eth_rxd , + output wire eth_txck , + output wire eth_txctl , + output wire [3:0] eth_txd , + output wire eth_rst_n , + input logic phy_tx_clk_i , // 25 MHz Clock + // MDIO Interface + inout wire eth_mdio , + output logic eth_mdc , + // SPI + output logic spi_clk_o , + output logic spi_mosi , + input logic spi_miso , + output logic spi_ss , + output logic [7:0] leds_o , + input logic [7:0] dip_switches_i +); + + // --------------- + // 1. PLIC + // --------------- + logic [ariane_soc::NumSources-1:0] irq_sources; + + REG_BUS #( + .ADDR_WIDTH ( 32 ), + .DATA_WIDTH ( 32 ) + ) reg_bus (clk_i); + + logic plic_penable; + logic plic_pwrite; + logic [31:0] plic_paddr; + logic plic_psel; + logic [31:0] plic_pwdata; + logic [31:0] plic_prdata; + logic plic_pready; + logic plic_pslverr; + + axi2apb_64_32 #( + .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ), + .AXI4_RDATA_WIDTH ( AxiDataWidth ), + .AXI4_WDATA_WIDTH ( AxiDataWidth ), + .AXI4_ID_WIDTH ( AxiIdWidth ), + .AXI4_USER_WIDTH ( AxiUserWidth ), + .BUFF_DEPTH_SLAVE ( 2 ), + .APB_ADDR_WIDTH ( 32 ) + ) i_axi2apb_64_32_plic ( + .ACLK ( clk_i ), + .ARESETn ( rst_ni ), + .test_en_i ( 1'b0 ), + .AWID_i ( plic.aw_id ), + .AWADDR_i ( plic.aw_addr ), + .AWLEN_i ( plic.aw_len ), + .AWSIZE_i ( plic.aw_size ), + .AWBURST_i ( plic.aw_burst ), + .AWLOCK_i ( plic.aw_lock ), + .AWCACHE_i ( plic.aw_cache ), + .AWPROT_i ( plic.aw_prot ), + .AWREGION_i( plic.aw_region ), + .AWUSER_i ( plic.aw_user ), + .AWQOS_i ( plic.aw_qos ), + .AWVALID_i ( plic.aw_valid ), + .AWREADY_o ( plic.aw_ready ), + .WDATA_i ( plic.w_data ), + .WSTRB_i ( plic.w_strb ), + .WLAST_i ( plic.w_last ), + .WUSER_i ( plic.w_user ), + .WVALID_i ( plic.w_valid ), + .WREADY_o ( plic.w_ready ), + .BID_o ( plic.b_id ), + .BRESP_o ( plic.b_resp ), + .BVALID_o ( plic.b_valid ), + .BUSER_o ( plic.b_user ), + .BREADY_i ( plic.b_ready ), + .ARID_i ( plic.ar_id ), + .ARADDR_i ( plic.ar_addr ), + .ARLEN_i ( plic.ar_len ), + .ARSIZE_i ( plic.ar_size ), + .ARBURST_i ( plic.ar_burst ), + .ARLOCK_i ( plic.ar_lock ), + .ARCACHE_i ( plic.ar_cache ), + .ARPROT_i ( plic.ar_prot ), + .ARREGION_i( plic.ar_region ), + .ARUSER_i ( plic.ar_user ), + .ARQOS_i ( plic.ar_qos ), + .ARVALID_i ( plic.ar_valid ), + .ARREADY_o ( plic.ar_ready ), + .RID_o ( plic.r_id ), + .RDATA_o ( plic.r_data ), + .RRESP_o ( plic.r_resp ), + .RLAST_o ( plic.r_last ), + .RUSER_o ( plic.r_user ), + .RVALID_o ( plic.r_valid ), + .RREADY_i ( plic.r_ready ), + .PENABLE ( plic_penable ), + .PWRITE ( plic_pwrite ), + .PADDR ( plic_paddr ), + .PSEL ( plic_psel ), + .PWDATA ( plic_pwdata ), + .PRDATA ( plic_prdata ), + .PREADY ( plic_pready ), + .PSLVERR ( plic_pslverr ) + ); + + apb_to_reg i_apb_to_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .penable_i ( plic_penable ), + .pwrite_i ( plic_pwrite ), + .paddr_i ( plic_paddr ), + .psel_i ( plic_psel ), + .pwdata_i ( plic_pwdata ), + .prdata_o ( plic_prdata ), + .pready_o ( plic_pready ), + .pslverr_o ( plic_pslverr ), + .reg_o ( reg_bus ) + ); + + plic #( + .ID_BITWIDTH ( ariane_soc::PLICIdWidth ), + .PARAMETER_BITWIDTH ( ariane_soc::ParameterBitwidth ), + .NUM_TARGETS ( ariane_soc::NumTargets ), + .NUM_SOURCES ( ariane_soc::NumSources ) + ) i_plic ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .irq_sources_i ( irq_sources ), + .eip_targets_o ( irq_o ), + .external_bus_io ( reg_bus ) + ); + + // --------------- + // 2. UART + // --------------- + logic uart_penable; + logic uart_pwrite; + logic [31:0] uart_paddr; + logic uart_psel; + logic [31:0] uart_pwdata; + logic [31:0] uart_prdata; + logic uart_pready; + logic uart_pslverr; + + axi2apb_64_32 #( + .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ), + .AXI4_RDATA_WIDTH ( AxiDataWidth ), + .AXI4_WDATA_WIDTH ( AxiDataWidth ), + .AXI4_ID_WIDTH ( AxiIdWidth ), + .AXI4_USER_WIDTH ( AxiUserWidth ), + .BUFF_DEPTH_SLAVE ( 2 ), + .APB_ADDR_WIDTH ( 32 ) + ) i_axi2apb_64_32_uart ( + .ACLK ( clk_i ), + .ARESETn ( rst_ni ), + .test_en_i ( 1'b0 ), + .AWID_i ( uart.aw_id ), + .AWADDR_i ( uart.aw_addr ), + .AWLEN_i ( uart.aw_len ), + .AWSIZE_i ( uart.aw_size ), + .AWBURST_i ( uart.aw_burst ), + .AWLOCK_i ( uart.aw_lock ), + .AWCACHE_i ( uart.aw_cache ), + .AWPROT_i ( uart.aw_prot ), + .AWREGION_i( uart.aw_region ), + .AWUSER_i ( uart.aw_user ), + .AWQOS_i ( uart.aw_qos ), + .AWVALID_i ( uart.aw_valid ), + .AWREADY_o ( uart.aw_ready ), + .WDATA_i ( uart.w_data ), + .WSTRB_i ( uart.w_strb ), + .WLAST_i ( uart.w_last ), + .WUSER_i ( uart.w_user ), + .WVALID_i ( uart.w_valid ), + .WREADY_o ( uart.w_ready ), + .BID_o ( uart.b_id ), + .BRESP_o ( uart.b_resp ), + .BVALID_o ( uart.b_valid ), + .BUSER_o ( uart.b_user ), + .BREADY_i ( uart.b_ready ), + .ARID_i ( uart.ar_id ), + .ARADDR_i ( uart.ar_addr ), + .ARLEN_i ( uart.ar_len ), + .ARSIZE_i ( uart.ar_size ), + .ARBURST_i ( uart.ar_burst ), + .ARLOCK_i ( uart.ar_lock ), + .ARCACHE_i ( uart.ar_cache ), + .ARPROT_i ( uart.ar_prot ), + .ARREGION_i( uart.ar_region ), + .ARUSER_i ( uart.ar_user ), + .ARQOS_i ( uart.ar_qos ), + .ARVALID_i ( uart.ar_valid ), + .ARREADY_o ( uart.ar_ready ), + .RID_o ( uart.r_id ), + .RDATA_o ( uart.r_data ), + .RRESP_o ( uart.r_resp ), + .RLAST_o ( uart.r_last ), + .RUSER_o ( uart.r_user ), + .RVALID_o ( uart.r_valid ), + .RREADY_i ( uart.r_ready ), + .PENABLE ( uart_penable ), + .PWRITE ( uart_pwrite ), + .PADDR ( uart_paddr ), + .PSEL ( uart_psel ), + .PWDATA ( uart_pwdata ), + .PRDATA ( uart_prdata ), + .PREADY ( uart_pready ), + .PSLVERR ( uart_pslverr ) + ); + + if (InclUART) begin : gen_uart + apb_uart i_apb_uart ( + .CLK ( clk_i ), + .RSTN ( rst_ni ), + .PSEL ( uart_psel ), + .PENABLE ( uart_penable ), + .PWRITE ( uart_pwrite ), + .PADDR ( uart_paddr[4:2] ), + .PWDATA ( uart_pwdata ), + .PRDATA ( uart_prdata ), + .PREADY ( uart_pready ), + .PSLVERR ( uart_pslverr ), + .INT ( irq_sources[0] ), + .OUT1N ( ), // keep open + .OUT2N ( ), // keep open + .RTSN ( ), // no flow control + .DTRN ( ), // no flow control + .CTSN ( 1'b0 ), + .DSRN ( 1'b0 ), + .DCDN ( 1'b0 ), + .RIN ( 1'b0 ), + .SIN ( rx_i ), + .SOUT ( tx_o ) + ); + end else begin + /* pragma translate_off */ + `ifndef VERILATOR + mock_uart i_mock_uart ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .penable_i ( uart_penable ), + .pwrite_i ( uart_pwrite ), + .paddr_i ( uart_paddr ), + .psel_i ( uart_psel ), + .pwdata_i ( uart_pwdata ), + .prdata_o ( uart_prdata ), + .pready_o ( uart_pready ), + .pslverr_o ( uart_pslverr ) + ); + `endif + /* pragma translate_on */ + end + + // --------------- + // 3. SPI + // --------------- + assign spi.b_user = 1'b0; + assign spi.r_user = 1'b0; + + if (InclSPI) begin : gen_spi + logic [31:0] s_axi_spi_awaddr; + logic [7:0] s_axi_spi_awlen; + logic [2:0] s_axi_spi_awsize; + logic [1:0] s_axi_spi_awburst; + logic [0:0] s_axi_spi_awlock; + logic [3:0] s_axi_spi_awcache; + logic [2:0] s_axi_spi_awprot; + logic [3:0] s_axi_spi_awregion; + logic [3:0] s_axi_spi_awqos; + logic s_axi_spi_awvalid; + logic s_axi_spi_awready; + logic [31:0] s_axi_spi_wdata; + logic [3:0] s_axi_spi_wstrb; + logic s_axi_spi_wlast; + logic s_axi_spi_wvalid; + logic s_axi_spi_wready; + logic [1:0] s_axi_spi_bresp; + logic s_axi_spi_bvalid; + logic s_axi_spi_bready; + logic [31:0] s_axi_spi_araddr; + logic [7:0] s_axi_spi_arlen; + logic [2:0] s_axi_spi_arsize; + logic [1:0] s_axi_spi_arburst; + logic [0:0] s_axi_spi_arlock; + logic [3:0] s_axi_spi_arcache; + logic [2:0] s_axi_spi_arprot; + logic [3:0] s_axi_spi_arregion; + logic [3:0] s_axi_spi_arqos; + logic s_axi_spi_arvalid; + logic s_axi_spi_arready; + logic [31:0] s_axi_spi_rdata; + logic [1:0] s_axi_spi_rresp; + logic s_axi_spi_rlast; + logic s_axi_spi_rvalid; + logic s_axi_spi_rready; + + xlnx_axi_dwidth_converter i_xlnx_axi_dwidth_converter_spi ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + + .s_axi_awid ( spi.aw_id ), + .s_axi_awaddr ( spi.aw_addr[31:0] ), + .s_axi_awlen ( spi.aw_len ), + .s_axi_awsize ( spi.aw_size ), + .s_axi_awburst ( spi.aw_burst ), + .s_axi_awlock ( spi.aw_lock ), + .s_axi_awcache ( spi.aw_cache ), + .s_axi_awprot ( spi.aw_prot ), + .s_axi_awregion ( spi.aw_region ), + .s_axi_awqos ( spi.aw_qos ), + .s_axi_awvalid ( spi.aw_valid ), + .s_axi_awready ( spi.aw_ready ), + .s_axi_wdata ( spi.w_data ), + .s_axi_wstrb ( spi.w_strb ), + .s_axi_wlast ( spi.w_last ), + .s_axi_wvalid ( spi.w_valid ), + .s_axi_wready ( spi.w_ready ), + .s_axi_bid ( spi.b_id ), + .s_axi_bresp ( spi.b_resp ), + .s_axi_bvalid ( spi.b_valid ), + .s_axi_bready ( spi.b_ready ), + .s_axi_arid ( spi.ar_id ), + .s_axi_araddr ( spi.ar_addr[31:0] ), + .s_axi_arlen ( spi.ar_len ), + .s_axi_arsize ( spi.ar_size ), + .s_axi_arburst ( spi.ar_burst ), + .s_axi_arlock ( spi.ar_lock ), + .s_axi_arcache ( spi.ar_cache ), + .s_axi_arprot ( spi.ar_prot ), + .s_axi_arregion ( spi.ar_region ), + .s_axi_arqos ( spi.ar_qos ), + .s_axi_arvalid ( spi.ar_valid ), + .s_axi_arready ( spi.ar_ready ), + .s_axi_rid ( spi.r_id ), + .s_axi_rdata ( spi.r_data ), + .s_axi_rresp ( spi.r_resp ), + .s_axi_rlast ( spi.r_last ), + .s_axi_rvalid ( spi.r_valid ), + .s_axi_rready ( spi.r_ready ), + + .m_axi_awaddr ( s_axi_spi_awaddr ), + .m_axi_awlen ( s_axi_spi_awlen ), + .m_axi_awsize ( s_axi_spi_awsize ), + .m_axi_awburst ( s_axi_spi_awburst ), + .m_axi_awlock ( s_axi_spi_awlock ), + .m_axi_awcache ( s_axi_spi_awcache ), + .m_axi_awprot ( s_axi_spi_awprot ), + .m_axi_awregion ( s_axi_spi_awregion ), + .m_axi_awqos ( s_axi_spi_awqos ), + .m_axi_awvalid ( s_axi_spi_awvalid ), + .m_axi_awready ( s_axi_spi_awready ), + .m_axi_wdata ( s_axi_spi_wdata ), + .m_axi_wstrb ( s_axi_spi_wstrb ), + .m_axi_wlast ( s_axi_spi_wlast ), + .m_axi_wvalid ( s_axi_spi_wvalid ), + .m_axi_wready ( s_axi_spi_wready ), + .m_axi_bresp ( s_axi_spi_bresp ), + .m_axi_bvalid ( s_axi_spi_bvalid ), + .m_axi_bready ( s_axi_spi_bready ), + .m_axi_araddr ( s_axi_spi_araddr ), + .m_axi_arlen ( s_axi_spi_arlen ), + .m_axi_arsize ( s_axi_spi_arsize ), + .m_axi_arburst ( s_axi_spi_arburst ), + .m_axi_arlock ( s_axi_spi_arlock ), + .m_axi_arcache ( s_axi_spi_arcache ), + .m_axi_arprot ( s_axi_spi_arprot ), + .m_axi_arregion ( s_axi_spi_arregion ), + .m_axi_arqos ( s_axi_spi_arqos ), + .m_axi_arvalid ( s_axi_spi_arvalid ), + .m_axi_arready ( s_axi_spi_arready ), + .m_axi_rdata ( s_axi_spi_rdata ), + .m_axi_rresp ( s_axi_spi_rresp ), + .m_axi_rlast ( s_axi_spi_rlast ), + .m_axi_rvalid ( s_axi_spi_rvalid ), + .m_axi_rready ( s_axi_spi_rready ) + ); + + xlnx_axi_quad_spi i_xlnx_axi_quad_spi ( + .ext_spi_clk ( clk_i ), + .s_axi4_aclk ( clk_i ), + .s_axi4_aresetn ( rst_ni ), + .s_axi4_awaddr ( s_axi_spi_awaddr[23:0] ), + .s_axi4_awlen ( s_axi_spi_awlen ), + .s_axi4_awsize ( s_axi_spi_awsize ), + .s_axi4_awburst ( s_axi_spi_awburst ), + .s_axi4_awlock ( s_axi_spi_awlock ), + .s_axi4_awcache ( s_axi_spi_awcache ), + .s_axi4_awprot ( s_axi_spi_awprot ), + .s_axi4_awvalid ( s_axi_spi_awvalid ), + .s_axi4_awready ( s_axi_spi_awready ), + .s_axi4_wdata ( s_axi_spi_wdata ), + .s_axi4_wstrb ( s_axi_spi_wstrb ), + .s_axi4_wlast ( s_axi_spi_wlast ), + .s_axi4_wvalid ( s_axi_spi_wvalid ), + .s_axi4_wready ( s_axi_spi_wready ), + .s_axi4_bresp ( s_axi_spi_bresp ), + .s_axi4_bvalid ( s_axi_spi_bvalid ), + .s_axi4_bready ( s_axi_spi_bready ), + .s_axi4_araddr ( s_axi_spi_araddr[23:0] ), + .s_axi4_arlen ( s_axi_spi_arlen ), + .s_axi4_arsize ( s_axi_spi_arsize ), + .s_axi4_arburst ( s_axi_spi_arburst ), + .s_axi4_arlock ( s_axi_spi_arlock ), + .s_axi4_arcache ( s_axi_spi_arcache ), + .s_axi4_arprot ( s_axi_spi_arprot ), + .s_axi4_arvalid ( s_axi_spi_arvalid ), + .s_axi4_arready ( s_axi_spi_arready ), + .s_axi4_rdata ( s_axi_spi_rdata ), + .s_axi4_rresp ( s_axi_spi_rresp ), + .s_axi4_rlast ( s_axi_spi_rlast ), + .s_axi4_rvalid ( s_axi_spi_rvalid ), + .s_axi4_rready ( s_axi_spi_rready ), + .io0_i ( '0 ), + .io0_o ( spi_mosi ), + .io0_t ( ), + .io1_i ( spi_miso ), + .io1_o ( ), + .io1_t ( ), + .ss_i ( '0 ), + .ss_o ( spi_ss ), + .ss_t ( ), + .sck_o ( spi_clk_o ), + .sck_i ( '0 ), + .sck_t ( ), + .ip2intc_irpt ( irq_sources[1] ) + ); + end else begin + assign spi_clk_o = 1'b0; + assign spi_mosi = 1'b0; + assign spi_ss = 1'b0; + + assign irq_sources [1] = 1'b0; + assign spi.aw_ready = 1'b1; + assign spi.ar_ready = 1'b1; + assign spi.w_ready = 1'b1; + + assign spi.b_valid = spi.aw_valid; + assign spi.b_id = spi.aw_id; + assign spi.b_resp = axi_pkg::RESP_SLVERR; + assign spi.b_user = '0; + + assign spi.r_valid = spi.ar_valid; + assign spi.r_resp = axi_pkg::RESP_SLVERR; + assign spi.r_data = 'hdeadbeef; + assign spi.r_last = 1'b1; + end + + + // --------------- + // 4. Ethernet + // --------------- + assign ethernet.b_user = 1'b0; + assign ethernet.r_user = 1'b0; + + if (InclEthernet) begin : gen_ethernet + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) axi_ethernet_cdc(); + + logic s_eth_rst_n; + + logic [31:0] s_axi_eth_awaddr; + logic [7:0] s_axi_eth_awlen; + logic [2:0] s_axi_eth_awsize; + logic [1:0] s_axi_eth_awburst; + logic [3:0] s_axi_eth_awcache; + logic s_axi_eth_awvalid; + logic s_axi_eth_awready; + logic [31:0] s_axi_eth_wdata; + logic [3:0] s_axi_eth_wstrb; + logic s_axi_eth_wlast; + logic s_axi_eth_wvalid; + logic s_axi_eth_wready; + logic [1:0] s_axi_eth_bresp; + logic s_axi_eth_bvalid; + logic s_axi_eth_bready; + logic [31:0] s_axi_eth_araddr; + logic [7:0] s_axi_eth_arlen; + logic [2:0] s_axi_eth_arsize; + logic [1:0] s_axi_eth_arburst; + logic [3:0] s_axi_eth_arcache; + logic s_axi_eth_arvalid; + logic s_axi_eth_arready; + logic [31:0] s_axi_eth_rdata; + logic [1:0] s_axi_eth_rresp; + logic s_axi_eth_rlast; + logic s_axi_eth_rvalid; + + rstgen i_rstgen ( + .clk_i ( eth_clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_en ), + .rst_no ( s_eth_rst_n ), + .init_no ( ) // keep open + ); + + xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ethernet ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + .s_axi_awid ( ethernet.aw_id ), + .s_axi_awaddr ( ethernet.aw_addr ), + .s_axi_awlen ( ethernet.aw_len ), + .s_axi_awsize ( ethernet.aw_size ), + .s_axi_awburst ( ethernet.aw_burst ), + .s_axi_awlock ( ethernet.aw_lock ), + .s_axi_awcache ( ethernet.aw_cache ), + .s_axi_awprot ( ethernet.aw_prot ), + .s_axi_awregion ( ethernet.aw_region ), + .s_axi_awqos ( ethernet.aw_qos ), + .s_axi_awvalid ( ethernet.aw_valid ), + .s_axi_awready ( ethernet.aw_ready ), + .s_axi_wdata ( ethernet.w_data ), + .s_axi_wstrb ( ethernet.w_strb ), + .s_axi_wlast ( ethernet.w_last ), + .s_axi_wvalid ( ethernet.w_valid ), + .s_axi_wready ( ethernet.w_ready ), + .s_axi_bid ( ethernet.b_id ), + .s_axi_bresp ( ethernet.b_resp ), + .s_axi_bvalid ( ethernet.b_valid ), + .s_axi_bready ( ethernet.b_ready ), + .s_axi_arid ( ethernet.ar_id ), + .s_axi_araddr ( ethernet.ar_addr ), + .s_axi_arlen ( ethernet.ar_len ), + .s_axi_arsize ( ethernet.ar_size ), + .s_axi_arburst ( ethernet.ar_burst ), + .s_axi_arlock ( ethernet.ar_lock ), + .s_axi_arcache ( ethernet.ar_cache ), + .s_axi_arprot ( ethernet.ar_prot ), + .s_axi_arregion ( ethernet.ar_region ), + .s_axi_arqos ( ethernet.ar_qos ), + .s_axi_arvalid ( ethernet.ar_valid ), + .s_axi_arready ( ethernet.ar_ready ), + .s_axi_rid ( ethernet.r_id ), + .s_axi_rdata ( ethernet.r_data ), + .s_axi_rresp ( ethernet.r_resp ), + .s_axi_rlast ( ethernet.r_last ), + .s_axi_rvalid ( ethernet.r_valid ), + .s_axi_rready ( ethernet.r_ready ), + // to size converter + .m_axi_aclk ( eth_clk_i ), + .m_axi_aresetn ( s_eth_rst_n ), + .m_axi_awid ( axi_ethernet_cdc.aw_id ), + .m_axi_awaddr ( axi_ethernet_cdc.aw_addr ), + .m_axi_awlen ( axi_ethernet_cdc.aw_len ), + .m_axi_awsize ( axi_ethernet_cdc.aw_size ), + .m_axi_awburst ( axi_ethernet_cdc.aw_burst ), + .m_axi_awlock ( axi_ethernet_cdc.aw_lock ), + .m_axi_awcache ( axi_ethernet_cdc.aw_cache ), + .m_axi_awprot ( axi_ethernet_cdc.aw_prot ), + .m_axi_awregion ( axi_ethernet_cdc.aw_region ), + .m_axi_awqos ( axi_ethernet_cdc.aw_qos ), + .m_axi_awvalid ( axi_ethernet_cdc.aw_valid ), + .m_axi_awready ( axi_ethernet_cdc.aw_ready ), + .m_axi_wdata ( axi_ethernet_cdc.w_data ), + .m_axi_wstrb ( axi_ethernet_cdc.w_strb ), + .m_axi_wlast ( axi_ethernet_cdc.w_last ), + .m_axi_wvalid ( axi_ethernet_cdc.w_valid ), + .m_axi_wready ( axi_ethernet_cdc.w_ready ), + .m_axi_bid ( axi_ethernet_cdc.b_id ), + .m_axi_bresp ( axi_ethernet_cdc.b_resp ), + .m_axi_bvalid ( axi_ethernet_cdc.b_valid ), + .m_axi_bready ( axi_ethernet_cdc.b_ready ), + .m_axi_arid ( axi_ethernet_cdc.ar_id ), + .m_axi_araddr ( axi_ethernet_cdc.ar_addr ), + .m_axi_arlen ( axi_ethernet_cdc.ar_len ), + .m_axi_arsize ( axi_ethernet_cdc.ar_size ), + .m_axi_arburst ( axi_ethernet_cdc.ar_burst ), + .m_axi_arlock ( axi_ethernet_cdc.ar_lock ), + .m_axi_arcache ( axi_ethernet_cdc.ar_cache ), + .m_axi_arprot ( axi_ethernet_cdc.ar_prot ), + .m_axi_arregion ( axi_ethernet_cdc.ar_region ), + .m_axi_arqos ( axi_ethernet_cdc.ar_qos ), + .m_axi_arvalid ( axi_ethernet_cdc.ar_valid ), + .m_axi_arready ( axi_ethernet_cdc.ar_ready ), + .m_axi_rid ( axi_ethernet_cdc.r_id ), + .m_axi_rdata ( axi_ethernet_cdc.r_data ), + .m_axi_rresp ( axi_ethernet_cdc.r_resp ), + .m_axi_rlast ( axi_ethernet_cdc.r_last ), + .m_axi_rvalid ( axi_ethernet_cdc.r_valid ), + .m_axi_rready ( axi_ethernet_cdc.r_ready ) + ); + + // system-bus is 64-bit, convert down to 32 bit + xlnx_axi_dwidth_converter i_xlnx_axi_dwidth_converter_ethernet ( + .s_axi_aclk ( eth_clk_i ), + .s_axi_aresetn ( s_eth_rst_n ), + .s_axi_awid ( axi_ethernet_cdc.aw_id ), + .s_axi_awaddr ( axi_ethernet_cdc.aw_addr[31:0] ), + .s_axi_awlen ( axi_ethernet_cdc.aw_len ), + .s_axi_awsize ( axi_ethernet_cdc.aw_size ), + .s_axi_awburst ( axi_ethernet_cdc.aw_burst ), + .s_axi_awlock ( axi_ethernet_cdc.aw_lock ), + .s_axi_awcache ( axi_ethernet_cdc.aw_cache ), + .s_axi_awprot ( axi_ethernet_cdc.aw_prot ), + .s_axi_awregion ( axi_ethernet_cdc.aw_region ), + .s_axi_awqos ( axi_ethernet_cdc.aw_qos ), + .s_axi_awvalid ( axi_ethernet_cdc.aw_valid ), + .s_axi_awready ( axi_ethernet_cdc.aw_ready ), + .s_axi_wdata ( axi_ethernet_cdc.w_data ), + .s_axi_wstrb ( axi_ethernet_cdc.w_strb ), + .s_axi_wlast ( axi_ethernet_cdc.w_last ), + .s_axi_wvalid ( axi_ethernet_cdc.w_valid ), + .s_axi_wready ( axi_ethernet_cdc.w_ready ), + .s_axi_bid ( axi_ethernet_cdc.b_id ), + .s_axi_bresp ( axi_ethernet_cdc.b_resp ), + .s_axi_bvalid ( axi_ethernet_cdc.b_valid ), + .s_axi_bready ( axi_ethernet_cdc.b_ready ), + .s_axi_arid ( axi_ethernet_cdc.ar_id ), + .s_axi_araddr ( axi_ethernet_cdc.ar_addr[31:0] ), + .s_axi_arlen ( axi_ethernet_cdc.ar_len ), + .s_axi_arsize ( axi_ethernet_cdc.ar_size ), + .s_axi_arburst ( axi_ethernet_cdc.ar_burst ), + .s_axi_arlock ( axi_ethernet_cdc.ar_lock ), + .s_axi_arcache ( axi_ethernet_cdc.ar_cache ), + .s_axi_arprot ( axi_ethernet_cdc.ar_prot ), + .s_axi_arregion ( axi_ethernet_cdc.ar_region ), + .s_axi_arqos ( axi_ethernet_cdc.ar_qos ), + .s_axi_arvalid ( axi_ethernet_cdc.ar_valid ), + .s_axi_arready ( axi_ethernet_cdc.ar_ready ), + .s_axi_rid ( axi_ethernet_cdc.r_id ), + .s_axi_rdata ( axi_ethernet_cdc.r_data ), + .s_axi_rresp ( axi_ethernet_cdc.r_resp ), + .s_axi_rlast ( axi_ethernet_cdc.r_last ), + .s_axi_rvalid ( axi_ethernet_cdc.r_valid ), + .s_axi_rready ( axi_ethernet_cdc.r_ready ), + + .m_axi_awaddr ( s_axi_eth_awaddr ), + .m_axi_awlen ( s_axi_eth_awlen ), + .m_axi_awsize ( s_axi_eth_awsize ), + .m_axi_awburst ( s_axi_eth_awburst ), + .m_axi_awlock ( ), + .m_axi_awcache ( s_axi_eth_awcache ), + .m_axi_awprot ( ), + .m_axi_awregion ( ), + .m_axi_awqos ( ), + .m_axi_awvalid ( s_axi_eth_awvalid ), + .m_axi_awready ( s_axi_eth_awready ), + .m_axi_wdata ( s_axi_eth_wdata ), + .m_axi_wstrb ( s_axi_eth_wstrb ), + .m_axi_wlast ( s_axi_eth_wlast ), + .m_axi_wvalid ( s_axi_eth_wvalid ), + .m_axi_wready ( s_axi_eth_wready ), + .m_axi_bresp ( s_axi_eth_bresp ), + .m_axi_bvalid ( s_axi_eth_bvalid ), + .m_axi_bready ( s_axi_eth_bready ), + .m_axi_araddr ( s_axi_eth_araddr ), + .m_axi_arlen ( s_axi_eth_arlen ), + .m_axi_arsize ( s_axi_eth_arsize ), + .m_axi_arburst ( s_axi_eth_arburst ), + .m_axi_arlock ( ), + .m_axi_arcache ( s_axi_eth_arcache ), + .m_axi_arprot ( ), + .m_axi_arregion ( ), + .m_axi_arqos ( ), + .m_axi_arvalid ( s_axi_eth_arvalid ), + .m_axi_arready ( s_axi_eth_arready ), + .m_axi_rdata ( s_axi_eth_rdata ), + .m_axi_rresp ( s_axi_eth_rresp ), + .m_axi_rlast ( s_axi_eth_rlast ), + .m_axi_rvalid ( s_axi_eth_rvalid ), + .m_axi_rready ( s_axi_eth_rready ) + ); + + logic phy_rx_clk; + logic phy_crs; + logic phy_dv; + logic [3:0] phy_rx_data; + logic phy_col; + logic phy_rx_er; + logic phy_rst_n; + logic phy_tx_en; + logic [3:0] phy_tx_data; + logic phy_mdio_i; + logic phy_mdio_o; + logic phy_mdio_t; + logic phy_mdc; + + xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite ( + .s_axi_aclk ( eth_clk_i ), + .s_axi_aresetn ( s_eth_rst_n ), + .ip2intc_irpt ( irq_sources[2] ), + .s_axi_awaddr ( s_axi_eth_awaddr[12:0] ), + .s_axi_awlen ( s_axi_eth_awlen ), + .s_axi_awsize ( s_axi_eth_awsize ), + .s_axi_awburst ( s_axi_eth_awburst ), + .s_axi_awcache ( s_axi_eth_awcache ), + .s_axi_awvalid ( s_axi_eth_awvalid ), + .s_axi_awready ( s_axi_eth_awready ), + .s_axi_wdata ( s_axi_eth_wdata ), + .s_axi_wstrb ( s_axi_eth_wstrb ), + .s_axi_wlast ( s_axi_eth_wlast ), + .s_axi_wvalid ( s_axi_eth_wvalid ), + .s_axi_wready ( s_axi_eth_wready ), + .s_axi_bresp ( s_axi_eth_bresp ), + .s_axi_bvalid ( s_axi_eth_bvalid ), + .s_axi_bready ( s_axi_eth_bready ), + .s_axi_araddr ( s_axi_eth_araddr[12:0] ), + .s_axi_arlen ( s_axi_eth_arlen ), + .s_axi_arsize ( s_axi_eth_arsize ), + .s_axi_arburst ( s_axi_eth_arburst ), + .s_axi_arcache ( s_axi_eth_arcache ), + .s_axi_arvalid ( s_axi_eth_arvalid ), + .s_axi_arready ( s_axi_eth_arready ), + .s_axi_rdata ( s_axi_eth_rdata ), + .s_axi_rresp ( s_axi_eth_rresp ), + .s_axi_rlast ( s_axi_eth_rlast ), + .s_axi_rvalid ( s_axi_eth_rvalid ), + .s_axi_rready ( s_axi_eth_rready ), + .phy_tx_clk ( phy_tx_clk_i ), + .phy_rx_clk ( phy_rx_clk ), + .phy_crs ( phy_crs ), + .phy_dv ( phy_dv ), + .phy_rx_data ( phy_rx_data ), + .phy_col ( phy_col ), + .phy_rx_er ( phy_rx_er ), + .phy_rst_n ( phy_rst_n ), + .phy_tx_en ( phy_tx_en ), + .phy_tx_data ( phy_tx_data ), + .phy_mdio_i ( phy_mdio_i ), + .phy_mdio_o ( phy_mdio_o ), + .phy_mdio_t ( phy_mdio_t ), + .phy_mdc ( phy_mdc ) + ); + + assign phy_crs = 1'b0; + assign phy_col = 1'b0; + + rgmii_to_mii_conv_xilinx i_rgmii_to_mii_conv_xilinx ( + .rgmii_phy_txc ( eth_txck ), + .rgmii_phy_txctl ( eth_txctl ), + .rgmii_phy_txd ( eth_txd ), + .rgmii_phy_rxc ( eth_rxck ), + .rgmii_phy_rxctl ( eth_rxctl ), + .rgmii_phy_rxd ( eth_rxd ), + .rgmii_phy_rst_n ( eth_rst_n ), + .rgmii_phy_mdio ( eth_mdio ), + .rgmii_phy_mdc ( eth_mdc ), + .mem_clk_i ( clk_200MHz_i ), + .net_phy_rst_n ( phy_rst_n ), + .net_phy_tx_clk ( phy_tx_clk_i ), + .net_phy_tx_en ( phy_tx_en ), + .net_phy_tx_data ( phy_tx_data ), + .net_phy_rx_clk ( phy_rx_clk ), + .net_phy_dv ( phy_dv ), + .net_phy_rx_data ( phy_rx_data ), + .net_phy_rx_er ( phy_rx_er ), + .net_mdio_i ( phy_mdio_o ), + .net_mdio_o ( phy_mdio_i ), + .net_mdio_t ( phy_mdio_t ), + .net_phy_mdc ( phy_mdc ) + ); + + end else begin + assign irq_sources [2] = 1'b0; + assign ethernet.aw_ready = 1'b1; + assign ethernet.ar_ready = 1'b1; + assign ethernet.w_ready = 1'b1; + + assign ethernet.b_valid = ethernet.aw_valid; + assign ethernet.b_id = ethernet.aw_id; + assign ethernet.b_resp = axi_pkg::RESP_SLVERR; + assign ethernet.b_user = '0; + + assign ethernet.r_valid = ethernet.ar_valid; + assign ethernet.r_resp = axi_pkg::RESP_SLVERR; + assign ethernet.r_data = 'hdeadbeef; + assign ethernet.r_last = 1'b1; + end + + // 5. GPIO + assign gpio.b_user = 1'b0; + assign gpio.r_user = 1'b0; + + if (InclGPIO) begin : gen_gpio + + logic [31:0] s_axi_gpio_awaddr; + logic [7:0] s_axi_gpio_awlen; + logic [2:0] s_axi_gpio_awsize; + logic [1:0] s_axi_gpio_awburst; + logic [3:0] s_axi_gpio_awcache; + logic s_axi_gpio_awvalid; + logic s_axi_gpio_awready; + logic [31:0] s_axi_gpio_wdata; + logic [3:0] s_axi_gpio_wstrb; + logic s_axi_gpio_wlast; + logic s_axi_gpio_wvalid; + logic s_axi_gpio_wready; + logic [1:0] s_axi_gpio_bresp; + logic s_axi_gpio_bvalid; + logic s_axi_gpio_bready; + logic [31:0] s_axi_gpio_araddr; + logic [7:0] s_axi_gpio_arlen; + logic [2:0] s_axi_gpio_arsize; + logic [1:0] s_axi_gpio_arburst; + logic [3:0] s_axi_gpio_arcache; + logic s_axi_gpio_arvalid; + logic s_axi_gpio_arready; + logic [31:0] s_axi_gpio_rdata; + logic [1:0] s_axi_gpio_rresp; + logic s_axi_gpio_rlast; + logic s_axi_gpio_rvalid; + // system-bus is 64-bit, convert down to 32 bit + xlnx_axi_dwidth_converter i_xlnx_axi_dwidth_converter_gpio ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + .s_axi_awid ( gpio.aw_id ), + .s_axi_awaddr ( gpio.aw_addr[31:0] ), + .s_axi_awlen ( gpio.aw_len ), + .s_axi_awsize ( gpio.aw_size ), + .s_axi_awburst ( gpio.aw_burst ), + .s_axi_awlock ( gpio.aw_lock ), + .s_axi_awcache ( gpio.aw_cache ), + .s_axi_awprot ( gpio.aw_prot ), + .s_axi_awregion ( gpio.aw_region ), + .s_axi_awqos ( gpio.aw_qos ), + .s_axi_awvalid ( gpio.aw_valid ), + .s_axi_awready ( gpio.aw_ready ), + .s_axi_wdata ( gpio.w_data ), + .s_axi_wstrb ( gpio.w_strb ), + .s_axi_wlast ( gpio.w_last ), + .s_axi_wvalid ( gpio.w_valid ), + .s_axi_wready ( gpio.w_ready ), + .s_axi_bid ( gpio.b_id ), + .s_axi_bresp ( gpio.b_resp ), + .s_axi_bvalid ( gpio.b_valid ), + .s_axi_bready ( gpio.b_ready ), + .s_axi_arid ( gpio.ar_id ), + .s_axi_araddr ( gpio.ar_addr[31:0] ), + .s_axi_arlen ( gpio.ar_len ), + .s_axi_arsize ( gpio.ar_size ), + .s_axi_arburst ( gpio.ar_burst ), + .s_axi_arlock ( gpio.ar_lock ), + .s_axi_arcache ( gpio.ar_cache ), + .s_axi_arprot ( gpio.ar_prot ), + .s_axi_arregion ( gpio.ar_region ), + .s_axi_arqos ( gpio.ar_qos ), + .s_axi_arvalid ( gpio.ar_valid ), + .s_axi_arready ( gpio.ar_ready ), + .s_axi_rid ( gpio.r_id ), + .s_axi_rdata ( gpio.r_data ), + .s_axi_rresp ( gpio.r_resp ), + .s_axi_rlast ( gpio.r_last ), + .s_axi_rvalid ( gpio.r_valid ), + .s_axi_rready ( gpio.r_ready ), + + .m_axi_awaddr ( s_axi_gpio_awaddr ), + .m_axi_awlen ( s_axi_gpio_awlen ), + .m_axi_awsize ( s_axi_gpio_awsize ), + .m_axi_awburst ( s_axi_gpio_awburst ), + .m_axi_awlock ( ), + .m_axi_awcache ( s_axi_gpio_awcache ), + .m_axi_awprot ( ), + .m_axi_awregion ( ), + .m_axi_awqos ( ), + .m_axi_awvalid ( s_axi_gpio_awvalid ), + .m_axi_awready ( s_axi_gpio_awready ), + .m_axi_wdata ( s_axi_gpio_wdata ), + .m_axi_wstrb ( s_axi_gpio_wstrb ), + .m_axi_wlast ( s_axi_gpio_wlast ), + .m_axi_wvalid ( s_axi_gpio_wvalid ), + .m_axi_wready ( s_axi_gpio_wready ), + .m_axi_bresp ( s_axi_gpio_bresp ), + .m_axi_bvalid ( s_axi_gpio_bvalid ), + .m_axi_bready ( s_axi_gpio_bready ), + .m_axi_araddr ( s_axi_gpio_araddr ), + .m_axi_arlen ( s_axi_gpio_arlen ), + .m_axi_arsize ( s_axi_gpio_arsize ), + .m_axi_arburst ( s_axi_gpio_arburst ), + .m_axi_arlock ( ), + .m_axi_arcache ( s_axi_gpio_arcache ), + .m_axi_arprot ( ), + .m_axi_arregion ( ), + .m_axi_arqos ( ), + .m_axi_arvalid ( s_axi_gpio_arvalid ), + .m_axi_arready ( s_axi_gpio_arready ), + .m_axi_rdata ( s_axi_gpio_rdata ), + .m_axi_rresp ( s_axi_gpio_rresp ), + .m_axi_rlast ( s_axi_gpio_rlast ), + .m_axi_rvalid ( s_axi_gpio_rvalid ), + .m_axi_rready ( s_axi_gpio_rready ) + ); + + xlnx_axi_gpio i_xlnx_axi_gpio ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + .s_axi_awaddr ( s_axi_gpio_awaddr[8:0] ), + .s_axi_awvalid ( s_axi_gpio_awvalid ), + .s_axi_awready ( s_axi_gpio_awready ), + .s_axi_wdata ( s_axi_gpio_wdata ), + .s_axi_wstrb ( s_axi_gpio_wstrb ), + .s_axi_wvalid ( s_axi_gpio_wvalid ), + .s_axi_wready ( s_axi_gpio_wready ), + .s_axi_bresp ( s_axi_gpio_bresp ), + .s_axi_bvalid ( s_axi_gpio_bvalid ), + .s_axi_bready ( s_axi_gpio_bready ), + .s_axi_araddr ( s_axi_gpio_araddr[8:0] ), + .s_axi_arvalid ( s_axi_gpio_arvalid ), + .s_axi_arready ( s_axi_gpio_arready ), + .s_axi_rdata ( s_axi_gpio_rdata ), + .s_axi_rresp ( s_axi_gpio_rresp ), + .s_axi_rvalid ( s_axi_gpio_rvalid ), + .s_axi_rready ( s_axi_gpio_rready ), + .gpio_io_i ( '0 ), + .gpio_io_o ( leds_o ), + .gpio_io_t ( ), + .gpio2_io_i ( dip_switches_i ) + ); + + assign s_axi_gpio_rlast = 1'b1; + assign s_axi_gpio_wlast = 1'b1; + end +endmodule diff --git a/fpga/src/ariane_xilinx.sv b/fpga/src/ariane_xilinx.sv new file mode 100644 index 0000000000..0f8563ea03 --- /dev/null +++ b/fpga/src/ariane_xilinx.sv @@ -0,0 +1,1140 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Description: Xilinx FPGA top-level +// Author: Florian Zaruba + +module ariane_xilinx ( +`ifdef GENESYSII + input logic sys_clk_p , + input logic sys_clk_n , + input logic cpu_resetn , + inout logic [31:0] ddr3_dq , + inout logic [ 3:0] ddr3_dqs_n , + inout logic [ 3:0] ddr3_dqs_p , + output logic [14:0] ddr3_addr , + output logic [ 2:0] ddr3_ba , + output logic ddr3_ras_n , + output logic ddr3_cas_n , + output logic ddr3_we_n , + output logic ddr3_reset_n, + output logic [ 0:0] ddr3_ck_p , + output logic [ 0:0] ddr3_ck_n , + output logic [ 0:0] ddr3_cke , + output logic [ 0:0] ddr3_cs_n , + output logic [ 3:0] ddr3_dm , + output logic [ 0:0] ddr3_odt , + output wire eth_rst_n , + input wire eth_rxck , + input wire eth_rxctl , + input wire [3:0] eth_rxd , + output wire eth_txck , + output wire eth_txctl , + output wire [3:0] eth_txd , + inout wire eth_mdio , + output logic eth_mdc , + output logic [ 7:0] led , + input logic [ 7:0] sw , + output logic fan_pwm , +`elsif VCU118 + input wire c0_sys_clk_p , // 250 MHz Clock for DDR + input wire c0_sys_clk_n , // 250 MHz Clock for DDR + input wire sys_clk_p , // 100 MHz Clock for PCIe + input wire sys_clk_n , // 100 MHz Clock for PCIE + input wire sys_rst_n , // PCIe Reset + input logic cpu_reset , // CPU subsystem reset + output wire [16:0] c0_ddr4_adr , + output wire [1:0] c0_ddr4_ba , + output wire [0:0] c0_ddr4_cke , + output wire [0:0] c0_ddr4_cs_n , + inout wire [7:0] c0_ddr4_dm_dbi_n, + inout wire [63:0] c0_ddr4_dq , + inout wire [7:0] c0_ddr4_dqs_c , + inout wire [7:0] c0_ddr4_dqs_t , + output wire [0:0] c0_ddr4_odt , + output wire [0:0] c0_ddr4_bg , + output wire c0_ddr4_reset_n , + output wire c0_ddr4_act_n , + output wire [0:0] c0_ddr4_ck_c , + output wire [0:0] c0_ddr4_ck_t , + output wire [7:0] pci_exp_txp , + output wire [7:0] pci_exp_txn , + input wire [7:0] pci_exp_rxp , + input wire [7:0] pci_exp_rxn , +`endif + // SPI + output logic spi_mosi , + input logic spi_miso , + output logic spi_ss , + output logic spi_clk_o , + // common part + input logic tck , + input logic tms , + input logic trst_n , + input logic tdi , + output logic tdo , + input logic rx , + output logic tx +); +// 24 MByte in 8 byte words +localparam NumWords = (24 * 1024 * 1024) / 8; +localparam NBSlave = 2; // debug, ariane +localparam CacheStartAddr = (1 << 31); +localparam AxiAddrWidth = 64; +localparam AxiDataWidth = 64; +localparam AxiIdWidthMaster = 4; +localparam AxiIdWidthSlaves = AxiIdWidthMaster + $clog2(NBSlave); // 5 +localparam AxiUserWidth = 1; + +AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthMaster ), + .AXI_USER_WIDTH ( AxiUserWidth ) +) slave[NBSlave-1:0](); + +AXI_BUS #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ) +) master[ariane_soc::NB_PERIPHERALS-1:0](); + +// disable test-enable +logic test_en; +logic ndmreset; +logic ndmreset_n; +logic debug_req_irq; +logic time_irq; +logic ipi; + +logic clk; +logic eth_clk; +logic spi_clk_i; +logic phy_tx_clk; + +logic ddr_sync_reset; +logic ddr_clock_out; + +logic rst_n, rst; +logic rtc; + +// we need to switch reset polarity +`ifdef VCU118 +logic cpu_resetn; +assign cpu_resetn = ~cpu_reset; +`elsif GENESYSII +logic cpu_reset; +assign cpu_reset = ~cpu_resetn; +`endif + +logic pll_locked; + +// ROM +logic rom_req; +logic [AxiAddrWidth-1:0] rom_addr; +logic [AxiDataWidth-1:0] rom_rdata; + +// Debug +logic debug_req_valid; +logic debug_req_ready; +dm::dmi_req_t debug_req; +logic debug_resp_valid; +logic debug_resp_ready; +dm::dmi_resp_t debug_resp; + +logic dmactive; + +// IRQ +logic [1:0] irq; +assign test_en = 1'b0; + +logic [NBSlave-1:0] pc_asserted; + +rstgen i_rstgen_main ( + .clk_i ( clk ), + .rst_ni ( pll_locked & (~ndmreset) ), + .test_mode_i ( test_en ), + .rst_no ( ndmreset_n ), + .init_no ( ) // keep open +); + +assign rst_n = ~ddr_sync_reset; +assign rst = ddr_sync_reset; + +// --------------- +// AXI Xbar +// --------------- +axi_node_wrap_with_slices #( + // three ports from Ariane (instruction, data and bypass) + .NB_SLAVE ( NBSlave ), + .NB_MASTER ( ariane_soc::NB_PERIPHERALS ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ), + .AXI_ID_WIDTH ( AxiIdWidthMaster ), + .MASTER_SLICE_DEPTH ( 2 ), + .SLAVE_SLICE_DEPTH ( 2 ) +) i_axi_xbar ( + .clk ( clk ), + .rst_n ( ndmreset_n ), + .test_en_i ( test_en ), + .slave ( slave ), + .master ( master ), + .start_addr_i ({ + ariane_soc::DebugBase, + ariane_soc::ROMBase, + ariane_soc::CLINTBase, + ariane_soc::PLICBase, + ariane_soc::UARTBase, + ariane_soc::SPIBase, + ariane_soc::EthernetBase, + ariane_soc::GPIOBase, + ariane_soc::DRAMBase + }), + .end_addr_i ({ + ariane_soc::DebugBase + ariane_soc::DebugLength - 1, + ariane_soc::ROMBase + ariane_soc::ROMLength - 1, + ariane_soc::CLINTBase + ariane_soc::CLINTLength - 1, + ariane_soc::PLICBase + ariane_soc::PLICLength - 1, + ariane_soc::UARTBase + ariane_soc::UARTLength - 1, + ariane_soc::SPIBase + ariane_soc::SPILength - 1, + ariane_soc::EthernetBase + ariane_soc::EthernetLength -1, + ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1, + ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1 + }) +); + +// --------------- +// Debug Module +// --------------- +dmi_jtag i_dmi_jtag ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .dmi_rst_no ( ), // keep open + .testmode_i ( test_en ), + .dmi_req_valid_o ( debug_req_valid ), + .dmi_req_ready_i ( debug_req_ready ), + .dmi_req_o ( debug_req ), + .dmi_resp_valid_i ( debug_resp_valid ), + .dmi_resp_ready_o ( debug_resp_ready ), + .dmi_resp_i ( debug_resp ), + .tck_i ( tck ), + .tms_i ( tms ), + .trst_ni ( trst_n ), + .td_i ( tdi ), + .td_o ( tdo ), + .tdo_oe_o ( ) +); + +ariane_axi::req_t dm_axi_m_req, dm_axi_s_req; +ariane_axi::resp_t dm_axi_m_resp, dm_axi_s_resp; + +// debug module +dm_top #( + // current implementation only supports 1 hart + .NrHarts ( 1 ), + .AxiIdWidth ( AxiIdWidthSlaves ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiUserWidth ( AxiUserWidth ) +) i_dm_top ( + .clk_i ( clk ), + .rst_ni ( rst_n ), // PoR + .testmode_i ( test_en ), + .ndmreset_o ( ndmreset ), + .dmactive_o ( dmactive ), // active debug session + .debug_req_o ( debug_req_irq ), + .unavailable_i ( '0 ), + .axi_s_req_i ( dm_axi_s_req ), + .axi_s_resp_o ( dm_axi_s_resp ), + .axi_m_req_o ( dm_axi_m_req ), + .axi_m_resp_i ( dm_axi_m_resp ), + .dmi_rst_ni ( rst_n ), + .dmi_req_valid_i ( debug_req_valid ), + .dmi_req_ready_o ( debug_req_ready ), + .dmi_req_i ( debug_req ), + .dmi_resp_valid_o ( debug_resp_valid ), + .dmi_resp_ready_i ( debug_resp_ready ), + .dmi_resp_o ( debug_resp ) +); + +axi_master_connect i_axi_master_dm (.axi_req_i(dm_axi_m_req), .axi_resp_o(dm_axi_m_resp), .master(slave[1])); +axi_slave_connect i_axi_slave_dm (.axi_req_o(dm_axi_s_req), .axi_resp_i(dm_axi_s_resp), .slave(master[ariane_soc::Debug])); + +// --------------- +// Core +// --------------- +ariane_axi::req_t axi_ariane_req; +ariane_axi::resp_t axi_ariane_resp; + +ariane #( + .CachedAddrBeg ( CacheStartAddr ) +) i_ariane ( + .clk_i ( clk ), + .rst_ni ( ndmreset_n ), + .boot_addr_i ( ariane_soc::ROMBase ), // start fetching from ROM + .hart_id_i ( '0 ), + .irq_i ( irq ), + .ipi_i ( ipi ), + .time_irq_i ( timer_irq ), + .debug_req_i ( debug_req_irq ), + .axi_req_o ( axi_ariane_req ), + .axi_resp_i ( axi_ariane_resp ) +); + +axi_master_connect i_axi_master_connect_ariane (.axi_req_i(axi_ariane_req), .axi_resp_o(axi_ariane_resp), .master(slave[0])); + +// --------------- +// CLINT +// --------------- +// divide clock by two +always_ff @(posedge clk or negedge ndmreset_n) begin + if (~ndmreset_n) begin + rtc <= 0; + end else begin + rtc <= rtc ^ 1'b1; + end +end + +ariane_axi::req_t axi_clint_req; +ariane_axi::resp_t axi_clint_resp; + +clint #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .NR_CORES ( 1 ) +) i_clint ( + .clk_i ( clk ), + .rst_ni ( ndmreset_n ), + .testmode_i ( test_en ), + .axi_req_i ( axi_clint_req ), + .axi_resp_o ( axi_clint_resp ), + .rtc_i ( rtc ), + .timer_irq_o ( timer_irq ), + .ipi_o ( ipi ) +); + +axi_slave_connect i_axi_slave_connect_clint (.axi_req_o(axi_clint_req), .axi_resp_i(axi_clint_resp), .slave(master[ariane_soc::CLINT])); + +// --------------- +// ROM +// --------------- +axi2mem #( + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) +) i_axi2rom ( + .clk_i ( clk ), + .rst_ni ( ndmreset_n ), + .slave ( master[ariane_soc::ROM] ), + .req_o ( rom_req ), + .we_o ( ), + .addr_o ( rom_addr ), + .be_o ( ), + .data_o ( ), + .data_i ( rom_rdata ) +); + +bootrom i_bootrom ( + .clk_i ( clk ), + .req_i ( rom_req ), + .addr_i ( rom_addr ), + .rdata_o ( rom_rdata ) +); + +// --------------- +// Peripherals +// --------------- +ariane_peripherals #( + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiIdWidth ( AxiIdWidthSlaves ), + .AxiUserWidth ( AxiUserWidth ), + .InclUART ( 1'b1 ), + .InclGPIO ( 1'b1 ), + `ifdef GENESYSII + .InclSPI ( 1'b1 ), + .InclEthernet ( 1'b1 ) + `elsif VCU118 + .InclSPI ( 1'b0 ), + .InclEthernet ( 1'b0 ) + `endif +) i_ariane_peripherals ( + .clk_i ( clk ), + .clk_200MHz_i ( ddr_clock_out ), + .rst_ni ( ndmreset_n ), + .plic ( master[ariane_soc::PLIC] ), + .uart ( master[ariane_soc::UART] ), + .spi ( master[ariane_soc::SPI] ), + .gpio ( master[ariane_soc::GPIO] ), + .eth_clk_i ( eth_clk ), + .ethernet ( master[ariane_soc::Ethernet] ), + .irq_o ( irq ), + .rx_i ( rx ), + .tx_o ( tx ), + .eth_txck, + .eth_rxck, + .eth_rxctl, + .eth_rxd, + .eth_rst_n, + .eth_txctl, + .eth_txd, + .eth_mdio, + .eth_mdc, + .phy_tx_clk_i ( phy_tx_clk ), + .spi_clk_o ( spi_clk_o ), + .spi_mosi ( spi_mosi ), + .spi_miso ( spi_miso ), + .spi_ss ( spi_ss ), + .leds_o ( led ), + .dip_switches_i ( sw ) +); + +// --------------------- +// Board peripherals +// --------------------- +// --------------- +// DDR +// --------------- +logic [AxiIdWidthSlaves-1:0] s_axi_awid; +logic [AxiAddrWidth-1:0] s_axi_awaddr; +logic [7:0] s_axi_awlen; +logic [2:0] s_axi_awsize; +logic [1:0] s_axi_awburst; +logic [0:0] s_axi_awlock; +logic [3:0] s_axi_awcache; +logic [2:0] s_axi_awprot; +logic [3:0] s_axi_awregion; +logic [3:0] s_axi_awqos; +logic s_axi_awvalid; +logic s_axi_awready; +logic [AxiDataWidth-1:0] s_axi_wdata; +logic [AxiDataWidth/8-1:0] s_axi_wstrb; +logic s_axi_wlast; +logic s_axi_wvalid; +logic s_axi_wready; +logic [AxiIdWidthSlaves-1:0] s_axi_bid; +logic [1:0] s_axi_bresp; +logic s_axi_bvalid; +logic s_axi_bready; +logic [AxiIdWidthSlaves-1:0] s_axi_arid; +logic [AxiAddrWidth-1:0] s_axi_araddr; +logic [7:0] s_axi_arlen; +logic [2:0] s_axi_arsize; +logic [1:0] s_axi_arburst; +logic [0:0] s_axi_arlock; +logic [3:0] s_axi_arcache; +logic [2:0] s_axi_arprot; +logic [3:0] s_axi_arregion; +logic [3:0] s_axi_arqos; +logic s_axi_arvalid; +logic s_axi_arready; +logic [AxiIdWidthSlaves-1:0] s_axi_rid; +logic [AxiDataWidth-1:0] s_axi_rdata; +logic [1:0] s_axi_rresp; +logic s_axi_rlast; +logic s_axi_rvalid; +logic s_axi_rready; + +assign master[ariane_soc::DRAM].r_user = '0; +assign master[ariane_soc::DRAM].b_user = '0; + +xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ddr ( + .s_axi_aclk ( clk ), + .s_axi_aresetn ( ndmreset_n ), + .s_axi_awid ( master[ariane_soc::DRAM].aw_id ), + .s_axi_awaddr ( master[ariane_soc::DRAM].aw_addr ), + .s_axi_awlen ( master[ariane_soc::DRAM].aw_len ), + .s_axi_awsize ( master[ariane_soc::DRAM].aw_size ), + .s_axi_awburst ( master[ariane_soc::DRAM].aw_burst ), + .s_axi_awlock ( master[ariane_soc::DRAM].aw_lock ), + .s_axi_awcache ( master[ariane_soc::DRAM].aw_cache ), + .s_axi_awprot ( master[ariane_soc::DRAM].aw_prot ), + .s_axi_awregion ( master[ariane_soc::DRAM].aw_region ), + .s_axi_awqos ( master[ariane_soc::DRAM].aw_qos ), + .s_axi_awvalid ( master[ariane_soc::DRAM].aw_valid ), + .s_axi_awready ( master[ariane_soc::DRAM].aw_ready ), + .s_axi_wdata ( master[ariane_soc::DRAM].w_data ), + .s_axi_wstrb ( master[ariane_soc::DRAM].w_strb ), + .s_axi_wlast ( master[ariane_soc::DRAM].w_last ), + .s_axi_wvalid ( master[ariane_soc::DRAM].w_valid ), + .s_axi_wready ( master[ariane_soc::DRAM].w_ready ), + .s_axi_bid ( master[ariane_soc::DRAM].b_id ), + .s_axi_bresp ( master[ariane_soc::DRAM].b_resp ), + .s_axi_bvalid ( master[ariane_soc::DRAM].b_valid ), + .s_axi_bready ( master[ariane_soc::DRAM].b_ready ), + .s_axi_arid ( master[ariane_soc::DRAM].ar_id ), + .s_axi_araddr ( master[ariane_soc::DRAM].ar_addr ), + .s_axi_arlen ( master[ariane_soc::DRAM].ar_len ), + .s_axi_arsize ( master[ariane_soc::DRAM].ar_size ), + .s_axi_arburst ( master[ariane_soc::DRAM].ar_burst ), + .s_axi_arlock ( master[ariane_soc::DRAM].ar_lock ), + .s_axi_arcache ( master[ariane_soc::DRAM].ar_cache ), + .s_axi_arprot ( master[ariane_soc::DRAM].ar_prot ), + .s_axi_arregion ( master[ariane_soc::DRAM].ar_region ), + .s_axi_arqos ( master[ariane_soc::DRAM].ar_qos ), + .s_axi_arvalid ( master[ariane_soc::DRAM].ar_valid ), + .s_axi_arready ( master[ariane_soc::DRAM].ar_ready ), + .s_axi_rid ( master[ariane_soc::DRAM].r_id ), + .s_axi_rdata ( master[ariane_soc::DRAM].r_data ), + .s_axi_rresp ( master[ariane_soc::DRAM].r_resp ), + .s_axi_rlast ( master[ariane_soc::DRAM].r_last ), + .s_axi_rvalid ( master[ariane_soc::DRAM].r_valid ), + .s_axi_rready ( master[ariane_soc::DRAM].r_ready ), + // to size converter + .m_axi_aclk ( ddr_clock_out ), + .m_axi_aresetn ( ndmreset_n ), + .m_axi_awid ( s_axi_awid ), + .m_axi_awaddr ( s_axi_awaddr ), + .m_axi_awlen ( s_axi_awlen ), + .m_axi_awsize ( s_axi_awsize ), + .m_axi_awburst ( s_axi_awburst ), + .m_axi_awlock ( s_axi_awlock ), + .m_axi_awcache ( s_axi_awcache ), + .m_axi_awprot ( s_axi_awprot ), + .m_axi_awregion ( s_axi_awregion ), + .m_axi_awqos ( s_axi_awqos ), + .m_axi_awvalid ( s_axi_awvalid ), + .m_axi_awready ( s_axi_awready ), + .m_axi_wdata ( s_axi_wdata ), + .m_axi_wstrb ( s_axi_wstrb ), + .m_axi_wlast ( s_axi_wlast ), + .m_axi_wvalid ( s_axi_wvalid ), + .m_axi_wready ( s_axi_wready ), + .m_axi_bid ( s_axi_bid ), + .m_axi_bresp ( s_axi_bresp ), + .m_axi_bvalid ( s_axi_bvalid ), + .m_axi_bready ( s_axi_bready ), + .m_axi_arid ( s_axi_arid ), + .m_axi_araddr ( s_axi_araddr ), + .m_axi_arlen ( s_axi_arlen ), + .m_axi_arsize ( s_axi_arsize ), + .m_axi_arburst ( s_axi_arburst ), + .m_axi_arlock ( s_axi_arlock ), + .m_axi_arcache ( s_axi_arcache ), + .m_axi_arprot ( s_axi_arprot ), + .m_axi_arregion ( s_axi_arregion ), + .m_axi_arqos ( s_axi_arqos ), + .m_axi_arvalid ( s_axi_arvalid ), + .m_axi_arready ( s_axi_arready ), + .m_axi_rid ( s_axi_rid ), + .m_axi_rdata ( s_axi_rdata ), + .m_axi_rresp ( s_axi_rresp ), + .m_axi_rlast ( s_axi_rlast ), + .m_axi_rvalid ( s_axi_rvalid ), + .m_axi_rready ( s_axi_rready ) +); + +xlnx_clk_gen i_xlnx_clk_gen ( + .clk_out1 ( clk ), // 50MHz + .clk_out2 ( phy_tx_clk ), // 25 MHz + .clk_out3 ( eth_clk ), // 100 MHz + .reset ( cpu_reset ), + .locked ( pll_locked ), + .clk_in1 ( ddr_clock_out ) +); + +`ifdef GENESYSII +fan_ctrl i_fan_ctrl ( + .clk_i ( clk ), + .rst_ni ( ndmreset_n ), + .pwm_setting_i ( sw[3:0] ), + .fan_pwm_o ( fan_pwm ) +); + +xlnx_mig_7_ddr3 i_ddr ( + .sys_clk_p, + .sys_clk_n, + .ddr3_dq, + .ddr3_dqs_n, + .ddr3_dqs_p, + .ddr3_addr, + .ddr3_ba, + .ddr3_ras_n, + .ddr3_cas_n, + .ddr3_we_n, + .ddr3_reset_n, + .ddr3_ck_p, + .ddr3_ck_n, + .ddr3_cke, + .ddr3_cs_n, + .ddr3_dm, + .ddr3_odt, + .mmcm_locked ( ), // keep open + .app_sr_req ( '0 ), + .app_ref_req ( '0 ), + .app_zq_req ( '0 ), + .app_sr_active ( ), // keep open + .app_ref_ack ( ), // keep open + .app_zq_ack ( ), // keep open + .ui_clk ( ddr_clock_out ), + .ui_clk_sync_rst ( ddr_sync_reset ), + .aresetn ( ndmreset_n ), + .s_axi_awid, + .s_axi_awaddr ( s_axi_awaddr[29:0] ), + .s_axi_awlen, + .s_axi_awsize, + .s_axi_awburst, + .s_axi_awlock, + .s_axi_awcache, + .s_axi_awprot, + .s_axi_awqos, + .s_axi_awvalid, + .s_axi_awready, + .s_axi_wdata, + .s_axi_wstrb, + .s_axi_wlast, + .s_axi_wvalid, + .s_axi_wready, + .s_axi_bready, + .s_axi_bid, + .s_axi_bresp, + .s_axi_bvalid, + .s_axi_arid, + .s_axi_araddr ( s_axi_araddr[29:0] ), + .s_axi_arlen, + .s_axi_arsize, + .s_axi_arburst, + .s_axi_arlock, + .s_axi_arcache, + .s_axi_arprot, + .s_axi_arqos, + .s_axi_arvalid, + .s_axi_arready, + .s_axi_rready, + .s_axi_rid, + .s_axi_rdata, + .s_axi_rresp, + .s_axi_rlast, + .s_axi_rvalid, + .init_calib_complete ( ), // keep open + .device_temp ( ), // keep open + .sys_rst ( cpu_resetn ) +); +`elsif VCU118 + + logic [63:0] dram_dwidth_axi_awaddr; + logic [7:0] dram_dwidth_axi_awlen; + logic [2:0] dram_dwidth_axi_awsize; + logic [1:0] dram_dwidth_axi_awburst; + logic [0:0] dram_dwidth_axi_awlock; + logic [3:0] dram_dwidth_axi_awcache; + logic [2:0] dram_dwidth_axi_awprot; + logic [3:0] dram_dwidth_axi_awqos; + logic dram_dwidth_axi_awvalid; + logic dram_dwidth_axi_awready; + logic [511:0] dram_dwidth_axi_wdata; + logic [63:0] dram_dwidth_axi_wstrb; + logic dram_dwidth_axi_wlast; + logic dram_dwidth_axi_wvalid; + logic dram_dwidth_axi_wready; + logic dram_dwidth_axi_bready; + logic [1:0] dram_dwidth_axi_bresp; + logic dram_dwidth_axi_bvalid; + logic [63:0] dram_dwidth_axi_araddr; + logic [7:0] dram_dwidth_axi_arlen; + logic [2:0] dram_dwidth_axi_arsize; + logic [1:0] dram_dwidth_axi_arburst; + logic [0:0] dram_dwidth_axi_arlock; + logic [3:0] dram_dwidth_axi_arcache; + logic [2:0] dram_dwidth_axi_arprot; + logic [3:0] dram_dwidth_axi_arqos; + logic dram_dwidth_axi_arvalid; + logic dram_dwidth_axi_arready; + logic dram_dwidth_axi_rready; + logic dram_dwidth_axi_rlast; + logic dram_dwidth_axi_rvalid; + logic [1:0] dram_dwidth_axi_rresp; + logic [511:0] dram_dwidth_axi_rdata; + +axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 ( + .s_axi_aclk ( ddr_clock_out ), + .s_axi_aresetn ( ndmreset_n ), + + .s_axi_awid ( s_axi_awid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awregion ( '0 ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arid ( s_axi_arid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arcache ( s_axi_arcache ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arregion ( '0 ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rid ( s_axi_rid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + + .m_axi_awaddr ( dram_dwidth_axi_awaddr ), + .m_axi_awlen ( dram_dwidth_axi_awlen ), + .m_axi_awsize ( dram_dwidth_axi_awsize ), + .m_axi_awburst ( dram_dwidth_axi_awburst ), + .m_axi_awlock ( dram_dwidth_axi_awlock ), + .m_axi_awcache ( dram_dwidth_axi_awcache ), + .m_axi_awprot ( dram_dwidth_axi_awprot ), + .m_axi_awregion ( ), // left open + .m_axi_awqos ( dram_dwidth_axi_awqos ), + .m_axi_awvalid ( dram_dwidth_axi_awvalid ), + .m_axi_awready ( dram_dwidth_axi_awready ), + .m_axi_wdata ( dram_dwidth_axi_wdata ), + .m_axi_wstrb ( dram_dwidth_axi_wstrb ), + .m_axi_wlast ( dram_dwidth_axi_wlast ), + .m_axi_wvalid ( dram_dwidth_axi_wvalid ), + .m_axi_wready ( dram_dwidth_axi_wready ), + .m_axi_bresp ( dram_dwidth_axi_bresp ), + .m_axi_bvalid ( dram_dwidth_axi_bvalid ), + .m_axi_bready ( dram_dwidth_axi_bready ), + .m_axi_araddr ( dram_dwidth_axi_araddr ), + .m_axi_arlen ( dram_dwidth_axi_arlen ), + .m_axi_arsize ( dram_dwidth_axi_arsize ), + .m_axi_arburst ( dram_dwidth_axi_arburst ), + .m_axi_arlock ( dram_dwidth_axi_arlock ), + .m_axi_arcache ( dram_dwidth_axi_arcache ), + .m_axi_arprot ( dram_dwidth_axi_arprot ), + .m_axi_arregion ( ), + .m_axi_arqos ( dram_dwidth_axi_arqos ), + .m_axi_arvalid ( dram_dwidth_axi_arvalid ), + .m_axi_arready ( dram_dwidth_axi_arready ), + .m_axi_rdata ( dram_dwidth_axi_rdata ), + .m_axi_rresp ( dram_dwidth_axi_rresp ), + .m_axi_rlast ( dram_dwidth_axi_rlast ), + .m_axi_rvalid ( dram_dwidth_axi_rvalid ), + .m_axi_rready ( dram_dwidth_axi_rready ) +); + + ddr4_0 i_ddr ( + .c0_init_calib_complete ( ), + .dbg_clk ( ), + .c0_sys_clk_p ( c0_sys_clk_p ), + .c0_sys_clk_n ( c0_sys_clk_n ), + .dbg_bus ( ), + .c0_ddr4_adr ( c0_ddr4_adr ), + .c0_ddr4_ba ( c0_ddr4_ba ), + .c0_ddr4_cke ( c0_ddr4_cke ), + .c0_ddr4_cs_n ( c0_ddr4_cs_n ), + .c0_ddr4_dm_dbi_n ( c0_ddr4_dm_dbi_n ), + .c0_ddr4_dq ( c0_ddr4_dq ), + .c0_ddr4_dqs_c ( c0_ddr4_dqs_c ), + .c0_ddr4_dqs_t ( c0_ddr4_dqs_t ), + .c0_ddr4_odt ( c0_ddr4_odt ), + .c0_ddr4_bg ( c0_ddr4_bg ), + .c0_ddr4_reset_n ( c0_ddr4_reset_n ), + .c0_ddr4_act_n ( c0_ddr4_act_n ), + .c0_ddr4_ck_c ( c0_ddr4_ck_c ), + .c0_ddr4_ck_t ( c0_ddr4_ck_t ), + .c0_ddr4_ui_clk ( ddr_clock_out ), + .c0_ddr4_ui_clk_sync_rst( ddr_sync_reset ), + .c0_ddr4_aresetn ( ndmreset_n ), + .c0_ddr4_s_axi_awid ( '0 ), + .c0_ddr4_s_axi_awaddr ( dram_dwidth_axi_awaddr[30:0] ), + .c0_ddr4_s_axi_awlen ( dram_dwidth_axi_awlen ), + .c0_ddr4_s_axi_awsize ( dram_dwidth_axi_awsize ), + .c0_ddr4_s_axi_awburst ( dram_dwidth_axi_awburst ), + .c0_ddr4_s_axi_awlock ( dram_dwidth_axi_awlock ), + .c0_ddr4_s_axi_awcache ( dram_dwidth_axi_awcache ), + .c0_ddr4_s_axi_awprot ( dram_dwidth_axi_awprot ), + .c0_ddr4_s_axi_awqos ( dram_dwidth_axi_awqos ), + .c0_ddr4_s_axi_awvalid ( dram_dwidth_axi_awvalid ), + .c0_ddr4_s_axi_awready ( dram_dwidth_axi_awready ), + .c0_ddr4_s_axi_wdata ( dram_dwidth_axi_wdata ), + .c0_ddr4_s_axi_wstrb ( dram_dwidth_axi_wstrb ), + .c0_ddr4_s_axi_wlast ( dram_dwidth_axi_wlast ), + .c0_ddr4_s_axi_wvalid ( dram_dwidth_axi_wvalid ), + .c0_ddr4_s_axi_wready ( dram_dwidth_axi_wready ), + .c0_ddr4_s_axi_bready ( dram_dwidth_axi_bready ), + .c0_ddr4_s_axi_bid ( ), + .c0_ddr4_s_axi_bresp ( dram_dwidth_axi_bresp ), + .c0_ddr4_s_axi_bvalid ( dram_dwidth_axi_bvalid ), + .c0_ddr4_s_axi_arid ( '0 ), + .c0_ddr4_s_axi_araddr ( dram_dwidth_axi_araddr[30:0] ), + .c0_ddr4_s_axi_arlen ( dram_dwidth_axi_arlen ), + .c0_ddr4_s_axi_arsize ( dram_dwidth_axi_arsize ), + .c0_ddr4_s_axi_arburst ( dram_dwidth_axi_arburst ), + .c0_ddr4_s_axi_arlock ( dram_dwidth_axi_arlock ), + .c0_ddr4_s_axi_arcache ( dram_dwidth_axi_arcache ), + .c0_ddr4_s_axi_arprot ( dram_dwidth_axi_arprot ), + .c0_ddr4_s_axi_arqos ( dram_dwidth_axi_arqos ), + .c0_ddr4_s_axi_arvalid ( dram_dwidth_axi_arvalid ), + .c0_ddr4_s_axi_arready ( dram_dwidth_axi_arready ), + .c0_ddr4_s_axi_rready ( dram_dwidth_axi_rready ), + .c0_ddr4_s_axi_rlast ( dram_dwidth_axi_rlast ), + .c0_ddr4_s_axi_rvalid ( dram_dwidth_axi_rvalid ), + .c0_ddr4_s_axi_rresp ( dram_dwidth_axi_rresp ), + .c0_ddr4_s_axi_rid ( ), + .c0_ddr4_s_axi_rdata ( dram_dwidth_axi_rdata ), + .sys_rst ( cpu_reset ) + ); + + + logic pcie_ref_clk; + logic pcie_ref_clk_gt; + + logic pcie_axi_clk; + logic pcie_axi_rstn; + + logic pcie_axi_awready; + logic pcie_axi_wready; + logic [3:0] pcie_axi_bid; + logic [1:0] pcie_axi_bresp; + logic pcie_axi_bvalid; + logic pcie_axi_arready; + logic [3:0] pcie_axi_rid; + logic [255:0] pcie_axi_rdata; + logic [1:0] pcie_axi_rresp; + logic pcie_axi_rlast; + logic pcie_axi_rvalid; + logic [3:0] pcie_axi_awid; + logic [63:0] pcie_axi_awaddr; + logic [7:0] pcie_axi_awlen; + logic [2:0] pcie_axi_awsize; + logic [1:0] pcie_axi_awburst; + logic [2:0] pcie_axi_awprot; + logic pcie_axi_awvalid; + logic pcie_axi_awlock; + logic [3:0] pcie_axi_awcache; + logic [255:0] pcie_axi_wdata; + logic [31:0] pcie_axi_wstrb; + logic pcie_axi_wlast; + logic pcie_axi_wvalid; + logic pcie_axi_bready; + logic [3:0] pcie_axi_arid; + logic [63:0] pcie_axi_araddr; + logic [7:0] pcie_axi_arlen; + logic [2:0] pcie_axi_arsize; + logic [1:0] pcie_axi_arburst; + logic [2:0] pcie_axi_arprot; + logic pcie_axi_arvalid; + logic pcie_axi_arlock; + logic [3:0] pcie_axi_arcache; + logic pcie_axi_rready; + + logic [63:0] pcie_dwidth_axi_awaddr; + logic [7:0] pcie_dwidth_axi_awlen; + logic [2:0] pcie_dwidth_axi_awsize; + logic [1:0] pcie_dwidth_axi_awburst; + logic [0:0] pcie_dwidth_axi_awlock; + logic [3:0] pcie_dwidth_axi_awcache; + logic [2:0] pcie_dwidth_axi_awprot; + logic [3:0] pcie_dwidth_axi_awregion; + logic [3:0] pcie_dwidth_axi_awqos; + logic pcie_dwidth_axi_awvalid; + logic pcie_dwidth_axi_awready; + logic [63:0] pcie_dwidth_axi_wdata; + logic [7:0] pcie_dwidth_axi_wstrb; + logic pcie_dwidth_axi_wlast; + logic pcie_dwidth_axi_wvalid; + logic pcie_dwidth_axi_wready; + logic [1:0] pcie_dwidth_axi_bresp; + logic pcie_dwidth_axi_bvalid; + logic pcie_dwidth_axi_bready; + logic [63:0] pcie_dwidth_axi_araddr; + logic [7:0] pcie_dwidth_axi_arlen; + logic [2:0] pcie_dwidth_axi_arsize; + logic [1:0] pcie_dwidth_axi_arburst; + logic [0:0] pcie_dwidth_axi_arlock; + logic [3:0] pcie_dwidth_axi_arcache; + logic [2:0] pcie_dwidth_axi_arprot; + logic [3:0] pcie_dwidth_axi_arregion; + logic [3:0] pcie_dwidth_axi_arqos; + logic pcie_dwidth_axi_arvalid; + logic pcie_dwidth_axi_arready; + logic [63:0] pcie_dwidth_axi_rdata; + logic [1:0] pcie_dwidth_axi_rresp; + logic pcie_dwidth_axi_rlast; + logic pcie_dwidth_axi_rvalid; + logic pcie_dwidth_axi_rready; + + // PCIe Reset + logic sys_rst_n_c; + IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n)); + + IBUFDS_GTE4 #( + .REFCLK_HROW_CK_SEL ( 2'b00 ) + ) IBUFDS_GTE4_inst ( + .O ( pcie_ref_clk_gt ), + .ODIV2 ( pcie_ref_clk ), + .CEB ( 1'b0 ), + .I ( sys_clk_p ), + .IB ( sys_clk_n ) + ); + + // 250 MHz AXI + xdma_0 i_xdma ( + .sys_clk ( pcie_ref_clk ), + .sys_clk_gt ( pcie_ref_clk_gt ), + .sys_rst_n ( sys_rst_n_c ), + .user_lnk_up ( ), + + // Tx + .pci_exp_txp ( pci_exp_txp ), + .pci_exp_txn ( pci_exp_txn ), + // Rx + .pci_exp_rxp ( pci_exp_rxp ), + .pci_exp_rxn ( pci_exp_rxn ), + .usr_irq_req ( 1'b0 ), + .usr_irq_ack ( ), + .msi_enable ( ), + .msi_vector_width ( ), + .axi_aclk ( pcie_axi_clk ), + .axi_aresetn ( pcie_axi_rstn ), + .m_axi_awready ( pcie_axi_awready ), + .m_axi_wready ( pcie_axi_wready ), + .m_axi_bid ( pcie_axi_bid ), + .m_axi_bresp ( pcie_axi_bresp ), + .m_axi_bvalid ( pcie_axi_bvalid ), + .m_axi_arready ( pcie_axi_arready ), + .m_axi_rid ( pcie_axi_rid ), + .m_axi_rdata ( pcie_axi_rdata ), + .m_axi_rresp ( pcie_axi_rresp ), + .m_axi_rlast ( pcie_axi_rlast ), + .m_axi_rvalid ( pcie_axi_rvalid ), + .m_axi_awid ( pcie_axi_awid ), + .m_axi_awaddr ( pcie_axi_awaddr ), + .m_axi_awlen ( pcie_axi_awlen ), + .m_axi_awsize ( pcie_axi_awsize ), + .m_axi_awburst ( pcie_axi_awburst ), + .m_axi_awprot ( pcie_axi_awprot ), + .m_axi_awvalid ( pcie_axi_awvalid ), + .m_axi_awlock ( pcie_axi_awlock ), + .m_axi_awcache ( pcie_axi_awcache ), + .m_axi_wdata ( pcie_axi_wdata ), + .m_axi_wstrb ( pcie_axi_wstrb ), + .m_axi_wlast ( pcie_axi_wlast ), + .m_axi_wvalid ( pcie_axi_wvalid ), + .m_axi_bready ( pcie_axi_bready ), + .m_axi_arid ( pcie_axi_arid ), + .m_axi_araddr ( pcie_axi_araddr ), + .m_axi_arlen ( pcie_axi_arlen ), + .m_axi_arsize ( pcie_axi_arsize ), + .m_axi_arburst ( pcie_axi_arburst ), + .m_axi_arprot ( pcie_axi_arprot ), + .m_axi_arvalid ( pcie_axi_arvalid ), + .m_axi_arlock ( pcie_axi_arlock ), + .m_axi_arcache ( pcie_axi_arcache ), + .m_axi_rready ( pcie_axi_rready ), + + .cfg_mgmt_addr ( '0 ), + .cfg_mgmt_write ( '0 ), + .cfg_mgmt_write_data ( '0 ), + .cfg_mgmt_byte_enable ( '0 ), + .cfg_mgmt_read ( '0 ), + .cfg_mgmt_read_data ( ), + .cfg_mgmt_read_write_done ( ) + ); + + axi_dwidth_converter_256_64 i_axi_dwidth_converter_256_64 ( + .s_axi_aclk ( pcie_axi_clk ), + .s_axi_aresetn ( pcie_axi_rstn ), + .s_axi_awid ( pcie_axi_awid ), + .s_axi_awaddr ( pcie_axi_awaddr ), + .s_axi_awlen ( pcie_axi_awlen ), + .s_axi_awsize ( pcie_axi_awsize ), + .s_axi_awburst ( pcie_axi_awburst ), + .s_axi_awlock ( pcie_axi_awlock ), + .s_axi_awcache ( pcie_axi_awcache ), + .s_axi_awprot ( pcie_axi_awprot ), + .s_axi_awregion ( '0 ), + .s_axi_awqos ( '0 ), + .s_axi_awvalid ( pcie_axi_awvalid ), + .s_axi_awready ( pcie_axi_awready ), + .s_axi_wdata ( pcie_axi_wdata ), + .s_axi_wstrb ( pcie_axi_wstrb ), + .s_axi_wlast ( pcie_axi_wlast ), + .s_axi_wvalid ( pcie_axi_wvalid ), + .s_axi_wready ( pcie_axi_wready ), + .s_axi_bid ( pcie_axi_bid ), + .s_axi_bresp ( pcie_axi_rresp ), + .s_axi_bvalid ( pcie_axi_bvalid ), + .s_axi_bready ( pcie_axi_bready ), + .s_axi_arid ( pcie_axi_arid ), + .s_axi_araddr ( pcie_axi_araddr ), + .s_axi_arlen ( pcie_axi_arlen ), + .s_axi_arsize ( pcie_axi_arsize ), + .s_axi_arburst ( pcie_axi_arburst ), + .s_axi_arlock ( pcie_axi_arlock ), + .s_axi_arcache ( pcie_axi_arcache ), + .s_axi_arprot ( pcie_axi_arprot ), + .s_axi_arregion ( '0 ), + .s_axi_arqos ( '0 ), + .s_axi_arvalid ( pcie_axi_arvalid ), + .s_axi_arready ( pcie_axi_arready ), + .s_axi_rid ( pcie_axi_rid ), + .s_axi_rdata ( pcie_axi_rdata ), + .s_axi_rresp ( pcie_axi_bresp ), + .s_axi_rlast ( pcie_axi_rlast ), + .s_axi_rvalid ( pcie_axi_rvalid ), + .s_axi_rready ( pcie_axi_rready ), + + .m_axi_awaddr ( pcie_dwidth_axi_awaddr ), + .m_axi_awlen ( pcie_dwidth_axi_awlen ), + .m_axi_awsize ( pcie_dwidth_axi_awsize ), + .m_axi_awburst ( pcie_dwidth_axi_awburst ), + .m_axi_awlock ( pcie_dwidth_axi_awlock ), + .m_axi_awcache ( pcie_dwidth_axi_awcache ), + .m_axi_awprot ( pcie_dwidth_axi_awprot ), + .m_axi_awregion ( pcie_dwidth_axi_awregion ), + .m_axi_awqos ( pcie_dwidth_axi_awqos ), + .m_axi_awvalid ( pcie_dwidth_axi_awvalid ), + .m_axi_awready ( pcie_dwidth_axi_awready ), + .m_axi_wdata ( pcie_dwidth_axi_wdata ), + .m_axi_wstrb ( pcie_dwidth_axi_wstrb ), + .m_axi_wlast ( pcie_dwidth_axi_wlast ), + .m_axi_wvalid ( pcie_dwidth_axi_wvalid ), + .m_axi_wready ( pcie_dwidth_axi_wready ), + .m_axi_bresp ( pcie_dwidth_axi_bresp ), + .m_axi_bvalid ( pcie_dwidth_axi_bvalid ), + .m_axi_bready ( pcie_dwidth_axi_bready ), + .m_axi_araddr ( pcie_dwidth_axi_araddr ), + .m_axi_arlen ( pcie_dwidth_axi_arlen ), + .m_axi_arsize ( pcie_dwidth_axi_arsize ), + .m_axi_arburst ( pcie_dwidth_axi_arburst ), + .m_axi_arlock ( pcie_dwidth_axi_arlock ), + .m_axi_arcache ( pcie_dwidth_axi_arcache ), + .m_axi_arprot ( pcie_dwidth_axi_arprot ), + .m_axi_arregion ( pcie_dwidth_axi_arregion ), + .m_axi_arqos ( pcie_dwidth_axi_arqos ), + .m_axi_arvalid ( pcie_dwidth_axi_arvalid ), + .m_axi_arready ( pcie_dwidth_axi_arready ), + .m_axi_rdata ( pcie_dwidth_axi_rdata ), + .m_axi_rresp ( pcie_dwidth_axi_rresp ), + .m_axi_rlast ( pcie_dwidth_axi_rlast ), + .m_axi_rvalid ( pcie_dwidth_axi_rvalid ), + .m_axi_rready ( pcie_dwidth_axi_rready ) + ); + + +assign slave[1].aw_user = '0; +assign slave[1].ar_user = '0; +assign slave[1].w_user = '0; + +logic [3:0] slave_b_id; +logic [3:0] slave_r_id; + +assign slave[1].b_id = slave_b_id[1:0]; +assign slave[1].r_id = slave_r_id[1:0]; + +// PCIe Clock Converter +axi_clock_converter_0 pcie_axi_clock_converter ( + .m_axi_aclk ( clk ), + .m_axi_aresetn ( ndmreset_n ), + .m_axi_awid ( {2'b0, slave[1].aw_id} ), + .m_axi_awaddr ( slave[1].aw_addr ), + .m_axi_awlen ( slave[1].aw_len ), + .m_axi_awsize ( slave[1].aw_size ), + .m_axi_awburst ( slave[1].aw_burst ), + .m_axi_awlock ( slave[1].aw_lock ), + .m_axi_awcache ( slave[1].aw_cache ), + .m_axi_awprot ( slave[1].aw_prot ), + .m_axi_awregion ( slave[1].aw_region ), + .m_axi_awqos ( slave[1].aw_qos ), + .m_axi_awvalid ( slave[1].aw_valid ), + .m_axi_awready ( slave[1].aw_ready ), + .m_axi_wdata ( slave[1].w_data ), + .m_axi_wstrb ( slave[1].w_strb ), + .m_axi_wlast ( slave[1].w_last ), + .m_axi_wvalid ( slave[1].w_valid ), + .m_axi_wready ( slave[1].w_ready ), + .m_axi_bid ( slave_b_id ), + .m_axi_bresp ( slave[1].b_resp ), + .m_axi_bvalid ( slave[1].b_valid ), + .m_axi_bready ( slave[1].b_ready ), + .m_axi_arid ( {2'b0, slave[1].ar_id} ), + .m_axi_araddr ( slave[1].ar_addr ), + .m_axi_arlen ( slave[1].ar_len ), + .m_axi_arsize ( slave[1].ar_size ), + .m_axi_arburst ( slave[1].ar_burst ), + .m_axi_arlock ( slave[1].ar_lock ), + .m_axi_arcache ( slave[1].ar_cache ), + .m_axi_arprot ( slave[1].ar_prot ), + .m_axi_arregion ( slave[1].ar_region ), + .m_axi_arqos ( slave[1].ar_qos ), + .m_axi_arvalid ( slave[1].ar_valid ), + .m_axi_arready ( slave[1].ar_ready ), + .m_axi_rid ( slave_r_id ), + .m_axi_rdata ( slave[1].r_data ), + .m_axi_rresp ( slave[1].r_resp ), + .m_axi_rlast ( slave[1].r_last ), + .m_axi_rvalid ( slave[1].r_valid ), + .m_axi_rready ( slave[1].r_ready ), + // from size converter + .s_axi_aclk ( pcie_axi_clk ), + .s_axi_aresetn ( ndmreset_n ), + .s_axi_awid ( '0 ), + .s_axi_awaddr ( pcie_dwidth_axi_awaddr ), + .s_axi_awlen ( pcie_dwidth_axi_awlen ), + .s_axi_awsize ( pcie_dwidth_axi_awsize ), + .s_axi_awburst ( pcie_dwidth_axi_awburst ), + .s_axi_awlock ( pcie_dwidth_axi_awlock ), + .s_axi_awcache ( pcie_dwidth_axi_awcache ), + .s_axi_awprot ( pcie_dwidth_axi_awprot ), + .s_axi_awregion ( pcie_dwidth_axi_awregion ), + .s_axi_awqos ( pcie_dwidth_axi_awqos ), + .s_axi_awvalid ( pcie_dwidth_axi_awvalid ), + .s_axi_awready ( pcie_dwidth_axi_awready ), + .s_axi_wdata ( pcie_dwidth_axi_wdata ), + .s_axi_wstrb ( pcie_dwidth_axi_wstrb ), + .s_axi_wlast ( pcie_dwidth_axi_wlast ), + .s_axi_wvalid ( pcie_dwidth_axi_wvalid ), + .s_axi_wready ( pcie_dwidth_axi_wready ), + .s_axi_bid ( ), + .s_axi_bresp ( pcie_dwidth_axi_bresp ), + .s_axi_bvalid ( pcie_dwidth_axi_bvalid ), + .s_axi_bready ( pcie_dwidth_axi_bready ), + .s_axi_arid ( '0 ), + .s_axi_araddr ( pcie_dwidth_axi_araddr ), + .s_axi_arlen ( pcie_dwidth_axi_arlen ), + .s_axi_arsize ( pcie_dwidth_axi_arsize ), + .s_axi_arburst ( pcie_dwidth_axi_arburst ), + .s_axi_arlock ( pcie_dwidth_axi_arlock ), + .s_axi_arcache ( pcie_dwidth_axi_arcache ), + .s_axi_arprot ( pcie_dwidth_axi_arprot ), + .s_axi_arregion ( pcie_dwidth_axi_arregion ), + .s_axi_arqos ( pcie_dwidth_axi_arqos ), + .s_axi_arvalid ( pcie_dwidth_axi_arvalid ), + .s_axi_arready ( pcie_dwidth_axi_arready ), + .s_axi_rid ( ), + .s_axi_rdata ( pcie_dwidth_axi_rdata ), + .s_axi_rresp ( pcie_dwidth_axi_rresp ), + .s_axi_rlast ( pcie_dwidth_axi_rlast ), + .s_axi_rvalid ( pcie_dwidth_axi_rvalid ), + .s_axi_rready ( pcie_dwidth_axi_rready ) +); +`endif + +endmodule diff --git a/fpga/src/axi2apb b/fpga/src/axi2apb new file mode 160000 index 0000000000..53e7b9f1b1 --- /dev/null +++ b/fpga/src/axi2apb @@ -0,0 +1 @@ +Subproject commit 53e7b9f1b16e3f4d4aadc8fbf880d05879f54fe8 diff --git a/fpga/src/axi_slice b/fpga/src/axi_slice new file mode 160000 index 0000000000..aae8ca49dc --- /dev/null +++ b/fpga/src/axi_slice @@ -0,0 +1 @@ +Subproject commit aae8ca49dcfbfa8e44e1938a2e4a768db83006cb diff --git a/fpga/src/bootrom/.gitignore b/fpga/src/bootrom/.gitignore new file mode 100644 index 0000000000..7415b4bce3 --- /dev/null +++ b/fpga/src/bootrom/.gitignore @@ -0,0 +1,5 @@ +venv +*.elf +*.o +*.img +*.bin diff --git a/fpga/src/bootrom/Makefile b/fpga/src/bootrom/Makefile new file mode 100644 index 0000000000..91a46d07e5 --- /dev/null +++ b/fpga/src/bootrom/Makefile @@ -0,0 +1,54 @@ +CROSSCOMPILE ?= riscv64-unknown-elf- +CC = ${CROSSCOMPILE}gcc +PYTHON=python + +CFLAGS = -Os -ggdb -march=rv64imac -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs +CCASFLAGS = -mcmodel=medany -mexplicit-relocs +LDFLAGS = -nostdlib -nodefaultlibs -nostartfiles + +INCLUDES = -I./ -I./src + +SRCS_C = src/main.c src/uart.c src/spi.c src/sd.c src/gpt.c +SRCS_ASM = startup.S +OBJS_C = $(SRCS_C:.c=.o) +OBJS_S = $(SRCS_ASM:.S=.o) + +MAIN = bootrom.elf +MAIN_BIN = $(MAIN:.elf=.bin) +MAIN_IMG = $(MAIN:.elf=.img) +MAIN_SV = $(MAIN:.elf=.sv) + +#.PHONY: clean + +$(MAIN): ariane.dtb $(OBJS_C) $(OBJS_S) linker.lds + $(CC) $(CFLAGS) $(LDFLAGS) $(INCLUDES) -Tlinker.lds $(OBJS_S) $(OBJS_C) -o $(MAIN) + @echo "LD >= $(MAIN)" + +%.img: %.bin + dd if=$< of=$@ bs=128 + +%.bin: %.elf + $(CROSSCOMPILE)objcopy -O binary $< $@ + +%.o: %.c + @$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@ + @echo "CC <= $<" + +%.o: %.S + @$(CC) $(CFLAGS) $(CCASFLAGS) $(INCLUDES) -c $< -o $@ + @echo "CC <= $<" + +%.dtb: %.dts + dtc -I dts $< -O dtb -o $@ + +%.sv: %.img + $(PYTHON) ./gen_rom.py $< + @echo "PYTHON >= $(MAIN_SV)" + +clean: + $(RM) $(OBJS_C) $(OBJS_S) $(MAIN) $(MAIN_BIN) $(MAIN_IMG) *.dtb + +all: $(MAIN) $(MAIN_BIN) $(MAIN_IMG) $(MAIN_SV) + @echo "zero stage bootloader has been compiled!" + +# DO NOT DELETE THIS LINE -- make depend needs it \ No newline at end of file diff --git a/fpga/src/bootrom/README.md b/fpga/src/bootrom/README.md new file mode 100644 index 0000000000..1ae6e1a5f5 --- /dev/null +++ b/fpga/src/bootrom/README.md @@ -0,0 +1,33 @@ +# First Stage Bootloader for Ariane + +## How-To prepare SD card +The bootloader requires a GPT partition table so you first have to create one with gdisk. + +```bash +$ sudo fdisk -l # search for the corresponding disk label (e.g. /dev/sdb) +$ sudo sgdisk --clear --new=1:2048:67583 --new=2 --typecode=1:3000 --typecode=2:8300 /dev/sdb # create a new gpt partition table and two partitions: 1st partition: 32mb (ONIE boot), second partition: rest (Linux root) +``` + +Now you have to make the linux kernel with the [ariane-sdk](https://github.com/pulp-platform/ariane-sdk): +```bash +$ cd /path/to/ariane-sdk +$ make bbl.bin # make the linux kernel with the ariane-sdk repository +``` + +Then the bbl+linux kernel image can get copied to the sd card with `dd`. __Careful:__ use the same disk label that you found before with `fdisk -l` but with a 1 in the end, e.g. `/dev/sdb` -> `/dev/sdb1`. +```bash +$ sudo dd if=bbl.bin of=/dev/sdb1 status=progress oflag=sync bs=1M +``` + +## Features + +- uart +- spi +- sd card reading +- GPT partitions + +## TODO + +- file systems (fat16/fat32) +- elf loader +- zeroing of the `.bss` section of the second stage boot loader diff --git a/fpga/src/bootrom/ariane.dts b/fpga/src/bootrom/ariane.dts new file mode 100644 index 0000000000..997f4c8c0b --- /dev/null +++ b/fpga/src/bootrom/ariane.dts @@ -0,0 +1,156 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "eth,ariane-bare-dev"; + model = "eth,ariane-bare"; + chosen { + stdout-path = "/soc/uart@10000000:115200"; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; // 25 MHz + CPU0: cpu@0 { + clock-frequency = <50000000>; // 50 MHz + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "eth, ariane", "riscv"; + riscv,isa = "rv64imacsu"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x8000000>; + }; + leds { + compatible = "gpio-leds"; + heartbeat-led { + gpios = <&xlnx_gpio 1 0>; + linux,default-trigger = "heartbeat"; + retain-state-suspended; + }; + }; + L26: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "eth,ariane-bare-soc", "simple-bus"; + ranges; + clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>; + reg = <0x0 0x2000000 0x0 0xc0000>; + reg-names = "control"; + }; + PLIC0: interrupt-controller@c000000 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <3>; + }; + debug-controller@0 { + compatible = "riscv,debug-013"; + interrupts-extended = <&CPU0_intc 65535>; + reg = <0x0 0x0 0x0 0x1000>; + reg-names = "control"; + }; + uart@10000000 { + compatible = "ns16750"; + reg = <0x0 0x10000000 0x0 0x1000>; + clock-frequency = <50000000>; + current-speed = <115200>; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <2>; // regs are spaced on 32 bit boundary + reg-io-width = <4>; // only 32-bit access are supported + }; + xps-spi@20000000 { + compatible = "xlnx,xps-spi-2.00.b", "xlnx,xps-spi-2.00.a"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&PLIC0>; + interrupts = < 2 2 >; + reg = < 0x0 0x20000000 0x0 0x1000 >; + xlnx,family = "kintex7"; + xlnx,fifo-exist = <0x1>; + xlnx,num-ss-bits = <0x1>; + xlnx,num-transfer-bits = <0x8>; + xlnx,sck-ratio = <0x4>; + + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <12500000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; + + // mmc-slot@0 { + // compatible = "fsl,mpc8323rdb-mmc-slot", "mmc-spi-slot"; + // reg = <0>; //Chip select 0 + // spi-max-frequency = <12500000>; + // voltage-ranges = <3300 3300>; + // //interrupts = < 2 2 >; + // //interrupt-parent = <&PLIC0>; + // }; + }; + xlnx_axi_ethernetlite: ethernet@30000000 { + compatible = "xlnx,axi-ethernetlite-3.0", "xlnx,xps-ethernetlite-1.00.a"; + device_type = "network"; + interrupt-parent = <&PLIC0>; + interrupts = <3 0>; + local-mac-address = [00 0a 35 00 01 22]; + phy-handle = <&phy0>; + reg = <0x0 0x30000000 0x0 0x10000>; + xlnx,duplex = <0x1>; + xlnx,include-global-buffers = <0x1>; + xlnx,include-internal-loopback = <0x0>; + xlnx,include-mdio = <0x1>; + xlnx,instance = "i_xlnx_axi_ethernetlite"; + xlnx,rx-ping-pong = <0x1>; + xlnx,s-axi-id-width = <0x4>; + xlnx,tx-ping-pong = <0x1>; + xlnx,use-internal = <0x0>; + xlnx,has-mdio = <0x1>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: axi_ethernetlite_0_mdio@1 { + compatible = "ethernet-phy-id001C.C915"; + device_type = "network"; + reg = <0x1>; + }; + }; + }; + xlnx_gpio: gpio@40000000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x40000000 0x0 0x10000 >; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x8>; + xlnx,gpio2-width = <0x8>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + }; + }; +}; diff --git a/fpga/src/bootrom/bootrom.h b/fpga/src/bootrom/bootrom.h new file mode 100644 index 0000000000..507e10896e --- /dev/null +++ b/fpga/src/bootrom/bootrom.h @@ -0,0 +1,1890 @@ +// Auto-generated code + +const int reset_vec_size = 1884; + +uint32_t reset_vec[reset_vec_size] = { + 0x00800913, + 0x30491073, + 0x00000493, + 0xf1402973, + 0x03249663, + 0x0210011b, + 0x01a11113, + 0x221000ef, + 0x020004b7, + 0x00100913, + 0x0124a023, + 0x00448493, + 0x02000937, + 0x4009091b, + 0xff24c6e3, + 0x10500073, + 0x34402973, + 0x00897913, + 0xfe090ae3, + 0x020004b7, + 0xf1402973, + 0x00291913, + 0x00990933, + 0x00092023, + 0x0004a903, + 0xfe091ee3, + 0x00448493, + 0x02000937, + 0x4009091b, + 0xff24c6e3, + 0xf1402573, + 0x00001597, + 0xb8458593, + 0x0010049b, + 0x01f49493, + 0x00048067, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00238082, + 0x808200b5, + 0x00054503, + 0x07b78082, + 0xc5031000, + 0x75130147, + 0x80820205, + 0x10000737, + 0x01474783, + 0x0207f793, + 0x0023dfe5, + 0x808200a7, + 0x100007b7, + 0x00078223, + 0xf8000713, + 0x00e78623, + 0x8023476d, + 0x822300e7, + 0x470d0007, + 0x00e78623, + 0xfc700713, + 0x00e78423, + 0x02000713, + 0x00e78823, + 0x11418082, + 0xe406e022, + 0x4503842a, + 0xe5090004, + 0x640260a2, + 0x80820141, + 0xfa5ff0ef, + 0xb7f50405, + 0x00001797, + 0x98078793, + 0x00f57713, + 0x4703973e, + 0x81110007, + 0x80a397aa, + 0xc78300e5, + 0x80230007, + 0x808200f5, + 0xf0227179, + 0xe84aec26, + 0x892af406, + 0x54e14461, + 0x0089553b, + 0x7513002c, + 0xf0ef0ff5, + 0x4503fc3f, + 0x34610081, + 0xf55ff0ef, + 0x00914503, + 0xf4dff0ef, + 0xfe9410e3, + 0x740270a2, + 0x694264e2, + 0x80826145, + 0xf0227179, + 0xe84aec26, + 0x892af406, + 0x03800413, + 0x553354e1, + 0x002c0089, + 0x0ff57513, + 0xf81ff0ef, + 0x00814503, + 0xf0ef3461, + 0x4503f13f, + 0xf0ef0091, + 0x10e3f0bf, + 0x70a2fe94, + 0x64e27402, + 0x61456942, + 0x11018082, + 0xec06002c, + 0xf55ff0ef, + 0x00814503, + 0xee9ff0ef, + 0x00914503, + 0xee1ff0ef, + 0x610560e2, + 0xc10c8082, + 0x41088082, + 0x25178082, + 0x11010000, + 0x84a50513, + 0xe822ec06, + 0xf0efe426, + 0x07b7f05f, + 0x47292000, + 0x47a9c3b8, + 0x37fd0001, + 0x0437fff5, + 0x07932000, + 0xd03c1040, + 0x25175064, + 0x05130000, + 0xf0ef82a5, + 0x2481eddf, + 0x02049513, + 0xf0ef9101, + 0x2517f53f, + 0x05130000, + 0xf0ef8325, + 0x0793ec5f, + 0xd03c1660, + 0x15175064, + 0x05130000, + 0xf0ef7fe5, + 0x2481eb1f, + 0x02049513, + 0xf0ef9101, + 0x2517f27f, + 0x05130000, + 0xf0ef8065, + 0x4799e99f, + 0x6442d03c, + 0x64a260e2, + 0x00001517, + 0x7e050513, + 0xf06f6105, + 0x1101e81f, + 0x200007b7, + 0xe822ec06, + 0x5779e426, + 0xd7a8dbb8, + 0x06400793, + 0x37fd0001, + 0x07b7fff5, + 0x07132000, + 0xd3b81060, + 0x849353f8, + 0x8b050647, + 0x57e0ff65, + 0x240153fc, + 0xe3958b85, + 0x00001517, + 0x7b050513, + 0xe3bff0ef, + 0x15024088, + 0xf0ef9101, + 0x1517eb3f, + 0x05130000, + 0xf0ef7925, + 0x07b7e25f, + 0x577d2000, + 0x0ff47513, + 0x644260e2, + 0x4719dbb8, + 0x64a2d3b8, + 0x80826105, + 0x10000793, + 0x06b7ec63, + 0x200007b7, + 0xdbb85779, + 0x200006b7, + 0x873b87aa, + 0x616340a7, + 0x079304b7, + 0x00010320, + 0xfff537fd, + 0x10600713, + 0x200007b7, + 0x0737d3b8, + 0x537c2000, + 0xfff58b85, + 0x20000537, + 0x20000837, + 0x0007869b, + 0x00b6ef63, + 0x200007b7, + 0xdbb8577d, + 0xd3b84719, + 0x80824501, + 0x0007c703, + 0xd6b80785, + 0x5178bf4d, + 0xff798b05, + 0x06c82683, + 0x00f60733, + 0x00230785, + 0xb7e900d7, + 0x8082557d, + 0x0ff00513, + 0xf07ff06f, + 0xf4067179, + 0xf022e432, + 0x842eec26, + 0xf0ef84aa, + 0xe513febf, + 0xf0ef0404, + 0x551beedf, + 0x75130184, + 0xf0ef0ff5, + 0x551bee1f, + 0x75130104, + 0xf0ef0ff5, + 0x551bed5f, + 0x75130084, + 0xf0ef0ff5, + 0x7513ec9f, + 0xf0ef0ff4, + 0x6622ec1f, + 0x06400413, + 0xf0ef8532, + 0xf0efeb5f, + 0x179bfa7f, + 0xd79b0185, + 0xd4634187, + 0x147d0007, + 0x70a2f47d, + 0x64e27402, + 0x80826145, + 0xe8221101, + 0x1517842a, + 0x05130000, + 0xec0668e5, + 0xf0efe42e, + 0x8522cfdf, + 0xcf7ff0ef, + 0x00001517, + 0x68850513, + 0xcebff0ef, + 0x852e65a2, + 0xda7ff0ef, + 0x60e26442, + 0x00001517, + 0x64050513, + 0xf06f6105, + 0x1101cd1f, + 0x6409e822, + 0xec06e426, + 0x0413e04a, + 0x44857104, + 0x09500613, + 0x45014581, + 0xf35ff0ef, + 0x892a347d, + 0xf25ff0ef, + 0x15e3c00d, + 0x1517fe99, + 0x05130000, + 0x45856465, + 0xf89ff0ef, + 0x60e24505, + 0x64a26442, + 0x61056902, + 0x45018082, + 0x1101bfcd, + 0x08700613, + 0x1aa00593, + 0xec064521, + 0xe426e822, + 0xf0efe04a, + 0x892aeeff, + 0xee1ff0ef, + 0xeddff0ef, + 0xed9ff0ef, + 0xf0ef84aa, + 0x842aed3f, + 0xecdff0ef, + 0xec9ff0ef, + 0x45014785, + 0x00f91b63, + 0x986388bd, + 0x051b0124, + 0x05130004, + 0x3513f565, + 0x60e20015, + 0x64a26442, + 0x61056902, + 0x11418082, + 0x06500613, + 0x05134581, + 0xe4060370, + 0xf0efe022, + 0x842ae97f, + 0xe89ff0ef, + 0x00001517, + 0x051385a2, + 0xf0ef5b85, + 0x051bef3f, + 0x60a20004, + 0x157d6402, + 0x00153513, + 0x80820141, + 0xe4261101, + 0xe822ec06, + 0xf0ef4485, + 0x0613fbdf, + 0x05b70770, + 0x05134000, + 0xf0ef0290, + 0x842ae53f, + 0x151785aa, + 0x05130000, + 0xf0ef57e5, + 0xf0efeb3f, + 0x0ce3e37f, + 0x051bfc94, + 0x60e20004, + 0x64a26442, + 0x00153513, + 0x80826105, + 0xe4061141, + 0xf0efe022, + 0x1517c89f, + 0x05130000, + 0xf0ef5565, + 0x4429b91f, + 0xf0ef347d, + 0xfc6de03f, + 0xeb7ff0ef, + 0xc91157fd, + 0xefbff0ef, + 0xc51157f9, + 0xf89ff0ef, + 0xc11157f5, + 0x60a24781, + 0x853e6402, + 0x80820141, + 0xd79b8de9, + 0xd51b0075, + 0x8d3d0045, + 0x15938d2d, + 0x8d2d0045, + 0x07f57513, + 0x579b8082, + 0x05220085, + 0x15428d5d, + 0x8da99141, + 0x0045d51b, + 0x8da9893d, + 0x00c59513, + 0x151b8d2d, + 0x551b0105, + 0x179b4105, + 0xd79b0105, + 0x67090107, + 0x979b1701, + 0x8ff90057, + 0x15428d3d, + 0x80829141, + 0xe1a27155, + 0xf94afd26, + 0xe58684b2, + 0xf152f54e, + 0xe95aed56, + 0x892ae55e, + 0x4781842e, + 0x0713567d, + 0x06b30800, + 0x802300f1, + 0x078500c6, + 0xfee79be3, + 0x0184559b, + 0x0ff5f593, + 0xf0ef4501, + 0x559bf6ff, + 0xf5930104, + 0xf0ef0ff5, + 0x559bf63f, + 0xf5930084, + 0xf0ef0ff5, + 0x7593f57f, + 0xf0ef0ff4, + 0x161bf4ff, + 0x66130015, + 0x76130016, + 0x85a20ff6, + 0xf0ef4549, + 0xc501d1bf, + 0xd0dff0ef, + 0x1482bff5, + 0x0a139081, + 0x0a930fe0, + 0xf0ef3e80, + 0x1ee3cfbf, + 0x0b13ff45, + 0x844a2009, + 0x86224981, + 0x04000593, + 0xf0ef850a, + 0x4901c63f, + 0x04000b93, + 0x012407b3, + 0x0007c583, + 0x0905854e, + 0xf0fff0ef, + 0x17e389aa, + 0x0413ff79, + 0x1ae30404, + 0xf0effd64, + 0x151bcbbf, + 0x89220085, + 0x03051413, + 0xf0ef9041, + 0x8c49cabf, + 0x90411442, + 0x12632981, + 0xe7b30534, + 0xe7990354, + 0x00001517, + 0x3f050513, + 0xa13ff0ef, + 0x46e314fd, + 0x4401f890, + 0x45814605, + 0xf0ef4531, + 0xf0efc83f, + 0x8522c77f, + 0x640e60ae, + 0x794a74ea, + 0x7a0a79aa, + 0x6b4a6aea, + 0x61696baa, + 0x54798082, + 0x715dbfe1, + 0xf052e0a2, + 0xe486e85a, + 0xf84afc26, + 0xec56f44e, + 0xe062e45e, + 0x8a2a0880, + 0xf0ef8b2e, + 0xc51de1ff, + 0x00001517, + 0x39850513, + 0x9b3ff0ef, + 0x011354fd, + 0x60a6fb04, + 0x64068526, + 0x794274e2, + 0x7a0279a2, + 0x6b426ae2, + 0x6c026ba2, + 0x80826161, + 0x00001517, + 0x39450513, + 0x987ff0ef, + 0x46057101, + 0x850a4585, + 0xe75ff0ef, + 0x84aa890a, + 0x1517c905, + 0x05130000, + 0xf0ef38e5, + 0x1517969f, + 0x05130000, + 0xf0ef39a5, + 0x852695df, + 0x9d9ff0ef, + 0x00001517, + 0x2b850513, + 0x94bff0ef, + 0xbf6154f9, + 0x00001517, + 0x39050513, + 0x93bff0ef, + 0x00001517, + 0x3a450513, + 0x92fff0ef, + 0x4b916502, + 0x9a9ff0ef, + 0x00001517, + 0x3a050513, + 0x91bff0ef, + 0xf0ef4522, + 0x1517957f, + 0x05130000, + 0xf0ef39e5, + 0x4532909f, + 0x945ff0ef, + 0x00001517, + 0x39c50513, + 0x8f7ff0ef, + 0xf0ef4542, + 0x1517933f, + 0x05130000, + 0xf0ef39a5, + 0x45528e5f, + 0x921ff0ef, + 0x00001517, + 0x39850513, + 0x8d3ff0ef, + 0xf0ef6562, + 0x151794ff, + 0x05130000, + 0xf0ef39e5, + 0x75028c1f, + 0x93dff0ef, + 0x00001517, + 0x39c50513, + 0x8afff0ef, + 0xf0ef6526, + 0x151792bf, + 0x05130000, + 0xf0ef3aa5, + 0x454689df, + 0x8d9ff0ef, + 0x00001517, + 0x3b850513, + 0x88bff0ef, + 0xf0ef4556, + 0x15178c7f, + 0x05130000, + 0xf0ef1e65, + 0x2583879f, + 0x71010489, + 0x850a4605, + 0xd65ff0ef, + 0x89aa8a8a, + 0xc50d0804, + 0x00001517, + 0x27c50513, + 0x857ff0ef, + 0x00001517, + 0x28850513, + 0x84bff0ef, + 0xf0ef854e, + 0x15178c7f, + 0x05130000, + 0xb5fd1a65, + 0x00001517, + 0x37c50513, + 0x82fff0ef, + 0x0ff9f513, + 0x8ebff0ef, + 0x00001517, + 0x38050513, + 0x81bff0ef, + 0xff048913, + 0x00094503, + 0xf0ef0905, + 0x1be38d1f, + 0x1517fe99, + 0x05130000, + 0xf0ef3825, + 0x0c13ffcf, + 0x45030109, + 0x09050009, + 0x8b3ff0ef, + 0xff2c1be3, + 0x00001517, + 0x38450513, + 0xfdeff0ef, + 0x89136888, + 0x8c130284, + 0xf0ef0704, + 0x1517853f, + 0x05130000, + 0xf0ef37a5, + 0x6c88fc4f, + 0x841ff0ef, + 0x00001517, + 0x37850513, + 0xfb2ff0ef, + 0xf0ef7088, + 0x151782ff, + 0x05130000, + 0xf0ef3765, + 0x4503fa0f, + 0x09050009, + 0x85bff0ef, + 0xff2c1be3, + 0x00001517, + 0x0f450513, + 0xf0ef2985, + 0x8493f84f, + 0x93e30804, + 0x1517f579, + 0x05130000, + 0xf0ef3565, + 0xa583f70f, + 0x865a020a, + 0xf0ef8552, + 0x84aac5ff, + 0x1517c50d, + 0x05130000, + 0xf0ef17a5, + 0x1517f54f, + 0x05130000, + 0xf0ef1865, + 0x8526f48f, + 0xfc4ff0ef, + 0x00001517, + 0x0a450513, + 0x1517b3f5, + 0x05130000, + 0xf0ef32a5, + 0xbbb5f2cf, + 0xe4061141, + 0xef0ff0ef, + 0x00001517, + 0x04450513, + 0xf16ff0ef, + 0x65a14505, + 0xf0ef057e, + 0xe911d31f, + 0x0010041b, + 0x01f41413, + 0x00000597, + 0x19c58593, + 0xa0018402, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x33323130, + 0x37363534, + 0x42413938, + 0x46454443, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xedfe0dd0, + 0x860e0000, + 0x38000000, + 0xe40a0000, + 0x28000000, + 0x11000000, + 0x10000000, + 0x00000000, + 0xa2030000, + 0xac0a0000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01000000, + 0x00000000, + 0x03000000, + 0x04000000, + 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0x69756720, + 0x20203a64, + 0x09202020, + 0x00000000, + 0x00000000, + 0x66090a0d, + 0x74737269, + 0x61626c20, + 0x0000093a, + 0x6c090a0d, + 0x20747361, + 0x3a61626c, + 0x00000009, + 0x61090a0d, + 0x69727474, + 0x65747562, + 0x00093a73, + 0x6e090a0d, + 0x3a656d61, + 0x00000009, + 0x00000000, + 0x79706f63, + 0x20676e69, + 0x746f6f62, + 0x616d6920, + 0x00206567, + 0x00000000, + 0x6e6f6420, + 0x0a0d2165, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; diff --git a/fpga/src/bootrom/bootrom.sv b/fpga/src/bootrom/bootrom.sv new file mode 100644 index 0000000000..ac893c64b5 --- /dev/null +++ b/fpga/src/bootrom/bootrom.sv @@ -0,0 +1,981 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: $filename.v + * + * Description: Auto-generated bootrom + */ + +// Auto-generated code +module bootrom ( + input logic clk_i, + input logic req_i, + input logic [63:0] addr_i, + output logic [63:0] rdata_o +); + localparam int RomSize = 942; + + const logic [RomSize-1:0][63:0] mem = { + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h0a0d2165_6e6f6420, + 64'h00000000_00206567, + 64'h616d6920_746f6f62, + 64'h20676e69_79706f63, + 64'h00000000_00000009, + 64'h3a656d61_6e090a0d, + 64'h00093a73_65747562, + 64'h69727474_61090a0d, + 64'h00000009_3a61626c, + 64'h20747361_6c090a0d, + 64'h0000093a_61626c20, + 64'h74737269_66090a0d, + 64'h00000000_00000000, + 64'h09202020_20203a64, + 64'h69756720_6e6f6974, + 64'h69747261_70090a0d, + 64'h00000000_00000000, + 64'h093a6469_75672065, + 64'h70797420_6e6f6974, + 64'h69747261_70090a0d, + 64'h00000000_20797274, + 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64'ha583f70f_f0ef3565, + 64'h05130000_1517f579, + 64'h93e30804_8493f84f, + 64'hf0ef2985_0f450513, + 64'h00001517_ff2c1be3, + 64'h85bff0ef_09050009, + 64'h4503fa0f_f0ef3765, + 64'h05130000_151782ff, + 64'hf0ef7088_fb2ff0ef, + 64'h37850513_00001517, + 64'h841ff0ef_6c88fc4f, + 64'hf0ef37a5_05130000, + 64'h1517853f_f0ef0704, + 64'h8c130284_89136888, + 64'hfdeff0ef_38450513, + 64'h00001517_ff2c1be3, + 64'h8b3ff0ef_09050009, + 64'h45030109_0c13ffcf, + 64'hf0ef3825_05130000, + 64'h1517fe99_1be38d1f, + 64'hf0ef0905_00094503, + 64'hff048913_81bff0ef, + 64'h38050513_00001517, + 64'h8ebff0ef_0ff9f513, + 64'h82fff0ef_37c50513, + 64'h00001517_b5fd1a65, + 64'h05130000_15178c7f, + 64'hf0ef854e_84bff0ef, + 64'h28850513_00001517, + 64'h857ff0ef_27c50513, + 64'h00001517_c50d0804, + 64'h89aa8a8a_d65ff0ef, + 64'h850a4605_71010489, + 64'h2583879f_f0ef1e65, + 64'h05130000_15178c7f, + 64'hf0ef4556_88bff0ef, + 64'h3b850513_00001517, + 64'h8d9ff0ef_454689df, + 64'hf0ef3aa5_05130000, + 64'h151792bf_f0ef6526, + 64'h8afff0ef_39c50513, + 64'h00001517_93dff0ef, + 64'h75028c1f_f0ef39e5, + 64'h05130000_151794ff, + 64'hf0ef6562_8d3ff0ef, + 64'h39850513_00001517, + 64'h921ff0ef_45528e5f, + 64'hf0ef39a5_05130000, + 64'h1517933f_f0ef4542, + 64'h8f7ff0ef_39c50513, + 64'h00001517_945ff0ef, + 64'h4532909f_f0ef39e5, + 64'h05130000_1517957f, + 64'hf0ef4522_91bff0ef, + 64'h3a050513_00001517, + 64'h9a9ff0ef_4b916502, + 64'h92fff0ef_3a450513, + 64'h00001517_93bff0ef, + 64'h39050513_00001517, + 64'hbf6154f9_94bff0ef, + 64'h2b850513_00001517, + 64'h9d9ff0ef_852695df, + 64'hf0ef39a5_05130000, + 64'h1517969f_f0ef38e5, + 64'h05130000_1517c905, + 64'h84aa890a_e75ff0ef, + 64'h850a4585_46057101, + 64'h987ff0ef_39450513, + 64'h00001517_80826161, + 64'h6c026ba2_6b426ae2, + 64'h7a0279a2_794274e2, + 64'h64068526_60a6fb04, + 64'h011354fd_9b3ff0ef, + 64'h39850513_00001517, + 64'hc51de1ff_f0ef8b2e, + 64'h8a2a0880_e062e45e, + 64'hec56f44e_f84afc26, + 64'he486e85a_f052e0a2, + 64'h715dbfe1_54798082, + 64'h61696baa_6b4a6aea, + 64'h7a0a79aa_794a74ea, + 64'h640e60ae_8522c77f, + 64'hf0efc83f_f0ef4531, + 64'h45814605_4401f890, + 64'h46e314fd_a13ff0ef, + 64'h3f050513_00001517, + 64'he7990354_e7b30534, + 64'h12632981_90411442, + 64'h8c49cabf_f0ef9041, + 64'h03051413_89220085, + 64'h151bcbbf_f0effd64, + 64'h1ae30404_0413ff79, + 64'h17e389aa_f0fff0ef, + 64'h0905854e_0007c583, + 64'h012407b3_04000b93, + 64'h4901c63f_f0ef850a, + 64'h04000593_86224981, + 64'h844a2009_0b13ff45, + 64'h1ee3cfbf_f0ef3e80, + 64'h0a930fe0_0a139081, + 64'h1482bff5_d0dff0ef, + 64'hc501d1bf_f0ef4549, + 64'h85a20ff6_76130016, + 64'h66130015_161bf4ff, + 64'hf0ef0ff4_7593f57f, + 64'hf0ef0ff5_f5930084, + 64'h559bf63f_f0ef0ff5, + 64'hf5930104_559bf6ff, + 64'hf0ef4501_0ff5f593, + 64'h0184559b_fee79be3, + 64'h078500c6_802300f1, + 64'h06b30800_0713567d, + 64'h4781842e_892ae55e, + 64'he95aed56_f152f54e, + 64'he58684b2_f94afd26, + 64'he1a27155_80829141, + 64'h15428d3d_8ff90057, + 64'h979b1701_67090107, + 64'hd79b0105_179b4105, + 64'h551b0105_151b8d2d, + 64'h00c59513_8da9893d, + 64'h0045d51b_8da99141, + 64'h15428d5d_05220085, + 64'h579b8082_07f57513, + 64'h8d2d0045_15938d2d, + 64'h8d3d0045_d51b0075, + 64'hd79b8de9_80820141, + 64'h853e6402_60a24781, + 64'hc11157f5_f89ff0ef, + 64'hc51157f9_efbff0ef, + 64'hc91157fd_eb7ff0ef, + 64'hfc6de03f_f0ef347d, + 64'h4429b91f_f0ef5565, + 64'h05130000_1517c89f, + 64'hf0efe022_e4061141, + 64'h80826105_00153513, + 64'h64a26442_60e20004, + 64'h051bfc94_0ce3e37f, + 64'hf0efeb3f_f0ef57e5, + 64'h05130000_151785aa, + 64'h842ae53f_f0ef0290, + 64'h05134000_05b70770, + 64'h0613fbdf_f0ef4485, + 64'he822ec06_e4261101, + 64'h80820141_00153513, + 64'h157d6402_60a20004, + 64'h051bef3f_f0ef5b85, + 64'h051385a2_00001517, + 64'he89ff0ef_842ae97f, + 64'hf0efe022_e4060370, + 64'h05134581_06500613, + 64'h11418082_61056902, + 64'h64a26442_60e20015, + 64'h3513f565_05130004, + 64'h051b0124_986388bd, + 64'h00f91b63_45014785, + 64'hec9ff0ef_ecdff0ef, + 64'h842aed3f_f0ef84aa, + 64'hed9ff0ef_eddff0ef, + 64'hee1ff0ef_892aeeff, + 64'hf0efe04a_e426e822, + 64'hec064521_1aa00593, + 64'h08700613_1101bfcd, + 64'h45018082_61056902, + 64'h64a26442_60e24505, + 64'hf89ff0ef_45856465, + 64'h05130000_1517fe99, + 64'h15e3c00d_f25ff0ef, + 64'h892a347d_f35ff0ef, + 64'h45014581_09500613, + 64'h44857104_0413e04a, + 64'hec06e426_6409e822, + 64'h1101cd1f_f06f6105, + 64'h64050513_00001517, + 64'h60e26442_da7ff0ef, + 64'h852e65a2_cebff0ef, + 64'h68850513_00001517, + 64'hcf7ff0ef_8522cfdf, + 64'hf0efe42e_ec0668e5, + 64'h05130000_1517842a, + 64'he8221101_80826145, + 64'h64e27402_70a2f47d, + 64'h147d0007_d4634187, + 64'hd79b0185_179bfa7f, + 64'hf0efeb5f_f0ef8532, + 64'h06400413_6622ec1f, + 64'hf0ef0ff4_7513ec9f, + 64'hf0ef0ff5_75130084, + 64'h551bed5f_f0ef0ff5, + 64'h75130104_551bee1f, + 64'hf0ef0ff5_75130184, + 64'h551beedf_f0ef0404, + 64'he513febf_f0ef84aa, + 64'h842eec26_f022e432, + 64'hf4067179_f07ff06f, + 64'h0ff00513_8082557d, + 64'hb7e900d7_00230785, + 64'h00f60733_06c82683, + 64'hff798b05_5178bf4d, + 64'hd6b80785_0007c703, + 64'h80824501_d3b84719, + 64'hdbb8577d_200007b7, + 64'h00b6ef63_0007869b, + 64'h20000837_20000537, + 64'hfff58b85_537c2000, + 64'h0737d3b8_200007b7, + 64'h10600713_fff537fd, + 64'h00010320_079304b7, + 64'h616340a7_873b87aa, + 64'h200006b7_dbb85779, + 64'h200007b7_06b7ec63, + 64'h10000793_80826105, + 64'h64a2d3b8_4719dbb8, + 64'h644260e2_0ff47513, + 64'h577d2000_07b7e25f, + 64'hf0ef7925_05130000, + 64'h1517eb3f_f0ef9101, + 64'h15024088_e3bff0ef, + 64'h7b050513_00001517, + 64'he3958b85_240153fc, + 64'h57e0ff65_8b050647, + 64'h849353f8_d3b81060, + 64'h07132000_07b7fff5, + 64'h37fd0001_06400793, + 64'hd7a8dbb8_5779e426, + 64'he822ec06_200007b7, + 64'h1101e81f_f06f6105, + 64'h7e050513_00001517, + 64'h64a260e2_6442d03c, + 64'h4799e99f_f0ef8065, + 64'h05130000_2517f27f, + 64'hf0ef9101_02049513, + 64'h2481eb1f_f0ef7fe5, + 64'h05130000_15175064, + 64'hd03c1660_0793ec5f, + 64'hf0ef8325_05130000, + 64'h2517f53f_f0ef9101, + 64'h02049513_2481eddf, + 64'hf0ef82a5_05130000, + 64'h25175064_d03c1040, + 64'h07932000_0437fff5, + 64'h37fd0001_47a9c3b8, + 64'h47292000_07b7f05f, + 64'hf0efe426_e822ec06, + 64'h84a50513_11010000, + 64'h25178082_41088082, + 64'hc10c8082_610560e2, + 64'hee1ff0ef_00914503, + 64'hee9ff0ef_00814503, + 64'hf55ff0ef_ec06002c, + 64'h11018082_61456942, + 64'h64e27402_70a2fe94, + 64'h10e3f0bf_f0ef0091, + 64'h4503f13f_f0ef3461, + 64'h00814503_f81ff0ef, + 64'h0ff57513_002c0089, + 64'h553354e1_03800413, + 64'h892af406_e84aec26, + 64'hf0227179_80826145, + 64'h694264e2_740270a2, + 64'hfe9410e3_f4dff0ef, + 64'h00914503_f55ff0ef, + 64'h34610081_4503fc3f, + 64'hf0ef0ff5_7513002c, + 64'h0089553b_54e14461, + 64'h892af406_e84aec26, + 64'hf0227179_808200f5, + 64'h80230007_c78300e5, + 64'h80a397aa_81110007, + 64'h4703973e_00f57713, + 64'h98078793_00001797, + 64'hb7f50405_fa5ff0ef, + 64'h80820141_640260a2, + 64'he5090004_4503842a, + 64'he406e022_11418082, + 64'h00e78823_02000713, + 64'h00e78423_fc700713, + 64'h00e78623_470d0007, + 64'h822300e7_8023476d, + 64'h00e78623_f8000713, + 64'h00078223_100007b7, + 64'h808200a7_0023dfe5, + 64'h0207f793_01474783, + 64'h10000737_80820205, + 64'h75130147_c5031000, + 64'h07b78082_00054503, + 64'h808200b5_00238082, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00000000_00000000, + 64'h00048067_01f49493, + 64'h0010049b_b8458593, + 64'h00001597_f1402573, + 64'hff24c6e3_4009091b, + 64'h02000937_00448493, + 64'hfe091ee3_0004a903, + 64'h00092023_00990933, + 64'h00291913_f1402973, + 64'h020004b7_fe090ae3, + 64'h00897913_34402973, + 64'h10500073_ff24c6e3, + 64'h4009091b_02000937, + 64'h00448493_0124a023, + 64'h00100913_020004b7, + 64'h221000ef_01a11113, + 64'h0210011b_03249663, + 64'hf1402973_00000493, + 64'h30491073_00800913 + }; + + logic [$clog2(RomSize)-1:0] addr_q; + + always_ff @(posedge clk_i) begin + if (req_i) begin + addr_q <= addr_i[$clog2(RomSize)-1+3:3]; + end + end + + // this prevents spurious Xes from propagating into + // the speculative fetch stage of the core + assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0; +endmodule diff --git a/fpga/src/bootrom/gen_rom.py b/fpga/src/bootrom/gen_rom.py new file mode 120000 index 0000000000..7f92eadd06 --- /dev/null +++ b/fpga/src/bootrom/gen_rom.py @@ -0,0 +1 @@ +../../../bootrom/gen_rom.py \ No newline at end of file diff --git a/fpga/src/bootrom/linker.lds b/fpga/src/bootrom/linker.lds new file mode 100644 index 0000000000..b4497b901a --- /dev/null +++ b/fpga/src/bootrom/linker.lds @@ -0,0 +1,40 @@ +ENTRY(main) + +SECTIONS +{ + ROM_BASE = 0x10000; /* ... but actually position independent */ + + . = ROM_BASE; + + .text.init : { *(.text.init) } + + .text : ALIGN(0x100) { + _TEXT_START_ = .; + *(.text) + _TEXT_END_ = .; + } + + .data : ALIGN(0x100) { + _DATA_START_ = .; + *(.data) + _DATA_END_ = .; + } + + PROVIDE(_data = ADDR(.data)); + PROVIDE(_data_lma = LOADADDR(.data)); + PROVIDE(_edata = .); + + .bss : ALIGN(0x100) { + _BSS_START_ = .; + *(.bss) + _BSS_END_ = .; + } + + .rodata : ALIGN(0x100) { + _RODATA_START_ = .; + *(.rodata) + *(.dtb*) + *(.rodata*) + _RODATA_END_ = .; + } +} diff --git a/fpga/src/bootrom/platform.h b/fpga/src/bootrom/platform.h new file mode 100644 index 0000000000..8c193f002b --- /dev/null +++ b/fpga/src/bootrom/platform.h @@ -0,0 +1,2 @@ +#define DRAM_BASE 0x80000000 +#define DRAM_SIZE 0x4000000 \ No newline at end of file diff --git a/fpga/src/bootrom/src/gpt.c b/fpga/src/bootrom/src/gpt.c new file mode 100644 index 0000000000..15c9751107 --- /dev/null +++ b/fpga/src/bootrom/src/gpt.c @@ -0,0 +1,108 @@ +#include "gpt.h" + +#include "sd.h" +#include "uart.h" +#include + +int gpt_find_boot_partition(uint8_t* dest, uint32_t size) +{ + int ret = init_sd(); + if (ret != 0) { + print_uart("could not initialize sd... exiting\r\n"); + return -1; + } + + print_uart("sd initialized!\r\n"); + + // load LBA1 + size_t block_size = 512; + uint8_t lba1_buf[block_size]; + + int res = sd_copy(lba1_buf, 1, 1); + + if (res != 0) + { + print_uart("SD card failed!\r\n"); + print_uart("sd copy return value: "); + print_uart_addr(res); + print_uart("\r\n"); + return -2; + } + + gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf; + + print_uart("gpt partition table header:"); + print_uart("\r\n\tsignature:\t"); + print_uart_addr(lba1->signature); + print_uart("\r\n\trevision:\t"); + print_uart_int(lba1->revision); + print_uart("\r\n\tsize:\t\t"); + print_uart_int(lba1->header_size); + print_uart("\r\n\tcrc_header:\t"); + print_uart_int(lba1->crc_header); + print_uart("\r\n\treserved:\t"); + print_uart_int(lba1->reserved); + print_uart("\r\n\tcurrent lba:\t"); + print_uart_addr(lba1->current_lba); + print_uart("\r\n\tbackup lda:\t"); + print_uart_addr(lba1->backup_lba); + print_uart("\r\n\tpartition entries lba: \t"); + print_uart_addr(lba1->partition_entries_lba); + print_uart("\r\n\tnumber partition entries:\t"); + print_uart_int(lba1->nr_partition_entries); + print_uart("\r\n\tsize partition entries: \t"); + print_uart_int(lba1->size_partition_entry); + print_uart("\r\n"); + + uint8_t lba2_buf[block_size]; + + res = sd_copy(lba2_buf, lba1->partition_entries_lba, 1); + + if (res != 0) + { + print_uart("SD card failed!\r\n"); + print_uart("sd copy return value: "); + print_uart_addr(res); + print_uart("\r\n"); + return -2; + } + + for (int i = 0; i < 4; i++) + { + partition_entries_t *part_entry = (partition_entries_t *)(lba2_buf + (i * 128)); + print_uart("gpt partition entry "); + print_uart_byte(i); + print_uart("\r\n\tpartition type guid:\t"); + for (int j = 0; j < 16; j++) + print_uart_byte(part_entry->partition_type_guid[j]); + print_uart("\r\n\tpartition guid: \t"); + for (int j = 0; j < 16; j++) + print_uart_byte(part_entry->partition_guid[j]); + print_uart("\r\n\tfirst lba:\t"); + print_uart_addr(part_entry->first_lba); + print_uart("\r\n\tlast lba:\t"); + print_uart_addr(part_entry->last_lba); + print_uart("\r\n\tattributes:\t"); + print_uart_addr(part_entry->attributes); + print_uart("\r\n\tname:\t"); + for (int j = 0; j < 72; j++) + print_uart_byte(part_entry->name[j]); + print_uart("\r\n"); + } + + partition_entries_t *boot = (partition_entries_t *)(lba2_buf); + print_uart("copying boot image "); + res = sd_copy(dest, boot->first_lba, size); + + if (res != 0) + { + print_uart("SD card failed!\r\n"); + print_uart("sd copy return value: "); + print_uart_addr(res); + print_uart("\r\n"); + return -2; + } + + print_uart(" done!\r\n"); + return 0; +} \ No newline at end of file diff --git a/fpga/src/bootrom/src/gpt.h b/fpga/src/bootrom/src/gpt.h new file mode 100644 index 0000000000..2968fbbd47 --- /dev/null +++ b/fpga/src/bootrom/src/gpt.h @@ -0,0 +1,39 @@ +#pragma once + +#include + +// LBA 0: Protective MBR +// ignored here + +// Partition Table Header (LBA 1) +typedef struct gpt_pth +{ + uint64_t signature; + uint32_t revision; + uint32_t header_size; //! little endian, usually 0x5c = 92 + uint32_t crc_header; + uint32_t reserved; //! must be 0 + uint64_t current_lba; + uint64_t backup_lba; + uint64_t first_usable_lba; + uint64_t last_usable_lba; + uint8_t disk_guid[16]; + uint64_t partition_entries_lba; + uint32_t nr_partition_entries; + uint32_t size_partition_entry; //! usually 0x80 = 128 + uint32_t crc_partition_entry; +} gpt_pth_t; + +// Partition Entries (LBA 2-33) +typedef struct partition_entries +{ + uint8_t partition_type_guid[16]; + uint8_t partition_guid[16]; + uint64_t first_lba; + uint64_t last_lba; //! inclusive + uint64_t attributes; + uint8_t name[72]; //! utf16 encoded +} partition_entries_t; + +// Find boot partition and load it to the destination +int gpt_find_boot_partition(uint8_t* dest, uint32_t size); \ No newline at end of file diff --git a/fpga/src/bootrom/src/main.c b/fpga/src/bootrom/src/main.c new file mode 100644 index 0000000000..66af9c3af6 --- /dev/null +++ b/fpga/src/bootrom/src/main.c @@ -0,0 +1,31 @@ +#include "uart.h" +#include "spi.h" +#include "sd.h" +#include "gpt.h" + +int main() +{ + init_uart(); + print_uart("Hello World!\r\n"); + + int res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384); + + if (res == 0) + { + // jump to the address + __asm__ volatile( + "li s0, 0x80000000;" + "la a1, _dtb;" + "jr s0"); + } + + while (1) + { + // do nothing + } +} + +void handle_trap(void) +{ + // print_uart("trap\r\n"); +} \ No newline at end of file diff --git a/fpga/src/bootrom/src/sd.c b/fpga/src/bootrom/src/sd.c new file mode 100644 index 0000000000..104a4ef531 --- /dev/null +++ b/fpga/src/bootrom/src/sd.c @@ -0,0 +1,208 @@ +#include "sd.h" +#include "spi.h" +#include "uart.h" + +// spi full duplex: send 0xff to receive byte +uint8_t sd_dummy() +{ + return spi_txrx(0xFF); +} + +uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) +{ + unsigned long n; + uint8_t r; + + sd_dummy(); + spi_txrx(0x40 | cmd); + spi_txrx(arg >> 24); + spi_txrx(arg >> 16); + spi_txrx(arg >> 8); + spi_txrx(arg); + spi_txrx(crc); + + n = 100; + do + { + r = sd_dummy(); + if (!(r & 0x80)) + { + break; + } + } while (--n > 0); + if (n == 0) + { + // print_uart("could not find valid sd response\r\n"); + } + return r; +} + +void print_status(const char *cmd, uint8_t response) +{ + print_uart("SD command "); + print_uart(cmd); + print_uart(" \tresponse : "); + print_uart_byte(response); + print_uart("\r\n"); +} + +int sd_cmd0() +{ + int counter = 10000; + uint8_t r = 0xff; + while (r != 0x1) + { + r = sd_cmd(0, 0, 0x95); + sd_dummy(); // R1: 1 Byte response + counter--; + if (counter <= 0) + return 1 == 0; + } + print_status("cmd0", r); + return r == 0x1; +} + +int sd_cmd8() +{ + uint8_t r1 = sd_cmd(8, 0x1aa, 0x87); + sd_dummy(); /* command version; reserved */ + sd_dummy(); /* reserved */ + uint8_t r4 = sd_dummy(); /* voltage */ + uint8_t r5 = sd_dummy(); /* check pattern */ + sd_dummy(); + + sd_dummy(); // additional 0xff for good measure + return r1 == 0x1 && (r4 & 0xf) == 0x1 && r5 == 0xaa; +} + +int sd_cmd55() +{ + uint8_t r = sd_cmd(55, 0x0, 0x65); + sd_dummy(); + print_status("cmd55", r); + return r == 0x1; +} + +int sd_acmd41() +{ + uint8_t r; + do + { + sd_cmd55(); + r = sd_cmd(41, 0x40000000, 0x77); /* HCS = 1 */ + print_status("cmd41", r); + sd_dummy(); + } while (r == 0x1); + return (r == 0x00); +} + +int init_sd() +{ + spi_init(); + + print_uart("initializing SD... \r\n"); + // mostly taken from + // https://electronics.stackexchange.com/questions/77417/what-is-the-correct-command-sequence-for-microsd-card-initialization-in-spi + // and the siFive implementation: + // https://github.com/sifive/freedom-u540-c000-bootloader/blob/09ac8c24dae741e6234e2b1e663784294367e147/sd/sd.c + + // send 10 bytes 0xff + for (int i = 0; i < 10; i++) + sd_dummy(); + + if (!sd_cmd0()) + return SD_INIT_ERROR_CMD0; + if (!sd_cmd8()) + return SD_INIT_ERROR_CMD8; + if (!sd_acmd41()) + return SD_INIT_ERROR_ACMD41; + return 0; +} + +uint8_t crc7(uint8_t prev, uint8_t in) +{ + // CRC polynomial 0x89 + uint8_t remainder = prev & in; + remainder ^= (remainder >> 4) ^ (remainder >> 7); + remainder ^= remainder << 4; + return remainder & 0x7f; +} + +uint16_t crc16(uint16_t crc, uint8_t data) +{ + // CRC polynomial 0x11021 + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + +int sd_copy(void *dst, uint32_t src_lba, uint32_t size) +{ + volatile uint8_t *p = dst; + long i = size; + int rc = 0; + + uint8_t ff[128]; + for (int j = 0; j < 128; j++) + ff[j] = 0xff; + + uint8_t crc = 0; + crc = crc7(crc, 0x40 | SD_CMD_READ_BLOCK_MULTIPLE); + crc = crc7(crc, (src_lba >> 24) & 0xff); + crc = crc7(crc, (src_lba >> 16) & 0xff); + crc = crc7(crc, (src_lba >> 8) & 0xff); + crc = crc7(crc, src_lba & 0xff); + crc = (crc << 1) | 1; + if (sd_cmd(18, src_lba, crc) != 0x00) + { + for (int j = 0; j < 8; i++) + sd_dummy(); + + print_uart("could not read SD block\r\n"); + return -1; + } + do + { + uint16_t crc, crc_exp; + long n; + + crc = 0; + n = 512; + while (sd_dummy() != SD_DATA_TOKEN) + ; + do + { + int bytes_per_transfer = 64; + spi_write_bytes(ff, bytes_per_transfer, (uint8_t *)p); + for (int i = 0; i < bytes_per_transfer; i++) + { + crc = crc16(crc, p[i]); + } + p += bytes_per_transfer; + n -= bytes_per_transfer; + // uint8_t x = sd_dummy(); + // *p++ = x; + // crc = crc16(crc, x); + } while (n > 0); + + crc_exp = ((uint16_t)sd_dummy() << 8); + crc_exp |= sd_dummy(); + + if (crc != crc_exp) + { + rc = SD_COPY_ERROR_CMD18_CRC; + break; + } + if ((i % 1000) == 0) + { + print_uart("."); + } + } while (--i > 0); + + sd_cmd(SD_CMD_STOP_TRANSMISSION, 0, 0x01); + sd_dummy(); + return rc; +} diff --git a/fpga/src/bootrom/src/sd.h b/fpga/src/bootrom/src/sd.h new file mode 100644 index 0000000000..ed0c52e469 --- /dev/null +++ b/fpga/src/bootrom/src/sd.h @@ -0,0 +1,20 @@ +#pragma once + +#include + +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_READ_BLOCK_MULTIPLE 18 +#define SD_DATA_TOKEN 0xfe +#define SD_COPY_ERROR_CMD18 -1 +#define SD_COPY_ERROR_CMD18_CRC -2 + +// errors +#define SD_INIT_ERROR_CMD0 -1 +#define SD_INIT_ERROR_CMD8 -2 +#define SD_INIT_ERROR_ACMD41 -3 + +int init_sd(); + +void put_sdcard_spi_mode(); + +int sd_copy(void *dst, uint32_t src_lba, uint32_t size); \ No newline at end of file diff --git a/fpga/src/bootrom/src/smp.h b/fpga/src/bootrom/src/smp.h new file mode 100644 index 0000000000..bb037755dc --- /dev/null +++ b/fpga/src/bootrom/src/smp.h @@ -0,0 +1,52 @@ +#pragma once + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +// The maximum number of HARTs this code supports +#define CLINT_CTRL_ADDR 0x2000000 +#ifndef MAX_HARTS +#define MAX_HARTS 256 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS * 4) + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8; \ + csrw mie, reg2; \ + li reg1, NONSMP_HART; \ + csrr reg2, mhartid; \ + bne reg1, reg2, 42f + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR; \ + 41:; \ + li reg2, 1; \ + sw reg2, 0(reg1); \ + addi reg1, reg1, 4; \ + li reg2, CLINT_END_HART_IPI; \ + blt reg1, reg2, 41b; \ + 42:; \ + wfi; \ + csrr reg2, mip; \ + andi reg2, reg2, 0x8; \ + beqz reg2, 42b; \ + li reg1, CLINT_CTRL_ADDR; \ + csrr reg2, mhartid; \ + slli reg2, reg2, 2; \ + add reg2, reg2, reg1; \ + sw zero, 0(reg2); \ + 41:; \ + lw reg2, 0(reg1); \ + bnez reg2, 41b; \ + addi reg1, reg1, 4; \ + li reg2, CLINT_END_HART_IPI; \ + blt reg1, reg2, 41b diff --git a/fpga/src/bootrom/src/spi.c b/fpga/src/bootrom/src/spi.c new file mode 100644 index 0000000000..c574f59cf6 --- /dev/null +++ b/fpga/src/bootrom/src/spi.c @@ -0,0 +1,131 @@ +#include "spi.h" + +#include "uart.h" + +void write_reg(uintptr_t addr, uint32_t value) +{ + volatile uint32_t *loc_addr = (volatile uint32_t *)addr; + *loc_addr = value; +} + +uint32_t read_reg(uintptr_t addr) +{ + return *(volatile uint32_t *)addr; +} + +void spi_init() +{ + print_uart("init SPI\r\n"); + + // reset the axi quadspi core + write_reg(SPI_RESET_REG, 0x0a); + + for (int i = 0; i < 10; i++) + { + __asm__ volatile( + "nop"); + } + + write_reg(SPI_CONTROL_REG, 0x104); + + uint32_t status = read_reg(SPI_STATUS_REG); + print_uart("status: 0x"); + print_uart_addr(status); + print_uart("\r\n"); + + // clear all fifos + write_reg(SPI_CONTROL_REG, 0x166); + + status = read_reg(SPI_STATUS_REG); + print_uart("status: 0x"); + print_uart_addr(status); + print_uart("\r\n"); + + write_reg(SPI_CONTROL_REG, 0x06); + + print_uart("SPI initialized!\r\n"); +} + +uint8_t spi_txrx(uint8_t byte) +{ + // enable slave select + write_reg(SPI_SLAVE_SELECT_REG, 0xfffffffe); + + write_reg(SPI_TRANSMIT_REG, byte); + + for (int i = 0; i < 100; i++) + { + __asm__ volatile( + "nop"); + } + + // enable spi control master flag + write_reg(SPI_CONTROL_REG, 0x106); + + while ((read_reg(SPI_STATUS_REG) & 0x1) == 0x1) + ; + + uint32_t result = read_reg(SPI_RECEIVE_REG); + + if ((read_reg(SPI_STATUS_REG) & 0x1) != 0x1) + { + print_uart("rx fifo not empty?? "); + print_uart_addr(read_reg(SPI_STATUS_REG)); + print_uart("\r\n"); + } + + // disable slave select + write_reg(SPI_SLAVE_SELECT_REG, 0xffffffff); + + // disable spi control master flag + write_reg(SPI_CONTROL_REG, 0x06); + + return result; +} + +int spi_write_bytes(uint8_t *bytes, uint32_t len, uint8_t *ret) +{ + uint32_t status; + + if (len > 256) // FIFO maxdepth 256 + return -1; + + // enable slave select + write_reg(SPI_SLAVE_SELECT_REG, 0xfffffffe); + + for (int i = 0; i < len; i++) + { + write_reg(SPI_TRANSMIT_REG, bytes[i] & 0xff); + } + + for (int i = 0; i < 50; i++) + { + __asm__ volatile( + "nop"); + } + + // enable spi control master flag + write_reg(SPI_CONTROL_REG, 0x106); + + do + { + status = read_reg(SPI_STATUS_REG); + } while ((status & 0x1) == 0x1); + + for (int i = 0; i < len;) + { + status = read_reg(SPI_STATUS_REG); + if ((status & 0x1) != 0x1) // recieve fifo not empty + { + ret[i++] = read_reg(SPI_RECEIVE_REG); + } + } + + // disable slave select + write_reg(SPI_SLAVE_SELECT_REG, 0xffffffff); + + // disable spi control master flag + write_reg(SPI_CONTROL_REG, 0x06); + + return 0; +} \ No newline at end of file diff --git a/fpga/src/bootrom/src/spi.h b/fpga/src/bootrom/src/spi.h new file mode 100644 index 0000000000..9d25e134de --- /dev/null +++ b/fpga/src/bootrom/src/spi.h @@ -0,0 +1,25 @@ +#pragma once + +#include + +#define SPI_BASE 0x20000000 + +#define SPI_RESET_REG SPI_BASE + 0x40 +#define SPI_CONTROL_REG SPI_BASE + 0x60 +#define SPI_STATUS_REG SPI_BASE + 0x64 +#define SPI_TRANSMIT_REG SPI_BASE + 0x68 +#define SPI_RECEIVE_REG SPI_BASE + 0x6C +#define SPI_SLAVE_SELECT_REG SPI_BASE + 0x70 +#define SPI_TRANSMIT_OCCUPANCY SPI_BASE + 0x74 +#define SPI_RECEIVE_OCCUPANCY SPI_BASE + 0x78 +#define SPI_INTERRUPT_GLOBAL_ENABLE_REG SPI_BASE + 0x1c +#define SPI_INTERRUPT_STATUS_REG SPI_BASE + 0x20 +#define SPI_INTERRUPT_ENABLE_REG SPI_BASE + 0x28 + + +void spi_init(); + +uint8_t spi_txrx(uint8_t byte); + +// return -1 if something went wrong +int spi_write_bytes(uint8_t *bytes, uint32_t len, uint8_t *ret); \ No newline at end of file diff --git a/fpga/src/bootrom/src/uart.c b/fpga/src/bootrom/src/uart.c new file mode 100644 index 0000000000..29ccffce6d --- /dev/null +++ b/fpga/src/bootrom/src/uart.c @@ -0,0 +1,89 @@ +#include "uart.h" + +void write_reg_u8(uintptr_t addr, uint8_t value) +{ + volatile uint8_t *loc_addr = (volatile uint8_t *)addr; + *loc_addr = value; +} + +uint8_t read_reg_u8(uintptr_t addr) +{ + return *(volatile uint8_t *)addr; +} + +int is_transmit_empty() +{ + return read_reg_u8(UART_LINE_STATUS) & 0x20; +} + +void write_serial(char a) +{ + while (is_transmit_empty() == 0) {}; + + write_reg_u8(UART_THR, a); +} + +void init_uart() +{ + write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts + write_reg_u8(UART_LINE_CONTROL, 0x80); // Enable DLAB (set baud rate divisor) + write_reg_u8(UART_DLAB_LSB, 0x1B); // Set divisor to 27 (lo byte) 115200 baud + write_reg_u8(UART_DLAB_MSB, 0x00); // (hi byte) + write_reg_u8(UART_LINE_CONTROL, 0x03); // 8 bits, no parity, one stop bit + write_reg_u8(UART_FIFO_CONTROL, 0xC7); // Enable FIFO, clear them, with 14-byte threshold + write_reg_u8(UART_MODEM_CONTROL, 0x20); // Autoflow mode +} + +void print_uart(const char *str) +{ + const char *cur = &str[0]; + while (*cur != '\0') + { + write_serial((uint8_t)*cur); + ++cur; + } +} + +uint8_t bin_to_hex_table[16] = { + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + +void bin_to_hex(uint8_t inp, uint8_t res[2]) +{ + res[1] = bin_to_hex_table[inp & 0xf]; + res[0] = bin_to_hex_table[(inp >> 4) & 0xf]; + return; +} + +void print_uart_int(uint32_t addr) +{ + int i; + for (i = 3; i > -1; i--) + { + uint8_t cur = (addr >> (i * 8)) & 0xff; + uint8_t hex[2]; + bin_to_hex(cur, hex); + write_serial(hex[0]); + write_serial(hex[1]); + } +} + +void print_uart_addr(uint64_t addr) +{ + int i; + for (i = 7; i > -1; i--) + { + uint8_t cur = (addr >> (i * 8)) & 0xff; + uint8_t hex[2]; + bin_to_hex(cur, hex); + write_serial(hex[0]); + write_serial(hex[1]); + } +} + +void print_uart_byte(uint8_t byte) +{ + uint8_t hex[2]; + bin_to_hex(byte, hex); + write_serial(hex[0]); + write_serial(hex[1]); +} \ No newline at end of file diff --git a/fpga/src/bootrom/src/uart.h b/fpga/src/bootrom/src/uart.h new file mode 100644 index 0000000000..6505c6bb0e --- /dev/null +++ b/fpga/src/bootrom/src/uart.h @@ -0,0 +1,27 @@ +#pragma once + +#include + +#define UART_BASE 0x10000000 + +#define UART_RBR UART_BASE + 0 +#define UART_THR UART_BASE + 0 +#define UART_INTERRUPT_ENABLE UART_BASE + 4 +#define UART_INTERRUPT_IDENT UART_BASE + 8 +#define UART_FIFO_CONTROL UART_BASE + 8 +#define UART_LINE_CONTROL UART_BASE + 12 +#define UART_MODEM_CONTROL UART_BASE + 16 +#define UART_LINE_STATUS UART_BASE + 20 +#define UART_MODEM_STATUS UART_BASE + 24 +#define UART_DLAB_LSB UART_BASE + 0 +#define UART_DLAB_MSB UART_BASE + 4 + +void init_uart(); + +void print_uart(const char* str); + +void print_uart_int(uint32_t addr); + +void print_uart_addr(uint64_t addr); + +void print_uart_byte(uint8_t byte); \ No newline at end of file diff --git a/fpga/src/bootrom/startup.S b/fpga/src/bootrom/startup.S new file mode 100644 index 0000000000..76a49801de --- /dev/null +++ b/fpga/src/bootrom/startup.S @@ -0,0 +1,24 @@ +# start sequence of the bootloader +# +# +#include +#define DRAM_BASE 0x80000000 + + .section .text.init + .option norvc + .globl _prog_start +_prog_start: + smp_pause(s1, s2) + li sp, 0x84000000 + call main + smp_resume(s1, s2) + csrr a0, mhartid + la a1, _dtb + li s1, DRAM_BASE + jr s1 + + .section .dtb + .globl _dtb + .align 4, 0 +_dtb: + .incbin "ariane.dtb" \ No newline at end of file diff --git a/fpga/src/fan_ctrl.sv b/fpga/src/fan_ctrl.sv new file mode 100644 index 0000000000..fb02114360 --- /dev/null +++ b/fpga/src/fan_ctrl.sv @@ -0,0 +1,59 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Description: PWM Fan Control for Genesys II board +// Author: Florian Zaruba, zarubaf@iis.ee.ethz.ch + +module fan_ctrl ( + input logic clk_i, + input logic rst_ni, + input logic [3:0] pwm_setting_i, + output logic fan_pwm_o +); + logic [3:0] ms_clock_d, ms_clock_q; + logic [19:0] cycle_counter_d, cycle_counter_q; + + // clock divider + always_comb begin + cycle_counter_d = cycle_counter_q; + ms_clock_d = ms_clock_q; + + // divide clock by 499999 + if (cycle_counter_q == 499_999) begin + cycle_counter_d = 0; + ms_clock_d = ms_clock_q + 1; + end else begin + cycle_counter_d = cycle_counter_q + 1; + end + + if (ms_clock_q == 15) begin + ms_clock_d = 0; + end + end + + // duty cycle + always_comb begin + if (ms_clock_q < pwm_setting_i) begin + fan_pwm_o = 1'b1; + end else begin + fan_pwm_o = 1'b0; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + ms_clock_q <= '0; + cycle_counter_q <= '0; + end else begin + ms_clock_q <= ms_clock_d; + cycle_counter_q <= cycle_counter_d; + end + end +endmodule diff --git a/fpga/src/genesysii.svh b/fpga/src/genesysii.svh new file mode 100644 index 0000000000..8f73d26c71 --- /dev/null +++ b/fpga/src/genesysii.svh @@ -0,0 +1,14 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Description: Set global FPGA degines +// Author: Florian Zaruba + +`define GENESYSII diff --git a/fpga/src/rgmii_to_mii_conv_xilinx.sv b/fpga/src/rgmii_to_mii_conv_xilinx.sv new file mode 100644 index 0000000000..9925af8a77 --- /dev/null +++ b/fpga/src/rgmii_to_mii_conv_xilinx.sv @@ -0,0 +1,195 @@ +// Copyright (c) 2015-2018 Princeton University +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of Princeton University nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY +// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +// Simplified RGMII <-> MII converter (boldly copied from OpenPiton) +// Specific to 7-series FPGA +module rgmii_to_mii_conv_xilinx ( + // to PHY (RGMII) + output logic rgmii_phy_txc, + output logic rgmii_phy_txctl, + output logic [3:0] rgmii_phy_txd, + input logic rgmii_phy_rxc, + input logic rgmii_phy_rxctl, + input logic [3:0] rgmii_phy_rxd, + output logic rgmii_phy_rst_n, + inout wire rgmii_phy_mdio, + output logic rgmii_phy_mdc, + // from MAC (MII) + input logic mem_clk_i, // 200 MHz + input logic net_phy_rst_n, + input logic net_phy_tx_clk, // 25 MHz + input logic net_phy_tx_en, + input logic [3:0] net_phy_tx_data, + output logic net_phy_rx_clk, + output logic net_phy_dv, + output logic [3:0] net_phy_rx_data, + output logic net_phy_rx_er, + + input logic net_mdio_i, + output logic net_mdio_o, + input logic net_mdio_t, + input logic net_phy_mdc +); + + // ------------- + // MDIO + // ------------- + IOBUF mdio_io_iobuf (.I (net_mdio_i), .IO(rgmii_phy_mdio), .O (net_mdio_o), .T (net_mdio_t)); + assign rgmii_phy_mdc = net_phy_mdc; + assign rgmii_phy_rst_n = net_phy_rst_n; + + // ------------- + // TX + // ------------- + // net_phy_tx_clk: ___|------|______|------|______|------|______| + // rgmii_phy_txc: ---|______|------|______|------|______|------| + // net_phy_tx_en: -----_________________________________________ + // rgmii_phy_txctl: _____--------------___________________________ + + // basically inverts the clock + ODDR net_phy_txc_oddr ( + .C ( net_phy_tx_clk ), // 1-bit clock input (The CLK pin represents the clock input pin) + .CE ( 1'b1 ), // 1-bit clock enable input (CE represents the clock enable pin. When asserted Low, + .Q ( rgmii_phy_txc ), // 1-bit DDR output (ODDR register output) + // this port disables the output clock on port Q.) + .D1 ( 1'b0 ), // 1-bit data input (positive edge) (ODDR register inputs) + .D2 ( 1'b1 ), // 1-bit data input (negative edge) (ODDR register inputs) + // Synchronous/Asynchronous set/reset pin. Set/Reset is + // asserted High. + .R ( 1'b0 ), // 1-bit reset + .S ( 1'b0 ) // 1-bit set + ); + + // D-FF + FD net_phy_txctl_dff ( + .C ( net_phy_tx_clk ), + .D ( net_phy_tx_en ), + .Q ( rgmii_phy_txctl ) + ); + + for (genvar i = 0; i < 4; i++) begin : gen_net_phy_txd + FD net_phy_txd_dff ( + .C ( net_phy_tx_clk ), + .D ( net_phy_tx_data[i] ), + .Q ( rgmii_phy_txd[i] ) + ); + end + + // ------------- + // RX + // ------------- + logic net_phy_rxc_ibufg_out; + logic net_phy_rxc_delayed; + + logic net_phy_rx_dv_f; + logic net_phy_rx_err_f; + logic net_phy_rx_dv_ff; + logic net_phy_rx_err_ff; + logic [3:0] net_phy_rxd_f; + logic [3:0] net_phy_rxd_ff; + + IBUFG net_phy_rxc_ibufg ( + .I ( rgmii_phy_rxc ), + .O ( net_phy_rxc_ibufg_out ) + ); + + // Delay by RXC 31*78 (IDELAY_VALUE*tap_delay@200MHz) to put in RXD/RXCTL eye + (* IODELAY_GROUP = "NET_PHY_RXC" *) + IDELAYE2 #( + .CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE) + .DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN) + .HIGH_PERFORMANCE_MODE ( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE") + .IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE + .IDELAY_VALUE ( 31 ), // Input delay tap setting (0-31) + .PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE + .REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0). + .SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal + ) i_idelaye2 ( + .CNTVALUEOUT ( ), // 5-bit output: Counter value output + .DATAOUT ( net_phy_rxc_delayed ), // 1-bit output: Delayed data output + .C ( 1'b0 ), // 1-bit input: Clock input + .CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input + .CINVCTRL ( ), // 1-bit input: Dynamic clock inversion input + .CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input + .DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input + .IDATAIN ( net_phy_rxc_ibufg_out ), // 1-bit input: Data input from the I/O + .INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input + .LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input + .LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input + .REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input + ); + + (* IODELAY_GROUP = "NET_PHY_RXC" *) + IDELAYCTRL i_idelayctrl ( + .RDY ( ), // 1-bit output: Ready output + // 200-MHz for g2, clk_mmccm drives clocks through BUFG + .REFCLK ( mem_clk_i ), // 1-bit input: Reference clock input + .RST ( 1'b0 ) // 1-bit input: Active high reset input + ); + + BUFG BUFG_inst ( + .I ( net_phy_rxc_delayed ), + .O ( net_phy_rx_clk ) + ); + + // The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) + // on the falling edge. + // data valid is transmitted on positive edge + always_ff @(posedge net_phy_rx_clk) begin + if (~rgmii_phy_rst_n) begin + net_phy_rx_dv_f <= 1'b0; + end else begin + net_phy_rx_dv_f <= rgmii_phy_rxctl; + end + end + + // data error is encoded on negative edge of rxctl + always_ff @(negedge net_phy_rx_clk) begin + if (~rgmii_phy_rst_n) begin + net_phy_rx_err_f <= 1'b0; + end else begin + net_phy_rx_err_f <= rgmii_phy_rxctl; + end + end + + always_ff @(posedge net_phy_rx_clk) begin + if (~rgmii_phy_rst_n) begin + net_phy_rxd_f <= '0; + net_phy_rxd_ff <= '0; + net_phy_rx_dv_ff <= 1'b0; + net_phy_rx_err_ff <= 1'b0; + end else begin + net_phy_rxd_f <= rgmii_phy_rxd; + net_phy_rxd_ff <= net_phy_rxd_f; + net_phy_rx_dv_ff <= net_phy_rx_dv_f; + net_phy_rx_err_ff <= net_phy_rx_err_f; + end + end + + assign net_phy_dv = net_phy_rx_dv_ff; + assign net_phy_rx_er = net_phy_rx_dv_ff ^ net_phy_rx_err_ff; + assign net_phy_rx_data = net_phy_rxd_ff; + +endmodule diff --git a/fpga/src/vcu118.svh b/fpga/src/vcu118.svh new file mode 100644 index 0000000000..47440a844b --- /dev/null +++ b/fpga/src/vcu118.svh @@ -0,0 +1,14 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Description: Set global FPGA degines +// Author: Florian Zaruba + +`define VCU118 diff --git a/fpga/xilinx/.gitignore b/fpga/xilinx/.gitignore new file mode 100644 index 0000000000..12ef7f9f21 --- /dev/null +++ b/fpga/xilinx/.gitignore @@ -0,0 +1,5 @@ +xlnx*/* +!xlnx*/tcl +!Makefile +!common.mk +!*.prj \ No newline at end of file diff --git a/fpga/xilinx/common.mk b/fpga/xilinx/common.mk new file mode 100644 index 0000000000..60c91008bb --- /dev/null +++ b/fpga/xilinx/common.mk @@ -0,0 +1,19 @@ +all: + vivado -mode batch -source tcl/run.tcl + mkdir -p ip + cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/. + cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/. + +gui: + vivado -mode gui -source tcl/run.tcl & + +clean: + rm -rf ip/* + mkdir -p ip + rm -rf ${PROJECT}.* + rm -rf component.xml + rm -rf vivado*.jou + rm -rf vivado*.log + rm -rf vivado*.str + rm -rf xgui + rm -rf .Xil \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_clock_converter/Makefile b/fpga/xilinx/xlnx_axi_clock_converter/Makefile new file mode 100644 index 0000000000..426a7d735e --- /dev/null +++ b/fpga/xilinx/xlnx_axi_clock_converter/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_axi_clock_converter +include ../common.mk \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl b/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl new file mode 100644 index 0000000000..8c14214ae2 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl @@ -0,0 +1,17 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_axi_clock_converter + +create_project $ipName . -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {5}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile b/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile new file mode 100644 index 0000000000..d109f974d7 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_axi_dwidth_converter +include ../common.mk \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl b/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl new file mode 100644 index 0000000000..39fcaff850 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl @@ -0,0 +1,17 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_axi_dwidth_converter + +create_project $ipName . -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {5} CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_ethernetlite/Makefile b/fpga/xilinx/xlnx_axi_ethernetlite/Makefile new file mode 100644 index 0000000000..22240b12b0 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_ethernetlite/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_axi_ethernetlite +include ../common.mk \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_ethernetlite/tcl/run.tcl b/fpga/xilinx/xlnx_axi_ethernetlite/tcl/run.tcl new file mode 100644 index 0000000000..2e77e4c1c7 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_ethernetlite/tcl/run.tcl @@ -0,0 +1,17 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_axi_ethernetlite + +create_project $ipName . -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_ethernetlite -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [list CONFIG.C_S_AXI_PROTOCOL {AXI4} CONFIG.AXI_ACLK_FREQ_MHZ {100}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_gpio/Makefile b/fpga/xilinx/xlnx_axi_gpio/Makefile new file mode 100644 index 0000000000..46dd3417c4 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_gpio/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_axi_gpio +include ../common.mk \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl b/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl new file mode 100644 index 0000000000..7ec5415e45 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl @@ -0,0 +1,16 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_axi_gpio + +create_project $ipName . -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_gpio -vendor xilinx.com -library ip -module_name $ipName +set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.C_INTERRUPT_PRESENT {0}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_quad_spi/Makefile b/fpga/xilinx/xlnx_axi_quad_spi/Makefile new file mode 100644 index 0000000000..d61633d1b4 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_quad_spi/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_axi_quad_spi +include ../common.mk \ No newline at end of file diff --git a/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl b/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl new file mode 100644 index 0000000000..df8e09ad00 --- /dev/null +++ b/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl @@ -0,0 +1,16 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_axi_quad_spi + +create_project $ipName . -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_quad_spi -vendor xilinx.com -library ip -module_name $ipName +set_property -dict [list CONFIG.C_USE_STARTUP {0} CONFIG.C_SCK_RATIO {4} CONFIG.C_FIFO_DEPTH {256} CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} CONFIG.C_S_AXI4_ID_WIDTH {0}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/fpga/xilinx/xlnx_clk_gen/Makefile b/fpga/xilinx/xlnx_clk_gen/Makefile new file mode 100644 index 0000000000..8ce5e6e63e --- /dev/null +++ b/fpga/xilinx/xlnx_clk_gen/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_clk_gen +include ../common.mk \ No newline at end of file diff --git a/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl new file mode 100644 index 0000000000..246e4d2ea1 --- /dev/null +++ b/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl @@ -0,0 +1,17 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_clk_gen + +create_project $ipName . -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT3_USED {true} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {25} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.000} CONFIG.MMCM_CLKIN2_PERIOD {10.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} CONFIG.MMCM_CLKOUT1_DIVIDE {40} CONFIG.MMCM_CLKOUT2_DIVIDE {10} CONFIG.NUM_OUT_CLKS {3} CONFIG.CLKOUT1_JITTER {129.198} CONFIG.CLKOUT1_PHASE_ERROR {89.971} CONFIG.CLKOUT2_JITTER {148.629} CONFIG.CLKOUT2_PHASE_ERROR {89.971} CONFIG.CLKOUT3_JITTER {112.316} CONFIG.CLKOUT3_PHASE_ERROR {89.971}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/fpga/xilinx/xlnx_ila/Makefile b/fpga/xilinx/xlnx_ila/Makefile new file mode 100644 index 0000000000..299a7133f7 --- /dev/null +++ b/fpga/xilinx/xlnx_ila/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_ila +include ../common.mk \ No newline at end of file diff --git a/fpga/xilinx/xlnx_ila/tcl/run.tcl b/fpga/xilinx/xlnx_ila/tcl/run.tcl new file mode 100644 index 0000000000..640b248353 --- /dev/null +++ b/fpga/xilinx/xlnx_ila/tcl/run.tcl @@ -0,0 +1,17 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_ila + +create_project $ipName . -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name ila -vendor xilinx.com -library ip -module_name $ipName +set_property -dict [list CONFIG.C_PROBE6_WIDTH {4} CONFIG.C_PROBE3_WIDTH {4} CONFIG.C_DATA_DEPTH {16384} CONFIG.C_NUM_OF_PROBES {8} CONFIG.C_INPUT_PIPE_STAGES {1}] [get_ips $ipName] + + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/Makefile b/fpga/xilinx/xlnx_mig_7_ddr3/Makefile new file mode 100644 index 0000000000..dd00c21cc8 --- /dev/null +++ b/fpga/xilinx/xlnx_mig_7_ddr3/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_mig_7_ddr3 +include ../common.mk \ No newline at end of file diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj b/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj new file mode 100755 index 0000000000..cdc818e9c7 --- /dev/null +++ b/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj @@ -0,0 +1,160 @@ + + + + xlnx_mig_7_ddr3 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7k325t-ffg900/-2 + 4.1 + Differential + Use System Clock + ACTIVE LOW + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41J256m16XX-107 + 1250 + 2.0V + 4:1 + 200 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 30 + 64 + 5 + 0 + + + + \ No newline at end of file diff --git a/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl b/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl new file mode 100644 index 0000000000..db0887620e --- /dev/null +++ b/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl @@ -0,0 +1,19 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_mig_7_ddr3 + +create_project $ipName . -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName + +exec cp mig_genesys2.prj ./$ipName.srcs/sources_1/ip/$ipName/mig_a.prj + +set_property -dict [list CONFIG.XML_INPUT_FILE {mig_a.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/fpuwave.do b/fpuwave.do deleted file mode 100644 index f5380e36b1..0000000000 --- a/fpuwave.do +++ /dev/null @@ -1,802 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/pc_i -add wave -noupdate -divider {HandShake In} -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Op_SI -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/InValid_SI -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/InReady_SO -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/A_DI -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/B_DI -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/C_DI -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Tag_DI -add wave -noupdate -divider {HandShake Out} -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OutValid_SO -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OutReady_SI -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/result_o -add wave -noupdate /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Tag_DO -add wave -noupdate -divider Unit -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/A_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/B_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/C_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/ABox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/BBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/CBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/RoundMode_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Op_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/OpMod_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/VectorialOp_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FpFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/InValid_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/InReady_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Flush_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Z_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Status_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Tag_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/Zext_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/OutValid_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FmtInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FmtOutResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FmtOutStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FmtOutTags_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FmtOutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FmtOutReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FmtOutResult2d_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/ArbInResults_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/FmtOutTags2d_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/ArbInStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/ArbInTags_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/ArbInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/ArbInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/OutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/OutputProcessed_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/RoundRobin_SP -add wave -noupdate -expand -group Wrapper -expand -group Top -group AddMul /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_addmul_block/RoundRobin_SN -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/A_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/ABox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/RoundMode_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/SrcFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/DstFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InValid_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InReady_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Flush_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Z_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Status_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Tag_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Zext_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/OutValid_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/SrcFmt_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/DstFmt_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Sign_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f -expand /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/FmtInputExp_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InputExp_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f -expand /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/FmtInputMant_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InputMant_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InputMantZero_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InputZero_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InputInf_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InputNan_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/SigNan_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InputNormal_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/OFBeforeRound_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/OFAfterRound_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/UFAfterRound_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/SpecialRes_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/SpecialResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/SpecialStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/MantLeadingZeroes_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/ExpNormShift_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InternalExp_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/InternalMant_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f -radix decimal /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/DestExp_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/FinalExp_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/MantPreshift_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/ShiftedMant_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/FinalMant_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f -radix decimal /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/MantShamt_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/FmtPreRndRes_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/PreRndRes_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/RoundSticky_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/ResRounded_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/ResRoundedSignCorr_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/RegularStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Result_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -group f2f /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/g_f2f/i_fp_f2fcasts/Status_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 -divider -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/A_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/ABox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/RoundMode_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Op_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/OpMod_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/FpFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/FpFmt2_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/IntFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/InValid_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/InReady_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Flush_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Z_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Status_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Tag_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Zext_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/OutValid_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/OutReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2IInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/I2FInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2FInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2IInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/I2FInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2FInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2IOutResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/I2FOutResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2FOutResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2IOutStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/I2FOutStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2FOutStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2IResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/I2FResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2FResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2IOutTag_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/I2FOutTag_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2FOutTag_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2IZext_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/I2FZext_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2FZext_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2IOutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/I2FOutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/F2FOutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Result_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Status_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/Zext_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/TagInt_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/TagIntPiped_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi -group Lane0 /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_conv_multi/OutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/A_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/B_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/C_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/ABox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/BBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/CBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/RoundMode_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Op_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/OpMod_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/FpFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/FpFmt2_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/IntFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/VectorialOp_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/InValid_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/InReady_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Flush_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Z_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Status_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Tag_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Zext_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/OutValid_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/Target_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/SrcFmtWidth_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/DstFmtSlv_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/IsDstFmtInt_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/SrcShift_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/DstShift_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/DstCPK_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/TagInt_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/VecTag_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/DstVecTag_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/VectorialOp_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/TargetInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/TargetOutReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/FmtOpResults_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/IntFmtOpResults_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/LaneResults_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/ResultVectorial_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/IsResultFmtInt_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/IsResultCPK_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/ResultShift_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/ResultFpFmt_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/ResultIntFmt_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/LaneStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/LaneOutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/LaneInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/LaneZext_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/LaneTags_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/TargetDelayed_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv -expand -group Multi /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/g_mergedOps/i_conv_multifmt_slice/PackedResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/A_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/B_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/C_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/ABox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/BBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/CBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/RoundMode_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Op_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/OpMod_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FpFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FpFmt2_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/IntFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/VectorialOp_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/InValid_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/InReady_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Flush_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Z_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Status_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Tag_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/Zext_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/OutValid_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtOutResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtOutStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtOutTags_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtOutZext_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtOutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtOutReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtOutResult2d_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/ArbInResults_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/FmtOutTags2d_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/ArbInStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/ArbInTags_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/ArbInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/ArbInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/OutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/OutputProcessed_S -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/ArbOutTag_D -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/RoundRobin_SP -add wave -noupdate -expand -group Wrapper -expand -group Top -group Conv /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_conv_block/RoundRobin_SN -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Rst_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Div_start_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Sqrt_start_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Operand_a_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Operand_b_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/RM_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Precision_ctl_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Format_sel_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Kill_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Result_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Fflags_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Ready_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Done_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Exp_a_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Exp_b_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Mant_a_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Mant_b_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Exp_z_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Mant_z_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Sign_z_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Start_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/RM_dly_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Div_enable_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Sqrt_enable_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Inf_a_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Inf_b_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Zero_a_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Zero_b_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/NaN_a_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/NaN_b_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/SNaN_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Special_case_SB -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Special_case_dly_SB -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/Full_precision_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/FP32_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/FP64_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/FP16_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -expand -group divsqrt_inst /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_divsqrt/FP16ALT_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/A_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/B_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/ABox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/BBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/RoundMode_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Op_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/OpMod_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/FpFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/InValid_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/InReady_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Flush_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Z_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Status_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Tag_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Zext_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/OutValid_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/InReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/IsInFP8_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/DivValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/SqrtValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/DivSqrtReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/A_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/B_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/Fmt_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/DivSqrtDone_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/DivSqrtResultPre_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/DivSqrtResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/DivSqrtStatusSlv_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/DivSqrtStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/CurrentTag_DP -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/IsOutFP8_SP -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/HoldResult_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/HoldResult_DP -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/HoldStatus_DP -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/PipeInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/PipeInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/PipeInDataSel_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/PipeInResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/PipeInStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/State_DP -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/State_DN -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/Result_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/Status_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/InValid_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/InReady_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/Flush_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/ResultPiped_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/StatusPiped_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/TagPiped_DO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/OutValid_SO -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/ResPipe_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/StatPipe_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe -expand /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/TagPipe_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/ValidPipe_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt -expand -group Wrapper -group divPipe /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/g_mergedOps/i_divsqrt_multifmt_slice/g_sliceLanes(0)/g_laneInst/i_fp_divsqrt_multi/i_fp_pipe/StageReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/A_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/B_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/C_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/ABox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/BBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/CBox_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/RoundMode_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/OpMod_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/FpFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/VectorialOp_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt 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-noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/FmtInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/FmtOutResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/FmtOutStatus_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/FmtOutTags_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt 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/ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/OutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/OutputProcessed_S -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/ArbOutTag_D -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/RoundRobin_SP -add wave -noupdate -expand -group Wrapper -expand -group Top -expand -group DivSqrt /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/i_divsqrt_block/RoundRobin_SN -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Clk_CI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Reset_RBI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/A_DI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/B_DI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/C_DI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/RoundMode_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Op_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpMod_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/VectorialOp_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/FpFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/FpFmt2_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/IntFmt_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Tag_DI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Flush_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/InValid_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/InReady_SO -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Z_DO -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Status_DO -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OutValid_SO -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OutReady_SI -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/Tag_DO -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpGrpInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpGrpInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/ABox_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/BBox_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/CBox_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/AddMulResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/DivSqrtResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/NonCompResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/ConvResult_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpGrpOutResults_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpGrpOutStatuses_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpGrpOutTags_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpGrpOutZext_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpGrpOutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OpGrpOutReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/ArbInResults_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/ArbInStatuses_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/ArbInTags_D -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/ArbInValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/ArbInReady_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OutValid_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/OutputProcessed_S -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/RoundRobin_SP -add wave -noupdate -expand -group Wrapper -expand -group Top /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpnew_top_i/i_fpnew/RoundRobin_SN -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/clk_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/rst_ni -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/flush_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/trans_id_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fu_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_valid_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_ready_o -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operator_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_a_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_b_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_c_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_fmt_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_rm_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_frm_i -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_trans_id_o -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/result_o -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_valid_o -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_exception_o -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_a_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_a_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_a -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_b_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_b_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_b -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_c_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_c_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/operand_c -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_op_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_op_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_op -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_op_mod_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_op_mod_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_op_mod -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_fmt_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_fmt_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_fmt -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_fmt2_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_fmt2_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_fmt2 -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_ifmt_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_ifmt_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_ifmt -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_rm_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_rm_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_rm -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_vec_op_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_vec_op_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_vec_op -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_tag_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_tag_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_tag -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_in_ready -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_in_valid -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_out_ready -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_out_valid -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_status -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/state_q -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/state_d -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/hold_inputs -add wave -noupdate -expand -group Wrapper /ariane_tb/dut/i_ariane/ex_stage_i/fpu_gen/fpu_i/use_hold -add wave -noupdate -divider Ariane -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/clk_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rst_ni -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/flush_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/issue_instr_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/issue_instr_valid_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/issue_ack_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs1_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs1_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs1_valid_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs2_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs2_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs2_valid_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs3_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs3_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rs3_valid_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rd_clobber_gpr_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rd_clobber_fpr_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fu_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operator_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_a_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_b_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/imm_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/trans_id_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/pc_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/is_compressed_instr_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/alu_ready_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/alu_valid_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/branch_valid_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/branch_predict_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/lsu_ready_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/lsu_valid_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/mult_ready_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/mult_valid_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_ready_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_valid_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_fmt_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_rm_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/csr_valid_o -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/waddr_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/wdata_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/we_gpr_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/we_fpr_i -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/stall -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fu_busy -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_a_regfile -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_b_regfile -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_c_regfile -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_a_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_a_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_b_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operand_b_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/imm_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/imm_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/alu_valid_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/alu_valid_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/mult_valid_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/mult_valid_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_valid_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_valid_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_fmt_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_fmt_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_rm_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fpu_rm_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/lsu_valid_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/lsu_valid_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/csr_valid_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/csr_valid_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/branch_valid_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/branch_valid_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/trans_id_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/trans_id_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operator_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/operator_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fu_n -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fu_q -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/forward_rs1 -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/forward_rs2 -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/forward_rs3 -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/orig_instr -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/rdata -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/raddr_pack -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/waddr_pack -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/wdata_pack -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/we_pack -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands -expand /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fprdata -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fp_raddr_pack -add wave -noupdate -expand -group {Issue stage} -group Issue_Read_Operands /ariane_tb/dut/i_ariane/issue_stage_i/i_issue_read_operands/fp_wdata_pack -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/clk_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rst_ni -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/flush_unissued_instr_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/flush_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/decoded_instr_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/decoded_instr_valid_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/is_ctrl_flow_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/decoded_instr_ack_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/fu_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/operator_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/operand_a_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/operand_b_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/imm_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/trans_id_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/pc_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/is_compressed_instr_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/alu_ready_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/alu_valid_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/resolve_branch_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/lsu_ready_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/lsu_valid_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/branch_valid_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/branch_predict_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/mult_ready_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/mult_valid_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/fpu_ready_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/fpu_valid_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/fpu_fmt_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/fpu_rm_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/csr_valid_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/trans_id_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/resolved_branch_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/wbdata_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/ex_ex_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/wb_valid_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/waddr_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/wdata_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/we_gpr_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/we_fpr_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/commit_instr_o -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/commit_ack_i -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rd_clobber_gpr_sb_iro -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rd_clobber_fpr_sb_iro -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs1_iro_sb -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs1_sb_iro -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs1_valid_sb_iro -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs2_iro_sb -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs2_sb_iro -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs2_valid_iro_sb -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs3_iro_sb -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs3_sb_iro -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/rs3_valid_iro_sb -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/issue_instr_rename_sb -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/issue_instr_valid_rename_sb -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/issue_ack_sb_rename -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/issue_instr_sb_iro -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/issue_instr_valid_sb_iro -add wave -noupdate -expand -group {Issue stage} /ariane_tb/dut/i_ariane/issue_stage_i/issue_ack_iro_sb -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/clk_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rst_ni -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/flush_unissued_instr_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/flush_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/unresolved_branch_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rd_clobber_gpr_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rd_clobber_fpr_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs1_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs1_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs1_valid_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs2_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs2_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs2_valid_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs3_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs3_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/rs3_valid_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/commit_instr_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/commit_ack_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/decoded_instr_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/decoded_instr_valid_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/decoded_instr_ack_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/issue_instr_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/issue_instr_valid_o -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/issue_ack_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/trans_id_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/wbdata_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/ex_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/wb_valid_i -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/issue_cnt_n -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/issue_cnt_q -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/issue_pointer_n -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/issue_pointer_q -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/commit_pointer_n -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/commit_pointer_q -add wave -noupdate -expand -group {Issue stage} -group ScoreBoard /ariane_tb/dut/i_ariane/issue_stage_i/i_scoreboard/issue_full -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/clk_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/rst_ni -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/flush_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fu_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/operator_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/operand_a_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/operand_b_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/imm_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/trans_id_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/pc_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/is_compressed_instr_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/alu_ready_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/alu_valid_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/alu_valid_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/alu_result_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/alu_trans_id_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/alu_exception_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/branch_valid_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/branch_predict_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/resolved_branch_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/resolve_branch_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/csr_valid_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/csr_addr_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/csr_commit_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_ready_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_valid_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_valid_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_result_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_trans_id_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_commit_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_commit_ready_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_exception_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/no_st_pending_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/amo_valid_commit_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/mult_ready_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/mult_valid_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/mult_trans_id_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/mult_result_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/mult_valid_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_ready_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_valid_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_fmt_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_rm_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_frm_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_trans_id_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_result_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_valid_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/fpu_exception_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/enable_translation_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/en_ld_st_translation_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/flush_tlb_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/priv_lvl_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/ld_st_priv_lvl_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/sum_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/mxr_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/satp_ppn_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/asid_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/icache_areq_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/icache_areq_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/dcache_req_ports_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/dcache_req_ports_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/amo_req_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/amo_resp_i -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/itlb_miss_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/dtlb_miss_o -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/alu_branch_res -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/alu_data -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/mult_data -add wave -noupdate -group {EX stage} /ariane_tb/dut/i_ariane/ex_stage_i/lsu_data -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/pc_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/is_compressed_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/is_illegal_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/instruction_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/branch_predict_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/ex_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/priv_lvl_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/debug_mode_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/fs_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/frm_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/tvm_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/tw_i -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/tsr_i -add wave -noupdate -expand -group Decoder -expand /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/instruction_o -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/is_control_flow_instr_o -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/illegal_instr -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/ecall -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/ebreak -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/check_fprm -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/instr -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/imm_select -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/imm_i_type -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/imm_s_type -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/imm_sb_type -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/imm_u_type -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/imm_uj_type -add wave -noupdate -expand -group Decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/imm_bi_type -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 6} {25911563 ns} 1} {{Cursor 3} {25812676 ns} 0} -quietly wave cursor active 2 -configure wave -namecolwidth 259 -configure wave -valuecolwidth 178 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {25810978 ns} {25815752 ns} diff --git a/include/ariane_axi_pkg.sv b/include/ariane_axi_pkg.sv new file mode 100644 index 0000000000..d06c90b5ea --- /dev/null +++ b/include/ariane_axi_pkg.sv @@ -0,0 +1,107 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: ariane_axi_pkg.sv + * Author: Florian Zaruba + * Date: 17.8.2018 + * + * Description: Contains Ariane's AXI ports, does not contain user ports + */ + +package ariane_axi; + + // used in axi_adapter.sv + typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } ad_req_t; + + // 4 is recommended by AXI standard, so lets stick to it, do not change + localparam IdWidth = 4; + localparam UserWidth = 1; + localparam AddrWidth = 64; + localparam DataWidth = 64; + localparam StrbWidth = DataWidth / 8; + + typedef logic [IdWidth-1:0] id_t; + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [StrbWidth-1:0] strb_t; + typedef logic [UserWidth-1:0] user_t; + + // AW Channel + typedef struct packed { + id_t id; + addr_t addr; + axi_pkg::len_t len; + axi_pkg::size_t size; + axi_pkg::burst_t burst; + logic lock; + axi_pkg::cache_t cache; + axi_pkg::prot_t prot; + axi_pkg::qos_t qos; + axi_pkg::region_t region; + axi_pkg::atop_t atop; + } aw_chan_t; + + // W Channel + typedef struct packed { + data_t data; + strb_t strb; + logic last; + } w_chan_t; + + // B Channel + typedef struct packed { + id_t id; + axi_pkg::resp_t resp; + } b_chan_t; + + // AR Channel + typedef struct packed { + id_t id; + addr_t addr; + axi_pkg::len_t len; + axi_pkg::size_t size; + axi_pkg::burst_t burst; + logic lock; + axi_pkg::cache_t cache; + axi_pkg::prot_t prot; + axi_pkg::qos_t qos; + axi_pkg::region_t region; + } ar_chan_t; + + // R Channel + typedef struct packed { + id_t id; + data_t data; + axi_pkg::resp_t resp; + logic last; + } r_chan_t; + + typedef struct packed { + aw_chan_t aw; + logic aw_valid; + w_chan_t w; + logic w_valid; + logic b_ready; + ar_chan_t ar; + logic ar_valid; + logic r_ready; + } req_t; + + typedef struct packed { + logic aw_ready; + logic ar_ready; + logic w_ready; + logic b_valid; + b_chan_t b; + logic r_valid; + r_chan_t r; + } resp_t; + +endpackage diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv index 7db67cb16f..b48bc082a9 100644 --- a/include/ariane_pkg.sv +++ b/include/ariane_pkg.sv @@ -16,6 +16,15 @@ * in one package. */ +// this is needed to propagate the +// configuration in case Ariane is +// instantiated in OpenPiton +`ifdef PITON_ARIANE +`ifndef AXI64_CACHE_PORTS + `include "l15.tmp.h" +`endif +`endif + package ariane_pkg; // --------------- @@ -24,15 +33,33 @@ package ariane_pkg; localparam NR_SB_ENTRIES = 8; // number of scoreboard entries localparam TRANS_ID_BITS = $clog2(NR_SB_ENTRIES); // depending on the number of scoreboard entries we need that many bits // to uniquely identify the entry in the scoreboard - localparam NR_WB_PORTS = 4; localparam ASID_WIDTH = 1; - localparam BTB_ENTRIES = 8; - localparam BHT_ENTRIES = 32; + localparam BTB_ENTRIES = 64; + localparam BHT_ENTRIES = 128; localparam RAS_DEPTH = 2; localparam BITS_SATURATION_COUNTER = 2; localparam NR_COMMIT_PORTS = 2; - localparam ENABLE_RENAME = 1'b1; + localparam ENABLE_RENAME = 1'b0; + + localparam ISSUE_WIDTH = 1; + // amount of pipeline registers inserted for load/store return path + // this can be tuned to trade-off IPC vs. cycle time + localparam NR_LOAD_PIPE_REGS = 1; + localparam NR_STORE_PIPE_REGS = 0; + + // depth of store-buffers, this needs to be a power of two + localparam int unsigned DEPTH_SPEC = 4; + +`ifdef PITON_ARIANE + // in this case we can use a small commit queue since we have a write buffer in the dcache + // we could in principle do without the commit queue in this case, but the timing degrades if we do that due + // to longer paths into the commit stage + localparam int unsigned DEPTH_COMMIT = 2; +`else + // allocate more space for the commit buffer to be on the save side, this needs to be a power of two + localparam int unsigned DEPTH_COMMIT = 8; +`endif // Floating-point extensions configuration localparam bit RVF = 1'b0; // Is F extension enabled @@ -92,11 +119,12 @@ package ariane_pkg; // 32 registers + 1 bit for re-naming = 6 localparam REG_ADDR_SIZE = 6; + localparam NR_WB_PORTS = 4; // static debug hartinfo localparam dm::hartinfo_t DebugHartInfo = '{ zero1: '0, - nscratch: 1, // DTM currently needs at least one scratch register + nscratch: 2, // Debug module needs at least two scratch regs zero0: '0, dataaccess: 1'b1, // data registers are memory mapped in the debugger datasize: dm::DataCount, @@ -111,7 +139,34 @@ package ariane_pkg; // where coherence is not necessary this can improve performance. This needs to be switched on // when more than one core is in a system localparam logic INVALIDATE_ON_FLUSH = 1'b1; - + // enable performance cycle counter, if set to zero mcycle will be incremented + // with instret (non RISC-V conformal) + localparam bit ENABLE_CYCLE_COUNT = 1'b1; + // mark WIF as nop + localparam bit ENABLE_WFI = 1'b1; + // Spike zeros tval on all exception except memory faults + localparam bit ZERO_TVAL = 1'b0; + + // read mask for SSTATUS over MMSTATUS + localparam logic [63:0] SMODE_STATUS_READ_MASK = riscv::SSTATUS_UIE + | riscv::SSTATUS_SIE + | riscv::SSTATUS_SPIE + | riscv::SSTATUS_SPP + | riscv::SSTATUS_FS + | riscv::SSTATUS_XS + | riscv::SSTATUS_SUM + | riscv::SSTATUS_MXR + | riscv::SSTATUS_UPIE + | riscv::SSTATUS_SPIE + | riscv::SSTATUS_UXL + | riscv::SSTATUS64_SD; + + localparam logic [63:0] SMODE_STATUS_WRITE_MASK = riscv::SSTATUS_SIE + | riscv::SSTATUS_SPIE + | riscv::SSTATUS_SPP + | riscv::SSTATUS_FS + | riscv::SSTATUS_SUM + | riscv::SSTATUS_MXR; // --------------- // Fetch Stage // --------------- @@ -119,6 +174,8 @@ package ariane_pkg; // leave as is (fails with >8 entries and wider fetch width) localparam int unsigned FETCH_FIFO_DEPTH = 8; localparam int unsigned FETCH_WIDTH = 32; + // maximum instructions we can fetch on one request (we support compressed instructions) + localparam int unsigned INSTR_PER_FETCH = FETCH_WIDTH / 16; // Only use struct when signals have same direction // exception @@ -139,7 +196,6 @@ package ariane_pkg; logic [63:0] target_address; // target address at which to jump, or not logic is_mispredict; // set if this was a mis-predict logic is_taken; // branch is taken - logic is_lower_16; // branch instruction is compressed and resides // in the lower 16 bit of the word logic valid; // prediction with all its values is valid logic clear; // invalidate this entry @@ -153,7 +209,6 @@ package ariane_pkg; logic valid; // this is a valid hint logic [63:0] predict_address; // target address at which to jump, or not logic predict_taken; // branch is taken - logic is_lower_16; // branch instruction is compressed and resides // in the lower 16 bit of the word cf_t cf_type; // Type of control flow change } branchpredict_sbe_t; @@ -162,14 +217,12 @@ package ariane_pkg; logic valid; logic [63:0] pc; // update at PC logic [63:0] target_address; - logic is_lower_16; logic clear; } btb_update_t; typedef struct packed { logic valid; logic [63:0] target_address; - logic is_lower_16; } btb_prediction_t; typedef struct packed { @@ -208,17 +261,58 @@ package ariane_pkg; // Cache config // --------------- - // I$ - localparam int unsigned ICACHE_INDEX_WIDTH = 12; // in bit - localparam int unsigned ICACHE_TAG_WIDTH = 44; // in bit - localparam int unsigned ICACHE_SET_ASSOC = 4; - localparam int unsigned ICACHE_LINE_WIDTH = 128; // in bit + // if serpent pulp is used standalone (outside of openpiton) + // we just use the default config of ariane + // otherwise we have to propagate the openpiton L15 configuration from l15.h +`ifdef PITON_ARIANE + +`ifndef CONFIG_L1I_CACHELINE_WIDTH + `define CONFIG_L1I_CACHELINE_WIDTH 128 +`endif + +`ifndef CONFIG_L1I_ASSOCIATIVITY + `define CONFIG_L1I_ASSOCIATIVITY 4 +`endif + +`ifndef CONFIG_L1I_SIZE + `define CONFIG_L1I_SIZE 16*1024 +`endif +`ifndef CONFIG_L1D_CACHELINE_WIDTH + `define CONFIG_L1D_CACHELINE_WIDTH 128 +`endif + +`ifndef CONFIG_L1D_ASSOCIATIVITY + `define CONFIG_L1D_ASSOCIATIVITY 4 +`endif + +`ifndef CONFIG_L1D_SIZE + `define CONFIG_L1D_SIZE 16*1024 +`endif + + // I$ + localparam int unsigned ICACHE_LINE_WIDTH = `CONFIG_L1I_CACHELINE_WIDTH; + localparam int unsigned ICACHE_SET_ASSOC = `CONFIG_L1I_ASSOCIATIVITY; + localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(`CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); + localparam int unsigned ICACHE_TAG_WIDTH = 56 - ICACHE_INDEX_WIDTH; + // D$ + localparam int unsigned DCACHE_LINE_WIDTH = `CONFIG_L1D_CACHELINE_WIDTH; + localparam int unsigned DCACHE_SET_ASSOC = `CONFIG_L1D_ASSOCIATIVITY; + localparam int unsigned DCACHE_INDEX_WIDTH = $clog2(`CONFIG_L1D_SIZE / DCACHE_SET_ASSOC); + localparam int unsigned DCACHE_TAG_WIDTH = 56 - DCACHE_INDEX_WIDTH; +`else + // align to openpiton for the time being (this should be more configurable in the future) + // I$ + localparam int unsigned ICACHE_INDEX_WIDTH = 12; // in bit + localparam int unsigned ICACHE_TAG_WIDTH = 44; // in bit + localparam int unsigned ICACHE_LINE_WIDTH = 128; // in bit + localparam int unsigned ICACHE_SET_ASSOC = 4; // D$ - localparam int unsigned DCACHE_INDEX_WIDTH = 12; - localparam int unsigned DCACHE_TAG_WIDTH = 44; - localparam int unsigned DCACHE_LINE_WIDTH = 128; - localparam int unsigned DCACHE_SET_ASSOC = 8; + localparam int unsigned DCACHE_INDEX_WIDTH = 12; // in bit + localparam int unsigned DCACHE_TAG_WIDTH = 44; // in bit + localparam int unsigned DCACHE_LINE_WIDTH = 128; // in bit + localparam int unsigned DCACHE_SET_ASSOC = 8; +`endif // --------------- // EX Stage @@ -262,10 +356,12 @@ package ariane_pkg; } fu_op; typedef struct packed { - fu_op operator; - logic [63:0] operand_a; - logic [63:0] operand_b; - logic [63:0] imm; + fu_t fu; + fu_op operator; + logic [63:0] operand_a; + logic [63:0] operand_b; + logic [63:0] imm; + logic [TRANS_ID_BITS-1:0] trans_id; } fu_data_t; // ------------------------------- @@ -356,12 +452,20 @@ package ariane_pkg; // --------------- // IF/ID Stage // --------------- + typedef struct packed { + logic [63:0] address; // the address of the instructions from below + logic [FETCH_WIDTH-1:0] instruction; // instruction word + branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path + logic [INSTR_PER_FETCH-1:0] bp_taken; // at which instruction is this branch taken? + logic page_fault; // an instruction page fault happened + } frontend_fetch_t; + // store the decompressed instruction typedef struct packed { - logic [63:0] address; // the address of the instructions from below - logic [31:0] instruction; // instruction word - branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path - exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions + logic [63:0] address; // the address of the instructions from below + logic [31:0] instruction; // instruction word + branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path + exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions } fetch_entry_t; // --------------- @@ -394,8 +498,20 @@ package ariane_pkg; // Atomics // -------------------- typedef enum logic [3:0] { - AMO_NONE, AMO_LR, AMO_SC, AMO_SWAP, AMO_ADD, AMO_AND, - AMO_OR, AMO_XOR, AMO_MAX, AMO_MAXU, AMO_MIN, AMO_MINU + AMO_NONE =4'b0000, + AMO_LR =4'b0001, + AMO_SC =4'b0010, + AMO_SWAP =4'b0011, + AMO_ADD =4'b0100, + AMO_AND =4'b0101, + AMO_OR =4'b0110, + AMO_XOR =4'b0111, + AMO_MAX =4'b1000, + AMO_MAXU =4'b1001, + AMO_MIN =4'b1010, + AMO_MINU =4'b1011, + AMO_CAS1 =4'b1100, // unused, not part of riscv spec, but provided in OpenPiton + AMO_CAS2 =4'b1101 // unused, not part of riscv spec, but provided in OpenPiton } amo_t; typedef struct packed { @@ -408,6 +524,7 @@ package ariane_pkg; } tlb_update_t; localparam logic [3:0] MODE_SV39 = 4'h8; + localparam logic [3:0] MODE_OFF = 4'h0; // Bits required for representation of physical address space as 4K pages // (e.g. 27*4K == 39bit address space). @@ -476,9 +593,9 @@ package ariane_pkg; } dcache_req_i_t; typedef struct packed { - logic data_gnt; - logic data_rvalid; - logic [63:0] data_rdata; + logic data_gnt; + logic data_rvalid; + logic [63:0] data_rdata; } dcache_req_o_t; // ---------------------- diff --git a/include/riscv_pkg.sv b/include/riscv_pkg.sv index ba5fdf34b7..b9a94c315a 100644 --- a/include/riscv_pkg.sv +++ b/include/riscv_pkg.sv @@ -96,9 +96,6 @@ package riscv; logic [43:0] ppn; } satp_t; - // read mask for SSTATUS over MMSTATUS - localparam logic [63:0] SMODE_STATUS_MASK = 64'h80000003000DE133; - // -------------------- // Instruction Types // -------------------- @@ -273,6 +270,8 @@ package riscv; localparam logic [11:0] PERF_CALL = 12'h9; // Procedure call localparam logic [11:0] PERF_RET = 12'hA; // Procedure Return localparam logic [11:0] PERF_MIS_PREDICT = 12'hB; // Branch mis-predicted + localparam logic [11:0] PERF_SB_FULL = 12'hC; // Scoreboard full + localparam logic [11:0] PERF_IF_EMPTY = 12'hD; // instruction fetch queue empty // ---------------------- // Virtual Memory @@ -310,12 +309,26 @@ package riscv; localparam logic [63:0] LOAD_PAGE_FAULT = 13; // Load page fault localparam logic [63:0] STORE_PAGE_FAULT = 15; // Store page fault - localparam logic [63:0] S_SW_INTERRUPT = (1 << 63) | 1; - localparam logic [63:0] M_SW_INTERRUPT = (1 << 63) | 3; - localparam logic [63:0] S_TIMER_INTERRUPT = (1 << 63) | 5; - localparam logic [63:0] M_TIMER_INTERRUPT = (1 << 63) | 7; - localparam logic [63:0] S_EXT_INTERRUPT = (1 << 63) | 9; - localparam logic [63:0] M_EXT_INTERRUPT = (1 << 63) | 11; + localparam int unsigned IRQ_S_SOFT = 1; + localparam int unsigned IRQ_M_SOFT = 3; + localparam int unsigned IRQ_S_TIMER = 5; + localparam int unsigned IRQ_M_TIMER = 7; + localparam int unsigned IRQ_S_EXT = 9; + localparam int unsigned IRQ_M_EXT = 11; + + localparam logic [63:0] MIP_SSIP = (1 << IRQ_S_SOFT); + localparam logic [63:0] MIP_MSIP = (1 << IRQ_M_SOFT); + localparam logic [63:0] MIP_STIP = (1 << IRQ_S_TIMER); + localparam logic [63:0] MIP_MTIP = (1 << IRQ_M_TIMER); + localparam logic [63:0] MIP_SEIP = (1 << IRQ_S_EXT); + localparam logic [63:0] MIP_MEIP = (1 << IRQ_M_EXT); + + localparam logic [63:0] S_SW_INTERRUPT = (1 << 63) | IRQ_S_SOFT; + localparam logic [63:0] M_SW_INTERRUPT = (1 << 63) | IRQ_M_SOFT; + localparam logic [63:0] S_TIMER_INTERRUPT = (1 << 63) | IRQ_S_TIMER; + localparam logic [63:0] M_TIMER_INTERRUPT = (1 << 63) | IRQ_M_TIMER; + localparam logic [63:0] S_EXT_INTERRUPT = (1 << 63) | IRQ_S_EXT; + localparam logic [63:0] M_EXT_INTERRUPT = (1 << 63) | IRQ_M_EXT; // ----- // CSRs @@ -391,6 +404,43 @@ package riscv; CSR_MIS_PREDICT = PERF_MIS_PREDICT + 12'hC03 } csr_reg_t; + localparam logic [63:0] SSTATUS_UIE = 64'h00000001; + localparam logic [63:0] SSTATUS_SIE = 64'h00000002; + localparam logic [63:0] SSTATUS_SPIE = 64'h00000020; + localparam logic [63:0] SSTATUS_SPP = 64'h00000100; + localparam logic [63:0] SSTATUS_FS = 64'h00006000; + localparam logic [63:0] SSTATUS_XS = 64'h00018000; + localparam logic [63:0] SSTATUS_SUM = 64'h00040000; + localparam logic [63:0] SSTATUS_MXR = 64'h00080000; + localparam logic [63:0] SSTATUS_UPIE = 64'h00000010; + localparam logic [63:0] SSTATUS_UXL = 64'h0000000300000000; + localparam logic [63:0] SSTATUS64_SD = 64'h8000000000000000; + localparam logic [63:0] SSTATUS32_SD = 64'h80000000; + + localparam logic [63:0] MSTATUS_UIE = 64'h00000001; + localparam logic [63:0] MSTATUS_SIE = 64'h00000002; + localparam logic [63:0] MSTATUS_HIE = 64'h00000004; + localparam logic [63:0] MSTATUS_MIE = 64'h00000008; + localparam logic [63:0] MSTATUS_UPIE = 64'h00000010; + localparam logic [63:0] MSTATUS_SPIE = 64'h00000020; + localparam logic [63:0] MSTATUS_HPIE = 64'h00000040; + localparam logic [63:0] MSTATUS_MPIE = 64'h00000080; + localparam logic [63:0] MSTATUS_SPP = 64'h00000100; + localparam logic [63:0] MSTATUS_HPP = 64'h00000600; + localparam logic [63:0] MSTATUS_MPP = 64'h00001800; + localparam logic [63:0] MSTATUS_FS = 64'h00006000; + localparam logic [63:0] MSTATUS_XS = 64'h00018000; + localparam logic [63:0] MSTATUS_MPRV = 64'h00020000; + localparam logic [63:0] MSTATUS_SUM = 64'h00040000; + localparam logic [63:0] MSTATUS_MXR = 64'h00080000; + localparam logic [63:0] MSTATUS_TVM = 64'h00100000; + localparam logic [63:0] MSTATUS_TW = 64'h00200000; + localparam logic [63:0] MSTATUS_TSR = 64'h00400000; + localparam logic [63:0] MSTATUS32_SD = 64'h80000000; + localparam logic [63:0] MSTATUS_UXL = 64'h0000000300000000; + localparam logic [63:0] MSTATUS_SXL = 64'h0000000C00000000; + localparam logic [63:0] MSTATUS64_SD = 64'h8000000000000000; + typedef enum logic [2:0] { CSRRW = 3'h1, CSRRS = 3'h2, @@ -513,4 +563,15 @@ package riscv; end endfunction // pragma translate_on + + typedef struct { + byte priv; + longint unsigned pc; + byte is_fp; + byte rd; + longint unsigned data; + int unsigned instr; + byte was_exception; + } commit_log_t; + endpackage diff --git a/include/serpent_cache_pkg.sv b/include/serpent_cache_pkg.sv new file mode 100644 index 0000000000..9d192de170 --- /dev/null +++ b/include/serpent_cache_pkg.sv @@ -0,0 +1,364 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: Package for OpenPiton compatible L1 cache subsystem + +// this is needed to propagate the +// configuration in case Ariane is +// instantiated in OpenPiton +`ifdef PITON_ARIANE +`ifndef AXI64_CACHE_PORTS + `include "l15.tmp.h" + `include "define.tmp.h" +`endif +`endif + +package serpent_cache_pkg; + + // these parames need to coincide with the + // L1.5 parameterization, do not change +`ifdef PITON_ARIANE + +`ifndef CONFIG_L15_ASSOCIATIVITY + `define CONFIG_L15_ASSOCIATIVITY 4 +`endif + +`ifndef L15_THREADID_WIDTH + `define L15_THREADID_WIDTH 1 +`endif + +`ifndef TLB_CSM_WIDTH + `define TLB_CSM_WIDTH 33 +`endif + + localparam L15_SET_ASSOC = `CONFIG_L15_ASSOCIATIVITY; + localparam L15_TID_WIDTH = `L15_THREADID_WIDTH; + localparam L15_TLB_CSM_WIDTH = `TLB_CSM_WIDTH; +`else + localparam L15_SET_ASSOC = ariane_pkg::DCACHE_SET_ASSOC;// align with dcache for compatibility with the standard Ariane setup + localparam L15_TID_WIDTH = 2; + localparam L15_TLB_CSM_WIDTH = 33; +`endif + localparam L15_WAY_WIDTH = $clog2(L15_SET_ASSOC); + localparam L1I_WAY_WIDTH = $clog2(ariane_pkg::ICACHE_SET_ASSOC); + localparam L1D_WAY_WIDTH = $clog2(ariane_pkg::DCACHE_SET_ASSOC); + + // FIFO depths of L15 adapter + localparam ADAPTER_REQ_FIFO_DEPTH = 2; + localparam ADAPTER_RTRN_FIFO_DEPTH = 2; + + + // Calculated parameter + localparam ICACHE_OFFSET_WIDTH = $clog2(ariane_pkg::ICACHE_LINE_WIDTH/8); + localparam ICACHE_NUM_WORDS = 2**(ariane_pkg::ICACHE_INDEX_WIDTH-ICACHE_OFFSET_WIDTH); + localparam ICACHE_CL_IDX_WIDTH = $clog2(ICACHE_NUM_WORDS);// excluding byte offset + + localparam DCACHE_OFFSET_WIDTH = $clog2(ariane_pkg::DCACHE_LINE_WIDTH/8); + localparam DCACHE_NUM_WORDS = 2**(ariane_pkg::DCACHE_INDEX_WIDTH-DCACHE_OFFSET_WIDTH); + localparam DCACHE_CL_IDX_WIDTH = $clog2(DCACHE_NUM_WORDS);// excluding byte offset + + localparam DCACHE_NUM_BANKS = ariane_pkg::DCACHE_LINE_WIDTH/64; + + // write buffer parameterization + localparam DCACHE_WBUF_DEPTH = 8; + localparam DCACHE_MAX_TX = 2**L15_TID_WIDTH; + localparam DCACHE_ID_WIDTH = $clog2(DCACHE_MAX_TX); + + + typedef struct packed { + logic [ariane_pkg::DCACHE_INDEX_WIDTH+ariane_pkg::DCACHE_TAG_WIDTH-1:0] wtag; + logic [63:0] data; + logic [7:0] dirty; // byte is dirty + logic [7:0] valid; // byte is valid + logic [7:0] txblock; // byte is part of transaction in-flight + logic checked; // if cache state of this word has been checked + logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] hit_oh; // valid way in the cache + } wbuffer_t; + + // TX status registers are indexed with the transaction ID + // they basically store which bytes from which buffer entry are part + // of that transaction + typedef struct packed { + logic vld; + logic [7:0] be; + logic [$clog2(DCACHE_WBUF_DEPTH)-1:0] ptr; + } tx_stat_t; + + // local interfaces between caches and L15 adapter + typedef enum logic [1:0] { + DCACHE_STORE_REQ, + DCACHE_LOAD_REQ, + DCACHE_ATOMIC_REQ, + DCACHE_INT_REQ + } dcache_out_t; + + typedef enum logic [2:0] { + DCACHE_INV_REQ, // no ack from the core required + DCACHE_STORE_ACK,// note: this may contain an invalidation vector, too + DCACHE_LOAD_ACK, + DCACHE_ATOMIC_ACK, + DCACHE_INT_ACK + } dcache_in_t; + + typedef enum logic [0:0] { + ICACHE_INV_REQ, // no ack from the core required + ICACHE_IFILL_ACK + } icache_in_t; + + typedef struct packed { + logic vld; // invalidate only affected way + logic all; // invalidate all ways + logic [ariane_pkg::ICACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate + logic [L15_WAY_WIDTH-1:0] way; // way to invalidate + } cache_inval_t; + + // icache interface + typedef struct packed { + logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] way; // way to replace + logic [63:0] paddr; // physical address + logic nc; // noncacheable + logic [L15_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + } icache_req_t; + + typedef struct packed { + icache_in_t rtype; // see definitions above + logic [ariane_pkg::ICACHE_LINE_WIDTH-1:0] data; // full cache line width + cache_inval_t inv; // invalidation vector + logic nc; // noncacheable + logic [L15_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + logic f4b; // fetch 4 bytes only (from I/O space) + } icache_rtrn_t; + + // dcache interface + typedef struct packed { + dcache_out_t rtype; // see definitions above + logic [2:0] size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) + logic [L1D_WAY_WIDTH-1:0] way; // way to replace + logic [63:0] paddr; // physical address + logic [63:0] data; // word width of processor (no block stores at the moment) + logic nc; // noncacheable + logic [L15_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + ariane_pkg::amo_t amo_op; // amo opcode + } dcache_req_t; + + typedef struct packed { + dcache_in_t rtype; // see definitions above + logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // full cache line width + cache_inval_t inv; // invalidation vector + logic nc; // noncacheable + logic [L15_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + } dcache_rtrn_t; + + + // taken from iop.h in openpiton + // to l1.5 (only marked subset is used) + typedef enum logic [4:0] { + L15_LOAD_RQ = 5'b00000, // load request + L15_IMISS_RQ = 5'b10000, // instruction fill request + L15_STORE_RQ = 5'b00001, // store request + L15_ATOMIC_RQ = 5'b00110, // atomic op + //L15_CAS1_RQ = 5'b00010, // compare and swap1 packet (OpenSparc atomics) + //L15_CAS2_RQ = 5'b00011, // compare and swap2 packet (OpenSparc atomics) + //L15_SWAP_RQ = 5'b00110, // swap packet (OpenSparc atomics) + L15_STRLOAD_RQ = 5'b00100, // unused + L15_STRST_RQ = 5'b00101, // unused + L15_STQ_RQ = 5'b00111, // unused + L15_INT_RQ = 5'b01001, // interrupt request + L15_FWD_RQ = 5'b01101, // unused + L15_FWD_RPY = 5'b01110, // unused + L15_RSVD_RQ = 5'b11111 // unused + } l15_reqtypes_t; + + // from l1.5 (only marked subset is used) + typedef enum logic [3:0] { + L15_LOAD_RET = 4'b0000, // load packet + // L15_INV_RET = 4'b0011, // invalidate packet, not unique... + L15_ST_ACK = 4'b0100, // store ack packet + //L15_AT_ACK = 4'b0011, // unused, not unique... + L15_INT_RET = 4'b0111, // interrupt packet + L15_TEST_RET = 4'b0101, // unused + L15_FP_RET = 4'b1000, // unused + L15_IFILL_RET = 4'b0001, // instruction fill packet + L15_EVICT_REQ = 4'b0011, // eviction request + L15_ERR_RET = 4'b1100, // unused + L15_STRLOAD_RET = 4'b0010, // unused + L15_STRST_ACK = 4'b0110, // unused + L15_FWD_RQ_RET = 4'b1010, // unused + L15_FWD_RPY_RET = 4'b1011, // unused + L15_RSVD_RET = 4'b1111, // unused + L15_CPX_RESTYPE_ATOMIC_RES = 4'b1110 // custom type for atomic responses + } l15_rtrntypes_t; + + + typedef struct packed { + logic l15_val; // valid signal, asserted with request + logic l15_req_ack; // ack for response + l15_reqtypes_t l15_rqtype; // see below for encoding + logic l15_nc; // non-cacheable bit + logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) + logic [L15_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1 + logic l15_prefetch; // unused in openpiton + logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment + logic l15_blockstore; // unused in openpiton + logic l15_blockinitstore; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_l1rplway; // way to replace + logic [39:0] l15_address; // physical address + logic [63:0] l15_data; // word to write + logic [63:0] l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests) + logic [L15_TLB_CSM_WIDTH-1:0] l15_csm_data; // unused in Ariane + logic [3:0] l15_amo_op; // atomic operation type + } l15_req_t; + + typedef struct packed { + logic l15_ack; // ack for request struct + logic l15_header_ack; // ack for request struct + logic l15_val; // valid signal for return struct + l15_rtrntypes_t l15_returntype; // see below for encoding + logic l15_l2miss; // unused in Ariane + logic [1:0] l15_error; // unused in openpiton + logic l15_noncacheable; // non-cacheable bit + logic l15_atomic; // asserted in load return and store ack packets of atomic tx + logic [L15_TID_WIDTH-1:0] l15_threadid; // used as transaction ID + logic l15_prefetch; // unused in openpiton + logic l15_f4b; // 4byte instruction fill from I/O space (nc). + logic [63:0] l15_data_0; // used for both caches + logic [63:0] l15_data_1; // used for both caches + logic [63:0] l15_data_2; // currently only used for I$ + logic [63:0] l15_data_3; // currently only used for I$ + logic l15_inval_icache_all_way; // invalidate all ways + logic l15_inval_dcache_all_way; // unused in openpiton + logic [15:4] l15_inval_address_15_4; // invalidate selected cacheline + logic l15_cross_invalidate; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_cross_invalidate_way; // unused in openpiton + logic l15_inval_dcache_inval; // invalidate selected cacheline and way + logic l15_inval_icache_inval; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_inval_way; // way to invalidate + logic l15_blockinitstore; // unused in openpiton + } l15_rtrn_t; + + // swap endianess in a 64bit word + function automatic logic[63:0] swendian64(input logic[63:0] in); + automatic logic[63:0] out; + for(int k=0; k<64;k+=8)begin + out[k +: 8] = in[63-k -: 8]; + end + return out; + endfunction + + function automatic logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] icache_way_bin2oh ( + input logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] in + ); + logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] out; + out = '0; + out[in] = 1'b1; + return out; + endfunction + + function automatic logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] dcache_way_bin2oh ( + input logic [$clog2(ariane_pkg::DCACHE_SET_ASSOC)-1:0] in + ); + logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] out; + out = '0; + out[in] = 1'b1; + return out; + endfunction + + function automatic logic [DCACHE_NUM_BANKS-1:0] dcache_cl_bin2oh ( + input logic [$clog2(DCACHE_NUM_BANKS)-1:0] in + ); + logic [DCACHE_NUM_BANKS-1:0] out; + out = '0; + out[in] = 1'b1; + return out; + endfunction + + + function automatic logic [5:0] popcnt64 ( + input logic [63:0] in + ); + logic [5:0] cnt= 0; + foreach (in[k]) begin + cnt += in[k]; + end + return cnt; + endfunction : popcnt64 + + function automatic logic [7:0] toByteEnable8( + input logic [2:0] offset, + input logic [1:0] size + ); + logic [7:0] be; + be = '0; + unique case(size) + 2'b00: be[offset] = '1; // byte + 2'b01: be[offset +:2 ] = '1; // hword + 2'b10: be[offset +:4 ] = '1; // word + default: be = '1; // dword + endcase // size + return be; + endfunction : toByteEnable8 + + // openpiton requires the data to be replicated in case of smaller sizes than dwords + function automatic logic [63:0] repData64( + input logic [63:0] data, + input logic [2:0] offset, + input logic [1:0] size + ); + logic [63:0] out; + unique case(size) + 2'b00: for(int k=0; k<8; k++) out[k*8 +: 8] = data[offset*8 +: 8]; // byte + 2'b01: for(int k=0; k<4; k++) out[k*16 +: 16] = data[offset*8 +: 16]; // hword + 2'b10: for(int k=0; k<2; k++) out[k*32 +: 32] = data[offset*8 +: 32]; // word + default: out = data; // dword + endcase // size + return out; + endfunction : repData64 + + // note: this is openpiton specific. cannot transmit unaligned words. + // hence we default to individual bytes in that case, and they have to be transmitted + // one after the other + function automatic logic [1:0] toSize64( + input logic [7:0] be + ); + logic [1:0] size; + unique case(be) + 8'b1111_1111: size = 2'b11; // dword + 8'b0000_1111, 8'b1111_0000: size = 2'b10; // word + 8'b1100_0000, 8'b0011_0000, 8'b0000_1100, 8'b0000_0011: size = 2'b01; // hword + default: size = 2'b00; // individual bytes + endcase // be + return size; + endfunction : toSize64 + + // align the physical address to the specified size: + // 000: bytes + // 001: hword + // 010: word + // 011: dword + // 111: DCACHE line + function automatic logic [63:0] paddrSizeAlign( + input logic [63:0] paddr, + input logic [2:0] size + ); + logic [63:0] out; + out = paddr; + unique case (size) + 3'b001: out[0:0] = '0; + 3'b010: out[1:0] = '0; + 3'b011: out[2:0] = '0; + 3'b111: out[DCACHE_OFFSET_WIDTH-1:0] = '0; + default: ; + endcase + return out; + endfunction : paddrSizeAlign + +endpackage : serpent_cache_pkg diff --git a/include/std_cache_pkg.sv b/include/std_cache_pkg.sv index f6280b62a5..4a13dbd32e 100644 --- a/include/std_cache_pkg.sv +++ b/include/std_cache_pkg.sv @@ -1,20 +1,18 @@ -// Copyright (c) 2018 ETH Zurich, University of Bologna -// All rights reserved. -// -// This code is under development and not yet released to the public. -// Until it is released, the code is under the copyright of ETH Zurich and -// the University of Bologna, and may contain confidential and/or unpublished -// work. Any reuse/redistribution is strictly forbidden without written -// permission from ETH Zurich. -// -// Bug fixes and contributions will eventually be released under the -// SolderPad open hardware license in the context of the PULP platform -// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the -// University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. // // Author: Florian Zaruba , ETH Zurich // Michael Schaffner , ETH Zurich // Date: 15.08.2018 + +// ******* WIP ******* // Description: package for the standard Ariane cache subsystem. package std_cache_pkg; @@ -25,9 +23,6 @@ package std_cache_pkg; localparam DCACHE_DIRTY_WIDTH = ariane_pkg::DCACHE_SET_ASSOC*2; // localparam DECISION_BIT = 30; // bit on which to decide whether the request is cache-able or not - typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } req_t; - - typedef struct packed { logic [1:0] id; // id for which we handle the miss logic valid; diff --git a/openpiton/ariane_verilog_wrap.sv b/openpiton/ariane_verilog_wrap.sv new file mode 100644 index 0000000000..da5a095ea9 --- /dev/null +++ b/openpiton/ariane_verilog_wrap.sv @@ -0,0 +1,152 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 19.03.2017 +// Description: Ariane Top-level wrapper to break out SV structs to logic vectors. + +// default to AXI64 cache ports if not using the +// serpent PULP extension +`ifndef PITON_ARIANE +`ifndef AXI64_CACHE_PORTS + `define AXI64_CACHE_PORTS +`endif +`endif + +module ariane_verilog_wrap #( + parameter bit SwapEndianess = 1, // swap endianess in l15 adapter + parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region + parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000 // begin of cached region +) ( + input clk_i, + input reset_l, // this is an openpiton-specific name, do not change (hier. paths in TB use this) + output spc_grst_l, // this is an openpiton-specific name, do not change (hier. paths in TB use this) + // Core ID, Cluster ID and boot address are considered more or less static + input [63:0] boot_addr_i, // reset boot address + input [63:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR) + // Interrupt inputs + input [1:0] irq_i, // level sensitive IR lines, mip & sip (async) + input ipi_i, // inter-processor interrupts (async) + // Timer facilities + input time_irq_i, // timer interrupt in (async) + input debug_req_i, // debug request (async) + +`ifdef AXI64_CACHE_PORTS + // AXI (memory side) + output [$size(ariane_axi::req_t)-1:0] axi_req_o, + input [$size(ariane_axi::resp_t)-1:0] axi_resp_i +`else + // L15 (memory side) + output [$size(serpent_cache_pkg::l15_req_t)-1:0] l15_req_o, + input [$size(serpent_cache_pkg::l15_rtrn_t)-1:0] l15_rtrn_i +`endif + ); + +// assign bitvector to packed struct and vice versa +`ifdef AXI64_CACHE_PORTS + ariane_axi::req_t axi_req; + ariane_axi::resp_t axi_resp; + + assign axi_req_o = axi_req; + assign axi_resp = axi_resp_i; +`else + // L15 (memory side) + serpent_cache_pkg::l15_req_t l15_req, l15_req_remapped; + serpent_cache_pkg::l15_rtrn_t l15_rtrn; + + always_comb begin : p_remap + l15_req_remapped = l15_req; + if (l15_req.l15_address < 64'h1000) begin + l15_req_remapped.l15_address = l15_req.l15_address + 64'hfff1000000; + end + end + + assign l15_req_o = l15_req_remapped; + assign l15_rtrn = l15_rtrn_i; +`endif + + // // this is a workaround since interrupts are not fully supported yet. + // // the logic below catches the initial wake up interrupt that enables the cores. + // logic wake_up_d, wake_up_q; + // logic rst_n; + + // assign wake_up_d = wake_up_q || ((l15_rtrn.l15_returntype == serpent_cache_pkg::L15_INT_RET) && l15_rtrn.l15_val); + + // always_ff @(posedge clk_i or negedge reset_l) begin : p_regs + // if(~reset_l) begin + // wake_up_q <= 0; + // end else begin + // wake_up_q <= wake_up_d; + // end + // end + + // // reset gate this + // assign rst_n = wake_up_q & reset_l; + + // this is a workaround, + // we basically wait for 32k cycles such that the SRAMs in openpiton can initialize + // 128KB..8K cycles + // 256KB..16K cycles + // etc, so this should be enough for 512k per tile + + logic [15:0] wake_up_cnt_d, wake_up_cnt_q; + logic rst_n; + + assign wake_up_cnt_d = (wake_up_cnt_q[$high(wake_up_cnt_q)]) ? wake_up_cnt_q : wake_up_cnt_q + 1; + + always_ff @(posedge clk_i or negedge reset_l) begin : p_regs + if(~reset_l) begin + wake_up_cnt_q <= 0; + end else begin + wake_up_cnt_q <= wake_up_cnt_d; + end + end + + // reset gate this + assign rst_n = wake_up_cnt_q[$high(wake_up_cnt_q)] & reset_l; + + // reset_synchronizer #( + // .NUM_REGS(2) + // ) i_sync ( + // .clk_i ( clk_i ), + // .rst_ni ( rst_n ), + // .tmode_i ( 1'b0 ), + // .rst_no ( spc_grst_l ) + // ); + + synchronizer i_sync ( + .clk ( clk_i ), + .presyncdata ( rst_n ), + .syncdata ( spc_grst_l ) + ); + + ariane #( + .SwapEndianess ( SwapEndianess ), + .CachedAddrEnd ( CachedAddrEnd ), + .CachedAddrBeg ( CachedAddrBeg ) + ) ariane ( + .clk_i ( clk_i ), + .rst_ni ( spc_grst_l ), + .boot_addr_i , + .hart_id_i , + .irq_i , + .ipi_i , + .time_irq_i , + .debug_req_i , +`ifdef AXI64_CACHE_PORTS + .axi_req_o ( axi_req ), + .axi_resp_i ( axi_resp ) +`else + .l15_req_o ( l15_req ), + .l15_rtrn_i ( l15_rtrn ) +`endif + ); + +endmodule // ariane_verilog_wrap diff --git a/openpiton/serpent_peripherals.sv b/openpiton/serpent_peripherals.sv new file mode 100644 index 0000000000..8cd32aea70 --- /dev/null +++ b/openpiton/serpent_peripherals.sv @@ -0,0 +1,591 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 14.11.2018 +// Description: Ariane chipset for OpenPiton that includes the bootrom (with DTB), +// debug module, clint and plic. +// +// Note that direct system bus accesses are not yet possible due to a missing +// AXI-lite br_master <-> NOC converter module. +// +// The address bases for the individual peripherals are defined in the +// devices.xml file in OpenPiton, and should be set to +// +// Debug 40'h90_0000_0000 +// Boot Rom 40'h90_0001_0000 +// CLINT 40'h90_0200_0000 +// PLIC 40'h90_0300_0000 +// + +module serpent_peripherals #( + parameter int unsigned DataWidth = 64, + parameter int unsigned NumHarts = 1, + parameter int unsigned NumSources = 1, + parameter bit SwapEndianess = 0 +) ( + input clk_i, + input rst_ni, + input testmode_i, + // connections to OpenPiton NoC filters + // Debug/JTAG + input [DataWidth-1:0] buf_ariane_debug_noc2_data_i, + input buf_ariane_debug_noc2_valid_i, + output ariane_debug_buf_noc2_ready_o, + output [DataWidth-1:0] ariane_debug_buf_noc3_data_o, + output ariane_debug_buf_noc3_valid_o, + input buf_ariane_debug_noc3_ready_i, + // Bootrom + input [DataWidth-1:0] buf_ariane_bootrom_noc2_data_i, + input buf_ariane_bootrom_noc2_valid_i, + output ariane_bootrom_buf_noc2_ready_o, + output [DataWidth-1:0] ariane_bootrom_buf_noc3_data_o, + output ariane_bootrom_buf_noc3_valid_o, + input buf_ariane_bootrom_noc3_ready_i, + // CLINT + input [DataWidth-1:0] buf_ariane_clint_noc2_data_i, + input buf_ariane_clint_noc2_valid_i, + output ariane_clint_buf_noc2_ready_o, + output [DataWidth-1:0] ariane_clint_buf_noc3_data_o, + output ariane_clint_buf_noc3_valid_o, + input buf_ariane_clint_noc3_ready_i, + // PLIC + input [DataWidth-1:0] buf_ariane_plic_noc2_data_i, + input buf_ariane_plic_noc2_valid_i, + output ariane_plic_buf_noc2_ready_o, + output [DataWidth-1:0] ariane_plic_buf_noc3_data_o, + output ariane_plic_buf_noc3_valid_o, + input buf_ariane_plic_noc3_ready_i, + // Debug sigs to cores + output ndmreset_o, // non-debug module reset + output dmactive_o, // debug module is active + output [NumHarts-1:0] debug_req_o, // async debug request + input [NumHarts-1:0] unavailable_i, // communicate whether the hart is unavailable (e.g.: power down) + // JTAG + input tck_i, + input tms_i, + input trst_ni, + input td_i, + output td_o, + output tdo_oe_o, + // CLINT + input rtc_i, // Real-time clock in (usually 32.768 kHz) + output [NumHarts-1:0] timer_irq_o, // Timer interrupts + output [NumHarts-1:0] ipi_o, // software interrupt (a.k.a inter-process-interrupt) + // PLIC + // TODO + input [NumSources-1:0] irq_sources_i, + output [NumHarts-1:0][1:0] irq_o // level sensitive IR lines, mip & sip (async) +); + + localparam int unsigned AxiIdWidth = 0; + localparam int unsigned AxiAddrWidth = 64; + localparam int unsigned AxiDataWidth = 64; + localparam int unsigned AxiUserWidth = 0; + + ///////////////////////////// + // Debug module and JTAG + ///////////////////////////// + + logic jtag_req_valid; + logic debug_req_ready; + logic jtag_resp_ready; + logic jtag_resp_valid; + + dm::dmi_req_t jtag_dmi_req; + dm::dmi_resp_t debug_resp; + + dmi_jtag i_dmi_jtag ( + .clk_i , + .rst_ni , + .testmode_i , + .dmi_req_o ( jtag_dmi_req ), + .dmi_req_valid_o ( jtag_req_valid ), + .dmi_req_ready_i ( debug_req_ready ), + .dmi_resp_i ( debug_resp ), + .dmi_resp_ready_o ( jtag_resp_ready ), + .dmi_resp_valid_i ( jtag_resp_valid ), + .dmi_rst_no ( ), // not connected + .tck_i , + .tms_i , + .trst_ni , + .td_i , + .td_o , + .tdo_oe_o + ); + + ariane_axi::req_t dm_axi_m_req, dm_axi_s_req; + ariane_axi::resp_t dm_axi_m_resp, dm_axi_s_resp; + + // debug module + dm_top #( + // current implementation only supports 1 hart + .NrHarts ( NumHarts ), + .AxiIdWidth ( AxiIdWidth ), + .AxiAddrWidth ( AxiAddrWidth ), + .AxiDataWidth ( AxiDataWidth ), + .AxiUserWidth ( AxiUserWidth ) + ) i_dm_top ( + .clk_i , + .rst_ni , // PoR + .testmode_i , + .ndmreset_o , + .dmactive_o , // active debug session + .debug_req_o , + .unavailable_i , + .axi_s_req_i ( dm_axi_s_req ), + .axi_s_resp_o ( dm_axi_s_resp ), + .axi_m_req_o ( dm_axi_m_req ), + .axi_m_resp_i ( dm_axi_m_resp ), + .dmi_rst_ni ( rst_ni ), + .dmi_req_valid_i ( jtag_req_valid ), + .dmi_req_ready_o ( debug_req_ready ), + .dmi_req_i ( jtag_dmi_req ), + .dmi_resp_valid_o ( jtag_resp_valid ), + .dmi_resp_ready_i ( jtag_resp_ready ), + .dmi_resp_o ( debug_resp ) + ); + + noc_axilite_bridge #( + .SLAVE_RESP_BYTEWIDTH ( 8 ), + .SWAP_ENDIANESS ( SwapEndianess ) + ) i_debug_axilite_bridge ( + .clk ( clk_i ), + .rst ( ~rst_ni ), + // to/from NOC + .splitter_bridge_val ( buf_ariane_debug_noc2_valid_i ), + .splitter_bridge_data ( buf_ariane_debug_noc2_data_i ), + .bridge_splitter_rdy ( ariane_debug_buf_noc2_ready_o ), + .bridge_splitter_val ( ariane_debug_buf_noc3_valid_o ), + .bridge_splitter_data ( ariane_debug_buf_noc3_data_o ), + .splitter_bridge_rdy ( buf_ariane_debug_noc3_ready_i ), + //axi lite signals + //write address channel + .m_axi_awaddr ( dm_axi_s_req.aw.addr ), + .m_axi_awvalid ( dm_axi_s_req.aw_valid ), + .m_axi_awready ( dm_axi_s_resp.aw_ready ), + //write data channel + .m_axi_wdata ( dm_axi_s_req.w.data ), + .m_axi_wstrb ( dm_axi_s_req.w.strb ), + .m_axi_wvalid ( dm_axi_s_req.w_valid ), + .m_axi_wready ( dm_axi_s_resp.w_ready ), + //read address channel + .m_axi_araddr ( dm_axi_s_req.ar.addr ), + .m_axi_arvalid ( dm_axi_s_req.ar_valid ), + .m_axi_arready ( dm_axi_s_resp.ar_ready ), + //read data channel + .m_axi_rdata ( dm_axi_s_resp.r.data ), + .m_axi_rresp ( dm_axi_s_resp.r.resp ), + .m_axi_rvalid ( dm_axi_s_resp.r_valid ), + .m_axi_rready ( dm_axi_s_req.r_ready ), + //write response channel + .m_axi_bresp ( dm_axi_s_resp.b.resp ), + .m_axi_bvalid ( dm_axi_s_resp.b_valid ), + .m_axi_bready ( dm_axi_s_req.b_ready ) + ); + + // tie off system bus accesses (not supported yet due to + // missing AXI-lite br_master <-> NOC converter) + assign dm_axi_m_resp = '0; + + // tie off signals not used by AXI-lite + assign dm_axi_s_req.aw.id = '0; + assign dm_axi_s_req.aw.len = '0; + assign dm_axi_s_req.aw.size = 2'b11;// 8byte + assign dm_axi_s_req.aw.burst = '0; + assign dm_axi_s_req.aw.lock = '0; + assign dm_axi_s_req.aw.cache = '0; + assign dm_axi_s_req.aw.prot = '0; + assign dm_axi_s_req.aw.qos = '0; + assign dm_axi_s_req.aw.region = '0; + assign dm_axi_s_req.aw.atop = '0; + assign dm_axi_s_req.w.last = 1'b1; + assign dm_axi_s_req.ar.id = '0; + assign dm_axi_s_req.ar.len = '0; + assign dm_axi_s_req.ar.size = 2'b11;// 8byte + assign dm_axi_s_req.ar.burst = '0; + assign dm_axi_s_req.ar.lock = '0; + assign dm_axi_s_req.ar.cache = '0; + assign dm_axi_s_req.ar.prot = '0; + assign dm_axi_s_req.ar.qos = '0; + assign dm_axi_s_req.ar.region = '0; + // assign dm_axi_s_resp.r.id = '0; + // assign dm_axi_s_resp.r.last = 1'b1; + // assign dm_axi_s_resp.b.id = '0; + + ///////////////////////////// + // Bootrom + ///////////////////////////// + + logic rom_req; + logic [AxiAddrWidth-1:0] rom_addr; + logic [AxiDataWidth-1:0] rom_rdata; + + AXI_BUS #( + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) br_master(); + + axi2mem #( + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) i_axi2rom ( + .clk_i , + .rst_ni , + .slave ( br_master ), + .req_o ( rom_req ), + .we_o ( ), + .addr_o ( rom_addr ), + .be_o ( ), + .data_o ( ), + .data_i ( rom_rdata ) + ); + + bootrom i_bootrom ( + .clk_i , + .req_i ( rom_req ), + .addr_i ( rom_addr ), + .rdata_o ( rom_rdata ) + ); + + noc_axilite_bridge #( + .SLAVE_RESP_BYTEWIDTH ( 8 ), + .SWAP_ENDIANESS ( SwapEndianess ) + ) i_bootrom_axilite_bridge ( + .clk ( clk_i ), + .rst ( ~rst_ni ), + // to/from NOC + .splitter_bridge_val ( buf_ariane_bootrom_noc2_valid_i ), + .splitter_bridge_data ( buf_ariane_bootrom_noc2_data_i ), + .bridge_splitter_rdy ( ariane_bootrom_buf_noc2_ready_o ), + .bridge_splitter_val ( ariane_bootrom_buf_noc3_valid_o ), + .bridge_splitter_data ( ariane_bootrom_buf_noc3_data_o ), + .splitter_bridge_rdy ( buf_ariane_bootrom_noc3_ready_i ), + //axi lite signals + //write address channel + .m_axi_awaddr ( br_master.aw_addr ), + .m_axi_awvalid ( br_master.aw_valid ), + .m_axi_awready ( br_master.aw_ready ), + //write data channel + .m_axi_wdata ( br_master.w_data ), + .m_axi_wstrb ( br_master.w_strb ), + .m_axi_wvalid ( br_master.w_valid ), + .m_axi_wready ( br_master.w_ready ), + //read address channel + .m_axi_araddr ( br_master.ar_addr ), + .m_axi_arvalid ( br_master.ar_valid ), + .m_axi_arready ( br_master.ar_ready ), + //read data channel + .m_axi_rdata ( br_master.r_data ), + .m_axi_rresp ( br_master.r_resp ), + .m_axi_rvalid ( br_master.r_valid ), + .m_axi_rready ( br_master.r_ready ), + //write response channel + .m_axi_bresp ( br_master.b_resp ), + .m_axi_bvalid ( br_master.b_valid ), + .m_axi_bready ( br_master.b_ready ) + ); + + // tie off signals not used by AXI-lite + assign br_master.aw_id = '0; + assign br_master.aw_len = '0; + assign br_master.aw_size = 2'b11;// 8byte + assign br_master.aw_burst = '0; + assign br_master.aw_lock = '0; + assign br_master.aw_cache = '0; + assign br_master.aw_prot = '0; + assign br_master.aw_qos = '0; + assign br_master.aw_region = '0; + assign br_master.w_last = 1'b1; + assign br_master.ar_id = '0; + assign br_master.ar_len = '0; + assign br_master.ar_size = 2'b11;// 8byte + assign br_master.ar_burst = '0; + assign br_master.ar_lock = '0; + assign br_master.ar_cache = '0; + assign br_master.ar_prot = '0; + assign br_master.ar_qos = '0; + assign br_master.ar_region = '0; + // assign br_master.r_id = '0; + // assign br_master.r_last = 1'b1; + // assign br_master.b_id = '0; + + ///////////////////////////// + // CLINT + ///////////////////////////// + + ariane_axi::req_t clint_axi_req; + ariane_axi::resp_t clint_axi_resp; + + clint #( + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_ID_WIDTH ( AxiIdWidth ), + .NR_CORES ( NumHarts ) + ) i_clint ( + .clk_i , + .rst_ni , + .testmode_i , + .axi_req_i ( clint_axi_req ), + .axi_resp_o ( clint_axi_resp ), + .rtc_i , + .timer_irq_o , + .ipi_o + ); + + noc_axilite_bridge #( + .SLAVE_RESP_BYTEWIDTH ( 8 ), + .SWAP_ENDIANESS ( SwapEndianess ) + ) i_clint_axilite_bridge ( + .clk ( clk_i ), + .rst ( ~rst_ni ), + // to/from NOC + .splitter_bridge_val ( buf_ariane_clint_noc2_valid_i ), + .splitter_bridge_data ( buf_ariane_clint_noc2_data_i ), + .bridge_splitter_rdy ( ariane_clint_buf_noc2_ready_o ), + .bridge_splitter_val ( ariane_clint_buf_noc3_valid_o ), + .bridge_splitter_data ( ariane_clint_buf_noc3_data_o ), + .splitter_bridge_rdy ( buf_ariane_clint_noc3_ready_i ), + //axi lite signals + //write address channel + .m_axi_awaddr ( clint_axi_req.aw.addr ), + .m_axi_awvalid ( clint_axi_req.aw_valid ), + .m_axi_awready ( clint_axi_resp.aw_ready ), + //write data channel + .m_axi_wdata ( clint_axi_req.w.data ), + .m_axi_wstrb ( clint_axi_req.w.strb ), + .m_axi_wvalid ( clint_axi_req.w_valid ), + .m_axi_wready ( clint_axi_resp.w_ready ), + //read address channel + .m_axi_araddr ( clint_axi_req.ar.addr ), + .m_axi_arvalid ( clint_axi_req.ar_valid ), + .m_axi_arready ( clint_axi_resp.ar_ready ), + //read data channel + .m_axi_rdata ( clint_axi_resp.r.data ), + .m_axi_rresp ( clint_axi_resp.r.resp ), + .m_axi_rvalid ( clint_axi_resp.r_valid ), + .m_axi_rready ( clint_axi_req.r_ready ), + //write response channel + .m_axi_bresp ( clint_axi_resp.b.resp ), + .m_axi_bvalid ( clint_axi_resp.b_valid ), + .m_axi_bready ( clint_axi_req.b_ready ) + ); + + // tie off signals not used by AXI-lite + assign clint_axi_req.aw.id = '0; + assign clint_axi_req.aw.len = '0; + assign clint_axi_req.aw.size = 2'b11;// 8byte + assign clint_axi_req.aw.burst = '0; + assign clint_axi_req.aw.lock = '0; + assign clint_axi_req.aw.cache = '0; + assign clint_axi_req.aw.prot = '0; + assign clint_axi_req.aw.qos = '0; + assign clint_axi_req.aw.region = '0; + assign clint_axi_req.aw.atop = '0; + assign clint_axi_req.w.last = 1'b1; + assign clint_axi_req.ar.id = '0; + assign clint_axi_req.ar.len = '0; + assign clint_axi_req.ar.size = 2'b11;// 8byte + assign clint_axi_req.ar.burst = '0; + assign clint_axi_req.ar.lock = '0; + assign clint_axi_req.ar.cache = '0; + assign clint_axi_req.ar.prot = '0; + assign clint_axi_req.ar.qos = '0; + assign clint_axi_req.ar.region = '0; + + + ///////////////////////////// + // PLIC + ///////////////////////////// + + AXI_BUS #( + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) plic_master(); + + noc_axilite_bridge #( + .SLAVE_RESP_BYTEWIDTH ( 8 ), + .SWAP_ENDIANESS ( SwapEndianess ) + ) i_plic_axilite_bridge ( + .clk ( clk_i ), + .rst ( ~rst_ni ), + // to/from NOC + .splitter_bridge_val ( buf_ariane_plic_noc2_valid_i ), + .splitter_bridge_data ( buf_ariane_plic_noc2_data_i ), + .bridge_splitter_rdy ( ariane_plic_buf_noc2_ready_o ), + .bridge_splitter_val ( ariane_plic_buf_noc3_valid_o ), + .bridge_splitter_data ( ariane_plic_buf_noc3_data_o ), + .splitter_bridge_rdy ( buf_ariane_plic_noc3_ready_i ), + //axi lite signals + //write address channel + //write address channel + .m_axi_awaddr ( plic_master.aw_addr ), + .m_axi_awvalid ( plic_master.aw_valid ), + .m_axi_awready ( plic_master.aw_ready ), + //write data channel + .m_axi_wdata ( plic_master.w_data ), + .m_axi_wstrb ( plic_master.w_strb ), + .m_axi_wvalid ( plic_master.w_valid ), + .m_axi_wready ( plic_master.w_ready ), + //read address channel + .m_axi_araddr ( plic_master.ar_addr ), + .m_axi_arvalid ( plic_master.ar_valid ), + .m_axi_arready ( plic_master.ar_ready ), + //read data channel + .m_axi_rdata ( plic_master.r_data ), + .m_axi_rresp ( plic_master.r_resp ), + .m_axi_rvalid ( plic_master.r_valid ), + .m_axi_rready ( plic_master.r_ready ), + //write response channel + .m_axi_bresp ( plic_master.b_resp ), + .m_axi_bvalid ( plic_master.b_valid ), + .m_axi_bready ( plic_master.b_ready ) + ); + + // tie off signals not used by AXI-lite + assign plic_master.aw_id = '0; + assign plic_master.aw_len = '0; + assign plic_master.aw_size = 2'b11;// 8byte + assign plic_master.aw_burst = '0; + assign plic_master.aw_lock = '0; + assign plic_master.aw_cache = '0; + assign plic_master.aw_prot = '0; + assign plic_master.aw_qos = '0; + assign plic_master.aw_region = '0; + assign plic_master.w_last = 1'b1; + assign plic_master.ar_id = '0; + assign plic_master.ar_len = '0; + assign plic_master.ar_size = 2'b11;// 8byte + assign plic_master.ar_burst = '0; + assign plic_master.ar_lock = '0; + assign plic_master.ar_cache = '0; + assign plic_master.ar_prot = '0; + assign plic_master.ar_qos = '0; + assign plic_master.ar_region = '0; + + REG_BUS #( + .ADDR_WIDTH ( 32 ), + .DATA_WIDTH ( 32 ) + ) reg_bus (clk_i); + + logic plic_penable; + logic plic_pwrite; + logic [31:0] plic_paddr; + logic plic_psel; + logic [31:0] plic_pwdata; + logic [31:0] plic_prdata; + logic plic_pready; + logic plic_pslverr; + + axi2apb_64_32 #( + .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ), + .AXI4_RDATA_WIDTH ( AxiDataWidth ), + .AXI4_WDATA_WIDTH ( AxiDataWidth ), + .AXI4_ID_WIDTH ( AxiIdWidth ), + .AXI4_USER_WIDTH ( AxiUserWidth ), + .BUFF_DEPTH_SLAVE ( 2 ), + .APB_ADDR_WIDTH ( 32 ) + ) i_axi2apb_64_32_plic ( + .ACLK ( clk_i ), + .ARESETn ( rst_ni ), + .test_en_i ( testmode_i ), + .AWID_i ( plic_master.aw_id ), + .AWADDR_i ( plic_master.aw_addr ), + .AWLEN_i ( plic_master.aw_len ), + .AWSIZE_i ( plic_master.aw_size ), + .AWBURST_i ( plic_master.aw_burst ), + .AWLOCK_i ( plic_master.aw_lock ), + .AWCACHE_i ( plic_master.aw_cache ), + .AWPROT_i ( plic_master.aw_prot ), + .AWREGION_i( plic_master.aw_region ), + .AWUSER_i ( plic_master.aw_user ), + .AWQOS_i ( plic_master.aw_qos ), + .AWVALID_i ( plic_master.aw_valid ), + .AWREADY_o ( plic_master.aw_ready ), + .WDATA_i ( plic_master.w_data ), + .WSTRB_i ( plic_master.w_strb ), + .WLAST_i ( plic_master.w_last ), + .WUSER_i ( plic_master.w_user ), + .WVALID_i ( plic_master.w_valid ), + .WREADY_o ( plic_master.w_ready ), + .BID_o ( plic_master.b_id ), + .BRESP_o ( plic_master.b_resp ), + .BVALID_o ( plic_master.b_valid ), + .BUSER_o ( plic_master.b_user ), + .BREADY_i ( plic_master.b_ready ), + .ARID_i ( plic_master.ar_id ), + .ARADDR_i ( plic_master.ar_addr ), + .ARLEN_i ( plic_master.ar_len ), + .ARSIZE_i ( plic_master.ar_size ), + .ARBURST_i ( plic_master.ar_burst ), + .ARLOCK_i ( plic_master.ar_lock ), + .ARCACHE_i ( plic_master.ar_cache ), + .ARPROT_i ( plic_master.ar_prot ), + .ARREGION_i( plic_master.ar_region ), + .ARUSER_i ( plic_master.ar_user ), + .ARQOS_i ( plic_master.ar_qos ), + .ARVALID_i ( plic_master.ar_valid ), + .ARREADY_o ( plic_master.ar_ready ), + .RID_o ( plic_master.r_id ), + .RDATA_o ( plic_master.r_data ), + .RRESP_o ( plic_master.r_resp ), + .RLAST_o ( plic_master.r_last ), + .RUSER_o ( plic_master.r_user ), + .RVALID_o ( plic_master.r_valid ), + .RREADY_i ( plic_master.r_ready ), + .PENABLE ( plic_penable ), + .PWRITE ( plic_pwrite ), + .PADDR ( plic_paddr ), + .PSEL ( plic_psel ), + .PWDATA ( plic_pwdata ), + .PRDATA ( plic_prdata ), + .PREADY ( plic_pready ), + .PSLVERR ( plic_pslverr ) + ); + + apb_to_reg i_apb_to_reg ( + .clk_i , + .rst_ni , + .penable_i ( plic_penable ), + .pwrite_i ( plic_pwrite ), + .paddr_i ( plic_paddr ), + .psel_i ( plic_psel ), + .pwdata_i ( plic_pwdata ), + .prdata_o ( plic_prdata ), + .pready_o ( plic_pready ), + .pslverr_o ( plic_pslverr ), + .reg_o ( reg_bus ) + ); + + plic #( + .ADDR_WIDTH ( 32 ), + .DATA_WIDTH ( 32 ), + .ID_BITWIDTH ( 3 ), // TODO (zarubaf): Find propper width + .PARAMETER_BITWIDTH ( 3 ), // TODO (zarubaf): Find propper width + .NUM_TARGETS ( 2*NumHarts ), + .NUM_SOURCES ( NumSources ) + ) i_plic ( + .clk_i , + .rst_ni , + .irq_sources_i , + .eip_targets_o ( irq_o ), + .external_bus_io ( reg_bus ) +); + + + +endmodule + diff --git a/scripts/parse_ila_trace.py b/scripts/parse_ila_trace.py new file mode 100755 index 0000000000..ee393934b1 --- /dev/null +++ b/scripts/parse_ila_trace.py @@ -0,0 +1,10 @@ +import csv + +with open('iladata.csv', 'r') as csvfile: + csvreader = csv.reader(csvfile, delimiter=',', quotechar='|') + for row in csvreader: + if (row[5] == '1'): + print(row[3]) + if (row[6] == '1'): + print(row[4]) + # print(', '.join(row[])); \ No newline at end of file diff --git a/src/alu.sv b/src/alu.sv index b9fe8d235a..23a76dbba5 100644 --- a/src/alu.sv +++ b/src/alu.sv @@ -12,65 +12,35 @@ // Author: Igor Loi // Author: Andreas Traber // Author: Lukas Mueller -// Author: Florian Zaruba +// Author: Florian Zaruba // // Date: 19.03.2017 -// Description: Ariane ALU +// Description: Ariane ALU based on RI5CY's ALU import ariane_pkg::*; module alu ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input logic flush_i, - input logic [63:0] pc_i, - input logic [TRANS_ID_BITS-1:0] trans_id_i, - input logic alu_valid_i, - input logic branch_valid_i, - input logic csr_valid_i, - input fu_op operator_i, - input logic [63:0] operand_a_i, - input logic [63:0] operand_b_i, - input logic [63:0] imm_i, + input fu_data_t fu_data_i, output logic [63:0] result_o, - output logic alu_valid_o, - output logic alu_ready_o, - output logic [TRANS_ID_BITS-1:0] alu_trans_id_o, - output exception_t alu_exception_o, - - input logic fu_valid_i, - input logic is_compressed_instr_i, - input branchpredict_sbe_t branch_predict_i, - output branchpredict_t resolved_branch_o, - output logic resolve_branch_o, - - input logic commit_i, - // to CSR file - output logic [11:0] csr_addr_o // CSR address to commit stage + output logic alu_branch_res_o ); - logic csr_ready; - - assign alu_ready_o = csr_ready; - assign alu_valid_o = alu_valid_i | branch_valid_i | csr_valid_i; - assign alu_trans_id_o = trans_id_i; - logic [63:0] operand_a_rev; logic [31:0] operand_a_rev32; logic [64:0] operand_b_neg; logic [65:0] adder_result_ext_o; logic less; // handles both signed and unsigned forms - logic alu_branch_res; - logic [63:0] branch_result, csr_result; // bit reverse operand_a for left shifts and bit counting generate genvar k; for(k = 0; k < 64; k++) - assign operand_a_rev[k] = operand_a_i[63-k]; + assign operand_a_rev[k] = fu_data_i.operand_a[63-k]; for (k = 0; k < 32; k++) - assign operand_a_rev32[k] = operand_a_i[31-k]; + assign operand_a_rev32[k] = fu_data_i.operand_a[31-k]; endgenerate // ------ @@ -84,7 +54,7 @@ module alu ( always_comb begin adder_op_b_negate = 1'b0; - unique case (operator_i) + unique case (fu_data_i.operator) // ADDER OPS EQ, NE, SUB, SUBW: adder_op_b_negate = 1'b1; @@ -94,10 +64,10 @@ module alu ( end // prepare operand a - assign adder_in_a = {operand_a_i, 1'b1}; + assign adder_in_a = {fu_data_i.operand_a, 1'b1}; // prepare operand b - assign operand_b_neg = {operand_b_i, 1'b0} ^ {65{adder_op_b_negate}}; + assign operand_b_neg = {fu_data_i.operand_b, 1'b0} ^ {65{adder_op_b_negate}}; assign adder_in_b = operand_b_neg ; // actual adder @@ -108,13 +78,13 @@ module alu ( // get the right branch comparison result always_comb begin : branch_resolve // set comparison by default - alu_branch_res = 1'b1; - case (operator_i) - EQ: alu_branch_res = adder_z_flag; - NE: alu_branch_res = ~adder_z_flag; - LTS, LTU: alu_branch_res = less; - GES, GEU: alu_branch_res = ~less; - default: alu_branch_res = 1'b1; + alu_branch_res_o = 1'b1; + case (fu_data_i.operator) + EQ: alu_branch_res_o = adder_z_flag; + NE: alu_branch_res_o = ~adder_z_flag; + LTS, LTU: alu_branch_res_o = less; + GES, GEU: alu_branch_res_o = ~less; + default: alu_branch_res_o = 1'b1; endcase end @@ -139,19 +109,19 @@ module alu ( logic [63:0] shift_left_result; logic [31:0] shift_left_result32; - assign shift_amt = operand_b_i; + assign shift_amt = fu_data_i.operand_b; - assign shift_left = (operator_i == SLL) | (operator_i == SLLW); + assign shift_left = (fu_data_i.operator == SLL) | (fu_data_i.operator == SLLW); - assign shift_arithmetic = (operator_i == SRA) | (operator_i == SRAW); + assign shift_arithmetic = (fu_data_i.operator == SRA) | (fu_data_i.operator == SRAW); // right shifts, we let the synthesizer optimize this logic [64:0] shift_op_a_64; logic [32:0] shift_op_a_32; // choose the bit reversed or the normal input for shift operand a - assign shift_op_a = shift_left ? operand_a_rev : operand_a_i; - assign shift_op_a32 = shift_left ? operand_a_rev32 : operand_a_i[31:0]; + assign shift_op_a = shift_left ? operand_a_rev : fu_data_i.operand_a; + assign shift_op_a32 = shift_left ? operand_a_rev32 : fu_data_i.operand_a[31:0]; assign shift_op_a_64 = { shift_arithmetic & shift_op_a[63], shift_op_a}; assign shift_op_a_32 = { shift_arithmetic & shift_op_a[31], shift_op_a32}; @@ -181,12 +151,12 @@ module alu ( logic sgn; sgn = 1'b0; - if ((operator_i == SLTS) || - (operator_i == LTS) || - (operator_i == GES)) + if ((fu_data_i.operator == SLTS) || + (fu_data_i.operator == LTS) || + (fu_data_i.operator == GES)) sgn = 1'b1; - less = ($signed({sgn & operand_a_i[63], operand_a_i}) < $signed({sgn & operand_b_i[63], operand_b_i})); + less = ($signed({sgn & fu_data_i.operand_a[63], fu_data_i.operand_a}) < $signed({sgn & fu_data_i.operand_b[63], fu_data_i.operand_b})); end // ----------- @@ -195,11 +165,11 @@ module alu ( always_comb begin result_o = '0; - unique case (operator_i) + unique case (fu_data_i.operator) // Standard Operations - ANDL: result_o = operand_a_i & operand_b_i; - ORL: result_o = operand_a_i | operand_b_i; - XORL: result_o = operand_a_i ^ operand_b_i; + ANDL: result_o = fu_data_i.operand_a & fu_data_i.operand_b; + ORL: result_o = fu_data_i.operand_a | fu_data_i.operand_b; + XORL: result_o = fu_data_i.operand_a ^ fu_data_i.operand_b; // Adder Operations ADD, SUB: result_o = adder_result; @@ -217,48 +187,5 @@ module alu ( default: ; // default case to suppress unique warning endcase - - if (branch_valid_i) begin - result_o = branch_result; - end else if (csr_valid_i) begin - result_o = csr_result; - end - end - - // ---------------------- - // Branch Unit - // ---------------------- - branch_unit branch_unit_i ( - .operator_i, - .operand_a_i, - .operand_b_i, - .imm_i, - .pc_i, - .is_compressed_instr_i, - // any functional unit is valid, check that there is no accidental mis-predict - .fu_valid_i, - .branch_valid_i, - .branch_comp_res_i ( alu_branch_res ), - .branch_result_o ( branch_result ), - .branch_predict_i, - .resolved_branch_o, - .resolve_branch_o, - .branch_exception_o ( alu_exception_o ) - ); - - csr_buffer csr_buffer_i ( - .clk_i, - .rst_ni, - .flush_i, - .csr_valid_i, - .operator_i, - .operand_a_i, - .operand_b_i, - .csr_ready_o ( csr_ready ), - .csr_result_o ( csr_result ), - .commit_i, - .csr_addr_o - ); - endmodule diff --git a/src/ariane.sv b/src/ariane.sv index bfdf5f4b58..4927f205be 100644 --- a/src/ariane.sv +++ b/src/ariane.sv @@ -13,694 +13,788 @@ // Description: Ariane Top-level module import ariane_pkg::*; -`ifndef verilator -`ifndef SYNTHESIS +//pragma translate_off +`ifndef VERILATOR import instruction_tracer_pkg::*; `endif +//pragma translate_on + +// default to AXI64 cache ports if not using the +// serpent PULP extension +`ifndef PITON_ARIANE +`ifndef AXI64_CACHE_PORTS + `define AXI64_CACHE_PORTS +`endif `endif module ariane #( - parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not - parameter int unsigned AXI_ID_WIDTH = 10, // minimum 1 - parameter int unsigned AXI_USER_WIDTH = 1 // minimum 1 - )( - input logic clk_i, - input logic rst_ni, - // Core ID, Cluster ID and boot address are considered more or less static - input logic [63:0] boot_addr_i, // reset boot address - input logic [ 3:0] core_id_i, // core id in a multicore environment (reflected in a CSR) - input logic [ 5:0] cluster_id_i, // PULP specific if core is used in a clustered environment - // Instruction memory interface - AXI_BUS.Master instr_if, - // Data memory interface - AXI_BUS.Master data_if, // data cache refill port - AXI_BUS.Master bypass_if, // bypass axi port (disabled cache or uncacheable access) - // Interrupt inputs - input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async) - input logic ipi_i, // inter-processor interrupts (async) - // Timer facilities - input logic time_irq_i, // timer interrupt in (async) - input logic debug_req_i // debug request (async) - ); +`ifdef PITON_ARIANE + parameter bit SwapEndianess = 0, // swap endianess in l15 adapter + parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region +`endif + parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000 // begin of cached region +) ( + input logic clk_i, + input logic rst_ni, + // Core ID, Cluster ID and boot address are considered more or less static + input logic [63:0] boot_addr_i, // reset boot address + input logic [63:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR) + + // Interrupt inputs + input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async) + input logic ipi_i, // inter-processor interrupts (async) + // Timer facilities + input logic time_irq_i, // timer interrupt in (async) + input logic debug_req_i, // debug request (async) + +`ifdef AXI64_CACHE_PORTS + // memory side, AXI Master + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i +`else + // L15 (memory side) + output serpent_cache_pkg::l15_req_t l15_req_o, + input serpent_cache_pkg::l15_rtrn_t l15_rtrn_i +`endif +); + + // ------------------------------------------ + // Global Signals + // Signals connecting more than one module + // ------------------------------------------ + riscv::priv_lvl_t priv_lvl; + exception_t ex_commit; // exception from commit stage + branchpredict_t resolved_branch; + logic [63:0] pc_commit; + logic eret; + logic [NR_COMMIT_PORTS-1:0] commit_ack; + + // -------------- + // PCGEN <-> CSR + // -------------- + logic [63:0] trap_vector_base_commit_pcgen; + logic [63:0] epc_commit_pcgen; + // -------------- + // IF <-> ID + // -------------- + frontend_fetch_t fetch_entry_if_id; + logic fetch_valid_if_id; + logic decode_ack_id_if; + + // -------------- + // ID <-> ISSUE + // -------------- + scoreboard_entry_t issue_entry_id_issue; + logic issue_entry_valid_id_issue; + logic is_ctrl_fow_id_issue; + logic issue_instr_issue_id; + + // -------------- + // ISSUE <-> EX + // -------------- + fu_data_t fu_data_id_ex; + logic [63:0] pc_id_ex; + logic is_compressed_instr_id_ex; + // fixed latency units + logic flu_ready_ex_id; + logic [TRANS_ID_BITS-1:0] flu_trans_id_ex_id; + logic flu_valid_ex_id; + logic [63:0] flu_result_ex_id; + exception_t flu_exception_ex_id; + // ALU + logic alu_valid_id_ex; + // Branches and Jumps + logic branch_valid_id_ex; + + branchpredict_sbe_t branch_predict_id_ex; + logic resolve_branch_ex_id; + // LSU + logic lsu_valid_id_ex; + logic lsu_ready_ex_id; + + logic [TRANS_ID_BITS-1:0] load_trans_id_ex_id; + logic [63:0] load_result_ex_id; + logic load_valid_ex_id; + exception_t load_exception_ex_id; + + logic [63:0] store_result_ex_id; + logic [TRANS_ID_BITS-1:0] store_trans_id_ex_id; + logic store_valid_ex_id; + exception_t store_exception_ex_id; + // MULT + logic mult_valid_id_ex; + // FPU + logic fpu_ready_ex_id; + logic fpu_valid_id_ex; + logic [1:0] fpu_fmt_id_ex; + logic [2:0] fpu_rm_id_ex; + logic [TRANS_ID_BITS-1:0] fpu_trans_id_ex_id; + logic [63:0] fpu_result_ex_id; + logic fpu_valid_ex_id; + exception_t fpu_exception_ex_id; + // CSR + logic csr_valid_id_ex; + // -------------- + // EX <-> COMMIT + // -------------- + // CSR Commit + logic csr_commit_commit_ex; + logic dirty_fp_state; + // LSU Commit + logic lsu_commit_commit_ex; + logic lsu_commit_ready_ex_commit; + logic no_st_pending_ex; + logic no_st_pending_commit; + logic amo_valid_commit; + // -------------- + // ID <-> COMMIT + // -------------- + scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_id_commit; + // -------------- + // COMMIT <-> ID + // -------------- + logic [NR_COMMIT_PORTS-1:0][4:0] waddr_commit_id; + logic [NR_COMMIT_PORTS-1:0][63:0] wdata_commit_id; + logic [NR_COMMIT_PORTS-1:0] we_gpr_commit_id; + logic [NR_COMMIT_PORTS-1:0] we_fpr_commit_id; + // -------------- + // CSR <-> * + // -------------- + logic [4:0] fflags_csr_commit; + riscv::xs_t fs; + logic [2:0] frm_csr_id_issue_ex; + logic [6:0] fprec_csr_ex; + logic enable_translation_csr_ex; + logic en_ld_st_translation_csr_ex; + riscv::priv_lvl_t ld_st_priv_lvl_csr_ex; + logic sum_csr_ex; + logic mxr_csr_ex; + logic [43:0] satp_ppn_csr_ex; + logic [0:0] asid_csr_ex; + logic [11:0] csr_addr_ex_csr; + fu_op csr_op_commit_csr; + logic [63:0] csr_wdata_commit_csr; + logic [63:0] csr_rdata_csr_commit; + exception_t csr_exception_csr_commit; + logic tvm_csr_id; + logic tw_csr_id; + logic tsr_csr_id; + logic dcache_en_csr_nbdcache; + logic csr_write_fflags_commit_cs; + logic icache_en_csr; + logic debug_mode; + logic single_step_csr_commit; + // ---------------------------- + // Performance Counters <-> * + // ---------------------------- + logic [11:0] addr_csr_perf; + logic [63:0] data_csr_perf, data_perf_csr; + logic we_csr_perf; + + logic icache_flush_ctrl_cache; + logic itlb_miss_ex_perf; + logic dtlb_miss_ex_perf; + logic dcache_miss_cache_perf; + logic icache_miss_cache_perf; + // -------------- + // CTRL <-> * + // -------------- + logic set_pc_ctrl_pcgen; + logic flush_csr_ctrl; + logic flush_unissued_instr_ctrl_id; + logic flush_ctrl_if; + logic flush_ctrl_id; + logic flush_ctrl_ex; + logic flush_tlb_ctrl_ex; + logic fence_i_commit_controller; + logic fence_commit_controller; + logic sfence_vma_commit_controller; + logic halt_ctrl; + logic halt_csr_ctrl; + logic dcache_flush_ctrl_cache; + logic dcache_flush_ack_cache_ctrl; + logic set_debug_pc; + logic flush_commit; + + icache_areq_i_t icache_areq_ex_cache; + icache_areq_o_t icache_areq_cache_ex; + icache_dreq_i_t icache_dreq_if_cache; + icache_dreq_o_t icache_dreq_cache_if; + + amo_req_t amo_req; + amo_resp_t amo_resp; + logic sb_full; + + logic debug_req; + // Disable debug during AMO commit + assign debug_req = debug_req_i & ~amo_valid_commit; + + // ---------------- + // DCache <-> * + // ---------------- + dcache_req_i_t [2:0] dcache_req_ports_ex_cache; + dcache_req_o_t [2:0] dcache_req_ports_cache_ex; + logic dcache_commit_wbuffer_empty; + + // -------------- + // Frontend + // -------------- + frontend i_frontend ( + .flush_i ( flush_ctrl_if ), // not entirely correct + .flush_bp_i ( 1'b0 ), + .debug_mode_i ( debug_mode ), + .boot_addr_i ( boot_addr_i ), + .icache_dreq_i ( icache_dreq_cache_if ), + .icache_dreq_o ( icache_dreq_if_cache ), + .resolved_branch_i ( resolved_branch ), + .pc_commit_i ( pc_commit ), + .set_pc_commit_i ( set_pc_ctrl_pcgen ), + .set_debug_pc_i ( set_debug_pc ), + .epc_i ( epc_commit_pcgen ), + .eret_i ( eret ), + .trap_vector_base_i ( trap_vector_base_commit_pcgen ), + .ex_valid_i ( ex_commit.valid ), + .fetch_entry_o ( fetch_entry_if_id ), + .fetch_entry_valid_o ( fetch_valid_if_id ), + .fetch_ack_i ( decode_ack_id_if ), + .* + ); - // ------------------------------------------ - // Global Signals - // Signals connecting more than one module - // ------------------------------------------ - riscv::priv_lvl_t priv_lvl; - exception_t ex_commit; // exception from commit stage - branchpredict_t resolved_branch; - logic [63:0] pc_commit; - logic eret; - logic [NR_COMMIT_PORTS-1:0] commit_ack; - - // -------------- - // PCGEN <-> CSR - // -------------- - logic [63:0] trap_vector_base_commit_pcgen; - logic [63:0] epc_commit_pcgen; - // -------------- - // IF <-> ID - // -------------- - fetch_entry_t fetch_entry_if_id; - logic fetch_valid_if_id; - logic decode_ack_id_if; - - // -------------- - // ID <-> ISSUE - // -------------- - scoreboard_entry_t issue_entry_id_issue; - logic issue_entry_valid_id_issue; - logic is_ctrl_fow_id_issue; - logic issue_instr_issue_id; - - // -------------- - // ISSUE <-> EX - // -------------- - logic [63:0] imm_id_ex; - logic [TRANS_ID_BITS-1:0] trans_id_id_ex; - fu_t fu_id_ex; - fu_op operator_id_ex; - logic [63:0] operand_a_id_ex; - logic [63:0] operand_b_id_ex; - logic [63:0] pc_id_ex; - logic is_compressed_instr_id_ex; + // --------- + // ID + // --------- + id_stage id_stage_i ( + .flush_i ( flush_ctrl_if ), + + .fetch_entry_i ( fetch_entry_if_id ), + .fetch_entry_valid_i ( fetch_valid_if_id ), + .decoded_instr_ack_o ( decode_ack_id_if ), + + .issue_entry_o ( issue_entry_id_issue ), + .issue_entry_valid_o ( issue_entry_valid_id_issue ), + .is_ctrl_flow_o ( is_ctrl_fow_id_issue ), + .issue_instr_ack_i ( issue_instr_issue_id ), + + .priv_lvl_i ( priv_lvl ), + .fs_i ( fs ), + .frm_i ( frm_csr_id_issue_ex ), + .debug_mode_i ( debug_mode ), + .tvm_i ( tvm_csr_id ), + .tw_i ( tw_csr_id ), + .tsr_i ( tsr_csr_id ), + .* + ); + + // --------- + // Issue + // --------- + issue_stage #( + .NR_ENTRIES ( NR_SB_ENTRIES ), + .NR_WB_PORTS ( NR_WB_PORTS ) + ) issue_stage_i ( + .clk_i, + .rst_ni, + .sb_full_o ( sb_full ), + .flush_unissued_instr_i ( flush_unissued_instr_ctrl_id ), + .flush_i ( flush_ctrl_id ), + // ID Stage + .decoded_instr_i ( issue_entry_id_issue ), + .decoded_instr_valid_i ( issue_entry_valid_id_issue ), + .is_ctrl_flow_i ( is_ctrl_fow_id_issue ), + .decoded_instr_ack_o ( issue_instr_issue_id ), + // Functional Units + .fu_data_o ( fu_data_id_ex ), + .pc_o ( pc_id_ex ), + .is_compressed_instr_o ( is_compressed_instr_id_ex ), + // fixed latency unit ready + .flu_ready_i ( flu_ready_ex_id ), // ALU - logic alu_ready_ex_id; - logic alu_valid_id_ex; - logic [TRANS_ID_BITS-1:0] alu_trans_id_ex_id; - logic alu_valid_ex_id; - logic [63:0] alu_result_ex_id; - exception_t alu_exception_ex_id; + .alu_valid_o ( alu_valid_id_ex ), // Branches and Jumps - logic branch_valid_id_ex; - - branchpredict_sbe_t branch_predict_id_ex; - logic resolve_branch_ex_id; + .branch_valid_o ( branch_valid_id_ex ), // branch is valid + .branch_predict_o ( branch_predict_id_ex ), // branch predict to ex + .resolve_branch_i ( resolve_branch_ex_id ), // in order to resolve the branch // LSU - logic [TRANS_ID_BITS-1:0] lsu_trans_id_ex_id; - logic lsu_valid_id_ex; - logic [63:0] lsu_result_ex_id; - logic lsu_ready_ex_id; - logic lsu_valid_ex_id; - exception_t lsu_exception_ex_id; - // MULT - logic mult_ready_ex_id; - logic mult_valid_id_ex; - logic [TRANS_ID_BITS-1:0] mult_trans_id_ex_id; - logic [63:0] mult_result_ex_id; - logic mult_valid_ex_id; + .lsu_ready_i ( lsu_ready_ex_id ), + .lsu_valid_o ( lsu_valid_id_ex ), + // Multiplier + .mult_valid_o ( mult_valid_id_ex ), // FPU - logic fpu_ready_ex_id; - logic fpu_valid_id_ex; - logic [1:0] fpu_fmt_id_ex; - logic [2:0] fpu_rm_id_ex; - logic [TRANS_ID_BITS-1:0] fpu_trans_id_ex_id; - logic [63:0] fpu_result_ex_id; - logic fpu_valid_ex_id; - exception_t fpu_exception_ex_id; + .fpu_ready_i ( fpu_ready_ex_id ), + .fpu_valid_o ( fpu_valid_id_ex ), + .fpu_fmt_o ( fpu_fmt_id_ex ), + .fpu_rm_o ( fpu_rm_id_ex ), // CSR - logic csr_valid_id_ex; - // -------------- - // EX <-> COMMIT - // -------------- - // CSR Commit - logic csr_commit_commit_ex; - logic dirty_fp_state; - // LSU Commit - logic lsu_commit_commit_ex; - logic lsu_commit_ready_ex_commit; - logic no_st_pending_ex_commit; - logic amo_valid_commit; - // -------------- - // ID <-> COMMIT - // -------------- - scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_id_commit; - // -------------- - // COMMIT <-> ID - // -------------- - logic [NR_COMMIT_PORTS-1:0][4:0] waddr_commit_id; - logic [NR_COMMIT_PORTS-1:0][63:0] wdata_commit_id; - logic [NR_COMMIT_PORTS-1:0] we_gpr_commit_id; - logic [NR_COMMIT_PORTS-1:0] we_fpr_commit_id; - // -------------- - // CSR <-> * - // -------------- - logic [4:0] fflags_csr_commit; - riscv::xs_t fs; - logic [2:0] frm_csr_id_issue_ex; - logic [6:0] fprec_csr_ex; - logic enable_translation_csr_ex; - logic en_ld_st_translation_csr_ex; - riscv::priv_lvl_t ld_st_priv_lvl_csr_ex; - logic sum_csr_ex; - logic mxr_csr_ex; - logic [43:0] satp_ppn_csr_ex; - logic [0:0] asid_csr_ex; - logic [11:0] csr_addr_ex_csr; - fu_op csr_op_commit_csr; - logic [63:0] csr_wdata_commit_csr; - logic [63:0] csr_rdata_csr_commit; - exception_t csr_exception_csr_commit; - logic tvm_csr_id; - logic tw_csr_id; - logic tsr_csr_id; - logic dcache_en_csr_nbdcache; - logic csr_write_fflags_commit_cs; - logic icache_en_csr; - logic debug_mode; - logic single_step_csr_commit; - // ---------------------------- - // Performance Counters <-> * - // ---------------------------- - logic [11:0] addr_csr_perf; - logic [63:0] data_csr_perf, data_perf_csr; - logic we_csr_perf; - - logic icache_flush_ctrl_cache; - logic itlb_miss_ex_perf; - logic dtlb_miss_ex_perf; - logic dcache_miss_cache_perf; - logic icache_miss_cache_perf; - // -------------- - // CTRL <-> * - // -------------- - logic set_pc_ctrl_pcgen; - logic flush_csr_ctrl; - logic flush_unissued_instr_ctrl_id; - logic flush_ctrl_if; - logic flush_ctrl_id; - logic flush_ctrl_ex; - logic flush_tlb_ctrl_ex; - logic fence_i_commit_controller; - logic fence_commit_controller; - logic sfence_vma_commit_controller; - logic halt_ctrl; - logic halt_csr_ctrl; - logic dcache_flush_ctrl_cache; - logic dcache_flush_ack_cache_ctrl; - logic set_debug_pc; - logic flush_commit; - - icache_areq_i_t icache_areq_ex_cache; - icache_areq_o_t icache_areq_cache_ex; - icache_dreq_i_t icache_dreq_if_cache; - icache_dreq_o_t icache_dreq_cache_if; - - amo_req_t amo_req; - amo_resp_t amo_resp; - - logic debug_req; - // Disable debug during AMO commit - assign debug_req = debug_req_i & ~amo_valid_commit; - - // ---------------- - // DCache <-> * - // ---------------- - dcache_req_i_t [2:0] dcache_req_ports_ex_cache; - dcache_req_o_t [2:0] dcache_req_ports_cache_ex; - - // -------------- - // Frontend - // -------------- - frontend i_frontend ( - .flush_i ( flush_ctrl_if ), // not entirely correct - .flush_bp_i ( 1'b0 ), - .debug_mode_i ( debug_mode ), - .boot_addr_i ( boot_addr_i ), - .icache_dreq_i ( icache_dreq_cache_if ), - .icache_dreq_o ( icache_dreq_if_cache ), - .resolved_branch_i ( resolved_branch ), - .pc_commit_i ( pc_commit ), - .set_pc_commit_i ( set_pc_ctrl_pcgen ), - .set_debug_pc_i ( set_debug_pc ), - .epc_i ( epc_commit_pcgen ), - .eret_i ( eret ), - .trap_vector_base_i ( trap_vector_base_commit_pcgen ), - .ex_valid_i ( ex_commit.valid ), - .fetch_entry_o ( fetch_entry_if_id ), - .fetch_entry_valid_o ( fetch_valid_if_id ), - .fetch_ack_i ( decode_ack_id_if ), - .* - ); - - // --------- - // ID - // --------- - id_stage id_stage_i ( - .flush_i ( flush_ctrl_if ), - - .fetch_entry_i ( fetch_entry_if_id ), - .fetch_entry_valid_i ( fetch_valid_if_id ), - .decoded_instr_ack_o ( decode_ack_id_if ), - - .issue_entry_o ( issue_entry_id_issue ), - .issue_entry_valid_o ( issue_entry_valid_id_issue ), - .is_ctrl_flow_o ( is_ctrl_fow_id_issue ), - .issue_instr_ack_i ( issue_instr_issue_id ), - - .priv_lvl_i ( priv_lvl ), - .fs_i ( fs ), - .frm_i ( frm_csr_id_issue_ex ), - .debug_mode_i ( debug_mode ), - .tvm_i ( tvm_csr_id ), - .tw_i ( tw_csr_id ), - .tsr_i ( tsr_csr_id ), - - .* - ); - - // --------- - // Issue - // --------- - issue_stage #( - .NR_ENTRIES ( NR_SB_ENTRIES ), - .NR_WB_PORTS ( NR_WB_PORTS ) - ) issue_stage_i ( - .flush_unissued_instr_i ( flush_unissued_instr_ctrl_id ), - .flush_i ( flush_ctrl_id ), - - .decoded_instr_i ( issue_entry_id_issue ), - .decoded_instr_valid_i ( issue_entry_valid_id_issue ), - .is_ctrl_flow_i ( is_ctrl_fow_id_issue ), - .decoded_instr_ack_o ( issue_instr_issue_id ), - - // Functional Units - .fu_o ( fu_id_ex ), - .operator_o ( operator_id_ex ), - .operand_a_o ( operand_a_id_ex ), - .operand_b_o ( operand_b_id_ex ), - .imm_o ( imm_id_ex ), - .trans_id_o ( trans_id_id_ex ), - .pc_o ( pc_id_ex ), - .is_compressed_instr_o ( is_compressed_instr_id_ex ), - // ALU - .alu_ready_i ( alu_ready_ex_id ), - .alu_valid_o ( alu_valid_id_ex ), - // Branches and Jumps - .branch_valid_o ( branch_valid_id_ex ), // branch is valid - .branch_predict_o ( branch_predict_id_ex ), // branch predict to ex - .resolve_branch_i ( resolve_branch_ex_id ), // in order to resolve the branch - // LSU - .lsu_ready_i ( lsu_ready_ex_id ), - .lsu_valid_o ( lsu_valid_id_ex ), - // Multiplier - .mult_ready_i ( mult_ready_ex_id ), - .mult_valid_o ( mult_valid_id_ex ), - // FPU - .fpu_ready_i ( fpu_ready_ex_id ), - .fpu_valid_o ( fpu_valid_id_ex ), - .fpu_fmt_o ( fpu_fmt_id_ex ), - .fpu_rm_o ( fpu_rm_id_ex ), - // CSR - .csr_valid_o ( csr_valid_id_ex ), - - // Commit - .resolved_branch_i ( resolved_branch ), - .trans_id_i ( {alu_trans_id_ex_id, lsu_trans_id_ex_id, mult_trans_id_ex_id, fpu_trans_id_ex_id }), - .wbdata_i ( {alu_result_ex_id, lsu_result_ex_id, mult_result_ex_id, fpu_result_ex_id }), - .ex_ex_i ( {alu_exception_ex_id, lsu_exception_ex_id, {$bits(exception_t){1'b0}}, fpu_exception_ex_id }), - .wb_valid_i ( {alu_valid_ex_id, lsu_valid_ex_id, mult_valid_ex_id, fpu_valid_ex_id }), - - .waddr_i ( waddr_commit_id ), - .wdata_i ( wdata_commit_id ), - .we_gpr_i ( we_gpr_commit_id ), - .we_fpr_i ( we_fpr_commit_id ), - .commit_instr_o ( commit_instr_id_commit ), - .commit_ack_i ( commit_ack ), - .* - ); - - // --------- - // EX - // --------- - ex_stage ex_stage_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( flush_ctrl_ex ), - .fu_i ( fu_id_ex ), - .operator_i ( operator_id_ex ), - .operand_a_i ( operand_a_id_ex ), - .operand_b_i ( operand_b_id_ex ), - .imm_i ( imm_id_ex ), - .trans_id_i ( trans_id_id_ex ), - .pc_i ( pc_id_ex ), - .is_compressed_instr_i ( is_compressed_instr_id_ex ), - // ALU - .alu_ready_o ( alu_ready_ex_id ), - .alu_valid_i ( alu_valid_id_ex ), - .alu_result_o ( alu_result_ex_id ), - .alu_trans_id_o ( alu_trans_id_ex_id ), - .alu_valid_o ( alu_valid_ex_id ), - .alu_exception_o ( alu_exception_ex_id ), - // Branches and Jumps - .branch_valid_i ( branch_valid_id_ex ), - .branch_predict_i ( branch_predict_id_ex ), // branch predict to ex - .resolved_branch_o ( resolved_branch ), - .resolve_branch_o ( resolve_branch_ex_id ), - // CSR - .csr_valid_i ( csr_valid_id_ex ), - .csr_addr_o ( csr_addr_ex_csr ), - .csr_commit_i ( csr_commit_commit_ex ), // from commit - // LSU - .lsu_ready_o ( lsu_ready_ex_id ), - .lsu_valid_i ( lsu_valid_id_ex ), - .lsu_result_o ( lsu_result_ex_id ), - .lsu_trans_id_o ( lsu_trans_id_ex_id ), - .lsu_valid_o ( lsu_valid_ex_id ), - .lsu_commit_i ( lsu_commit_commit_ex ), // from commit - .lsu_commit_ready_o ( lsu_commit_ready_ex_commit ), // to commit - .lsu_exception_o ( lsu_exception_ex_id ), - .no_st_pending_o ( no_st_pending_ex_commit ), - // MULT - .mult_ready_o ( mult_ready_ex_id ), - .mult_valid_i ( mult_valid_id_ex ), - .mult_trans_id_o ( mult_trans_id_ex_id ), - .mult_result_o ( mult_result_ex_id ), - .mult_valid_o ( mult_valid_ex_id ), - // FPU - .fpu_ready_o ( fpu_ready_ex_id ), - .fpu_valid_i ( fpu_valid_id_ex ), - .fpu_fmt_i ( fpu_fmt_id_ex ), - .fpu_rm_i ( fpu_rm_id_ex ), - .fpu_frm_i ( frm_csr_id_issue_ex ), - .fpu_prec_i ( fprec_csr_ex ), - .fpu_trans_id_o ( fpu_trans_id_ex_id ), - .fpu_result_o ( fpu_result_ex_id ), - .fpu_valid_o ( fpu_valid_ex_id ), - .fpu_exception_o ( fpu_exception_ex_id ), - .amo_valid_commit_i ( amo_valid_commit ), - .amo_req_o ( amo_req ), - .amo_resp_i ( amo_resp ), - // Performance counters - .itlb_miss_o ( itlb_miss_ex_perf ), - .dtlb_miss_o ( dtlb_miss_ex_perf ), - // Memory Management - .enable_translation_i ( enable_translation_csr_ex ), // from CSR - .en_ld_st_translation_i ( en_ld_st_translation_csr_ex ), - .flush_tlb_i ( flush_tlb_ctrl_ex ), - .priv_lvl_i ( priv_lvl ), // from CSR - .ld_st_priv_lvl_i ( ld_st_priv_lvl_csr_ex ), // from CSR - .sum_i ( sum_csr_ex ), // from CSR - .mxr_i ( mxr_csr_ex ), // from CSR - .satp_ppn_i ( satp_ppn_csr_ex ), // from CSR - .asid_i ( asid_csr_ex ), // from CSR - .icache_areq_i ( icache_areq_cache_ex ), - .icache_areq_o ( icache_areq_ex_cache ), - // DCACHE interfaces - .dcache_req_ports_i ( dcache_req_ports_cache_ex ), - .dcache_req_ports_o ( dcache_req_ports_ex_cache ) - ); - - // --------- + .csr_valid_o ( csr_valid_id_ex ), // Commit - // --------- - commit_stage commit_stage_i ( - .clk_i, - .rst_ni, - .halt_i ( halt_ctrl ), - .flush_dcache_i ( dcache_flush_ctrl_cache ), - .exception_o ( ex_commit ), - .dirty_fp_state_o ( dirty_fp_state ), - .debug_mode_i ( debug_mode ), - .debug_req_i ( debug_req ), - .single_step_i ( single_step_csr_commit ), - .commit_instr_i ( commit_instr_id_commit ), - .commit_ack_o ( commit_ack ), - .no_st_pending_i ( no_st_pending_ex_commit ), - .waddr_o ( waddr_commit_id ), - .wdata_o ( wdata_commit_id ), - .we_gpr_o ( we_gpr_commit_id ), - .we_fpr_o ( we_fpr_commit_id ), - .commit_lsu_o ( lsu_commit_commit_ex ), - .commit_lsu_ready_i ( lsu_commit_ready_ex_commit ), - .amo_valid_commit_o ( amo_valid_commit ), - .amo_resp_i ( amo_resp ), - .commit_csr_o ( csr_commit_commit_ex ), - .pc_o ( pc_commit ), - .csr_op_o ( csr_op_commit_csr ), - .csr_wdata_o ( csr_wdata_commit_csr ), - .csr_rdata_i ( csr_rdata_csr_commit ), - .csr_write_fflags_o ( csr_write_fflags_commit_cs ), - .csr_exception_i ( csr_exception_csr_commit ), - .fence_i_o ( fence_i_commit_controller ), - .fence_o ( fence_commit_controller ), - .sfence_vma_o ( sfence_vma_commit_controller ), - .flush_commit_o ( flush_commit ), - .* - ); + .resolved_branch_i ( resolved_branch ), + .trans_id_i ( {flu_trans_id_ex_id, load_trans_id_ex_id, store_trans_id_ex_id, fpu_trans_id_ex_id }), + .wbdata_i ( {flu_result_ex_id, load_result_ex_id, store_result_ex_id, fpu_result_ex_id }), + .ex_ex_i ( {flu_exception_ex_id, load_exception_ex_id, store_exception_ex_id, fpu_exception_ex_id }), + .wb_valid_i ( {flu_valid_ex_id, load_valid_ex_id, store_valid_ex_id, fpu_valid_ex_id }), + + .waddr_i ( waddr_commit_id ), + .wdata_i ( wdata_commit_id ), + .we_gpr_i ( we_gpr_commit_id ), + .we_fpr_i ( we_fpr_commit_id ), + .commit_instr_o ( commit_instr_id_commit ), + .commit_ack_i ( commit_ack ), + .* + ); - // --------- + // --------- + // EX + // --------- + ex_stage ex_stage_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( flush_ctrl_ex ), + .fu_data_i ( fu_data_id_ex ), + .pc_i ( pc_id_ex ), + .is_compressed_instr_i ( is_compressed_instr_id_ex ), + // fixed latency units + .flu_result_o ( flu_result_ex_id ), + .flu_trans_id_o ( flu_trans_id_ex_id ), + .flu_valid_o ( flu_valid_ex_id ), + .flu_exception_o ( flu_exception_ex_id ), + .flu_ready_o ( flu_ready_ex_id ), + // ALU + .alu_valid_i ( alu_valid_id_ex ), + // Branches and Jumps + .branch_valid_i ( branch_valid_id_ex ), + .branch_predict_i ( branch_predict_id_ex ), // branch predict to ex + .resolved_branch_o ( resolved_branch ), + .resolve_branch_o ( resolve_branch_ex_id ), // CSR - // --------- - csr_regfile #( - .ASID_WIDTH ( ASID_WIDTH ) - ) csr_regfile_i ( - .flush_o ( flush_csr_ctrl ), - .halt_csr_o ( halt_csr_ctrl ), - .commit_instr_i ( commit_instr_id_commit ), - .commit_ack_i ( commit_ack ), - .ex_i ( ex_commit ), - .csr_op_i ( csr_op_commit_csr ), - .csr_write_fflags_i ( csr_write_fflags_commit_cs ), - .dirty_fp_state_i ( dirty_fp_state ), - .csr_addr_i ( csr_addr_ex_csr ), - .csr_wdata_i ( csr_wdata_commit_csr ), - .csr_rdata_o ( csr_rdata_csr_commit ), - .pc_i ( pc_commit ), - .csr_exception_o ( csr_exception_csr_commit ), - .epc_o ( epc_commit_pcgen ), - .eret_o ( eret ), - .set_debug_pc_o ( set_debug_pc ), - .trap_vector_base_o ( trap_vector_base_commit_pcgen ), - .priv_lvl_o ( priv_lvl ), - .fs_o ( fs ), - .fflags_o ( fflags_csr_commit ), - .frm_o ( frm_csr_id_issue_ex ), - .fprec_o ( fprec_csr_ex ), - .ld_st_priv_lvl_o ( ld_st_priv_lvl_csr_ex ), - .en_translation_o ( enable_translation_csr_ex ), - .en_ld_st_translation_o ( en_ld_st_translation_csr_ex ), - .sum_o ( sum_csr_ex ), - .mxr_o ( mxr_csr_ex ), - .satp_ppn_o ( satp_ppn_csr_ex ), - .asid_o ( asid_csr_ex ), - .tvm_o ( tvm_csr_id ), - .tw_o ( tw_csr_id ), - .tsr_o ( tsr_csr_id ), - .debug_mode_o ( debug_mode ), - .single_step_o ( single_step_csr_commit ), - .dcache_en_o ( dcache_en_csr_nbdcache ), - .icache_en_o ( icache_en_csr ), - .perf_addr_o ( addr_csr_perf ), - .perf_data_o ( data_csr_perf ), - .perf_data_i ( data_perf_csr ), - .perf_we_o ( we_csr_perf ), - .debug_req_i ( debug_req ), - .ipi_i, - .irq_i, - .time_irq_i, - .* - ); + .csr_valid_i ( csr_valid_id_ex ), + .csr_addr_o ( csr_addr_ex_csr ), + .csr_commit_i ( csr_commit_commit_ex ), // from commit + // MULT + .mult_valid_i ( mult_valid_id_ex ), + // LSU + .lsu_ready_o ( lsu_ready_ex_id ), + .lsu_valid_i ( lsu_valid_id_ex ), + + .load_result_o ( load_result_ex_id ), + .load_trans_id_o ( load_trans_id_ex_id ), + .load_valid_o ( load_valid_ex_id ), + .load_exception_o ( load_exception_ex_id ), + + .store_result_o ( store_result_ex_id ), + .store_trans_id_o ( store_trans_id_ex_id ), + .store_valid_o ( store_valid_ex_id ), + .store_exception_o ( store_exception_ex_id ), + + .lsu_commit_i ( lsu_commit_commit_ex ), // from commit + .lsu_commit_ready_o ( lsu_commit_ready_ex_commit ), // to commit + .no_st_pending_o ( no_st_pending_ex ), + // FPU + .fpu_ready_o ( fpu_ready_ex_id ), + .fpu_valid_i ( fpu_valid_id_ex ), + .fpu_fmt_i ( fpu_fmt_id_ex ), + .fpu_rm_i ( fpu_rm_id_ex ), + .fpu_frm_i ( frm_csr_id_issue_ex ), + .fpu_prec_i ( fprec_csr_ex ), + .fpu_trans_id_o ( fpu_trans_id_ex_id ), + .fpu_result_o ( fpu_result_ex_id ), + .fpu_valid_o ( fpu_valid_ex_id ), + .fpu_exception_o ( fpu_exception_ex_id ), + .amo_valid_commit_i ( amo_valid_commit ), + .amo_req_o ( amo_req ), + .amo_resp_i ( amo_resp ), + // Performance counters + .itlb_miss_o ( itlb_miss_ex_perf ), + .dtlb_miss_o ( dtlb_miss_ex_perf ), + // Memory Management + .enable_translation_i ( enable_translation_csr_ex ), // from CSR + .en_ld_st_translation_i ( en_ld_st_translation_csr_ex ), + .flush_tlb_i ( flush_tlb_ctrl_ex ), + .priv_lvl_i ( priv_lvl ), // from CSR + .ld_st_priv_lvl_i ( ld_st_priv_lvl_csr_ex ), // from CSR + .sum_i ( sum_csr_ex ), // from CSR + .mxr_i ( mxr_csr_ex ), // from CSR + .satp_ppn_i ( satp_ppn_csr_ex ), // from CSR + .asid_i ( asid_csr_ex ), // from CSR + .icache_areq_i ( icache_areq_cache_ex ), + .icache_areq_o ( icache_areq_ex_cache ), + // DCACHE interfaces + .dcache_req_ports_i ( dcache_req_ports_cache_ex ), + .dcache_req_ports_o ( dcache_req_ports_ex_cache ) + ); - // ------------------------ - // Performance Counters - // ------------------------ - perf_counters i_perf_counters ( - .addr_i ( addr_csr_perf ), - .we_i ( we_csr_perf ), - .data_i ( data_csr_perf ), - .data_o ( data_perf_csr ), - .commit_instr_i ( commit_instr_id_commit ), - .commit_ack_i ( commit_ack ), - - .l1_icache_miss_i ( icache_miss_cache_perf ), - .l1_dcache_miss_i ( dcache_miss_cache_perf ), - .itlb_miss_i ( itlb_miss_ex_perf ), - .dtlb_miss_i ( dtlb_miss_ex_perf ), - - .ex_i ( ex_commit ), - .eret_i ( eret ), - .resolved_branch_i ( resolved_branch ), - .* - ); + // --------- + // Commit + // --------- + + // we have to make sure that the whole write buffer path is empty before + // used e.g. for fence instructions. + assign no_st_pending_commit = no_st_pending_ex & dcache_commit_wbuffer_empty; + + commit_stage commit_stage_i ( + .clk_i, + .rst_ni, + .halt_i ( halt_ctrl ), + .flush_dcache_i ( dcache_flush_ctrl_cache ), + .exception_o ( ex_commit ), + .dirty_fp_state_o ( dirty_fp_state ), + .debug_mode_i ( debug_mode ), + .debug_req_i ( debug_req ), + .single_step_i ( single_step_csr_commit ), + .commit_instr_i ( commit_instr_id_commit ), + .commit_ack_o ( commit_ack ), + .no_st_pending_i ( no_st_pending_commit ), + .waddr_o ( waddr_commit_id ), + .wdata_o ( wdata_commit_id ), + .we_gpr_o ( we_gpr_commit_id ), + .we_fpr_o ( we_fpr_commit_id ), + .commit_lsu_o ( lsu_commit_commit_ex ), + .commit_lsu_ready_i ( lsu_commit_ready_ex_commit ), + .amo_valid_commit_o ( amo_valid_commit ), + .amo_resp_i ( amo_resp ), + .commit_csr_o ( csr_commit_commit_ex ), + .pc_o ( pc_commit ), + .csr_op_o ( csr_op_commit_csr ), + .csr_wdata_o ( csr_wdata_commit_csr ), + .csr_rdata_i ( csr_rdata_csr_commit ), + .csr_write_fflags_o ( csr_write_fflags_commit_cs ), + .csr_exception_i ( csr_exception_csr_commit ), + .fence_i_o ( fence_i_commit_controller ), + .fence_o ( fence_commit_controller ), + .sfence_vma_o ( sfence_vma_commit_controller ), + .flush_commit_o ( flush_commit ), + .* + ); - // ------------ - // Controller - // ------------ - controller controller_i ( - // flush ports - .set_pc_commit_o ( set_pc_ctrl_pcgen ), - .flush_unissued_instr_o ( flush_unissued_instr_ctrl_id ), - .flush_if_o ( flush_ctrl_if ), - .flush_id_o ( flush_ctrl_id ), - .flush_ex_o ( flush_ctrl_ex ), - .flush_tlb_o ( flush_tlb_ctrl_ex ), - .flush_dcache_o ( dcache_flush_ctrl_cache ), - .flush_dcache_ack_i ( dcache_flush_ack_cache_ctrl ), - - .halt_csr_i ( halt_csr_ctrl ), - .halt_o ( halt_ctrl ), - // control ports - .eret_i ( eret ), - .ex_valid_i ( ex_commit.valid ), - .set_debug_pc_i ( set_debug_pc ), - .flush_csr_i ( flush_csr_ctrl ), - .resolved_branch_i ( resolved_branch ), - .fence_i_i ( fence_i_commit_controller ), - .fence_i ( fence_commit_controller ), - .sfence_vma_i ( sfence_vma_commit_controller ), - .flush_commit_i ( flush_commit ), - - .flush_icache_o ( icache_flush_ctrl_cache ), - .* - ); + // --------- + // CSR + // --------- + csr_regfile #( + .ASID_WIDTH ( ASID_WIDTH ) + ) csr_regfile_i ( + .flush_o ( flush_csr_ctrl ), + .halt_csr_o ( halt_csr_ctrl ), + .commit_instr_i ( commit_instr_id_commit ), + .commit_ack_i ( commit_ack ), + .ex_i ( ex_commit ), + .csr_op_i ( csr_op_commit_csr ), + .csr_write_fflags_i ( csr_write_fflags_commit_cs ), + .dirty_fp_state_i ( dirty_fp_state ), + .csr_addr_i ( csr_addr_ex_csr ), + .csr_wdata_i ( csr_wdata_commit_csr ), + .csr_rdata_o ( csr_rdata_csr_commit ), + .pc_i ( pc_commit ), + .csr_exception_o ( csr_exception_csr_commit ), + .epc_o ( epc_commit_pcgen ), + .eret_o ( eret ), + .set_debug_pc_o ( set_debug_pc ), + .trap_vector_base_o ( trap_vector_base_commit_pcgen ), + .priv_lvl_o ( priv_lvl ), + .fs_o ( fs ), + .fflags_o ( fflags_csr_commit ), + .frm_o ( frm_csr_id_issue_ex ), + .fprec_o ( fprec_csr_ex ), + .ld_st_priv_lvl_o ( ld_st_priv_lvl_csr_ex ), + .en_translation_o ( enable_translation_csr_ex ), + .en_ld_st_translation_o ( en_ld_st_translation_csr_ex ), + .sum_o ( sum_csr_ex ), + .mxr_o ( mxr_csr_ex ), + .satp_ppn_o ( satp_ppn_csr_ex ), + .asid_o ( asid_csr_ex ), + .tvm_o ( tvm_csr_id ), + .tw_o ( tw_csr_id ), + .tsr_o ( tsr_csr_id ), + .debug_mode_o ( debug_mode ), + .single_step_o ( single_step_csr_commit ), + .dcache_en_o ( dcache_en_csr_nbdcache ), + .icache_en_o ( icache_en_csr ), + .perf_addr_o ( addr_csr_perf ), + .perf_data_o ( data_csr_perf ), + .perf_data_i ( data_perf_csr ), + .perf_we_o ( we_csr_perf ), + .debug_req_i ( debug_req ), + .ipi_i, + .irq_i, + .time_irq_i, + .* + ); - // ------------------- - // Cache Subsystem - // ------------------- - std_cache_subsystem #( - .CACHE_START_ADDR ( CACHE_START_ADDR ) - ) i_std_cache_subsystem ( - // to D$ - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - // I$ - .icache_en_i ( icache_en_csr ), - .icache_flush_i ( icache_flush_ctrl_cache ), - .icache_miss_o ( icache_miss_cache_perf ), - .icache_areq_i ( icache_areq_ex_cache ), - .icache_areq_o ( icache_areq_cache_ex ), - .icache_dreq_i ( icache_dreq_if_cache ), - .icache_dreq_o ( icache_dreq_cache_if ), - // D$ - .dcache_enable_i ( dcache_en_csr_nbdcache ), - .dcache_flush_i ( dcache_flush_ctrl_cache ), - .dcache_flush_ack_o ( dcache_flush_ack_cache_ctrl ), - // to commit stage - .amo_req_i ( amo_req ), - .amo_resp_o ( amo_resp ), - .dcache_miss_o ( dcache_miss_cache_perf ), - // from PTW, Load Unit and Store Unit - .dcache_req_ports_i ( dcache_req_ports_ex_cache ), - .dcache_req_ports_o ( dcache_req_ports_cache_ex ), - // memory side - .icache_data_if ( instr_if ), - .dcache_data_if ( data_if ), - .dcache_bypass_if ( bypass_if ) + // ------------------------ + // Performance Counters + // ------------------------ + perf_counters i_perf_counters ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .debug_mode_i ( debug_mode ), + .addr_i ( addr_csr_perf ), + .we_i ( we_csr_perf ), + .data_i ( data_csr_perf ), + .data_o ( data_perf_csr ), + .commit_instr_i ( commit_instr_id_commit ), + .commit_ack_i ( commit_ack ), + + .l1_icache_miss_i ( icache_miss_cache_perf ), + .l1_dcache_miss_i ( dcache_miss_cache_perf ), + .itlb_miss_i ( itlb_miss_ex_perf ), + .dtlb_miss_i ( dtlb_miss_ex_perf ), + .sb_full_i ( sb_full ), + .if_empty_i ( ~fetch_valid_if_id ), + .ex_i ( ex_commit ), + .eret_i ( eret ), + .resolved_branch_i ( resolved_branch ) ); - // ------------------- - // Instruction Tracer - // ------------------- - `ifndef SYNTHESIS - `ifndef verilator - instruction_tracer_if tracer_if (clk_i); - // assign instruction tracer interface - // control signals - assign tracer_if.rstn = rst_ni; - assign tracer_if.flush_unissued = flush_unissued_instr_ctrl_id; - assign tracer_if.flush = flush_ctrl_ex; - // fetch - assign tracer_if.instruction = id_stage_i.compressed_decoder_i.instr_o; - assign tracer_if.fetch_valid = id_stage_i.instr_realigner_i.fetch_entry_valid_o; - assign tracer_if.fetch_ack = id_stage_i.instr_realigner_i.fetch_ack_i; - // Issue - assign tracer_if.issue_ack = issue_stage_i.i_scoreboard.issue_ack_i; - assign tracer_if.issue_sbe = issue_stage_i.i_scoreboard.issue_instr_o; - // write-back - assign tracer_if.waddr = waddr_commit_id; - assign tracer_if.wdata = wdata_commit_id; - assign tracer_if.we_gpr = we_gpr_commit_id; - assign tracer_if.we_fpr = we_fpr_commit_id; - // commit - assign tracer_if.commit_instr = commit_instr_id_commit; - assign tracer_if.commit_ack = commit_ack; - // branch predict - assign tracer_if.resolve_branch = resolved_branch; - // address translation - // stores - assign tracer_if.st_valid = ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i; - assign tracer_if.st_paddr = ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i; - // loads - assign tracer_if.ld_valid = ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid; - assign tracer_if.ld_kill = ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req; - assign tracer_if.ld_paddr = ex_stage_i.lsu_i.i_load_unit.paddr_i; - // exceptions - assign tracer_if.exception = commit_stage_i.exception_o; - // assign current privilege level - assign tracer_if.priv_lvl = priv_lvl; - assign tracer_if.debug_mode = debug_mode; - instr_tracer instr_tracer_i (tracer_if, cluster_id_i, core_id_i); - `endif - `endif - - `ifndef SYNTHESIS - `ifndef verilator - program instr_tracer ( - instruction_tracer_if tracer_if, - input logic [5:0] cluster_id_i, - input logic [3:0] core_id_i - ); - - instruction_tracer it = new (tracer_if, 1'b0); - - initial begin - #15ns; - it.create_file(cluster_id_i, core_id_i); - it.trace(); - end + // ------------ + // Controller + // ------------ + controller controller_i ( + // flush ports + .set_pc_commit_o ( set_pc_ctrl_pcgen ), + .flush_unissued_instr_o ( flush_unissued_instr_ctrl_id ), + .flush_if_o ( flush_ctrl_if ), + .flush_id_o ( flush_ctrl_id ), + .flush_ex_o ( flush_ctrl_ex ), + .flush_tlb_o ( flush_tlb_ctrl_ex ), + .flush_dcache_o ( dcache_flush_ctrl_cache ), + .flush_dcache_ack_i ( dcache_flush_ack_cache_ctrl ), + + .halt_csr_i ( halt_csr_ctrl ), + .halt_o ( halt_ctrl ), + // control ports + .eret_i ( eret ), + .ex_valid_i ( ex_commit.valid ), + .set_debug_pc_i ( set_debug_pc ), + .flush_csr_i ( flush_csr_ctrl ), + .resolved_branch_i ( resolved_branch ), + .fence_i_i ( fence_i_commit_controller ), + .fence_i ( fence_commit_controller ), + .sfence_vma_i ( sfence_vma_commit_controller ), + .flush_commit_i ( flush_commit ), + + .flush_icache_o ( icache_flush_ctrl_cache ), + .* + ); - final begin - it.close(); - end - endprogram - // mock tracer for Verilator, to be used with spike-dasm - `else + // ------------------- + // Cache Subsystem + // ------------------- + +`ifdef PITON_ARIANE + // this is a cache subsystem that is compatible with OpenPiton + serpent_cache_subsystem #( + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ), + .SwapEndianess ( SwapEndianess ) + ) i_cache_subsystem ( + // to D$ + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + // I$ + .icache_en_i ( icache_en_csr ), + .icache_flush_i ( icache_flush_ctrl_cache ), + .icache_miss_o ( icache_miss_cache_perf ), + .icache_areq_i ( icache_areq_ex_cache ), + .icache_areq_o ( icache_areq_cache_ex ), + .icache_dreq_i ( icache_dreq_if_cache ), + .icache_dreq_o ( icache_dreq_cache_if ), + // D$ + .dcache_enable_i ( dcache_en_csr_nbdcache ), + .dcache_flush_i ( dcache_flush_ctrl_cache ), + .dcache_flush_ack_o ( dcache_flush_ack_cache_ctrl ), + // to commit stage + .dcache_amo_req_i ( amo_req ), + .dcache_amo_resp_o ( amo_resp ), + // from PTW, Load Unit and Store Unit + .dcache_miss_o ( dcache_miss_cache_perf ), + .dcache_req_ports_i ( dcache_req_ports_ex_cache ), + .dcache_req_ports_o ( dcache_req_ports_cache_ex ), + // write buffer status + .wbuffer_empty_o ( dcache_commit_wbuffer_empty ), +`ifdef AXI64_CACHE_PORTS + // memory side + .axi_req_o ( axi_req_o ), + .axi_resp_i ( axi_resp_i ) +`else + .l15_req_o ( l15_req_o ), + .l15_rtrn_i ( l15_rtrn_i ) +`endif + ); +`else + + std_cache_subsystem #( + .CACHE_START_ADDR ( CachedAddrBeg ) + ) i_cache_subsystem ( + // to D$ + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .priv_lvl_i ( priv_lvl ), + // I$ + .icache_en_i ( icache_en_csr ), + .icache_flush_i ( icache_flush_ctrl_cache ), + .icache_miss_o ( icache_miss_cache_perf ), + .icache_areq_i ( icache_areq_ex_cache ), + .icache_areq_o ( icache_areq_cache_ex ), + .icache_dreq_i ( icache_dreq_if_cache ), + .icache_dreq_o ( icache_dreq_cache_if ), + // D$ + .dcache_enable_i ( dcache_en_csr_nbdcache ), + .dcache_flush_i ( dcache_flush_ctrl_cache ), + .dcache_flush_ack_o ( dcache_flush_ack_cache_ctrl ), + // to commit stage + .amo_req_i ( amo_req ), + .amo_resp_o ( amo_resp ), + .dcache_miss_o ( dcache_miss_cache_perf ), + // this is statically set to 1 as the std_cache does not have a wbuffer + .wbuffer_empty_o ( dcache_commit_wbuffer_empty ), + // from PTW, Load Unit and Store Unit + .dcache_req_ports_i ( dcache_req_ports_ex_cache ), + .dcache_req_ports_o ( dcache_req_ports_cache_ex ), + // memory side + .axi_req_o ( axi_req_o ), + .axi_resp_i ( axi_resp_i ) + ); +`endif + + // ------------------- + // Instruction Tracer + // ------------------- + //pragma translate_off +`ifndef VERILATOR + instruction_tracer_if tracer_if (clk_i); + // assign instruction tracer interface + // control signals + assign tracer_if.rstn = rst_ni; + assign tracer_if.flush_unissued = flush_unissued_instr_ctrl_id; + assign tracer_if.flush = flush_ctrl_ex; + // fetch + assign tracer_if.instruction = id_stage_i.compressed_decoder_i.instr_o; + assign tracer_if.fetch_valid = id_stage_i.instr_realigner_i.fetch_entry_valid_o; + assign tracer_if.fetch_ack = id_stage_i.instr_realigner_i.fetch_ack_i; + // Issue + assign tracer_if.issue_ack = issue_stage_i.i_scoreboard.issue_ack_i; + assign tracer_if.issue_sbe = issue_stage_i.i_scoreboard.issue_instr_o; + // write-back + assign tracer_if.waddr = waddr_commit_id; + assign tracer_if.wdata = wdata_commit_id; + assign tracer_if.we_gpr = we_gpr_commit_id; + assign tracer_if.we_fpr = we_fpr_commit_id; + // commit + assign tracer_if.commit_instr = commit_instr_id_commit; + assign tracer_if.commit_ack = commit_ack; + // branch predict + assign tracer_if.resolve_branch = resolved_branch; + // address translation + // stores + assign tracer_if.st_valid = ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i; + assign tracer_if.st_paddr = ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i; + // loads + assign tracer_if.ld_valid = ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid; + assign tracer_if.ld_kill = ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req; + assign tracer_if.ld_paddr = ex_stage_i.lsu_i.i_load_unit.paddr_i; + // exceptions + assign tracer_if.exception = commit_stage_i.exception_o; + // assign current privilege level + assign tracer_if.priv_lvl = priv_lvl; + assign tracer_if.debug_mode = debug_mode; + instr_tracer instr_tracer_i (tracer_if, hart_id_i); + + program instr_tracer ( + instruction_tracer_if tracer_if, + input logic [63:0] hart_id_i + ); - int f; - logic [63:0] cycles; + instruction_tracer it = new (tracer_if, 1'b0); initial begin - f = $fopen("trace_core_00_0.dasm", "w"); + #15ns; + it.create_file(hart_id_i); + it.trace(); end - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - cycles <= 0; - end else begin - string mode = ""; - if (debug_mode) mode = "D"; - else begin - case (priv_lvl) - riscv::PRIV_LVL_M: mode = "M"; - riscv::PRIV_LVL_S: mode = "S"; - riscv::PRIV_LVL_U: mode = "U"; - endcase - end - for (int i = 0; i < NR_COMMIT_PORTS; i++) begin - if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin - $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]); - end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin - if (commit_instr_id_commit[i].ex.cause == 2) begin - $fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc); - end else begin - if (debug_mode) begin - $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]); - end else begin - $fwrite(f, "Exception Cause: %5d, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.cause, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc); - end - end - end + final begin + it.close(); + end + endprogram + +`ifdef PITON_ARIANE + + logic piton_pc_vld; + logic [63:0] piton_pc; + + // expose retired PCs to OpenPiton verification environment + // note: this only works with single issue, need to adapt this in case of dual issue + always_ff @(posedge clk_i or negedge rst_ni) begin + logic [63:0] pc_queue [$]; + if (~rst_ni) begin + pc_queue.delete(); + piton_pc_vld <= 1'b0; + piton_pc <= '0; + end else begin + // serialize retired PCs via queue construct + for (int i = 0; i < NR_COMMIT_PORTS; i++) begin + if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin + pc_queue.push_back(commit_instr_id_commit[i].pc); + end + end + + if (pc_queue.size()>0) begin + piton_pc_vld <= 1'b1; + piton_pc <= pc_queue.pop_front(); + end else begin + piton_pc_vld <= 1'b0; + piton_pc <= '0; + end + end + end + +`endif // PITON_ARIANE + +// mock tracer for Verilator, to be used with spike-dasm +`else + + int f; + logic [63:0] cycles; + + initial begin + f = $fopen("trace_hart_00.dasm", "w"); + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + cycles <= 0; + end else begin + string mode = ""; + if (debug_mode) mode = "D"; + else begin + case (priv_lvl) + riscv::PRIV_LVL_M: mode = "M"; + riscv::PRIV_LVL_S: mode = "S"; + riscv::PRIV_LVL_U: mode = "U"; + endcase + end + for (int i = 0; i < NR_COMMIT_PORTS; i++) begin + if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin + $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]); + end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin + if (commit_instr_id_commit[i].ex.cause == 2) begin + $fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc); + end else begin + if (debug_mode) begin + $fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]); + end else begin + $fwrite(f, "Exception Cause: %5d, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.cause, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc); end - cycles <= cycles + 1; + end end + end + cycles <= cycles + 1; end + end + + final begin + $fclose(f); + end +`endif // VERILATOR + //pragma translate_on - final begin - $fclose(f); - end - `endif - `endif endmodule // ariane diff --git a/src/axi b/src/axi index 328cbe05a4..de1af46722 160000 --- a/src/axi +++ b/src/axi @@ -1 +1 @@ -Subproject commit 328cbe05a42a31aae6f57f780351a2ba22954fef +Subproject commit de1af467229315ee6af31fea96664c7aae5638a9 diff --git a/src/axi_adapter.sv b/src/axi_adapter.sv index d253e42db9..8d55733553 100644 --- a/src/axi_adapter.sv +++ b/src/axi_adapter.sv @@ -14,18 +14,19 @@ * * Description: Manages communication with the AXI Bus */ -import std_cache_pkg::*; +//import std_cache_pkg::*; module axi_adapter #( - parameter int unsigned DATA_WIDTH = 256, - parameter logic CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature - parameter int unsigned AXI_ID_WIDTH = 10 + parameter int unsigned DATA_WIDTH = 256, + parameter logic CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature + parameter int unsigned AXI_ID_WIDTH = 10, + parameter int unsigned CACHELINE_BYTE_OFFSET = 8 )( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic req_i, - input req_t type_i, + input ariane_axi::ad_req_t type_i, output logic gnt_o, output logic [AXI_ID_WIDTH-1:0] gnt_id_o, input logic [63:0] addr_i, @@ -42,7 +43,8 @@ module axi_adapter #( output logic [63:0] critical_word_o, output logic critical_word_valid_o, // AXI port - AXI_BUS.Master axi + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i ); localparam BURST_SIZE = DATA_WIDTH/64-1; localparam ADDR_INDEX = ($clog2(DATA_WIDTH/64) > 0) ? $clog2(DATA_WIDTH/64) : 1; @@ -62,50 +64,47 @@ module axi_adapter #( always_comb begin : axi_fsm // Default assignments - axi.aw_valid = 1'b0; - axi.aw_addr = addr_i; - axi.aw_prot = 3'b0; - axi.aw_region = 4'b0; - axi.aw_len = 8'b0; - axi.aw_size = {1'b0, size_i}; - axi.aw_burst = (type_i == SINGLE_REQ) ? 2'b00 : 2'b01; // fixed size for single request and incremental transfer for everything else - axi.aw_lock = 1'b0; - axi.aw_cache = 4'b0; - axi.aw_qos = 4'b0; - axi.aw_id = id_i; - axi.aw_user = '0; - - axi.ar_valid = 1'b0; + axi_req_o.aw_valid = 1'b0; + axi_req_o.aw.addr = addr_i; + axi_req_o.aw.prot = 3'b0; + axi_req_o.aw.region = 4'b0; + axi_req_o.aw.len = 8'b0; + axi_req_o.aw.size = {1'b0, size_i}; + axi_req_o.aw.burst = (type_i == ariane_axi::SINGLE_REQ) ? 2'b00 : 2'b01; // fixed size for single request and incremental transfer for everything else + axi_req_o.aw.lock = 1'b0; + axi_req_o.aw.cache = 4'b0; + axi_req_o.aw.qos = 4'b0; + axi_req_o.aw.id = id_i; + axi_req_o.aw.atop = '0; // currently not used + + axi_req_o.ar_valid = 1'b0; // in case of a single request or wrapping transfer we can simply begin at the address, if we want to request a cache-line // with an incremental transfer we need to output the corresponding base address of the cache line - axi.ar_addr = (CRITICAL_WORD_FIRST || type_i == SINGLE_REQ) ? addr_i : { addr_i[63:DCACHE_BYTE_OFFSET], {{DCACHE_BYTE_OFFSET}{1'b0}}}; - axi.ar_prot = 3'b0; - axi.ar_region = 4'b0; - axi.ar_len = 8'b0; - axi.ar_size = {1'b0, size_i}; // 8 bytes - axi.ar_burst = (type_i == SINGLE_REQ) ? 2'b00 : (CRITICAL_WORD_FIRST ? 2'b10 : 2'b01); // wrapping transfer in case of a critical word first strategy - axi.ar_lock = 1'b0; - axi.ar_cache = 4'b0; - axi.ar_qos = 4'b0; - axi.ar_id = id_i; - axi.ar_user = '0; - - axi.w_valid = 1'b0; - axi.w_data = wdata_i[0]; - axi.w_strb = be_i[0]; - axi.w_user = '0; - axi.w_last = 1'b0; - - axi.b_ready = 1'b0; - axi.r_ready = 1'b0; + axi_req_o.ar.addr = (CRITICAL_WORD_FIRST || type_i == ariane_axi::SINGLE_REQ) ? addr_i : { addr_i[63:CACHELINE_BYTE_OFFSET], {{CACHELINE_BYTE_OFFSET}{1'b0}}}; + axi_req_o.ar.prot = 3'b0; + axi_req_o.ar.region = 4'b0; + axi_req_o.ar.len = 8'b0; + axi_req_o.ar.size = {1'b0, size_i}; // 8 bytes + axi_req_o.ar.burst = (type_i == ariane_axi::SINGLE_REQ) ? 2'b00 : (CRITICAL_WORD_FIRST ? 2'b10 : 2'b01); // wrapping transfer in case of a critical word first strategy + axi_req_o.ar.lock = 1'b0; + axi_req_o.ar.cache = 4'b0; + axi_req_o.ar.qos = 4'b0; + axi_req_o.ar.id = id_i; + + axi_req_o.w_valid = 1'b0; + axi_req_o.w.data = wdata_i[0]; + axi_req_o.w.strb = be_i[0]; + axi_req_o.w.last = 1'b0; + + axi_req_o.b_ready = 1'b0; + axi_req_o.r_ready = 1'b0; gnt_o = 1'b0; - gnt_id_o = '0; + gnt_id_o = id_i; valid_o = 1'b0; - id_o = axi.r_id; + id_o = axi_resp_i.r.id; - // rdata_o = axi.r_data; - critical_word_o = axi.r_data; + critical_word_o = axi_resp_i.r.data; critical_word_valid_o = 1'b0; rdata_o = cache_line_q; @@ -126,93 +125,83 @@ module axi_adapter #( // write if (we_i) begin // the data is valid - axi.aw_valid = 1'b1; - axi.w_valid = 1'b1; + axi_req_o.aw_valid = 1'b1; + axi_req_o.w_valid = 1'b1; // its a single write - if (type_i == SINGLE_REQ) begin + if (type_i == ariane_axi::SINGLE_REQ) begin // only a single write so the data is already the last one - axi.w_last = 1'b1; + axi_req_o.w.last = 1'b1; // single req can be granted here - gnt_o = axi.aw_ready & axi.w_ready; - gnt_id_o = id_i; - case ({axi.aw_ready, axi.w_ready}) + gnt_o = axi_resp_i.aw_ready & axi_resp_i.w_ready; + case ({axi_resp_i.aw_ready, axi_resp_i.w_ready}) 2'b11: state_d = WAIT_B_VALID; 2'b01: state_d = WAIT_AW_READY; 2'b10: state_d = WAIT_LAST_W_READY; default: state_d = IDLE; endcase - id_d = axi.aw_id; + // its a request for the whole cache line end else begin - axi.aw_len = BURST_SIZE; // number of bursts to do - axi.w_last = 1'b0; - axi.w_data = wdata_i[0]; - axi.w_strb = be_i[0]; + axi_req_o.aw.len = BURST_SIZE; // number of bursts to do + axi_req_o.w.data = wdata_i[0]; + axi_req_o.w.strb = be_i[0]; - if (axi.w_ready) + if (axi_resp_i.w_ready) cnt_d = BURST_SIZE - 1; else cnt_d = BURST_SIZE; - case ({axi.aw_ready, axi.w_ready}) + case ({axi_resp_i.aw_ready, axi_resp_i.w_ready}) 2'b11: state_d = WAIT_LAST_W_READY; 2'b01: state_d = WAIT_LAST_W_READY_AW_READY; 2'b10: state_d = WAIT_LAST_W_READY; default:; endcase - // save id - id_d = axi.aw_id; - end // read end else begin - axi.ar_valid = 1'b1; - gnt_o = axi.ar_ready; - gnt_id_o = id_i; - - if (type_i != SINGLE_REQ) begin - axi.ar_len = BURST_SIZE; + axi_req_o.ar_valid = 1'b1; + gnt_o = axi_resp_i.ar_ready; + if (type_i != ariane_axi::SINGLE_REQ) begin + axi_req_o.ar.len = BURST_SIZE; cnt_d = BURST_SIZE; end - if (axi.ar_ready) begin - state_d = (type_i == SINGLE_REQ) ? WAIT_R_VALID : WAIT_R_VALID_MULTIPLE; + if (axi_resp_i.ar_ready) begin + state_d = (type_i == ariane_axi::SINGLE_REQ) ? WAIT_R_VALID : WAIT_R_VALID_MULTIPLE; addr_offset_d = addr_i[ADDR_INDEX-1+3:3]; - // save id - id_d = axi.ar_id; end end end end - // ~> from single write, write request has already been granted + // ~> from single write WAIT_AW_READY: begin - axi.aw_valid = 1'b1; - axi.aw_len = 8'b0; + axi_req_o.aw_valid = 1'b1; - if (axi.aw_ready) + if (axi_resp_i.aw_ready) begin + gnt_o = 1'b1; state_d = WAIT_B_VALID; - + end end // ~> we need to wait for an aw_ready and there is at least one outstanding write WAIT_LAST_W_READY_AW_READY: begin - - axi.w_valid = 1'b1; - axi.w_last = (cnt_q == '0) ? 1'b1 : 1'b0; - if (type_i == SINGLE_REQ) begin - axi.w_data = wdata_i[0]; - axi.w_strb = be_i[0]; + axi_req_o.w_valid = 1'b1; + axi_req_o.w.last = (cnt_q == '0); + if (type_i == ariane_axi::SINGLE_REQ) begin + axi_req_o.w.data = wdata_i[0]; + axi_req_o.w.strb = be_i[0]; end else begin - axi.w_data = wdata_i[BURST_SIZE-cnt_q]; - axi.w_strb = be_i[BURST_SIZE-cnt_q]; + axi_req_o.w.data = wdata_i[BURST_SIZE-cnt_q]; + axi_req_o.w.strb = be_i[BURST_SIZE-cnt_q]; end - axi.aw_valid = 1'b1; + axi_req_o.aw_valid = 1'b1; // we are here because we want to write a cache line - axi.aw_len = BURST_SIZE; + axi_req_o.aw.len = BURST_SIZE; // we got an aw_ready - case ({axi.aw_ready, axi.w_ready}) + case ({axi_resp_i.aw_ready, axi_resp_i.w_ready}) // we got an aw ready 2'b01: begin // are there any outstanding transactions? @@ -225,9 +214,8 @@ module axi_adapter #( 2'b11: begin // we are finished if (cnt_q == 0) begin - state_d = WAIT_B_VALID; - gnt_o = 1'b1; - gnt_id_o = id_q; + state_d = WAIT_B_VALID; + gnt_o = 1'b1; // there are outstanding transactions end else begin state_d = WAIT_LAST_W_READY; @@ -241,49 +229,43 @@ module axi_adapter #( // ~> all data has already been sent, we are only waiting for the aw_ready WAIT_AW_READY_BURST: begin - axi.aw_valid = 1'b1; - axi.aw_len = BURST_SIZE; + axi_req_o.aw_valid = 1'b1; + axi_req_o.aw.len = BURST_SIZE; - if (axi.aw_ready) begin - state_d = WAIT_B_VALID; - gnt_o = 1'b1; - gnt_id_o = id_q; + if (axi_resp_i.aw_ready) begin + state_d = WAIT_B_VALID; + gnt_o = 1'b1; end end // ~> from write, there is an outstanding write WAIT_LAST_W_READY: begin - axi.w_valid = 1'b1; - if (type_i == SINGLE_REQ) begin - axi.w_data = wdata_i[0]; - axi.w_strb = be_i[0]; - end else begin - axi.w_data = wdata_i[BURST_SIZE-cnt_q]; - axi.w_strb = be_i[BURST_SIZE-cnt_q]; + axi_req_o.w_valid = 1'b1; + + if (type_i != ariane_axi::SINGLE_REQ) begin + axi_req_o.w.data = wdata_i[BURST_SIZE-cnt_q]; + axi_req_o.w.strb = be_i[BURST_SIZE-cnt_q]; end // this is the last write - axi.w_last = (cnt_q == '0) ? 1'b1 : 1'b0; - - if (axi.w_ready) begin - // last write -> go to WAIT_B_VALID - if (cnt_q == '0) begin - state_d = WAIT_B_VALID; - gnt_o = (cnt_q == '0); - gnt_id_o = id_q; - end else begin - cnt_d = cnt_q - 1; + if (cnt_q == '0) begin + axi_req_o.w.last = 1'b1; + if (axi_resp_i.w_ready) begin + state_d = WAIT_B_VALID; + gnt_o = 1'b1; end + end else if (axi_resp_i.w_ready) begin + cnt_d = cnt_q - 1; end end // ~> finish write transaction WAIT_B_VALID: begin - axi.b_ready = 1'b1; - id_o = axi.b_id; + axi_req_o.b_ready = 1'b1; + id_o = axi_resp_i.b.id; // Write is valid - if (axi.b_valid) begin + if (axi_resp_i.b_valid) begin state_d = IDLE; valid_o = 1'b1; end @@ -297,34 +279,35 @@ module axi_adapter #( index = BURST_SIZE-cnt_q; // reads are always wrapping here - axi.r_ready = 1'b1; + axi_req_o.r_ready = 1'b1; // this is the first read a.k.a the critical word - if (axi.r_valid) begin + if (axi_resp_i.r_valid) begin if (CRITICAL_WORD_FIRST) begin // this is the first word of a cacheline read, e.g.: the word which was causing the miss if (state_q == WAIT_R_VALID_MULTIPLE && cnt_q == BURST_SIZE) begin critical_word_valid_o = 1'b1; - critical_word_o = axi.r_data; + critical_word_o = axi_resp_i.r.data; end end else begin // check if the address offset matches - then we are getting the critical word if (index == addr_offset_q) begin critical_word_valid_o = 1'b1; - critical_word_o = axi.r_data; + critical_word_o = axi_resp_i.r.data; end end // this is the last read - if (axi.r_last) begin + if (axi_resp_i.r.last) begin + id_d = axi_resp_i.r.id; state_d = COMPLETE_READ; end // save the word if (state_q == WAIT_R_VALID_MULTIPLE) begin - cache_line_d[index] = axi.r_data; + cache_line_d[index] = axi_resp_i.r.data; end else - cache_line_d[0] = axi.r_data; + cache_line_d[0] = axi_resp_i.r.data; // Decrease the counter cnt_d = cnt_q - 1; diff --git a/src/axi_adapter2.sv b/src/axi_adapter2.sv new file mode 100644 index 0000000000..0441c37518 --- /dev/null +++ b/src/axi_adapter2.sv @@ -0,0 +1,327 @@ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the “License”); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: axi_adapter.sv + * Author: Florian Zaruba + * Date: 1.8.2018 + * + * Description: Manages communication with the AXI Bus. Note that if you intend + * to use read bursts with BLEN>0, you have to either use the same ID for all reads + * to ensure ordering of the transactions, or you have to make sure that only one read + * is in flight. otherwise, the read response deserialization mechanism may not work + * correctly due to axi beat interleaving. + */ + +import std_cache_pkg::*; + +module axi_adapter2 #( + parameter int unsigned DATA_WORDS = 4, // data width in dwords, this is also the maximum burst length, must be >=2 + parameter int unsigned AXI_ID_WIDTH = 10, + parameter int unsigned CRITICAL_WORD_FIRST = 0 // this must be supported by the AXI subsystem, note that the data will be shifted by the word offset when this is enabled +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // read channel + // request + input logic rd_req_i, + output logic rd_gnt_o, + input logic [63:0] rd_addr_i, + input logic [$clog2(DATA_WORDS)-1:0] rd_blen_i, // axi convention: LEN-1 + input logic [1:0] rd_size_i, + input logic [AXI_ID_WIDTH-1:0] rd_id_i, // use same ID for reads, or make sure you only have one outstanding read tx + // read response + input logic rd_rdy_i, + output logic rd_valid_o, + output logic [DATA_WORDS-1:0][63:0] rd_data_o, + output logic [AXI_ID_WIDTH-1:0] rd_id_o, + // can be used to determine critical word + output logic [63:0] rd_word_o, + output logic rd_word_valid_o, + output logic rd_word_cnt_o, + // write channel + input logic wr_req_i, + output logic wr_gnt_o, + input logic [63:0] wr_addr_i, + input logic [DATA_WORDS-1:0][63:0] wr_data_i, + input logic [DATA_WORDS-1:0][7:0] wr_be_i, + input logic [$clog2(DATA_WORDS)-1:0] wr_blen_i, // axi convention: LEN-1 + input logic [1:0] wr_size_i, + input logic [AXI_ID_WIDTH-1:0] wr_id_i, + // write response + input logic wr_rdy_i, + output logic wr_valid_o, + output logic [AXI_ID_WIDTH-1:0] wr_id_o, + + // AXI port + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i +); + localparam ADDR_INDEX = ($clog2(DATA_WORDS) > 0) ? $clog2(DATA_WORDS) : 1; + +/////////////////////////////////////////////////////// +// write channel +/////////////////////////////////////////////////////// + + enum logic [3:0] { + IDLE, WAIT_AW_READY, WAIT_LAST_W_READY, WAIT_LAST_W_READY_AW_READY, WAIT_AW_READY_BURST + } wr_state_q, wr_state_d; + + // AXI tx counter + logic [ADDR_INDEX-1:0] wr_cnt_d, wr_cnt_q; + logic wr_single_req, wr_cnt_done, wr_cnt_clr, wr_cnt_en; + + assign wr_single_req = (wr_blen_i == 0); + + // address + assign axi_req_o.aw.burst = (wr_single_req) ? 2'b00 : 2'b01; // fixed size for single request and incremental transfer for everything else + assign axi_req_o.aw.addr = wr_addr_i; + assign axi_req_o.aw.size = wr_size_i; + assign axi_req_o.aw.len = wr_blen_i; + assign axi_req_o.aw.id = wr_id_i; + assign axi_req_o.aw.prot = 3'b0; + assign axi_req_o.aw.region = 4'b0; + assign axi_req_o.aw.lock = 1'b0; + assign axi_req_o.aw.cache = 4'b0; + assign axi_req_o.aw.qos = 4'b0; + assign axi_req_o.aw.atop = '0; // currently not used + // data + assign axi_req_o.w.data = wr_data_i[wr_cnt_q]; + assign axi_req_o.w.strb = wr_be_i[wr_cnt_q]; + assign axi_req_o.w.last = wr_cnt_done; + + // response + assign axi_req_o.b_ready = wr_rdy_i; + assign wr_valid_o = axi_resp_i.b_valid; + assign wr_id_o = axi_resp_i.b.id; + + // tx counter + assign wr_cnt_done = (wr_cnt_q == wr_blen_i); + assign wr_cnt_d = (wr_cnt_clr) ? '0 : + (wr_cnt_en) ? wr_cnt_q+1 : + wr_cnt_q; + + always_comb begin : p_axi_write_fsm + // default + wr_state_d = wr_state_q; + + axi_req_o.aw_valid = 1'b0; + axi_req_o.w_valid = 1'b0; + wr_gnt_o = 1'b0; + + wr_cnt_en = 1'b0; + wr_cnt_clr = 1'b0; + + case (wr_state_q) + /////////////////////////////////// + IDLE: begin + // we have an incoming request + if (wr_req_i) begin + // is this a read or write? + axi_req_o.aw_valid = 1'b1; + axi_req_o.w_valid = 1'b1; + + // its a single write + if (wr_single_req) begin + wr_cnt_clr = 1'b1; + // single req can be granted here + wr_gnt_o = axi_resp_i.aw_ready & axi_resp_i.w_ready; + case ({axi_resp_i.aw_ready, axi_resp_i.w_ready}) + 2'b01: wr_state_d = WAIT_AW_READY; + 2'b10: wr_state_d = WAIT_LAST_W_READY; + default: wr_state_d = IDLE; + endcase + // its a request for the whole cache line + end else begin + wr_cnt_en = axi_resp_i.w_ready; + + case ({axi_resp_i.aw_ready, axi_resp_i.w_ready}) + 2'b11: wr_state_d = WAIT_LAST_W_READY; + 2'b01: wr_state_d = WAIT_LAST_W_READY_AW_READY; + 2'b10: wr_state_d = WAIT_LAST_W_READY; + default:; + endcase + end + end + end + /////////////////////////////////// + // ~> from single write + WAIT_AW_READY: begin + axi_req_o.aw_valid = 1'b1; + + if (axi_resp_i.aw_ready) begin + wr_state_d = IDLE; + wr_gnt_o = 1'b1; + end + end + /////////////////////////////////// + // ~> we need to wait for an aw_ready and there is at least one outstanding write + WAIT_LAST_W_READY_AW_READY: begin + axi_req_o.w_valid = 1'b1; + axi_req_o.aw_valid = 1'b1; + // we got an aw_ready + case ({axi_resp_i.aw_ready, axi_resp_i.w_ready}) + // we got an aw ready + 2'b01: begin + // are there any outstanding transactions? + if (wr_cnt_done) begin + wr_state_d = WAIT_AW_READY_BURST; + wr_cnt_clr = 1'b1; + end else begin + // yes, so reduce the count and stay here + wr_cnt_en = 1'b1; + end + end + 2'b10: wr_state_d = WAIT_LAST_W_READY; + 2'b11: begin + // we are finished + if (wr_cnt_done) begin + wr_state_d = IDLE; + wr_gnt_o = 1'b1; + wr_cnt_clr = 1'b1; + // there are outstanding transactions + end else begin + wr_state_d = WAIT_LAST_W_READY; + wr_cnt_en = 1'b1; + end + end + default:; + endcase + end + /////////////////////////////////// + // ~> all data has already been sent, we are only waiting for the aw_ready + WAIT_AW_READY_BURST: begin + axi_req_o.aw_valid = 1'b1; + + if (axi_resp_i.aw_ready) begin + wr_state_d = IDLE; + wr_gnt_o = 1'b1; + end + end + /////////////////////////////////// + // ~> from write, there is an outstanding write + WAIT_LAST_W_READY: begin + axi_req_o.w_valid = 1'b1; + + // this is the last write + if (wr_cnt_done) begin + if (axi_resp_i.w_ready) begin + wr_state_d = IDLE; + wr_cnt_clr = 1'b1; + wr_gnt_o = 1'b1; + end + end else if (axi_resp_i.w_ready) begin + wr_cnt_en = 1'b1; + end + end + /////////////////////////////////// + default: begin + wr_state_d = IDLE; + end + endcase + end + + +/////////////////////////////////////////////////////// +// read channel +/////////////////////////////////////////////////////// + + // AXI tx counter + logic [ADDR_INDEX-1:0] rd_cnt_d, rd_cnt_q; + logic rd_single_req, rd_cnt_clr, rd_cnt_en; + logic [DATA_WORDS-1:0][63:0] rd_data_d, rd_data_q; + logic rd_valid_d, rd_valid_q; + logic [AXI_ID_WIDTH-1:0] rd_id_d, rd_id_q; + + assign rd_single_req = (rd_blen_i == 0); + + // address + // in case of a single request or wrapping transfer we can simply begin at the address, if we want to request a cache-line + // with an incremental transfer we need to output the corresponding base address of the cache line + assign axi_req_o.ar.burst = (rd_single_req) ? 2'b00 : + (CRITICAL_WORD_FIRST) ? 2'b10 : + 2'b01; // wrapping transfer in case of a critical word first strategy + assign axi_req_o.ar.addr = rd_addr_i; + assign axi_req_o.ar.size = rd_size_i; + assign axi_req_o.ar.len = rd_blen_i; + assign axi_req_o.ar.id = rd_id_i; + assign axi_req_o.ar.prot = 3'b0; + assign axi_req_o.ar.region = 4'b0; + assign axi_req_o.ar.lock = 1'b0; + assign axi_req_o.ar.cache = 4'b0; + assign axi_req_o.ar.qos = 4'b0; + + // make the read request + assign axi_req_o.ar_valid = rd_req_i; + assign rd_gnt_o = rd_req_i & axi_resp_i.ar_ready; + + // return path + // we are always ready + assign axi_req_o.r_ready = rd_rdy_i; + + assign rd_cnt_en = axi_resp_i.r_valid; + assign rd_cnt_clr = axi_resp_i.r.last; + assign rd_valid_d = axi_resp_i.r_valid & axi_resp_i.r.last; + assign rd_valid_o = rd_valid_q; + + assign rd_id_d = axi_resp_i.r.id; + assign rd_id_o = rd_id_q; + assign rd_data_o = rd_data_q; + // used to determine critical word + assign rd_word_o = axi_resp_i.r.data; + assign rd_word_valid_o = axi_resp_i.r_valid; + assign rd_word_cnt_o = rd_cnt_q; + + // tx counter + assign rd_cnt_d = (rd_cnt_clr) ? '0 : + (rd_cnt_en) ? rd_cnt_q+1 : + rd_cnt_q; + + generate + for(genvar k=0; k we are here as we need a second round of memory access for a store @@ -304,8 +304,7 @@ module cache_ctrl #( addr_o = mem_req_q.index; - if (gnt_i) - state_d = WAIT_TAG_SAVED; + if (gnt_i) state_d = WAIT_TAG_SAVED; end end @@ -422,15 +421,15 @@ module cache_ctrl #( end end - `ifndef SYNTHESIS - `ifndef verilator + //pragma translate_off + `ifndef VERILATOR initial begin assert (DCACHE_LINE_WIDTH == 128) else $error ("Cacheline width has to be 128 for the moment. But only small changes required in data select logic"); end // if the full MSHR address matches so should also match the partial one - partial_full_mshr_match: assert property(@(posedge clk_i) disable iff (rst_ni !== 1'b0) mshr_addr_matches_i -> mshr_index_matches_i) else $fatal ("partial mshr index doesn't match"); - // there should never be a valid answer when the MSHR matches - no_valid_on_mshr_match: assert property(@(posedge clk_i) disable iff (rst_ni !== 1'b0) mshr_addr_matches_i -> !req_port_o.data_rvalid) else $fatal ("rvalid_o should not be set on MSHR match"); - `endif + partial_full_mshr_match: assert property(@(posedge clk_i) disable iff (~rst_ni) mshr_addr_matches_i -> mshr_index_matches_i) else $fatal (1, "partial mshr index doesn't match"); + // there should never be a valid answer when the MSHR matches and we are not being served + no_valid_on_mshr_match: assert property(@(posedge clk_i) disable iff (~rst_ni) (mshr_addr_matches_i && !active_serving_i)-> !req_port_o.data_rvalid || req_port_i.kill_req) else $fatal (1, "rvalid_o should not be set on MSHR match"); `endif + //pragma translate_on endmodule diff --git a/src/cache_subsystem/miss_handler.sv b/src/cache_subsystem/miss_handler.sv index 31eed3a14f..c875ce4a79 100644 --- a/src/cache_subsystem/miss_handler.sv +++ b/src/cache_subsystem/miss_handler.sv @@ -19,9 +19,7 @@ import ariane_pkg::*; import std_cache_pkg::*; module miss_handler #( - parameter int unsigned NR_PORTS = 3, - parameter int unsigned AXI_ID_WIDTH = 10, - parameter int unsigned AXI_USER_WIDTH = 1 + parameter int unsigned NR_PORTS = 3 )( input logic clk_i, input logic rst_ni, @@ -35,14 +33,19 @@ module miss_handler #( output logic [NR_PORTS-1:0] bypass_gnt_o, output logic [NR_PORTS-1:0] bypass_valid_o, output logic [NR_PORTS-1:0][63:0] bypass_data_o, - AXI_BUS.Master bypass_if, + + // AXI port + output ariane_axi::req_t axi_bypass_o, + input ariane_axi::resp_t axi_bypass_i, + // Miss handling (~> cacheline refill) output logic [NR_PORTS-1:0] miss_gnt_o, output logic [NR_PORTS-1:0] active_serving_o, output logic [63:0] critical_word_o, output logic critical_word_valid_o, - AXI_BUS.Master data_if, + output ariane_axi::req_t axi_data_o, + input ariane_axi::resp_t axi_data_i, input logic [NR_PORTS-1:0][55:0] mshr_addr_i, output logic [NR_PORTS-1:0] mshr_addr_matches_o, @@ -101,7 +104,7 @@ module miss_handler #( logic [DCACHE_LINE_WIDTH-1:0] req_fsm_miss_wdata; logic req_fsm_miss_we; logic [(DCACHE_LINE_WIDTH/8)-1:0] req_fsm_miss_be; - req_t req_fsm_miss_req; + ariane_axi::ad_req_t req_fsm_miss_req; logic [1:0] req_fsm_miss_size; logic gnt_miss_fsm; @@ -150,7 +153,7 @@ module miss_handler #( req_fsm_miss_wdata = '0; req_fsm_miss_we = 1'b0; req_fsm_miss_be = '0; - req_fsm_miss_req = CACHE_LINE_REQ; + req_fsm_miss_req = ariane_axi::CACHE_LINE_REQ; req_fsm_miss_size = 2'b11; // core flush_ack_o = 1'b0; @@ -165,7 +168,6 @@ module miss_handler #( evict_cl_d = evict_cl_q; mshr_d = mshr_q; // communicate to the requester which unit we are currently serving - active_serving_o = '0; active_serving_o[mshr_q.id] = mshr_q.valid; // AMOs amo_resp_o.ack = 1'b0; @@ -382,7 +384,7 @@ module miss_handler #( req_fsm_miss_valid = 1'b1; // address is in operand a req_fsm_miss_addr = amo_req_i.operand_a; - req_fsm_miss_req = SINGLE_REQ; + req_fsm_miss_req = ariane_axi::SINGLE_REQ; req_fsm_miss_size = amo_req_i.size; // the request has been granted if (gnt_miss_fsm) begin @@ -411,11 +413,28 @@ module miss_handler #( amo_operand_b = amo_req_i.operand_b; end - // we do not need a store request for load reserved - req_fsm_miss_valid = (amo_req_i.amo_op == AMO_LR) ? 1'b0 : 1'b1; - // for a load reserved we do not want to write - req_fsm_miss_we = (amo_req_i.amo_op == AMO_LR) ? 1'b0 : 1'b1; - req_fsm_miss_req = SINGLE_REQ; + // we do not need a store request for load reserved or a failing store conditional + // we can bail-out without making any further requests + if (amo_req_i.amo_op == AMO_LR || + (amo_req_i.amo_op == AMO_SC && + ((reservation_q.valid && reservation_q.address != amo_req_i.operand_a[63:3]) || !reservation_q.valid))) begin + req_fsm_miss_valid = 1'b0; + state_d = IDLE; + amo_resp_o.ack = 1'b1; + // write-back the result + amo_resp_o.result = amo_operand_a; + // we know that the SC failed + if (amo_req_i.amo_op == AMO_SC) begin + amo_resp_o.result = 1'b1; + // also clear the reservation + reservation_d.valid = 1'b0; + end + end else begin + req_fsm_miss_valid = 1'b1; + end + + req_fsm_miss_we = 1'b1; + req_fsm_miss_req = ariane_axi::SINGLE_REQ; req_fsm_miss_size = amo_req_i.size; req_fsm_miss_addr = amo_req_i.operand_a; @@ -429,20 +448,16 @@ module miss_handler #( end // the request is valid or we didn't need to go for another store - if (valid_miss_fsm || (amo_req_i.amo_op == AMO_LR)) begin + if (valid_miss_fsm) begin state_d = IDLE; amo_resp_o.ack = 1'b1; // write-back the result amo_resp_o.result = amo_operand_a; - // in case we have a SC we need to look into the reservation table + if (amo_req_i.amo_op == AMO_SC) begin - if (reservation_q.address == amo_req_i.operand_a[63:3] && reservation_q.valid) begin - amo_resp_o.result = 1'b0; - end else begin - amo_resp_o.result = 1'b1; - end + amo_resp_o.result = 1'b0; // An SC must fail if there is a nother SC (to any address) between the LR and the SC in program - // order. + // order (even to the same address). // in any case destory the reservation reservation_d.valid = 1'b0; end @@ -492,13 +507,13 @@ module miss_handler #( end end - `ifndef SYNTHESIS + //pragma translate_off `ifndef VERILATOR // assert that cache only hits on one way assert property ( @(posedge clk_i) $onehot0(evict_way_q)) else $warning("Evict-way should be one-hot encoded"); `endif - `endif + //pragma translate_on // ---------------------- // Bypass Arbiter // ---------------------- @@ -513,8 +528,8 @@ module miss_handler #( logic valid_bypass_fsm; logic [63:0] data_bypass_fsm; logic [$clog2(NR_PORTS)-1:0] id_fsm_bypass; - logic [AXI_ID_WIDTH-1:0] id_bypass_fsm; - logic [AXI_ID_WIDTH-1:0] gnt_id_bypass_fsm; + logic [3:0] id_bypass_fsm; + logic [3:0] gnt_id_bypass_fsm; arbiter #( .NR_PORTS ( NR_PORTS ), @@ -547,35 +562,41 @@ module miss_handler #( ); axi_adapter #( - .DATA_WIDTH ( 64 ), - .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + .DATA_WIDTH ( 64 ), + .AXI_ID_WIDTH ( 4 ), + .CACHELINE_BYTE_OFFSET ( DCACHE_BYTE_OFFSET ) ) i_bypass_axi_adapter ( - .req_i ( req_fsm_bypass_valid ), - .type_i ( SINGLE_REQ ), - .gnt_o ( gnt_bypass_fsm ), - .addr_i ( req_fsm_bypass_addr ), - .we_i ( req_fsm_bypass_we ), - .wdata_i ( req_fsm_bypass_wdata ), - .be_i ( req_fsm_bypass_be ), - .size_i ( req_fsm_bypass_size ), - .id_i ( {{{AXI_ID_WIDTH-$clog2(NR_PORTS)}{1'b0}}, id_fsm_bypass} ), - .valid_o ( valid_bypass_fsm ), - .rdata_o ( data_bypass_fsm ), - .gnt_id_o ( gnt_id_bypass_fsm ), - .id_o ( id_bypass_fsm ), - .critical_word_o ( ), // not used for single requests - .critical_word_valid_o ( ), // not used for single requests - .axi ( bypass_if ), - .* + .clk_i, + .rst_ni, + .req_i ( req_fsm_bypass_valid ), + .type_i ( ariane_axi::SINGLE_REQ ), + .gnt_o ( gnt_bypass_fsm ), + .addr_i ( req_fsm_bypass_addr ), + .we_i ( req_fsm_bypass_we ), + .wdata_i ( req_fsm_bypass_wdata ), + .be_i ( req_fsm_bypass_be ), + .size_i ( req_fsm_bypass_size ), + .id_i ( {2'b10, id_fsm_bypass} ), + .valid_o ( valid_bypass_fsm ), + .rdata_o ( data_bypass_fsm ), + .gnt_id_o ( gnt_id_bypass_fsm ), + .id_o ( id_bypass_fsm ), + .critical_word_o ( ), // not used for single requests + .critical_word_valid_o ( ), // not used for single requests + .axi_req_o ( axi_bypass_o ), + .axi_resp_i ( axi_bypass_i ) ); // ---------------------- // Cache Line AXI Refill // ---------------------- axi_adapter #( - .DATA_WIDTH ( DCACHE_LINE_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + .DATA_WIDTH ( DCACHE_LINE_WIDTH ), + .AXI_ID_WIDTH ( 4 ), + .CACHELINE_BYTE_OFFSET ( DCACHE_BYTE_OFFSET ) ) i_miss_axi_adapter ( + .clk_i, + .rst_ni, .req_i ( req_fsm_miss_valid ), .type_i ( req_fsm_miss_req ), .gnt_o ( gnt_miss_fsm ), @@ -584,13 +605,15 @@ module miss_handler #( .wdata_i ( req_fsm_miss_wdata ), .be_i ( req_fsm_miss_be ), .size_i ( req_fsm_miss_size ), - .id_i ( '0 ), + .id_i ( 4'b1100 ), .gnt_id_o ( ), // open .valid_o ( valid_miss_fsm ), .rdata_o ( data_miss_fsm ), .id_o ( ), - .axi ( data_if ), - .* + .critical_word_o, + .critical_word_valid_o, + .axi_req_o ( axi_data_o ), + .axi_resp_i ( axi_data_i ) ); // ----------------- @@ -631,13 +654,6 @@ module miss_handler #( miss_req_size [i] = miss_req.size; end end - - `ifndef SYNTHESIS - initial begin - assert (AXI_ID_WIDTH >= $clog2(NR_PORTS)) else $fatal (1, "AXI ID Width needs to be larger than number of requestors"); - end - `endif - endmodule // -------------- @@ -762,7 +778,7 @@ module arbiter #( // Assertions // ------------ - `ifndef SYNTHESIS + //pragma translate_off `ifndef VERILATOR // make sure that we eventually get an rvalid after we received a grant assert property (@(posedge clk_i) data_gnt_i |-> ##[1:$] data_rvalid_i ) @@ -775,5 +791,5 @@ module arbiter #( else begin $error("address contains X when request is set"); $stop(); end `endif - `endif + //pragma translate_on endmodule diff --git a/src/cache_subsystem/serpent_cache_subsystem.sv b/src/cache_subsystem/serpent_cache_subsystem.sv new file mode 100644 index 0000000000..0505ecd431 --- /dev/null +++ b/src/cache_subsystem/serpent_cache_subsystem.sv @@ -0,0 +1,337 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: Ariane cache subsystem that is compatible with the OpenPiton +// coherent memory system. +// +// Define PITON_ARIANE if you want to use this cache. +// Define AXI64_CACHE_PORTS if you want to use this cache +// with a standard 64bit AXI interace instead of the openpiton +// L1.5 interface. + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module serpent_cache_subsystem #( +`ifdef AXI64_CACHE_PORTS + parameter int unsigned AxiIdWidth = 10, +`endif + parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region + parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region + parameter bit SwapEndianess = 0 // swap endianess in l15 adapter +) ( + input logic clk_i, + input logic rst_ni, + // I$ + input logic icache_en_i, // enable icache (or bypass e.g: in debug mode) + input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together + output logic icache_miss_o, // to performance counter + // address translation requests + input icache_areq_i_t icache_areq_i, // to/from frontend + output icache_areq_o_t icache_areq_o, + // data requests + input icache_dreq_i_t icache_dreq_i, // to/from frontend + output icache_dreq_o_t icache_dreq_o, + // D$ + // Cache management + input logic dcache_enable_i, // from CSR + input logic dcache_flush_i, // high until acknowledged + output logic dcache_flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic dcache_miss_o, // we missed on a ld/st + // AMO interface + input amo_req_t dcache_amo_req_i, + output amo_resp_t dcache_amo_resp_o, + // Request ports + input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU + output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU + // writebuffer status + output logic wbuffer_empty_o, +`ifdef AXI64_CACHE_PORTS + // memory side + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i +`else + // L15 (memory side) + output l15_req_t l15_req_o, + input l15_rtrn_t l15_rtrn_i +`endif + // TODO: interrupt interface +); + +logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld; +serpent_cache_pkg::icache_req_t icache_adapter; +serpent_cache_pkg::icache_rtrn_t adapter_icache; + + +logic dcache_adapter_data_req, adapter_dcache_data_ack, adapter_dcache_rtrn_vld; +serpent_cache_pkg::dcache_req_t dcache_adapter; +serpent_cache_pkg::dcache_rtrn_t adapter_dcache; + +`ifdef AXI64_CACHE_PORTS +// used for local plumbing in this case +l15_req_t l15_req; +l15_rtrn_t l15_rtrn; +`endif + +serpent_icache #( +`ifdef AXI64_CACHE_PORTS + .Axi64BitCompliant ( 1'b1 ), +`endif + // use ID 0 for icache reads + .RdTxId ( 0 ), + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ) + ) i_serpent_icache ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( icache_flush_i ), + .en_i ( icache_en_i ), + .miss_o ( icache_miss_o ), + .areq_i ( icache_areq_i ), + .areq_o ( icache_areq_o ), + .dreq_i ( icache_dreq_i ), + .dreq_o ( icache_dreq_o ), + .mem_rtrn_vld_i ( adapter_icache_rtrn_vld ), + .mem_rtrn_i ( adapter_icache ), + .mem_data_req_o ( icache_adapter_data_req ), + .mem_data_ack_i ( adapter_icache_data_ack ), + .mem_data_o ( icache_adapter ) + ); + + +// Note: +// Ports 0/1 for PTW and LD unit are read only. +// they have equal prio and are RR arbited +// Port 2 is write only and goes into the merging write buffer +serpent_dcache #( + // use ID 1 for dcache reads and amos. note that the writebuffer + // uses all IDs up to DCACHE_MAX_TX-1 for write transactions. + .RdAmoTxId ( 1 ), + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ) + ) i_serpent_dcache ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .enable_i ( dcache_enable_i ), + .flush_i ( dcache_flush_i ), + .flush_ack_o ( dcache_flush_ack_o ), + .miss_o ( dcache_miss_o ), + .wbuffer_empty_o ( wbuffer_empty_o ), + .amo_req_i ( dcache_amo_req_i ), + .amo_resp_o ( dcache_amo_resp_o ), + .req_ports_i ( dcache_req_ports_i ), + .req_ports_o ( dcache_req_ports_o ), + .mem_rtrn_vld_i ( adapter_dcache_rtrn_vld ), + .mem_rtrn_i ( adapter_dcache ), + .mem_data_req_o ( dcache_adapter_data_req ), + .mem_data_ack_i ( adapter_dcache_data_ack ), + .mem_data_o ( dcache_adapter ) + ); + + +// arbiter/adapter +serpent_l15_adapter #( + .SwapEndianess ( SwapEndianess ), + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ) + ) i_adapter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .icache_data_req_i ( icache_adapter_data_req ), + .icache_data_ack_o ( adapter_icache_data_ack ), + .icache_data_i ( icache_adapter ), + .icache_rtrn_vld_o ( adapter_icache_rtrn_vld ), + .icache_rtrn_o ( adapter_icache ), + .dcache_data_req_i ( dcache_adapter_data_req ), + .dcache_data_ack_o ( adapter_dcache_data_ack ), + .dcache_data_i ( dcache_adapter ), + .dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ), + .dcache_rtrn_o ( adapter_dcache ), +`ifdef AXI64_CACHE_PORTS + .l15_req_o ( l15_req ), + .l15_rtrn_i ( l15_rtrn ) +`else + .l15_req_o ( l15_req_o ), + .l15_rtrn_i ( l15_rtrn_i ) +`endif + ); + +/////////////////////////////////////////////////////// +// different memory plumbing to allow for using the +// serpent cache subsystem in a standard AXI setting +// for verificaton purposes. +/////////////////////////////////////////////////////// + +`ifdef AXI64_CACHE_PORTS + +// support up to 512bit cache lines +localparam AxiNumWords = 8; + +logic axi_rd_req, axi_rd_gnt; +logic [63:0] axi_rd_addr, axi_wr_addr; +logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen; +logic [1:0] axi_rd_size, axi_wr_size; +logic [AxiIdWidth-1:0] axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out; +logic axi_rd_valid; +logic [AxiNumWords-1:0][63:0] axi_rd_data, axi_wr_data; +logic [AxiNumWords-1:0][7:0] axi_wr_be; +logic axi_wr_req, axi_wr_gnt; +logic axi_wr_valid, axi_rd_rdy, axi_wr_rdy; + +logic ifill; +logic [serpent_cache_pkg::L15_TID_WIDTH+2-1:0] id_tmp; +logic rd_pending_d, rd_pending_q; + +// request side +assign ifill = (l15_req.l15_rqtype==serpent_cache_pkg::L15_IMISS_RQ); + +assign axi_rd_req = l15_req.l15_val && (l15_req.l15_rqtype==serpent_cache_pkg::L15_LOAD_RQ | ifill) && !rd_pending_q; +assign axi_wr_req = l15_req.l15_val && (l15_req.l15_rqtype==serpent_cache_pkg::L15_STORE_RQ); + +assign axi_rd_addr = l15_req.l15_address; +assign axi_wr_addr = axi_rd_addr; + +// the axi interconnect does not correctly handle the ordering of read responses. +// workaround: only allow for one outstanding TX. need to improve this. +assign rd_pending_d = (axi_rd_valid ) ? '0 : rd_pending_q | axi_rd_gnt; + +assign axi_rd_id_in = {l15_req.l15_threadid, ifill, l15_req.l15_nc}; +assign axi_wr_id_in = axi_rd_id_in; + +assign axi_rd_size = (ifill) ? 2'b11 : l15_req.l15_size[1:0];// always request 64bit words in case of ifill +assign axi_wr_size = l15_req.l15_size[1:0]; + +assign axi_rd_blen = (l15_req.l15_size[2]) ? ((ifill) ? ariane_pkg::ICACHE_LINE_WIDTH/64-1 : + ariane_pkg::DCACHE_LINE_WIDTH/64-1) : '0; +assign axi_wr_blen = '0;// single word writes + +assign axi_wr_data = l15_req.l15_data; +assign axi_wr_be = (axi_wr_req) ? serpent_cache_pkg::toByteEnable8(axi_wr_addr[2:0], axi_wr_size) : '0; + + +// return path +always_comb begin : p_axi_rtrn + // default + l15_rtrn = '0; + + // from request path + l15_rtrn.l15_ack = axi_rd_gnt | axi_wr_gnt; + l15_rtrn.l15_header_ack = axi_rd_gnt | axi_wr_gnt; + + // we are always ready to consume packets unconditionally, + // but in case of returning reads, we have to stall the write response + axi_rd_rdy = 1'b1; + axi_wr_rdy = ~axi_rd_valid;// this vld signal comes directly from a register + + // unconditionally consume packets + l15_rtrn.l15_val = axi_rd_valid | axi_wr_valid; + + // encode packet type + id_tmp = (axi_rd_valid) ? axi_rd_id_out : axi_wr_id_out; + l15_rtrn.l15_returntype = (axi_rd_valid && id_tmp[1]) ? L15_IFILL_RET : + (axi_rd_valid) ? L15_LOAD_RET : + L15_ST_ACK; + + // decode id and set flags accordingly + l15_rtrn.l15_noncacheable = id_tmp[0]; + l15_rtrn.l15_threadid = id_tmp>>2; + // 4B non-cacheable ifill + l15_rtrn.l15_f4b = id_tmp[0] & id_tmp[1] & axi_rd_valid; + + l15_rtrn.l15_data_0 = axi_rd_data[0]; + l15_rtrn.l15_data_1 = axi_rd_data[1]; + l15_rtrn.l15_data_2 = axi_rd_data[2]; + l15_rtrn.l15_data_3 = axi_rd_data[3]; +end + +always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if(~rst_ni) begin + rd_pending_q <= '0; + end else begin + rd_pending_q <= rd_pending_d; + end +end + + +axi_adapter2 #( + .DATA_WORDS ( AxiNumWords ), + .AXI_ID_WIDTH ( AxiIdWidth ) +) i_axi_adapter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .rd_req_i ( axi_rd_req ), + .rd_gnt_o ( axi_rd_gnt ), + .rd_addr_i ( axi_rd_addr ), + .rd_blen_i ( axi_rd_blen ), + .rd_size_i ( axi_rd_size ), + .rd_id_i ( axi_rd_id_in ), + .rd_rdy_i ( axi_rd_rdy ), + .rd_valid_o ( axi_rd_valid ), + .rd_data_o ( axi_rd_data ), + .rd_id_o ( axi_rd_id_out ), + .rd_word_o ( ), + .rd_word_valid_o ( ), + .rd_word_cnt_o ( ), + .wr_req_i ( axi_wr_req ), + .wr_gnt_o ( axi_wr_gnt ), + .wr_addr_i ( axi_wr_addr ), + .wr_data_i ( axi_wr_data ), + .wr_be_i ( axi_wr_be ), + .wr_blen_i ( axi_wr_blen ), + .wr_size_i ( axi_wr_size ), + .wr_id_i ( axi_wr_id_in ), + .wr_rdy_i ( axi_wr_rdy ), + .wr_valid_o ( axi_wr_valid ), + .wr_id_o ( axi_wr_id_out ), + .axi_req_o ( axi_req_o ), + .axi_resp_i ( axi_resp_i ) +); + +`endif + + +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + +//pragma translate_off +`ifndef VERILATOR + +`ifdef AXI64_CACHE_PORTS + initial begin + assert (AxiIdWidth >= $clog2(serpent_cache_pkg::DCACHE_MAX_TX)+2) else + $fatal(1,$psprintf("[l1 cache] AXI ID must be at least %01d bit wide", $clog2(serpent_cache_pkg::DCACHE_MAX_TX)+2)); + end +`endif + +a_invalid_instruction_fetch: assert property ( + @(posedge clk_i) disable iff (~rst_ni) icache_dreq_o.valid |-> (|icache_dreq_o.data) !== 1'hX) +else $warning(1,"[l1 dcache] reading invalid instructions: vaddr=%08X, data=%08X", + icache_dreq_o.vaddr, icache_dreq_o.data); + +a_invalid_write_data: assert property ( + @(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX) +else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X", + {dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata); + + +for(genvar j=0; j<2; j++) begin : g_assertion + a_invalid_read_data: assert property ( + @(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX) + else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X", + j, dcache_req_ports_o[j].data_rdata); +end +`endif +//pragma translate_on + + +endmodule // serpent_cache_subsystem diff --git a/src/cache_subsystem/serpent_dcache.sv b/src/cache_subsystem/serpent_dcache.sv new file mode 100644 index 0000000000..c1c8c40458 --- /dev/null +++ b/src/cache_subsystem/serpent_dcache.sv @@ -0,0 +1,329 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: Instruction cache that is compatible with openpiton. + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module serpent_dcache #( + // ID to be used for read and AMO transactions. + // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions + parameter logic [DCACHE_ID_WIDTH-1:0] RdAmoTxId = 1, + parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region + parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000 // end of cached region +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + + // Cache management + input logic enable_i, // from CSR + input logic flush_i, // high until acknowledged + output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic miss_o, // we missed on a ld/st + output logic wbuffer_empty_o, + + // AMO interface + input amo_req_t amo_req_i, + output amo_resp_t amo_resp_o, + + // Request ports + input dcache_req_i_t [2:0] req_ports_i, + output dcache_req_o_t [2:0] req_ports_o, + + input logic mem_rtrn_vld_i, + input dcache_rtrn_t mem_rtrn_i, + output logic mem_data_req_o, + input logic mem_data_ack_i, + output dcache_req_t mem_data_o +); + + // LD unit and PTW + localparam NumPorts = 3; + + // miss unit <-> read controllers + logic cache_en; + + // miss unit <-> memory + logic wr_cl_vld; + logic wr_cl_nc; + logic [DCACHE_SET_ASSOC-1:0] wr_cl_we; + logic [DCACHE_TAG_WIDTH-1:0] wr_cl_tag; + logic [DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx; + logic [DCACHE_OFFSET_WIDTH-1:0] wr_cl_off; + logic [DCACHE_LINE_WIDTH-1:0] wr_cl_data; + logic [DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be; + logic [DCACHE_SET_ASSOC-1:0] wr_vld_bits; + logic [DCACHE_SET_ASSOC-1:0] wr_req; + logic wr_ack; + logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx; + logic [DCACHE_OFFSET_WIDTH-1:0] wr_off; + logic [63:0] wr_data; + logic [7:0] wr_data_be; + + // miss unit <-> controllers/wbuffer + logic [NumPorts-1:0] miss_req; + logic [NumPorts-1:0] miss_ack; + logic [NumPorts-1:0] miss_nc; + logic [NumPorts-1:0] miss_we; + logic [NumPorts-1:0][63:0] miss_wdata; + logic [NumPorts-1:0][63:0] miss_paddr; + logic [NumPorts-1:0][DCACHE_SET_ASSOC-1:0] miss_vld_bits; + logic [NumPorts-1:0][2:0] miss_size; + logic [NumPorts-1:0][DCACHE_ID_WIDTH-1:0] miss_id; + logic [NumPorts-1:0] miss_replay; + logic [NumPorts-1:0] miss_rtrn_vld; + logic [DCACHE_ID_WIDTH-1:0] miss_rtrn_id; + + // memory <-> read controllers/miss unit + logic [NumPorts-1:0] rd_prio; + logic [NumPorts-1:0] rd_tag_only; + logic [NumPorts-1:0] rd_req; + logic [NumPorts-1:0] rd_ack; + logic [NumPorts-1:0][DCACHE_TAG_WIDTH-1:0] rd_tag; + logic [NumPorts-1:0][DCACHE_CL_IDX_WIDTH-1:0] rd_idx; + logic [NumPorts-1:0][DCACHE_OFFSET_WIDTH-1:0] rd_off; + logic [63:0] rd_data; + logic [DCACHE_SET_ASSOC-1:0] rd_vld_bits; + logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh; + + // miss unit <-> wbuffer + logic [DCACHE_MAX_TX-1:0][63:0] tx_paddr; + logic [DCACHE_MAX_TX-1:0] tx_vld; + + // wbuffer <-> memory + wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_data; + + +/////////////////////////////////////////////////////// +// miss handling unit +/////////////////////////////////////////////////////// + + serpent_dcache_missunit #( + .AmoTxId ( RdAmoTxId ), + .NumPorts ( NumPorts ) + ) i_serpent_dcache_missunit ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .enable_i ( enable_i ), + .flush_i ( flush_i ), + .flush_ack_o ( flush_ack_o ), + .miss_o ( miss_o ), + .wbuffer_empty_i ( wbuffer_empty_o ), + .cache_en_o ( cache_en ), + // amo interface + .amo_req_i ( amo_req_i ), + .amo_resp_o ( amo_resp_o ), + // miss handling interface + .miss_req_i ( miss_req ), + .miss_ack_o ( miss_ack ), + .miss_nc_i ( miss_nc ), + .miss_we_i ( miss_we ), + .miss_wdata_i ( miss_wdata ), + .miss_paddr_i ( miss_paddr ), + .miss_vld_bits_i ( miss_vld_bits ), + .miss_size_i ( miss_size ), + .miss_id_i ( miss_id ), + .miss_replay_o ( miss_replay ), + .miss_rtrn_vld_o ( miss_rtrn_vld ), + .miss_rtrn_id_o ( miss_rtrn_id ), + // from writebuffer + .tx_paddr_i ( tx_paddr ), + .tx_vld_i ( tx_vld ), + // cache memory interface + .wr_cl_vld_o ( wr_cl_vld ), + .wr_cl_nc_o ( wr_cl_nc ), + .wr_cl_we_o ( wr_cl_we ), + .wr_cl_tag_o ( wr_cl_tag ), + .wr_cl_idx_o ( wr_cl_idx ), + .wr_cl_off_o ( wr_cl_off ), + .wr_cl_data_o ( wr_cl_data ), + .wr_cl_data_be_o ( wr_cl_data_be ), + .wr_vld_bits_o ( wr_vld_bits ), + // memory interface + .mem_rtrn_vld_i ( mem_rtrn_vld_i ), + .mem_rtrn_i ( mem_rtrn_i ), + .mem_data_req_o ( mem_data_req_o ), + .mem_data_ack_i ( mem_data_ack_i ), + .mem_data_o ( mem_data_o ) + ); + +/////////////////////////////////////////////////////// +// read controllers (LD unit and PTW/MMU) +/////////////////////////////////////////////////////// + + generate + // note: last read port is used by the write buffer + for(genvar k=0; k flush_ack_o |-> wbuffer_empty_o) + else $fatal(1,"[l1 dcache] flushed cache implies flushed wbuffer"); + + initial begin + // assert wrong parameterizations + assert (DCACHE_INDEX_WIDTH<=12) + else $fatal(1,"[l1 dcache] cache index width can be maximum 12bit since VM uses 4kB pages"); + end +`endif +//pragma translate_on + +endmodule // serpent_dcache diff --git a/src/cache_subsystem/serpent_dcache_ctrl.sv b/src/cache_subsystem/serpent_dcache_ctrl.sv new file mode 100644 index 0000000000..5d4cf9a54c --- /dev/null +++ b/src/cache_subsystem/serpent_dcache_ctrl.sv @@ -0,0 +1,267 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: DCache controller for read port + + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module serpent_dcache_ctrl #( + parameter logic [DCACHE_ID_WIDTH-1:0] RdTxId = 1, // ID to use for read transactions + parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region + parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000 // end of cached region +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + input logic cache_en_i, + // core request ports + input dcache_req_i_t req_port_i, + output dcache_req_o_t req_port_o, + // interface to miss handler + output logic miss_req_o, + input logic miss_ack_i, + output logic miss_we_o, // unused (set to 0) + output logic [63:0] miss_wdata_o, // unused (set to 0) + output logic [DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, // valid bits at the missed index + output logic [63:0] miss_paddr_o, + output logic miss_nc_o, // request to I/O space + output logic [2:0] miss_size_o, // 00: 1byte, 01: 2byte, 10: 4byte, 11: 8byte, 111: cacheline + output logic [DCACHE_ID_WIDTH-1:0] miss_id_o, // set to constant ID + input logic miss_replay_i, // request collided with pending miss - have to replay the request + input logic miss_rtrn_vld_i, // signals that the miss has been served, asserted in the same cycle as when the data returns from memory + // used to detect readout mux collisions + input logic wr_cl_vld_i, + // cache memory interface + output logic [DCACHE_TAG_WIDTH-1:0] rd_tag_o, // tag in - comes one cycle later + output logic [DCACHE_CL_IDX_WIDTH-1:0] rd_idx_o, + output logic [DCACHE_OFFSET_WIDTH-1:0] rd_off_o, + output logic rd_req_o, // read the word at offset off_i[:3] in all ways + output logic rd_tag_only_o, // set to zero here + input logic rd_ack_i, + input logic [63:0] rd_data_i, + input logic [DCACHE_SET_ASSOC-1:0] rd_vld_bits_i, + input logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh_i +); + + // controller FSM + typedef enum logic[2:0] {IDLE, READ, MISS_REQ, MISS_WAIT, KILL_MISS, REPLAY_REQ, REPLAY_READ} state_t; + state_t state_d, state_q; + + logic [DCACHE_TAG_WIDTH-1:0] address_tag_d, address_tag_q; + logic [DCACHE_CL_IDX_WIDTH-1:0] address_idx_d, address_idx_q; + logic [DCACHE_OFFSET_WIDTH-1:0] address_off_d, address_off_q; + logic [DCACHE_SET_ASSOC-1:0] vld_data_d, vld_data_q; + logic save_tag, rd_req_d, rd_req_q, rd_ack_d, rd_ack_q; + logic [1:0] data_size_d, data_size_q; + +/////////////////////////////////////////////////////// +// misc +/////////////////////////////////////////////////////// + + // map address to tag/idx/offset and save + assign vld_data_d = (rd_req_q) ? rd_vld_bits_i : vld_data_q; + assign address_tag_d = (save_tag) ? req_port_i.address_tag : address_tag_q; + assign address_idx_d = (req_port_o.data_gnt) ? req_port_i.address_index[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH] : address_idx_q; + assign address_off_d = (req_port_o.data_gnt) ? req_port_i.address_index[DCACHE_OFFSET_WIDTH-1:0] : address_off_q; + assign data_size_d = (req_port_o.data_gnt) ? req_port_i.data_size : data_size_q; + assign rd_tag_o = address_tag_d; + assign rd_idx_o = address_idx_d; + assign rd_off_o = address_off_d; + + assign req_port_o.data_rdata = rd_data_i; + + // to miss unit + assign miss_vld_bits_o = vld_data_q; + assign miss_paddr_o = {address_tag_q, address_idx_q, address_off_q}; + assign miss_size_o = (miss_nc_o) ? data_size_q : 3'b111; + + assign miss_nc_o = (address_tag_q < (CachedAddrBeg>>DCACHE_INDEX_WIDTH)) || + (address_tag_q >= (CachedAddrEnd>>DCACHE_INDEX_WIDTH)) || + (!cache_en_i); + + assign miss_we_o = '0; + assign miss_wdata_o = '0; + assign miss_id_o = RdTxId; + assign rd_req_d = rd_req_o; + assign rd_ack_d = rd_ack_i; + assign rd_tag_only_o = '0; + +/////////////////////////////////////////////////////// +// main control logic +/////////////////////////////////////////////////////// + + always_comb begin : p_fsm + // default assignment + state_d = state_q; + save_tag = 1'b0; + rd_req_o = 1'b0; + miss_req_o = 1'b0; + req_port_o.data_rvalid = 1'b0; + req_port_o.data_gnt = 1'b0; + + // interfaces + unique case (state_q) + ////////////////////////////////// + // wait for an incoming request + IDLE: begin + + if (req_port_i.data_req) begin + rd_req_o = 1'b1; + + if (rd_ack_i) begin + state_d = READ; + req_port_o.data_gnt = 1'b1; + end + end + end + ////////////////////////////////// + // check whether we have a hit + // in case the cache is disabled, + // or in case the address is NC, we + // reuse the miss mechanism to handle + // the request + READ, REPLAY_READ: begin + // speculatively request cache line + rd_req_o = 1'b1; + + // kill -> go back to IDLE + if(req_port_i.kill_req) begin + state_d = IDLE; + req_port_o.data_rvalid = 1'b1; + end else if(req_port_i.tag_valid | state_q==REPLAY_READ) begin + save_tag = (state_q!=REPLAY_READ); + if(wr_cl_vld_i | ~rd_ack_q) begin + state_d = REPLAY_REQ; + // we've got a hit + end else if((|rd_hit_oh_i) & cache_en_i) begin + state_d = IDLE; + req_port_o.data_rvalid = 1'b1; + // we can handle another request + if (rd_ack_i && req_port_i.data_req) begin + state_d = READ; + req_port_o.data_gnt = 1'b1; + end + // we've got a miss + end else begin + state_d = MISS_REQ; + end + end + end + ////////////////////////////////// + // issue request + MISS_REQ: begin + miss_req_o = 1'b1; + + if(req_port_i.kill_req) begin + req_port_o.data_rvalid = 1'b1; + if(miss_ack_i) begin + state_d = KILL_MISS; + end else begin + state_d = IDLE; + end + end else if(miss_replay_i) begin + state_d = REPLAY_REQ; + end else if(miss_ack_i) begin + state_d = MISS_WAIT; + end + end + ////////////////////////////////// + // wait until the memory transaction + // returns. + MISS_WAIT: begin + if(req_port_i.kill_req) begin + req_port_o.data_rvalid = 1'b1; + if(miss_rtrn_vld_i) begin + state_d = IDLE; + end else begin + state_d = KILL_MISS; + end + end else if(miss_rtrn_vld_i) begin + state_d = IDLE; + req_port_o.data_rvalid = 1'b1; + end + end + ////////////////////////////////// + // replay read request + REPLAY_REQ: begin + rd_req_o = 1'b1; + if (req_port_i.kill_req) begin + req_port_o.data_rvalid = 1'b1; + state_d = IDLE; + end else if(rd_ack_i) begin + state_d = REPLAY_READ; + end + end + ////////////////////////////////// + // killed miss, + // wait until miss unit responds and + // go back to idle + KILL_MISS: begin + if (miss_rtrn_vld_i) begin + state_d = IDLE; + end + end + default: begin + // we should never get here + state_d = IDLE; + end + endcase // state_q + end + +/////////////////////////////////////////////////////// +// ff's +/////////////////////////////////////////////////////// + +always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if(~rst_ni) begin + state_q <= IDLE; + address_tag_q <= '0; + address_idx_q <= '0; + address_off_q <= '0; + vld_data_q <= '0; + data_size_q <= '0; + rd_req_q <= '0; + rd_ack_q <= '0; + end else begin + state_q <= state_d; + address_tag_q <= address_tag_d; + address_idx_q <= address_idx_d; + address_off_q <= address_off_d; + vld_data_q <= vld_data_d; + data_size_q <= data_size_d; + rd_req_q <= rd_req_d; + rd_ack_q <= rd_ack_d; + end +end + + +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + +//pragma translate_off +`ifndef VERILATOR + + hot1: assert property ( + @(posedge clk_i) disable iff (~rst_ni) (~rd_ack_i) |=> cache_en_i |-> $onehot0(rd_hit_oh_i)) + else $fatal(1,"[l1 dcache ctrl] rd_hit_oh_i signal must be hot1"); + + initial begin + // assert wrong parameterizations + assert (DCACHE_INDEX_WIDTH<=12) + else $fatal(1,"[l1 dcache ctrl] cache index width can be maximum 12bit since VM uses 4kB pages"); + end +`endif +//pragma translate_on + +endmodule // serpent_dcache_ctrl \ No newline at end of file diff --git a/src/cache_subsystem/serpent_dcache_mem.sv b/src/cache_subsystem/serpent_dcache_mem.sv new file mode 100644 index 0000000000..968617d469 --- /dev/null +++ b/src/cache_subsystem/serpent_dcache_mem.sv @@ -0,0 +1,373 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: Memory arrays, arbiter and tag comparison for serpent dcache. +// +// +// Notes: 1) all ports can trigger a readout of all ways, and the way where the tag hits is selected +// +// 2) only port0 can write full cache lines. higher ports are read only. also, port0 can only read the tag array, +// and does not trigger a cache line readout. +// +// 3) the single word write port is a separate port without access to the tag memory. +// these single word writes can interleave with read operations if they go to different +// cacheline offsets, since each word offset is placed into a different SRAM bank. +// +// 4) Read ports with same priority are RR arbited. but high prio ports (rd_prio_i[port_nr] = '1b1) will stall +// low prio ports (rd_prio_i[port_nr] = '1b0) + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module serpent_dcache_mem #( + parameter int unsigned NumPorts = 3 + )( + input logic clk_i, + input logic rst_ni, + + // ports + input logic [NumPorts-1:0][DCACHE_TAG_WIDTH-1:0] rd_tag_i, // tag in - comes one cycle later + input logic [NumPorts-1:0][DCACHE_CL_IDX_WIDTH-1:0] rd_idx_i, + input logic [NumPorts-1:0][DCACHE_OFFSET_WIDTH-1:0] rd_off_i, + input logic [NumPorts-1:0] rd_req_i, // read the word at offset off_i[:3] in all ways + input logic [NumPorts-1:0] rd_tag_only_i, // only do a tag/valid lookup, no access to data arrays + input logic [NumPorts-1:0] rd_prio_i, // 0: low prio, 1: high prio + output logic [NumPorts-1:0] rd_ack_o, + output logic [DCACHE_SET_ASSOC-1:0] rd_vld_bits_o, + output logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh_o, + output logic [63:0] rd_data_o, + + // only available on port 0, uses address signals of port 0 + input logic wr_cl_vld_i, + input logic wr_cl_nc_i, // noncacheable access + input logic [DCACHE_SET_ASSOC-1:0] wr_cl_we_i, // writes a full cacheline + input logic [DCACHE_TAG_WIDTH-1:0] wr_cl_tag_i, + input logic [DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx_i, + input logic [DCACHE_OFFSET_WIDTH-1:0] wr_cl_off_i, + input logic [DCACHE_LINE_WIDTH-1:0] wr_cl_data_i, + input logic [DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be_i, + input logic [DCACHE_SET_ASSOC-1:0] wr_vld_bits_i, + + // separate port for single word write, no tag access + input logic [DCACHE_SET_ASSOC-1:0] wr_req_i, // write a single word to offset off_i[:3] + output logic wr_ack_o, + input logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx_i, + input logic [DCACHE_OFFSET_WIDTH-1:0] wr_off_i, + input logic [63:0] wr_data_i, + input logic [7:0] wr_data_be_i, + + // forwarded wbuffer + input wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_data_i + ); + + + logic [DCACHE_NUM_BANKS-1:0] bank_req; + logic [DCACHE_NUM_BANKS-1:0] bank_we; + logic [DCACHE_NUM_BANKS-1:0][DCACHE_SET_ASSOC-1:0][7:0] bank_be; + logic [DCACHE_NUM_BANKS-1:0][DCACHE_CL_IDX_WIDTH-1:0] bank_idx; + logic [DCACHE_CL_IDX_WIDTH-1:0] bank_idx_d, bank_idx_q; + logic [DCACHE_OFFSET_WIDTH-1:0] bank_off_d, bank_off_q; + + logic [DCACHE_NUM_BANKS-1:0][DCACHE_SET_ASSOC-1:0][63:0] bank_wdata; // + logic [DCACHE_NUM_BANKS-1:0][DCACHE_SET_ASSOC-1:0][63:0] bank_rdata; // + logic [DCACHE_SET_ASSOC-1:0][63:0] rdata_cl; // selected word from each cacheline + + logic [DCACHE_TAG_WIDTH-1:0] rd_tag; + logic [DCACHE_SET_ASSOC-1:0] vld_req; // bit enable for valid regs + logic vld_we; // valid bits write enable + logic [DCACHE_SET_ASSOC-1:0] vld_wdata; // valid bits to write + logic [DCACHE_SET_ASSOC-1:0][DCACHE_TAG_WIDTH-1:0] tag_rdata; // these are the tags coming from the tagmem + logic [DCACHE_CL_IDX_WIDTH-1:0] vld_addr; // valid bit + + logic [$clog2(NumPorts)-1:0] vld_sel_d, vld_sel_q; + + logic [DCACHE_WBUF_DEPTH-1:0] wbuffer_hit_oh; + logic [7:0] wbuffer_be; + logic [63:0] wbuffer_rdata, rdata; + logic [63:0] wbuffer_cmp_addr; + + logic cmp_en_d, cmp_en_q; + logic rd_acked; + logic [NumPorts-1:0] bank_collision, rd_req_masked, rd_req_prio; + +/////////////////////////////////////////////////////// +// arbiter +/////////////////////////////////////////////////////// + + // Priority is highest for lowest read port index + // + // SRAM bank mapping: + // + // Bank 0 Bank 2 + // [way0, w0] [way1, w0] .. [way0, w1] [way1, w1] .. + + // byte enable mapping + generate + for (genvar k=0;k0 + assign rd_hit_oh_o[i] = (rd_tag == tag_rdata[i]) & rd_vld_bits_o[i] & cmp_en_q; + // byte offset mux of ways >0 + assign rdata_cl[i] = bank_rdata[bank_off_q[DCACHE_OFFSET_WIDTH-1:3]][i]; + end + + for(genvar k=0; k> 3)); + end + endgenerate + + + lzc #( + .WIDTH ( DCACHE_WBUF_DEPTH ) + ) i_lzc_wbuffer_hit ( + .in_i ( wbuffer_hit_oh ), + .cnt_o ( wbuffer_hit_idx ), + .empty_o ( ) + ); + + lzc #( + .WIDTH ( DCACHE_SET_ASSOC ) + ) i_lzc_rd_hit ( + .in_i ( rd_hit_oh_o ), + .cnt_o ( rd_hit_idx ), + .empty_o ( ) + ); + + assign wbuffer_rdata = wbuffer_data_i[wbuffer_hit_idx].data; + assign wbuffer_be = (|wbuffer_hit_oh) ? wbuffer_data_i[wbuffer_hit_idx].valid : '0; + + assign wr_cl_off = (wr_cl_nc_i) ? '0 : wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3]; + assign rdata = (wr_cl_vld_i) ? wr_cl_data_i[wr_cl_off*64 +: 64] : + rdata_cl[rd_hit_idx]; + + // overlay bytes that hit in the write buffer + generate + for(genvar k=0; k<8; k++) begin : g_rd_data + assign rd_data_o[8*k +: 8] = (wbuffer_be[k]) ? wbuffer_rdata[8*k +: 8] : rdata[8*k +: 8]; + end + endgenerate + + + +/////////////////////////////////////////////////////// +// memory arrays and regs +/////////////////////////////////////////////////////// + + logic [DCACHE_TAG_WIDTH:0] vld_tag_rdata [DCACHE_SET_ASSOC-1:0]; + + generate + for (genvar k = 0; k < DCACHE_NUM_BANKS; k++) begin : g_data_banks + // Data RAM + sram #( + .DATA_WIDTH ( ariane_pkg::DCACHE_SET_ASSOC * 64 ), + .NUM_WORDS ( serpent_cache_pkg::DCACHE_NUM_WORDS ) + ) i_data_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( bank_req [k] ), + .we_i ( bank_we [k] ), + .addr_i ( bank_idx [k] ), + .wdata_i ( bank_wdata [k] ), + .be_i ( bank_be [k] ), + .rdata_o ( bank_rdata [k] ) + ); + end + + for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin : g_tag_srams + + assign tag_rdata[i] = vld_tag_rdata[i][DCACHE_TAG_WIDTH-1:0]; + assign rd_vld_bits_o[i] = vld_tag_rdata[i][DCACHE_TAG_WIDTH]; + + // Tag RAM + sram #( + // tag + valid bit + .DATA_WIDTH ( ariane_pkg::DCACHE_TAG_WIDTH + 1 ), + .NUM_WORDS ( serpent_cache_pkg::DCACHE_NUM_WORDS ) + ) i_tag_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( vld_req[i] ), + .we_i ( vld_we ), + .addr_i ( vld_addr ), + .wdata_i ( {vld_wdata[i], wr_cl_tag_i} ), + .be_i ( '1 ), + .rdata_o ( vld_tag_rdata[i] ) + ); + end + endgenerate + + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if(~rst_ni) begin + bank_idx_q <= '0; + bank_off_q <= '0; + vld_sel_q <= '0; + cmp_en_q <= '0; + end else begin + bank_idx_q <= bank_idx_d; + bank_off_q <= bank_off_d; + vld_sel_q <= vld_sel_d ; + cmp_en_q <= cmp_en_d; + end + end + + + +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + +//pragma translate_off +`ifndef VERILATOR + + hit_hot1: assert property ( + @(posedge clk_i) disable iff (~rst_ni) &vld_req |-> ~vld_we |=> $onehot0(rd_hit_oh_o)) + else $fatal(1,"[l1 dcache] rd_hit_oh_o signal must be hot1"); + + word_write_hot1: assert property ( + @(posedge clk_i) disable iff (~rst_ni) wr_ack_o |-> $onehot0(wr_req_i)) + else $fatal(1,"[l1 dcache] wr_req_i signal must be hot1"); + + wbuffer_hit_hot1: assert property ( + @(posedge clk_i) disable iff (~rst_ni) &vld_req |-> ~vld_we |=> $onehot0(wbuffer_hit_oh)) + else $fatal(1,"[l1 dcache] wbuffer_hit_oh signal must be hot1"); + + // this is only used for verification! + logic vld_mirror[serpent_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0]; + logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag_mirror[serpent_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0]; + logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] tag_write_duplicate_test; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror + if(~rst_ni) begin + vld_mirror <= '{default:'0}; + tag_mirror <= '{default:'0}; + end else begin + for (int i = 0; i < DCACHE_SET_ASSOC; i++) begin + if(vld_req[i] & vld_we) begin + vld_mirror[vld_addr][i] <= vld_wdata[i]; + tag_mirror[vld_addr][i] <= wr_cl_tag_i; + end + end + end + end + + generate + for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin + assign tag_write_duplicate_test[i] = (tag_mirror[vld_addr][i] == wr_cl_tag_i) & vld_mirror[vld_addr][i] & (|vld_wdata); + end + endgenerate + + tag_write_duplicate: assert property ( + @(posedge clk_i) disable iff (~rst_ni) |vld_req |-> vld_we |-> ~(|tag_write_duplicate_test)) + else $fatal(1,"[l1 dcache] cannot allocate a CL that is already present in the cache"); + + // logic tst; + // always_comb begin : p_test + // tst = tag == 44'h13; + // // for (int k=0; k, ETH Zurich +// Date: 13.09.2018 +// Description: miss controller for serpent dcache. Note that the current assumption +// is that the port with the highest index issues writes instead of reads. + + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module serpent_dcache_missunit #( + parameter logic [DCACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs + parameter int unsigned NumPorts = 3 // number of miss ports + ) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // cache management, signals from/to core + input logic enable_i, // from CSR + input logic flush_i, // flush request, this waits for pending tx (write, read) to finish and will clear the cache + output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic miss_o, // we missed on a ld/st + // local cache management signals + input logic wbuffer_empty_i, + output logic cache_en_o, // local cache enable signal + // AMO interface + input amo_req_t amo_req_i, + output amo_resp_t amo_resp_o, + // miss handling interface (ld, ptw, wbuffer) + input logic [NumPorts-1:0] miss_req_i, + output logic [NumPorts-1:0] miss_ack_o, + input logic [NumPorts-1:0] miss_nc_i, + input logic [NumPorts-1:0] miss_we_i, + input logic [NumPorts-1:0][63:0] miss_wdata_i, + input logic [NumPorts-1:0][63:0] miss_paddr_i, + input logic [NumPorts-1:0][DCACHE_SET_ASSOC-1:0] miss_vld_bits_i, + input logic [NumPorts-1:0][2:0] miss_size_i, + input logic [NumPorts-1:0][DCACHE_ID_WIDTH-1:0] miss_id_i, // used as transaction ID + // signals that the request collided with a pending read + output logic [NumPorts-1:0] miss_replay_o, + // signals response from memory + output logic [NumPorts-1:0] miss_rtrn_vld_o, + output logic [DCACHE_ID_WIDTH-1:0] miss_rtrn_id_o, // only used for writes, set to zero fro reads + // from writebuffer + input logic [DCACHE_MAX_TX-1:0][63:0] tx_paddr_i, // used to check for address collisions with read operations + input logic [DCACHE_MAX_TX-1:0] tx_vld_i, // used to check for address collisions with read operations + // write interface to cache memory + output logic wr_cl_vld_o, // writes a full cacheline + output logic wr_cl_nc_o, // writes a full cacheline + output logic [DCACHE_SET_ASSOC-1:0] wr_cl_we_o, // writes a full cacheline + output logic [DCACHE_TAG_WIDTH-1:0] wr_cl_tag_o, + output logic [DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx_o, + output logic [DCACHE_OFFSET_WIDTH-1:0] wr_cl_off_o, + output logic [DCACHE_LINE_WIDTH-1:0] wr_cl_data_o, + output logic [DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be_o, + output logic [DCACHE_SET_ASSOC-1:0] wr_vld_bits_o, + // memory interface + input logic mem_rtrn_vld_i, + input dcache_rtrn_t mem_rtrn_i, + output logic mem_data_req_o, + input logic mem_data_ack_i, + output dcache_req_t mem_data_o +); + + // controller FSM + typedef enum logic[2:0] {IDLE, DRAIN, AMO, FLUSH, STORE_WAIT, LOAD_WAIT, AMO_WAIT} state_t; + state_t state_d, state_q; + + // MSHR for reads + typedef struct packed { + logic [63:0] paddr ; + logic [2:0] size ; + logic [DCACHE_SET_ASSOC-1:0] vld_bits; + logic [DCACHE_ID_WIDTH-1:0] id ; + logic nc ; + logic [$clog2(DCACHE_SET_ASSOC)-1:0] repl_way; + logic [$clog2(NumPorts)-1:0] miss_port_idx; + } mshr_t; + + mshr_t mshr_d, mshr_q; + logic [$clog2(DCACHE_SET_ASSOC)-1:0] repl_way, inv_way, rnd_way; + logic mshr_vld_d, mshr_vld_q, mshr_vld_q1; + logic mshr_allocate; + logic update_lfsr, all_ways_valid; + + logic enable_d, enable_q; + logic flush_ack_d, flush_ack_q; + logic flush_en, flush_done; + logic mask_reads, lock_reqs; + logic amo_sel, miss_is_write; + logic [63:0] amo_data, tmp_paddr, amo_rtrn_mux; + + logic [$clog2(NumPorts)-1:0] miss_port_idx; + logic [DCACHE_CL_IDX_WIDTH-1:0] cnt_d, cnt_q; + logic [NumPorts-1:0] miss_req_masked_d, miss_req_masked_q; + + logic inv_vld, inv_vld_all, cl_write_en; + logic load_ack, store_ack, amo_ack; + + logic [NumPorts-1:0] mshr_rdrd_collision_d, mshr_rdrd_collision_q; + logic [NumPorts-1:0] mshr_rdrd_collision; + logic tx_rdwr_collision, mshr_rdwr_collision; + +/////////////////////////////////////////////////////// +// input arbitration and general control sigs +/////////////////////////////////////////////////////// + + assign cache_en_o = enable_q; + assign cnt_d = (flush_en) ? cnt_q + 1 : '0; + assign flush_done = (cnt_q == serpent_cache_pkg::DCACHE_NUM_WORDS-1); + + assign miss_req_masked_d = ( lock_reqs ) ? miss_req_masked_q : + ( mask_reads ) ? miss_we_i & miss_req_i : miss_req_i; + assign miss_is_write = miss_we_i[miss_port_idx]; + + // read port arbiter + lzc #( + .WIDTH ( NumPorts ) + ) i_lzc_reqs ( + .in_i ( miss_req_masked_d ), + .cnt_o ( miss_port_idx ), + .empty_o ( ) + ); + + always_comb begin : p_ack + miss_ack_o = '0; + if (~amo_sel) begin + miss_ack_o[miss_port_idx] = mem_data_ack_i & mem_data_req_o; + end + end + +/////////////////////////////////////////////////////// +// MSHR and way replacement logic (only for read ops) +/////////////////////////////////////////////////////// + + // find invalid cache line + lzc #( + .WIDTH ( ariane_pkg::DCACHE_SET_ASSOC ) + ) i_lzc_inv ( + .in_i ( ~miss_vld_bits_i[miss_port_idx] ), + .cnt_o ( inv_way ), + .empty_o ( all_ways_valid ) + ); + + // generate random cacheline index + lfsr_8bit #( + .WIDTH ( ariane_pkg::DCACHE_SET_ASSOC ) + ) i_lfsr_inv ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .en_i ( update_lfsr ), + .refill_way_oh ( ), + .refill_way_bin ( rnd_way ) + ); + + assign repl_way = (all_ways_valid) ? rnd_way : inv_way; + + assign mshr_d.size = (mshr_allocate) ? miss_size_i [miss_port_idx] : mshr_q.size; + assign mshr_d.paddr = (mshr_allocate) ? miss_paddr_i [miss_port_idx] : mshr_q.paddr; + assign mshr_d.vld_bits = (mshr_allocate) ? miss_vld_bits_i[miss_port_idx] : mshr_q.vld_bits; + assign mshr_d.id = (mshr_allocate) ? miss_id_i [miss_port_idx] : mshr_q.id; + assign mshr_d.nc = (mshr_allocate) ? miss_nc_i [miss_port_idx] : mshr_q.nc; + assign mshr_d.repl_way = (mshr_allocate) ? repl_way : mshr_q.repl_way; + assign mshr_d.miss_port_idx = (mshr_allocate) ? miss_port_idx : mshr_q.miss_port_idx; + + // currently we only have one outstanding read TX, hence an incoming load clears the MSHR + assign mshr_vld_d = (mshr_allocate) ? 1'b1 : + (load_ack) ? 1'b0 : + mshr_vld_q; + + assign miss_o = (mshr_allocate) ? ~miss_nc_i[miss_port_idx] : 1'b0; + + + generate + for(genvar k=0; k mshr_q.nc |-> mem_rtrn_vld_i |-> load_ack |-> mem_rtrn_i.nc) + else $fatal(1,"[l1 dcache missunit] NC load response implies NC load response"); + + read_tid : assert property ( + @(posedge clk_i) disable iff (~rst_ni) mshr_vld_q |-> mem_rtrn_vld_i |-> load_ack |-> mem_rtrn_i.tid == mshr_q.id) + else $fatal(1,"[l1 dcache missunit] TID of load response doesn't match"); + + read_ports : assert property ( + @(posedge clk_i) disable iff (~rst_ni) |miss_req_i[NumPorts-2:0] |-> miss_we_i[NumPorts-2:0] == 0) + else $fatal(1,"[l1 dcache missunit] only last port can issue write requests"); + + write_port : assert property ( + @(posedge clk_i) disable iff (~rst_ni) miss_req_i[NumPorts-1] |-> miss_we_i[NumPorts-1]) + else $fatal(1,"[l1 dcache missunit] last port can only issue write requests"); + + initial begin + // assert wrong parameterizations + assert (NumPorts>=2) + else $fatal(1,"[l1 dcache missunit] at least two ports are required (one read port, one write port)"); + end +`endif +//pragma translate_on + +endmodule // serpent_dcache_missunit \ No newline at end of file diff --git a/src/cache_subsystem/serpent_dcache_wbuffer.sv b/src/cache_subsystem/serpent_dcache_wbuffer.sv new file mode 100644 index 0000000000..c7e1d952e7 --- /dev/null +++ b/src/cache_subsystem/serpent_dcache_wbuffer.sv @@ -0,0 +1,550 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 13.09.2018 +// Description: coalescing write buffer for serpent dcache +// +// A couple of notes: +// +// 1) the write buffer behaves as a fully-associative cache, and is therefore coalescing. +// this cache is used by the cache readout logic to forward data to the load unit. +// +// each byte can be in the following states (valid/dirty/txblock): +// +// 0/0/0: invalid -> free entry in the buffer +// 1/1/0: valid and dirty, Byte is hence not part of TX in-flight +// 1/0/1: valid and not dirty, Byte is part of a TX in-flight +// 1/1/1: valid and, part of tx and dirty. this means that the byte has been +// overwritten while in TX and needs to be retransmitted once the write of that byte returns. +// 1/0/0: this would represent a clean state, but is never reached in the wbuffer in the current implementation. +// this is because when a TX returns, and the byte is in state [1/0/1], it is written to cache if needed and +// its state is immediately cleared to 0/x/x. +// +// this state is used to distinguish between bytes that have been written and not +// yet sent to the memory subsystem, and bytes that are part of a transaction. +// +// 2) further, each word in the write buffer has a cache states (checked, hit_oh) +// +// checked == 0: unknown cache state +// checked == 1: cache state has been looked up, valid way is stored in "hit_oh" +// +// cache invalidations/refills affecting a particular word will clear its word state to 0, +// so another lookup has to be done. note that these lookups are triggered as soon as there is +// a valid word with checked == 0 in the write buffer. +// +// 3) returning write ACKs trigger a cache update if the word is present in the cache, and evict that +// word from the write buffer. if the word is not allocated to the cache, it is just evicted from the write buffer. +// if the word cache state is VOID, the pipeline is stalled until it is clear whether that word is in the cache or not. +// +// 4) we handle NC writes using the writebuffer circuitry. upon an NC request, the writebuffer will first be drained. +// then, only the NC word is written into the write buffer and no further write requests are acknowledged until that +// word has been evicted from the write buffer. + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module serpent_dcache_wbuffer #( + parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region + parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000 // end of cached region +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + + input logic cache_en_i, // writes are treated as NC if disabled + output logic empty_o, // asserted if no data is present in write buffer + // core request ports + input dcache_req_i_t req_port_i, + output dcache_req_o_t req_port_o, + // interface to miss handler + input logic miss_ack_i, + output logic [63:0] miss_paddr_o, + output logic miss_req_o, + output logic miss_we_o, // always 1 here + output logic [63:0] miss_wdata_o, + output logic [DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, // unused here (set to 0) + output logic miss_nc_o, // request to I/O space + output logic [2:0] miss_size_o, // + output logic [DCACHE_ID_WIDTH-1:0] miss_id_o, // ID of this transaction (wbuffer uses all IDs from 0 to DCACHE_MAX_TX-1) + // write responses from memory + input logic miss_rtrn_vld_i, + input logic [DCACHE_ID_WIDTH-1:0] miss_rtrn_id_i, // transaction ID to clear + // cache read interface + output logic [DCACHE_TAG_WIDTH-1:0] rd_tag_o, // tag in - comes one cycle later + output logic [DCACHE_CL_IDX_WIDTH-1:0] rd_idx_o, + output logic [DCACHE_OFFSET_WIDTH-1:0] rd_off_o, + output logic rd_req_o, // read the word at offset off_i[:3] in all ways + output logic rd_tag_only_o, // set to 1 here as we do not have to read the data arrays + input logic rd_ack_i, + input logic [63:0] rd_data_i, // unused + input logic [DCACHE_SET_ASSOC-1:0] rd_vld_bits_i, // unused + input logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh_i, + // cacheline writes + input logic wr_cl_vld_i, + input logic [DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx_i, + // cache word write interface + output logic [DCACHE_SET_ASSOC-1:0] wr_req_o, + input logic wr_ack_i, + output logic [DCACHE_CL_IDX_WIDTH-1:0] wr_idx_o, + output logic [DCACHE_OFFSET_WIDTH-1:0] wr_off_o, + output logic [63:0] wr_data_o, + output logic [7:0] wr_data_be_o, + // to forwarding logic and miss unit + output wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_data_o, + output logic [DCACHE_MAX_TX-1:0][63:0] tx_paddr_o, // used to check for address collisions with read operations + output logic [DCACHE_MAX_TX-1:0] tx_vld_o +); + +tx_stat_t [DCACHE_MAX_TX-1:0] tx_stat_d, tx_stat_q; +wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_d, wbuffer_q; +logic [DCACHE_WBUF_DEPTH-1:0] valid; +logic [DCACHE_WBUF_DEPTH-1:0] dirty; +logic [DCACHE_WBUF_DEPTH-1:0] tocheck; +logic [DCACHE_WBUF_DEPTH-1:0] wbuffer_hit_oh, inval_hit; +logic [DCACHE_WBUF_DEPTH-1:0][7:0] bdirty; + +logic [$clog2(DCACHE_WBUF_DEPTH)-1:0] next_ptr, dirty_ptr, hit_ptr, wr_ptr, check_ptr_d, check_ptr_q, check_ptr_q1, rtrn_ptr; +logic [DCACHE_ID_WIDTH-1:0] tx_id, rtrn_id; + +logic [2:0] bdirty_off; +logic [7:0] tx_be; +logic [63:0] wr_paddr, rd_paddr; +logic [DCACHE_TAG_WIDTH-1:0] rd_tag_d, rd_tag_q; +logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh_d, rd_hit_oh_q; +logic check_en_d, check_en_q, check_en_q1; +logic full, dirty_rd_en, rdy; +logic rtrn_empty, evict; +logic nc_pending_d, nc_pending_q, addr_is_nc; +logic wbuffer_wren; +logic free_tx_slots; + +logic wr_cl_vld_q, wr_cl_vld_d; +logic [DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx_q, wr_cl_idx_d; + +logic [63:0] debug_paddr [DCACHE_WBUF_DEPTH-1:0]; + +/////////////////////////////////////////////////////// +// misc +/////////////////////////////////////////////////////// + +assign miss_nc_o = nc_pending_q; + +assign addr_is_nc = (req_port_i.address_tag < (CachedAddrBeg>>DCACHE_INDEX_WIDTH)) || + (req_port_i.address_tag >= (CachedAddrEnd>>DCACHE_INDEX_WIDTH)) || + (!cache_en_i); + +assign miss_we_o = 1'b1; +assign miss_vld_bits_o = '0; +assign wbuffer_data_o = wbuffer_q; + +generate + for(genvar k=0; k TX0: 0000_0001, TX1: 0000_1000, TX2: 0011_0000 +assign miss_size_o = toSize64(bdirty[dirty_ptr]); + +// replicate transfers shorter than a dword +assign miss_wdata_o = repData64(wbuffer_q[dirty_ptr].data, + bdirty_off, + miss_size_o[1:0]); + +assign tx_be = toByteEnable8(bdirty_off, + miss_size_o[1:0]); + +/////////////////////////////////////////////////////// +// TX status registers and ID counters +/////////////////////////////////////////////////////// + +// TODO: todo: make this fall through if timing permits it +fifo_v2 #( + .FALL_THROUGH ( 1'b0 ), + .DATA_WIDTH ( $clog2(DCACHE_MAX_TX) ), + .DEPTH ( DCACHE_MAX_TX ) +) i_rtrn_id_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( ), + .empty_o ( rtrn_empty ), + .alm_full_o ( ), + .alm_empty_o( ), + .data_i ( miss_rtrn_id_i ), + .push_i ( miss_rtrn_vld_i ), + .data_o ( rtrn_id ), + .pop_i ( evict ) +); + +always_comb begin : p_tx_stat + tx_stat_d = tx_stat_q; + evict = 1'b0; + wr_req_o = '0; + + // clear entry if it is clear whether it can be pushed to the cache or not + if((~rtrn_empty) && wbuffer_q[rtrn_ptr].checked) begin + // check if data is clean and can be written, otherwise skip + // check if CL is present, otherwise skip + if((|wr_data_be_o) && (|wbuffer_q[rtrn_ptr].hit_oh)) begin + wr_req_o = wbuffer_q[rtrn_ptr].hit_oh; + if(wr_ack_i) begin + evict = 1'b1; + tx_stat_d[rtrn_id].vld = 1'b0; + end + end else begin + evict = 1'b1; + tx_stat_d[rtrn_id].vld = 1'b0; + end + end + + // allocate a new entry + if(dirty_rd_en) begin + tx_stat_d[tx_id].vld = 1'b1; + tx_stat_d[tx_id].ptr = dirty_ptr; + tx_stat_d[tx_id].be = tx_be; + end +end + +assign free_tx_slots = |(~tx_vld_o); + +// get free TX slot +rrarbiter #( + .NUM_REQ ( DCACHE_MAX_TX ), + .LOCK_IN ( 1 )// lock the decision, once request is asserted +) i_tx_id_rr ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .en_i ( dirty_rd_en ), + .req_i ( ~tx_vld_o ), + .ack_o ( ), + .vld_o ( ), + .idx_o ( tx_id ) +); + +/////////////////////////////////////////////////////// +// cache readout & update +/////////////////////////////////////////////////////// + +assign rd_tag_d = rd_paddr>>DCACHE_INDEX_WIDTH; + +// trigger TAG readout in cache +assign rd_tag_only_o = 1'b1; +assign rd_paddr = wbuffer_q[check_ptr_d].wtag<<3; +assign rd_req_o = |tocheck; +assign rd_tag_o = rd_tag_q;//delay by one cycle +assign rd_idx_o = rd_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH]; +assign rd_off_o = rd_paddr[DCACHE_OFFSET_WIDTH-1:0]; +assign check_en_d = rd_req_o & rd_ack_i; + +// cache update port +assign rtrn_ptr = tx_stat_q[rtrn_id].ptr; +// if we wrote into a word while it was in-flight, we cannot write the dirty bytes to the cache +// when the TX returns +assign wr_data_be_o = tx_stat_q[rtrn_id].be & (~wbuffer_q[rtrn_ptr].dirty); +assign wr_paddr = wbuffer_q[rtrn_ptr].wtag<<3; +assign wr_idx_o = wr_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH]; +assign wr_off_o = wr_paddr[DCACHE_OFFSET_WIDTH-1:0]; +assign wr_data_o = wbuffer_q[rtrn_ptr].data; + + +/////////////////////////////////////////////////////// +// readout of status bits, index calculation +/////////////////////////////////////////////////////// + +assign wr_cl_vld_d = wr_cl_vld_i; +assign wr_cl_idx_d = wr_cl_idx_i; + +generate + for(genvar k=0; k, ETH Zurich +// Date: 15.08.2018 +// Description: Instruction cache that is compatible with openpiton. +// +// Some notes: +// +// 1) refills always have the size of one cache line, except for accesses to the I/O region, which is mapped +// to the top half of the physical address space (bit 39 = 1). the data width of the interface has the width +// of one cache line, and hence the ifills can be transferred in a single cycle. note that the ifills must be +// consumed unconditionally. +// +// 2) instruction fetches are always assumed to be aligned to 32bit (lower 2 bits are ignored) +// +// 3) NC accesses to I/O space are expected to return 32bit from memory. +// + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module serpent_icache #( + parameter logic [DCACHE_ID_WIDTH-1:0] RdTxId = 0, // ID to be used for read transactions + parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter + parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region + parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000 // end of cached region +) ( + input logic clk_i, + input logic rst_ni, + + input logic flush_i, // flush the icache, flush and kill have to be asserted together + input logic en_i, // enable icache + output logic miss_o, // to performance counter + // address translation requests + input icache_areq_i_t areq_i, + output icache_areq_o_t areq_o, + // data requests + input icache_dreq_i_t dreq_i, + output icache_dreq_o_t dreq_o, + // refill port + input logic mem_rtrn_vld_i, + input icache_rtrn_t mem_rtrn_i, + output logic mem_data_req_o, + input logic mem_data_ack_i, + output icache_req_t mem_data_o +); + + // signals + logic cache_en_d, cache_en_q; // cache is enabled + logic [63:0] vaddr_d, vaddr_q; + logic paddr_is_nc; // asserted if physical address is non-cacheable + logic [ICACHE_SET_ASSOC-1:0] cl_hit; // hit from tag compare + logic cache_rden; // triggers cache lookup + logic cache_wren; // triggers write to cacheline + logic cmp_en_d, cmp_en_q; // enable tag comparison in next cycle. used to cut long path due to NC signal. + logic flush_d, flush_q; // used to register and signal pending flushes + + // replacement strategy + logic update_lfsr; // shift the LFSR + logic [$clog2(ICACHE_SET_ASSOC)-1:0] inv_way; // first non-valid encountered + logic [$clog2(ICACHE_SET_ASSOC)-1:0] rnd_way; // random index for replacement + logic [$clog2(ICACHE_SET_ASSOC)-1:0] repl_way; // way to replace + logic [ICACHE_SET_ASSOC-1:0] repl_way_oh_d, repl_way_oh_q; // way to replace (onehot) + logic all_ways_valid; // we need to switch repl strategy since all are valid + + // invalidations / flushing + logic inv_en; // incoming invalidations + logic flush_en, flush_done; // used to flush cache entries + logic [ICACHE_CL_IDX_WIDTH-1:0] flush_cnt_d, flush_cnt_q; // used to flush cache entries + + // mem arrays + logic cl_we; // write enable to memory array + logic [ICACHE_SET_ASSOC-1:0] cl_req; // request to memory array + logic [ICACHE_CL_IDX_WIDTH-1:0] cl_index; // this is a cache-line index, to memory array + logic [ICACHE_OFFSET_WIDTH-1:0] cl_offset_d, cl_offset_q; // offset in cache line + logic [ICACHE_TAG_WIDTH-1:0] cl_tag_d, cl_tag_q; // this is the cache tag + logic [ICACHE_TAG_WIDTH-1:0] cl_tag_rdata [ICACHE_SET_ASSOC-1:0]; // these are the tags coming from the tagmem + logic [ICACHE_LINE_WIDTH-1:0] cl_rdata [ICACHE_SET_ASSOC-1:0]; // these are the cachelines coming from the cache + logic [ICACHE_SET_ASSOC-1:0][FETCH_WIDTH-1:0]cl_sel; // selected word from each cacheline + logic [ICACHE_SET_ASSOC-1:0] vld_req; // bit enable for valid regs + logic vld_we; // valid bits write enable + logic [ICACHE_SET_ASSOC-1:0] vld_wdata; // valid bits to write + logic [ICACHE_SET_ASSOC-1:0] vld_rdata; // valid bits coming from valid regs + logic [ICACHE_CL_IDX_WIDTH-1:0] vld_addr; // valid bit + + // cpmtroller FSM + typedef enum logic[2:0] {FLUSH, IDLE, READ, MISS, TLB_MISS, KILL_ATRANS, KILL_MISS} state_t; + state_t state_d, state_q; + +/////////////////////////////////////////////////////// +// address -> cl_index mapping, interface plumbing +/////////////////////////////////////////////////////// + + // extract tag from physical address, check if NC + assign cl_tag_d = (areq_i.fetch_valid) ? areq_i.fetch_paddr[ICACHE_TAG_WIDTH+ICACHE_INDEX_WIDTH-1:ICACHE_INDEX_WIDTH] : cl_tag_q; + + // noncacheable if request goes to I/O space, or if cache is disabled + assign paddr_is_nc = (cl_tag_d < (CachedAddrBeg>>ICACHE_INDEX_WIDTH)) || + (cl_tag_d >= (CachedAddrEnd>>ICACHE_INDEX_WIDTH)) || + (!cache_en_q); + + // pass exception through + assign dreq_o.ex = areq_i.fetch_exception; + + // latch this in case we have to stall later on + // make sure this is 32bit aligned + assign vaddr_d = (dreq_o.ready & dreq_i.req) ? dreq_i.vaddr : vaddr_q; + assign areq_o.fetch_vaddr = {vaddr_q>>2, 2'b0}; + + // split virtual address into index and offset to address cache arrays + assign cl_index = vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH]; + + generate + if(Axi64BitCompliant)begin + // if we generate a noncacheable access, the word will be at offset 0 or 4 in the cl coming from memory + assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? {dreq_i.vaddr>>2, 2'b0} : + ( paddr_is_nc & mem_data_req_o ) ? cl_offset_q[2]<<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case + cl_offset_q; + // request word address instead of cl address in case of NC access + assign mem_data_o.paddr = (paddr_is_nc) ? {cl_tag_d, vaddr_q[ICACHE_INDEX_WIDTH-1:3], 3'b0} : // align to 32bit + {cl_tag_d, vaddr_q[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH], {ICACHE_OFFSET_WIDTH{1'b0}}}; // align to cl + end + if(!Axi64BitCompliant)begin + // icache fills are either cachelines or 4byte fills, depending on whether they go to the Piton I/O space or not. + // since the piton cache system replicates the data, we can always index the full CL + assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? {dreq_i.vaddr>>2, 2'b0} : + cl_offset_q; + + // request word address instead of cl address in case of NC access + assign mem_data_o.paddr = (paddr_is_nc) ? {cl_tag_d, vaddr_q[ICACHE_INDEX_WIDTH-1:2], 2'b0} : // align to 32bit + {cl_tag_d, vaddr_q[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH], {ICACHE_OFFSET_WIDTH{1'b0}}}; // align to cl + end + endgenerate + + assign mem_data_o.tid = RdTxId; + + assign mem_data_o.nc = paddr_is_nc; + // way that is being replaced + assign mem_data_o.way = repl_way; + assign dreq_o.vaddr = vaddr_q; + +/////////////////////////////////////////////////////// +// main control logic +/////////////////////////////////////////////////////// + + always_comb begin : p_fsm + // default assignment + state_d = state_q; + cache_en_d = cache_en_q & en_i;// disabling the cache is always possible, enable needs to go via flush + flush_en = 1'b0; + cmp_en_d = 1'b0; + cache_rden = 1'b0; + cache_wren = 1'b0; + inv_en = 1'b0; + flush_d = flush_q | flush_i; // register incoming flush + + // interfaces + dreq_o.ready = 1'b0; + areq_o.fetch_req = 1'b0; + dreq_o.valid = 1'b0; + mem_data_req_o = 1'b0; + // performance counter + miss_o = 1'b0; + + // handle invalidations unconditionally + // note: invald are mutually exclusive with + // ifills, since both arrive over the same IF + // however, we need to make sure below that we + // do not trigger a cache readout at the same time... + if (mem_rtrn_vld_i && mem_rtrn_i.rtype == ICACHE_INV_REQ) begin + inv_en = 1'b1; + end + + unique case (state_q) + ////////////////////////////////// + // this clears all valid bits + FLUSH: begin + flush_en = 1'b1; + if (flush_done) begin + state_d = IDLE; + flush_d = 1'b0; + // if the cache was not enabled set this + cache_en_d = en_i; + end + end + ////////////////////////////////// + // wait for an incoming request + IDLE: begin + // only enable tag comparison if cache is enabled + cmp_en_d = cache_en_q; + + // handle pending flushes, or perform cache clear upon enable + if (flush_d | (en_i & ~cache_en_q)) begin + state_d = FLUSH; + // wait for incoming requests + end else begin + // mem requests are for sure invals here + if (~mem_rtrn_vld_i) begin + dreq_o.ready = 1'b1; + // we have a new request + if (dreq_i.req) begin + cache_rden = 1'b1; + state_d = READ; + end + end + if (dreq_i.kill_s1) begin + state_d = IDLE; + end + end + end + ////////////////////////////////// + // check whether we have a hit + // in case the cache is disabled, + // or in case the address is NC, we + // reuse the miss mechanism to handle + // the request + READ: begin + state_d = TLB_MISS; + areq_o.fetch_req = '1; + // only enable tag comparison if cache is enabled + cmp_en_d = cache_en_q; + // readout speculatively + cache_rden = cache_en_q; + + if (areq_i.fetch_valid) begin + // check if we have to flush + if (flush_d) begin + state_d = IDLE; + // we have a hit or an exception output valid result + end else if ((|cl_hit & cache_en_q) | areq_i.fetch_exception.valid) begin + dreq_o.valid = ~dreq_i.kill_s2;// just don't output in this case + state_d = IDLE; + + // we can accept another request + // and stay here, but only if no inval is coming in + // note: we are not expecting ifill return packets here... + if (~mem_rtrn_vld_i) begin + dreq_o.ready = 1'b1; + if (dreq_i.req) begin + state_d = READ; + end + end + // if a request is being killed at this stage, + // we have to bail out and wait for the address translation to complete + if (dreq_i.kill_s1) begin + state_d = IDLE; + end + // we have a miss / NC transaction + end else if (dreq_i.kill_s2) begin + state_d = IDLE; + end else begin + cmp_en_d = 1'b0; + // only count this as a miss if the cache is enabled, and + // the address is cacheable + // send out ifill request + mem_data_req_o = 1'b1; + if (mem_data_ack_i) begin + miss_o = (~paddr_is_nc); + state_d = MISS; + end + end + // bail out if this request is being killed (and we missed on the TLB) + end else if (dreq_i.kill_s2 | flush_d) begin + state_d = KILL_ATRANS; + end + end + ////////////////////////////////// + // wait until the memory transaction + // returns. do not write to memory + // if the nc bit is set. + TLB_MISS: begin + areq_o.fetch_req = '1; + // only enable tag comparison if cache is enabled + cmp_en_d = cache_en_q; + // readout speculatively + cache_rden = cache_en_q; + + if (areq_i.fetch_valid) begin + // check if we have to kill this request + if (dreq_i.kill_s2 | flush_d) begin + state_d = IDLE; + // check whether we got an exception + end else if (areq_i.fetch_exception.valid) begin + dreq_o.valid = 1'b1; + state_d = IDLE; + // re-trigger cache readout for tag comparison and cache line selection + // but if we got an invalidation, we have to wait another cycle + end else if (~mem_rtrn_vld_i) begin + state_d = READ; + end + // bail out if this request is being killed + end else if (dreq_i.kill_s2 | flush_d) begin + state_d = KILL_ATRANS; + end + end + ////////////////////////////////// + // wait until the memory transaction + // returns. do not write to memory + // if the nc bit is set. + MISS: begin + // note: this is mutually exclusive with ICACHE_INV_REQ, + // so we do not have to check for invals here + if (mem_rtrn_vld_i && mem_rtrn_i.rtype == ICACHE_IFILL_ACK) begin + state_d = IDLE; + // only return data if request is not being killed + if (~(dreq_i.kill_s2 | flush_d)) begin + dreq_o.valid = 1'b1; + // only write to cache if this address is cacheable + cache_wren = ~paddr_is_nc; + end + // bail out if this request is being killed + end else if (dreq_i.kill_s2 | flush_d) begin + state_d = KILL_MISS; + end + end + ////////////////////////////////// + // killed address translation, + // wait until paddr is valid, and go + // back to idle + KILL_ATRANS: begin + areq_o.fetch_req = '1; + if (areq_i.fetch_valid) begin + state_d = IDLE; + end + end + ////////////////////////////////// + // killed miss, + // wait until memory responds and + // go back to idle + KILL_MISS: begin + if (mem_rtrn_vld_i && mem_rtrn_i.rtype == ICACHE_IFILL_ACK) begin + state_d = IDLE; + end + end + default: begin + // we should never get here + state_d = FLUSH; + end + endcase // state_q + end + +/////////////////////////////////////////////////////// +// valid bit invalidation and replacement strategy +/////////////////////////////////////////////////////// + + // note: it cannot happen that we get an invalidation + a cl replacement + // in the same cycle as these requests arrive via the same interface + // flushes take precedence over invalidations (it is ok if we ignore + // the inval since the cache is cleared anyway) + + assign flush_cnt_d = (flush_done) ? '0 : + (flush_en) ? flush_cnt_q + 1 : + flush_cnt_q; + + assign flush_done = (flush_cnt_q==(ICACHE_NUM_WORDS-1)); + + // invalidation/clearing address + // flushing takes precedence over invals + assign vld_addr = (flush_en) ? flush_cnt_q : + (inv_en) ? mem_rtrn_i.inv.idx[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH] : + cl_index; + + assign vld_req = (flush_en | cache_rden) ? '1 : + (mem_rtrn_i.inv.all & inv_en) ? '1 : + (mem_rtrn_i.inv.vld & inv_en) ? icache_way_bin2oh(mem_rtrn_i.inv.way) : + repl_way_oh_q; + + assign vld_wdata = (cache_wren) ? '1 : '0; + + assign vld_we = (cache_wren | inv_en | flush_en); + // assign vld_req = (vld_we | cache_rden); + + + // chose random replacement if all are valid + assign update_lfsr = cache_wren & all_ways_valid; + assign repl_way = (all_ways_valid) ? rnd_way : inv_way; + assign repl_way_oh_d = (cmp_en_q) ? icache_way_bin2oh(repl_way) : repl_way_oh_q; + + // enable signals for memory arrays + assign cl_req = (cache_rden) ? '1 : + (cache_wren) ? repl_way_oh_q : + '0; + assign cl_we = cache_wren; + + + // find invalid cache line + lzc #( + .WIDTH ( ICACHE_SET_ASSOC ) + ) i_lzc ( + .in_i ( ~vld_rdata ), + .cnt_o ( inv_way ), + .empty_o ( all_ways_valid ) + ); + + // generate random cacheline index + lfsr_8bit #( + .WIDTH (ICACHE_SET_ASSOC) + ) i_lfsr ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .en_i ( update_lfsr ), + .refill_way_oh ( ), + .refill_way_bin ( rnd_way ) + ); + + +/////////////////////////////////////////////////////// +// tag comparison, hit generation +/////////////////////////////////////////////////////// + + logic [$clog2(ICACHE_SET_ASSOC)-1:0] hit_idx; + + generate + for (genvar i=0;i mem_rtrn_vld_i |-> state_q != KILL_MISS |-> mem_rtrn_i.rtype == ICACHE_IFILL_ACK |-> mem_rtrn_i.nc) + else $fatal(1,"[l1 icache] NC paddr implies nc ifill"); + + noncacheable1: assert property ( + @(posedge clk_i) disable iff (~rst_ni) mem_rtrn_vld_i |-> state_q != KILL_MISS |-> mem_rtrn_i.f4b |-> mem_rtrn_i.nc) + else $fatal(1,"[l1 icache] 4b ifill implies NC"); + + repl_inval0: assert property ( + @(posedge clk_i) disable iff (~rst_ni) cache_wren |-> ~(mem_rtrn_i.inv.all | mem_rtrn_i.inv.vld)) + else $fatal(1,"[l1 icache] cannot replace cacheline and invalidate cacheline simultaneously"); + + repl_inval1: assert property ( + @(posedge clk_i) disable iff (~rst_ni) (mem_rtrn_i.inv.all | mem_rtrn_i.inv.vld) |-> ~cache_wren) + else $fatal(1,"[l1 icache] cannot replace cacheline and invalidate cacheline simultaneously"); + + invalid_state: assert property ( + @(posedge clk_i) disable iff (~rst_ni) (state_q inside {FLUSH, IDLE, READ, MISS, TLB_MISS, KILL_ATRANS, KILL_MISS})) + else $fatal(1,"[l1 icache] fsm reached an invalid state"); + + hot1: assert property ( + @(posedge clk_i) disable iff (~rst_ni) (~inv_en) |=> cmp_en_q |-> $onehot0(cl_hit)) + else $fatal(1,"[l1 icache] cl_hit signal must be hot1"); + + initial begin + // assert wrong parameterizations + assert (ICACHE_INDEX_WIDTH<=12) + else $fatal(1,"[l1 icache] cache index width can be maximum 12bit since VM uses 4kB pages"); + end +`endif +//pragma translate_on + +endmodule // serpent_icache diff --git a/src/cache_subsystem/serpent_l15_adapter.sv b/src/cache_subsystem/serpent_l15_adapter.sv new file mode 100644 index 0000000000..7f8f77c6f9 --- /dev/null +++ b/src/cache_subsystem/serpent_l15_adapter.sv @@ -0,0 +1,406 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 08.08.2018 +// Description: adapter module to connect the L1D$ and L1I$ to the native +// interface of the OpenPiton L1.5 cache. +// +// A couple of notes: +// +// 1) the L15 has been designed for an OpenSparc T1 core with 2 threads and can serve only +// 1 ld and rd request per thread. Ariane has only one hart, but the LSU can issue several write +// requests to optimize bandwidth. hence, we reuse the threadid field to issue and track multiple +// requests (up to 2 in this case). +// +// 2) the CSM (clumped shared memory = coherence domain restriction in OpenPiton) +// feature is currently not supported by Ariane. +// +// 3) some features like blockinitstore, prefetch, ECC errors are not used (see interface below) +// +// 4) the arbiter can store upt to two outgoing requests per cache. incoming responses are passed +// through one streaming register, and need to be consumed unconditionally by the caches. +// +// 5) The L1.5 protocol is closely related to the CPX bus of openSPARC, see also [1,2] +// +// 6) Note on transaction data and size: if a store packet is less than 64 bits, then +// the field is filled with copies of the data. in case of an interrupt vector, +// an 18bit interrupt vector is expected. +// +// 7) L1I$ refill requests always have precedence over L1D$ requests. +// +// 8) L1I$ fill requests are always complete cache lines at the moment +// +// 9) the adapter converts from little endian (Ariane) to big endian (openpiton), and vice versa. +// +// 10) L1I$ requests to I.O space (bit39 of address = 1'b1) always return 32bit nc data +// +// Refs: [1] OpenSPARC T1 Microarchitecture Specification +// https://www.oracle.com/technetwork/systems/opensparc/t1-01-opensparct1-micro-arch-1538959.html +// [2] OpenPiton Microarchitecture Specification +// https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf +// + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module serpent_l15_adapter #( + parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region + parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region + parameter bit SwapEndianess = 1 , + parameter bit PitonRemapIO = 1 // for OpenPiton +) ( + input logic clk_i, + input logic rst_ni, + + // icache + input logic icache_data_req_i, + output logic icache_data_ack_o, + input icache_req_t icache_data_i, + // returning packets must be consumed immediately + output logic icache_rtrn_vld_o, + output icache_rtrn_t icache_rtrn_o, + + + // dcache + input logic dcache_data_req_i, + output logic dcache_data_ack_o, + input dcache_req_t dcache_data_i, + // returning packets must be consumed immediately + output logic dcache_rtrn_vld_o, + output dcache_rtrn_t dcache_rtrn_o, + + // TODO: interrupt interface + + // L15 + output l15_req_t l15_req_o, + input l15_rtrn_t l15_rtrn_i +); + +// request path +icache_req_t icache_data; +logic icache_data_full, icache_data_empty; + +dcache_req_t dcache_data; +logic dcache_data_full, dcache_data_empty; + +logic [1:0] arb_req, arb_ack; +logic arb_idx; + +// return path +logic rtrn_fifo_empty, rtrn_fifo_full, rtrn_fifo_pop; +l15_rtrn_t rtrn_fifo_data; + + +/////////////////////////////////////////////////////// +// request path to L15 +/////////////////////////////////////////////////////// + +// relevant l15 signals +// l15_req_t l15_req_o.l15_rqtype; // see below for encoding +// logic l15_req_o.l15_nc; // non-cacheable bit +// logic [2:0] l15_req_o.l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) +// logic [L15_TID_WIDTH-1:0] l15_req_o.l15_threadid; // currently 0 or 1 +// logic l15_req_o.l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment +// logic [L15_WAY_WIDTH-1:0] l15_req_o.l15_l1rplway; // way to replace +// logic [39:0] l15_req_o.l15_address; // physical address +// logic [63:0] l15_req_o.l15_data; // word to write +// logic [63:0] l15_req_o.l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests) +// logic [L15_TLB_CSM_WIDTH-1:0] l15_req_o.l15_csm_data; + +logic [63:0] tmp_paddr; + +assign icache_data_ack_o = icache_data_req_i & ~icache_data_full; +assign dcache_data_ack_o = dcache_data_req_i & ~dcache_data_full; + +// data mux +assign l15_req_o.l15_nc = (arb_idx) ? dcache_data.nc : icache_data.nc; +// icache fills are either cachelines or 4byte fills, depending on whether they go to the Piton I/O space or not. +assign l15_req_o.l15_size = (arb_idx) ? dcache_data.size : + (icache_data.nc) ? 3'b010 : 3'b111; +assign l15_req_o.l15_threadid = (arb_idx) ? dcache_data.tid : icache_data.tid; +assign l15_req_o.l15_prefetch = '0; // unused in openpiton +assign l15_req_o.l15_invalidate_cacheline = '0; // unused by Ariane as L1 has no ECC at the moment +assign l15_req_o.l15_blockstore = '0; // unused in openpiton +assign l15_req_o.l15_blockinitstore = '0; // unused in openpiton +assign l15_req_o.l15_l1rplway = (arb_idx) ? dcache_data.way : icache_data.way; +// assign tmp_paddr = (arb_idx) ? dcache_data.paddr : +// icache_data.paddr; + +// assign l15_req_o.l15_address = ((tmp_paddr < CachedAddrBeg) && PitonRemapIO) ? {25'b1, tmp_paddr[38:0]} : tmp_paddr; +assign l15_req_o.l15_address = (arb_idx) ? dcache_data.paddr : + icache_data.paddr; + +assign l15_req_o.l15_data_next_entry = '0; // unused in Ariane (only used for CAS atomic requests) +assign l15_req_o.l15_csm_data = '0; // unused in Ariane (only used for coherence domain restriction features) +assign l15_req_o.l15_amo_op = dcache_data.amo_op; + + +// openpiton is big endian +generate + if (SwapEndianess) assign l15_req_o.l15_data = swendian64(dcache_data.data); + else assign l15_req_o.l15_data = dcache_data.data; +endgenerate + +// arbiter +rrarbiter #( + .NUM_REQ(2), + .LOCK_IN(1) +) i_rrarbiter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i( '0 ), + .en_i ( l15_rtrn_i.l15_ack ), + .req_i ( arb_req ), + .ack_o ( arb_ack ), + .vld_o ( ), + .idx_o ( arb_idx ) +); + +assign arb_req = {~dcache_data_empty, ~icache_data_empty}; +assign l15_req_o.l15_val = (|arb_req);// & ~header_ack_q; + +// encode packet type +always_comb begin : p_req + l15_req_o.l15_rqtype = L15_LOAD_RQ; + + unique case (arb_idx) + 0: begin// icache + l15_req_o.l15_rqtype = L15_IMISS_RQ; + end + 1: begin + unique case (dcache_data.rtype) + DCACHE_STORE_REQ: begin + l15_req_o.l15_rqtype = L15_STORE_RQ; + end + DCACHE_LOAD_REQ: begin + l15_req_o.l15_rqtype = L15_LOAD_RQ; + end + DCACHE_ATOMIC_REQ: begin + l15_req_o.l15_rqtype = L15_ATOMIC_RQ; + end + // DCACHE_INT_REQ: begin + // //TODO interrupt requests + // end + default: begin + ; + end + endcase // dcache_data.rtype + end + default: begin + ; + end + endcase +end // p_req + +fifo_v2 #( + .dtype ( icache_req_t ), + .DEPTH ( ADAPTER_REQ_FIFO_DEPTH ) +) i_icache_data_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( icache_data_full ), + .empty_o ( icache_data_empty ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( icache_data_i ), + .push_i ( icache_data_ack_o ), + .data_o ( icache_data ), + .pop_i ( arb_ack[0] ) +); + +fifo_v2 #( + .dtype ( dcache_req_t ), + .DEPTH ( ADAPTER_REQ_FIFO_DEPTH ) +) i_dcache_data_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( dcache_data_full ), + .empty_o ( dcache_data_empty ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( dcache_data_i ), + .push_i ( dcache_data_ack_o ), + .data_o ( dcache_data ), + .pop_i ( arb_ack[1] ) +); + +/////////////////////////////////////////////////////// +// return path from L15 +/////////////////////////////////////////////////////// + +// relevant l15 signals +// l15_rtrn_i.l15_returntype; // see below for encoding +// l15_rtrn_i.l15_noncacheable; // non-cacheable bit +// l15_rtrn_i.l15_atomic; // asserted in load return and store ack pack +// l15_rtrn_i.l15_threadid; // used as transaction ID +// l15_rtrn_i.l15_f4b; // 4byte instruction fill from I/O space (nc). +// l15_rtrn_i.l15_data_0; // used for both caches +// l15_rtrn_i.l15_data_1; // used for both caches +// l15_rtrn_i.l15_data_2; // currently only used for I$ +// l15_rtrn_i.l15_data_3; // currently only used for I$ +// l15_rtrn_i.l15_inval_icache_all_way; // invalidate all ways +// l15_rtrn_i.l15_inval_address_15_4; // invalidate selected cacheline +// l15_rtrn_i.l15_inval_dcache_inval; // invalidate selected cacheline and way +// l15_rtrn_i.l15_inval_way; // way to invalidate + +// acknowledge if we have space to hold this packet +assign l15_req_o.l15_req_ack = l15_rtrn_i.l15_val & ~rtrn_fifo_full; +// packets have to be consumed immediately +assign rtrn_fifo_pop = ~rtrn_fifo_empty; + +// decode packet type +always_comb begin : p_rtrn_logic + icache_rtrn_o.rtype = ICACHE_IFILL_ACK; + dcache_rtrn_o.rtype = DCACHE_LOAD_ACK; + icache_rtrn_vld_o = 1'b0; + dcache_rtrn_vld_o = 1'b0; + if(~rtrn_fifo_empty) begin + unique case (rtrn_fifo_data.l15_returntype) + L15_LOAD_RET: begin + dcache_rtrn_o.rtype = DCACHE_LOAD_ACK; + dcache_rtrn_vld_o = 1'b1; + end + L15_ST_ACK: begin + dcache_rtrn_o.rtype = DCACHE_STORE_ACK; + dcache_rtrn_vld_o = 1'b1; + end + L15_IFILL_RET: begin + icache_rtrn_o.rtype = ICACHE_IFILL_ACK; + icache_rtrn_vld_o = 1'b1; + end + L15_EVICT_REQ: begin + icache_rtrn_o.rtype = ICACHE_INV_REQ; + dcache_rtrn_o.rtype = DCACHE_INV_REQ; + icache_rtrn_vld_o = icache_rtrn_o.inv.vld | icache_rtrn_o.inv.all; + dcache_rtrn_vld_o = dcache_rtrn_o.inv.vld | dcache_rtrn_o.inv.all; + end + L15_CPX_RESTYPE_ATOMIC_RES: begin + dcache_rtrn_o.rtype = DCACHE_ATOMIC_ACK; + dcache_rtrn_vld_o = 1'b1; + end + // L15_INT_RET: begin + // TODO: implement this + // dcache_rtrn_o.reqType = DCACHE_INT_ACK; + // end + default: begin + ; + end + endcase // rtrn_fifo_data.l15_returntype + end +end + +// openpiton is big endian +generate + if (SwapEndianess) begin + assign dcache_rtrn_o.data = { swendian64(rtrn_fifo_data.l15_data_1), + swendian64(rtrn_fifo_data.l15_data_0) }; + + assign icache_rtrn_o.data = { swendian64(rtrn_fifo_data.l15_data_3), + swendian64(rtrn_fifo_data.l15_data_2), + swendian64(rtrn_fifo_data.l15_data_1), + swendian64(rtrn_fifo_data.l15_data_0) }; + end else begin + assign dcache_rtrn_o.data = { rtrn_fifo_data.l15_data_1, + rtrn_fifo_data.l15_data_0 }; + + assign icache_rtrn_o.data = { rtrn_fifo_data.l15_data_3, + rtrn_fifo_data.l15_data_2, + rtrn_fifo_data.l15_data_1, + rtrn_fifo_data.l15_data_0 }; + end +endgenerate + +// fifo signals +assign icache_rtrn_o.tid = rtrn_fifo_data.l15_threadid; +assign icache_rtrn_o.nc = rtrn_fifo_data.l15_noncacheable; +assign icache_rtrn_o.f4b = rtrn_fifo_data.l15_f4b; +assign dcache_rtrn_o.tid = rtrn_fifo_data.l15_threadid; +assign dcache_rtrn_o.nc = rtrn_fifo_data.l15_noncacheable; + +// invalidation signal mapping +assign icache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address_15_4, 4'b0000}; +assign icache_rtrn_o.inv.way = rtrn_fifo_data.l15_inval_way; +assign icache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_icache_inval; +assign icache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_icache_all_way; + +assign dcache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address_15_4, 4'b0000}; +assign dcache_rtrn_o.inv.way = rtrn_fifo_data.l15_inval_way; +assign dcache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_dcache_inval; +assign dcache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_dcache_all_way; + +fifo_v2 #( + .dtype ( l15_rtrn_t ), + .DEPTH ( ADAPTER_RTRN_FIFO_DEPTH ) +) i_rtrn_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( rtrn_fifo_full ), + .empty_o ( rtrn_fifo_empty ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( l15_rtrn_i ), + .push_i ( l15_req_o.l15_req_ack ), + .data_o ( rtrn_fifo_data ), + .pop_i ( rtrn_fifo_pop ) +); + + +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + +//pragma translate_off +`ifndef VERILATOR + + invalidations: assert property ( + @(posedge clk_i) disable iff (~rst_ni) l15_rtrn_i.l15_val |-> l15_rtrn_i.l15_returntype == L15_EVICT_REQ |-> (l15_rtrn_i.l15_inval_icache_inval | + l15_rtrn_i.l15_inval_dcache_inval | + l15_rtrn_i.l15_inval_icache_all_way | + l15_rtrn_i.l15_inval_dcache_all_way)) + else $fatal(1,"[l15_adapter] got invalidation package with zero invalidation flags"); + + blockstore_o: assert property ( + @(posedge clk_i) disable iff (~rst_ni) l15_req_o.l15_val |-> l15_req_o.l15_rqtype == L15_STORE_RQ |-> !(l15_req_o.l15_blockstore || l15_req_o.l15_blockinitstore)) + else $fatal(1,"[l15_adapter] blockstores are not supported (out)"); + + blockstore_i: assert property ( + @(posedge clk_i) disable iff (~rst_ni) l15_rtrn_i.l15_val |-> l15_rtrn_i.l15_returntype inside {L15_ST_ACK, L15_ST_ACK} |-> !l15_rtrn_i.l15_blockinitstore) + else $fatal(1,"[l15_adapter] blockstores are not supported (in)"); + + unsuported_rtrn_types: assert property ( + @(posedge clk_i) disable iff (~rst_ni) (l15_rtrn_i.l15_val |-> l15_rtrn_i.l15_returntype inside {L15_LOAD_RET, L15_ST_ACK, L15_IFILL_RET, L15_EVICT_REQ, L15_CPX_RESTYPE_ATOMIC_RES})) + else $warning("[l15_adapter] return type %X04 is not (yet) supported by l15 adapter.", l15_rtrn_i.l15_returntype); + + amo_type: assert property ( + @(posedge clk_i) disable iff (~rst_ni) (l15_rtrn_i.l15_val |-> l15_rtrn_i.l15_returntype inside {L15_CPX_RESTYPE_ATOMIC_RES} |-> l15_rtrn_i.l15_atomic )) + else $fatal(1,"[l15_adapter] l15_atomic must be asserted when the return type is an ATOMIC_RES"); + + initial begin + // assert wrong parameterizations + assert (L15_SET_ASSOC >= ICACHE_SET_ASSOC) + else $fatal(1,"[l15_adapter] number of icache ways must be smaller or equal the number of L15 ways"); + // assert wrong parameterizations + assert (L15_SET_ASSOC >= DCACHE_SET_ASSOC) + else $fatal(1,"[l15_adapter] number of dcache ways must be smaller or equal the number of L15 ways"); + // invalidation address returned by L1.5 is 16 bit + assert (16 >= DCACHE_INDEX_WIDTH && 16 >= ICACHE_INDEX_WIDTH) + else $fatal(1,"[l15_adapter] maximum number of index bits supported by L1.5 is 16"); + end +`endif +//pragma translate_on + +endmodule // serpent_l15_adapter \ No newline at end of file diff --git a/src/cache_subsystem/std_cache_subsystem.sv b/src/cache_subsystem/std_cache_subsystem.sv index e3cfeb6fa0..181387889b 100644 --- a/src/cache_subsystem/std_cache_subsystem.sv +++ b/src/cache_subsystem/std_cache_subsystem.sv @@ -1,16 +1,12 @@ -// Copyright (c) 2018 ETH Zurich, University of Bologna -// All rights reserved. -// -// This code is under development and not yet released to the public. -// Until it is released, the code is under the copyright of ETH Zurich and -// the University of Bologna, and may contain confidential and/or unpublished -// work. Any reuse/redistribution is strictly forbidden without written -// permission from ETH Zurich. -// -// Bug fixes and contributions will eventually be released under the -// SolderPad open hardware license in the context of the PULP platform -// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the -// University of Bologna. +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. // // Author: Florian Zaruba , ETH Zurich // Michael Schaffner , ETH Zurich @@ -22,10 +18,11 @@ import ariane_pkg::*; import std_cache_pkg::*; module std_cache_subsystem #( - parameter logic [63:0] CACHE_START_ADDR = 64'h4000_0000 -)( + parameter logic [63:0] CACHE_START_ADDR = 64'h4000_0000 +) ( input logic clk_i, input logic rst_ni, + input riscv::priv_lvl_t priv_lvl_i, // I$ input logic icache_en_i, // enable icache (or bypass e.g: in debug mode) input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together @@ -45,28 +42,38 @@ module std_cache_subsystem #( input logic dcache_flush_i, // high until acknowledged output logic dcache_flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed output logic dcache_miss_o, // we missed on a ld/st + output logic wbuffer_empty_o, // statically set to 1, as there is no wbuffer in this cache system // Request ports input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU // memory side - AXI_BUS.Master icache_data_if, // I$ refill port - AXI_BUS.Master dcache_data_if, // D$ refill port - AXI_BUS.Master dcache_bypass_if // bypass axi port (disabled D$ or uncacheable access) + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i ); - std_icache #( - ) i_icache ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( icache_flush_i ), - .en_i ( icache_en_i ), - .miss_o ( icache_miss_o ), - .areq_i ( icache_areq_i ), - .areq_o ( icache_areq_o ), - .dreq_i ( icache_dreq_i ), - .dreq_o ( icache_dreq_o ), - .axi ( icache_data_if ) - ); + assign wbuffer_empty_o = 1'b1; + + ariane_axi::req_t axi_req_icache; + ariane_axi::resp_t axi_resp_icache; + ariane_axi::req_t axi_req_bypass; + ariane_axi::resp_t axi_resp_bypass; + ariane_axi::req_t axi_req_data; + ariane_axi::resp_t axi_resp_data; + + std_icache i_icache ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .priv_lvl_i ( priv_lvl_i ), + .flush_i ( icache_flush_i ), + .en_i ( icache_en_i ), + .miss_o ( icache_miss_o ), + .areq_i ( icache_areq_i ), + .areq_o ( icache_areq_o ), + .dreq_i ( icache_dreq_i ), + .dreq_o ( icache_dreq_o ), + .axi_req_o ( axi_req_icache ), + .axi_resp_i ( axi_resp_icache ) + ); // decreasing priority // Port 0: PTW @@ -75,18 +82,193 @@ module std_cache_subsystem #( std_nbdcache #( .CACHE_START_ADDR ( CACHE_START_ADDR ) ) i_nbdcache ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), + .clk_i, + .rst_ni, .enable_i ( dcache_enable_i ), .flush_i ( dcache_flush_i ), .flush_ack_o ( dcache_flush_ack_o ), .miss_o ( dcache_miss_o ), - .data_if ( dcache_data_if ), - .bypass_if ( dcache_bypass_if ), + .axi_bypass_o ( axi_req_bypass ), + .axi_bypass_i ( axi_resp_bypass ), + .axi_data_o ( axi_req_data ), + .axi_data_i ( axi_resp_data ), .req_ports_i ( dcache_req_ports_i ), .req_ports_o ( dcache_req_ports_o ), - .amo_req_i ( amo_req_i ), - .amo_resp_o ( amo_resp_o ) + .amo_req_i, + .amo_resp_o ); + // ----------------------- + // Arbitrate AXI Ports + // ----------------------- + logic [1:0] w_select, w_select_fifo, w_select_arbiter; + logic w_fifo_empty; + + + // AR Channel + stream_arbiter #( + .DATA_T ( ariane_axi::ar_chan_t ), + .N_INP ( 3 ) + ) i_stream_arbiter_ar ( + .clk_i, + .rst_ni, + .inp_data_i ( {axi_req_icache.ar, axi_req_bypass.ar, axi_req_data.ar} ), + .inp_valid_i ( {axi_req_icache.ar_valid, axi_req_bypass.ar_valid, axi_req_data.ar_valid} ), + .inp_ready_o ( {axi_resp_icache.ar_ready, axi_resp_bypass.ar_ready, axi_resp_data.ar_ready} ), + .oup_data_o ( axi_req_o.ar ), + .oup_valid_o ( axi_req_o.ar_valid ), + .oup_ready_i ( axi_resp_i.ar_ready ) + ); + + // AW Channel + stream_arbiter #( + .DATA_T ( ariane_axi::aw_chan_t ), + .N_INP ( 3 ) + ) i_stream_arbiter_aw ( + .clk_i, + .rst_ni, + .inp_data_i ( {axi_req_icache.aw, axi_req_bypass.aw, axi_req_data.aw} ), + .inp_valid_i ( {axi_req_icache.aw_valid, axi_req_bypass.aw_valid, axi_req_data.aw_valid} ), + .inp_ready_o ( {axi_resp_icache.aw_ready, axi_resp_bypass.aw_ready, axi_resp_data.aw_ready} ), + .oup_data_o ( axi_req_o.aw ), + .oup_valid_o ( axi_req_o.aw_valid ), + .oup_ready_i ( axi_resp_i.aw_ready ) + ); + + // WID has been removed in AXI 4 so we need to keep track which AW request has been accepted + // to forward the correct write data. + always_comb begin + w_select = 0; + unique case (axi_req_o.aw.id) + 4'b1100: w_select = 2; // dcache + 4'b1000, 4'b1001, 4'b1010, 4'b1011: w_select = 1; // bypass + default: w_select = 0; // icache + endcase + end + + // TODO(zarubaf): This causes a cycle delay, might be optimize-able, FALL_THROUGH + // option made problems during synthesis (timing loop) + fifo_v3 #( + .DATA_WIDTH ( 2 ), + // we can have a maximum of 4 oustanding transactions as each port is blocking + .DEPTH ( 4 ) + ) i_fifo_w_channel ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( ), // leave open + .empty_o ( w_fifo_empty ), + .usage_o ( ), // leave open + .data_i ( w_select ), + // a new transaction was requested and granted + .push_i ( axi_req_o.aw_valid & axi_resp_i.aw_ready ), + // write ID to select the output MUX + .data_o ( w_select_fifo ), + // transaction has finished + .pop_i ( axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last ) + ); + + // icache will never write so select it as default (e.g.: when no arbitration is active) + // this is equal to setting it to zero + assign w_select_arbiter = (w_fifo_empty) ? 0 : w_select_fifo; + + stream_mux #( + .DATA_T ( ariane_axi::w_chan_t ), + .N_INP ( 3 ) + ) i_stream_mux_w ( + .inp_data_i ( {axi_req_data.w, axi_req_bypass.w, axi_req_icache.w} ), + .inp_valid_i ( {axi_req_data.w_valid, axi_req_bypass.w_valid, axi_req_icache.w_valid} ), + .inp_ready_o ( {axi_resp_data.w_ready, axi_resp_bypass.w_ready, axi_resp_icache.w_ready} ), + .inp_sel_i ( w_select_arbiter ), + .oup_data_o ( axi_req_o.w ), + .oup_valid_o ( axi_req_o.w_valid ), + .oup_ready_i ( axi_resp_i.w_ready ) + ); + + // Route responses based on ID + // 0000 -> I$ + // 10[00|10|01|11] -> Bypass + // 1100 -> D$ + // R Channel + assign axi_resp_icache.r = axi_resp_i.r; + assign axi_resp_bypass.r = axi_resp_i.r; + assign axi_resp_data.r = axi_resp_i.r; + + logic [1:0] r_select; + + always_comb begin + r_select = 0; + unique case (axi_resp_i.r.id) + 4'b1100: r_select = 0; // dcache + 4'b1000, 4'b1001, 4'b1010, 4'b1011: r_select = 1; // bypass + 4'b0000: r_select = 2; // icache + default: r_select = 0; + endcase + end + + stream_demux #( + .N_OUP ( 3 ) + ) i_stream_demux_r ( + .inp_valid_i ( axi_resp_i.r_valid ), + .inp_ready_o ( axi_req_o.r_ready ), + .oup_sel_i ( r_select ), + .oup_valid_o ( {axi_resp_icache.r_valid, axi_resp_bypass.r_valid, axi_resp_data.r_valid} ), + .oup_ready_i ( {axi_req_icache.r_ready, axi_req_bypass.r_ready, axi_req_data.r_ready} ) + ); + + // B Channel + logic [1:0] b_select; + + assign axi_resp_icache.b = axi_resp_i.b; + assign axi_resp_bypass.b = axi_resp_i.b; + assign axi_resp_data.b = axi_resp_i.b; + + always_comb begin + b_select = 0; + unique case (axi_resp_i.b.id) + 4'b1100: b_select = 0; // dcache + 4'b1000, 4'b1001, 4'b1010, 4'b1011: b_select = 1; // bypass + 4'b0000: b_select = 2; // icache + default: b_select = 0; + endcase + end + + stream_demux #( + .N_OUP ( 3 ) + ) i_stream_demux_b ( + .inp_valid_i ( axi_resp_i.b_valid ), + .inp_ready_o ( axi_req_o.b_ready ), + .oup_sel_i ( b_select ), + .oup_valid_o ( {axi_resp_icache.b_valid, axi_resp_bypass.b_valid, axi_resp_data.b_valid} ), + .oup_ready_i ( {axi_req_icache.b_ready, axi_req_bypass.b_ready, axi_req_data.b_ready} ) + ); + +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + +//pragma translate_off +`ifndef VERILATOR + + a_invalid_instruction_fetch: assert property ( + @(posedge clk_i) disable iff (~rst_ni) icache_dreq_o.valid |-> (|icache_dreq_o.data) !== 1'hX) + else $warning(1,"[l1 dcache] reading invalid instructions: vaddr=%08X, data=%08X", + icache_dreq_o.vaddr, icache_dreq_o.data); + + a_invalid_write_data: assert property ( + @(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX) + else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X", + {dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata); + generate + for(genvar j=0; j<2; j++) begin + a_invalid_read_data: assert property ( + @(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX) + else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X", + j, dcache_req_ports_o[j].data_rdata); + end + endgenerate + +`endif +//pragma translate_on endmodule // std_cache_subsystem diff --git a/src/cache_subsystem/std_icache.sv b/src/cache_subsystem/std_icache.sv index 5fbb295b57..5cc6ad1f11 100644 --- a/src/cache_subsystem/std_icache.sv +++ b/src/cache_subsystem/std_icache.sv @@ -16,10 +16,10 @@ import ariane_pkg::*; import std_cache_pkg::*; -module std_icache #( -)( +module std_icache ( input logic clk_i, input logic rst_ni, + input riscv::priv_lvl_t priv_lvl_i, input logic flush_i, // flush the icache, flush and kill have to be asserted together input logic en_i, // enable icache @@ -30,8 +30,9 @@ module std_icache #( // data requests input icache_dreq_i_t dreq_i, output icache_dreq_o_t dreq_o, - // refill port - AXI_BUS.Master axi + // AXI refill port + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i ); localparam int unsigned ICACHE_BYTE_OFFSET = $clog2(ICACHE_LINE_WIDTH/8); // 3 @@ -120,9 +121,9 @@ module std_icache #( assign idx = vaddr_q[ICACHE_BYTE_OFFSET-1:2]; generate - for (genvar i=0;i instruction fetch, LSB -> privileged access or not + assign axi_req_o.ar.prot = {1'b1, 1'b0, (priv_lvl_i == riscv::PRIV_LVL_M)}; + assign axi_req_o.ar.region = '0; + assign axi_req_o.ar.len = (2**NR_AXI_REFILLS) - 1; + assign axi_req_o.ar.size = 3'b011; + assign axi_req_o.ar.burst = 2'b01; + assign axi_req_o.ar.lock = '0; + assign axi_req_o.ar.cache = '0; + assign axi_req_o.ar.qos = '0; + assign axi_req_o.ar.id = '0; + + assign axi_req_o.r_ready = 1'b1; assign data_be = be; assign data_wdata = wdata; @@ -178,7 +177,6 @@ module std_icache #( assign addr = (state_q==FLUSH) ? cnt_q : vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_BYTE_OFFSET]; - // ------------------ // Cache Ctrl // ------------------ @@ -208,8 +206,8 @@ module std_icache #( update_lfsr = 1'b0; miss_o = 1'b0; - axi.ar_valid = 1'b0; - axi.ar_addr = '0; + axi_req_o.ar_valid = 1'b0; + axi_req_o.ar.addr = '0; areq_o.fetch_req = 1'b0; areq_o.fetch_vaddr = vaddr_q; @@ -319,15 +317,15 @@ module std_icache #( end // ~> request a cache-line refill REFILL, WAIT_KILLED_REFILL: begin - axi.ar_valid = 1'b1; - axi.ar_addr[ICACHE_INDEX_WIDTH+ICACHE_TAG_WIDTH-1:0] = {tag_q, vaddr_q[ICACHE_INDEX_WIDTH-1:ICACHE_BYTE_OFFSET], {ICACHE_BYTE_OFFSET{1'b0}}}; + axi_req_o.ar_valid = 1'b1; + axi_req_o.ar.addr[ICACHE_INDEX_WIDTH+ICACHE_TAG_WIDTH-1:0] = {tag_q, vaddr_q[ICACHE_INDEX_WIDTH-1:ICACHE_BYTE_OFFSET], {ICACHE_BYTE_OFFSET{1'b0}}}; burst_cnt_d = '0; if (dreq_i.kill_s2) state_d = WAIT_KILLED_REFILL; // we need to finish this AXI transfer - if (axi.ar_ready) + if (axi_resp_i.ar_ready) state_d = (dreq_i.kill_s2 || (state_q == WAIT_KILLED_REFILL)) ? WAIT_KILLED_AXI_R_RESP : WAIT_AXI_R_RESP; end // ~> wait for the read response @@ -336,11 +334,11 @@ module std_icache #( req = evict_way_q; vld_req = evict_way_q; - if (axi.r_valid) begin + if (axi_resp_i.r_valid) begin we = 1'b1; tag_wdata.tag = tag_q; tag_wdata.valid = 1'b1; - wdata[burst_cnt_q] = axi.r_data; + wdata[burst_cnt_q] = axi_resp_i.r.data; // enable the right write path be[burst_cnt_q] = '1; // increase burst count @@ -350,11 +348,11 @@ module std_icache #( if (dreq_i.kill_s2) state_d = WAIT_KILLED_AXI_R_RESP; - if (axi.r_valid && axi.r_last) begin + if (axi_resp_i.r_valid && axi_resp_i.r.last) begin state_d = (dreq_i.kill_s2) ? IDLE : REDO_REQ; end - if ((state_q == WAIT_KILLED_AXI_R_RESP) && axi.r_last && axi.r_valid) + if ((state_q == WAIT_KILLED_AXI_R_RESP) && axi_resp_i.r.last && axi_resp_i.r_valid) state_d = IDLE; end // ~> redo the request, @@ -450,7 +448,7 @@ module std_icache #( //pragma translate_off `ifndef VERILATOR initial begin - assert ($bits(axi.aw_addr) == 64) + assert ($bits(axi_req_o.aw.addr) == 64) else $fatal(1, "[icache] Ariane needs a 64-bit bus"); end diff --git a/src/cache_subsystem/std_nbdcache.sv b/src/cache_subsystem/std_nbdcache.sv index fa499cf6db..11715a0d33 100644 --- a/src/cache_subsystem/std_nbdcache.sv +++ b/src/cache_subsystem/std_nbdcache.sv @@ -32,8 +32,10 @@ module std_nbdcache #( input dcache_req_i_t [2:0] req_ports_i, // request ports output dcache_req_o_t [2:0] req_ports_o, // request ports // Cache AXI refill port - AXI_BUS.Master data_if, - AXI_BUS.Master bypass_if + output ariane_axi::req_t axi_data_o, + input ariane_axi::resp_t axi_data_i, + output ariane_axi::req_t axi_bypass_o, + input ariane_axi::resp_t axi_bypass_i ); // ------------------------------- @@ -130,8 +132,8 @@ module std_nbdcache #( .flush_i ( flush_i ), .busy_i ( |busy ), // AMOs - .amo_req_i ( amo_req_i ), - .amo_resp_o ( amo_resp_o ), + .amo_req_i ( amo_req_i ), + .amo_resp_o ( amo_resp_o ), .miss_req_i ( miss_req ), .miss_gnt_o ( miss_gnt ), .bypass_gnt_o ( bypass_gnt ), @@ -149,8 +151,10 @@ module std_nbdcache #( .be_o ( be [0] ), .data_o ( wdata [0] ), .we_o ( we [0] ), - .bypass_if, - .data_if, + .axi_bypass_o, + .axi_bypass_i, + .axi_data_o, + .axi_data_i, .* ); @@ -248,105 +252,10 @@ module std_nbdcache #( ); -`ifndef SYNTHESIS +//pragma translate_off initial begin - assert ($bits(data_if.aw_addr) == 64) else $fatal(1, "Ariane needs a 64-bit bus"); + assert ($bits(axi_data_o.aw.addr) == 64) else $fatal(1, "Ariane needs a 64-bit bus"); assert (DCACHE_LINE_WIDTH/64 inside {2, 4, 8, 16}) else $fatal(1, "Cache line size needs to be a power of two multiple of 64"); end -`endif -endmodule - -// -------------- -// Tag Compare -// -------------- -// -// Description: Arbitrates access to cache memories, simplified request grant protocol -// checks for hit or miss on cache -// -module tag_cmp #( - parameter int unsigned NR_PORTS = 3, - parameter int unsigned ADDR_WIDTH = 64, - parameter type data_t = cache_line_t, - parameter type be_t = cl_be_t, - parameter int unsigned DCACHE_SET_ASSOC = 8 - )( - input logic clk_i, - input logic rst_ni, - - input logic [NR_PORTS-1:0][DCACHE_SET_ASSOC-1:0] req_i, - output logic [NR_PORTS-1:0] gnt_o, - input logic [NR_PORTS-1:0][ADDR_WIDTH-1:0] addr_i, - input data_t [NR_PORTS-1:0] wdata_i, - input logic [NR_PORTS-1:0] we_i, - input be_t [NR_PORTS-1:0] be_i, - output data_t [DCACHE_SET_ASSOC-1:0] rdata_o, - input logic [NR_PORTS-1:0][DCACHE_TAG_WIDTH-1:0] tag_i, // tag in - comes one cycle later - output logic [DCACHE_SET_ASSOC-1:0] hit_way_o, // we've got a hit on the corresponding way - - - output logic [DCACHE_SET_ASSOC-1:0] req_o, - output logic [ADDR_WIDTH-1:0] addr_o, - output data_t wdata_o, - output logic we_o, - output be_t be_o, - input data_t [DCACHE_SET_ASSOC-1:0] rdata_i - ); - - assign rdata_o = rdata_i; - // one hot encoded - logic [NR_PORTS-1:0] id_d, id_q; - logic [DCACHE_TAG_WIDTH-1:0] sel_tag; - - always_comb begin : tag_sel - sel_tag = '0; - for (int unsigned i = 0; i < NR_PORTS; i++) - if (id_q[i]) - sel_tag = tag_i[i]; - end - - for (genvar j = 0; j < DCACHE_SET_ASSOC; j++) begin : tag_cmp - assign hit_way_o[j] = (sel_tag == rdata_i[j].tag) ? rdata_i[j].valid : 1'b0; - end - - always_comb begin - - gnt_o = '0; - id_d = '0; - wdata_o = '0; - req_o = '0; - addr_o = '0; - be_o = '0; - we_o = '0; - // Request Side - // priority select - for (int unsigned i = 0; i < NR_PORTS; i++) begin - req_o = req_i[i]; - id_d = (1'b1 << i); - gnt_o[i] = 1'b1; - addr_o = addr_i[i]; - be_o = be_i[i]; - we_o = we_i[i]; - wdata_o = wdata_i[i]; - - if (req_i[i]) - break; - end - - `ifndef SYNTHESIS - `ifndef VERILATOR - // assert that cache only hits on one way - assert property ( - @(posedge clk_i) $onehot0(hit_way_o)) else begin $error("Hit should be one-hot encoded"); $stop(); end - `endif - `endif - end - - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - id_q <= 0; - end else begin - id_q <= id_d; - end - end - +//pragma translate_on endmodule diff --git a/src/cache_subsystem/std_no_dcache.sv b/src/cache_subsystem/std_no_dcache.sv new file mode 100644 index 0000000000..339c7cf0ed --- /dev/null +++ b/src/cache_subsystem/std_no_dcache.sv @@ -0,0 +1,328 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Description: Bypass version of data cache + +module std_nbdcache #( + parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000 +) ( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + // Cache management + input logic enable_i, // from CSR + input logic flush_i, // high until acknowledged + output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed + output logic miss_o, // we missed on a LD/ST + // AMOs + input ariane_pkg::amo_req_t amo_req_i, + output ariane_pkg::amo_resp_t amo_resp_o, + // Request ports + input ariane_pkg::dcache_req_i_t [2:0] req_ports_i, // request ports + output ariane_pkg::dcache_req_o_t [2:0] req_ports_o, // request ports + // Cache AXI refill port + AXI_BUS.Master data_if, + AXI_BUS.Master bypass_if +); + + localparam PTW = 0; + localparam LOAD = 1; + localparam STORE = 2; + + // Registers + enum logic [3:0] { + Idle, + SampleTagPTW, + SampleTagLoad, + ReadPTW, + ReadLoad, + WaitReadPTW, + WaitReadLoad, + Write, + SendWrite, + WaitB, + AMORead, + WaitAMORead, + AMOSendAW, + AMOSendW, + AMOWaitB + } state_d, state_q; + + typedef struct packed { + logic [63:0] addr; + logic [7:0] be; + logic [1:0] size; + } cache_req_t; + + cache_req_t req_q, req_d; + logic [63:0] amo_load_d, amo_load_q; + // tie-off bypass bus + assign bypass_if.aw_valid = 1'b0; + assign bypass_if.w_valid = 1'b0; + assign bypass_if.ar_valid = 1'b0; + assign bypass_if.b_ready = 1'b1; + assign bypass_if.r_ready = 1'b1; + + // AMOs + ariane_pkg::amo_t amo_op; + logic [63:0] amo_operand_a, amo_operand_b, amo_result_o; + + logic [63:0] load_data; + // re-align load data + assign load_data = data_align(amo_req_i.operand_a[2:0], amo_load_q); + + always_comb begin + req_d = req_q; + amo_load_d = amo_load_q; + + for (int i = 0; i < 3; i++) begin + req_ports_o[i].data_gnt = 1'b0; + req_ports_o[i].data_rvalid = 1'b0; + req_ports_o[i].data_rdata = '0; + end + + data_if.aw_valid = 1'b0; + data_if.aw_id = '0; + data_if.aw_addr = '0; + data_if.aw_size = '0; + data_if.aw_lock = '0; + data_if.aw_cache = '0; + data_if.aw_prot = '0; + data_if.aw_qos = '0; + data_if.aw_region = '0; + data_if.aw_user = '0; + + data_if.w_valid = 1'b0; + data_if.w_data = '0; + data_if.w_strb = '0; + data_if.w_user = '0; + data_if.w_last = 1'b1; + + data_if.ar_id = '0; + data_if.ar_addr = req_q.addr; + data_if.ar_size = req_q.size; + data_if.ar_lock = '0; + data_if.ar_cache = '0; + data_if.ar_prot = '0; + data_if.ar_qos = '0; + data_if.ar_region = '0; + data_if.ar_user = '0; + + // AMOs + amo_resp_o.ack = 1'b0; + amo_resp_o.result = '0; + // silence the unit when not used + amo_op = amo_req_i.amo_op; + amo_operand_a = '0; + amo_operand_b = '0; + + case (state_q) + + Idle: begin + // PTW + if (req_ports_i[PTW].data_req) begin + state_d = SampleTagPTW; + req_d.addr[ariane_pkg::DCACHE_INDEX_WIDTH-1:0] = req_ports_i[PTW].address_index; + req_d.size = req_ports_i[PTW].data_size; + req_ports_o[PTW].data_gnt = 1'b1; + // Load + end else if (req_ports_i[LOAD].data_req) begin + state_d = SampleTagLoad; + req_d.addr[ariane_pkg::DCACHE_INDEX_WIDTH-1:0] = req_ports_i[LOAD].address_index; + req_d.size = req_ports_i[LOAD].data_size; + req_ports_o[LOAD].data_gnt = 1'b1; + // Store + end else if (req_ports_i[STORE].data_req) begin + state_d = Write; + // AMO + end else if (amo_req_i.req) begin + state_d = AMORead; + + end + end + + SampleTagPTW: begin + req_d.addr[ariane_pkg::DCACHE_TAG_WIDTH+ariane_pkg::DCACHE_INDEX_WIDTH-1:ariane_pkg::DCACHE_INDEX_WIDTH] = req_ports_i[PTW].address_tag; + + if (req_ports_i[PTW].kill_req) begin + state_d = Idle; + req_ports_o[PTW].data_rvalid = 1'b1; + end else begin + state_d = ReadPTW; + end + + end + + SampleTagLoad: begin + req_d.addr[ariane_pkg::DCACHE_TAG_WIDTH+ariane_pkg::DCACHE_INDEX_WIDTH-1:ariane_pkg::DCACHE_INDEX_WIDTH] = req_ports_i[LOAD].address_tag; + + if (req_ports_i[LOAD].kill_req) begin + state_d = Idle; + req_ports_o[LOAD].data_rvalid = 1'b1; + end else begin + state_d = ReadLoad; + end + end + + ReadPTW: begin + data_if.aw_valid = 1'b1; + + if (data_if.aw_ready) begin + state_d = WaitReadPTW; + end + end + + ReadLoad: begin + data_if.aw_valid = 1'b1; + + if (data_if.aw_ready) begin + state_d = WaitReadLoad; + end + end + + WaitReadPTW: begin + data_if.r_ready = 1'b1; + if (data_if.r_valid) begin + req_ports_o[PTW].data_rvalid = 1'b1; + req_ports_o[PTW].data_rdata = data_if.r_data; + state_d = Idle; + end + end + + WaitReadLoad: begin + data_if.r_ready = 1'b1; + if (data_if.r_valid) begin + req_ports_o[LOAD].data_rvalid = 1'b1; + req_ports_o[LOAD].data_rdata = data_if.r_data; + state_d = Idle; + end + end + + Write: begin + data_if.aw_valid = 1'b1; + data_if.aw_addr = {req_ports_i[STORE].address_tag, req_ports_i[STORE].address_index}; + data_if.aw_size = {1'b0, req_ports_i[STORE].data_size}; + + if (data_if.w_ready) state_d = SendWrite; + end + + SendWrite: begin + data_if.w_valid = 1'b1; + data_if.w_data = req_ports_i[STORE].data_wdata; + data_if.w_strb = req_ports_i[STORE].data_be; + + if (data_if.w_ready) begin + state_d = WaitB; + req_ports_o[STORE].data_gnt = 1'b1; + end + end + + WaitB: begin + data_if.b_ready = 1'b1; + if (data_if.b_valid) begin + state_d = Idle; + req_ports_o[STORE].data_rvalid = 1'b1; + end + end + + AMORead: begin + data_if.ar_addr = amo_req_i.operand_a; + data_if.ar_size = amo_req_i.size; + data_if.ar_valid = 1'b1; + if (data_if.ar_ready) state_d = WaitAMORead; + end + + WaitAMORead: begin + + data_if.r_ready = 1'b1; + + if (data_if.r_valid) begin + amo_load_d = data_if.r_data; + state_d = AMOSendAW; + end + + // place a reservation on the memory and bail out + if (amo_req_i.amo_op == ariane_pkg::AMO_LR) begin + state_d = Idle; + reservation_d.address = amo_req_i.operand_a[63:3]; + reservation_d.valid = 1'b1; + amo_resp_o.ack = 1'b1; + // Sign-extend for word operation + if (amo_req_i.size == 2'b10) begin + amo_resp_o.result = sext32(load_data[31:0]); + end else begin + amo_resp_o.result = load_data; + end + + end + + end + + AMOSendAW: begin + data_if.aw_valid = 1'b1; + data_if.aw_addr = amo_req_i.operand_a; + data_if.aw_size = {1'b0, amo_req_i.size}; + + if (data_if.aw_ready) begin + state_d = AMOSendW; + end + end + + AMOSendW: begin + // Sign-extend for word operation + if (amo_req_i.size == 2'b10) begin + amo_operand_a = sext32(load_data[31:0]); + amo_operand_b = sext32(amo_req_i.operand_b[31:0]); + end else begin + amo_operand_a = load_data; + amo_operand_b = amo_req_i.operand_b; + end + + data_if.w_valid = 1'b1; + data_if.w_data = data_align(amo_req_i.operand_a[2:0], amo_result_o); + data_if.w_strb = be_gen(amo_req_i.operand_a[2:0], amo_req_i.size); + + if (data_if.w_ready) begin + state_d = AMOWaitB; + end + + end + + AMOWaitB: begin + data_if.b_ready = 1'b1; + if (data_if.b_valid) begin + state_d = Idle; + end + end + endcase + end + + // ----------------- + // AMO ALU + // ----------------- + amo_alu i_amo_alu ( + .amo_op_i ( amo_op ), + .amo_operand_a_i ( amo_operand_a ), + .amo_operand_b_i ( amo_operand_b ), + .amo_result_o ( amo_result_o ) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + state_q <= Idle; + req_q <= '0; + amo_load_q <= '0; + end else begin + state_q <= state_d; + req_q <= req_d; + amo_load_q <= amo_load_d; + end + end +endmodule diff --git a/src/cache_subsystem/tag_cmp.sv b/src/cache_subsystem/tag_cmp.sv new file mode 100644 index 0000000000..b08f28966d --- /dev/null +++ b/src/cache_subsystem/tag_cmp.sv @@ -0,0 +1,104 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// Author: Florian Zaruba +// -------------- +// Tag Compare +// -------------- +// +// Description: Arbitrates access to cache memories, simplified request grant protocol +// checks for hit or miss on cache +// +module tag_cmp #( + parameter int unsigned NR_PORTS = 3, + parameter int unsigned ADDR_WIDTH = 64, + parameter type l_data_t = std_cache_pkg::cache_line_t, + parameter type l_be_t = std_cache_pkg::cl_be_t, + parameter int unsigned DCACHE_SET_ASSOC = 8 +) ( + input logic clk_i, + input logic rst_ni, + + input logic [NR_PORTS-1:0][DCACHE_SET_ASSOC-1:0] req_i, + output logic [NR_PORTS-1:0] gnt_o, + input logic [NR_PORTS-1:0][ADDR_WIDTH-1:0] addr_i, + input l_data_t [NR_PORTS-1:0] wdata_i, + input logic [NR_PORTS-1:0] we_i, + input l_be_t [NR_PORTS-1:0] be_i, + output l_data_t [DCACHE_SET_ASSOC-1:0] rdata_o, + input logic [NR_PORTS-1:0][ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag_i, // tag in - comes one cycle later + output logic [DCACHE_SET_ASSOC-1:0] hit_way_o, // we've got a hit on the corresponding way + + + output logic [DCACHE_SET_ASSOC-1:0] req_o, + output logic [ADDR_WIDTH-1:0] addr_o, + output l_data_t wdata_o, + output logic we_o, + output l_be_t be_o, + input l_data_t [DCACHE_SET_ASSOC-1:0] rdata_i +); + + assign rdata_o = rdata_i; + // one hot encoded + logic [NR_PORTS-1:0] id_d, id_q; + logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] sel_tag; + + always_comb begin : tag_sel + sel_tag = '0; + for (int unsigned i = 0; i < NR_PORTS; i++) + if (id_q[i]) + sel_tag = tag_i[i]; + end + + for (genvar j = 0; j < DCACHE_SET_ASSOC; j++) begin : tag_cmp + assign hit_way_o[j] = (sel_tag == rdata_i[j].tag) ? rdata_i[j].valid : 1'b0; + end + + always_comb begin + + gnt_o = '0; + id_d = '0; + wdata_o = '0; + req_o = '0; + addr_o = '0; + be_o = '0; + we_o = '0; + // Request Side + // priority select + for (int unsigned i = 0; i < NR_PORTS; i++) begin + req_o = req_i[i]; + id_d = (1'b1 << i); + gnt_o[i] = 1'b1; + addr_o = addr_i[i]; + be_o = be_i[i]; + we_o = we_i[i]; + wdata_o = wdata_i[i]; + + if (req_i[i]) + break; + end + + `ifndef SYNTHESIS + `ifndef VERILATOR + // assert that cache only hits on one way + assert property ( + @(posedge clk_i) $onehot0(hit_way_o)) else begin $error("Hit should be one-hot encoded"); $stop(); end + `endif + `endif + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + id_q <= 0; + end else begin + id_q <= id_d; + end + end + +endmodule diff --git a/src/clint/axi_lite_interface.sv b/src/clint/axi_lite_interface.sv index 982ce2fbc3..1dfcc29e85 100644 --- a/src/clint/axi_lite_interface.sv +++ b/src/clint/axi_lite_interface.sv @@ -21,7 +21,8 @@ module axi_lite_interface #( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - AXI_BUS.Slave slave, + input ariane_axi::req_t axi_req_i, + output ariane_axi::resp_t axi_resp_o, output logic [AXI_ADDR_WIDTH-1:0] address_o, output logic en_o, // transaction is valid @@ -38,17 +39,17 @@ module axi_lite_interface #( logic [AXI_ADDR_WIDTH-1:0] address_n, address_q; // pass through read data on the read data channel - assign slave.r_data = data_i; + assign axi_resp_o.r.data = data_i; // send back the transaction id we've latched - assign slave.r_id = trans_id_q; - assign slave.b_id = trans_id_q; + assign axi_resp_o.r.id = trans_id_q; + assign axi_resp_o.b.id = trans_id_q; // set r_last to one as defined by the AXI4 - Lite standard - assign slave.r_last = 1'b1; + assign axi_resp_o.r.last = 1'b1; // we do not support any errors so set response flag to all zeros - assign slave.b_resp = 2'b0; - assign slave.r_resp = 2'b0; + assign axi_resp_o.b.resp = 2'b0; + assign axi_resp_o.r.resp = 2'b0; // output data which we want to write to the slave - assign data_o = slave.w_data; + assign data_o = axi_req_i.w.data; // ------------------------ // AXI4-Lite State Machine // ------------------------ @@ -59,12 +60,12 @@ module axi_lite_interface #( trans_id_n = trans_id_q; // we'll answer a write request only if we got address and data - slave.aw_ready = 1'b0; - slave.w_ready = 1'b0; - slave.b_valid = 1'b0; + axi_resp_o.aw_ready = 1'b0; + axi_resp_o.w_ready = 1'b0; + axi_resp_o.b_valid = 1'b0; - slave.ar_ready = 1'b1; - slave.r_valid = 1'b0; + axi_resp_o.ar_ready = 1'b1; + axi_resp_o.r_valid = 1'b0; address_o = '0; we_o = 1'b0; @@ -74,24 +75,24 @@ module axi_lite_interface #( // we are ready to accept a new request IDLE: begin // we've git a valid write request, we also know that we have asserted the aw_ready - if (slave.aw_valid) begin + if (axi_req_i.aw_valid) begin - slave.aw_ready = 1'b1; + axi_resp_o.aw_ready = 1'b1; // this costs performance but the interconnect does not obey the AXI standard NS = WRITE; // save address - address_n = slave.aw_addr; + address_n = axi_req_i.aw.addr; // save the transaction id for reflection - trans_id_n = slave.aw_id; + trans_id_n = axi_req_i.aw.id; // we've got a valid read request, we also know that we have asserted the ar_ready - end else if (slave.ar_valid) begin + end else if (axi_req_i.ar_valid) begin NS = READ; - address_n = slave.ar_addr; + address_n = axi_req_i.ar.addr; // also request the word from the memory-like interface - address_o = slave.ar_addr; + address_o = axi_req_i.ar.addr; // save the transaction id for reflection - trans_id_n = slave.ar_id; + trans_id_n = axi_req_i.ar.id; end end @@ -101,22 +102,22 @@ module axi_lite_interface #( // enable the ram-like en_o = 1'b1; // we are not ready for another request here - slave.ar_ready = 1'b0; + axi_resp_o.ar_ready = 1'b0; // further assert the correct address address_o = address_q; // the read is valid - slave.r_valid = 1'b1; + axi_resp_o.r_valid = 1'b1; // check if we got a valid r_ready and go back to IDLE - if (slave.r_ready) + if (axi_req_i.r_ready) NS = IDLE; end // We've got a write request at least one cycle earlier // wait here for the data WRITE: begin - if (slave.w_valid) begin + if (axi_req_i.w_valid) begin // we are not ready for another request here - slave.ar_ready = 1'b0; - slave.w_ready = 1'b1; + axi_resp_o.ar_ready = 1'b0; + axi_resp_o.w_ready = 1'b1; // use the latched address address_o = address_q; en_o = 1'b1; @@ -127,9 +128,9 @@ module axi_lite_interface #( end WRITE_B: begin - slave.b_valid = 1'b1; + axi_resp_o.b_valid = 1'b1; // we've already performed the write here so wait for the ready signal - if (slave.b_ready) + if (axi_req_i.b_ready) NS = IDLE; end default:; @@ -156,14 +157,14 @@ module axi_lite_interface #( // Assertions // ------------------------ // Listen for illegal transactions - `ifndef SYNTHESIS + //pragma translate_off `ifndef VERILATOR - // check that burst length is just one - assert property (@(posedge clk_i) slave.ar_valid |-> ((slave.ar_len == 8'b0))) - else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end - // do the same for the write channel - assert property (@(posedge clk_i) slave.aw_valid |-> ((slave.aw_len == 8'b0))) - else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end - `endif + // check that burst length is just one + assert property (@(posedge clk_i) axi_req_i.ar_valid |-> ((axi_req_i.ar.len == 8'b0))) + else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end + // do the same for the write channel + assert property (@(posedge clk_i) axi_req_i.aw_valid |-> ((axi_req_i.aw.len == 8'b0))) + else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end `endif + //pragma translate_on endmodule diff --git a/src/clint/clint.sv b/src/clint/clint.sv index 6b58686ed5..5e84ebaf9c 100644 --- a/src/clint/clint.sv +++ b/src/clint/clint.sv @@ -21,12 +21,12 @@ module clint #( parameter int unsigned AXI_DATA_WIDTH = 64, parameter int unsigned AXI_ID_WIDTH = 10, parameter int unsigned NR_CORES = 1 // Number of cores therefore also the number of timecmp registers and timer interrupts -)( +) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic testmode_i, - AXI_BUS.Slave slave, - + input ariane_axi::req_t axi_req_i, + output ariane_axi::resp_t axi_resp_o, input logic rtc_i, // Real-time clock in (usually 32.768 kHz) output logic [NR_CORES-1:0] timer_irq_o, // Timer interrupts output logic [NR_CORES-1:0] ipi_o // software interrupt (a.k.a inter-process-interrupt) @@ -35,6 +35,9 @@ module clint #( localparam logic [15:0] MSIP_BASE = 16'h0; localparam logic [15:0] MTIMECMP_BASE = 16'h4000; localparam logic [15:0] MTIME_BASE = 16'hbff8; + + localparam AddrSelWidth = (NR_CORES == 1) ? 1 : $clog2(NR_CORES); + // signals from AXI 4 Lite logic [AXI_ADDR_WIDTH-1:0] address; logic en; @@ -60,12 +63,15 @@ module clint #( .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_WIDTH ) ) axi_lite_interface_i ( - .address_o ( address ), - .en_o ( en ), - .we_o ( we ), - .data_i ( rdata ), - .data_o ( wdata ), - .* + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .axi_req_i ( axi_req_i ), + .axi_resp_o ( axi_resp_o ), + .address_o ( address ), + .en_o ( en ), + .we_o ( we ), + .data_i ( rdata ), + .data_o ( wdata ) ); // ----------------------------- @@ -84,11 +90,11 @@ module clint #( if (en && we) begin case (register_address) inside [MSIP_BASE:MSIP_BASE+8*NR_CORES]: begin - msip_n[$unsigned(address[NR_CORES-1+3:3])] = wdata[0]; + msip_n[$unsigned(address[AddrSelWidth-1+3:3])] = wdata[0]; end [MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin - mtimecmp_n[$unsigned(address[NR_CORES-1+3:3])] = wdata; + mtimecmp_n[$unsigned(address[AddrSelWidth-1+3:3])] = wdata; end MTIME_BASE: begin @@ -106,11 +112,11 @@ module clint #( if (en && !we) begin case (register_address) inside [MSIP_BASE:MSIP_BASE+8*NR_CORES]: begin - rdata = msip_q[$unsigned(address[NR_CORES-1+3:3])]; + rdata = msip_q[$unsigned(address[AddrSelWidth-1+3:3])]; end [MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin - rdata = mtimecmp_q[$unsigned(address[NR_CORES-1+3:3])]; + rdata = mtimecmp_q[$unsigned(address[AddrSelWidth-1+3:3])]; end MTIME_BASE: begin @@ -132,7 +138,7 @@ module clint #( always_comb begin : irq_gen // check that the mtime cmp register is set to a meaningful value for (int unsigned i = 0; i < NR_CORES; i++) begin - if (mtimecmp_q[i] != 0 && mtime_q >= mtimecmp_q[i]) begin + if (mtime_q >= mtimecmp_q[i]) begin timer_irq_o[i] = 1'b1; end else begin timer_irq_o[i] = 1'b0; @@ -146,12 +152,13 @@ module clint #( // 1. Put the RTC input through a classic two stage edge-triggered synchronizer to filter out any // metastability effects (or at least make them unlikely :-)) sync_wedge i_sync_edge ( + .clk_i, + .rst_ni, .en_i ( ~testmode_i ), .serial_i ( rtc_i ), .r_edge_o ( increase_timer ), .f_edge_o ( ), // left open - .serial_o ( ), - .* + .serial_o ( ) // left open ); // Registers @@ -167,15 +174,18 @@ module clint #( end end + assign ipi_o = msip_q; + // ------------- // Assertions // -------------- - `ifndef SYNTHESIS + //pragma translate_off `ifndef VERILATOR // Static assertion check for appropriate bus width initial begin assert (AXI_DATA_WIDTH == 64) else $fatal("Timer needs to interface with a 64 bit bus, everything else is not supported"); end `endif - `endif + //pragma translate_on + endmodule diff --git a/src/commit_stage.sv b/src/commit_stage.sv index 9da3081bd3..36813d5228 100644 --- a/src/commit_stage.sv +++ b/src/commit_stage.sv @@ -56,6 +56,20 @@ module commit_stage #( output logic sfence_vma_o // flush TLBs and pipeline ); +// ila_0 i_ila_commit ( +// .clk(clk_i), // input wire clk +// .probe0(commit_instr_i[0].pc), // input wire [63:0] probe0 +// .probe1(commit_instr_i[1].pc), // input wire [63:0] probe1 +// .probe2(commit_instr_i[0].valid), // input wire [0:0] probe2 +// .probe3(commit_instr_i[1].valid), // input wire [0:0] probe3 +// .probe4(commit_ack_o[0]), // input wire [0:0] probe4 +// .probe5(commit_ack_o[0]), // input wire [0:0] probe5 +// .probe6(1'b0), // input wire [0:0] probe6 +// .probe7(1'b0), // input wire [0:0] probe7 +// .probe8(1'b0), // input wire [0:0] probe8 +// .probe9(1'b0) // input wire [0:0] probe9 +// ); + // TODO make these parametric with NR_COMMIT_PORTS assign waddr_o[0] = commit_instr_i[0].rd[4:0]; assign waddr_o[1] = commit_instr_i[1].rd[4:0]; @@ -141,6 +155,7 @@ module commit_stage #( // CSR Logic // --------- // check whether the instruction we retire was a CSR instruction + // interrupts are never taken on CSR instructions if (commit_instr_i[0].fu == CSR) begin // write the CSR file commit_csr_o = 1'b1; @@ -151,6 +166,8 @@ module commit_stage #( // ------------------ // SFENCE.VMA Logic // ------------------ + // sfence.vma is idempotent so we can safely re-execute it after returning + // from interrupt service routine // check if this instruction was a SFENCE_VMA if (commit_instr_i[0].op == SFENCE_VMA) begin // no store pending so we can flush the TLBs and pipeline @@ -161,6 +178,8 @@ module commit_stage #( // ------------------ // FENCE.I Logic // ------------------ + // fence.i is idempotent so we can safely re-execute it after returning + // from interrupt service routine // Fence synchronizes data and instruction streams. That means that we need to flush the private icache // and the private dcache. This is the most expensive instruction. if (commit_instr_i[0].op == FENCE_I || (flush_dcache_i && commit_instr_i[0].fu != STORE)) begin @@ -171,6 +190,8 @@ module commit_stage #( // ------------------ // FENCE Logic // ------------------ + // fence is idempotent so we can safely re-execute it after returning + // from interrupt service routine if (commit_instr_i[0].op == FENCE) begin commit_ack_o[0] = no_st_pending_i; // tell the controller to flush the D$ @@ -230,6 +251,7 @@ module commit_stage #( // ----------------------------- // Exception & Interrupt Logic // ----------------------------- + // TODO(zarubaf): Move interrupt handling to commit stage. // here we know for sure that we are taking the exception always_comb begin : exception_handling // Multiple simultaneous interrupts and traps at the same privilege level are handled in the following decreasing @@ -265,8 +287,15 @@ module commit_stage #( // ------------------------ // check for CSR interrupts (e.g.: normal interrupts which get triggered here) // by putting interrupts here we give them precedence over any other exception - // Don't take the interrupt if we are committing an AMO. - if (csr_exception_i.valid && csr_exception_i.cause[63] && !amo_valid_commit_o) begin + // Don't take the interrupt if we are committing an AMO or a CSR. + // - Atomics because they are atomic in their nature and should not be interrupted + // - CSRs because it makes the implementation easier as CSRs are figured out at the same + // time as interrupts (here in the commit stage). By not allowing them on CSRs we + // reduce the potential critical path length. As all CSRs are single-cycle (plus a + // potential pipeline flush) this only impacts interrupt latency in a couple of cycles. + if (csr_exception_i.valid && csr_exception_i.cause[63] + && !amo_valid_commit_o + && commit_instr_i[0].fu != CSR) begin exception_o = csr_exception_i; exception_o.tval = commit_instr_i[0].ex.tval; end @@ -278,4 +307,4 @@ module commit_stage #( end end -endmodule \ No newline at end of file +endmodule diff --git a/src/common_cells b/src/common_cells index 21a060d2c2..b4769f4121 160000 --- a/src/common_cells +++ b/src/common_cells @@ -1 +1 @@ -Subproject commit 21a060d2c2c75173312b82cc72db96a2c62e66c5 +Subproject commit b4769f4121ed42e99dd168122e036ce1f218637b diff --git a/src/controller.sv b/src/controller.sv index 51916ffbe3..bbd340bdd9 100644 --- a/src/controller.sv +++ b/src/controller.sv @@ -54,9 +54,9 @@ module controller ( flush_unissued_instr_o = 1'b0; flush_id_o = 1'b0; flush_ex_o = 1'b0; - flush_tlb_o = 1'b0; flush_dcache = 1'b0; flush_icache_o = 1'b0; + flush_tlb_o = 1'b0; // ------------ // Mis-predict // ------------ diff --git a/src/csr_buffer.sv b/src/csr_buffer.sv index 9ddac2b65e..706d1f6569 100644 --- a/src/csr_buffer.sv +++ b/src/csr_buffer.sv @@ -20,15 +20,12 @@ module csr_buffer ( input logic rst_ni, // Asynchronous reset active low input logic flush_i, - input fu_op operator_i, - input logic [63:0] operand_a_i, - input logic [63:0] operand_b_i, + input fu_data_t fu_data_i, output logic csr_ready_o, // FU is ready e.g. not busy input logic csr_valid_i, // Input is valid output logic [63:0] csr_result_o, - input logic commit_i, // commit the pending CSR OP - + input logic csr_commit_i, // commit the pending CSR OP // to CSR file output logic [11:0] csr_addr_o // CSR address to commit stage ); @@ -40,7 +37,7 @@ module csr_buffer ( } csr_reg_n, csr_reg_q; // control logic, scoreboard signals - assign csr_result_o = operand_a_i; + assign csr_result_o = fu_data_i.operand_a; assign csr_addr_o = csr_reg_q.csr_address; // write logic @@ -49,16 +46,16 @@ module csr_buffer ( // by default we are ready csr_ready_o = 1'b1; // if we have a valid uncomiited csr req or are just getting one WITHOUT a commit in, we are not ready - if ((csr_reg_q.valid || csr_valid_i) && ~commit_i) + if ((csr_reg_q.valid || csr_valid_i) && ~csr_commit_i) csr_ready_o = 1'b0; // if we got a valid from the scoreboard // store the CSR address if (csr_valid_i) begin - csr_reg_n.csr_address = operand_b_i[11:0]; + csr_reg_n.csr_address = fu_data_i.operand_b[11:0]; csr_reg_n.valid = 1'b1; end // if we get a commit and no new valid instruction -> clear the valid bit - if (commit_i && ~csr_valid_i) begin + if (csr_commit_i && ~csr_valid_i) begin csr_reg_n.valid = 1'b0; end // clear the buffer if we flushed diff --git a/src/csr_regfile.sv b/src/csr_regfile.sv index 541d7c2eb3..ce6b00175e 100644 --- a/src/csr_regfile.sv +++ b/src/csr_regfile.sv @@ -17,7 +17,7 @@ import ariane_pkg::*; module csr_regfile #( parameter int ASID_WIDTH = 1, parameter int unsigned NR_COMMIT_PORTS = 2 -)( +) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic time_irq_i, // Timer threw a interrupt @@ -28,9 +28,8 @@ module csr_regfile #( input scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i, // the instruction we want to commit input logic [NR_COMMIT_PORTS-1:0] commit_ack_i, // Commit acknowledged a instruction -> increase instret CSR // Core and Cluster ID - input logic [3:0] core_id_i, // Core ID is considered static - input logic [5:0] cluster_id_i, // Cluster ID is considered static input logic [63:0] boot_addr_i, // Address from which to start booting, mtvec is set to the same address + input logic [63:0] hart_id_i, // Hart id in a multicore environment (reflected in a CSR) // we are taking an exception input exception_t ex_i, // We've got an exception from the commit stage, take its @@ -117,12 +116,11 @@ module csr_regfile #( logic [63:0] dpc_q, dpc_d; logic [63:0] dscratch0_q, dscratch0_d; + logic [63:0] dscratch1_q, dscratch1_d; logic [63:0] mtvec_q, mtvec_d; logic [63:0] medeleg_q, medeleg_d; logic [63:0] mideleg_q, mideleg_d; logic [63:0] mip_q, mip_d; - logic [63:0] pmpcfg0_q, pmpcfg0_d; - logic [63:0] pmpaddr0_q, pmpaddr0_d; logic [63:0] mie_q, mie_d; logic [63:0] mscratch_q, mscratch_d; logic [63:0] mepc_q, mepc_d; @@ -155,7 +153,7 @@ module csr_regfile #( perf_addr_o = csr_addr.address; if (csr_read) begin - case (csr_addr.address) + unique case (csr_addr.address) riscv::CSR_FFLAGS: begin if (mstatus_q.fs == riscv::Off) begin read_access_exception = 1'b1; @@ -189,13 +187,16 @@ module csr_regfile #( riscv::CSR_DCSR: csr_rdata = {32'b0, dcsr_q}; riscv::CSR_DPC: csr_rdata = dpc_q; riscv::CSR_DSCRATCH0: csr_rdata = dscratch0_q; + riscv::CSR_DSCRATCH1: csr_rdata = dscratch1_q; // trigger module registers riscv::CSR_TSELECT:; // not implemented riscv::CSR_TDATA1:; // not implemented riscv::CSR_TDATA2:; // not implemented riscv::CSR_TDATA3:; // not implemented // supervisor registers - riscv::CSR_SSTATUS: csr_rdata = mstatus_q & riscv::SMODE_STATUS_MASK; + riscv::CSR_SSTATUS: begin + csr_rdata = mstatus_q & ariane_pkg::SMODE_STATUS_READ_MASK; + end riscv::CSR_SIE: csr_rdata = mie_q & mideleg_q; riscv::CSR_SIP: csr_rdata = mip_q & mideleg_q; riscv::CSR_STVEC: csr_rdata = stvec_q; @@ -206,10 +207,11 @@ module csr_regfile #( riscv::CSR_STVAL: csr_rdata = stval_q; riscv::CSR_SATP: begin // intercept reads to SATP if in S-Mode and TVM is enabled - if (priv_lvl_o == riscv::PRIV_LVL_S && mstatus_q.tvm) + if (priv_lvl_o == riscv::PRIV_LVL_S && mstatus_q.tvm) begin read_access_exception = 1'b1; - else + end else begin csr_rdata = satp_q; + end end // machine mode registers riscv::CSR_MSTATUS: csr_rdata = mstatus_q; @@ -224,13 +226,10 @@ module csr_regfile #( riscv::CSR_MCAUSE: csr_rdata = mcause_q; riscv::CSR_MTVAL: csr_rdata = mtval_q; riscv::CSR_MIP: csr_rdata = mip_q; - // Placeholders for M-mode protection - riscv::CSR_PMPCFG0: csr_rdata = pmpcfg0_q; - riscv::CSR_PMPADDR0: csr_rdata = pmpaddr0_q; riscv::CSR_MVENDORID: csr_rdata = 64'b0; // not implemented riscv::CSR_MARCHID: csr_rdata = ARIANE_MARCHID; riscv::CSR_MIMPID: csr_rdata = 64'b0; // not implemented - riscv::CSR_MHARTID: csr_rdata = {53'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]}; + riscv::CSR_MHARTID: csr_rdata = hart_id_i; riscv::CSR_MCYCLE: csr_rdata = cycle_q; riscv::CSR_MINSTRET: csr_rdata = instret_q; // custom (non RISC-V) cache control @@ -258,15 +257,30 @@ module csr_regfile #( // --------------------------- // CSR Write and update logic // --------------------------- + logic [63:0] mask; always_comb begin : csr_update automatic riscv::satp_t sapt; - automatic logic [63:0] mip; automatic logic [63:0] instret; + sapt = satp_q; - mip = csr_wdata & 64'h33; instret = instret_q; - // only FCSR, USIP, SSIP, UTIP, STIP are write-able + + // -------------------- + // Counters + // -------------------- + cycle_d = cycle_q; + instret_d = instret_q; + if (!debug_mode_q) begin + // increase instruction retired counter + for (int i = 0; i < NR_COMMIT_PORTS; i++) begin + if (commit_ack_i[i] && !ex_i.valid) instret++; + end + instret_d = instret; + // increment the cycle count + if (ENABLE_CYCLE_COUNT) cycle_d = cycle_q + 1'b1; + else cycle_d = instret; + end eret_o = 1'b0; flush_o = 1'b0; @@ -284,6 +298,7 @@ module csr_regfile #( dcsr_d = dcsr_q; dpc_d = dpc_q; dscratch0_d = dscratch0_q; + dscratch1_d = dscratch1_q; mstatus_d = mstatus_q; // check whether we come out of reset @@ -316,14 +331,12 @@ module csr_regfile #( stval_d = stval_q; satp_d = satp_q; - cycle_d = cycle_q; - instret_d = instret_q; - en_ld_st_translation_d = en_ld_st_translation_q; dirty_fp_state_csr = 1'b0; + // check for correct access rights and that we are writing if (csr_we) begin - case (csr_addr.address) + unique case (csr_addr.address) // Floating-Point riscv::CSR_FFLAGS: begin if (mstatus_q.fs == riscv::Off) begin @@ -370,6 +383,8 @@ module csr_regfile #( dcsr_d = csr_wdata[31:0]; // debug is implemented dcsr_d.xdebugver = 4'h4; + // privilege level + dcsr_d.prv = priv_lvl_q; // currently not supported dcsr_d.nmip = 1'b0; dcsr_d.stopcount = 1'b0; @@ -377,6 +392,7 @@ module csr_regfile #( end riscv::CSR_DPC: dpc_d = csr_wdata; riscv::CSR_DSCRATCH0: dscratch0_d = csr_wdata; + riscv::CSR_DSCRATCH1: dscratch1_d = csr_wdata; // trigger module CSRs riscv::CSR_TSELECT:; // not implemented riscv::CSR_TDATA1:; // not implemented @@ -384,44 +400,28 @@ module csr_regfile #( riscv::CSR_TDATA3:; // not implemented // sstatus is a subset of mstatus - mask it accordingly riscv::CSR_SSTATUS: begin - mstatus_d = csr_wdata; - // also hardwire the registers for sstatus - mstatus_d.sxl = riscv::XLEN_64; - mstatus_d.uxl = riscv::XLEN_64; - // hardwired extension registers - mstatus_d.sd = (&mstatus_q.xs) | (&mstatus_q.fs); - mstatus_d.xs = riscv::Off; + mask = ariane_pkg::SMODE_STATUS_WRITE_MASK; + mstatus_d = (mstatus_q & ~mask) | (csr_wdata & mask); // hardwire to zero if floating point extension is not present if (!FP_PRESENT) begin mstatus_d.fs = riscv::Off; end - mstatus_d.upie = 1'b0; - mstatus_d.uie = 1'b0; - // not all fields of mstatus can be written - mstatus_d.mie = mstatus_q.mie; - mstatus_d.mpie = mstatus_q.mpie; - mstatus_d.mpp = mstatus_q.mpp; - mstatus_d.mprv = mstatus_q.mprv; - mstatus_d.tsr = mstatus_q.tsr; - mstatus_d.tw = mstatus_q.tw; - mstatus_d.tvm = mstatus_q.tvm; + // hardwired extension registers + mstatus_d.sd = (&mstatus_q.xs) | (&mstatus_q.fs); // this instruction has side-effects flush_o = 1'b1; end // even machine mode interrupts can be visible and set-able to supervisor // if the corresponding bit in mideleg is set riscv::CSR_SIE: begin - // the mideleg makes sure only delegate-able register (and therefore also only implemented registers) - // are written - for (int unsigned i = 0; i < 64; i++) - if (mideleg_q[i]) - mie_d[i] = csr_wdata[i]; + // the mideleg makes sure only delegate-able register (and therefore also only implemented registers) are written + mie_d = (mie_q & ~mideleg_q) | (csr_wdata & mideleg_q); end riscv::CSR_SIP: begin - for (int unsigned i = 0; i < 64; i++) - if (mideleg_q[i]) - mip_d[i] = mip[i]; + // only the supervisor software interrupt is write-able, iff delegated + mask = riscv::MIP_SSIP & mideleg_q; + mip_d = (mip_q & ~mask) | (csr_wdata & mask); end riscv::CSR_SCOUNTEREN:; @@ -439,7 +439,8 @@ module csr_regfile #( sapt = riscv::satp_t'(csr_wdata); // only make ASID_LEN - 1 bit stick, that way software can figure out how many ASID bits are supported sapt.asid = sapt.asid & {{(16-ASID_WIDTH){1'b0}}, {ASID_WIDTH{1'b1}}}; - satp_d = sapt; + // only update if we actually support this mode + if (sapt.mode == MODE_OFF || sapt.mode == MODE_SV39) satp_d = sapt; end // changing the mode can have side-effects on address translation (e.g.: other instructions), re-fetch // the next instruction by executing a flush @@ -448,8 +449,6 @@ module csr_regfile #( riscv::CSR_MSTATUS: begin mstatus_d = csr_wdata; - mstatus_d.sxl = riscv::XLEN_64; - mstatus_d.uxl = riscv::XLEN_64; // hardwired zero registers mstatus_d.sd = (&mstatus_q.xs) | (&mstatus_q.fs); mstatus_d.xs = riscv::Off; @@ -465,20 +464,32 @@ module csr_regfile #( riscv::CSR_MISA:; // machine exception delegation register // 0 - 15 exceptions supported - riscv::CSR_MEDELEG: medeleg_d = csr_wdata & 64'hF7FF; + riscv::CSR_MEDELEG: begin + mask = (1 << riscv::INSTR_ADDR_MISALIGNED) | + (1 << riscv::BREAKPOINT) | + (1 << riscv::ENV_CALL_UMODE) | + (1 << riscv::INSTR_PAGE_FAULT) | + (1 << riscv::LOAD_PAGE_FAULT) | + (1 << riscv::STORE_PAGE_FAULT); + medeleg_d = (medeleg_q & ~mask) | (csr_wdata & mask); + end // machine interrupt delegation register // we do not support user interrupt delegation - riscv::CSR_MIDELEG: mideleg_d = csr_wdata & 64'hBBB; - + riscv::CSR_MIDELEG: begin + mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP; + mideleg_d = (mideleg_q & ~mask) | (csr_wdata & mask); + end // mask the register so that unsupported interrupts can never be set - riscv::CSR_MIE: mie_d = csr_wdata & 64'hBBB; // we only support supervisor and m-mode interrupts + riscv::CSR_MIE: begin + mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP | riscv::MIP_MSIP | riscv::MIP_MTIP; + mie_d = (mie_q & ~mask) | (csr_wdata & mask); // we only support supervisor and M-mode interrupts + end riscv::CSR_MTVEC: begin - mtvec_d = {csr_wdata[63:2], 1'b0, csr_wdata[0]}; + mtvec_d = {csr_wdata[63:2], 1'b0, csr_wdata[0]}; // we are in vector mode, this implementation requires the additional // alignment constraint of 64 * 4 bytes - if (csr_wdata[0]) - mtvec_d = {csr_wdata[63:8], 7'b0, csr_wdata[0]}; + if (csr_wdata[0]) mtvec_d = {csr_wdata[63:8], 7'b0, csr_wdata[0]}; end riscv::CSR_MCOUNTEREN:; @@ -486,10 +497,10 @@ module csr_regfile #( riscv::CSR_MEPC: mepc_d = {csr_wdata[63:1], 1'b0}; riscv::CSR_MCAUSE: mcause_d = csr_wdata; riscv::CSR_MTVAL: mtval_d = csr_wdata; - riscv::CSR_MIP: mip_d = mip; - // Placeholders for M-mode protection - riscv::CSR_PMPCFG0: pmpcfg0_d = csr_wdata; - riscv::CSR_PMPADDR0: pmpaddr0_d = csr_wdata; + riscv::CSR_MIP: begin + mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP; + mip_d = (mip_q & ~mask) | (csr_wdata & mask); + end // performance counters riscv::CSR_MCYCLE: cycle_d = csr_wdata; riscv::CSR_MINSTRET: instret = csr_wdata; @@ -514,25 +525,27 @@ module csr_regfile #( endcase end + mstatus_d.sxl = riscv::XLEN_64; + mstatus_d.uxl = riscv::XLEN_64; + // mark the floating point extension register as dirty if (FP_PRESENT && (dirty_fp_state_csr || dirty_fp_state_i)) begin mstatus_d.fs = riscv::Dirty; end // write the floating point status register - if (csr_write_fflags_i) + if (csr_write_fflags_i) begin fcsr_d.fflags = csr_wdata_i[4:0] | fcsr_q.fflags; - + end // --------------------- // External Interrupts // --------------------- // Machine Mode External Interrupt Pending - mip_d[11] = mie_q[11] & irq_i[1]; - mip_d[9] = mie_q[9] & irq_i[0]; + mip_d[riscv::IRQ_M_EXT] = irq_i[0]; // Machine software interrupt - mip_d[3] = mie_q[3] & ipi_i; + mip_d[riscv::IRQ_M_SOFT] = ipi_i; // Timer interrupt pending, coming from platform timer - mip_d[7] = time_irq_i; + mip_d[riscv::IRQ_M_TIMER] = time_irq_i; // ----------------------- // Manage Exception Stack @@ -562,13 +575,20 @@ module csr_regfile #( mstatus_d.sie = 1'b0; mstatus_d.spie = mstatus_q.sie; // this can either be user or supervisor mode - mstatus_d.spp = logic'(priv_lvl_q); + mstatus_d.spp = priv_lvl_q[0]; // set cause scause_d = ex_i.cause; // set epc sepc_d = pc_i; // set mtval or stval - stval_d = ex_i.tval; + stval_d = (ariane_pkg::ZERO_TVAL + && (ex_i.cause inside { + riscv::ILLEGAL_INSTR, + riscv::BREAKPOINT, + riscv::ENV_CALL_UMODE, + riscv::ENV_CALL_SMODE, + riscv::ENV_CALL_MMODE + } || ex_i.cause[63])) ? '0 : ex_i.tval; // trap to machine mode end else begin // update mstatus @@ -580,11 +600,17 @@ module csr_regfile #( // set epc mepc_d = pc_i; // set mtval or stval - mtval_d = ex_i.tval; + mtval_d = (ariane_pkg::ZERO_TVAL + && (ex_i.cause inside { + riscv::ILLEGAL_INSTR, + riscv::BREAKPOINT, + riscv::ENV_CALL_UMODE, + riscv::ENV_CALL_SMODE, + riscv::ENV_CALL_MMODE + } || ex_i.cause[63])) ? '0 : ex_i.tval; end priv_lvl_d = trap_to_priv_lvl; - end // ------------------------------ @@ -698,11 +724,11 @@ module csr_regfile #( // return from exception, IF doesn't care from where we are returning eret_o = 1'b1; // return the previous supervisor interrupt enable flag - mstatus_d.sie = mstatus_d.spie; + mstatus_d.sie = mstatus_q.spie; // restore the previous privilege level - priv_lvl_d = riscv::priv_lvl_t'({1'b0, mstatus_d.spp}); + priv_lvl_d = riscv::priv_lvl_t'({1'b0, mstatus_q.spp}); // set spp to user mode - mstatus_d.spp = logic'(riscv::PRIV_LVL_U); + mstatus_d.spp = 1'b0; // set spie to 1 mstatus_d.spie = 1'b1; end @@ -716,21 +742,6 @@ module csr_regfile #( // actually return from debug mode debug_mode_d = 1'b0; end - - // -------------------- - // Counters - // -------------------- - if (!debug_mode_q) begin - // just increment the cycle count - cycle_d = cycle_q + 1'b1; - // increase instruction retired counter - for (int i = 0; i < NR_COMMIT_PORTS; i++) begin - if (commit_ack_i[i]) begin - instret++; - end - end - instret_d = instret; - end end // --------------------------- @@ -766,7 +777,7 @@ module csr_regfile #( csr_we = 1'b0; csr_read = 1'b0; dret = 1'b1; // signal a return from debug mode - end // DRET: + end default: begin csr_we = 1'b0; csr_read = 1'b0; @@ -796,6 +807,7 @@ module csr_regfile #( // ----------------- // Interrupt Control // ----------------- + // TODO(zarubaf): Move interrupt handling to commit stage. // we decode an interrupt the same as an exception, hence it will be taken if the instruction did not // throw any previous exception. // we have three interrupt sources: external interrupts, software interrupts, timer interrupts (order of precedence) @@ -807,7 +819,9 @@ module csr_regfile #( if (mie_q[riscv::S_SW_INTERRUPT[5:0]] && mip_q[riscv::S_SW_INTERRUPT[5:0]]) interrupt_cause = riscv::S_SW_INTERRUPT; // Supervisor External Interrupt - if (mie_q[riscv::S_EXT_INTERRUPT[5:0]] && mip_q[riscv::S_EXT_INTERRUPT[5:0]]) + // The logical-OR of the software-writable bit and the signal from the external interrupt controller is + // used to generate external interrupts to the supervisor + if (mie_q[riscv::S_EXT_INTERRUPT[5:0]] && (mip_q[riscv::S_EXT_INTERRUPT[5:0]] | irq_i[1])) interrupt_cause = riscv::S_EXT_INTERRUPT; // Machine Timer Interrupt if (mip_q[riscv::M_TIMER_INTERRUPT[5:0]] && mie_q[riscv::M_TIMER_INTERRUPT[5:0]]) @@ -846,7 +860,8 @@ module csr_regfile #( // ----------------- // Privilege Check // ----------------- - // if we are reading or writing, check for the correct privilege level + // if we are reading or writing, check for the correct privilege level this has + // precedence over interrupts if (csr_we || csr_read) begin if ((riscv::priv_lvl_t'(priv_lvl_o & csr_addr.csr_decode.priv_lvl) != csr_addr.csr_decode.priv_lvl)) begin csr_exception_o.cause = riscv::ILLEGAL_INSTR; @@ -871,9 +886,10 @@ module csr_regfile #( // ------------------- // if there is any interrupt pending un-stall the core // also un-stall if we want to enter debug mode - if (|mip_q || debug_req_i) begin + if (|mip_q || debug_req_i || irq_i[1]) begin wfi_d = 1'b0; - // or alternatively if there is no exception pending and we are not in debug mode wait here for the interrupt + // or alternatively if there is no exception pending and we are not in debug mode wait here + // for the interrupt end else if (!debug_mode_q && csr_op_i == WFI && !ex_i.valid) begin wfi_d = 1'b1; end @@ -913,7 +929,23 @@ module csr_regfile #( // ------------------- // Output Assignments // ------------------- - assign csr_rdata_o = csr_rdata; + always_comb begin + // When the SEIP bit is read with a CSRRW, CSRRS, or CSRRC instruction, the value + // returned in the rd destination register contains the logical-OR of the software-writable + // bit and the interrupt signal from the interrupt controller. + csr_rdata_o = csr_rdata; + + unique case (csr_addr.address) + riscv::CSR_MIP: csr_rdata_o = csr_rdata | (irq_i[1] << riscv::IRQ_S_EXT); + // in supervisor mode we also need to check whether we delegated this bit + riscv::CSR_SIP: begin + csr_rdata_o = csr_rdata + | ((irq_i[1] & mideleg_q[riscv::IRQ_S_EXT]) << riscv::IRQ_S_EXT); + end + default:; + endcase + end + // in debug mode we execute with privilege level M assign priv_lvl_o = (debug_mode_q) ? riscv::PRIV_LVL_M : priv_lvl_q; // FPU outputs @@ -925,7 +957,9 @@ module csr_regfile #( assign asid_o = satp_q.asid[ASID_WIDTH-1:0]; assign sum_o = mstatus_q.sum; // we support bare memory addressing and SV39 - assign en_translation_o = (satp_q.mode == 4'h8 && priv_lvl_o != riscv::PRIV_LVL_M) ? 1'b1 : 1'b0; + assign en_translation_o = (satp_q.mode == 4'h8 && priv_lvl_o != riscv::PRIV_LVL_M) + ? 1'b1 + : 1'b0; assign mxr_o = mstatus_q.mxr; assign tvm_o = mstatus_q.tvm; assign tw_o = mstatus_q.tw; @@ -950,6 +984,7 @@ module csr_regfile #( dcsr_q.prv <= riscv::PRIV_LVL_M; dpc_q <= 64'b0; dscratch0_q <= 64'b0; + dscratch1_q <= 64'b0; // machine mode registers mstatus_q <= 64'b0; // set to boot address + direct mode + 4 byte offset which is the initial trap @@ -988,6 +1023,7 @@ module csr_regfile #( dcsr_q <= dcsr_d; dpc_q <= dpc_d; dscratch0_q <= dscratch0_d; + dscratch1_q <= dscratch1_d; // machine mode registers mstatus_q <= mstatus_d; mtvec_rst_load_q <= 1'b0; @@ -1022,12 +1058,12 @@ module csr_regfile #( //------------- // Assertions //------------- - `ifndef SYNTHESIS + //pragma translate_off `ifndef VERILATOR // check that eret and ex are never valid together assert property ( @(posedge clk_i) !(eret_o && ex_i.valid)) else begin $error("eret and exception should never be valid at the same time"); $stop(); end `endif - `endif + //pragma translate_on endmodule diff --git a/src/debug/ariane.cfg b/src/debug/ariane.cfg index eb83763c46..00ab350811 100644 --- a/src/debug/ariane.cfg +++ b/src/debug/ariane.cfg @@ -15,7 +15,7 @@ riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 # prefer to use sba for system bus access -riscv set_prefer_sba off +riscv set_prefer_sba on init halt diff --git a/src/debug/debug_rom/debug_rom.sv b/src/debug/debug_rom/debug_rom.sv index e295075e72..05ca2388d9 100644 --- a/src/debug/debug_rom/debug_rom.sv +++ b/src/debug/debug_rom/debug_rom.sv @@ -1,10 +1,10 @@ /* Copyright 2018 ETH Zurich and University of Bologna. * Copyright and related rights are licensed under the Solderpad Hardware - * License, Version 0.51 (the “License”); you may not use this file except in + * License, Version 0.51 (the "License"); you may not use this file except in * compliance with the License. You may obtain a copy of the License at * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law * or agreed to in writing, software, hardware and materials distributed under - * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR + * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR * CONDITIONS OF ANY KIND, either express or implied. See the License for the * specific language governing permissions and limitations under the License. * @@ -20,21 +20,22 @@ module debug_rom ( input logic [63:0] addr_i, output logic [63:0] rdata_o ); - localparam int RomSize = 12; + localparam int RomSize = 13; const logic [RomSize-1:0][63:0] mem = { - 64'h7b200073_7b202473, - 64'h10802423_f1402473, + 64'h00000000_00000000, + 64'h7B200073_7B202473, + 64'h10802423_F1402473, 64'h30000067_10002223, - 64'h7b202473_00100073, - 64'h10002623_fddff06f, - 64'hfc0418e3_00247413, - 64'h40044403_f1402473, + 64'h7B202473_00100073, + 64'h10002623_FDDFF06F, + 64'hFC0418E3_00247413, + 64'h40044403_F1402473, 64'h02041063_00147413, 64'h40044403_10802023, - 64'hf1402473_7b241073, - 64'h0ff0000f_0340006f, - 64'h04c0006f_00c0006f + 64'hF1402473_7B241073, + 64'h0FF0000F_0340006F, + 64'h04C0006F_00C0006F }; logic [$clog2(RomSize)-1:0] addr_q; @@ -45,5 +46,7 @@ module debug_rom ( end end - assign rdata_o = mem[addr_q]; + // this prevents spurious Xes from propagating into + // the speculative fetch stage of the core + assign rdata_o = (addr_q 32) ? &halted_i[hartsel[19:10] +: 32] : 1'b0; - // assign haltsum2[i] = (NrHarts > 1024) ? &halted_i[hartsel[19:15] +: 1024] : 1'b0; - // assign haltsum3[i] = (NrHarts > 32768) ? &halted_i[hartsel[19:19] +: 32768] : 1'b0; + logic [NrHarts/2**5 :0][31:0] halted_reshaped0; + logic [NrHarts/2**10:0][31:0] halted_reshaped1; + logic [NrHarts/2**15:0][31:0] halted_reshaped2; + logic [(NrHarts/2**10+1)*32-1:0] halted_flat1; + logic [(NrHarts/2**15+1)*32-1:0] halted_flat2; + logic [32-1:0] halted_flat3; + + // haltsum0 + assign halted_reshaped0 = halted_i; + assign haltsum0 = halted_reshaped0[hartsel_o[19:5]]; + // haltsum1 + always_comb begin : p_reduction1 + halted_flat1 = '0; + for (int k=0; k NrHarts[19:0] - 1) ? 1'b1 : 1'b0; dmstatus.anynonexistent = (hartsel_o > NrHarts[19:0] - 1) ? 1'b1 : 1'b0; - dmstatus.allhalted = halted_i[hartsel_o[HartSelLen-1:0]]; - dmstatus.anyhalted = halted_i[hartsel_o[HartSelLen-1:0]]; + dmstatus.allhalted = halted_i[selected_hart]; + dmstatus.anyhalted = halted_i[selected_hart]; - dmstatus.allrunning = ~halted_i[hartsel_o[HartSelLen-1:0]]; - dmstatus.anyrunning = ~halted_i[hartsel_o[HartSelLen-1:0]]; + dmstatus.allrunning = ~halted_i[selected_hart]; + dmstatus.anyrunning = ~halted_i[selected_hart]; // abstractcs abstractcs = '0; @@ -201,7 +229,7 @@ module dm_csrs #( end if (!cmdbusy_i) begin // check whether we need to re-execute the command (just give a cmd_valid) - cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - dm::Data0]; + cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - int'(dm::Data0)]; end end dm::DMControl: resp_queue_data = dmcontrol_q; @@ -215,7 +243,8 @@ module dm_csrs #( resp_queue_data = progbuf_q[dmi_req_i.addr[4:0]]; if (!cmdbusy_i) begin // check whether we need to re-execute the command (just give a cmd_valid) - cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]]; + // TODO(zarubaf): check if offset is correct - without it this may assign Xes + cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]+16]; end end dm::HaltSum0: resp_queue_data = haltsum0; @@ -272,7 +301,7 @@ module dm_csrs #( if (!cmdbusy_i && dm::DataCount > 0) begin data_d[dmi_req_i.addr[4:0]] = dmi_req_i.data; // check whether we need to re-execute the command (just give a cmd_valid) - cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - dm::Data0]; + cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - int'(dm::Data0)]; end end dm::DMControl: begin @@ -327,7 +356,8 @@ module dm_csrs #( progbuf_d[dmi_req_i.addr[4:0]] = dmi_req_i.data; // check whether we need to re-execute the command (just give a cmd_valid) // this should probably throw an error if executed during another command was busy - cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]]; + // TODO(zarubaf): check if offset is correct - without it this may assign Xes + cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]+16]; end end dm::SBCS: begin @@ -429,7 +459,7 @@ module dm_csrs #( // output multiplexer always_comb begin - selected_hart = hartsel_o[NrHarts-1:0]; + selected_hart = hartsel_o[HartSelLen-1:0]; // default assignment haltreq_o = '0; resumereq_o = '0; @@ -446,17 +476,7 @@ module dm_csrs #( logic ndmreset_n; - // if the PoR is set we want to re-set the other system as well - rstgen_bypass i_rstgen_bypass ( - .clk_i ( clk_i ), - .rst_ni ( ~(dmcontrol_q.ndmreset | ~rst_ni) ), - .rst_test_mode_ni ( rst_ni ), - .test_mode_i ( testmode_i ), - .rst_no ( ndmreset_n ), - .init_no () // keep open - ); - - assign ndmreset_o = ~ndmreset_n; + assign ndmreset_o = dmcontrol_q.ndmreset; // response FIFO fifo_v2 #( @@ -529,4 +549,21 @@ module dm_csrs #( end end end -endmodule \ No newline at end of file + + +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + + +//pragma translate_off +`ifndef VERILATOR + haltsum: assert property ( + @(posedge clk_i) disable iff (~rst_ni) (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) |-> + !({1'b0, dmi_req_i.addr} inside {dm::HaltSum0, dm::HaltSum1, dm::HaltSum2, dm::HaltSum3})) + else $warning("Haltsums are not implemented yet and always return 0."); +`endif +//pragma translate_on + + +endmodule diff --git a/src/debug/dm_sba.sv b/src/debug/dm_sba.sv index 7b46d92cb2..218ae19678 100644 --- a/src/debug/dm_sba.sv +++ b/src/debug/dm_sba.sv @@ -20,8 +20,9 @@ module dm_sba ( input logic clk_i, // Clock input logic rst_ni, input logic dmactive_i, // synchronous reset active low - - AXI_BUS.Master axi_master, + // AXI port + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i, input logic [63:0] sbaddress_i, input logic sbaddress_write_valid_i, @@ -136,7 +137,7 @@ module dm_sba ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .req_i ( req ), - .type_i ( std_cache_pkg::SINGLE_REQ ), + .type_i ( ariane_axi::SINGLE_REQ ), .gnt_o ( gnt ), .gnt_id_o ( ), .addr_i ( address ), @@ -150,15 +151,16 @@ module dm_sba ( .id_o ( ), .critical_word_o ( ), // not needed here .critical_word_valid_o ( ), // not needed here - .axi ( axi_master ) + .axi_req_o, + .axi_resp_i ); - `ifndef SYNTHESIS - `ifndef verilator + //pragma translate_off + `ifndef VERILATOR // maybe bump severity to $error if not handled at runtime dm_sba_access_size: assert property(@(posedge clk_i) disable iff (dmactive_i !== 1'b0) (state_d != Idle) |-> (sbaccess_i < 4)) else $warning ("accesses > 8 byte not supported at the moment"); `endif - `endif + //pragma translate_on endmodule diff --git a/src/debug/dm_top.sv b/src/debug/dm_top.sv index 303c414afe..b8026124f5 100644 --- a/src/debug/dm_top.sv +++ b/src/debug/dm_top.sv @@ -23,7 +23,7 @@ module dm_top #( parameter int AxiAddrWidth = -1, parameter int AxiDataWidth = -1, parameter int AxiUserWidth = -1 -)( +) ( input logic clk_i, // clock input logic rst_ni, // asynchronous reset active low, connect PoR here, not the system reset input logic testmode_i, @@ -32,8 +32,14 @@ module dm_top #( output logic [NrHarts-1:0] debug_req_o, // async debug request input logic [NrHarts-1:0] unavailable_i, // communicate whether the hart is unavailable (e.g.: power down) - AXI_BUS.Slave axi_slave, // bus slave, for an execution based technique - AXI_BUS.Master axi_master, // bus master, for system bus accesses + // bus slave, for an execution based technique + input ariane_axi::req_t axi_s_req_i, + output ariane_axi::resp_t axi_s_resp_o, + + // bus master, for system bus accesses + output ariane_axi::req_t axi_m_req_o, + input ariane_axi::resp_t axi_m_resp_i, + // Connection to DTM - compatible to RocketChip Debug Module input logic dmi_rst_ni, input logic dmi_req_valid_i, @@ -48,7 +54,7 @@ module dm_top #( // Debug CSRs dm::hartinfo_t [NrHarts-1:0] hartinfo; logic [NrHarts-1:0] halted; - logic [NrHarts-1:0] running; + // logic [NrHarts-1:0] running; logic [NrHarts-1:0] resumeack; logic [NrHarts-1:0] haltreq; logic [NrHarts-1:0] resumereq; @@ -145,7 +151,8 @@ module dm_top #( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .dmactive_i ( dmactive_o ), - .axi_master, + .axi_req_o ( axi_m_req_o ), + .axi_resp_i ( axi_m_resp_i ), .sbaddress_i ( sbaddress_csrs_sba ), .sbaddress_o ( sbaddress_sba_csrs ), .sbaddress_write_valid_i ( sbaddress_write_valid ), @@ -191,20 +198,33 @@ module dm_top #( .rdata_o ( rdata ) ); + AXI_BUS #( + .AXI_ID_WIDTH ( AxiIdWidth ), + .AXI_ADDR_WIDTH ( AxiAddrWidth ), + .AXI_DATA_WIDTH ( AxiDataWidth ), + .AXI_USER_WIDTH ( AxiUserWidth ) + ) slave(); + + axi_slave_connect_rev i_axi_slave_connect_rev ( + .axi_req_i (axi_s_req_i), + .axi_resp_o(axi_s_resp_o), + .slave(slave)); + axi2mem #( .AXI_ID_WIDTH ( AxiIdWidth ), .AXI_ADDR_WIDTH ( AxiAddrWidth ), .AXI_DATA_WIDTH ( AxiDataWidth ), .AXI_USER_WIDTH ( AxiUserWidth ) ) i_axi2mem ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slave ( axi_slave ), - .req_o ( req ), - .we_o ( we ), - .addr_o ( addr ), - .be_o ( be ), - .data_o ( wdata ), - .data_i ( rdata ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slave ( slave ), + .req_o ( req ), + .we_o ( we ), + .addr_o ( addr ), + .be_o ( be ), + .data_o ( wdata ), + .data_i ( rdata ) ); + endmodule diff --git a/src/decoder.sv b/src/decoder.sv index 4362d551e3..87c7ae07af 100644 --- a/src/decoder.sv +++ b/src/decoder.sv @@ -23,6 +23,7 @@ import ariane_pkg::*; module decoder ( input logic [63:0] pc_i, // PC from IF input logic is_compressed_i, // is a compressed instruction + input logic [15:0] compressed_instr_i, // compressed form of instruction input logic is_illegal_i, // illegal compressed instruction input logic [31:0] instruction_i, // instruction from IF input branchpredict_sbe_t branch_predict_i, @@ -114,7 +115,7 @@ module decoder ( if (priv_lvl_i == riscv::PRIV_LVL_S && tsr_i) begin illegal_instr = 1'b1; // do not change privilege level if this is an illegal instruction - instruction_o.op = ADD; + instruction_o.op = ADD; end end // MRET @@ -133,7 +134,7 @@ module decoder ( end // WFI 12'b1_0000_0101: begin - instruction_o.op = WFI; + if (ENABLE_WFI) instruction_o.op = WFI; // if timeout wait is set, trap on an illegal instruction in S Mode // (after 0 cycles timeout) if (priv_lvl_i == riscv::PRIV_LVL_S && tw_i) begin @@ -1055,7 +1056,7 @@ module decoder ( if (~ex_i.valid) begin // if we didn't already get an exception save the instruction here as we may need it // in the commit stage if we got a access exception to one of the CSR registers - instruction_o.ex.tval = {32'b0, instruction_i}; + instruction_o.ex.tval = (is_compressed_i) ? {48'b0, compressed_instr_i} : {32'b0, instruction_i}; // instructions which will throw an exception are marked as valid // e.g.: they can be committed anytime and do not need to wait for any functional unit // check here if we decoded an invalid instruction or if the compressed decoder already decoded diff --git a/src/ex_stage.sv b/src/ex_stage.sv index acb41cc469..f40bec636f 100644 --- a/src/ex_stage.sv +++ b/src/ex_stage.sv @@ -15,30 +15,25 @@ import ariane_pkg::*; -module ex_stage #( - parameter int ASID_WIDTH = 1 -)( +module ex_stage ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic flush_i, - input fu_t fu_i, - input fu_op operator_i, - input logic [63:0] operand_a_i, - input logic [63:0] operand_b_i, - input logic [63:0] imm_i, - input logic [TRANS_ID_BITS-1:0] trans_id_i, + input fu_data_t fu_data_i, input logic [63:0] pc_i, // PC of current instruction input logic is_compressed_instr_i, // we need to know if this was a compressed instruction // in order to calculate the next PC on a mis-predict + // Fixed latency unit(s) + output logic [63:0] flu_result_o, + output logic [TRANS_ID_BITS-1:0] flu_trans_id_o, // ID of scoreboard entry at which to write back + output exception_t flu_exception_o, + output logic flu_ready_o, // FLU is ready + output logic flu_valid_o, // FLU result is valid + // Branches and Jumps // ALU 1 - output logic alu_ready_o, // FU is ready input logic alu_valid_i, // Output is valid - output logic alu_valid_o, // ALU result is valid - output logic [63:0] alu_result_o, - output logic [TRANS_ID_BITS-1:0] alu_trans_id_o, // ID of scoreboard entry at which to write back - output exception_t alu_exception_o, - // Branches and Jumps + // Branch Unit input logic branch_valid_i, // we are using the branch unit input branchpredict_sbe_t branch_predict_i, output branchpredict_t resolved_branch_o, // the branch engine uses the write back from the ALU @@ -47,23 +42,25 @@ module ex_stage #( input logic csr_valid_i, output logic [11:0] csr_addr_o, input logic csr_commit_i, + // MULT + input logic mult_valid_i, // Output is valid // LSU - output logic lsu_ready_o, // FU is ready - input logic lsu_valid_i, // Input is valid - output logic lsu_valid_o, // Output is valid - output logic [63:0] lsu_result_o, - output logic [TRANS_ID_BITS-1:0] lsu_trans_id_o, + output logic lsu_ready_o, // FU is ready + input logic lsu_valid_i, // Input is valid + + output logic load_valid_o, + output logic [63:0] load_result_o, + output logic [TRANS_ID_BITS-1:0] load_trans_id_o, + output exception_t load_exception_o, + output logic store_valid_o, + output logic [63:0] store_result_o, + output logic [TRANS_ID_BITS-1:0] store_trans_id_o, + output exception_t store_exception_o, + input logic lsu_commit_i, - output logic lsu_commit_ready_o, // commit queue is ready to accept another commit request - output exception_t lsu_exception_o, + output logic lsu_commit_ready_o, // commit queue is ready to accept another commit request output logic no_st_pending_o, input logic amo_valid_commit_i, - // MULT - output logic mult_ready_o, // FU is ready - input logic mult_valid_i, // Output is valid - output logic [TRANS_ID_BITS-1:0] mult_trans_id_o, - output logic [63:0] mult_result_o, - output logic mult_valid_o, // FPU output logic fpu_ready_o, // FU is ready input logic fpu_valid_i, // Output is valid @@ -75,7 +72,6 @@ module ex_stage #( output logic [63:0] fpu_result_o, output logic fpu_valid_o, output exception_t fpu_exception_o, - // Memory Management input logic enable_translation_i, input logic en_ld_st_translation_i, @@ -101,69 +97,116 @@ module ex_stage #( output logic dtlb_miss_o ); + // ------------------------- + // Fixed Latency Units + // ------------------------- + // all fixed latency units share a single issue port and a sing write + // port into the scoreboard. At the moment those are: + // 1. ALU - all operations are single cycle + // 2. Branch unit: operation is single cycle, the ALU is needed + // for comparison + // 3. CSR: This is a small buffer which saves the address of the CSR. + // The value is then re-fetched once the instruction retires. The buffer + // is only a single entry deep, hence this operation will block all + // other operations once this buffer is full. This should not be a major + // concern though as CSRs are infrequent. + // 4. Multiplier/Divider: The multiplier has a fixed latency of 1 cycle. + // The issue logic will take care of not issuing + // another instruction if it will collide on the + // output port. Divisions are arbitrary in length + // they will simply block the issue of all other + // instructions. + + // from ALU to branch unit logic alu_branch_res; // branch comparison result + logic [63:0] alu_result, branch_result, csr_result, mult_result; + logic csr_ready, mult_ready; + logic [TRANS_ID_BITS-1:0] mult_trans_id; + logic mult_valid; - // ----- - // ALU - // ----- + // 1. ALU (combinatorial) + // data silence operation fu_data_t alu_data; - assign alu_data.operator = (alu_valid_i | branch_valid_i | csr_valid_i) ? operator_i : ADD; - assign alu_data.operand_a = (alu_valid_i | branch_valid_i | csr_valid_i) ? operand_a_i : '0; - assign alu_data.operand_b = (alu_valid_i | branch_valid_i | csr_valid_i) ? operand_b_i : '0; - assign alu_data.imm = (alu_valid_i | branch_valid_i | csr_valid_i) ? imm_i : '0; + assign alu_data = (alu_valid_i | branch_valid_i) ? fu_data_i : '0; - // fixed latency FUs - // TOOD(zarubaf) Re-name this module and re-factor ALU alu alu_i ( .clk_i, .rst_ni, - .flush_i, - .pc_i, - .trans_id_i, - .alu_valid_i, - .branch_valid_i, - .csr_valid_i ( csr_valid_i ), - .operator_i ( alu_data.operator ), - .operand_a_i ( alu_data.operand_a ), - .operand_b_i ( alu_data.operand_b ), - .imm_i ( alu_data.imm ), - .result_o ( alu_result_o ), - .alu_valid_o, - .alu_ready_o, - .alu_trans_id_o, - .alu_exception_o, + .fu_data_i ( alu_data ), + .result_o ( alu_result ), + .alu_branch_res_o ( alu_branch_res ) + ); - .fu_valid_i ( alu_valid_i || lsu_valid_i || csr_valid_i || mult_valid_i || fpu_valid_i ), + // 2. Branch Unit (combinatorial) + // we don't silence the branch unit as this is already critical and we do + // not want to add another layer of logic + branch_unit branch_unit_i ( + .fu_data_i, + .pc_i, .is_compressed_instr_i, + // any functional unit is valid, check that there is no accidental mis-predict + .fu_valid_i ( alu_valid_i || lsu_valid_i || csr_valid_i || mult_valid_i || fpu_valid_i ) , + .branch_valid_i, + .branch_comp_res_i ( alu_branch_res ), + .branch_result_o ( branch_result ), .branch_predict_i, .resolved_branch_o, .resolve_branch_o, + .branch_exception_o ( flu_exception_o ) + ); - .commit_i ( csr_commit_i ), - .csr_addr_o ( csr_addr_o ) + // 3. CSR (sequential) + csr_buffer csr_buffer_i ( + .clk_i, + .rst_ni, + .flush_i, + .fu_data_i, + .csr_valid_i, + .csr_ready_o ( csr_ready ), + .csr_result_o ( csr_result ), + .csr_commit_i, + .csr_addr_o ); - // ---------------- - // Multiplication - // ---------------- + assign flu_valid_o = alu_valid_i | branch_valid_i | csr_valid_i | mult_valid; + + // result MUX + always_comb begin + // Branch result as default case + flu_result_o = branch_result; + flu_trans_id_o = fu_data_i.trans_id; + // ALU result + if (alu_valid_i) begin + flu_result_o = alu_result; + // CSR result + end else if (csr_valid_i) begin + flu_result_o = csr_result; + end else if (mult_valid) begin + flu_result_o = mult_result; + flu_trans_id_o = mult_trans_id; + end + end + + // ready flags for FLU + always_comb begin + flu_ready_o = csr_ready & mult_ready; + end + + // 4. Multiplication (Sequential) fu_data_t mult_data; - assign mult_data.operator = mult_valid_i ? operator_i : MUL; - assign mult_data.operand_a = mult_valid_i ? operand_a_i : '0; - assign mult_data.operand_b = mult_valid_i ? operand_b_i : '0; + // input silencing of multiplier + assign mult_data = mult_valid_i ? fu_data_i : '0; mult i_mult ( .clk_i, .rst_ni, .flush_i, - .trans_id_i, .mult_valid_i, - .operator_i ( mult_data.operator ), - .operand_a_i ( mult_data.operand_a ), - .operand_b_i ( mult_data.operand_b ), - .result_o ( mult_result_o ), - .mult_valid_o, - .mult_ready_o, - .mult_trans_id_o + .fu_data_i ( mult_data ), + .result_o ( mult_result ), + .mult_valid_o ( mult_valid ), + .mult_ready_o ( mult_ready ), + .mult_trans_id_o ( mult_trans_id ) ); // ---------------- @@ -172,29 +215,21 @@ module ex_stage #( generate if (FP_PRESENT) begin : fpu_gen fu_data_t fpu_data; - assign fpu_data.operator = fpu_valid_i ? operator_i : FSGNJ; - assign fpu_data.operand_a = fpu_valid_i ? operand_a_i : '0; - assign fpu_data.operand_b = fpu_valid_i ? operand_b_i : '0; - assign fpu_data.imm = fpu_valid_i ? imm_i : '0; + assign fpu_data = fpu_valid_i ? fu_data_i : '0; fpu_wrap fpu_i ( .clk_i, .rst_ni, .flush_i, - .trans_id_i, - .fu_i, .fpu_valid_i, .fpu_ready_o, - .operator_i ( fpu_data.operator ), - .operand_a_i ( fpu_data.operand_a[FLEN-1:0] ), - .operand_b_i ( fpu_data.operand_b[FLEN-1:0] ), - .operand_c_i ( fpu_data.imm[FLEN-1:0] ), + .fu_data_i ( fpu_data ), .fpu_fmt_i, .fpu_rm_i, .fpu_frm_i, .fpu_prec_i, .fpu_trans_id_o, - .result_o ( fpu_result_o ), + .result_o ( fpu_result_o ), .fpu_valid_o, .fpu_exception_o ); @@ -211,47 +246,44 @@ module ex_stage #( // Load-Store Unit // ---------------- fu_data_t lsu_data; - assign lsu_data.operator = lsu_valid_i ? operator_i : LD; - assign lsu_data.operand_a = lsu_valid_i ? operand_a_i : '0; - assign lsu_data.operand_b = lsu_valid_i ? operand_b_i : '0; - assign lsu_data.imm = lsu_valid_i ? imm_i : '0; - lsu lsu_i ( - .clk_i , - .rst_ni , - .flush_i , - .no_st_pending_o , - .fu_i , - .operator_i (lsu_data.operator ), - .operand_a_i (lsu_data.operand_a ), - .operand_b_i (lsu_data.operand_b ), - .imm_i (lsu_data.imm ), - .lsu_ready_o , - .lsu_valid_i , - .trans_id_i , - .lsu_trans_id_o , - .lsu_result_o , - .lsu_valid_o , - .commit_i (lsu_commit_i ), - .commit_ready_o (lsu_commit_ready_o ), - .enable_translation_i , - .en_ld_st_translation_i , - .icache_areq_i , - .icache_areq_o , - .priv_lvl_i , - .ld_st_priv_lvl_i , - .sum_i , - .mxr_i , - .satp_ppn_i , - .asid_i , - .flush_tlb_i , - .itlb_miss_o , - .dtlb_miss_o , - .dcache_req_ports_i , - .dcache_req_ports_o , - .lsu_exception_o , - .amo_valid_commit_i , - .amo_req_o , + assign lsu_data = lsu_valid_i ? fu_data_i : '0; + + load_store_unit lsu_i ( + .clk_i, + .rst_ni, + .flush_i, + .no_st_pending_o, + .fu_data_i ( lsu_data ), + .lsu_ready_o, + .lsu_valid_i, + .load_trans_id_o, + .load_result_o, + .load_valid_o, + .load_exception_o, + .store_trans_id_o, + .store_result_o, + .store_valid_o, + .store_exception_o, + .commit_i ( lsu_commit_i ), + .commit_ready_o ( lsu_commit_ready_o ), + .enable_translation_i, + .en_ld_st_translation_i, + .icache_areq_i, + .icache_areq_o, + .priv_lvl_i, + .ld_st_priv_lvl_i, + .sum_i, + .mxr_i, + .satp_ppn_i, + .asid_i, + .flush_tlb_i, + .itlb_miss_o, + .dtlb_miss_o, + .dcache_req_ports_i, + .dcache_req_ports_o, + .amo_valid_commit_i, + .amo_req_o, .amo_resp_i ); diff --git a/src/fpga-support b/src/fpga-support index 3e925e169b..a3ba269c0f 160000 --- a/src/fpga-support +++ b/src/fpga-support @@ -1 +1 @@ -Subproject commit 3e925e169bd02ebf26e3d4ab65cd1832319cf580 +Subproject commit a3ba269c0fc6cfcee6f81e5d9af018a08e479d2b diff --git a/src/fpu b/src/fpu index 00e2579173..0d4970af8f 160000 --- a/src/fpu +++ b/src/fpu @@ -1 +1 @@ -Subproject commit 00e2579173f1412f06d4eb95d6b98d0eb1cd2e94 +Subproject commit 0d4970af8fbe35e88a6d0395c51cfb58b6d1faf9 diff --git a/src/fpu_wrap.sv b/src/fpu_wrap.sv index 0dd7684c84..0b442b9068 100644 --- a/src/fpu_wrap.sv +++ b/src/fpu_wrap.sv @@ -12,21 +12,16 @@ // Date: 12.04.2018 // Description: Wrapper for the floating-point unit - import ariane_pkg::*; module fpu_wrap ( input logic clk_i, input logic rst_ni, input logic flush_i, - input logic [TRANS_ID_BITS-1:0] trans_id_i, - input fu_t fu_i, input logic fpu_valid_i, output logic fpu_ready_o, - input fu_op operator_i, - input logic [FLEN-1:0] operand_a_i, - input logic [FLEN-1:0] operand_b_i, // imm will be here unless used as operand - input logic [FLEN-1:0] operand_c_i, // imm will be here unless used as operand + input fu_data_t fu_data_i, + input logic [1:0] fpu_fmt_i, input logic [2:0] fpu_rm_i, input logic [2:0] fpu_frm_i, @@ -41,6 +36,14 @@ module fpu_wrap ( // otherwise compilation might issue an error if FLEN=0 generate if (FP_PRESENT) begin : fpu_gen + + logic [FLEN-1:0] operand_a_i; + logic [FLEN-1:0] operand_b_i; + logic [FLEN-1:0] operand_c_i; + assign operand_a_i = fu_data_i.operand_a[FLEN-1:0]; + assign operand_b_i = fu_data_i.operand_b[FLEN-1:0]; + assign operand_c_i = fu_data_i.imm[FLEN-1:0]; + //----------------------------------- // FPnew encoding from FPnew package //----------------------------------- @@ -166,8 +169,8 @@ generate fpu_fmt2_d = FMT_FP32; fpu_ifmt_d = IFMT_INT32; fpu_rm_d = fpu_rm_i; - fpu_vec_op_d = fu_i == FPU_VEC; - fpu_tag_d = trans_id_i; + fpu_vec_op_d = fu_data_i.fu == FPU_VEC; + fpu_tag_d = fu_data_i.trans_id; vec_replication = fpu_rm_i[0]; // replication bit is sent via rm field replicate_c = 1'b0; check_ah = 1'b0; // whether set scalar AH encoding from MSB of rm_i @@ -199,7 +202,7 @@ generate // Operations (this can modify the rounding mode field and format!) - unique case (operator_i) + unique case (fu_data_i.operator) // Addition FADD : begin fpu_op_d = OP_ADD; @@ -606,5 +609,4 @@ generate end endgenerate - -endmodule \ No newline at end of file +endmodule diff --git a/src/frontend/btb.sv b/src/frontend/btb.sv index 2169ac961e..7b9396b123 100644 --- a/src/frontend/btb.sv +++ b/src/frontend/btb.sv @@ -57,8 +57,6 @@ module btb #( btb_d[update_pc].valid = 1'b1; // the target address is simply updated btb_d[update_pc].target_address = btb_update_i.target_address; - // as is the information whether this was a compressed branch - btb_d[update_pc].is_lower_16 = btb_update_i.is_lower_16; // check if we should invalidate this entry, this happens in case we predicted a branch // where actually none-is (aliasing) if (btb_update_i.clear) begin diff --git a/src/frontend/frontend.sv b/src/frontend/frontend.sv index c8877ef917..5a23eb81c1 100644 --- a/src/frontend/frontend.sv +++ b/src/frontend/frontend.sv @@ -39,22 +39,18 @@ module frontend ( input icache_dreq_o_t icache_dreq_i, output icache_dreq_i_t icache_dreq_o, // instruction output port -> to processor back-end - output fetch_entry_t fetch_entry_o, // fetch entry containing all relevant data for the ID stage + output frontend_fetch_t fetch_entry_o, // fetch entry containing all relevant data for the ID stage output logic fetch_entry_valid_o, // instruction in IF is valid input logic fetch_ack_i // ID acknowledged this instruction ); - // maximum instructions we can fetch on one request - localparam int unsigned INSTR_PER_FETCH = FETCH_WIDTH/16; - // Registers logic [31:0] icache_data_q; logic icache_valid_q; - exception_t icache_ex_q; - + logic icache_ex_valid_q; logic instruction_valid; + logic [INSTR_PER_FETCH-1:0] instr_is_compressed; logic [63:0] icache_vaddr_q; - // BHT, BTB and RAS prediction bht_prediction_t bht_prediction; btb_prediction_t btb_prediction; @@ -89,7 +85,6 @@ module frontend ( logic is_mispredict; // branch-prediction which we inject into the pipeline branchpredict_sbe_t bp_sbe; - // fetch fifo credit system logic fifo_valid, fifo_ready, fifo_empty, fifo_pop; logic s2_eff_kill, issue_req, s2_in_flight_d, s2_in_flight_q; @@ -103,36 +98,46 @@ module frontend ( // register to save the unaligned address logic [63:0] unaligned_address_d, unaligned_address_q; - // TODO: generalize to arbitrary instruction fetch width + for (genvar i = 0; i < INSTR_PER_FETCH; i ++) begin + // LSB != 2'b11 + assign instr_is_compressed[i] = ~&icache_data_q[i * 16 +: 2]; + end + + // Soft-realignment to do branch-prediction always_comb begin : re_align unaligned_d = unaligned_q; unaligned_address_d = unaligned_address_q; unaligned_instr_d = unaligned_instr_q; instruction_valid = icache_valid_q; - instr[1] = '0; + // 32-bit can contain 2 instructions instr[0] = icache_data_q; + addr[0] = icache_vaddr_q; - addr[1] = {icache_vaddr_q[63:2], 2'b10}; - addr[0] = icache_vaddr_q; + instr[1] = '0; + addr[1] = {icache_vaddr_q[63:2], 2'b10}; if (icache_valid_q) begin // last instruction was unaligned if (unaligned_q) begin instr[0] = {icache_data_q[15:0], unaligned_instr_q}; addr[0] = unaligned_address_q; + unaligned_address_d = {icache_vaddr_q[63:2], 2'b10}; unaligned_instr_d = icache_data_q[31:16]; // save the upper bits for next cycle + // check if this is instruction is still unaligned e.g.: it is not compressed // if its compressed re-set unaligned flag - if (icache_data_q[17:16] != 2'b11) begin + // for 32 bit we can simply check the next instruction and whether it is compressed or not + // if it is compressed the next fetch will contain an aligned instruction + if (instr_is_compressed[1]) begin unaligned_d = 1'b0; instr[1] = {16'b0, icache_data_q[31:16]}; end - end else if (is_rvc[0]) begin // instruction zero is RVC + end else if (instr_is_compressed[0]) begin // instruction zero is RVC // is instruction 1 also compressed // yes? -> no problem, no -> we've got an unaligned instruction - if (icache_data_q[17:16] != 2'b11) begin + if (instr_is_compressed[1]) begin instr[1] = {16'b0, icache_data_q[31:16]}; end else begin unaligned_instr_d = icache_data_q[31:16]; @@ -144,13 +149,14 @@ module frontend ( // we started to fetch on a unaligned boundary with a whole instruction -> wait until we've // received the next instruction - if (icache_valid_q && icache_vaddr_q[1] && icache_data_q[17:16] == 2'b11) begin + if (icache_valid_q && icache_vaddr_q[1] && !instr_is_compressed[1]) begin instruction_valid = 1'b0; unaligned_d = 1'b1; unaligned_address_d = {icache_vaddr_q[63:2], 2'b10}; unaligned_instr_d = icache_data_q[31:16]; end + // if we killed the consecutive fetch we are starting on a clean slate if (icache_dreq_o.kill_s2) begin unaligned_d = 1'b0; end @@ -178,7 +184,7 @@ module frontend ( // only predict if the response is valid if (instruction_valid) begin - // look at instruction 0, 1, 2,... + // look at instruction 0, 1, 2, ... for (int unsigned i = 0; i < INSTR_PER_FETCH; i++) begin // only speculate if the previous instruction was not taken if (!taken[i]) begin @@ -237,6 +243,7 @@ module frontend ( // we are not interested in the lower instruction if (icache_vaddr_q[1]) begin taken[1] = 1'b0; + // TODO(zarubaf): that seems to be overly pessimistic ras_pop = 1'b0; ras_push = 1'b0; end @@ -249,29 +256,14 @@ module frontend ( bp_sbe.valid = bp_valid; bp_sbe.predict_address = bp_vaddr; bp_sbe.predict_taken = bp_valid; - bp_sbe.is_lower_16 = taken[1]; // the branch is on the lower 16 (in a 32-bit setup) - end assign is_mispredict = resolved_branch_i.valid & resolved_branch_i.is_mispredict; - - always_comb begin : id_if - icache_dreq_o.kill_s1 = 1'b0; - icache_dreq_o.kill_s2 = 1'b0; - - // we mis-predicted so kill the icache request and the fetch queue - if (is_mispredict || flush_i) begin - icache_dreq_o.kill_s1 = 1'b1; - icache_dreq_o.kill_s2 = 1'b1; - end - - // if we have a valid branch-prediction we need to kill the last cache request - if (bp_valid) begin - icache_dreq_o.kill_s2 = 1'b1; - end - - fifo_valid = icache_valid_q; - end + // we mis-predicted so kill the icache request and the fetch queue + assign icache_dreq_o.kill_s1 = is_mispredict | flush_i; + // if we have a valid branch-prediction we need to kill the last cache request + assign icache_dreq_o.kill_s2 = icache_dreq_o.kill_s1 | bp_valid; + assign fifo_valid = icache_valid_q; // ---------------------------------------- // Update Control Flow Predictions @@ -285,7 +277,6 @@ module frontend ( assign btb_update.valid = resolved_branch_i.valid & (resolved_branch_i.cf_type == BTB); assign btb_update.pc = resolved_branch_i.pc; assign btb_update.target_address = resolved_branch_i.target_address; - assign btb_update.is_lower_16 = resolved_branch_i.is_lower_16; assign btb_update.clear = resolved_branch_i.clear; // ------------------- @@ -329,7 +320,7 @@ module frontend ( // 0. Default assignment // ------------------------------- if (if_ready) begin - npc_d = {fetch_address[63:2], 2'b0} + 64'h4; + npc_d = {fetch_address[63:2], 2'b0} + 'h4; end // ------------------------------- // 2. Control flow change request @@ -394,14 +385,15 @@ module frontend ( assign icache_dreq_o.req = fifo_ready; assign fetch_entry_valid_o = ~fifo_empty; + //pragma translate_off `ifndef VERILATOR fetch_fifo_credits0 : assert property ( @(posedge clk_i) disable iff (~rst_ni) (fifo_credits_q <= FETCH_FIFO_DEPTH)) - else $fatal("[frontend] fetch fifo credits must be <= FETCH_FIFO_DEPTH!"); + else $fatal(1,"[frontend] fetch fifo credits must be <= FETCH_FIFO_DEPTH!"); initial begin - assert (FETCH_FIFO_DEPTH<=8) else $fatal("[frontend] fetch fifo deeper than 8 not supported"); - assert (FETCH_WIDTH==32) else $fatal("[frontend] fetch width != not supported"); + assert (FETCH_FIFO_DEPTH <= 8) else $fatal(1,"[frontend] fetch fifo deeper than 8 not supported"); + assert (FETCH_WIDTH == 32) else $fatal(1,"[frontend] fetch width != not supported"); end `endif //pragma translate_on @@ -413,7 +405,7 @@ module frontend ( icache_data_q <= '0; icache_valid_q <= 1'b0; icache_vaddr_q <= 'b0; - icache_ex_q <= '0; + icache_ex_valid_q <= 1'b0; unaligned_q <= 1'b0; unaligned_address_q <= '0; unaligned_instr_q <= '0; @@ -425,7 +417,7 @@ module frontend ( icache_data_q <= icache_dreq_i.data; icache_valid_q <= icache_dreq_i.valid; icache_vaddr_q <= icache_dreq_i.vaddr; - icache_ex_q <= icache_dreq_i.ex; + icache_ex_valid_q <= icache_dreq_i.ex.valid; unaligned_q <= unaligned_d; unaligned_address_q <= unaligned_address_d; unaligned_instr_q <= unaligned_instr_d; @@ -488,10 +480,11 @@ module frontend ( ); end + fifo_v2 #( .DEPTH ( 8 ), - .dtype ( fetch_entry_t )) - i_fetch_fifo ( + .dtype ( frontend_fetch_t ) + ) i_fetch_fifo ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .flush_i ( flush_i ), @@ -500,7 +493,7 @@ module frontend ( .empty_o ( fifo_empty ), .alm_full_o ( ), .alm_empty_o ( ), - .data_i ( {icache_vaddr_q, icache_data_q, bp_sbe, icache_ex_q} ), + .data_i ( {icache_vaddr_q, icache_data_q, bp_sbe, taken[INSTR_PER_FETCH:1], icache_ex_valid_q} ), .push_i ( fifo_valid ), .data_o ( fetch_entry_o ), .pop_i ( fifo_pop ) diff --git a/src/id_stage.sv b/src/id_stage.sv index 46b248c60e..cef80f1aa8 100644 --- a/src/id_stage.sv +++ b/src/id_stage.sv @@ -21,7 +21,7 @@ module id_stage ( input logic flush_i, // from IF - input fetch_entry_t fetch_entry_i, + input frontend_fetch_t fetch_entry_i, input logic fetch_entry_valid_i, output logic decoded_instr_ack_o, // acknowledge the instruction (fetch entry) @@ -45,7 +45,6 @@ module id_stage ( logic valid; scoreboard_entry_t sbe; logic is_ctrl_flow; - } issue_n, issue_q; logic is_control_flow_instr; @@ -62,9 +61,9 @@ module id_stage ( // 1. Re-align instructions // --------------------------------------------------------- instr_realigner instr_realigner_i ( - .fetch_entry_0_i ( fetch_entry_i ), - .fetch_entry_valid_0_i ( fetch_entry_valid_i ), - .fetch_ack_0_o ( decoded_instr_ack_o ), + .fetch_entry_i ( fetch_entry_i ), + .fetch_entry_valid_i ( fetch_entry_valid_i ), + .fetch_ack_o ( decoded_instr_ack_o ), .fetch_entry_o ( fetch_entry ), .fetch_entry_valid_o ( fetch_entry_valid ), @@ -85,14 +84,15 @@ module id_stage ( // 3. Decode and emit instruction to issue stage // --------------------------------------------------------- decoder decoder_i ( - .pc_i ( fetch_entry.address ), - .is_compressed_i ( is_compressed ), - .instruction_i ( instruction ), - .branch_predict_i ( fetch_entry.branch_predict ), - .is_illegal_i ( is_illegal ), - .ex_i ( fetch_entry.ex ), - .instruction_o ( decoded_instruction ), - .is_control_flow_instr_o ( is_control_flow_instr ), + .pc_i ( fetch_entry.address ), + .is_compressed_i ( is_compressed ), + .compressed_instr_i ( fetch_entry.instruction[15:0] ), + .instruction_i ( instruction ), + .branch_predict_i ( fetch_entry.branch_predict ), + .is_illegal_i ( is_illegal ), + .ex_i ( fetch_entry.ex ), + .instruction_o ( decoded_instruction ), + .is_control_flow_instr_o ( is_control_flow_instr ), .fs_i, .frm_i, .* diff --git a/src/instr_realigner.sv b/src/instr_realigner.sv index 44be48f511..9b5557fd7b 100644 --- a/src/instr_realigner.sv +++ b/src/instr_realigner.sv @@ -20,9 +20,9 @@ module instr_realigner ( // control signals input logic flush_i, - input fetch_entry_t fetch_entry_0_i, - input logic fetch_entry_valid_0_i, - output logic fetch_ack_0_o, + input frontend_fetch_t fetch_entry_i, + input logic fetch_entry_valid_i, + output logic fetch_ack_o, output fetch_entry_t fetch_entry_o, output logic fetch_entry_valid_o, @@ -45,9 +45,9 @@ module instr_realigner ( // check if the lower compressed instruction was no branch otherwise we will need to squash this instruction // but only if we predicted it to be taken, the predict was on the lower 16 bit compressed instruction logic kill_upper_16_bit; - assign kill_upper_16_bit = fetch_entry_0_i.branch_predict.valid & - fetch_entry_0_i.branch_predict.predict_taken & - fetch_entry_0_i.branch_predict.is_lower_16; + assign kill_upper_16_bit = fetch_entry_i.branch_predict.valid & + fetch_entry_i.branch_predict.predict_taken & + fetch_entry_i.bp_taken[0]; // ---------- // Registers // ---------- @@ -58,10 +58,16 @@ module instr_realigner ( compressed_n = compressed_q; unaligned_address_n = unaligned_address_q; - // directly output this instruction. adoptions are made throughout the process - fetch_entry_o = fetch_entry_0_i; - fetch_entry_valid_o = fetch_entry_valid_0_i; - fetch_ack_0_o = fetch_ack_i; + // directly output this instruction. adoptions are made throughout the always comb block + fetch_entry_o.address = fetch_entry_i.address; + fetch_entry_o.instruction = fetch_entry_i.instruction; + fetch_entry_o.branch_predict = fetch_entry_i.branch_predict; + fetch_entry_o.ex.valid = fetch_entry_i.page_fault; + fetch_entry_o.ex.tval = (fetch_entry_i.page_fault) ? fetch_entry_i.address : '0; + fetch_entry_o.ex.cause = (fetch_entry_i.page_fault) ? riscv::INSTR_PAGE_FAULT : '0; + + fetch_entry_valid_o = fetch_entry_valid_i; + fetch_ack_o = fetch_ack_i; // we just jumped to a half word and encountered an unaligned 32-bit instruction jump_unaligned_half_word = 1'b0; // --------------------------------- @@ -69,21 +75,21 @@ module instr_realigner ( // --------------------------------- // check if the entry if the fetch FIFO is valid and if we are currently not serving the second part // of a compressed instruction - if (fetch_entry_valid_0_i && !compressed_q) begin + if (fetch_entry_valid_i && !compressed_q) begin // ------------------------ // Access on Word Boundary // ------------------------ - if (fetch_entry_0_i.address[1] == 1'b0) begin + if (fetch_entry_i.address[1] == 1'b0) begin // do we actually want the first instruction or was the address a half word access? if (!unaligned_q) begin // we got a valid instruction so we can satisfy the unaligned instruction unaligned_n = 1'b0; // check if the instruction is compressed - if (fetch_entry_0_i.instruction[1:0] != 2'b11) begin + if (fetch_entry_i.instruction[1:0] != 2'b11) begin // it is compressed - fetch_entry_o.instruction = {15'b0, fetch_entry_0_i.instruction[15:0]}; + fetch_entry_o.instruction = {15'b0, fetch_entry_i.instruction[15:0]}; // we need to kill the lower prediction - if (fetch_entry_0_i.branch_predict.valid && !fetch_entry_0_i.branch_predict.is_lower_16) + if (fetch_entry_i.branch_predict.valid && !fetch_entry_i.bp_taken[0]) fetch_entry_o.branch_predict.valid = 1'b0; // should we even look at the upper instruction bits? @@ -93,20 +99,20 @@ module instr_realigner ( // _____________________________________________ // | compressed 2 [31:16] | compressed 1[15:0] | // |____________________________________________ - if (fetch_entry_0_i.instruction[17:16] != 2'b11) begin + if (fetch_entry_i.instruction[17:16] != 2'b11) begin // yes, this was a compressed instruction compressed_n = 1'b1; // do not advance the queue pointer - fetch_ack_0_o = 1'b0; + fetch_ack_o = 1'b0; // 2. or is it an unaligned 32 bit instruction like // ____________________________________________________ // |instr [15:0] | instr [31:16] | compressed 1[15:0] | // |____________________________________________________ end else begin // save the lower 16 bit - unaligned_instr_n = fetch_entry_0_i.instruction[31:16]; + unaligned_instr_n = fetch_entry_i.instruction[31:16]; // save the address - unaligned_address_n = {fetch_entry_0_i.address[63:2], 2'b10}; + unaligned_address_n = {fetch_entry_i.address[63:2], 2'b10}; // and that it was unaligned unaligned_n = 1'b1; // this does not consume space in the FIFO @@ -124,7 +130,7 @@ module instr_realigner ( fetch_entry_o.address = unaligned_address_q; - fetch_entry_o.instruction = {fetch_entry_0_i.instruction[15:0], unaligned_instr_q}; + fetch_entry_o.instruction = {fetch_entry_i.instruction[15:0], unaligned_instr_q}; // again should we look at the upper bits? if (!kill_upper_16_bit) begin @@ -135,15 +141,15 @@ module instr_realigner ( // |____________________________________________ // check if the lower compressed instruction was no branch otherwise we will need to squash this instruction // but only if we predicted it to be taken, the predict was on the lower 16 bit compressed instruction - if (fetch_entry_0_i.instruction[17:16] != 2'b11) begin + if (fetch_entry_i.instruction[17:16] != 2'b11) begin // this was a compressed instruction compressed_n = 1'b1; // do not advance the queue pointer - fetch_ack_0_o = 1'b0; + fetch_ack_o = 1'b0; // unaligned access served unaligned_n = 1'b0; // we need to kill the lower prediction - if (fetch_entry_0_i.branch_predict.valid && !fetch_entry_0_i.branch_predict.is_lower_16) + if (fetch_entry_i.branch_predict.valid && !fetch_entry_i.bp_taken[0]) fetch_entry_o.branch_predict.valid = 1'b0; // or is it an unaligned 32 bit instruction like // ____________________________________________________ @@ -151,15 +157,15 @@ module instr_realigner ( // |____________________________________________________ end else if (!kill_upper_16_bit) begin // save the lower 16 bit - unaligned_instr_n = fetch_entry_0_i.instruction[31:16]; + unaligned_instr_n = fetch_entry_i.instruction[31:16]; // save the address - unaligned_address_n = {fetch_entry_0_i.address[63:2], 2'b10}; + unaligned_address_n = {fetch_entry_i.address[63:2], 2'b10}; // and that it was unaligned unaligned_n = 1'b1; end end // we've got a predicted taken branch we need to clear the unaligned flag if it was decoded as a lower 16 instruction - else if (fetch_entry_0_i.branch_predict.valid) begin + else if (fetch_entry_i.branch_predict.valid) begin // the next fetch will start from a 4 byte boundary again unaligned_n = 1'b0; end @@ -168,26 +174,26 @@ module instr_realigner ( // ---------------------------- // Access on half-Word Boundary // ---------------------------- - else if (fetch_entry_0_i.address[1] == 1'b1) begin // address was a half word access + else if (fetch_entry_i.address[1] == 1'b1) begin // address was a half word access // reset the unaligned flag as this is a completely new fetch (because consecutive fetches only happen on a word basis) unaligned_n = 1'b0; // this is a compressed instruction - if (fetch_entry_0_i.instruction[17:16] != 2'b11) begin + if (fetch_entry_i.instruction[17:16] != 2'b11) begin // it is compressed - fetch_entry_o.instruction = {15'b0, fetch_entry_0_i.instruction[31:16]}; + fetch_entry_o.instruction = {15'b0, fetch_entry_i.instruction[31:16]}; // this is the first part of a 32 bit unaligned instruction end else begin // save the lower 16 bit - unaligned_instr_n = fetch_entry_0_i.instruction[31:16]; + unaligned_instr_n = fetch_entry_i.instruction[31:16]; // and that it was unaligned unaligned_n = 1'b1; // save the address - unaligned_address_n = {fetch_entry_0_i.address[63:2], 2'b10}; + unaligned_address_n = {fetch_entry_i.address[63:2], 2'b10}; // we need to wait for the second instruction fetch_entry_valid_o = 1'b0; // so get it by acknowledging this instruction - fetch_ack_0_o = 1'b1; + fetch_ack_o = 1'b1; // we got to an unaligned instruction -> get the next entry to full-fill the need jump_unaligned_half_word = 1'b1; end @@ -199,10 +205,10 @@ module instr_realigner ( // ---------------------------- // we are serving the second part of an instruction which was also compressed if (compressed_q) begin - fetch_ack_0_o = fetch_ack_i; + fetch_ack_o = fetch_ack_i; compressed_n = 1'b0; - fetch_entry_o.instruction = {16'b0, fetch_entry_0_i.instruction[31:16]}; - fetch_entry_o.address = {fetch_entry_0_i.address[63:2], 2'b10}; + fetch_entry_o.instruction = {16'b0, fetch_entry_i.instruction[31:16]}; + fetch_entry_o.address = {fetch_entry_i.address[63:2], 2'b10}; fetch_entry_valid_o = 1'b1; end diff --git a/src/issue_read_operands.sv b/src/issue_read_operands.sv index 492e2b3057..7fff6a1f76 100644 --- a/src/issue_read_operands.sv +++ b/src/issue_read_operands.sv @@ -40,16 +40,11 @@ module issue_read_operands #( input fu_t [2**REG_ADDR_SIZE:0] rd_clobber_gpr_i, input fu_t [2**REG_ADDR_SIZE:0] rd_clobber_fpr_i, // To FU, just single issue for now - output fu_t fu_o, - output fu_op operator_o, - output logic [63:0] operand_a_o, - output logic [63:0] operand_b_o, - output logic [63:0] imm_o, // output immediate for the LSU - output logic [TRANS_ID_BITS-1:0] trans_id_o, + output fu_data_t fu_data_o, output logic [63:0] pc_o, output logic is_compressed_instr_o, // ALU 1 - input logic alu_ready_i, // FU is ready + input logic flu_ready_i, // Fixed latency unit ready to accept a new request output logic alu_valid_o, // Output is valid // Branches and Jumps output logic branch_valid_o, // this is a valid branch instruction @@ -58,7 +53,6 @@ module issue_read_operands #( input logic lsu_ready_i, // FU is ready output logic lsu_valid_o, // Output is valid // MULT - input logic mult_ready_i, // FU is ready output logic mult_valid_o, // Output is valid // FPU input logic fpu_ready_i, // FU is ready @@ -81,7 +75,6 @@ module issue_read_operands #( logic fu_busy; // functional unit is busy logic [63:0] operand_a_regfile, operand_b_regfile; // operands coming from regfile logic [FLEN-1:0] operand_c_regfile; // third operand only from fp regfile - // output flipflop (ID <-> EX) logic [63:0] operand_a_n, operand_a_q, operand_b_n, operand_b_q, @@ -108,20 +101,20 @@ module issue_read_operands #( assign orig_instr = riscv::instruction_t'(issue_instr_i.ex.tval[31:0]); // ID <-> EX registers - assign operand_a_o = operand_a_q; - assign operand_b_o = operand_b_q; - assign fu_o = fu_q; - assign operator_o = operator_q; - assign alu_valid_o = alu_valid_q; - assign branch_valid_o = branch_valid_q; - assign lsu_valid_o = lsu_valid_q; - assign csr_valid_o = csr_valid_q; - assign mult_valid_o = mult_valid_q; - assign fpu_valid_o = fpu_valid_q; - assign fpu_fmt_o = fpu_fmt_q; - assign fpu_rm_o = fpu_rm_q; - assign trans_id_o = trans_id_q; - assign imm_o = imm_q; + assign fu_data_o.operand_a = operand_a_q; + assign fu_data_o.operand_b = operand_b_q; + assign fu_data_o.fu = fu_q; + assign fu_data_o.operator = operator_q; + assign fu_data_o.trans_id = trans_id_q; + assign fu_data_o.imm = imm_q; + assign alu_valid_o = alu_valid_q; + assign branch_valid_o = branch_valid_q; + assign lsu_valid_o = lsu_valid_q; + assign csr_valid_o = csr_valid_q; + assign mult_valid_o = mult_valid_q; + assign fpu_valid_o = fpu_valid_q; + assign fpu_fmt_o = fpu_fmt_q; + assign fpu_rm_o = fpu_rm_q; // --------------- // Issue Stage // --------------- @@ -132,10 +125,8 @@ module issue_read_operands #( unique case (issue_instr_i.fu) NONE: fu_busy = 1'b0; - ALU, CTRL_FLOW, CSR: - fu_busy = ~alu_ready_i; - MULT: - fu_busy = ~mult_ready_i; + ALU, CTRL_FLOW, CSR, MULT: + fu_busy = ~flu_ready_i; FPU, FPU_VEC: fu_busy = ~fpu_ready_i; LOAD, STORE: @@ -170,27 +161,30 @@ module issue_read_operands #( // check if the clobbering instruction is not a CSR instruction, CSR instructions can only // be fetched through the register file since they can't be forwarded // if the operand is available, forward it. CSRs don't write to/from FPR - if (rs1_valid_i && (is_rs1_fpr(issue_instr_i.op) ? 1'b1 : rd_clobber_gpr_i[issue_instr_i.rs1] != CSR)) + if (rs1_valid_i && (is_rs1_fpr(issue_instr_i.op) ? 1'b1 : rd_clobber_gpr_i[issue_instr_i.rs1] != CSR)) begin forward_rs1 = 1'b1; - else // the operand is not available -> stall + end else begin // the operand is not available -> stall stall = 1'b1; + end end if (is_rs2_fpr(issue_instr_i.op) ? rd_clobber_fpr_i[issue_instr_i.rs2] != NONE : rd_clobber_gpr_i[issue_instr_i.rs2] != NONE) begin // if the operand is available, forward it. CSRs don't write to/from FPR - if (rs2_valid_i && (is_rs2_fpr(issue_instr_i.op) ? 1'b1 : rd_clobber_gpr_i[issue_instr_i.rs2] != CSR)) + if (rs2_valid_i && (is_rs2_fpr(issue_instr_i.op) ? 1'b1 : rd_clobber_gpr_i[issue_instr_i.rs2] != CSR)) begin forward_rs2 = 1'b1; - else // the operand is not available -> stall + end else begin // the operand is not available -> stall stall = 1'b1; + end end if (is_imm_fpr(issue_instr_i.op) && rd_clobber_fpr_i[issue_instr_i.result[REG_ADDR_SIZE-1:0]] != NONE) begin // if the operand is available, forward it. CSRs don't write to/from FPR so no need to check - if (rs3_valid_i) + if (rs3_valid_i) begin forward_rs3 = 1'b1; - else // the operand is not available -> stall + end else begin // the operand is not available -> stall stall = 1'b1; + end end end @@ -325,6 +319,11 @@ module issue_read_operands #( issue_ack_o = 1'b1; end end + // after a multiplication was issued we can only issue another multiplication + // otherwise we will get contentions on the fixed latency bus + if (mult_valid_q && issue_instr_i.fu != MULT) begin + issue_ack_o = 1'b0; + end end // ---------------------- @@ -437,8 +436,8 @@ module issue_read_operands #( end end - `ifndef SYNTHESIS - `ifndef verilator + //pragma translate_off + `ifndef VERILATOR assert property ( @(posedge clk_i) (branch_valid_q) |-> (!$isunknown(operand_a_q) && !$isunknown(operand_b_q))) else $warning ("Got unknown value in one of the operands"); @@ -447,7 +446,7 @@ module issue_read_operands #( assert (NR_COMMIT_PORTS == 2) else $error("Only two commit ports are supported at the moment!"); end `endif - `endif + //pragma translate_on endmodule diff --git a/src/issue_stage.sv b/src/issue_stage.sv index 1cc08afc4a..8e4ade577f 100644 --- a/src/issue_stage.sv +++ b/src/issue_stage.sv @@ -23,6 +23,7 @@ module issue_stage #( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low + output logic sb_full_o, input logic flush_unissued_instr_i, input logic flush_i, // from ISSUE @@ -31,16 +32,10 @@ module issue_stage #( input logic is_ctrl_flow_i, output logic decoded_instr_ack_o, // to EX - output fu_t fu_o, - output fu_op operator_o, - output logic [63:0] operand_a_o, - output logic [63:0] operand_b_o, - output logic [63:0] imm_o, - output logic [TRANS_ID_BITS-1:0] trans_id_o, + output fu_data_t fu_data_o, output logic [63:0] pc_o, output logic is_compressed_instr_o, - - input logic alu_ready_i, + input logic flu_ready_i, output logic alu_valid_o, // ex just resolved our predicted branch, we are ready to accept new requests input logic resolve_branch_i, @@ -49,10 +44,9 @@ module issue_stage #( output logic lsu_valid_o, // branch prediction output logic branch_valid_o, // use branch prediction unit - output branchpredict_sbe_t branch_predict_o, + output branchpredict_sbe_t branch_predict_o, // Branch predict Out - input logic mult_ready_i, - output logic mult_valid_o, // Branch predict Out + output logic mult_valid_o, input logic fpu_ready_i, output logic fpu_valid_o, @@ -126,6 +120,7 @@ module issue_stage #( .NR_ENTRIES (NR_ENTRIES ), .NR_WB_PORTS(NR_WB_PORTS) ) i_scoreboard ( + .sb_full_o ( sb_full_o ), .unresolved_branch_i ( 1'b0 ), .rd_clobber_gpr_o ( rd_clobber_gpr_sb_iro ), .rd_clobber_fpr_o ( rd_clobber_fpr_sb_iro ), @@ -161,6 +156,8 @@ module issue_stage #( .issue_instr_i ( issue_instr_sb_iro ), .issue_instr_valid_i ( issue_instr_valid_sb_iro ), .issue_ack_o ( issue_ack_iro_sb ), + .fu_data_o ( fu_data_o ), + .flu_ready_i ( flu_ready_i ), .rs1_o ( rs1_iro_sb ), .rs1_i ( rs1_sb_iro ), .rs1_valid_i ( rs1_valid_sb_iro ), @@ -172,6 +169,10 @@ module issue_stage #( .rs3_valid_i ( rs3_valid_iro_sb ), .rd_clobber_gpr_i ( rd_clobber_gpr_sb_iro ), .rd_clobber_fpr_i ( rd_clobber_fpr_sb_iro ), + .alu_valid_o ( alu_valid_o ), + .branch_valid_o ( branch_valid_o ), + .csr_valid_o ( csr_valid_o ), + .mult_valid_o ( mult_valid_o ), .* ); diff --git a/src/lsu.sv b/src/load_store_unit.sv similarity index 87% rename from src/lsu.sv rename to src/load_store_unit.sv index 1f668ff873..5f475b62ab 100644 --- a/src/lsu.sv +++ b/src/load_store_unit.sv @@ -14,7 +14,7 @@ import ariane_pkg::*; -module lsu #( +module load_store_unit #( parameter int unsigned ASID_WIDTH = 1 )( input logic clk_i, @@ -23,17 +23,20 @@ module lsu #( output logic no_st_pending_o, input logic amo_valid_commit_i, - input fu_t fu_i, - input fu_op operator_i, - input logic [63:0] operand_a_i, - input logic [63:0] operand_b_i, - input logic [63:0] imm_i, + input fu_data_t fu_data_i, output logic lsu_ready_o, // FU is ready e.g. not busy input logic lsu_valid_i, // Input is valid - input logic [TRANS_ID_BITS-1:0] trans_id_i, // transaction id, needed for WB - output logic [TRANS_ID_BITS-1:0] lsu_trans_id_o, // ID of scoreboard entry at which to write back - output logic [63:0] lsu_result_o, - output logic lsu_valid_o, // transaction id for which the output is the requested one + + output logic [TRANS_ID_BITS-1:0] load_trans_id_o, // ID of scoreboard entry at which to write back + output logic [63:0] load_result_o, + output logic load_valid_o, + output exception_t load_exception_o, // to WB, signal exception status LD exception + + output logic [TRANS_ID_BITS-1:0] store_trans_id_o, // ID of scoreboard entry at which to write back + output logic [63:0] store_result_o, + output logic store_valid_o, + output exception_t store_exception_o, // to WB, signal exception status ST exception + input logic commit_i, // commit the pending store output logic commit_ready_o, // commit queue is ready to accept another commit request @@ -60,9 +63,7 @@ module lsu #( output dcache_req_i_t [2:0] dcache_req_ports_o, // AMO interface output amo_req_t amo_req_o, - input amo_resp_t amo_resp_i, - output exception_t lsu_exception_o // to WB, signal exception status LD/ST exception - + input amo_resp_t amo_resp_i ); // data is misaligned logic data_misaligned; @@ -83,7 +84,7 @@ module lsu #( logic [63:0] vaddr_i; logic [7:0] be_i; - assign vaddr_i = $unsigned($signed(imm_i) + $signed(operand_a_i)); + assign vaddr_i = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a)); logic st_valid_i; logic ld_valid_i; @@ -201,27 +202,27 @@ module lsu #( .* ); - // --------------------- - // Result Sequentialize - // --------------------- - lsu_arbiter i_lsu_arbiter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( flush_i ), - .ld_valid_i ( ld_valid ), - .ld_trans_id_i ( ld_trans_id ), - .ld_result_i ( ld_result ), - .ld_ex_i ( ld_ex ), - - .st_valid_i ( st_valid ), - .st_trans_id_i ( st_trans_id ), - .st_result_i ( st_result ), - .st_ex_i ( st_ex ), - - .valid_o ( lsu_valid_o ), - .trans_id_o ( lsu_trans_id_o ), - .result_o ( lsu_result_o ), - .ex_o ( lsu_exception_o ) + // ---------------------------- + // Output Pipeline Register + // ---------------------------- + pipe_reg_simple #( + .dtype ( logic[$bits(ld_valid) + $bits(ld_trans_id) + $bits(ld_result) + $bits(ld_ex) - 1: 0]), + .Depth ( NR_LOAD_PIPE_REGS ) + ) i_pipe_reg_load ( + .clk_i, + .rst_ni, + .d_i ( {ld_valid, ld_trans_id, ld_result, ld_ex} ), + .d_o ( {load_valid_o, load_trans_id_o, load_result_o, load_exception_o} ) + ); + + pipe_reg_simple #( + .dtype ( logic[$bits(st_valid) + $bits(st_trans_id) + $bits(st_result) + $bits(st_ex) - 1: 0]), + .Depth ( NR_STORE_PIPE_REGS ) + ) i_pipe_reg_store ( + .clk_i, + .rst_ni, + .d_i ( {st_valid, st_trans_id, st_result, st_ex} ), + .d_o ( {store_valid_o, store_trans_id_o, store_result_o, store_exception_o} ) ); // determine whether this is a load or store @@ -259,7 +260,7 @@ module lsu #( // we can generate the byte enable from the virtual address since the last // 12 bit are the same anyway // and we can always generate the byte enable from the address at hand - assign be_i = be_gen(vaddr_i[2:0], extract_transfer_size(operator_i)); + assign be_i = be_gen(vaddr_i[2:0], extract_transfer_size(fu_data_i.operator)); // ------------------------ // Misaligned Exception @@ -328,19 +329,19 @@ module lsu #( end end - // check that all bits in the address >= 39 are equal - if (!((&lsu_ctrl.vaddr[63:39]) == 1'b1 || (|lsu_ctrl.vaddr[63:39]) == 1'b0)) begin + // we work with SV39, so if VM is enabled, check that all bits [63:38] are equal + if (en_ld_st_translation_i && !((&lsu_ctrl.vaddr[63:38]) == 1'b1 || (|lsu_ctrl.vaddr[63:38]) == 1'b0)) begin if (lsu_ctrl.fu == LOAD) begin misaligned_exception = { - riscv::LOAD_PAGE_FAULT, + riscv::LD_ACCESS_FAULT, lsu_ctrl.vaddr, 1'b1 }; end else if (lsu_ctrl.fu == STORE) begin misaligned_exception = { - riscv::STORE_PAGE_FAULT, + riscv::ST_ACCESS_FAULT, lsu_ctrl.vaddr, 1'b1 }; @@ -354,7 +355,7 @@ module lsu #( // new data arrives here lsu_ctrl_t lsu_req_i; - assign lsu_req_i = {lsu_valid_i, vaddr_i, operand_b_i, be_i, fu_i, operator_i, trans_id_i}; + assign lsu_req_i = {lsu_valid_i, vaddr_i, fu_data_i.operand_b, be_i, fu_data_i.fu, fu_data_i.operator, fu_data_i.trans_id}; lsu_bypass lsu_bypass_i ( .lsu_req_i ( lsu_req_i ), diff --git a/src/load_unit.sv b/src/load_unit.sv index 39437fe682..a6761edb9d 100644 --- a/src/load_unit.sv +++ b/src/load_unit.sv @@ -63,9 +63,11 @@ module load_unit ( assign in_data = {lsu_ctrl_i.trans_id, lsu_ctrl_i.vaddr[2:0], lsu_ctrl_i.operator}; // output address // we can now output the lower 12 bit as the index to the cache - assign req_port_o.address_index = lsu_ctrl_i.vaddr[11:0]; + assign req_port_o.address_index = lsu_ctrl_i.vaddr[ariane_pkg::DCACHE_INDEX_WIDTH-1:0]; // translation from last cycle, again: control is handled in the FSM - assign req_port_o.address_tag = paddr_i[55:12]; + assign req_port_o.address_tag = paddr_i[ariane_pkg::DCACHE_TAG_WIDTH + + ariane_pkg::DCACHE_INDEX_WIDTH-1 : + ariane_pkg::DCACHE_INDEX_WIDTH]; // directly output an exception assign ex_o = ex_i; @@ -341,17 +343,20 @@ module load_unit ( end // end result mux fast -`ifndef SYNTHESIS +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + +//pragma translate_off `ifndef VERILATOR // check invalid offsets - assert property (@(posedge clk_i) disable iff (~rst_ni) - (load_data_q.operator inside {LW, LWU}) |-> load_data_q.address_offset < 5) else $fatal ("invalid address offset used with {LW, LWU}"); - assert property (@(posedge clk_i) disable iff (~rst_ni) - (load_data_q.operator inside {LH, LHU}) |-> load_data_q.address_offset < 7) else $fatal ("invalid address offset used with {LH, LHU}"); - assert property (@(posedge clk_i) disable iff (~rst_ni) - (load_data_q.operator inside {LB, LBU}) |-> load_data_q.address_offset < 8) else $fatal ("invalid address offset used with {LB, LBU}"); -`endif + addr_offset0: assert property (@(posedge clk_i) disable iff (~rst_ni) + valid_o |-> (load_data_q.operator inside {LW, LWU}) |-> load_data_q.address_offset < 5) else $fatal (1,"invalid address offset used with {LW, LWU}"); + addr_offset1: assert property (@(posedge clk_i) disable iff (~rst_ni) + valid_o |-> (load_data_q.operator inside {LH, LHU}) |-> load_data_q.address_offset < 7) else $fatal (1,"invalid address offset used with {LH, LHU}"); + addr_offset2: assert property (@(posedge clk_i) disable iff (~rst_ni) + valid_o |-> (load_data_q.operator inside {LB, LBU}) |-> load_data_q.address_offset < 8) else $fatal (1,"invalid address offset used with {LB, LBU}"); `endif - +//pragma translate_on endmodule diff --git a/src/lsu_arbiter.sv b/src/lsu_arbiter.sv deleted file mode 100644 index 7dafa14669..0000000000 --- a/src/lsu_arbiter.sv +++ /dev/null @@ -1,134 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Author: Florian Zaruba , ETH Zurich -// Michael Schaffner , ETH Zurich -// Date: 15.08.2018 -// Description: Arbitrates the LSU result port - -import ariane_pkg::*; - -module lsu_arbiter ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic flush_i, - // Load Port - input logic ld_valid_i, - input logic [TRANS_ID_BITS-1:0] ld_trans_id_i, - input logic [63:0] ld_result_i, - input exception_t ld_ex_i, - // Store Port - input logic st_valid_i, - input logic [TRANS_ID_BITS-1:0] st_trans_id_i, - input logic [63:0] st_result_i, - input exception_t st_ex_i, - // Output Port - output logic valid_o, - output logic [TRANS_ID_BITS-1:0] trans_id_o, - output logic [63:0] result_o, - output exception_t ex_o -); - - // the two fifos are used to buffer results from ld and st paths, and arbits between these results in - // RR fashion. FIFOs need to be 2 deep in order to unconditionally accept loads and stores since we can - // have a maximum of 2 outstanding loads. - // if there are valid elements in the fifos, the unit posts the result on its output ports and expects it - // to be consumed unconditionally - - // Important: this needs to be greater than 2 to unconditionally acept incoming requests - localparam int DEPTH = 4; - - typedef struct packed { - logic [TRANS_ID_BITS-1:0] trans_id; - logic [63:0] result; - exception_t ex; - } fifo_t; - - fifo_t st_in, st_out, ld_in, ld_out; - - logic ld_full, ld_empty, ld_ren; - logic st_full, st_empty, st_ren; - logic idx; - - assign st_in.trans_id = st_trans_id_i; - assign st_in.result = st_result_i; - assign st_in.ex = st_ex_i; - - assign ld_in.trans_id = ld_trans_id_i; - assign ld_in.result = ld_result_i; - assign ld_in.ex = ld_ex_i; - - assign trans_id_o = (idx) ? st_out.trans_id : ld_out.trans_id; - assign result_o = (idx) ? st_out.result : ld_out.result; - assign ex_o = (idx) ? st_out.ex : ld_out.ex; - - // round robin with "lookahead" for 2 requesters - rrarbiter #( - .NUM_REQ ( 2 ) - ) i_rrarbiter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( flush_i ), - .en_i ( 1'b1 ), - .req_i ( {~st_empty, ~ld_empty} ), - .ack_o ( { st_ren, ld_ren } ), - .vld_o ( valid_o ), - .idx_o ( idx ) - ); - - fifo_v2 #( - .dtype ( fifo_t ), - .DEPTH ( DEPTH ) - ) i_ld_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( flush_i ), - .testmode_i ( 1'b0 ), - .full_o ( ld_full ), - .empty_o ( ld_empty ), - .alm_full_o ( ), - .alm_empty_o ( ), - .data_i ( ld_in ), - .push_i ( ld_valid_i ), - .data_o ( ld_out ), - .pop_i ( ld_ren ) - ); - - fifo_v2 #( - .dtype ( fifo_t ), - .DEPTH ( DEPTH ) - ) i_st_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( flush_i ), - .testmode_i ( 1'b0 ), - .full_o ( st_full ), - .empty_o ( st_empty ), - .alm_full_o ( ), - .alm_empty_o ( ), - .data_i ( st_in ), - .push_i ( st_valid_i ), - .data_o ( st_out ), - .pop_i ( st_ren ) - ); - - -`ifndef SYNTHESIS -`ifndef VERILATOR - // check fifo control signals - assert property (@(posedge clk_i) disable iff (~rst_ni) ld_full |-> !ld_valid_i) else $fatal ("cannot write full ld_fifo"); - assert property (@(posedge clk_i) disable iff (~rst_ni) st_full |-> !st_valid_i) else $fatal ("cannot write full st_fifo"); - assert property (@(posedge clk_i) disable iff (~rst_ni) ld_empty |-> !ld_ren) else $fatal ("cannot read empty ld_fifo"); - assert property (@(posedge clk_i) disable iff (~rst_ni) st_empty |-> !st_ren) else $fatal ("cannot read empty st_fifo"); -`endif -`endif - - -endmodule diff --git a/src/mmu.sv b/src/mmu.sv index ada0e86144..b45de2c114 100644 --- a/src/mmu.sv +++ b/src/mmu.sv @@ -156,6 +156,25 @@ module mmu #( .* ); + // ila_1 i_ila_1 ( + // .clk(clk_i), // input wire clk + // .probe0({req_port_o.address_tag, req_port_o.address_index}), + // .probe1(req_port_o.data_req), // input wire [63:0] probe1 + // .probe2(req_port_i.data_gnt), // input wire [0:0] probe2 + // .probe3(req_port_i.data_rdata), // input wire [0:0] probe3 + // .probe4(req_port_i.data_rvalid), // input wire [0:0] probe4 + // .probe5(ptw_error), // input wire [1:0] probe5 + // .probe6(update_vaddr), // input wire [0:0] probe6 + // .probe7(update_ptw_itlb.valid), // input wire [0:0] probe7 + // .probe8(update_ptw_dtlb.valid), // input wire [0:0] probe8 + // .probe9(dtlb_lu_access), // input wire [0:0] probe9 + // .probe10(lsu_vaddr_i), // input wire [0:0] probe10 + // .probe11(dtlb_lu_hit), // input wire [0:0] probe11 + // .probe12(itlb_lu_access), // input wire [0:0] probe12 + // .probe13(icache_areq_i.fetch_vaddr), // input wire [0:0] probe13 + // .probe14(itlb_lu_hit) // input wire [0:0] probe13 + // ); + //----------------------- // Instruction Interface //----------------------- @@ -172,15 +191,16 @@ module mmu #( iaccess_err = icache_areq_i.fetch_req && (((priv_lvl_i == riscv::PRIV_LVL_U) && ~itlb_content.u) || ((priv_lvl_i == riscv::PRIV_LVL_S) && itlb_content.u)); - // check that the upper-most bits (63-39) are the same, otherwise throw a page fault exception... - if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[63:39]) == 1'b1 || (|icache_areq_i.fetch_vaddr[63:39]) == 1'b0)) begin - icache_areq_o.fetch_exception = {riscv::INSTR_PAGE_FAULT, icache_areq_i.fetch_vaddr, 1'b1}; - end // MMU enabled: address from TLB, request delayed until hit. Error when TLB // hit and no access right or TLB hit and translated address not valid (e.g. // AXI decode error), or when PTW performs walk due to ITLB miss and raises // an error. if (enable_translation_i) begin + // we work with SV39, so if VM is enabled, check that all bits [63:38] are equal + if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[63:38]) == 1'b1 || (|icache_areq_i.fetch_vaddr[63:38]) == 1'b0)) begin + icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, icache_areq_i.fetch_vaddr, 1'b1}; + end + icache_areq_o.fetch_valid = 1'b0; // 4K page diff --git a/src/mult.sv b/src/mult.sv index 2cbb5fe5c5..1d2658008d 100644 --- a/src/mult.sv +++ b/src/mult.sv @@ -1,17 +1,3 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Author: Florian Zaruba -// -// Date: 05.06.2017 -// Description: Ariane Multiplier import ariane_pkg::*; @@ -19,11 +5,8 @@ module mult ( input logic clk_i, input logic rst_ni, input logic flush_i, - input logic [TRANS_ID_BITS-1:0] trans_id_i, + input fu_data_t fu_data_i, input logic mult_valid_i, - input fu_op operator_i, - input logic [63:0] operand_a_i, - input logic [63:0] operand_b_i, output logic [63:0] result_o, output logic mult_valid_o, output logic mult_ready_o, @@ -40,8 +23,8 @@ module mult ( logic div_valid_op; logic mul_valid_op; // Input Arbitration - assign mul_valid_op = ~flush_i && mult_valid_i && (operator_i inside { MUL, MULH, MULHU, MULHSU, MULW }); - assign div_valid_op = ~flush_i && mult_valid_i && (operator_i inside { DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW }); + assign mul_valid_op = ~flush_i && mult_valid_i && (fu_data_i.operator inside { MUL, MULH, MULHU, MULHSU, MULW }); + assign div_valid_op = ~flush_i && mult_valid_i && (fu_data_i.operator inside { DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW }); // --------------------- // Output Arbitration @@ -57,45 +40,34 @@ module mult ( // --------------------- // Multiplication // --------------------- - mul i_mul ( + multiplier i_multiplier ( + .clk_i, + .rst_ni, + .trans_id_i ( fu_data_i.trans_id ), + .operator_i ( fu_data_i.operator ), + .operand_a_i ( fu_data_i.operand_a ), + .operand_b_i ( fu_data_i.operand_b ), .result_o ( mul_result ), .mult_valid_i ( mul_valid_op ), .mult_valid_o ( mul_valid ), .mult_trans_id_o ( mul_trans_id ), - .mult_ready_o ( ), // this unit is unconditionally ready - .* + .mult_ready_o ( ) // this unit is unconditionally ready ); // --------------------- // Division // --------------------- - logic [5:0] lzc_result; // holds the index of the last '1' (as the input operand is reversed) - logic lzc_no_one; // no one was found by find first one - logic [63:0] lzc_input; // input to find first one - logic [63:0] operand_b_rev, operand_b_rev_neg, operand_b_shift; // couple of different representations for the dividend - logic [6:0] div_shift; // amount of which to shift to left - logic div_signed; // should this operation be performed as a signed or unsigned division - logic div_op_signed; // actual sign signal depends on div_signed and the MSB of the word logic [63:0] operand_b, operand_a; // input operands after input MUX (input silencing, word operations or full inputs) logic [63:0] result; // result before result mux - logic word_op; // is it a word operation + logic div_signed; // signed or unsigned division logic rem; // is it a reminder (or not a reminder e.g.: a division) logic word_op_d, word_op_q; // save whether the operation was signed or not - // is this a signed operation? - assign div_signed = (operator_i inside {DIV, DIVW, REM, REMW}) ? 1'b1 : 1'b0; - // if this operation is signed look at the actual sign bit to determine whether we should perform signed or unsigned division - assign div_op_signed = div_signed & operand_b[63]; - - // reverse input operands - generate - for (genvar k = 0; k < 64; k++) - assign operand_b_rev[k] = operand_b[63-k]; - endgenerate - // negated reverse input operand, used for signed divisions - assign operand_b_rev_neg = ~operand_b_rev; - assign lzc_input = (div_op_signed) ? operand_b_rev_neg : operand_b_rev; + // is this a signed op? + assign div_signed = fu_data_i.operator inside {DIV, DIVW, REM, REMW}; + // is this a modulo? + assign rem = fu_data_i.operator inside {REM, REMU, REMW, REMUW}; // prepare the input operands and control divider always_comb begin @@ -103,82 +75,53 @@ module mult ( operand_a = '0; operand_b = '0; // control signals - word_op_d = word_op_q; - word_op = 1'b0; - rem = 1'b0; + word_op_d = word_op_q; // we've go a new division operation - if (mult_valid_i && operator_i inside {DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW}) begin + if (mult_valid_i && fu_data_i.operator inside {DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW}) begin // is this a word operation? - if (operator_i inside {DIVW, DIVUW, REMW, REMUW}) begin - word_op = 1'b1; + if (fu_data_i.operator inside {DIVW, DIVUW, REMW, REMUW}) begin // yes so check if we should sign extend this is only done for a signed operation if (div_signed) begin - operand_a = sext32(operand_a_i[31:0]); - operand_b = sext32(operand_b_i[31:0]); + operand_a = sext32(fu_data_i.operand_a[31:0]); + operand_b = sext32(fu_data_i.operand_b[31:0]); end else begin - operand_a = {32'b0, operand_a_i[31:0]}; - operand_b = {32'b0, operand_b_i[31:0]}; + operand_a = fu_data_i.operand_a[31:0]; + operand_b = fu_data_i.operand_b[31:0]; end // save whether we want sign extend the result or not, this is done for all word operations word_op_d = 1'b1; - // regular operation end else begin + // regular op + operand_a = fu_data_i.operand_a; + operand_b = fu_data_i.operand_b; word_op_d = 1'b0; - // no sign extending is necessary as we are already using the full 64 bit - operand_a = operand_a_i; - operand_b = operand_b_i; - end - - // is this a modulo? - if (operator_i inside {REM, REMU, REMW, REMUW}) begin - rem = 1'b1; end end end - // --------------------- - // Leading Zero Counter - // --------------------- - // this unit is used to speed up the sequential division by shifting the dividend first - lzc #( - .WIDTH ( 64 ) - ) i_lzc ( - .in_i ( lzc_input ), // signed = operand_b_rev_neg, unsigned operand_b_rev - .cnt_o ( lzc_result ), - .empty_o ( lzc_no_one ) - ); - - // if the dividend is all zero go for the full length - assign div_shift = lzc_no_one ? 7'd64 : lzc_result; - // prepare dividend by shifting - assign operand_b_shift = operand_b <<< div_shift; - // --------------------- // Serial Divider // --------------------- - serial_divider #( - .C_WIDTH ( 64 ), - .C_LOG_WIDTH ( $clog2(64) + 1 ) + serdiv #( + .WIDTH ( 64 ) ) i_div ( - .Clk_CI ( clk_i ), - .Rst_RBI ( rst_ni ), - .TransId_DI ( trans_id_i ), - .OpA_DI ( operand_a ), - .OpB_DI ( operand_b_shift ), - .OpBShift_DI ( div_shift ), - .OpBIsZero_SI ( ~(|operand_b) ), - .OpBSign_SI ( div_op_signed ), // gate this to 0 in case of unsigned ops - .OpCode_SI ( {rem, div_signed} ), // 00: udiv, 10: urem, 01: div, 11: rem - .InVld_SI ( div_valid_op ), - .Flush_SI ( flush_i ), - .OutRdy_SO ( mult_ready_o ), - .OutRdy_SI ( div_ready_i ), - .OutVld_SO ( div_valid ), - .TransId_DO ( div_trans_id ), - .Res_DO ( result ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .id_i ( fu_data_i.trans_id ), + .op_a_i ( operand_a ), + .op_b_i ( operand_b ), + .opcode_i ( {rem, div_signed} ), // 00: udiv, 10: urem, 01: div, 11: rem + .in_vld_i ( div_valid_op ), + .in_rdy_o ( mult_ready_o ), + .flush_i ( flush_i ), + .out_vld_o ( div_valid ), + .out_rdy_i ( div_ready_i ), + .id_o ( div_trans_id ), + .res_o ( result ) ); + // Result multiplexer // if it was a signed word operation the bit will be set and the result will be sign extended accordingly assign div_result = (word_op_q) ? sext32(result) : result; @@ -188,323 +131,9 @@ module mult ( // --------------------- always_ff @(posedge clk_i or negedge rst_ni) begin if(~rst_ni) begin - word_op_q <= ADD; + word_op_q <= '0; end else begin word_op_q <= word_op_d; end end endmodule - -/* File : mult.sv - * Ver : 1.0 - * Date : 15.03.2016 - * - * - * Copyright (C) 2017 ETH Zurich, University of Bologna - * - * Description: this is a simple serial divider for signed integers. - * - * - * Authors : Michael Schaffner (schaffner@iis.ee.ethz.ch) - * Andreas Traber (atraber@iis.ee.ethz.ch) - * - */ -module serial_divider #( - parameter int unsigned C_WIDTH = 32, - parameter int unsigned C_LOG_WIDTH = 6 -)( - input logic Clk_CI, - input logic Rst_RBI, - // input IF - input logic [TRANS_ID_BITS-1:0] TransId_DI, - input logic [C_WIDTH-1:0] OpA_DI, - input logic [C_WIDTH-1:0] OpB_DI, - input logic [C_LOG_WIDTH-1:0] OpBShift_DI, - input logic OpBIsZero_SI, - // - input logic OpBSign_SI, // gate this to 0 in case of unsigned ops - input logic [1:0] OpCode_SI, // 0: udiv, 2: urem, 1: div, 3: rem - // handshake - input logic InVld_SI, - input logic Flush_SI, - // output IF - output logic OutRdy_SO, - input logic OutRdy_SI, - output logic OutVld_SO, - output logic [TRANS_ID_BITS-1:0] TransId_DO, - output logic [C_WIDTH-1:0] Res_DO -); - - // ---------------------------------- - // Signal Declarations - // ---------------------------------- - logic [C_WIDTH-1:0] ResReg_DP, ResReg_DN; - logic [C_WIDTH-1:0] ResReg_DP_rev; - logic [C_WIDTH-1:0] AReg_DP, AReg_DN; - logic [C_WIDTH-1:0] BReg_DP, BReg_DN; - logic OpBIsZero_SP, OpBIsZero_SN; - - logic [TRANS_ID_BITS-1:0] TransId_DP, TransId_DN; - - logic RemSel_SN, RemSel_SP; - logic CompInv_SN, CompInv_SP; - logic ResInv_SN, ResInv_SP; - - logic [C_WIDTH-1:0] AddMux_D; - logic [C_WIDTH-1:0] AddOut_D; - logic [C_WIDTH-1:0] AddTmp_D; - logic [C_WIDTH-1:0] BMux_D; - logic [C_WIDTH-1:0] OutMux_D; - - logic [C_LOG_WIDTH-1:0] Cnt_DP, Cnt_DN; - logic CntZero_S; - - logic ARegEn_S, BRegEn_S, ResRegEn_S, ABComp_S, PmSel_S, LoadEn_S; - - enum logic [1:0] {IDLE, DIVIDE, FINISH} State_SN, State_SP; - - - // ----------------- - // Datapath - // ----------------- - assign PmSel_S = LoadEn_S & ~(OpCode_SI[0] & (OpA_DI[$high(OpA_DI)] ^ OpBSign_SI)); - - // muxes - assign AddMux_D = (LoadEn_S) ? OpA_DI : BReg_DP; - - // attention: logical shift in case of negative operand B! - assign BMux_D = (LoadEn_S) ? OpB_DI : {CompInv_SP, (BReg_DP[$high(BReg_DP):1])}; - - assign ResReg_DP_rev = {<<{ResReg_DP}}; - assign OutMux_D = (RemSel_SP) ? AReg_DP : ResReg_DP_rev; - - // invert if necessary - assign Res_DO = (ResInv_SP) ? -$signed(OutMux_D) : OutMux_D; - - // main comparator - assign ABComp_S = ((AReg_DP == BReg_DP) | ((AReg_DP > BReg_DP) ^ CompInv_SP)) & ((|AReg_DP) | OpBIsZero_SP); - - // main adder - assign AddTmp_D = (LoadEn_S) ? 0 : AReg_DP; - assign AddOut_D = (PmSel_S) ? AddTmp_D + AddMux_D : AddTmp_D - $signed(AddMux_D); - - // ----------------- - // Counter - // ----------------- - assign Cnt_DN = (LoadEn_S) ? OpBShift_DI : - (~CntZero_S) ? Cnt_DP - 1 : Cnt_DP; - - assign CntZero_S = ~(|Cnt_DP); - - // ----------------- - // FSM - // ----------------- - always_comb begin : p_fsm - // default - State_SN = State_SP; - - OutVld_SO = 1'b0; - OutRdy_SO = 1'b0; - - LoadEn_S = 1'b0; - - ARegEn_S = 1'b0; - BRegEn_S = 1'b0; - ResRegEn_S = 1'b0; - - case (State_SP) - - IDLE: begin - OutRdy_SO = 1'b1; - - if (InVld_SI) begin - OutRdy_SO = 1'b0; - OutVld_SO = 1'b0; - ARegEn_S = 1'b1; - BRegEn_S = 1'b1; - LoadEn_S = 1'b1; - State_SN = DIVIDE; - end - end - - DIVIDE: begin - - ARegEn_S = ABComp_S; - BRegEn_S = 1'b1; - ResRegEn_S = 1'b1; - - // calculation finished - // one more divide cycle (C_WIDTH th divide cycle) - if (CntZero_S) begin - State_SN = FINISH; - end - end - - FINISH: begin - OutVld_SO = 1'b1; - - if (OutRdy_SI) begin - State_SN = IDLE; - end - end - - default : /* default */ ; - - endcase - - if (Flush_SI) begin - OutRdy_SO = 1'b0; - OutVld_SO = 1'b0; - ARegEn_S = 1'b0; - BRegEn_S = 1'b0; - LoadEn_S = 1'b0; - State_SN = IDLE; - end - end - - // ----------------- - // Registers - // ----------------- - // get flags - assign RemSel_SN = (LoadEn_S) ? OpCode_SI[1] : RemSel_SP; - assign CompInv_SN = (LoadEn_S) ? OpBSign_SI : CompInv_SP; - assign OpBIsZero_SN = (LoadEn_S) ? OpBIsZero_SI : OpBIsZero_SP; - assign ResInv_SN = (LoadEn_S) ? (~OpBIsZero_SI | OpCode_SI[1]) & OpCode_SI[0] & (OpA_DI[$high(OpA_DI)] ^ OpBSign_SI) : ResInv_SP; - - // transaction id - assign TransId_DN = (LoadEn_S) ? TransId_DI : TransId_DP; - assign TransId_DO = TransId_DP; - - assign AReg_DN = (ARegEn_S) ? AddOut_D : AReg_DP; - assign BReg_DN = (BRegEn_S) ? BMux_D : BReg_DP; - assign ResReg_DN = (LoadEn_S) ? '0 : - (ResRegEn_S) ? {ABComp_S, ResReg_DP[$high(ResReg_DP):1]} : ResReg_DP; - - always_ff @(posedge Clk_CI or negedge Rst_RBI) begin : p_regs - if (~Rst_RBI) begin - State_SP <= IDLE; - AReg_DP <= '0; - BReg_DP <= '0; - ResReg_DP <= '0; - Cnt_DP <= '0; - TransId_DP <= '0; - RemSel_SP <= 1'b0; - CompInv_SP <= 1'b0; - ResInv_SP <= 1'b0; - OpBIsZero_SP <= 1'b0; - end else begin - State_SP <= State_SN; - AReg_DP <= AReg_DN; - BReg_DP <= BReg_DN; - ResReg_DP <= ResReg_DN; - Cnt_DP <= Cnt_DN; - TransId_DP <= TransId_DN; - RemSel_SP <= RemSel_SN; - CompInv_SP <= CompInv_SN; - ResInv_SP <= ResInv_SN; - OpBIsZero_SP <= OpBIsZero_SN; - end - end - - // ------------ - // Assertions - // ------------ - `ifndef SYNTHESIS - initial begin : p_assertions - assert (C_LOG_WIDTH == $clog2(C_WIDTH+1)) else $error("C_LOG_WIDTH must be $clog2(C_WIDTH+1)"); - end - `endif - -endmodule - -// -------------------------------------------------- -// Multiplication Unit with one pipeline register -// -------------------------------------------------- -module mul ( - input logic clk_i, - input logic rst_ni, - input logic [TRANS_ID_BITS-1:0] trans_id_i, - input logic mult_valid_i, - input fu_op operator_i, - input logic [63:0] operand_a_i, - input logic [63:0] operand_b_i, - output logic [63:0] result_o, - output logic mult_valid_o, - output logic mult_ready_o, - output logic [TRANS_ID_BITS-1:0] mult_trans_id_o - -); - // Pipeline register - logic [TRANS_ID_BITS-1:0] trans_id_q; - logic mult_valid_q; - fu_op operator_d, operator_q; - logic [127:0] mult_result_d, mult_result_q; - - // control registers - logic sign_a, sign_b; - logic mult_valid; - - // control signals - assign mult_valid_o = mult_valid_q; - assign mult_trans_id_o = trans_id_q; - assign mult_ready_o = 1'b1; - - assign mult_valid = mult_valid_i && (operator_i inside {MUL, MULH, MULHU, MULHSU, MULW}); - // datapath - logic [127:0] mult_result; - assign mult_result = $signed({operand_a_i[63] & sign_a, operand_a_i}) * $signed({operand_b_i[63] & sign_b, operand_b_i}); - - // Sign Select MUX - always_comb begin - sign_a = 1'b0; - sign_b = 1'b0; - - // signed multiplication - if (operator_i == MULH) begin - sign_a = 1'b1; - sign_b = 1'b1; - // signed - unsigned multiplication - end else if (operator_i == MULHSU) begin - sign_a = 1'b1; - // unsigned multiplication - end else begin - sign_a = 1'b0; - sign_b = 1'b0; - end - end - - - // single stage version - assign mult_result_d = $signed({operand_a_i[63] & sign_a, operand_a_i}) * - $signed({operand_b_i[63] & sign_b, operand_b_i}); - - - assign operator_d = operator_i; - always_comb begin : p_selmux - unique case (operator_q) - MULH, MULHU, MULHSU: result_o = mult_result_q[127:64]; - MULW: result_o = sext32(mult_result_q[31:0]); - // MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register - default: result_o = mult_result_q[63:0];// including MUL - endcase - end - - // ----------------------- - // Output pipeline register - // ----------------------- - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - mult_valid_q <= '0; - trans_id_q <= '0; - operator_q <= MUL; - mult_result_q <= '0; - end else begin - // Input silencing - trans_id_q <= trans_id_i; - // Output Register - mult_valid_q <= mult_valid; - operator_q <= operator_d; - mult_result_q <= mult_result_d; - end - end -endmodule diff --git a/src/multiplier.sv b/src/multiplier.sv new file mode 100644 index 0000000000..bbe9de2b6e --- /dev/null +++ b/src/multiplier.sv @@ -0,0 +1,105 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba +// +// Description: Multiplication Unit with one pipeline register +// This unit relies on retiming features of the synthesizer +// + +import ariane_pkg::*; + +module multiplier ( + input logic clk_i, + input logic rst_ni, + input logic [TRANS_ID_BITS-1:0] trans_id_i, + input logic mult_valid_i, + input fu_op operator_i, + input logic [63:0] operand_a_i, + input logic [63:0] operand_b_i, + output logic [63:0] result_o, + output logic mult_valid_o, + output logic mult_ready_o, + output logic [TRANS_ID_BITS-1:0] mult_trans_id_o +); + // Pipeline register + logic [TRANS_ID_BITS-1:0] trans_id_q; + logic mult_valid_q; + fu_op operator_d, operator_q; + logic [127:0] mult_result_d, mult_result_q; + + // control registers + logic sign_a, sign_b; + logic mult_valid; + + // control signals + assign mult_valid_o = mult_valid_q; + assign mult_trans_id_o = trans_id_q; + assign mult_ready_o = 1'b1; + + assign mult_valid = mult_valid_i && (operator_i inside {MUL, MULH, MULHU, MULHSU, MULW}); + // datapath + logic [127:0] mult_result; + assign mult_result = $signed({operand_a_i[63] & sign_a, operand_a_i}) * $signed({operand_b_i[63] & sign_b, operand_b_i}); + + // Sign Select MUX + always_comb begin + sign_a = 1'b0; + sign_b = 1'b0; + + // signed multiplication + if (operator_i == MULH) begin + sign_a = 1'b1; + sign_b = 1'b1; + // signed - unsigned multiplication + end else if (operator_i == MULHSU) begin + sign_a = 1'b1; + // unsigned multiplication + end else begin + sign_a = 1'b0; + sign_b = 1'b0; + end + end + + + // single stage version + assign mult_result_d = $signed({operand_a_i[63] & sign_a, operand_a_i}) * + $signed({operand_b_i[63] & sign_b, operand_b_i}); + + + assign operator_d = operator_i; + always_comb begin : p_selmux + unique case (operator_q) + MULH, MULHU, MULHSU: result_o = mult_result_q[127:64]; + MULW: result_o = sext32(mult_result_q[31:0]); + // MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register + default: result_o = mult_result_q[63:0];// including MUL + endcase + end + + // ----------------------- + // Output pipeline register + // ----------------------- + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + mult_valid_q <= '0; + trans_id_q <= '0; + operator_q <= MUL; + mult_result_q <= '0; + end else begin + // Input silencing + trans_id_q <= trans_id_i; + // Output Register + mult_valid_q <= mult_valid; + operator_q <= operator_d; + mult_result_q <= mult_result_d; + end + end +endmodule diff --git a/src/perf_counters.sv b/src/perf_counters.sv index caa244f93f..381ff105ff 100644 --- a/src/perf_counters.sv +++ b/src/perf_counters.sv @@ -17,8 +17,9 @@ import ariane_pkg::*; module perf_counters #( int unsigned NR_EXTERNAL_COUNTERS = 1 )( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + input logic clk_i, + input logic rst_ni, + input logic debug_mode_i, // debug mode // SRAM like interface input logic [11:0] addr_i, // read/write address input logic we_i, // write enable @@ -34,64 +35,79 @@ module perf_counters #( // from MMU input logic itlb_miss_i, input logic dtlb_miss_i, + // from issue stage + input logic sb_full_i, + // from frontend + input logic if_empty_i, // from PC Gen input exception_t ex_i, input logic eret_i, input branchpredict_t resolved_branch_i ); - logic [11:0][63:0] perf_counter_d, perf_counter_q; + logic [13:0][63:0] perf_counter_d, perf_counter_q; always_comb begin : perf_counters perf_counter_d = perf_counter_q; data_o = 'b0; - // ------------------------------ - // Update Performance Counters - // ------------------------------ - if (l1_icache_miss_i) - perf_counter_d[riscv::PERF_L1_ICACHE_MISS] = perf_counter_q[riscv::PERF_L1_ICACHE_MISS] + 1'b1; + // don't increment counters in debug mode + if (!debug_mode_i) begin + // ------------------------------ + // Update Performance Counters + // ------------------------------ + if (l1_icache_miss_i) + perf_counter_d[riscv::PERF_L1_ICACHE_MISS] = perf_counter_q[riscv::PERF_L1_ICACHE_MISS] + 1'b1; - if (l1_dcache_miss_i) - perf_counter_d[riscv::PERF_L1_DCACHE_MISS] = perf_counter_q[riscv::PERF_L1_DCACHE_MISS] + 1'b1; + if (l1_dcache_miss_i) + perf_counter_d[riscv::PERF_L1_DCACHE_MISS] = perf_counter_q[riscv::PERF_L1_DCACHE_MISS] + 1'b1; - if (itlb_miss_i) - perf_counter_d[riscv::PERF_ITLB_MISS] = perf_counter_q[riscv::PERF_ITLB_MISS] + 1'b1; + if (itlb_miss_i) + perf_counter_d[riscv::PERF_ITLB_MISS] = perf_counter_q[riscv::PERF_ITLB_MISS] + 1'b1; - if (dtlb_miss_i) - perf_counter_d[riscv::PERF_DTLB_MISS] = perf_counter_q[riscv::PERF_DTLB_MISS] + 1'b1; + if (dtlb_miss_i) + perf_counter_d[riscv::PERF_DTLB_MISS] = perf_counter_q[riscv::PERF_DTLB_MISS] + 1'b1; - // instruction related perf counters - for (int unsigned i = 0; i < NR_COMMIT_PORTS-1; i++) begin - if (commit_ack_i[i]) begin - if (commit_instr_i[i].fu == LOAD) - perf_counter_d[riscv::PERF_LOAD] = perf_counter_q[riscv::PERF_LOAD] + 1'b1; + // instruction related perf counters + for (int unsigned i = 0; i < NR_COMMIT_PORTS-1; i++) begin + if (commit_ack_i[i]) begin + if (commit_instr_i[i].fu == LOAD) + perf_counter_d[riscv::PERF_LOAD] = perf_counter_q[riscv::PERF_LOAD] + 1'b1; - if (commit_instr_i[i].fu == STORE) - perf_counter_d[riscv::PERF_STORE] = perf_counter_q[riscv::PERF_STORE] + 1'b1; + if (commit_instr_i[i].fu == STORE) + perf_counter_d[riscv::PERF_STORE] = perf_counter_q[riscv::PERF_STORE] + 1'b1; - if (commit_instr_i[i].fu == CTRL_FLOW) - perf_counter_d[riscv::PERF_BRANCH_JUMP] = perf_counter_q[riscv::PERF_BRANCH_JUMP] + 1'b1; + if (commit_instr_i[i].fu == CTRL_FLOW) + perf_counter_d[riscv::PERF_BRANCH_JUMP] = perf_counter_q[riscv::PERF_BRANCH_JUMP] + 1'b1; - // The standard software calling convention uses register x1 to hold the return address on a call - // the unconditional jump is decoded as ADD op - if (commit_instr_i[i].fu == CTRL_FLOW && commit_instr_i[i].op == '0 && commit_instr_i[i].rd == 'b1) - perf_counter_d[riscv::PERF_CALL] = perf_counter_q[riscv::PERF_CALL] + 1'b1; + // The standard software calling convention uses register x1 to hold the return address on a call + // the unconditional jump is decoded as ADD op + if (commit_instr_i[i].fu == CTRL_FLOW && commit_instr_i[i].op == '0 && commit_instr_i[i].rd == 'b1) + perf_counter_d[riscv::PERF_CALL] = perf_counter_q[riscv::PERF_CALL] + 1'b1; - // Return from call - if (commit_instr_i[i].op == JALR && commit_instr_i[i].rs1 == 'b1) - perf_counter_d[riscv::PERF_RET] = perf_counter_q[riscv::PERF_RET] + 1'b1; + // Return from call + if (commit_instr_i[i].op == JALR && commit_instr_i[i].rs1 == 'b1) + perf_counter_d[riscv::PERF_RET] = perf_counter_q[riscv::PERF_RET] + 1'b1; + end end - end - if (ex_i.valid) - perf_counter_d[riscv::PERF_EXCEPTION] = perf_counter_q[riscv::PERF_EXCEPTION] + 1'b1; + if (ex_i.valid) + perf_counter_d[riscv::PERF_EXCEPTION] = perf_counter_q[riscv::PERF_EXCEPTION] + 1'b1; + + if (eret_i) + perf_counter_d[riscv::PERF_EXCEPTION_RET] = perf_counter_q[riscv::PERF_EXCEPTION_RET] + 1'b1; + + if (resolved_branch_i.valid && resolved_branch_i.is_mispredict) + perf_counter_d[riscv::PERF_MIS_PREDICT] = perf_counter_q[riscv::PERF_MIS_PREDICT] + 1'b1; - if (eret_i) - perf_counter_d[riscv::PERF_EXCEPTION_RET] = perf_counter_q[riscv::PERF_EXCEPTION_RET] + 1'b1; + if (sb_full_i) begin + perf_counter_d[riscv::PERF_SB_FULL] = perf_counter_q[riscv::PERF_SB_FULL] + 1'b1; + end - if (resolved_branch_i.valid && resolved_branch_i.is_mispredict) - perf_counter_d[riscv::PERF_MIS_PREDICT] = perf_counter_q[riscv::PERF_MIS_PREDICT] + 1'b1; + if (if_empty_i) begin + perf_counter_d[riscv::PERF_IF_EMPTY] = perf_counter_q[riscv::PERF_IF_EMPTY] + 1'b1; + end + end // Read Port if (!we_i) begin diff --git a/src/plic/plic.sv b/src/plic/plic.sv new file mode 100644 index 0000000000..5e694f65ce --- /dev/null +++ b/src/plic/plic.sv @@ -0,0 +1,155 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +//------------------------------------------------------------------------------- +//-- Title : PLIC Core +//-- File : plic_core.sv +//-- Author : Gian Marti +//-- Author : Thomas Kramer +//-- Author : Thomas E. Benz +//-- Company : Integrated Systems Laboratory, ETH Zurich +//-- Created : 2018-03-31 +//-- Last update: 2018-03-31 +//-- Platform : ModelSim (simulation), Synopsys (synthesis) +//-- Standard : SystemVerilog IEEE 1800-2012 +//------------------------------------------------------------------------------- +//-- Description: PLIC Top-level +//------------------------------------------------------------------------------- +//-- Revisions : +//-- Date Version Author Description +//-- 2018-03-31 2.0 tbenz Created header +//------------------------------------------------------------------------------- + +module plic #( + parameter int ADDR_WIDTH = 32, // can be either 32 or 64 bits (don't use 64bit at the moment as this causes memory map issues) + parameter int DATA_WIDTH = 32, // can be either 32 or 64 bits (don't use 64bit at the moment as this causes memory map issues) + parameter int ID_BITWIDTH = -1, // width of the gateway identifiers + parameter int PARAMETER_BITWIDTH = -1, // width of the internal parameter e.g. priorities + parameter int NUM_TARGETS = -1, // number of target slices + parameter int NUM_SOURCES = -1 // number of sources = number of gateways +) ( + input logic clk_i, + input logic rst_ni, + input logic [NUM_SOURCES-1:0] irq_sources_i, + output logic [NUM_TARGETS-1:0] eip_targets_o, + REG_BUS.in external_bus_io +); + // declare all local variables + // gateway arrays always go from NUM_SOURCES to 1 because gateway ids start at 1 + logic gateway_irq_pendings [NUM_SOURCES]; //for pending irqs of the gateways + logic gateway_claimed [NUM_SOURCES]; //if a gateway is claimed, it masks its irq + logic gateway_completed [NUM_SOURCES]; //if a gateway is completed, it is reenabled + logic [ID_BITWIDTH-1:0 ] gateway_ids [NUM_SOURCES]; //ids of gateways + logic [PARAMETER_BITWIDTH-1:0] gateway_priorities [NUM_SOURCES]; //priorities of gateways + + logic irq_enableds [NUM_SOURCES][NUM_TARGETS]; + logic [PARAMETER_BITWIDTH-1:0] target_thresholds [NUM_TARGETS]; + logic [ID_BITWIDTH-1:0 ] identifier_of_largest_priority_per_target [NUM_TARGETS]; + + logic target_irq_claims [NUM_TARGETS]; + logic target_irq_completes [NUM_TARGETS]; + logic [ID_BITWIDTH-1:0 ] target_irq_completes_id [NUM_TARGETS]; + + //instantiate and connect gateways + for (genvar counter = 0; counter < NUM_SOURCES; counter++) begin : gen_plic_gateway + plic_gateway plic_gateway_instance ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .irq_source_i ( irq_sources_i [counter] ), + .claim_i ( gateway_claimed [counter] ), + .completed_i ( gateway_completed [counter] ), + .irq_pending_o ( gateway_irq_pendings[counter] ) + ); + end + + // assign ids to gateways + for (genvar counter = 1; counter <= NUM_SOURCES; counter++) begin + assign gateway_ids[counter-1] = counter; + + end + + // instantiate and connect target slices + for (genvar counter = 0; counter < NUM_TARGETS; counter++) begin : gen_plic_target_slice + + logic irq_enableds_slice[NUM_SOURCES]; + for (genvar inner_counter = 0; inner_counter < NUM_SOURCES; inner_counter++) begin + assign irq_enableds_slice[inner_counter] = irq_enableds[inner_counter][counter]; + end + + plic_target_slice #( + .PRIORITY_BITWIDTH ( PARAMETER_BITWIDTH ), + .ID_BITWIDTH ( ID_BITWIDTH ), + .NUM_GATEWAYS ( NUM_SOURCES ) + ) plic_target_slice_instance ( + .interrupt_pending_i ( gateway_irq_pendings ), + .interrupt_priority_i ( gateway_priorities ), + .interrupt_id_i ( gateway_ids ), + .interrupt_enable_i ( irq_enableds_slice ), + .threshold_i ( target_thresholds[counter] ), + .ext_interrupt_present_o ( eip_targets_o[counter] ), + .identifier_of_largest_o ( identifier_of_largest_priority_per_target[counter] ) + ); + end + + //instantiate and connect plic_interface + plic_interface #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .ID_BITWIDTH ( ID_BITWIDTH ), + .PARAMETER_BITWIDTH ( PARAMETER_BITWIDTH ), + .NUM_TARGETS ( NUM_TARGETS ), + .NUM_GATEWAYS ( NUM_SOURCES ) + ) plic_interface_instance ( + .clk_i, + .rst_ni, + .id_of_largest_priority_i ( identifier_of_largest_priority_per_target ), + .pending_array_i ( gateway_irq_pendings ), + .thresholds_o ( target_thresholds ), + .gateway_priorities_o ( gateway_priorities ), + .irq_enables_o ( irq_enableds ), + .target_irq_claims_o ( target_irq_claims ), + .target_irq_completes_o ( target_irq_completes ), + .target_irq_completes_id_o ( target_irq_completes_id ), + .external_bus_io ( external_bus_io ) + ); + + //instantiate and connect claim_complete_tracker + plic_claim_complete_tracker #( + .NUM_TARGETS ( NUM_TARGETS ), + .NUM_GATEWAYS ( NUM_SOURCES ), + .ID_BITWIDTH ( ID_BITWIDTH ) + ) plic_claim_complete_tracker_instance ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .identifier_of_largest_priority_per_target ( identifier_of_largest_priority_per_target ), + .target_irq_claims_i ( target_irq_claims ), + .target_irq_completes_i ( target_irq_completes ), + .target_irq_completes_identifier_i ( target_irq_completes_id ), + .gateway_irq_claims_o ( gateway_claimed ), + .gateway_irq_completes_o ( gateway_completed ) + ); + + //pragma translate_off + `ifndef VERILATOR + initial begin + assert((ADDR_WIDTH == 32) | (ADDR_WIDTH == 64)) else $error("Address width has to bei either 32 or 64 bit"); + assert((DATA_WIDTH == 32) | (DATA_WIDTH == 64)) else $error("Data width has to bei either 32 or 64 bit"); + assert(ID_BITWIDTH > 0 ) else $error("ID_BITWIDTH has to be larger than 1"); + assert(ID_BITWIDTH < 10 ) else $error("ID_BITWIDTH has to be smaller than 10"); + assert(PARAMETER_BITWIDTH > 0) else $error("PARAMETER_BITWIDTH has to be larger than 1"); + assert(PARAMETER_BITWIDTH < 8) else $error("PARAMETER_BITWIDTH has to be smaller than 8"); + assert(NUM_SOURCES > 0 ) else $error("Num od Gateways has to be larger than 1"); + assert(NUM_SOURCES < 512 ) else $error("Num of Gateways has to be smaller than 512"); + assert(NUM_TARGETS > 0 ) else $error("Num Target slices has to be larger than 1"); + assert(NUM_TARGETS < 15872 ) else $error("Num target slices has to be smaller than 15872"); + end + `endif + //pragma translate_on +endmodule diff --git a/src/plic/plic_claim_complete_tracker.sv b/src/plic/plic_claim_complete_tracker.sv new file mode 100644 index 0000000000..0de0b212ca --- /dev/null +++ b/src/plic/plic_claim_complete_tracker.sv @@ -0,0 +1,134 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +//------------------------------------------------------------------------------- +//-- Title : Claim - Complete - Tracker +//------------------------------------------------------------------------------- +//-- File : plic_claim_complete_tracker.sv +//-- Author : Gian Marti +//-- Author : Thomas Kramer +//-- Author : Thomas E. Benz +//-- Company : Integrated Systems Laboratory, ETH Zurich +//-- Created : 2018-03-31 +//-- Last update: 2018-03-31 +//-- Platform : ModelSim (simulation), Synopsys (synthesis) +//-- Standard : SystemVerilog IEEE 1800-2012 +//------------------------------------------------------------------------------- +//-- Description: Implements the control logic of the plic +//------------------------------------------------------------------------------- +//-- Revisions : +//-- Date Version Author Description +//-- 2018-03-31 2.0 tbenz Created header +//------------------------------------------------------------------------------- + +//FSM that receives interrupt claims and interrupt completes from targets +//and generates the fitting inerrupt claims and interrupt completes for sources +module plic_claim_complete_tracker #( + parameter int NUM_TARGETS = 1, + parameter int NUM_GATEWAYS = 1, + parameter int ID_BITWIDTH = 4 +)( + input logic clk_i, // Clock + input logic rst_ni, // Asynchronous reset active low + + input logic [ID_BITWIDTH-1:0] identifier_of_largest_priority_per_target[NUM_TARGETS], + input logic target_irq_claims_i [NUM_TARGETS], + input logic target_irq_completes_i[NUM_TARGETS], + input logic [ID_BITWIDTH-1:0] target_irq_completes_identifier_i[NUM_TARGETS], + + output logic gateway_irq_claims_o [NUM_GATEWAYS], + output logic gateway_irq_completes_o[NUM_GATEWAYS] + +); + + // claimed_gateways_q[target] is 0 if the target has not claimed the irq of any gateway + // and the is the identifier of the claimed gateway otherwise + logic [ID_BITWIDTH-1:0] claimed_gateways_q[NUM_TARGETS]; + + // the +1 is because counting starts from 1 and goes to NUM_GATEWAYS+1 + logic claim_array [NUM_GATEWAYS+1][NUM_TARGETS]; + logic save_claims_array_q [NUM_GATEWAYS+1][NUM_TARGETS]; + logic complete_array [NUM_GATEWAYS+1][NUM_TARGETS]; + + logic [ID_BITWIDTH-1:0] complete_id; + + + // for handling claims + for (genvar counter = 0; counter < NUM_TARGETS; counter++) begin + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_target + integer id; + + if (~rst_ni) begin + claimed_gateways_q[counter] <= '0; + + for (integer i = 0; i <= NUM_GATEWAYS; i++) begin + claim_array[i][counter] <= '0; + save_claims_array_q[i][counter] <= '0; + end + + end else begin + // per default, all claims and completes are zero + for (integer i = 0; i <= NUM_GATEWAYS; i++) begin + claim_array[i][counter] <= 0; + complete_array[i][counter] <= 0; + end + + // if a claim is issued, forward it to gateway with highest priority for the claiming target + if (target_irq_claims_i[counter]) begin + id = identifier_of_largest_priority_per_target[counter]; + claim_array[id][counter] <= 1; + + // save claim for later when the complete-notification arrives + save_claims_array_q[id][counter] <= 1; + + end else begin + // if a complete is issued, check if that gateway has previously been claimed by + // this target and forward the + // complete message to that gateway. if no claim has previously been issued, the + // complete message is ignored + // integer complete_id = target_irq_completes_identifier_i[counter]; + complete_id = target_irq_completes_identifier_i[counter]; + + if (target_irq_completes_i[counter] && (save_claims_array_q[complete_id][counter] > 0)) begin + complete_array[complete_id][counter] <= 1; + save_claims_array_q[complete_id][counter] <= 0; + end + end + end + end + end + + + // the outputs for an id are the ORs of all targets for that id + always_comb begin : proc_result_computation + for (integer gateway = 1; gateway <= NUM_GATEWAYS; gateway++) begin + automatic logic is_claimed = '0; + automatic logic is_completed = '0; + + for (integer target = 0; target < NUM_TARGETS; target++) begin + is_claimed = is_claimed | claim_array [gateway][target]; + is_completed = is_completed | complete_array[gateway][target]; + end + + if (is_claimed) begin + gateway_irq_claims_o [gateway-1] = 1; + end else begin + gateway_irq_claims_o [gateway-1] = 0; + end + + if (is_completed) begin + gateway_irq_completes_o[gateway-1] = 1; + end else begin + gateway_irq_completes_o[gateway-1] = 0; + end + end + end + +endmodule //plic_claim_complete_tracker diff --git a/src/plic/plic_comparator.sv b/src/plic/plic_comparator.sv new file mode 100644 index 0000000000..49b5f2f57c --- /dev/null +++ b/src/plic/plic_comparator.sv @@ -0,0 +1,63 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +//------------------------------------------------------------------------------- +//-- Title : Comperator +//-- File : plic_comperator.sv +//-- Author : Gian Marti +//-- Author : Thomas Kramer +//-- Author : Thomas E. Benz +//-- Company : Integrated Systems Laboratory, ETH Zurich +//-- Created : 2018-03-31 +//-- Last update: 2018-03-31 +//-- Platform : ModelSim (simulation), Synopsys (synthesis) +//-- Standard : SystemVerilog IEEE 1800-2012 +//------------------------------------------------------------------------------- +//-- Description: Comparator +//------------------------------------------------------------------------------- +//-- Revisions : +//-- Date Version Author Description +//-- 2018-03-31 2.0 tbenz Created header +//------------------------------------------------------------------------------- + +// find larger operand (value and identifier) +// chooses the left operand on equality +module plic_comparator #( + parameter int ID_BITWIDTH = -1, + parameter int PRIORITY_BITWIDTH = -1 +)( + input logic [PRIORITY_BITWIDTH-1:0] left_priority_i, + input logic [PRIORITY_BITWIDTH-1:0] right_priority_i, + input logic [ID_BITWIDTH-1:0 ] left_identifier_i, + input logic [ID_BITWIDTH-1:0 ] right_identifier_i, + output logic [PRIORITY_BITWIDTH-1:0] larger_priority_o, + output logic[ ID_BITWIDTH-1:0 ] identifier_of_larger_o +); + + always_comb begin : proc_compare + if (left_priority_i >= right_priority_i) begin + larger_priority_o = left_priority_i; + identifier_of_larger_o = left_identifier_i; + end else begin + larger_priority_o = right_priority_i; + identifier_of_larger_o = right_identifier_i; + end + end + + //pragma translate_off + `ifndef VERILATOR + initial begin + assert(ID_BITWIDTH > 0) else $error("ID_BITWIDTH has to be larger than 0"); + assert(PRIORITY_BITWIDTH > 0) else $error("PRIORITY_BITWIDTH has to be larger than 0"); + end + `endif + //pragma translate_on + +endmodule diff --git a/src/plic/plic_find_max.sv b/src/plic/plic_find_max.sv new file mode 100644 index 0000000000..2d20687740 --- /dev/null +++ b/src/plic/plic_find_max.sv @@ -0,0 +1,78 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +//------------------------------------------------------------------------------- +//-- Title : Find Maximun +//-- File : plic_find_max.sv +//-- Author : Gian Marti +//-- Author : Thomas Kramer +//-- Author : Thomas E. Benz +//-- Company : Integrated Systems Laboratory, ETH Zurich +//-- Created : 2018-03-31 +//-- Last update: 2018-03-31 +//-- Platform : ModelSim (simulation), Synopsys (synthesis) +//-- Standard : SystemVerilog IEEE 1800-2012 +//------------------------------------------------------------------------------- +//-- Description: Find the element with the largest priority +//------------------------------------------------------------------------------- +//-- Revisions : +//-- Date Version Author Description +//-- 2018-03-31 2.0 tbenz Created header +//------------------------------------------------------------------------------- + +module plic_find_max #( + parameter int NUM_OPERANDS = 2, + parameter int ID_BITWIDTH = 4, + parameter int PRIORITY_BITWIDTH = 3 +)( + input logic [PRIORITY_BITWIDTH-1:0] priorities_i [NUM_OPERANDS], + input logic [ID_BITWIDTH-1:0 ] identifiers_i [NUM_OPERANDS], + output logic [PRIORITY_BITWIDTH-1:0] largest_priority_o, + output logic [ID_BITWIDTH-1:0 ] identifier_of_largest_o +); + + localparam int max_stage = ($clog2(NUM_OPERANDS)-1); + localparam int num_operands_aligned = 2**(max_stage+1); + + logic [PRIORITY_BITWIDTH-1:0] priority_stages [max_stage + 2][num_operands_aligned]; + logic [ID_BITWIDTH-1:0 ] identifier_stages [max_stage + 2][num_operands_aligned]; + + + always_comb begin : proc_zero_padding + for (integer operand = 0; operand < num_operands_aligned; operand++) begin + if(operand < NUM_OPERANDS) begin + priority_stages [0][operand] = priorities_i [operand]; + identifier_stages[0][operand] = identifiers_i [operand]; + end else begin + priority_stages [0][operand] = '0; + identifier_stages[0][operand] = '0; + end + end + end + + for (genvar comparator_stage = max_stage; comparator_stage >= 0 ; comparator_stage--) begin + for (genvar stage_index = 0; stage_index < 2**comparator_stage; stage_index++) begin + plic_comparator #( + .ID_BITWIDTH (ID_BITWIDTH ), + .PRIORITY_BITWIDTH (PRIORITY_BITWIDTH ) + ) comp_instance( + .left_priority_i ( priority_stages [max_stage - comparator_stage][2*stage_index] ), + .right_priority_i ( priority_stages [max_stage - comparator_stage][2*stage_index + 1] ), + .left_identifier_i ( identifier_stages[max_stage - comparator_stage][2*stage_index] ), + .right_identifier_i ( identifier_stages[max_stage - comparator_stage][2*stage_index + 1] ), + .larger_priority_o ( priority_stages [max_stage - (comparator_stage-1)][stage_index] ), + .identifier_of_larger_o ( identifier_stages[max_stage - (comparator_stage-1)][stage_index] ) + ); + end + end + + assign largest_priority_o = priority_stages [max_stage+1][0]; + assign identifier_of_largest_o = identifier_stages[max_stage+1][0]; +endmodule diff --git a/src/plic/plic_gateway.sv b/src/plic/plic_gateway.sv new file mode 100644 index 0000000000..137e5af785 --- /dev/null +++ b/src/plic/plic_gateway.sv @@ -0,0 +1,80 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +//------------------------------------------------------------------------------- +//-- Title : Interrupt Gateway +//-- File : plic_gateway.sv +//-- Author : Gian Marti +//-- Author : Thomas Kramer +//-- Author : Thomas E. Benz +//-- Company : Integrated Systems Laboratory, ETH Zurich +//-- Created : 2018-03-31 +//-- Last update: 2018-03-31 +//-- Platform : ModelSim (simulation), Synopsys (synthesis) +//-- Standard : SystemVerilog IEEE 1800-2012 +//------------------------------------------------------------------------------- +//-- Description: Implementation of the Irq Gateway +//------------------------------------------------------------------------------- +//-- Revisions : +//-- Date Version Author Description +//-- 2018-03-31 2.0 tbenz Created header +//------------------------------------------------------------------------------- + +// the gateway does enable or disable itself depending on the signals claim_i, completed_i +// the gateway knows neither its gateway_id nor its priority +module plic_gateway ( + input logic clk_i, + input logic rst_ni, + input logic irq_source_i, + input logic claim_i, + input logic completed_i, + output logic irq_pending_o +); + logic irq_pending_q; // is 1 when an interrupt appears until the interrupt is claimed + logic wait_completion_q; // is 1 when an interrupt appears until the interrupt is completed + // also determines if the gateway is disabled, i.e. if interrupts are masked + logic irq_trigger; + + assign irq_trigger = (~wait_completion_q | completed_i) & irq_source_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_update_ff + if (~rst_ni) begin + irq_pending_q <= 1'b0; + wait_completion_q <= 1'b0; + end else begin + //pragma translate_off + `ifndef VERILATOR + assert (~(claim_i & (~wait_completion_q & irq_source_i))); + assert (~(completed_i & (~wait_completion_q & irq_source_i))); + `endif + //pragma translate_on + + //interrupts not masked and interrupt received -> output to 1 + if (irq_trigger) begin + irq_pending_q <= 1; + //interrupt claimed -> output to 0 + end else if (claim_i) begin + irq_pending_q <= 0; + end + + //interrupts not masked and interrupt received -> interrupts masked from know on + if (irq_trigger) begin + wait_completion_q <= 1; + //interrupt completed -> demask interrupts + end else if (completed_i) begin + wait_completion_q <= 0; + end + end + end + + // Make sure there is 0 cycles delay from claim_i to irq_pending_o. + assign irq_pending_o = (irq_pending_q | irq_trigger) & ~claim_i; + +endmodule diff --git a/src/plic/plic_interface.sv b/src/plic/plic_interface.sv new file mode 100644 index 0000000000..8293cc857a --- /dev/null +++ b/src/plic/plic_interface.sv @@ -0,0 +1,304 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +//------------------------------------------------------------------------------- +//-- Title : Register Interface +//-- File : plic_target_slice.sv +//-- Author : Gian Marti +//-- Author : Thomas Kramer +//-- Author : Thomas E. Benz +//-- Company : Integrated Systems Laboratory, ETH Zurich +//-- Created : 2018-03-31 +//-- Last update: 2018-03-31 +//-- Platform : ModelSim (simulation), Synopsys (synthesis) +//-- Standard : SystemVerilog IEEE 1800-2012 +//------------------------------------------------------------------------------- +//-- Description: Implementation of the plic's register interface +//------------------------------------------------------------------------------- +//-- Revisions : +//-- Date Version Author Description +//-- 2018-03-31 2.0 tbenz Created header +//------------------------------------------------------------------------------- + +module plic_interface #( + parameter int ADDR_WIDTH = 32, // width of external address bus + parameter int DATA_WIDTH = 32, // width of external data bus + parameter int ID_BITWIDTH = 10, // width of the gateway indecies + parameter int PARAMETER_BITWIDTH = 3, // width of the internal parameter e.g. priorities + parameter int NUM_TARGETS = 1, // number of target slices + parameter int NUM_GATEWAYS = 1 // number of gateways +)( + input logic clk_i, // the clock signal + input logic rst_ni, // asynchronous reset active low + input logic[ID_BITWIDTH-1:0] id_of_largest_priority_i[NUM_TARGETS], // input array id of largest priority + input logic pending_array_i[NUM_GATEWAYS], // array with the interrupt pending , idx0 is gateway 1 + output reg [PARAMETER_BITWIDTH-1:0] thresholds_o[NUM_TARGETS], // save internally the thresholds, communicate values over this port to the core + output reg [PARAMETER_BITWIDTH-1:0] gateway_priorities_o[NUM_GATEWAYS], // save internally the the priorities, communicate values + output logic irq_enables_o[NUM_GATEWAYS][NUM_TARGETS], // communicate enable bits over this port + output logic target_irq_claims_o[NUM_TARGETS], // claim signals + output logic target_irq_completes_o[NUM_TARGETS], // complete signals + output logic[ID_BITWIDTH-1:0] target_irq_completes_id_o[NUM_TARGETS], // the id of the gateway to be completed + REG_BUS.in external_bus_io // the bus +); + + //define ennumerated types + enum logic [2:0] {INV, PRI, IPA, IEB, THR, CCP} funct; // the address mapping will primarily check what + // function should be performed + // INV: invalid, PRI: priorities, IPA: interrupt pending + // IEB: interrupt enable, THR: threshold and claim/complete + // CCP: claim/clear pulses + + //calculate some parameter needed later + localparam int num_gateway_bundles = (NUM_GATEWAYS-1) / DATA_WIDTH + 1; // how many bundles we have to consider + localparam int bpw = DATA_WIDTH / 8; // how many bytes a data word consist of + //internal signals + logic [ADDR_WIDTH-12-1:0 ] page_address; // the upper part of the address + logic [11:0 ] page_offset; // the lowest 12 bit describes the page offset + logic [11-$clog2(bpw):0 ] page_word_offset; // the word address of each page offset + logic [$clog2(bpw)-1:0 ] word_offset; // the byte in the word + + logic [DATA_WIDTH/8-1:0 ] write_active; // 0 if inactive, else what byte ahs to be written + logic read_active; // 0 if inactive, 1 when reading the word + //bundle definitions + logic [DATA_WIDTH-1:0 ] irq_pending_bundle[num_gateway_bundles]; + + //registers + logic [PARAMETER_BITWIDTH-1:0] thresholds_d[NUM_TARGETS]; + logic [PARAMETER_BITWIDTH-1:0] thresholds_q[NUM_TARGETS]; + + logic [PARAMETER_BITWIDTH-1:0] priorities_d[NUM_GATEWAYS]; + logic [PARAMETER_BITWIDTH-1:0] priorities_q[NUM_GATEWAYS]; + + logic [ID_BITWIDTH-1:0 ] id_of_largest_priority_d[NUM_TARGETS]; + logic [ID_BITWIDTH-1:0 ] id_of_largest_priority_q[NUM_TARGETS]; + + logic [DATA_WIDTH/bpw-1:0 ] ena_bundles_d[num_gateway_bundles][NUM_TARGETS][DATA_WIDTH/8]; + logic [DATA_WIDTH/bpw-1:0 ] ena_bundles_q[num_gateway_bundles][NUM_TARGETS][DATA_WIDTH/8]; + + // assignments + assign id_of_largest_priority_d = id_of_largest_priority_i; + + // assign addresses + assign page_address = external_bus_io.addr[ADDR_WIDTH-1:12]; + assign page_offset = external_bus_io.addr[11:0 ]; + assign page_word_offset = external_bus_io.addr[11:$clog2(bpw) ]; + assign word_offset = external_bus_io.addr[$clog2(bpw)-1:0]; + + assign write_active = (external_bus_io.valid & external_bus_io.write) ? external_bus_io.wstrb : '0; + assign read_active = external_bus_io.valid & !external_bus_io.write; + + // bundle signals + for (genvar bundle = 0; bundle < num_gateway_bundles; bundle++) begin + for (genvar ip_bit = 0; ip_bit < DATA_WIDTH; ip_bit++) begin + if (bundle * DATA_WIDTH + ip_bit < NUM_GATEWAYS) begin + assign irq_pending_bundle[bundle][ip_bit] = pending_array_i[bundle * DATA_WIDTH + ip_bit]; + end else begin + assign irq_pending_bundle[bundle][ip_bit] = '0; + end + end + end + + for (genvar bundle = 0; bundle < num_gateway_bundles; bundle++) begin + for (genvar target = 0; target < NUM_TARGETS; target++) begin + for (genvar byte_in_word = 0; byte_in_word < DATA_WIDTH/8; byte_in_word++) begin + for (genvar enable_bit = 0; enable_bit < 8; enable_bit++) begin + assign irq_enables_o[bundle * DATA_WIDTH + enable_bit + byte_in_word * 8][target] = + ena_bundles_q[bundle][target][byte_in_word][enable_bit]; + end + end + end + end + + // determine the function to be performed + always_comb begin : proc_address_map + // default values + funct = INV; + // only aligned access is allowed: + if (word_offset == '0) begin + // we have now an word alligned access -> check out page offset to determine + // what type of access this is. + if (page_address[13:0] == 0) begin // we access the gateway priority bits + // the page_word_offset tells us now which gateway we consider + // in order to grant or deny access, we have to check if the gateway + // in question really exist. + // Gateway 0 does not exist, so return an error + if (page_word_offset <= NUM_GATEWAYS && page_word_offset > 0) begin //the gateway in question exists + // set the current operation to be an access to the priority registers + funct = PRI; + end + // we now access the IP Bits, read only + end else if (page_address[13:0] == 1) begin + // the page_word_offset tells us now, which word we have to consider, + // the word, which includes the IP bit in question should be returned + if (page_word_offset0) else $error("ID_BITWIDTH has to be larger than 1"); + assert (ID_BITWIDTH<10) else $error("ID_BITWIDTH has to be smaller than 10"); + assert (PARAMETER_BITWIDTH>0) else $error("PARAMETER_BITWIDTH has to be larger than 1"); + assert (PARAMETER_BITWIDTH<8) else $error("PARAMETER_BITWIDTH has to be smaller than 8"); + assert (NUM_GATEWAYS>0) else $error("Num od Gateways has to be larger than 1"); + assert (NUM_GATEWAYS<512) else $error("Num of Gateways has to be smaller than 512"); + assert (NUM_TARGETS>0) else $error("Num Target slices has to be larger than 1"); + assert (NUM_TARGETS<15872) else $error("Num target slices has to be smaller than 15872"); + end + `endif + // pragma translate_on + +endmodule diff --git a/src/plic/plic_target_slice.sv b/src/plic/plic_target_slice.sv new file mode 100644 index 0000000000..aba2152195 --- /dev/null +++ b/src/plic/plic_target_slice.sv @@ -0,0 +1,92 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +//------------------------------------------------------------------------------- +//-- Title : Target Slice +//-- File : plic_target_slice.sv +//-- Author : Gian Marti +//-- Author : Thomas Kramer +//-- Author : Thomas E. Benz +//-- Company : Integrated Systems Laboratory, ETH Zurich +//-- Created : 2018-03-31 +//-- Last update: 2018-03-31 +//-- Platform : ModelSim (simulation), Synopsys (synthesis) +//-- Standard : SystemVerilog IEEE 1800-2012 +//------------------------------------------------------------------------------- +//-- Description: Target Slice +//------------------------------------------------------------------------------- +//-- Revisions : +//-- Date Version Author Description +//-- 2018-03-31 2.0 tbenz Created header +//------------------------------------------------------------------------------- + +// Note: The gateways are expected to be ordered by their IDs (ascending). +// This resolves priority ties by choosing the gateway with the lower ID. +module plic_target_slice #( + parameter int PRIORITY_BITWIDTH = 8, + parameter int ID_BITWIDTH = 8, + parameter int NUM_GATEWAYS = 1 +)( + // Input signals from gateways. + input logic interrupt_pending_i [NUM_GATEWAYS], + input logic [PRIORITY_BITWIDTH-1:0] interrupt_priority_i[NUM_GATEWAYS], + input logic [ID_BITWIDTH-1:0 ] interrupt_id_i [NUM_GATEWAYS], + input logic interrupt_enable_i [NUM_GATEWAYS], + input logic [PRIORITY_BITWIDTH-1:0] threshold_i, + output logic ext_interrupt_present_o, + output logic [ID_BITWIDTH-1:0 ] identifier_of_largest_o +); + + logic[PRIORITY_BITWIDTH:0] interrupt_priority_masked[NUM_GATEWAYS]; + + + // Signals that represent the selected interrupt source. + logic[PRIORITY_BITWIDTH:0] best_priority; + logic[ID_BITWIDTH-1:0 ] best_id; + + // Create a tree to find the best interrupt source. + plic_find_max #( + .NUM_OPERANDS ( NUM_GATEWAYS ), + .ID_BITWIDTH ( ID_BITWIDTH ), + .PRIORITY_BITWIDTH ( PRIORITY_BITWIDTH + 1 ) + ) find_max_instance ( + .priorities_i ( interrupt_priority_masked ), + .identifiers_i ( interrupt_id_i ), + // Outputs + .largest_priority_o ( best_priority ), + .identifier_of_largest_o ( best_id ) + ); + + // Compare the priority of the best interrupt source to the threshold. + always_comb begin : proc_compare_threshold + if ((best_priority - 1 > threshold_i) && (best_priority != '0)) begin + ext_interrupt_present_o = 1; + identifier_of_largest_o = best_id; + end else begin + if ((best_priority - 1 <= threshold_i) && (best_priority != '0)) begin + ext_interrupt_present_o = 0; + identifier_of_largest_o = best_id; + end else begin + ext_interrupt_present_o = 0; + identifier_of_largest_o = 0; + end + end + end + + always_comb begin : proc_mask_gateway_outputs + for (int i = 0; i < NUM_GATEWAYS; i++) begin + if (interrupt_enable_i[i] && interrupt_pending_i[i]) begin + interrupt_priority_masked[i] = interrupt_priority_i[i] + 1; //priority shift +1 + end else begin + interrupt_priority_masked[i] = '0; + end + end + end +endmodule diff --git a/src/ptw.sv b/src/ptw.sv index 89a04e2cac..8129c06949 100644 --- a/src/ptw.sv +++ b/src/ptw.sv @@ -99,8 +99,8 @@ module ptw #( assign ptw_active_o = (state_q != IDLE); assign walking_instr_o = is_instr_ptw_q; // directly output the correct physical address - assign req_port_o.address_index = ptw_pptr_q[11:0]; - assign req_port_o.address_tag = ptw_pptr_q[55:12]; + assign req_port_o.address_index = ptw_pptr_q[DCACHE_INDEX_WIDTH-1:0]; + assign req_port_o.address_tag = ptw_pptr_q[DCACHE_INDEX_WIDTH+DCACHE_TAG_WIDTH-1:DCACHE_INDEX_WIDTH]; // we are never going to kill this request assign req_port_o.kill_req = '0; // we are never going to write with the HPTW diff --git a/src/register_interface b/src/register_interface new file mode 160000 index 0000000000..d10dce04b7 --- /dev/null +++ b/src/register_interface @@ -0,0 +1 @@ +Subproject commit d10dce04b7211da044d31baaa06c7044c84083d9 diff --git a/src/scoreboard.sv b/src/scoreboard.sv index 990c598584..13bc00b514 100644 --- a/src/scoreboard.sv +++ b/src/scoreboard.sv @@ -21,6 +21,7 @@ module scoreboard #( )( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low + output logic sb_full_o, input logic flush_unissued_instr_i, // flush only un-issued instructions input logic flush_i, // flush whole scoreboard input logic unresolved_branch_i, // we have an unresolved branch @@ -79,6 +80,8 @@ module scoreboard #( // the issue queue is full don't issue any new instructions assign issue_full = (issue_cnt_q == NR_ENTRIES-1); + assign sb_full_o = issue_full; + // output commit instruction directly always_comb begin : commit_ports for (logic [BITS_ENTRIES-1:0] i = 0; i < NR_COMMIT_PORTS; i++) @@ -276,8 +279,9 @@ module scoreboard #( commit_pointer_q <= commit_pointer_n; end end - `ifndef SYNTHESIS - `ifndef verilator + + //pragma translate_off + `ifndef VERILATOR initial begin assert (NR_ENTRIES == 2**BITS_ENTRIES) else $fatal("Scoreboard size needs to be a power of two."); end @@ -310,5 +314,5 @@ module scoreboard #( end end `endif - `endif + //pragma translate_on endmodule diff --git a/src/serdiv.sv b/src/serdiv.sv new file mode 100644 index 0000000000..d71baf2025 --- /dev/null +++ b/src/serdiv.sv @@ -0,0 +1,257 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Andreas Traber , ETH Zurich +// +// Date: 18.10.2018 +// Description: simple 64bit serial divider + +import ariane_pkg::*; + +module serdiv #( + parameter WIDTH = 64 +) ( + input logic clk_i, + input logic rst_ni, + // input IF + input logic [TRANS_ID_BITS-1:0] id_i, + input logic [WIDTH-1:0] op_a_i, + input logic [WIDTH-1:0] op_b_i, + input logic [1:0] opcode_i, // 0: udiv, 2: urem, 1: div, 3: rem + // handshake + input logic in_vld_i, // there is a cycle delay from in_rdy_o->in_vld_i, see issue_read_operands.sv stage + output logic in_rdy_o, + input logic flush_i, + // output IF + output logic out_vld_o, + input logic out_rdy_i, + output logic [TRANS_ID_BITS-1:0] id_o, + output logic [WIDTH-1:0] res_o +); + +///////////////////////////////////// +// signal declarations +///////////////////////////////////// + + enum logic [1:0] {IDLE, DIVIDE, FINISH} state_d, state_q; + + logic [WIDTH-1:0] res_q, res_d; + logic [WIDTH-1:0] op_a_q, op_a_d; + logic [WIDTH-1:0] op_b_q, op_b_d; + logic op_a_sign, op_b_sign; + logic op_b_zero, op_b_zero_q, op_b_zero_d; + + logic [TRANS_ID_BITS-1:0] id_q, id_d; + + logic rem_sel_d, rem_sel_q; + logic comp_inv_d, comp_inv_q; + logic res_inv_d, res_inv_q; + + logic [WIDTH-1:0] add_mux; + logic [WIDTH-1:0] add_out; + logic [WIDTH-1:0] add_tmp; + logic [WIDTH-1:0] b_mux; + logic [WIDTH-1:0] out_mux; + + logic [$clog2(WIDTH+1)-1:0] cnt_q, cnt_d; + logic cnt_zero; + + logic [WIDTH-1:0] lzc_a_input, lzc_b_input, op_b; + logic [$clog2(WIDTH)-1:0] lzc_a_result, lzc_b_result; + logic [$clog2(WIDTH+1)-1:0] shift_a; + logic [$clog2(WIDTH+1):0] div_shift; + + logic a_reg_en, b_reg_en, res_reg_en, ab_comp, pm_sel, load_en; + logic lzc_a_no_one, lzc_b_no_one; + logic div_res_zero_d, div_res_zero_q; + + +///////////////////////////////////// +// align the input operands +// for faster division +///////////////////////////////////// + + assign op_b_zero = (op_b_i == 0); + assign op_a_sign = op_a_i[$high(op_a_i)]; + assign op_b_sign = op_b_i[$high(op_b_i)]; + + assign lzc_a_input = (opcode_i[0] & op_a_sign) ? {~op_a_i, 1'b0} : op_a_i; + assign lzc_b_input = (opcode_i[0] & op_b_sign) ? ~op_b_i : op_b_i; + + lzc #( + .MODE ( 1 ), // count leading zeros + .WIDTH ( WIDTH ) + ) i_lzc_a ( + .in_i ( lzc_a_input ), + .cnt_o ( lzc_a_result ), + .empty_o ( lzc_a_no_one ) + ); + + lzc #( + .MODE ( 1 ), // count leading zeros + .WIDTH ( WIDTH ) + ) i_lzc_b ( + .in_i ( lzc_b_input ), + .cnt_o ( lzc_b_result ), + .empty_o ( lzc_b_no_one ) + ); + + assign shift_a = (lzc_a_no_one) ? WIDTH : lzc_a_result; + assign div_shift = (lzc_b_no_one) ? WIDTH : lzc_b_result-shift_a; + + assign op_b = op_b_i <<< $unsigned(div_shift); + + // the division is zero if |opB| > |opA| and can be terminated + assign div_res_zero_d = (load_en) ? ($signed(div_shift) < 0) : div_res_zero_q; + +///////////////////////////////////// +// Datapath +///////////////////////////////////// + + assign pm_sel = load_en & ~(opcode_i[0] & (op_a_sign ^ op_b_sign)); + + // muxes + assign add_mux = (load_en) ? op_a_i : op_b_q; + + // attention: logical shift by one in case of negative operand B! + assign b_mux = (load_en) ? op_b : {comp_inv_q, (op_b_q[$high(op_b_q):1])}; + + // in case of bad timing, we could output from regs -> needs a cycle more in the FSM + assign out_mux = (rem_sel_q) ? op_a_q : res_q; + // assign out_mux = (rem_sel_q) ? op_a_d : res_d; + + // invert if necessary + assign res_o = (res_inv_q) ? -$signed(out_mux) : out_mux; + + // main comparator + assign ab_comp = ((op_a_q == op_b_q) | ((op_a_q > op_b_q) ^ comp_inv_q)) & ((|op_a_q) | op_b_zero_q); + + // main adder + assign add_tmp = (load_en) ? 0 : op_a_q; + assign add_out = (pm_sel) ? add_tmp + add_mux : add_tmp - $signed(add_mux); + +///////////////////////////////////// +// FSM, counter +///////////////////////////////////// + + assign cnt_zero = (cnt_q == 0); + assign cnt_d = (load_en) ? div_shift : + (~cnt_zero) ? cnt_q - 1 : cnt_q; + + always_comb begin : p_fsm + // default + state_d = state_q; + in_rdy_o = 1'b0; + out_vld_o = 1'b0; + load_en = 1'b0; + a_reg_en = 1'b0; + b_reg_en = 1'b0; + res_reg_en = 1'b0; + + unique case (state_q) + IDLE: begin + in_rdy_o = 1'b1; + + if (in_vld_i) begin + in_rdy_o = 1'b0;// there is a cycle delay until the valid signal is asserted by the id stage + a_reg_en = 1'b1; + b_reg_en = 1'b1; + load_en = 1'b1; + state_d = DIVIDE; + end + end + DIVIDE: begin + if(~div_res_zero_q) begin + a_reg_en = ab_comp; + b_reg_en = 1'b1; + res_reg_en = 1'b1; + end + // can end the division now if the result is clearly 0 + if(div_res_zero_q) begin + out_vld_o = 1'b1; + state_d = FINISH; + if(out_rdy_i) begin + // in_rdy_o = 1'b1;// there is a cycle delay until the valid signal is asserted by the id stage + state_d = IDLE; + end + end else if (cnt_zero) begin + state_d = FINISH; + end + end + FINISH: begin + out_vld_o = 1'b1; + + if (out_rdy_i) begin + // in_rdy_o = 1'b1;// there is a cycle delay until the valid signal is asserted by the id stage + state_d = IDLE; + end + end + default : state_d = IDLE; + endcase + + if (flush_i) begin + in_rdy_o = 1'b0; + out_vld_o = 1'b0; + a_reg_en = 1'b0; + b_reg_en = 1'b0; + load_en = 1'b0; + state_d = IDLE; + end + end + +///////////////////////////////////// +// regs, flags +///////////////////////////////////// + + // get flags + assign rem_sel_d = (load_en) ? opcode_i[1] : rem_sel_q; + assign comp_inv_d = (load_en) ? opcode_i[0] & op_b_sign : comp_inv_q; + assign op_b_zero_d = (load_en) ? op_b_zero : op_b_zero_q; + assign res_inv_d = (load_en) ? (~op_b_zero | opcode_i[1]) & opcode_i[0] & (op_a_sign ^ op_b_sign) : res_inv_q; + + // transaction id + assign id_d = (load_en) ? id_i : id_q; + assign id_o = id_q; + + assign op_a_d = (a_reg_en) ? add_out : op_a_q; + assign op_b_d = (b_reg_en) ? b_mux : op_b_q; + assign res_d = (load_en) ? '0 : + (res_reg_en) ? {res_q[$high(res_q)-1:0], ab_comp} : res_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (~rst_ni) begin + state_q <= IDLE; + op_a_q <= '0; + op_b_q <= '0; + res_q <= '0; + cnt_q <= '0; + id_q <= '0; + rem_sel_q <= 1'b0; + comp_inv_q <= 1'b0; + res_inv_q <= 1'b0; + op_b_zero_q <= 1'b0; + div_res_zero_q <= 1'b0; + end else begin + state_q <= state_d; + op_a_q <= op_a_d; + op_b_q <= op_b_d; + res_q <= res_d; + cnt_q <= cnt_d; + id_q <= id_d; + rem_sel_q <= rem_sel_d; + comp_inv_q <= comp_inv_d; + res_inv_q <= res_inv_d; + op_b_zero_q <= op_b_zero_d; + div_res_zero_q <= div_res_zero_d; + end + end + +endmodule \ No newline at end of file diff --git a/src/store_buffer.sv b/src/store_buffer.sv index 6b07536f8b..0932ae3a97 100644 --- a/src/store_buffer.sv +++ b/src/store_buffer.sv @@ -39,19 +39,13 @@ module store_buffer ( input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write) // D$ interface - input dcache_req_o_t req_port_i, - output dcache_req_i_t req_port_o - ); - // depth of store-buffers - localparam int unsigned DEPTH_SPEC = 4; - // allocate more space for the commit buffer to be on the save side - localparam int unsigned DEPTH_COMMIT = 4; - + input dcache_req_o_t req_port_i, + output dcache_req_i_t req_port_o +); // the store queue has two parts: // 1. Speculative queue // 2. Commit queue which is non-speculative, e.g.: the store will definitely happen. - struct packed { logic [63:0] address; logic [63:0] data; @@ -71,6 +65,7 @@ module store_buffer ( logic [$clog2(DEPTH_COMMIT)-1:0] commit_read_pointer_n, commit_read_pointer_q; logic [$clog2(DEPTH_COMMIT)-1:0] commit_write_pointer_n, commit_write_pointer_q; + // ---------------------------------------- // Speculative Queue - Core Interface // ---------------------------------------- @@ -125,18 +120,22 @@ module store_buffer ( // ---------------------------------------- // Commit Queue - Memory Interface // ---------------------------------------- + + // we will never kill a request in the store buffer since we already know that the translation is valid + // e.g.: a kill request will only be necessary if we are not sure if the requested memory address will result in a TLB fault + assign req_port_o.kill_req = 1'b0; + assign req_port_o.data_we = 1'b1; // we will always write in the store queue + assign req_port_o.tag_valid = 1'b0; + // those signals can directly be output to the memory - assign req_port_o.address_index = commit_queue_q[commit_read_pointer_q].address[11:0]; + assign req_port_o.address_index = commit_queue_q[commit_read_pointer_q].address[ariane_pkg::DCACHE_INDEX_WIDTH-1:0]; // if we got a new request we already saved the tag from the previous cycle - assign req_port_o.address_tag = commit_queue_q[commit_read_pointer_q].address[55:12]; - assign req_port_o.tag_valid = 1'b0; + assign req_port_o.address_tag = commit_queue_q[commit_read_pointer_q].address[ariane_pkg::DCACHE_TAG_WIDTH + + ariane_pkg::DCACHE_INDEX_WIDTH-1 : + ariane_pkg::DCACHE_INDEX_WIDTH]; assign req_port_o.data_wdata = commit_queue_q[commit_read_pointer_q].data; assign req_port_o.data_be = commit_queue_q[commit_read_pointer_q].be; assign req_port_o.data_size = commit_queue_q[commit_read_pointer_q].data_size; - // we will never kill a request in the store buffer since we already know that the translation is valid - // e.g.: a kill request will only be necessary if we are not sure if the requested memory address will result in a TLB fault - assign req_port_o.kill_req = 1'b0; - assign req_port_o.data_we = 1'b1; // we will always write in the store queue always_comb begin : store_if automatic logic [DEPTH_COMMIT:0] commit_status_cnt; @@ -195,6 +194,7 @@ module store_buffer ( // page offsets are virtually and physically the same always_comb begin : address_checker page_offset_matches_o = 1'b0; + // check if the LSBs are identical and the entry is valid for (int unsigned i = 0; i < DEPTH_COMMIT; i++) begin // Check if the page offset matches and whether the entry is valid, for the commit queue @@ -203,6 +203,7 @@ module store_buffer ( break; end end + for (int unsigned i = 0; i < DEPTH_SPEC; i++) begin // do the same for the speculative queue if ((page_offset_i[11:3] == speculative_queue_q[i].address[11:3]) && speculative_queue_q[i].valid) begin @@ -218,31 +219,41 @@ module store_buffer ( // registers - always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ + always_ff @(posedge clk_i or negedge rst_ni) begin : p_spec if (~rst_ni) begin - // initialize the queues speculative_queue_q <= '{default: 0}; - commit_queue_q <= '{default: 0}; - commit_read_pointer_q <= '0; - commit_write_pointer_q <= '0; - commit_status_cnt_q <= '0; speculative_read_pointer_q <= '0; speculative_write_pointer_q <= '0; speculative_status_cnt_q <= '0; end else begin speculative_queue_q <= speculative_queue_n; + speculative_read_pointer_q <= speculative_read_pointer_n; + speculative_write_pointer_q <= speculative_write_pointer_n; + speculative_status_cnt_q <= speculative_status_cnt_n; + end + end + + // registers + always_ff @(posedge clk_i or negedge rst_ni) begin : p_commit + if (~rst_ni) begin + commit_queue_q <= '{default: 0}; + commit_read_pointer_q <= '0; + commit_write_pointer_q <= '0; + commit_status_cnt_q <= '0; + end else begin commit_queue_q <= commit_queue_n; commit_read_pointer_q <= commit_read_pointer_n; commit_write_pointer_q <= commit_write_pointer_n; commit_status_cnt_q <= commit_status_cnt_n; - speculative_read_pointer_q <= speculative_read_pointer_n; - speculative_write_pointer_q <= speculative_write_pointer_n; - speculative_status_cnt_q <= speculative_status_cnt_n; end end - `ifndef SYNTHESIS - `ifndef verilator +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + + //pragma translate_off + `ifndef VERILATOR // assert that commit is never set when we are flushing this would be counter intuitive // as flush and commit is decided in the same stage commit_and_flush: assert property ( @@ -258,9 +269,11 @@ module store_buffer ( else $error ("[Speculative Queue] You are committing although there are no stores to commit"); commit_buffer_overflow: assert property ( - @(posedge clk_i) rst_ni && (commit_status_cnt_q == DEPTH_SPEC) |-> !commit_i) + @(posedge clk_i) rst_ni && (commit_status_cnt_q == DEPTH_COMMIT) |-> !commit_i) else $error("[Commit Queue] You are trying to commit a store although the buffer is full"); - - `endif `endif + //pragma translate_on endmodule + + + diff --git a/src/tlb.sv b/src/tlb.sv index 2e88ff5210..497cec7a87 100644 --- a/src/tlb.sv +++ b/src/tlb.sv @@ -217,7 +217,7 @@ module tlb #( // Sanity checks //-------------- - `ifndef SYNTHESIS + //pragma translate_off `ifndef VERILATOR initial begin : p_assertions @@ -242,6 +242,6 @@ module tlb #( else begin $error("More then one TLB entry selected for next replace!"); $stop(); end `endif - `endif + //pragma translate_on endmodule diff --git a/src/util/axi_master_connect.sv b/src/util/axi_master_connect.sv new file mode 100644 index 0000000000..72cf8c703f --- /dev/null +++ b/src/util/axi_master_connect.sv @@ -0,0 +1,67 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Description: Connects SV AXI interface to structs used by Ariane +// Author: Florian Zaruba + +module axi_master_connect ( + input ariane_axi::req_t axi_req_i, + output ariane_axi::resp_t axi_resp_o, + AXI_BUS.out master +); + + assign master.aw_id = axi_req_i.aw.id; + assign master.aw_addr = axi_req_i.aw.addr; + assign master.aw_len = axi_req_i.aw.len; + assign master.aw_size = axi_req_i.aw.size; + assign master.aw_burst = axi_req_i.aw.burst; + assign master.aw_lock = axi_req_i.aw.lock; + assign master.aw_cache = axi_req_i.aw.cache; + assign master.aw_prot = axi_req_i.aw.prot; + assign master.aw_qos = axi_req_i.aw.qos; + assign master.aw_region = axi_req_i.aw.region; + assign master.aw_user = '0; + assign master.aw_valid = axi_req_i.aw_valid; + assign axi_resp_o.aw_ready = master.aw_ready; + + assign master.w_data = axi_req_i.w.data; + assign master.w_strb = axi_req_i.w.strb; + assign master.w_last = axi_req_i.w.last; + assign master.w_user = '0; + assign master.w_valid = axi_req_i.w_valid; + assign axi_resp_o.w_ready = master.w_ready; + + assign axi_resp_o.b.id = master.b_id; + assign axi_resp_o.b.resp = master.b_resp; + assign axi_resp_o.b_valid = master.b_valid; + assign master.b_ready = axi_req_i.b_ready; + + assign master.ar_id = axi_req_i.ar.id; + assign master.ar_addr = axi_req_i.ar.addr; + assign master.ar_len = axi_req_i.ar.len; + assign master.ar_size = axi_req_i.ar.size; + assign master.ar_burst = axi_req_i.ar.burst; + assign master.ar_lock = axi_req_i.ar.lock; + assign master.ar_cache = axi_req_i.ar.cache; + assign master.ar_prot = axi_req_i.ar.prot; + assign master.ar_qos = axi_req_i.ar.qos; + assign master.ar_region = axi_req_i.ar.region; + assign master.ar_user = '0; + assign master.ar_valid = axi_req_i.ar_valid; + assign axi_resp_o.ar_ready = master.ar_ready; + + assign axi_resp_o.r.id = master.r_id; + assign axi_resp_o.r.data = master.r_data; + assign axi_resp_o.r.resp = master.r_resp; + assign axi_resp_o.r.last = master.r_last; + assign axi_resp_o.r_valid = master.r_valid; + assign master.r_ready = axi_req_i.r_ready; + +endmodule diff --git a/src/util/axi_master_connect_rev.sv b/src/util/axi_master_connect_rev.sv new file mode 100644 index 0000000000..74383c7e02 --- /dev/null +++ b/src/util/axi_master_connect_rev.sv @@ -0,0 +1,68 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Description: Connects SV AXI interface to structs used by Ariane +// Author: Florian Zaruba + +module axi_master_connect_rev ( + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i, + AXI_BUS.in master +); + + assign axi_req_o.aw.atop = '0; // not supported at the moment + assign axi_req_o.aw.id = master.aw_id; + assign axi_req_o.aw.addr = master.aw_addr; + assign axi_req_o.aw.len = master.aw_len; + assign axi_req_o.aw.size = master.aw_size; + assign axi_req_o.aw.burst = master.aw_burst; + assign axi_req_o.aw.lock = master.aw_lock; + assign axi_req_o.aw.cache = master.aw_cache; + assign axi_req_o.aw.prot = master.aw_prot; + assign axi_req_o.aw.qos = master.aw_qos; + assign axi_req_o.aw.region = master.aw_region; + // assign = master.aw_user; + assign axi_req_o.aw_valid = master.aw_valid; + assign master.aw_ready = axi_resp_i.aw_ready; + + assign axi_req_o.w.data = master.w_data; + assign axi_req_o.w.strb = master.w_strb; + assign axi_req_o.w.last = master.w_last; + // assign = master.w_user; + assign axi_req_o.w_valid = master.w_valid; + assign master.w_ready = axi_resp_i.w_ready; + + assign master.b_id = axi_resp_i.b.id; + assign master.b_resp = axi_resp_i.b.resp; + assign master.b_valid = axi_resp_i.b_valid; + assign axi_req_o.b_ready = master.b_ready; + + assign axi_req_o.ar.id = master.ar_id; + assign axi_req_o.ar.addr = master.ar_addr; + assign axi_req_o.ar.len = master.ar_len; + assign axi_req_o.ar.size = master.ar_size; + assign axi_req_o.ar.burst = master.ar_burst; + assign axi_req_o.ar.lock = master.ar_lock; + assign axi_req_o.ar.cache = master.ar_cache; + assign axi_req_o.ar.prot = master.ar_prot; + assign axi_req_o.ar.qos = master.ar_qos; + assign axi_req_o.ar.region = master.ar_region; + // assign = master.ar_user; + assign axi_req_o.ar_valid = master.ar_valid; + assign master.ar_ready = axi_resp_i.ar_ready; + + assign master.r_id = axi_resp_i.r.id; + assign master.r_data = axi_resp_i.r.data; + assign master.r_resp = axi_resp_i.r.resp; + assign master.r_last = axi_resp_i.r.last; + assign master.r_valid = axi_resp_i.r_valid; + assign axi_req_o.r_ready = master.r_ready; + +endmodule diff --git a/src/util/axi_slave_connect.sv b/src/util/axi_slave_connect.sv new file mode 100644 index 0000000000..3c6f388e34 --- /dev/null +++ b/src/util/axi_slave_connect.sv @@ -0,0 +1,70 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Description: Connects SV AXI interface to structs used by Ariane +// Author: Florian Zaruba + +module axi_slave_connect ( + output ariane_axi::req_t axi_req_o, + input ariane_axi::resp_t axi_resp_i, + AXI_BUS.in slave +); + + assign axi_req_o.aw.atop = '0; // not supported at the moment + assign axi_req_o.aw.id = slave.aw_id; + assign axi_req_o.aw.addr = slave.aw_addr; + assign axi_req_o.aw.len = slave.aw_len; + assign axi_req_o.aw.size = slave.aw_size; + assign axi_req_o.aw.burst = slave.aw_burst; + assign axi_req_o.aw.lock = slave.aw_lock; + assign axi_req_o.aw.cache = slave.aw_cache; + assign axi_req_o.aw.prot = slave.aw_prot; + assign axi_req_o.aw.qos = slave.aw_qos; + assign axi_req_o.aw.region = slave.aw_region; + // assign = slave.aw_user; + assign axi_req_o.aw_valid = slave.aw_valid; + assign slave.aw_ready = axi_resp_i.aw_ready; + + assign axi_req_o.w.data = slave.w_data; + assign axi_req_o.w.strb = slave.w_strb; + assign axi_req_o.w.last = slave.w_last; + // assign = slave.w_user; + assign axi_req_o.w_valid = slave.w_valid; + assign slave.w_ready = axi_resp_i.w_ready; + + assign slave.b_id = axi_resp_i.b.id; + assign slave.b_resp = axi_resp_i.b.resp; + assign slave.b_valid = axi_resp_i.b_valid; + assign slave.b_user = 1'b0; + assign axi_req_o.b_ready = slave.b_ready; + + assign axi_req_o.ar.id = slave.ar_id; + assign axi_req_o.ar.addr = slave.ar_addr; + assign axi_req_o.ar.len = slave.ar_len; + assign axi_req_o.ar.size = slave.ar_size; + assign axi_req_o.ar.burst = slave.ar_burst; + assign axi_req_o.ar.lock = slave.ar_lock; + assign axi_req_o.ar.cache = slave.ar_cache; + assign axi_req_o.ar.prot = slave.ar_prot; + assign axi_req_o.ar.qos = slave.ar_qos; + assign axi_req_o.ar.region = slave.ar_region; + // assign = slave.ar_user; + assign axi_req_o.ar_valid = slave.ar_valid; + assign slave.ar_ready = axi_resp_i.ar_ready; + + assign slave.r_id = axi_resp_i.r.id; + assign slave.r_data = axi_resp_i.r.data; + assign slave.r_resp = axi_resp_i.r.resp; + assign slave.r_last = axi_resp_i.r.last; + assign slave.r_valid = axi_resp_i.r_valid; + assign slave.r_user = 1'b0; + assign axi_req_o.r_ready = slave.r_ready; + +endmodule diff --git a/src/util/axi_slave_connect_rev.sv b/src/util/axi_slave_connect_rev.sv new file mode 100644 index 0000000000..0106887ece --- /dev/null +++ b/src/util/axi_slave_connect_rev.sv @@ -0,0 +1,67 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Description: Connects SV AXI interface to structs used by Ariane +// Author: Florian Zaruba + +module axi_slave_connect_rev ( + input ariane_axi::req_t axi_req_i, + output ariane_axi::resp_t axi_resp_o, + AXI_BUS.out slave +); + + assign slave.aw_id = axi_req_i.aw.id; + assign slave.aw_addr = axi_req_i.aw.addr; + assign slave.aw_len = axi_req_i.aw.len; + assign slave.aw_size = axi_req_i.aw.size; + assign slave.aw_burst = axi_req_i.aw.burst; + assign slave.aw_lock = axi_req_i.aw.lock; + assign slave.aw_cache = axi_req_i.aw.cache; + assign slave.aw_prot = axi_req_i.aw.prot; + assign slave.aw_qos = axi_req_i.aw.qos; + assign slave.aw_region = axi_req_i.aw.region; + assign slave.aw_user = '0; + assign slave.aw_valid = axi_req_i.aw_valid; + assign axi_resp_o.aw_ready = slave.aw_ready; + + assign slave.w_data = axi_req_i.w.data; + assign slave.w_strb = axi_req_i.w.strb; + assign slave.w_last = axi_req_i.w.last; + assign slave.w_user = '0; + assign slave.w_valid = axi_req_i.w_valid; + assign axi_resp_o.w_ready = slave.w_ready; + + assign axi_resp_o.b.id = slave.b_id; + assign axi_resp_o.b.resp = slave.b_resp; + assign axi_resp_o.b_valid = slave.b_valid; + assign slave.b_ready = axi_req_i.b_ready; + + assign slave.ar_id = axi_req_i.ar.id; + assign slave.ar_addr = axi_req_i.ar.addr; + assign slave.ar_len = axi_req_i.ar.len; + assign slave.ar_size = axi_req_i.ar.size; + assign slave.ar_burst = axi_req_i.ar.burst; + assign slave.ar_lock = axi_req_i.ar.lock; + assign slave.ar_cache = axi_req_i.ar.cache; + assign slave.ar_prot = axi_req_i.ar.prot; + assign slave.ar_qos = axi_req_i.ar.qos; + assign slave.ar_region = axi_req_i.ar.region; + assign slave.ar_user = '0; + assign slave.ar_valid = axi_req_i.ar_valid; + assign axi_resp_o.ar_ready = slave.ar_ready; + + assign axi_resp_o.r.id = slave.r_id; + assign axi_resp_o.r.data = slave.r_data; + assign axi_resp_o.r.resp = slave.r_resp; + assign axi_resp_o.r.last = slave.r_last; + assign axi_resp_o.r_valid = slave.r_valid; + assign slave.r_ready = axi_req_i.r_ready; + +endmodule diff --git a/src/util/instruction_tracer.svh b/src/util/instruction_tracer.svh index 87f5d730a6..a056e237b2 100644 --- a/src/util/instruction_tracer.svh +++ b/src/util/instruction_tracer.svh @@ -47,10 +47,10 @@ class instruction_tracer; endfunction : new - function void create_file(logic [5:0] cluster_id, logic [3:0] core_id); + function void create_file(logic [63:0] hart_id); string fn, fn_commit_log; - $sformat(fn, "trace_core_%h_%h.log", cluster_id, core_id); - $sformat(fn_commit_log, "trace_core_%h_%h_commit.log", cluster_id, core_id); + $sformat(fn, "trace_hart_%04.0f.log", hart_id); + $sformat(fn_commit_log, "trace_hart_%04.0f_commit.log", hart_id); $display("[TRACER] Output filename is: %s", fn); this.f = $fopen(fn,"w"); @@ -61,7 +61,8 @@ class instruction_tracer; logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction; scoreboard_entry_t commit_instruction; // initialize register 0 - gp_reg_file [0] = 0; + gp_reg_file = '{default:0}; + fp_reg_file = '{default:0}; forever begin automatic branchpredict_t bp_instruction = '0; diff --git a/src/util/instruction_tracer_if.sv b/src/util/instruction_tracer_if.sv index fe19684ea1..873e812bfa 100644 --- a/src/util/instruction_tracer_if.sv +++ b/src/util/instruction_tracer_if.sv @@ -53,13 +53,14 @@ interface instruction_tracer_if ( riscv::priv_lvl_t priv_lvl; logic debug_mode; // the tracer just has a passive interface we do not drive anything with it - `ifndef SYNTHESIS + + //pragma translate_off clocking pck @(posedge clk); input rstn, flush_unissued, flush, instruction, fetch_valid, fetch_ack, issue_ack, issue_sbe, waddr, st_valid, st_paddr, ld_valid, ld_kill, ld_paddr, resolve_branch, wdata, we_gpr, we_fpr, commit_instr, commit_ack, exception, priv_lvl, debug_mode; endclocking - `endif + //pragma translate_on endinterface `endif diff --git a/src/util/instruction_tracer_pkg.sv b/src/util/instruction_tracer_pkg.sv index 74fa56efa8..f17d6c88cd 100644 --- a/src/util/instruction_tracer_pkg.sv +++ b/src/util/instruction_tracer_pkg.sv @@ -15,12 +15,13 @@ package instruction_tracer_pkg; import ariane_pkg::*; - `ifndef SYNTHESIS + //pragma translate_off import uvm_pkg::*; `include "uvm_macros.svh" `include "instruction_tracer_defines.svh" `include "instruction_trace_item.svh" `include "exception_trace_item.svh" `include "instruction_tracer.svh" - `endif + //pragma translate_on + endpackage diff --git a/src/util/sram.sv b/src/util/sram.sv index 0f794e75fb..3ed089885a 100644 --- a/src/util/sram.sv +++ b/src/util/sram.sv @@ -13,15 +13,15 @@ // Date: 15.08.2018 // Description: SRAM wrapper for FPGA (requires the fpga-support submodule) // -// Note: the wrapped module contains two different implementations for -// ALTERA and XILINX tools, since these follow different coding styles for -// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or +// Note: the wrapped module contains two different implementations for +// ALTERA and XILINX tools, since these follow different coding styles for +// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or // `FPGA_TARGET_ALTERA in your build environment (default is ALTERA) - + module sram #( parameter DATA_WIDTH = 64, parameter NUM_WORDS = 1024, - parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2) + parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2) )( input logic clk_i, input logic rst_ni, @@ -52,23 +52,24 @@ end genvar k; generate - for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin + for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin // unused byte-enable segments (8bits) are culled by the tool SyncSpRamBeNx64 #( .ADDR_WIDTH($clog2(NUM_WORDS)), - .DATA_DEPTH(NUM_WORDS), - .OUT_REGS (0) + .DATA_DEPTH(NUM_WORDS), + .OUT_REGS (0), + .SIM_INIT (2) ) i_ram ( .Clk_CI ( clk_i ), .Rst_RBI ( rst_ni ), .CSel_SI ( req_i ), .WrEn_SI ( we_i ), .BEn_SI ( be_aligned[k*8 +: 8] ), - .WrData_DI ( wdata_aligned[k*64 +: 64] ), - .Addr_DI ( addr_i ), + .WrData_DI ( wdata_aligned[k*64 +: 64] ), + .Addr_DI ( addr_i ), .RdData_DO ( rdata_aligned[k*64 +: 64] ) - ); - end + ); + end endgenerate endmodule : sram diff --git a/src_files.yml b/src_files.yml index 7e6ee93705..a5e7fd259d 100644 --- a/src_files.yml +++ b/src_files.yml @@ -32,8 +32,7 @@ ariane: src/issue_stage.sv, src/lfsr.sv, src/load_unit.sv, - src/lsu_arbiter.sv, - src/lsu.sv, + src/load_store_unit.sv, src/miss_handler.sv, src/mmu.sv, src/mult.sv, diff --git a/tb/ariane_peripherals.sv b/tb/ariane_peripherals.sv new file mode 100644 index 0000000000..89309cff49 --- /dev/null +++ b/tb/ariane_peripherals.sv @@ -0,0 +1,667 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Xilinx Peripehrals +module ariane_peripherals #( + parameter int AxiAddrWidth = -1, + parameter int AxiDataWidth = -1, + parameter int AxiIdWidth = -1, + parameter int AxiUserWidth = 1, + parameter bit InclUART = 1, + parameter bit InclSPI = 0, + parameter bit InclEthernet = 0, + parameter bit InclGPIO = 0 +) ( + input logic clk_i , // Clock + input logic rst_ni , // Asynchronous reset active low + AXI_BUS.in plic , + AXI_BUS.in uart , + AXI_BUS.in spi , + AXI_BUS.in ethernet , + output logic [1:0] irq_o , + // UART + input logic rx_i , + output logic tx_o , + // Ethernet + input wire eth_txck , + input wire eth_rxck , + input wire eth_rxctl , + input wire [3:0] eth_rxd , + output wire eth_rst_n , + output wire eth_tx_en , + output wire [3:0] eth_txd , + inout wire phy_mdio , + output logic eth_mdc , + // MDIO Interface + inout mdio , + output mdc , + // SPI + output logic spi_clk_o , + output logic spi_mosi , + input logic spi_miso , + output logic spi_ss +); + + // --------------- + // 1. PLIC + // --------------- + logic [ariane_soc::NumSources-1:0] irq_sources; + + REG_BUS #( + .ADDR_WIDTH ( 32 ), + .DATA_WIDTH ( 32 ) + ) reg_bus (clk_i); + + logic plic_penable; + logic plic_pwrite; + logic [31:0] plic_paddr; + logic plic_psel; + logic [31:0] plic_pwdata; + logic [31:0] plic_prdata; + logic plic_pready; + logic plic_pslverr; + + axi2apb_64_32 #( + .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ), + .AXI4_RDATA_WIDTH ( AxiDataWidth ), + .AXI4_WDATA_WIDTH ( AxiDataWidth ), + .AXI4_ID_WIDTH ( AxiIdWidth ), + .AXI4_USER_WIDTH ( AxiUserWidth ), + .BUFF_DEPTH_SLAVE ( 2 ), + .APB_ADDR_WIDTH ( 32 ) + ) i_axi2apb_64_32_plic ( + .ACLK ( clk_i ), + .ARESETn ( rst_ni ), + .test_en_i ( 1'b0 ), + .AWID_i ( plic.aw_id ), + .AWADDR_i ( plic.aw_addr ), + .AWLEN_i ( plic.aw_len ), + .AWSIZE_i ( plic.aw_size ), + .AWBURST_i ( plic.aw_burst ), + .AWLOCK_i ( plic.aw_lock ), + .AWCACHE_i ( plic.aw_cache ), + .AWPROT_i ( plic.aw_prot ), + .AWREGION_i( plic.aw_region ), + .AWUSER_i ( plic.aw_user ), + .AWQOS_i ( plic.aw_qos ), + .AWVALID_i ( plic.aw_valid ), + .AWREADY_o ( plic.aw_ready ), + .WDATA_i ( plic.w_data ), + .WSTRB_i ( plic.w_strb ), + .WLAST_i ( plic.w_last ), + .WUSER_i ( plic.w_user ), + .WVALID_i ( plic.w_valid ), + .WREADY_o ( plic.w_ready ), + .BID_o ( plic.b_id ), + .BRESP_o ( plic.b_resp ), + .BVALID_o ( plic.b_valid ), + .BUSER_o ( plic.b_user ), + .BREADY_i ( plic.b_ready ), + .ARID_i ( plic.ar_id ), + .ARADDR_i ( plic.ar_addr ), + .ARLEN_i ( plic.ar_len ), + .ARSIZE_i ( plic.ar_size ), + .ARBURST_i ( plic.ar_burst ), + .ARLOCK_i ( plic.ar_lock ), + .ARCACHE_i ( plic.ar_cache ), + .ARPROT_i ( plic.ar_prot ), + .ARREGION_i( plic.ar_region ), + .ARUSER_i ( plic.ar_user ), + .ARQOS_i ( plic.ar_qos ), + .ARVALID_i ( plic.ar_valid ), + .ARREADY_o ( plic.ar_ready ), + .RID_o ( plic.r_id ), + .RDATA_o ( plic.r_data ), + .RRESP_o ( plic.r_resp ), + .RLAST_o ( plic.r_last ), + .RUSER_o ( plic.r_user ), + .RVALID_o ( plic.r_valid ), + .RREADY_i ( plic.r_ready ), + .PENABLE ( plic_penable ), + .PWRITE ( plic_pwrite ), + .PADDR ( plic_paddr ), + .PSEL ( plic_psel ), + .PWDATA ( plic_pwdata ), + .PRDATA ( plic_prdata ), + .PREADY ( plic_pready ), + .PSLVERR ( plic_pslverr ) + ); + + apb_to_reg i_apb_to_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .penable_i ( plic_penable ), + .pwrite_i ( plic_pwrite ), + .paddr_i ( plic_paddr ), + .psel_i ( plic_psel ), + .pwdata_i ( plic_pwdata ), + .prdata_o ( plic_prdata ), + .pready_o ( plic_pready ), + .pslverr_o ( plic_pslverr ), + .reg_o ( reg_bus ) + ); + + plic #( + .ID_BITWIDTH ( ariane_soc::PLICIdWidth ), + .PARAMETER_BITWIDTH ( ariane_soc::ParameterBitwidth ), + .NUM_TARGETS ( ariane_soc::NumTargets ), + .NUM_SOURCES ( ariane_soc::NumSources ) + ) i_plic ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .irq_sources_i ( irq_sources ), + .eip_targets_o ( irq_o ), + .external_bus_io ( reg_bus ) + ); + + // --------------- + // 2. UART + // --------------- + logic uart_penable; + logic uart_pwrite; + logic [31:0] uart_paddr; + logic uart_psel; + logic [31:0] uart_pwdata; + logic [31:0] uart_prdata; + logic uart_pready; + logic uart_pslverr; + + axi2apb_64_32 #( + .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ), + .AXI4_RDATA_WIDTH ( AxiDataWidth ), + .AXI4_WDATA_WIDTH ( AxiDataWidth ), + .AXI4_ID_WIDTH ( AxiIdWidth ), + .AXI4_USER_WIDTH ( AxiUserWidth ), + .BUFF_DEPTH_SLAVE ( 2 ), + .APB_ADDR_WIDTH ( 32 ) + ) i_axi2apb_64_32_uart ( + .ACLK ( clk_i ), + .ARESETn ( rst_ni ), + .test_en_i ( 1'b0 ), + .AWID_i ( uart.aw_id ), + .AWADDR_i ( uart.aw_addr ), + .AWLEN_i ( uart.aw_len ), + .AWSIZE_i ( uart.aw_size ), + .AWBURST_i ( uart.aw_burst ), + .AWLOCK_i ( uart.aw_lock ), + .AWCACHE_i ( uart.aw_cache ), + .AWPROT_i ( uart.aw_prot ), + .AWREGION_i( uart.aw_region ), + .AWUSER_i ( uart.aw_user ), + .AWQOS_i ( uart.aw_qos ), + .AWVALID_i ( uart.aw_valid ), + .AWREADY_o ( uart.aw_ready ), + .WDATA_i ( uart.w_data ), + .WSTRB_i ( uart.w_strb ), + .WLAST_i ( uart.w_last ), + .WUSER_i ( uart.w_user ), + .WVALID_i ( uart.w_valid ), + .WREADY_o ( uart.w_ready ), + .BID_o ( uart.b_id ), + .BRESP_o ( uart.b_resp ), + .BVALID_o ( uart.b_valid ), + .BUSER_o ( uart.b_user ), + .BREADY_i ( uart.b_ready ), + .ARID_i ( uart.ar_id ), + .ARADDR_i ( uart.ar_addr ), + .ARLEN_i ( uart.ar_len ), + .ARSIZE_i ( uart.ar_size ), + .ARBURST_i ( uart.ar_burst ), + .ARLOCK_i ( uart.ar_lock ), + .ARCACHE_i ( uart.ar_cache ), + .ARPROT_i ( uart.ar_prot ), + .ARREGION_i( uart.ar_region ), + .ARUSER_i ( uart.ar_user ), + .ARQOS_i ( uart.ar_qos ), + .ARVALID_i ( uart.ar_valid ), + .ARREADY_o ( uart.ar_ready ), + .RID_o ( uart.r_id ), + .RDATA_o ( uart.r_data ), + .RRESP_o ( uart.r_resp ), + .RLAST_o ( uart.r_last ), + .RUSER_o ( uart.r_user ), + .RVALID_o ( uart.r_valid ), + .RREADY_i ( uart.r_ready ), + .PENABLE ( uart_penable ), + .PWRITE ( uart_pwrite ), + .PADDR ( uart_paddr ), + .PSEL ( uart_psel ), + .PWDATA ( uart_pwdata ), + .PRDATA ( uart_prdata ), + .PREADY ( uart_pready ), + .PSLVERR ( uart_pslverr ) + ); + + if (InclUART) begin : gen_uart + apb_uart i_apb_uart ( + .CLK ( clk_i ), + .RSTN ( rst_ni ), + .PSEL ( uart_psel ), + .PENABLE ( uart_penable ), + .PWRITE ( uart_pwrite ), + .PADDR ( uart_paddr[4:2] ), + .PWDATA ( uart_pwdata ), + .PRDATA ( uart_prdata ), + .PREADY ( uart_pready ), + .PSLVERR ( uart_pslverr ), + .INT ( irq_sources[2] ), + .OUT1N ( ), // keep open + .OUT2N ( ), // keep open + .RTSN ( ), // no flow control + .DTRN ( ), // no flow control + .CTSN ( 1'b0 ), + .DSRN ( 1'b0 ), + .DCDN ( 1'b0 ), + .RIN ( 1'b0 ), + .SIN ( rx_i ), + .SOUT ( tx_o ) + ); + end else begin + /* pragma translate_off */ + `ifndef VERILATOR + mock_uart i_mock_uart ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .penable_i ( uart_penable ), + .pwrite_i ( uart_pwrite ), + .paddr_i ( uart_paddr ), + .psel_i ( uart_psel ), + .pwdata_i ( uart_pwdata ), + .prdata_o ( uart_prdata ), + .pready_o ( uart_pready ), + .pslverr_o ( uart_pslverr ) + ); + `endif + /* pragma translate_on */ + end + + // --------------- + // 3. SPI + // --------------- + if (InclSPI) begin : gen_spi + logic [31:0] s_axi_spi_awaddr; + logic [7:0] s_axi_spi_awlen; + logic [2:0] s_axi_spi_awsize; + logic [1:0] s_axi_spi_awburst; + logic [0:0] s_axi_spi_awlock; + logic [3:0] s_axi_spi_awcache; + logic [2:0] s_axi_spi_awprot; + logic [3:0] s_axi_spi_awregion; + logic [3:0] s_axi_spi_awqos; + logic s_axi_spi_awvalid; + logic s_axi_spi_awready; + logic [31:0] s_axi_spi_wdata; + logic [3:0] s_axi_spi_wstrb; + logic s_axi_spi_wlast; + logic s_axi_spi_wvalid; + logic s_axi_spi_wready; + logic [1:0] s_axi_spi_bresp; + logic s_axi_spi_bvalid; + logic s_axi_spi_bready; + logic [31:0] s_axi_spi_araddr; + logic [7:0] s_axi_spi_arlen; + logic [2:0] s_axi_spi_arsize; + logic [1:0] s_axi_spi_arburst; + logic [0:0] s_axi_spi_arlock; + logic [3:0] s_axi_spi_arcache; + logic [2:0] s_axi_spi_arprot; + logic [3:0] s_axi_spi_arregion; + logic [3:0] s_axi_spi_arqos; + logic s_axi_spi_arvalid; + logic s_axi_spi_arready; + logic [31:0] s_axi_spi_rdata; + logic [1:0] s_axi_spi_rresp; + logic s_axi_spi_rlast; + logic s_axi_spi_rvalid; + logic s_axi_spi_rready; + + xlnx_axi_clock_converter i_xlnx_axi_clock_converter_spi ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + + .s_axi_awid ( spi.aw_id ), + .s_axi_awaddr ( spi.aw_addr[31:0] ), + .s_axi_awlen ( spi.aw_len ), + .s_axi_awsize ( spi.aw_size ), + .s_axi_awburst ( spi.aw_burst ), + .s_axi_awlock ( spi.aw_lock ), + .s_axi_awcache ( spi.aw_cache ), + .s_axi_awprot ( spi.aw_prot ), + .s_axi_awregion ( spi.aw_region ), + .s_axi_awqos ( spi.aw_qos ), + .s_axi_awvalid ( spi.aw_valid ), + .s_axi_awready ( spi.aw_ready ), + .s_axi_wdata ( spi.w_data ), + .s_axi_wstrb ( spi.w_strb ), + .s_axi_wlast ( spi.w_last ), + .s_axi_wvalid ( spi.w_valid ), + .s_axi_wready ( spi.w_ready ), + .s_axi_bid ( spi.b_id ), + .s_axi_bresp ( spi.b_resp ), + .s_axi_bvalid ( spi.b_valid ), + .s_axi_bready ( spi.b_ready ), + .s_axi_arid ( spi.ar_id ), + .s_axi_araddr ( spi.ar_addr[31:0] ), + .s_axi_arlen ( spi.ar_len ), + .s_axi_arsize ( spi.ar_size ), + .s_axi_arburst ( spi.ar_burst ), + .s_axi_arlock ( spi.ar_lock ), + .s_axi_arcache ( spi.ar_cache ), + .s_axi_arprot ( spi.ar_prot ), + .s_axi_arregion ( spi.ar_region ), + .s_axi_arqos ( spi.ar_qos ), + .s_axi_arvalid ( spi.ar_valid ), + .s_axi_arready ( spi.ar_ready ), + .s_axi_rid ( spi.r_id ), + .s_axi_rdata ( spi.r_data ), + .s_axi_rresp ( spi.r_resp ), + .s_axi_rlast ( spi.r_last ), + .s_axi_rvalid ( spi.r_valid ), + .s_axi_rready ( spi.r_ready ), + + .m_axi_awaddr ( s_axi_spi_awaddr ), + .m_axi_awlen ( s_axi_spi_awlen ), + .m_axi_awsize ( s_axi_spi_awsize ), + .m_axi_awburst ( s_axi_spi_awburst ), + .m_axi_awlock ( s_axi_spi_awlock ), + .m_axi_awcache ( s_axi_spi_awcache ), + .m_axi_awprot ( s_axi_spi_awprot ), + .m_axi_awregion ( s_axi_spi_awregion ), + .m_axi_awqos ( s_axi_spi_awqos ), + .m_axi_awvalid ( s_axi_spi_awvalid ), + .m_axi_awready ( s_axi_spi_awready ), + .m_axi_wdata ( s_axi_spi_wdata ), + .m_axi_wstrb ( s_axi_spi_wstrb ), + .m_axi_wlast ( s_axi_spi_wlast ), + .m_axi_wvalid ( s_axi_spi_wvalid ), + .m_axi_wready ( s_axi_spi_wready ), + .m_axi_bresp ( s_axi_spi_bresp ), + .m_axi_bvalid ( s_axi_spi_bvalid ), + .m_axi_bready ( s_axi_spi_bready ), + .m_axi_araddr ( s_axi_spi_araddr ), + .m_axi_arlen ( s_axi_spi_arlen ), + .m_axi_arsize ( s_axi_spi_arsize ), + .m_axi_arburst ( s_axi_spi_arburst ), + .m_axi_arlock ( s_axi_spi_arlock ), + .m_axi_arcache ( s_axi_spi_arcache ), + .m_axi_arprot ( s_axi_spi_arprot ), + .m_axi_arregion ( s_axi_spi_arregion ), + .m_axi_arqos ( s_axi_spi_arqos ), + .m_axi_arvalid ( s_axi_spi_arvalid ), + .m_axi_arready ( s_axi_spi_arready ), + .m_axi_rdata ( s_axi_spi_rdata ), + .m_axi_rresp ( s_axi_spi_rresp ), + .m_axi_rlast ( s_axi_spi_rlast ), + .m_axi_rvalid ( s_axi_spi_rvalid ), + .m_axi_rready ( s_axi_spi_rready ) + ); + + xlnx_axi_quad_spi i_xlnx_axi_quad_spi ( + .ext_spi_clk ( clk_i ), + .s_axi4_aclk ( clk_i ), + .s_axi4_aresetn ( rst_ni ), + .s_axi4_awaddr ( s_axi_spi_awaddr[23:0] ), + .s_axi4_awlen ( s_axi_spi_awlen ), + .s_axi4_awsize ( s_axi_spi_awsize ), + .s_axi4_awburst ( s_axi_spi_awburst ), + .s_axi4_awlock ( s_axi_spi_awlock ), + .s_axi4_awcache ( s_axi_spi_awcache ), + .s_axi4_awprot ( s_axi_spi_awprot ), + .s_axi4_awvalid ( s_axi_spi_awvalid ), + .s_axi4_awready ( s_axi_spi_awready ), + .s_axi4_wdata ( s_axi_spi_wdata ), + .s_axi4_wstrb ( s_axi_spi_wstrb ), + .s_axi4_wlast ( s_axi_spi_wlast ), + .s_axi4_wvalid ( s_axi_spi_wvalid ), + .s_axi4_wready ( s_axi_spi_wready ), + .s_axi4_bresp ( s_axi_spi_bresp ), + .s_axi4_bvalid ( s_axi_spi_bvalid ), + .s_axi4_bready ( s_axi_spi_bready ), + .s_axi4_araddr ( s_axi_spi_araddr[23:0] ), + .s_axi4_arlen ( s_axi_spi_arlen ), + .s_axi4_arsize ( s_axi_spi_arsize ), + .s_axi4_arburst ( s_axi_spi_arburst ), + .s_axi4_arlock ( s_axi_spi_arlock ), + .s_axi4_arcache ( s_axi_spi_arcache ), + .s_axi4_arprot ( s_axi_spi_arprot ), + .s_axi4_arvalid ( s_axi_spi_arvalid ), + .s_axi4_arready ( s_axi_spi_arready ), + .s_axi4_rdata ( s_axi_spi_rdata ), + .s_axi4_rresp ( s_axi_spi_rresp ), + .s_axi4_rlast ( s_axi_spi_rlast ), + .s_axi4_rvalid ( s_axi_spi_rvalid ), + .s_axi4_rready ( s_axi_spi_rready ), + + .io0_i ( '0 ), + .io0_o ( spi_mosi ), + .io0_t ( '0 ), + .io1_i ( spi_miso ), + .io1_o ( ), + .io1_t ( '0 ), + .ss_i ( '0 ), + .ss_o ( spi_ss ), + .ss_t ( '0 ), + .sck_o ( spi_clk_o ), + .sck_i ( '0 ), + .sck_t ( ), + .ip2intc_irpt ( irq_sources[1] ) + // .ip2intc_irpt ( irq_sources[1] ) + ); + // assign irq_sources [1] = 1'b0; + end else begin + assign spi_clk_o = 1'b0; + assign spi_mosi = 1'b0; + assign spi_ss = 1'b0; + + assign irq_sources [1] = 1'b0; + assign spi.aw_ready = 1'b1; + assign spi.ar_ready = 1'b1; + assign spi.w_ready = 1'b1; + + assign spi.b_valid = spi.aw_valid; + assign spi.b_id = spi.aw_id; + assign spi.b_resp = axi_pkg::RESP_SLVERR; + assign spi.b_user = '0; + + assign spi.r_valid = spi.ar_valid; + assign spi.r_resp = axi_pkg::RESP_SLVERR; + assign spi.r_data = 'hdeadbeef; + assign spi.r_last = 1'b1; + end + + + // --------------- + // 4. Ethernet + // --------------- + if (InclEthernet) begin : gen_ethernet + wire mdio_i, mdio_o, mdio_t; + logic [3:0] s_axi_eth_awid; + logic [31:0] s_axi_eth_awaddr; + logic [7:0] s_axi_eth_awlen; + logic [2:0] s_axi_eth_awsize; + logic [1:0] s_axi_eth_awburst; + logic [3:0] s_axi_eth_awcache; + logic s_axi_eth_awvalid; + logic s_axi_eth_awready; + logic [31:0] s_axi_eth_wdata; + logic [3:0] s_axi_eth_wstrb; + logic s_axi_eth_wlast; + logic s_axi_eth_wvalid; + logic s_axi_eth_wready; + logic [3:0] s_axi_eth_bid; + logic [1:0] s_axi_eth_bresp; + logic s_axi_eth_bvalid; + logic s_axi_eth_bready; + logic [3:0] s_axi_eth_arid; + logic [31:0] s_axi_eth_araddr; + logic [7:0] s_axi_eth_arlen; + logic [2:0] s_axi_eth_arsize; + logic [1:0] s_axi_eth_arburst; + logic [3:0] s_axi_eth_arcache; + logic s_axi_eth_arvalid; + logic s_axi_eth_arready; + logic [3:0] s_axi_eth_rid; + logic [31:0] s_axi_eth_rdata; + logic [1:0] s_axi_eth_rresp; + logic s_axi_eth_rlast; + logic s_axi_eth_rvalid; + + assign s_axi_eth_awid = '0; + assign s_axi_eth_arid = '0; + + // system-bus is 64-bit, convert down to 32 bit + xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ethernet ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + .s_axi_awid ( ethernet.aw_id ), + .s_axi_awaddr ( ethernet.aw_addr[31:0] ), + .s_axi_awlen ( ethernet.aw_len ), + .s_axi_awsize ( ethernet.aw_size ), + .s_axi_awburst ( ethernet.aw_burst ), + .s_axi_awlock ( ethernet.aw_lock ), + .s_axi_awcache ( ethernet.aw_cache ), + .s_axi_awprot ( ethernet.aw_prot ), + .s_axi_awregion ( ethernet.aw_region ), + .s_axi_awqos ( ethernet.aw_qos ), + .s_axi_awvalid ( ethernet.aw_valid ), + .s_axi_awready ( ethernet.aw_ready ), + .s_axi_wdata ( ethernet.w_data ), + .s_axi_wstrb ( ethernet.w_strb ), + .s_axi_wlast ( ethernet.w_last ), + .s_axi_wvalid ( ethernet.w_valid ), + .s_axi_wready ( ethernet.w_ready ), + .s_axi_bid ( ethernet.b_id ), + .s_axi_bresp ( ethernet.b_resp ), + .s_axi_bvalid ( ethernet.b_valid ), + .s_axi_bready ( ethernet.b_ready ), + .s_axi_arid ( ethernet.ar_id ), + .s_axi_araddr ( ethernet.ar_addr[31:0] ), + .s_axi_arlen ( ethernet.ar_len ), + .s_axi_arsize ( ethernet.ar_size ), + .s_axi_arburst ( ethernet.ar_burst ), + .s_axi_arlock ( ethernet.ar_lock ), + .s_axi_arcache ( ethernet.ar_cache ), + .s_axi_arprot ( ethernet.ar_prot ), + .s_axi_arregion ( ethernet.ar_region ), + .s_axi_arqos ( ethernet.ar_qos ), + .s_axi_arvalid ( ethernet.ar_valid ), + .s_axi_arready ( ethernet.ar_ready ), + .s_axi_rid ( ethernet.r_id ), + .s_axi_rdata ( ethernet.r_data ), + .s_axi_rresp ( ethernet.r_resp ), + .s_axi_rlast ( ethernet.r_last ), + .s_axi_rvalid ( ethernet.r_valid ), + .s_axi_rready ( ethernet.r_ready ), + + .m_axi_awaddr ( s_axi_eth_awaddr ), + .m_axi_awlen ( s_axi_eth_awlen ), + .m_axi_awsize ( s_axi_eth_awsize ), + .m_axi_awburst ( s_axi_eth_awburst ), + .m_axi_awlock ( ), + .m_axi_awcache ( s_axi_eth_awcache ), + .m_axi_awprot ( ), + .m_axi_awregion ( ), + .m_axi_awqos ( ), + .m_axi_awvalid ( s_axi_eth_awvalid ), + .m_axi_awready ( s_axi_eth_awready ), + .m_axi_wdata ( s_axi_eth_wdata ), + .m_axi_wstrb ( s_axi_eth_wstrb ), + .m_axi_wlast ( s_axi_eth_wlast ), + .m_axi_wvalid ( s_axi_eth_wvalid ), + .m_axi_wready ( s_axi_eth_wready ), + .m_axi_bresp ( s_axi_eth_bresp ), + .m_axi_bvalid ( s_axi_eth_bvalid ), + .m_axi_bready ( s_axi_eth_bready ), + .m_axi_araddr ( s_axi_eth_araddr ), + .m_axi_arlen ( s_axi_eth_arlen ), + .m_axi_arsize ( s_axi_eth_arsize ), + .m_axi_arburst ( s_axi_eth_arburst ), + .m_axi_arlock ( ), + .m_axi_arcache ( s_axi_eth_arcache ), + .m_axi_arprot ( ), + .m_axi_arregion ( ), + .m_axi_arqos ( ), + .m_axi_arvalid ( s_axi_eth_arvalid ), + .m_axi_arready ( s_axi_eth_arready ), + .m_axi_rdata ( s_axi_eth_rdata ), + .m_axi_rresp ( s_axi_eth_rresp ), + .m_axi_rlast ( s_axi_eth_rlast ), + .m_axi_rvalid ( s_axi_eth_rvalid ), + .m_axi_rready ( m_axi_rready ) + ); + + xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + .ip2intc_irpt ( irq_sources[0] ), + .s_axi_awid ( s_axi_eth_awid ), + .s_axi_awaddr ( s_axi_eth_awaddr[12:0] ), + .s_axi_awlen ( s_axi_eth_awlen ), + .s_axi_awsize ( s_axi_eth_awsize ), + .s_axi_awburst ( s_axi_eth_awburst ), + .s_axi_awcache ( s_axi_eth_awcache ), + .s_axi_awvalid ( s_axi_eth_awvalid ), + .s_axi_awready ( s_axi_eth_awready ), + .s_axi_wdata ( s_axi_eth_wdata ), + .s_axi_wstrb ( s_axi_eth_wstrb ), + .s_axi_wlast ( s_axi_eth_wlast ), + .s_axi_wvalid ( s_axi_eth_wvalid ), + .s_axi_wready ( s_axi_eth_wready ), + .s_axi_bid ( s_axi_eth_bid ), + .s_axi_bresp ( s_axi_eth_bresp ), + .s_axi_bvalid ( s_axi_eth_bvalid ), + .s_axi_bready ( s_axi_eth_bready ), + .s_axi_arid ( s_axi_eth_arid ), + .s_axi_araddr ( s_axi_eth_araddr[12:0] ), + .s_axi_arlen ( s_axi_eth_arlen ), + .s_axi_arsize ( s_axi_eth_arsize ), + .s_axi_arburst ( s_axi_eth_arburst ), + .s_axi_arcache ( s_axi_eth_arcache ), + .s_axi_arvalid ( s_axi_eth_arvalid ), + .s_axi_arready ( s_axi_eth_arready ), + .s_axi_rid ( s_axi_eth_rid ), + .s_axi_rdata ( s_axi_eth_rdata ), + .s_axi_rresp ( s_axi_eth_rresp ), + .s_axi_rlast ( s_axi_eth_rlast ), + .s_axi_rvalid ( s_axi_eth_rvalid ), + .s_axi_rready ( s_axi_eth_rready ), + .phy_tx_clk ( eth_txck ), + .phy_rx_clk ( eth_rxck ), + .phy_crs ( 1'b0 ), + .phy_dv ( eth_rxctl ), + .phy_rx_data ( eth_rxd ), + .phy_col ( 1'b0 ), + .phy_rx_er ( 1'b0 ), + .phy_rst_n ( eth_rst_n ), + .phy_tx_en ( eth_tx_en ), + .phy_tx_data ( eth_txd ), + .phy_mdio_i ( mdio_i ), + .phy_mdio_o ( mdio_o ), + .phy_mdio_t ( mdio_t ), + .phy_mdc ( eth_mdc ) + ); + IOBUF mdio_io_iobuf (.I (mdio_o), .IO(mdio), .O (mdio_i), .T (mdio_t)); + end else begin + assign irq_sources [2] = 1'b0; + assign ethernet.aw_ready = 1'b1; + assign ethernet.ar_ready = 1'b1; + assign ethernet.w_ready = 1'b1; + + assign ethernet.b_valid = ethernet.aw_valid; + assign ethernet.b_id = ethernet.aw_id; + assign ethernet.b_resp = axi_pkg::RESP_SLVERR; + assign ethernet.b_user = '0; + + assign ethernet.r_valid = ethernet.ar_valid; + assign ethernet.r_resp = axi_pkg::RESP_SLVERR; + assign ethernet.r_data = 'hdeadbeef; + assign ethernet.r_last = 1'b1; + end +endmodule diff --git a/tb/ariane_soc_pkg.sv b/tb/ariane_soc_pkg.sv new file mode 100644 index 0000000000..5e7f24902f --- /dev/null +++ b/tb/ariane_soc_pkg.sv @@ -0,0 +1,60 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Description: Contains SoC information as constants +package ariane_soc; + // M-Mode Hart, S-Mode Hart + localparam NumTargets = 2; + // Uart, SPI, Ethernet + localparam NumSources = 3; + localparam PLICIdWidth = 3; + localparam ParameterBitwidth = PLICIdWidth; + + typedef enum int unsigned { + DRAM = 0, + GPIO = 1, + Ethernet = 2, + SPI = 3, + UART = 4, + PLIC = 5, + CLINT = 6, + ROM = 7, + Debug = 8 + } axi_slaves_t; + + localparam NB_PERIPHERALS = Debug + 1; + + localparam logic[63:0] DebugLength = 64'h1000; + localparam logic[63:0] ROMLength = 64'h10000; + localparam logic[63:0] CLINTLength = 64'hC0000; + localparam logic[63:0] PLICLength = 64'h3FF_FFFF; + localparam logic[63:0] UARTLength = 64'h1000; + localparam logic[63:0] SPILength = 64'h800000; + localparam logic[63:0] EthernetLength = 64'h10000; + localparam logic[63:0] GPIOLength = 64'h1000; + localparam logic[63:0] DRAMLength = 64'h8000000; // 128 MByte of DDR + localparam logic[63:0] SRAMLength = 64'h1800000; // 24 MByte of SRAM + // Instantiate AXI protocol checkers + localparam bit GenProtocolChecker = 1'b0; + + typedef enum logic [63:0] { + DebugBase = 64'h0000_0000, + ROMBase = 64'h0001_0000, + CLINTBase = 64'h0200_0000, + PLICBase = 64'h0C00_0000, + UARTBase = 64'h1000_0000, + SPIBase = 64'h2000_0000, + EthernetBase = 64'h3000_0000, + GPIOBase = 64'h4000_0000, + DRAMBase = 64'h8000_0000 + } soc_bus_start_t; + +endpackage diff --git a/tb/ariane_tb.cpp b/tb/ariane_tb.cpp index 0a5ad92529..c64c4db6b0 100644 --- a/tb/ariane_tb.cpp +++ b/tb/ariane_tb.cpp @@ -265,6 +265,7 @@ int main(int argc, char **argv) { for (int i = 0; i < 10; i++) { top->rst_ni = 0; top->clk_i = 0; + top->rtc_i = 0; top->eval(); #if VM_TRACE tfp->dump(static_cast(main_time * 2)); @@ -274,11 +275,11 @@ int main(int argc, char **argv) { #if VM_TRACE tfp->dump(static_cast(main_time * 2 + 1)); #endif - main_time ++; + main_time++; } top->rst_ni = 1; -while (!dtm->done() && !jtag->done()) { + while (!dtm->done() && !jtag->done()) { top->clk_i = 0; top->eval(); #if VM_TRACE @@ -293,6 +294,10 @@ while (!dtm->done() && !jtag->done()) { // if (dump) tfp->dump(static_cast(main_time * 2 + 1)); #endif + // toggle RTC + if (main_time % 2 == 0) { + top->rtc_i ^= 1; + } main_time++; } diff --git a/tb/ariane_tb.sv b/tb/ariane_tb.sv index 65dd9fd0f1..e4a6668773 100644 --- a/tb/ariane_tb.sv +++ b/tb/ariane_tb.sv @@ -19,23 +19,41 @@ import uvm_pkg::*; `include "uvm_macros.svh" +`define MAIN_MEM(P) dut.i_sram.genblk1[0].i_ram.Mem_DP[(``P``)] + +import "DPI-C" function read_elf(input string filename); +import "DPI-C" function byte get_section(output longint address, output longint len); +import "DPI-C" context function byte read_section(input longint address, inout byte buffer[]); + module ariane_tb; - // static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); + static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); localparam int unsigned CLOCK_PERIOD = 20ns; + // toggle with RTC period + localparam int unsigned RTC_CLOCK_PERIOD = 30.517us; + localparam NUM_WORDS = 2**25; logic clk_i; logic rst_ni; + logic rtc_i; longint unsigned cycles; longint unsigned max_cycles; logic [31:0] exit_o; - ariane_testharness dut ( + string binary = ""; + + ariane_testharness #( + .NUM_WORDS ( NUM_WORDS ), + .InclSimDTM ( 1'b1 ), + .StallRandomOutput ( 1'b1 ), + .StallRandomInput ( 1'b1 ) + ) dut ( .clk_i, .rst_ni, + .rtc_i, .exit_o ); @@ -57,6 +75,14 @@ module ariane_tb; end end + initial begin + forever begin + rtc_i = 1'b0; + #(RTC_CLOCK_PERIOD/2) rtc_i = 1'b1; + #(RTC_CLOCK_PERIOD/2) rtc_i = 1'b0; + end + end + initial begin forever begin @@ -72,4 +98,38 @@ module ariane_tb; end end + // for faster simulation we can directly preload the ELF + // Note that we are loosing the capabilities to use risc-fesvr though + initial begin + automatic logic [7:0][7:0] mem_row; + longint address, len; + byte buffer[]; + void'(uvcl.get_arg_value("+PRELOAD=", binary)); + + if (binary != "") begin + `uvm_info( "Core Test", $sformatf("Preloading ELF: %s", binary), UVM_LOW) + + void'(read_elf(binary)); + // wait with preloading, otherwise randomization will overwrite the existing value + wait(rst_ni); + + // while there are more sections to process + while (get_section(address, len)) begin + `uvm_info( "Core Test", $sformatf("Loading Address: %x, Length: %x", address, len), UVM_LOW) + buffer = new [len]; + void'(read_section(address, buffer)); + // preload memories + // 64-bit + for (int i = 0; i < buffer.size()/8; i++) begin + mem_row = '0; + for (int j = 0; j < 8; j++) begin + mem_row[j] = buffer[i*8 + j]; + end + + `MAIN_MEM((address[28:0] >> 3) + i) = mem_row; + end + end + end + end + endmodule diff --git a/tb/ariane_testharness.sv b/tb/ariane_testharness.sv index 66103be8bf..212c3cebbc 100644 --- a/tb/ariane_testharness.sv +++ b/tb/ariane_testharness.sv @@ -14,14 +14,17 @@ // Instantiates an AXI-Bus and memories module ariane_testharness #( - parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not - parameter int unsigned AXI_ID_WIDTH = 10, + parameter int unsigned AXI_ID_WIDTH = 4, parameter int unsigned AXI_USER_WIDTH = 1, parameter int unsigned AXI_ADDRESS_WIDTH = 64, parameter int unsigned AXI_DATA_WIDTH = 64, - parameter int unsigned NUM_WORDS = 2**24 // memory size -)( + parameter bit InclSimDTM = 1'b1, + parameter int unsigned NUM_WORDS = 2**25, // memory size + parameter bit StallRandomOutput = 1'b0, + parameter bit StallRandomInput = 1'b0 +) ( input logic clk_i, + input logic rtc_i, input logic rst_ni, output logic [31:0] exit_o ); @@ -47,8 +50,6 @@ module ariane_testharness #( logic debug_req_ready; logic debug_resp_valid; logic debug_resp_ready; - logic [1:0] debug_resp_bits_resp; - logic [31:0] debug_resp_bits_data; logic jtag_req_valid; logic [6:0] jtag_req_bits_addr; @@ -58,20 +59,18 @@ module ariane_testharness #( logic jtag_resp_valid; logic dmi_req_valid; - logic [6:0] dmi_req_bits_addr; - logic [1:0] dmi_req_bits_op; - logic [31:0] dmi_req_bits_data; logic dmi_resp_ready; logic dmi_resp_valid; - logic rtc_i; - assign rtc_i = 1'b0; + dm::dmi_req_t jtag_dmi_req; + dm::dmi_req_t dmi_req; + + dm::dmi_req_t debug_req; + dm::dmi_resp_t debug_resp; assign test_en = 1'b0; - assign ndmreset_n = ~ndmreset ; - localparam NB_SLAVE = 4; - localparam NB_MASTER = 4; + localparam NB_SLAVE = 2; localparam AXI_ID_WIDTH_SLAVES = AXI_ID_WIDTH + $clog2(NB_SLAVE); @@ -87,7 +86,15 @@ module ariane_testharness #( .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) master[NB_MASTER-1:0](); + ) master[ariane_soc::NB_PERIPHERALS-1:0](); + + rstgen i_rstgen_main ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni & (~ndmreset) ), + .test_mode_i ( test_en ), + .rst_no ( ndmreset_n ), + .init_no ( ) // keep open + ); // --------------- // Debug @@ -98,12 +105,6 @@ module ariane_testharness #( if (!$value$plusargs("jtag_rbb_enable=%b", jtag_enable)) jtag_enable = 'h0; end - dm::dmi_req_t jtag_dmi_req; - dm::dmi_req_t dmi_req; - - dm::dmi_req_t debug_req; - dm::dmi_resp_t debug_resp; - // debug if MUX assign debug_req_valid = (jtag_enable[0]) ? jtag_req_valid : dmi_req_valid; assign debug_resp_ready = (jtag_enable[0]) ? jtag_resp_ready : dmi_resp_ready; @@ -151,30 +152,41 @@ module ariane_testharness #( // Converts to DPI calls logic [1:0] debug_req_bits_op; assign dmi_req.op = dm::dtm_op_t'(debug_req_bits_op); - SimDTM i_SimDTM ( - .clk ( clk_i ), - .reset ( ~rst_ni ), - .debug_req_valid ( dmi_req_valid ), - .debug_req_ready ( debug_req_ready ), - .debug_req_bits_addr ( dmi_req.addr ), - .debug_req_bits_op ( debug_req_bits_op ), - .debug_req_bits_data ( dmi_req.data ), - .debug_resp_valid ( dmi_resp_valid ), - .debug_resp_ready ( dmi_resp_ready ), - .debug_resp_bits_resp ( debug_resp.resp ), - .debug_resp_bits_data ( debug_resp.data ), - .exit ( dmi_exit ) - ); + + if (InclSimDTM) begin + SimDTM i_SimDTM ( + .clk ( clk_i ), + .reset ( ~rst_ni ), + .debug_req_valid ( dmi_req_valid ), + .debug_req_ready ( debug_req_ready ), + .debug_req_bits_addr ( dmi_req.addr ), + .debug_req_bits_op ( debug_req_bits_op ), + .debug_req_bits_data ( dmi_req.data ), + .debug_resp_valid ( dmi_resp_valid ), + .debug_resp_ready ( dmi_resp_ready ), + .debug_resp_bits_resp ( debug_resp.resp ), + .debug_resp_bits_data ( debug_resp.data ), + .exit ( dmi_exit ) + ); + end else begin + assign dmi_req_valid = '0; + assign debug_req_bits_op = '0; + assign dmi_exit = 1'b0; + end + + ariane_axi::req_t dm_axi_m_req, dm_axi_s_req; + ariane_axi::resp_t dm_axi_m_resp, dm_axi_s_resp; // debug module dm_top #( // current implementation only supports 1 hart - .NrHarts ( 1 ), - .AxiIdWidth ( AXI_ID_WIDTH_SLAVES ), - .AxiAddrWidth ( AXI_ADDRESS_WIDTH ), - .AxiDataWidth ( AXI_DATA_WIDTH ), - .AxiUserWidth ( AXI_USER_WIDTH ) + .NrHarts ( 1 ), + .AxiIdWidth ( AXI_ID_WIDTH_SLAVES ), + .AxiAddrWidth ( AXI_ADDRESS_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .AxiUserWidth ( AXI_USER_WIDTH ) ) i_dm_top ( + .clk_i ( clk_i ), .rst_ni ( rst_ni ), // PoR .testmode_i ( test_en ), @@ -182,8 +194,10 @@ module ariane_testharness #( .dmactive_o ( ), // active debug session .debug_req_o ( debug_req_core ), .unavailable_i ( '0 ), - .axi_master ( slave[3] ), - .axi_slave ( master[3] ), + .axi_s_req_i ( dm_axi_s_req ), + .axi_s_resp_o ( dm_axi_s_resp ), + .axi_m_req_o ( dm_axi_m_req ), + .axi_m_resp_i ( dm_axi_m_resp ), .dmi_rst_ni ( rst_ni ), .dmi_req_valid_i ( debug_req_valid ), .dmi_req_ready_o ( debug_req_ready ), @@ -193,6 +207,10 @@ module ariane_testharness #( .dmi_resp_o ( debug_resp ) ); + axi_master_connect i_axi_master_dm (.axi_req_i(dm_axi_m_req), .axi_resp_o(dm_axi_m_resp), .master(slave[1])); + axi_slave_connect i_axi_slave_dm (.axi_req_o(dm_axi_s_req), .axi_resp_i(dm_axi_s_resp), .slave(master[ariane_soc::Debug])); + + // --------------- // ROM // --------------- @@ -206,15 +224,15 @@ module ariane_testharness #( .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ) ) i_axi2rom ( - .clk_i ( clk_i ), - .rst_ni ( ndmreset_n ), - .slave ( master[2] ), - .req_o ( rom_req ), - .we_o ( ), - .addr_o ( rom_addr ), - .be_o ( ), - .data_o ( ), - .data_i ( rom_rdata ) + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .slave ( master[ariane_soc::ROM] ), + .req_o ( rom_req ), + .we_o ( ), + .addr_o ( rom_addr ), + .be_o ( ), + .data_o ( ), + .data_i ( rom_rdata ) ); bootrom i_bootrom ( @@ -227,6 +245,14 @@ module ariane_testharness #( // --------------- // Memory // --------------- + + AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) dram(); + logic req; logic we; logic [AXI_ADDRESS_WIDTH-1:0] addr; @@ -234,6 +260,137 @@ module ariane_testharness #( logic [AXI_DATA_WIDTH-1:0] wdata; logic [AXI_DATA_WIDTH-1:0] rdata; + axi_pkg::aw_chan_t aw_chan_i; + axi_pkg::w_chan_t w_chan_i; + axi_pkg::b_chan_t b_chan_o; + axi_pkg::ar_chan_t ar_chan_i; + axi_pkg::r_chan_t r_chan_o; + axi_pkg::aw_chan_t aw_chan_o; + axi_pkg::w_chan_t w_chan_o; + axi_pkg::b_chan_t b_chan_i; + axi_pkg::ar_chan_t ar_chan_o; + axi_pkg::r_chan_t r_chan_i; + + axi_delayer #( + .aw_t ( axi_pkg::aw_chan_t ), + .w_t ( axi_pkg::w_chan_t ), + .b_t ( axi_pkg::b_chan_t ), + .ar_t ( axi_pkg::ar_chan_t ), + .r_t ( axi_pkg::r_chan_t ), + .StallRandomOutput ( StallRandomOutput ), + .StallRandomInput ( StallRandomInput ), + .FixedDelayInput ( 0 ), + .FixedDelayOutput ( 0 ) + ) i_axi_delayer ( + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .aw_valid_i ( master[ariane_soc::DRAM].aw_valid ), + .aw_chan_i ( aw_chan_i ), + .aw_ready_o ( master[ariane_soc::DRAM].aw_ready ), + .w_valid_i ( master[ariane_soc::DRAM].w_valid ), + .w_chan_i ( w_chan_i ), + .w_ready_o ( master[ariane_soc::DRAM].w_ready ), + .b_valid_o ( master[ariane_soc::DRAM].b_valid ), + .b_chan_o ( b_chan_o ), + .b_ready_i ( master[ariane_soc::DRAM].b_ready ), + .ar_valid_i ( master[ariane_soc::DRAM].ar_valid ), + .ar_chan_i ( ar_chan_i ), + .ar_ready_o ( master[ariane_soc::DRAM].ar_ready ), + .r_valid_o ( master[ariane_soc::DRAM].r_valid ), + .r_chan_o ( r_chan_o ), + .r_ready_i ( master[ariane_soc::DRAM].r_ready ), + .aw_valid_o ( dram.aw_valid ), + .aw_chan_o ( aw_chan_o ), + .aw_ready_i ( dram.aw_ready ), + .w_valid_o ( dram.w_valid ), + .w_chan_o ( w_chan_o ), + .w_ready_i ( dram.w_ready ), + .b_valid_i ( dram.b_valid ), + .b_chan_i ( b_chan_i ), + .b_ready_o ( dram.b_ready ), + .ar_valid_o ( dram.ar_valid ), + .ar_chan_o ( ar_chan_o ), + .ar_ready_i ( dram.ar_ready ), + .r_valid_i ( dram.r_valid ), + .r_chan_i ( r_chan_i ), + .r_ready_o ( dram.r_ready ) + ); + + assign aw_chan_i.atop = '0; + assign aw_chan_i.id = master[ariane_soc::DRAM].aw_id; + assign aw_chan_i.addr = master[ariane_soc::DRAM].aw_addr; + assign aw_chan_i.len = master[ariane_soc::DRAM].aw_len; + assign aw_chan_i.size = master[ariane_soc::DRAM].aw_size; + assign aw_chan_i.burst = master[ariane_soc::DRAM].aw_burst; + assign aw_chan_i.lock = master[ariane_soc::DRAM].aw_lock; + assign aw_chan_i.cache = master[ariane_soc::DRAM].aw_cache; + assign aw_chan_i.prot = master[ariane_soc::DRAM].aw_prot; + assign aw_chan_i.qos = master[ariane_soc::DRAM].aw_qos; + assign aw_chan_i.region = master[ariane_soc::DRAM].aw_region; + + assign ar_chan_i.id = master[ariane_soc::DRAM].ar_id; + assign ar_chan_i.addr = master[ariane_soc::DRAM].ar_addr; + assign ar_chan_i.len = master[ariane_soc::DRAM].ar_len; + assign ar_chan_i.size = master[ariane_soc::DRAM].ar_size; + assign ar_chan_i.burst = master[ariane_soc::DRAM].ar_burst; + assign ar_chan_i.lock = master[ariane_soc::DRAM].ar_lock; + assign ar_chan_i.cache = master[ariane_soc::DRAM].ar_cache; + assign ar_chan_i.prot = master[ariane_soc::DRAM].ar_prot; + assign ar_chan_i.qos = master[ariane_soc::DRAM].ar_qos; + assign ar_chan_i.region = master[ariane_soc::DRAM].ar_region; + + assign w_chan_i.data = master[ariane_soc::DRAM].w_data; + assign w_chan_i.strb = master[ariane_soc::DRAM].w_strb; + assign w_chan_i.last = master[ariane_soc::DRAM].w_last; + + assign master[ariane_soc::DRAM].r_id = r_chan_o.id; + assign master[ariane_soc::DRAM].r_data = r_chan_o.data; + assign master[ariane_soc::DRAM].r_resp = r_chan_o.resp; + assign master[ariane_soc::DRAM].r_last = r_chan_o.last; + + assign master[ariane_soc::DRAM].b_id = b_chan_o.id; + assign master[ariane_soc::DRAM].b_resp = b_chan_o.resp; + + + assign dram.aw_id = aw_chan_o.id; + assign dram.aw_addr = aw_chan_o.addr; + assign dram.aw_len = aw_chan_o.len; + assign dram.aw_size = aw_chan_o.size; + assign dram.aw_burst = aw_chan_o.burst; + assign dram.aw_lock = aw_chan_o.lock; + assign dram.aw_cache = aw_chan_o.cache; + assign dram.aw_prot = aw_chan_o.prot; + assign dram.aw_qos = aw_chan_o.qos; + assign dram.aw_region = aw_chan_o.region; + assign dram.aw_user = master[ariane_soc::DRAM].aw_user; + + assign dram.ar_id = ar_chan_o.id; + assign dram.ar_addr = ar_chan_o.addr; + assign dram.ar_len = ar_chan_o.len; + assign dram.ar_size = ar_chan_o.size; + assign dram.ar_burst = ar_chan_o.burst; + assign dram.ar_lock = ar_chan_o.lock; + assign dram.ar_cache = ar_chan_o.cache; + assign dram.ar_prot = ar_chan_o.prot; + assign dram.ar_qos = ar_chan_o.qos; + assign dram.ar_region = ar_chan_o.region; + assign dram.ar_user = master[ariane_soc::DRAM].ar_user; + + assign dram.w_data = w_chan_o.data; + assign dram.w_strb = w_chan_o.strb; + assign dram.w_last = w_chan_o.last; + assign dram.w_user = master[ariane_soc::DRAM].w_user; + + assign r_chan_i.id = dram.r_id; + assign r_chan_i.data = dram.r_data; + assign r_chan_i.resp = dram.r_resp; + assign r_chan_i.last = dram.r_last; + assign master[ariane_soc::DRAM].r_user = dram.r_user; + + assign b_chan_i.id = dram.b_id; + assign b_chan_i.resp = dram.b_resp; + assign master[ariane_soc::DRAM].b_user = dram.b_user; + axi2mem #( .AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ), @@ -243,7 +400,7 @@ module ariane_testharness #( ) i_axi2mem ( .clk_i ( clk_i ), .rst_ni ( ndmreset_n ), - .slave ( master[0] ), + .slave ( dram ), .req_o ( req ), .we_o ( we ), .addr_o ( addr ), @@ -270,21 +427,42 @@ module ariane_testharness #( // AXI Xbar // --------------- axi_node_intf_wrap #( - // three ports from Ariane (instruction, data and bypass) - .NB_SLAVE ( NB_SLAVE ), - .NB_MASTER ( NB_MASTER ), // debug unit, memory unit - .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + .NB_SLAVE ( NB_SLAVE ), + .NB_MASTER ( ariane_soc::NB_PERIPHERALS ), + .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + // .MASTER_SLICE_DEPTH ( 0 ), + // .SLAVE_SLICE_DEPTH ( 0 ) ) i_axi_xbar ( - .clk ( clk_i ), - .rst_n ( ndmreset_n ), - .test_en_i ( test_en ), - .slave ( slave ), - .master ( master ), - .start_addr_i ( {64'h0, 64'h10000, 64'h2000000, CACHE_START_ADDR} ), - .end_addr_i ( {64'hFFF, 64'h1FFFF, 64'h2FFFFFF, CACHE_START_ADDR + 2**24} ) + .clk ( clk_i ), + .rst_n ( ndmreset_n ), + .test_en_i ( test_en ), + .slave ( slave ), + .master ( master ), + .start_addr_i ({ + ariane_soc::DebugBase, + ariane_soc::ROMBase, + ariane_soc::CLINTBase, + ariane_soc::PLICBase, + ariane_soc::UARTBase, + ariane_soc::SPIBase, + ariane_soc::EthernetBase, + ariane_soc::GPIOBase, + ariane_soc::DRAMBase + }), + .end_addr_i ({ + ariane_soc::DebugBase + ariane_soc::DebugLength - 1, + ariane_soc::ROMBase + ariane_soc::ROMLength - 1, + ariane_soc::CLINTBase + ariane_soc::CLINTLength - 1, + ariane_soc::PLICBase + ariane_soc::PLICLength - 1, + ariane_soc::UARTBase + ariane_soc::UARTLength - 1, + ariane_soc::SPIBase + ariane_soc::SPILength - 1, + ariane_soc::EthernetBase + ariane_soc::EthernetLength -1, + ariane_soc::GPIOBase + ariane_soc::GPIOLength - 1, + ariane_soc::DRAMBase + ariane_soc::DRAMLength - 1 + }) ); // --------------- @@ -293,42 +471,94 @@ module ariane_testharness #( logic ipi; logic timer_irq; + ariane_axi::req_t axi_clint_req; + ariane_axi::resp_t axi_clint_resp; + clint #( .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_WIDTH_SLAVES ), .NR_CORES ( 1 ) ) i_clint ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .testmode_i ( test_en ), - .slave ( master[1] ), - .rtc_i ( rtc_i ), - .timer_irq_o ( timer_irq ), - .ipi_o ( ipi ) + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .testmode_i ( test_en ), + .axi_req_i ( axi_clint_req ), + .axi_resp_o ( axi_clint_resp ), + .rtc_i ( rtc_i ), + .timer_irq_o ( timer_irq ), + .ipi_o ( ipi ) ); + axi_slave_connect i_axi_slave_connect_clint (.axi_req_o(axi_clint_req), .axi_resp_i(axi_clint_resp), .slave(master[ariane_soc::CLINT])); + + // --------------- + // Peripherals + // --------------- + logic tx, rx; + logic [1:0] irqs; + + ariane_peripherals #( + .AxiAddrWidth ( AXI_ADDRESS_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .AxiIdWidth ( AXI_ID_WIDTH_SLAVES ), + .InclUART ( 1'b0 ), + .InclSPI ( 1'b0 ), + .InclEthernet ( 1'b0 ) + ) i_ariane_peripherals ( + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .plic ( master[ariane_soc::PLIC] ), + .uart ( master[ariane_soc::UART] ), + .spi ( master[ariane_soc::SPI] ), + .ethernet ( master[ariane_soc::Ethernet] ), + .irq_o ( irqs ), + .rx_i ( rx ), + .tx_o ( tx ), + .eth_txck ( ), + .eth_rxck ( ), + .eth_rxctl ( ), + .eth_rxd ( ), + .eth_rst_n ( ), + .eth_tx_en ( ), + .eth_txd ( ), + .phy_mdio ( ), + .eth_mdc ( ), + .mdio ( ), + .mdc ( ), + .spi_clk_o ( ), + .spi_mosi ( ), + .spi_miso ( ), + .spi_ss ( ) + ); + + uart_bus #(.BAUD_RATE(115200), .PARITY_EN(0)) i_uart_bus (.rx(tx), .tx(rx), .rx_en(1'b1)); + // --------------- // Core // --------------- + ariane_axi::req_t axi_ariane_req; + ariane_axi::resp_t axi_ariane_resp; + ariane #( - .CACHE_START_ADDR ( CACHE_START_ADDR ), - .AXI_ID_WIDTH ( AXI_ID_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +`ifdef PITON_ARIANE + .SwapEndianess ( 0 ), + .CachedAddrEnd ( (ariane_soc::DRAMBase + ariane_soc::DRAMLength) ), +`endif + .CachedAddrBeg ( ariane_soc::DRAMBase ) ) i_ariane ( - .clk_i ( clk_i ), - .rst_ni ( ndmreset_n ), - .boot_addr_i ( 64'h10000 ), // start fetching from ROM - .core_id_i ( '0 ), - .cluster_id_i ( '0 ), - .irq_i ( '0 ), // we do not specify other interrupts in this TB - .ipi_i ( ipi ), - .time_irq_i ( timer_irq ), - .debug_req_i ( debug_req_core ), - .data_if ( slave[2] ), - .bypass_if ( slave[1] ), - .instr_if ( slave[0] ) + .clk_i ( clk_i ), + .rst_ni ( ndmreset_n ), + .boot_addr_i ( ariane_soc::ROMBase ), // start fetching from ROM + .hart_id_i ( '0 ), + .irq_i ( irqs ), + .ipi_i ( ipi ), + .time_irq_i ( timer_irq ), + .debug_req_i ( debug_req_core ), + .axi_req_o ( axi_ariane_req ), + .axi_resp_i ( axi_ariane_resp ) ); -endmodule + axi_master_connect i_axi_master_connect_ariane (.axi_req_i(axi_ariane_req), .axi_resp_o(axi_ariane_resp), .master(slave[0])); +endmodule diff --git a/tb/common/core_mem.sv b/tb/common/core_mem.sv old mode 100755 new mode 100644 diff --git a/tb/common/dp_ram.sv b/tb/common/dp_ram.sv old mode 100755 new mode 100644 diff --git a/tb/common/mock_uart.sv b/tb/common/mock_uart.sv new file mode 100644 index 0000000000..1f9c0c0f3b --- /dev/null +++ b/tb/common/mock_uart.sv @@ -0,0 +1,134 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 28/09/2018 +// Description: Mock replacement for UART in testbench (not synthesiesable!) + +module mock_uart ( + input logic clk_i, + input logic rst_ni, + input logic penable_i, + input logic pwrite_i, + input logic [31:0] paddr_i, + input logic psel_i, + input logic [31:0] pwdata_i, + output logic [31:0] prdata_o, + output logic pready_o, + output logic pslverr_o +); + localparam RBR = 0; + localparam THR = 0; + localparam IER = 1; + localparam IIR = 2; + localparam FCR = 2; + localparam LCR = 3; + localparam MCR = 4; + localparam LSR = 5; + localparam MSR = 6; + localparam SCR = 7; + localparam DLL = 0; + localparam DLM = 1; + + localparam THRE = 5; // transmit holding register empty + localparam TEMT = 6; // transmit holding register empty + + byte lcr = 0; + byte dlm = 0; + byte dll = 0; + byte mcr = 0; + byte lsr = 0; + byte ier = 0; + byte msr = 0; + byte scr = 0; + logic fifo_enabled = 1'b0; + + assign pready_o = 1'b1; + assign pslverr_o = 1'b0; + + // string buffer + byte buffer [$]; + + function void flush(); + string s; + // dump the buffer out the whole buffer + foreach (buffer[i]) begin + s = $sformatf("%s%c",s, buffer[i]); + end + + $display(s); + + // clear buffer afterwards + buffer = {}; + endfunction : flush + + // put a char into the buffer + function void append(byte ch); + + // wait for the new line + if (ch == 8'hA) + flush(); + else + buffer.push_back(ch); + + endfunction : append + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (rst_ni) begin + if (psel_i & penable_i & pwrite_i) begin + case ((paddr_i >> 'h2) & 'h7) + THR: begin + if (lcr & 'h80) dll <= byte'(pwdata_i[7:0]); + else append(byte'(pwdata_i[7:0])); + end + IER: begin + if (lcr & 'h80) dlm <= byte'(pwdata_i[7:0]); + else ier <= byte'(pwdata_i[7:0] & 'hF); + end + FCR: begin + if (pwdata_i[0]) fifo_enabled <= 1'b1; + else fifo_enabled <= 1'b0; + end + LCR: lcr <= byte'(pwdata_i[7:0]); + MCR: mcr <= byte'(pwdata_i[7:0] & 'h1F); + LSR: lsr <= byte'(pwdata_i[7:0]); + MSR: msr <= byte'(pwdata_i[7:0]); + SCR: scr <= byte'(pwdata_i[7:0]); + default:; + endcase + end + end + end + + always_comb begin + prdata_o = '0; + if (psel_i & penable_i & ~pwrite_i) begin + case ((paddr_i >> 'h2) & 'h7) + THR: begin + if (lcr & 'h80) prdata_o = {24'b0, dll}; + end + IER: begin + if (lcr & 'h80) prdata_o = {24'b0, dlm}; + else prdata_o = {24'b0, ier}; + end + IIR: begin + if (fifo_enabled) prdata_o = {24'b0, 8'hc0}; + else prdata_o = {24'b0, 8'b0}; + end + LCR: prdata_o = {24'b0, lcr}; + MCR: prdata_o = {24'b0, mcr}; + LSR: prdata_o = {24'b0, (lsr | (1 << THRE) | (1 << TEMT))}; + MSR: prdata_o = {24'b0, msr}; + SCR: prdata_o = {24'b0, scr}; + default:; + endcase + end + end +endmodule diff --git a/tb/common/string_buffer.svh b/tb/common/string_buffer.svh old mode 100755 new mode 100644 diff --git a/tb/common/tb.svh b/tb/common/tb.svh new file mode 100644 index 0000000000..ee4dabae6e --- /dev/null +++ b/tb/common/tb.svh @@ -0,0 +1,66 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: +// + +////////////////////////////////////////////////////////////////////////////// +// use to ensure proper ATI timing +/////////////////////////////////////////////////////////////////////////////// + +`define APPL_ACQ_WAIT #(ACQ_DEL-APPL_DEL); + +`define WAIT_CYC(CLK, N) \ +repeat(N) @(posedge(CLK)); + +`define WAIT(CLK, SIG) \ +do begin \ + @(posedge(CLK)); \ +end while(SIG == 1'b0); + +`define WAIT_SIG(CLK,SIG) \ +do begin \ + @(posedge(CLK)); \ +end while(SIG == 1'b0); + +`define APPL_WAIT_COMB_SIG(CLK,SIG) \ +`APPL_ACQ_WAIT \ +while(SIG == 1'b0) begin \ + @(posedge(CLK)); \ + #(ACQ_DEL); \ +end + +`define APPL_WAIT_SIG(CLK,SIG) \ +do begin \ + @(posedge(CLK)); \ + #(APPL_DEL); \ +end while(SIG == 1'b0); + +`define ACQ_WAIT_SIG(CLK,SIG) \ +do begin \ + @(posedge(CLK)); \ + #(ACQ_DEL); \ +end while(SIG == 1'b0); + + +`define APPL_WAIT_CYC(CLK, N) \ +repeat(N) @(posedge(CLK)); \ +#(tb_pkg::APPL_DEL); + +`define ACQ_WAIT_CYC(CLK, N) \ +repeat(N) @(posedge(CLK)); \ +#(tb_pkg::ACQ_DEL); + diff --git a/tb/common/uart.sv b/tb/common/uart.sv index b1b1eedbfa..568e0aa9a9 100644 --- a/tb/common/uart.sv +++ b/tb/common/uart.sv @@ -13,19 +13,18 @@ // Description: This module takes data over UART and prints them to the console // A string is printed to the console as soon as a '\n' character is found -interface uart_bus - #( - parameter BAUD_RATE = 115200, - parameter PARITY_EN = 0 - ) - ( +interface uart_bus #( + parameter int unsigned BAUD_RATE = 115200, + parameter int unsigned PARITY_EN = 0 +)( input logic rx, output logic tx, - input logic rx_en - ); +); - localparam BIT_PERIOD = (1000000000/BAUD_RATE*1000); +/* pragma translate_off */ +`ifndef VERILATOR + localparam time BIT_PERIOD = (1000000000 / BAUD_RATE) * 1ns; logic [7:0] character; logic [256*8-1:0] stringa; @@ -33,35 +32,28 @@ interface uart_bus integer charnum; integer file; - initial - begin + initial begin tx = 1'bZ; - file = $fopen("stdout/uart", "w"); + file = $fopen("uart", "w"); end - always - begin - if (rx_en) - begin + always begin + if (rx_en) begin @(negedge rx); - #(BIT_PERIOD/2) ; - for (int i=0;i<=7;i++) - begin + #(BIT_PERIOD/2); + for (int i = 0; i <= 7; i++) begin #BIT_PERIOD character[i] = rx; end - if(PARITY_EN == 1) - begin + if (PARITY_EN == 1) begin // check parity #BIT_PERIOD parity = rx; - for (int i=7;i>=0;i--) - begin + for (int i=7;i>=0;i--) begin parity = character[i] ^ parity; end - if(parity == 1'b1) - begin + if (parity == 1'b1) begin $display("Parity error detected"); end end @@ -71,24 +63,20 @@ interface uart_bus $fwrite(file, "%c", character); stringa[(255-charnum)*8 +: 8] = character; - if (character == 8'h0A || charnum == 254) // line feed or max. chars reached - begin - if (character == 8'h0A) + if (character == 8'h0A || charnum == 254) begin // line feed or max. chars reached + if (character == 8'h0A) begin stringa[(255-charnum)*8 +: 8] = 8'h0; // null terminate string, replace line feed - else + end else begin stringa[(255-charnum-1)*8 +: 8] = 8'h0; // null terminate string + end - $write("RX string: %s\n",stringa); + $write("[UART]: %s\n", stringa); charnum = 0; stringa = ""; - end - else - begin + end else begin charnum = charnum + 1; end - end - else - begin + end else begin charnum = 0; stringa = ""; #10; @@ -111,4 +99,6 @@ interface uart_bus tx = 1'b1; #(BIT_PERIOD); endtask +/* pragma translate_on */ +`endif endinterface diff --git a/tb/dpi/SimDTM.cc b/tb/dpi/SimDTM.cc index 330b60d91e..8d6d34d607 100644 --- a/tb/dpi/SimDTM.cc +++ b/tb/dpi/SimDTM.cc @@ -1,4 +1,5 @@ // See LICENSE.SiFive for license details. +#include "msim_helper.h" #include #include @@ -22,38 +23,10 @@ extern "C" int debug_tick int debug_resp_bits_data ) { - bool permissive_on = false; if (!dtm) { - s_vpi_vlog_info info; - if (!vpi_get_vlog_info(&info)) - abort(); - std::vector htif_args; - - // sanitize arguments - for (int i = 1; i < info.argc; i++) { - if (strcmp(info.argv[i], "+permissive") == 0) { - permissive_on = true; - printf("Found permissive %s\n", info.argv[i]); - } - - // remove any two double pluses at the beginning (those are target arguments) - if (info.argv[i][0] == '+' && info.argv[i][1] == '+' && strlen(info.argv[i]) > 3) { - for (int j = 0; j < strlen(info.argv[i]) - 1; j++) { - info.argv[i][j] = info.argv[i][j + 2]; - } - } - - if (!permissive_on) { - htif_args.push_back(info.argv[i]); - } - - if (strcmp(info.argv[i], "+permissive-off") == 0) { - permissive_on = false; - printf("Found permissive-off %s\n", info.argv[i]); - } - } + std::vector htif_args = sanitize_args(); // convert vector to argc and argv int argc = htif_args.size() + 1; diff --git a/tb/dpi/bootrom.h b/tb/dpi/bootrom.h new file mode 120000 index 0000000000..343e003dde --- /dev/null +++ b/tb/dpi/bootrom.h @@ -0,0 +1 @@ +../../bootrom/bootrom.h \ No newline at end of file diff --git a/tb/dpi/elfloader.cc b/tb/dpi/elfloader.cc new file mode 100644 index 0000000000..2aa1dfb14f --- /dev/null +++ b/tb/dpi/elfloader.cc @@ -0,0 +1,135 @@ +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SHT_PROGBITS 0x1 +#define SHT_GROUP 0x11 + +// address and size +std::vector> sections; +std::map symbols; +// memory based address and content +std::map> mems; +reg_t entry; +int section_index = 0; + +void write (uint64_t address, uint64_t len, uint8_t* buf) { + uint64_t datum; + std::vector mem; + for (int i = 0; i < len; i++) { + mem.push_back(buf[i]); + } + mems.insert(std::make_pair(address, mem)); +} + +// Communicate the section address and len +// Returns: +// 0 if there are no more sections +// 1 if there are more sections to load +extern "C" char get_section (long long* address, long long* len) { + if (section_index < sections.size()) { + *address = sections[section_index].first; + *len = sections[section_index].second; + section_index++; + return 1; + } else return 0; +} + +extern "C" char read_section (long long address, const svOpenArrayHandle buffer) { + // get actual poitner + void* buf = svGetArrayPtr(buffer); + // check that the address points to a section + assert(mems.count(address) > 0); + // copy array + int i = 0; + for (auto &datum : mems.find(address)->second) { + *((char *) buf + i) = datum; + i++; + } +} + +extern "C" void read_elf(const char* filename) { + int fd = open(filename, O_RDONLY); + struct stat s; + assert(fd != -1); + if (fstat(fd, &s) < 0) + abort(); + size_t size = s.st_size; + + char* buf = (char*)mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0); + assert(buf != MAP_FAILED); + close(fd); + + assert(size >= sizeof(Elf64_Ehdr)); + const Elf64_Ehdr* eh64 = (const Elf64_Ehdr*)buf; + assert(IS_ELF32(*eh64) || IS_ELF64(*eh64)); + + + + std::vector zeros; + std::map symbols; + + #define LOAD_ELF(ehdr_t, phdr_t, shdr_t, sym_t) do { \ + ehdr_t* eh = (ehdr_t*)buf; \ + phdr_t* ph = (phdr_t*)(buf + eh->e_phoff); \ + entry = eh->e_entry; \ + assert(size >= eh->e_phoff + eh->e_phnum*sizeof(*ph)); \ + for (unsigned i = 0; i < eh->e_phnum; i++) { \ + if(ph[i].p_type == PT_LOAD && ph[i].p_memsz) { \ + if (ph[i].p_filesz) { \ + assert(size >= ph[i].p_offset + ph[i].p_filesz); \ + sections.push_back(std::make_pair(ph[i].p_paddr, ph[i].p_memsz)); \ + write(ph[i].p_paddr, ph[i].p_filesz, (uint8_t*)buf + ph[i].p_offset); \ + } \ + zeros.resize(ph[i].p_memsz - ph[i].p_filesz); \ + } \ + } \ + shdr_t* sh = (shdr_t*)(buf + eh->e_shoff); \ + assert(size >= eh->e_shoff + eh->e_shnum*sizeof(*sh)); \ + assert(eh->e_shstrndx < eh->e_shnum); \ + assert(size >= sh[eh->e_shstrndx].sh_offset + sh[eh->e_shstrndx].sh_size); \ + char *shstrtab = buf + sh[eh->e_shstrndx].sh_offset; \ + unsigned strtabidx = 0, symtabidx = 0; \ + for (unsigned i = 0; i < eh->e_shnum; i++) { \ + unsigned max_len = sh[eh->e_shstrndx].sh_size - sh[i].sh_name; \ + if ((sh[i].sh_type & SHT_GROUP) && strcmp(shstrtab + sh[i].sh_name, ".strtab") != 0 && strcmp(shstrtab + sh[i].sh_name, ".shstrtab") != 0) \ + assert(strnlen(shstrtab + sh[i].sh_name, max_len) < max_len); \ + if (sh[i].sh_type & SHT_PROGBITS) continue; \ + if (strcmp(shstrtab + sh[i].sh_name, ".strtab") == 0) \ + strtabidx = i; \ + if (strcmp(shstrtab + sh[i].sh_name, ".symtab") == 0) \ + symtabidx = i; \ + } \ + if (strtabidx && symtabidx) { \ + char* strtab = buf + sh[strtabidx].sh_offset; \ + sym_t* sym = (sym_t*)(buf + sh[symtabidx].sh_offset); \ + for (unsigned i = 0; i < sh[symtabidx].sh_size/sizeof(sym_t); i++) { \ + unsigned max_len = sh[strtabidx].sh_size - sym[i].st_name; \ + assert(sym[i].st_name < sh[strtabidx]. sh_size); \ + assert(strnlen(strtab + sym[i].st_name, max_len) < max_len); \ + symbols[strtab + sym[i].st_name] = sym[i].st_value; \ + } \ + } \ + } while(0) + + if (IS_ELF32(*eh64)) + LOAD_ELF(Elf32_Ehdr, Elf32_Phdr, Elf32_Shdr, Elf32_Sym); + else + LOAD_ELF(Elf64_Ehdr, Elf64_Phdr, Elf64_Shdr, Elf64_Sym); + + munmap(buf, size); +} diff --git a/tb/dpi/msim_helper.cc b/tb/dpi/msim_helper.cc new file mode 100644 index 0000000000..cc0e449f7d --- /dev/null +++ b/tb/dpi/msim_helper.cc @@ -0,0 +1,46 @@ +// Author: Florian Zaruba +// Description: ModelSim Helper Functions + +#include + +#include +#include +#include +#include + +// sanitize htif arguments +std::vector sanitize_args() { + bool permissive_on = false; + + s_vpi_vlog_info info; + if (!vpi_get_vlog_info(&info)) + abort(); + + std::vector htif_args; + + // sanitize arguments + for (int i = 1; i < info.argc; i++) { + if (strcmp(info.argv[i], "+permissive") == 0) { + permissive_on = true; + // printf("Found permissive %s\n", info.argv[i]); + } + + // remove any two double pluses at the beginning (those are target arguments) + if (info.argv[i][0] == '+' && info.argv[i][1] == '+' && strlen(info.argv[i]) > 3) { + for (int j = 0; j < strlen(info.argv[i]) - 1; j++) { + info.argv[i][j] = info.argv[i][j + 2]; + } + } + + if (!permissive_on) { + htif_args.push_back(info.argv[i]); + } + + if (strcmp(info.argv[i], "+permissive-off") == 0) { + permissive_on = false; + // printf("Found permissive-off %s\n", info.argv[i]); + } + } + + return htif_args; +} diff --git a/tb/dpi/msim_helper.h b/tb/dpi/msim_helper.h new file mode 100644 index 0000000000..100ad65f31 --- /dev/null +++ b/tb/dpi/msim_helper.h @@ -0,0 +1,12 @@ +// Author: Florian Zaruba +// Description: ModelSim Helper Functions +#ifndef _MSIM_HELPER_H +#define _MSIM_HELPER_H + +#include +#include + +// sanitize htif arguments +std::vector sanitize_args(); + +#endif diff --git a/tb/tb_serdiv/.gitignore b/tb/tb_serdiv/.gitignore new file mode 100644 index 0000000000..f8cb654656 --- /dev/null +++ b/tb/tb_serdiv/.gitignore @@ -0,0 +1,7 @@ +work +*.rep +transcript +*.ini +*.wlf +*.log + diff --git a/tb/tb_serdiv/Makefile b/tb/tb_serdiv/Makefile new file mode 100755 index 0000000000..8c5e4f5d44 --- /dev/null +++ b/tb/tb_serdiv/Makefile @@ -0,0 +1,41 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# Copyright and related rights are licensed under the Solderpad Hardware +# License, Version 0.51 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +# or agreed to in writing, software, hardware and materials distributed under +# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. +# +# Author: Michael Schaffner , ETH Zurich +# Date: 15.08.2018 +# Description: Makefile for the serial divider testbench. + +library ?= work +toplevel ?= tb +src-list := tb.list +inc-path := $(shell pwd)/hdl/ +src := $(shell xargs printf '\n%s' < $(src-list) | cut -b 1-) +compile_flag += +cover+i_dut -incr -64 -nologo +sim_opts += -64 -coverage -classdebug -voptargs="+acc" +questa_version ?= ${QUESTASIM_VERSION} +incdir += ../common/ + +build: clean + vlib${questa_version} $(library) + vlog${questa_version} -work $(library) -pedanticerrors $(src) $(compile_flag) +incdir+$(incdir) + touch $(library)/.build + +sim: build + vsim${questa_version} -lib $(library) $(toplevel) -do "do wave.do" $(sim_opts) + +simc: build + vsim${questa_version} -lib $(library) $(toplevel) -c -do "run -all; exit" $(sim_opts) + + +clean: + rm -rf $(library) + +.PHONY: clean simc sim build + diff --git a/tb/tb_serdiv/hdl/tb.sv b/tb/tb_serdiv/hdl/tb.sv new file mode 100644 index 0000000000..a01a1bfe3b --- /dev/null +++ b/tb/tb_serdiv/hdl/tb.sv @@ -0,0 +1,314 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner (schaffner@iis.ee.ethz.ch), ETH Zurich +// Andreas Traber (traber@iis.ee.ethz.ch), ETH Zurich +// +// Date: 18.10.2018 +// Description: testbench for serial 64bit divider +// + +`include "tb.svh" + +import ariane_pkg::*; +import tb_pkg::*; + +// tb package +module tb; + +/////////////////////////////////////////////////////////////////////////////// +// config +/////////////////////////////////////////////////////////////////////////////// + + // leave this + timeunit 1ps; + timeprecision 1ps; + + parameter VERBOSE = 1; + parameter WIDTH = 64; + parameter logic [WIDTH-1:0] MAX_NUM64 = '1; + parameter logic [WIDTH-2:0] MAX_NUM63 = '1; + parameter logic signed [WIDTH-1:0] MIN_NUM = {1'b1,{WIDTH-1{1'b0}}}; + +/////////////////////////////////////////////////////////////////////////////// +// MUT signal declarations +/////////////////////////////////////////////////////////////////////////////// + + + logic signed [WIDTH:0] op_a, op_b; + logic signed [WIDTH:0] op_a_tmp, op_b_tmp; + + logic flush_i; + logic [TRANS_ID_BITS-1:0] id_i; + logic [TRANS_ID_BITS-1:0] id_o; + + logic [WIDTH-1:0] op_a_i; + logic [WIDTH-1:0] op_b_i; + + logic [1:0] opcode_i; + logic [1:0] opcode_tmp; + + logic in_rdy_o; + logic in_vld_i; + logic out_rdy_i; + logic out_vld_o; + logic [WIDTH-1:0] res_o; + +/////////////////////////////////////////////////////////////////////////////// +// TB signal declarations +/////////////////////////////////////////////////////////////////////////////// + + logic clk_i, rst_ni; + logic stim_start, stim_end, end_of_sim; + longint num_stim; + logic acq_trig; + string test_name; + +/////////////////////////////////////////////////////////////////////////////// +// Clock Process +/////////////////////////////////////////////////////////////////////////////// + + always @* + begin + do begin + clk_i = 1; #(CLK_HI); + clk_i = 0; #(CLK_LO); + end while (end_of_sim == 1'b0); + // generate one extra cycle to allow response acquisition to complete + clk_i = 1; #(CLK_HI); + clk_i = 0; #(CLK_LO); + end + + +/////////////////////////////////////////////////////////////////////////////// +// MUT +/////////////////////////////////////////////////////////////////////////////// + + + assign OpBIsZero_SI = ~(|op_b_i); + serdiv #(.WIDTH(WIDTH)) i_dut (.*); + +/////////////////////////////////////////////////////////////////////////////// +// application process +/////////////////////////////////////////////////////////////////////////////// + + initial begin : p_stim + longint signed k; + bit randBit; + + stim_start = 0; + stim_end = 0; + num_stim = 0; + test_name = ""; + acq_trig = 0; + + rst_ni = 0; + + op_a = 0; + op_b = 0; + + op_a_i = 0; + op_b_i = 0; + opcode_i = 0; + in_vld_i = 0; + flush_i = 0; + id_i = 0; + + `APPL_WAIT_CYC(clk_i, 100) + + rst_ni <= 1'b1; + + `APPL_WAIT_CYC(clk_i, 100) + + $display("TB> stimuli application started"); + stim_start <= 1'b1; + `APPL_WAIT_CYC(clk_i, 100) + + /////////////////////////////////////////////// + // unsigned division test + + `include "tb_udiv.sv" + + /////////////////////////////////////////////// + // unsigned modulo test + + `include "tb_urem.sv" + + /////////////////////////////////////////////// + // signed division test + + `include "tb_div.sv" + + /////////////////////////////////////////////// + // signed modulo test + + `include "tb_rem.sv" + + /////////////////////////////////////////////// + + `APPL_WAIT_CYC(clk_i, 400) + + stim_end <= 1; + $display("TB> stimuli application ended"); + + end + + +/////////////////////////////////////////////////////////////////////////////// +// acquisition process +/////////////////////////////////////////////////////////////////////////////// + + + initial begin : p_acq + + /////////////////////////////////////////////// + // define vars, init... + /////////////////////////////////////////////// + bit ok; + string opStr; + progress status; + string failingTests, tmpstr; + longint acqCnt, res, act; + + status = new("TB"); + failingTests = ""; + + out_rdy_i = 0; + end_of_sim = 0; + + `ACQ_WAIT_SIG(clk_i, stim_start) + + $display("TB> response acquisition started"); + + /////////////////////////////////////////////// + // acquisiton and verification + /////////////////////////////////////////////// + repeat(4) begin + + // wait for acquisition trigger + do begin + `ACQ_WAIT_CYC(clk_i, 1) + if (stim_end == 1) begin + end_of_sim <= 1; + $display("response acquisition ended"); + $finish(); + end + end while(acq_trig == 1'b0); + + acqCnt = 0; + + $display(""); + $display("TB> ----------------------------------------------------------------------"); + $display("TB> %s", test_name); + $display("TB> ----------------------------------------------------------------------\n"); + $display(""); + + $display("TB> checking %00d vectors",num_stim); + $display(""); + status.reset(num_stim); + + do begin + + + + out_rdy_i = 1'b1; + + `ACQ_WAIT_SIG(clk_i, in_vld_i) + + opcode_tmp = opcode_i; + op_a_tmp = op_a; + op_b_tmp = op_b; + + ////////////////////////// + // udiv / udiv + if(opcode_i[1] == 1'b0) begin + + res = op_a_tmp/op_b_tmp; + + if((op_b_tmp == 0) && (opcode_i[0] == 0)) begin + res = MAX_NUM64; + end else if ((op_b_tmp == 0) && (opcode_i[0] == 1'b1)) begin + res = -1; + end else if ((op_a_tmp == MIN_NUM) && (op_b_tmp == -1) && (opcode_i[0] == 1'b1)) begin + res = MIN_NUM; + end + + `ACQ_WAIT_SIG(clk_i, out_vld_o) + + // interpret result correctly! + if (opcode_tmp[0] == 1'b1) + act = $signed(res_o); + else + act = $unsigned(res_o); + + opStr="/"; + ////////////////////////// + // rem / urem + end else if(opcode_i[1] == 1'b1) begin + + res = op_a_tmp % op_b_tmp; + + if((op_b_tmp == 0)) begin + res = op_a_tmp; + end + + `ACQ_WAIT_SIG(clk_i, out_vld_o) + + // interpret result correctly! + if (opcode_tmp[0] == 1'b1) + act = $signed(res_o); + else + act = $unsigned(res_o); + + opStr="\%"; + end + + ok = (res==act); + + if(VERBOSE | !ok) begin + if(!ok) tmpstr = $psprintf("vector: %04d> %d %s %d = %d != %d -> error!", acqCnt, op_a_tmp, opStr, op_b_tmp, res, act); + else tmpstr = $psprintf("vector: %04d> %d %s %d = %d == %d " , acqCnt, op_a_tmp, opStr, op_b_tmp, res, act); + $display("TB> %s", tmpstr); + end + + if(!ok) begin + failingTests = $psprintf("%sTB> %s\n", failingTests, tmpstr); + end + + status.addRes(!ok); + status.print(); + + // status + acqCnt++; + end + while (acqCnt < num_stim); + end + /////////////////////////////////////////////// + + status.printToFile("summary.rep", 1); + + if(status.totErrCnt == 0) begin + $display("TB> ----------------------------------------------------------------------"); + $display("TB> PASSED %0d VECTORS", status.totAcqCnt); + $display("TB> ----------------------------------------------------------------------\n"); + end else begin + $display("TB> ----------------------------------------------------------------------\n"); + $display("TB> FAILED %0d OF %0d VECTORS\n" , status.totErrCnt, status.totAcqCnt); + $display("TB> failing tests:"); + $display("TB", failingTests); + $display("TB> ----------------------------------------------------------------------\n"); + end + + end_of_sim <= 1; + $finish(); + /////////////////////////////////////////////// + end + +endmodule diff --git a/tb/tb_serdiv/hdl/tb_div.sv b/tb/tb_serdiv/hdl/tb_div.sv new file mode 100644 index 0000000000..4cd5cd8ce0 --- /dev/null +++ b/tb/tb_serdiv/hdl/tb_div.sv @@ -0,0 +1,117 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner (schaffner@iis.ee.ethz.ch), ETH Zurich +// Andreas Traber (traber@iis.ee.ethz.ch), ETH Zurich +// +// Date: 18.10.2018 +// Description: testbench for serial 64bit divider +// + +/////////////////////////////////////////////// +// unsigned division test + +// init +num_stim = 5+1000; + +test_name = "div test"; + +acq_trig <= 1; +`APPL_WAIT_CYC(clk_i, 2) +acq_trig <= 0; +`APPL_WAIT_CYC(clk_i, 2) + +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +opcode_i = 1; + +op_a = 100; +op_b = -10; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = -100; +op_b = -10; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = -100; +op_b = 0; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + + +op_a = MIN_NUM; +op_b = 1; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + + +op_a = MIN_NUM; +op_b = -1; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +//////////////////// +// a couple of random stimuli + +for (k = 0; k < 1000; k++) begin + + + void'(randomize(op_a_i)); + void'(randomize(op_b_i)); + op_a = $signed(op_a_i); + op_b = $signed(op_b_i); + + in_vld_i = 1; + `APPL_WAIT_CYC(clk_i, 1) + in_vld_i = 0; + `APPL_WAIT_SIG(clk_i, in_rdy_o) + +end + +`APPL_WAIT_CYC(clk_i, 400) + +/////////////////////////////////////////////// diff --git a/tb/tb_serdiv/hdl/tb_pkg.sv b/tb/tb_serdiv/hdl/tb_pkg.sv new file mode 100644 index 0000000000..9767d472e2 --- /dev/null +++ b/tb/tb_serdiv/hdl/tb_pkg.sv @@ -0,0 +1,148 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner (schaffner@iis.ee.ethz.ch), ETH Zurich +// Andreas Traber (traber@iis.ee.ethz.ch), ETH Zurich +// +// Date: 18.10.2018 +// Description: testbench package with some helper functions. +// + +package tb_pkg; + + // // for abs(double) function + // import mti_cstdlib::*; + + // for timestamps + import "DPI-C" \time = function int _time (inout int tloc[4]); + import "DPI-C" function string ctime(inout int tloc[4]); + +/////////////////////////////////////////////////////////////////////////////// +// parameters +/////////////////////////////////////////////////////////////////////////////// + + // creates a 10ns ATI timing cycle + time CLK_HI = 5ns; // set clock high time + time CLK_LO = 5ns; // set clock low time + time CLK_PERIOD = CLK_HI+CLK_LO; + time APPL_DEL = 2ns; // set stimuli application delay + time ACQ_DEL = 8ns; // set response aquisition delay + + parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation... + + // tb_readport sequences + typedef enum logic [2:0] { RANDOM_SEQ, LINEAR_SEQ, BURST_SEQ, IDLE_SEQ, WRAP_SEQ } seq_t; + +/////////////////////////////////////////////////////////////////////////////// +// progress +/////////////////////////////////////////////////////////////////////////////// + + class progress; + real newState, oldState; + longint numResp, acqCnt, errCnt, totAcqCnt, totErrCnt; + string name; + + function new(string name); + begin + this.name = name; + this.acqCnt = 0; + this.errCnt = 0; + this.newState = 0.0; + this.oldState = 0.0; + this.numResp = 1; + this.totAcqCnt = 0; + this.totErrCnt = 0; + + end + endfunction : new + + function void reset(longint numResp_); + begin + this.acqCnt = 0; + this.errCnt = 0; + this.newState = 0.0; + this.oldState = 0.0; + this.numResp = numResp_; + end + endfunction : reset + + function void addRes(int isError); + begin + this.acqCnt++; + this.totAcqCnt++; + this.errCnt += isError; + this.totErrCnt += isError; + + if(ERROR_CNT_STOP_LEVEL <= this.errCnt && ERROR_CNT_STOP_LEVEL > 0) begin + $error("%s> simulation stopped (ERROR_CNT_STOP_LEVEL = %d reached).", this.name, ERROR_CNT_STOP_LEVEL); + $stop(); + end + end + endfunction : addRes + + function void print(); + begin + this.newState = $itor(this.acqCnt) / $itor(this.numResp); + if(this.newState - this.oldState >= 0.01) begin + $display("%s> validated %03d%% -- %01d failed (%03.3f%%) ", + this.name, + $rtoi(this.newState*100.0), + this.errCnt, + $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); + // $fflush(); + this.oldState = this.newState; + end + end + endfunction : print + + function void printToFile(string file, bit summary = 0); + begin + int fptr; + + // sanitize string + for(fptr=0; fptr<$size(file);fptr++) begin + if(file[fptr] == " " || file[fptr] == "/" || file[fptr] == "\\") begin + file[fptr] = "_"; + end + end + + + fptr = $fopen(file,"w"); + if(summary) begin + $fdisplay(fptr, "Simulation Summary of %s", this.name); + $fdisplay(fptr, "total: %01d of %01d vectors failed (%03.3f%%) ", + this.totErrCnt, + this.totAcqCnt, + $itor(this.totErrCnt) / ($itor(this.totAcqCnt) * 100.0 + 0.000000001)); + if(this.totErrCnt == 0) begin + $fdisplay(fptr, "CI: PASSED"); + end else begin + $fdisplay(fptr, "CI: FAILED"); + end + end else begin + $fdisplay(fptr, "test name: %s", file); + $fdisplay(fptr, "this test: %01d of %01d vectors failed (%03.3f%%) ", + this.errCnt, + this.acqCnt, + $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); + + $fdisplay(fptr, "total so far: %01d of %01d vectors failed (%03.3f%%) ", + this.totErrCnt, + this.totAcqCnt, + $itor(this.totErrCnt) / $itor(this.totAcqCnt) * 100.0); + end + $fclose(fptr); + end + endfunction : printToFile + + endclass : progress + +endpackage : tb_pkg + diff --git a/tb/tb_serdiv/hdl/tb_rem.sv b/tb/tb_serdiv/hdl/tb_rem.sv new file mode 100644 index 0000000000..81bb933416 --- /dev/null +++ b/tb/tb_serdiv/hdl/tb_rem.sv @@ -0,0 +1,116 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner (schaffner@iis.ee.ethz.ch), ETH Zurich +// Andreas Traber (traber@iis.ee.ethz.ch), ETH Zurich +// +// Date: 18.10.2018 +// Description: testbench for serial 64bit divider + +/////////////////////////////////////////////// +// unsigned division test + +// init +num_stim = 5+1000; + +test_name = "rem test"; + +acq_trig <= 1; +`APPL_WAIT_CYC(clk_i, 2) +acq_trig <= 0; +`APPL_WAIT_CYC(clk_i, 2) + +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +opcode_i = 3; + +op_a = 100; +op_b = -10; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +in_vld_i = 0; + +op_a = -100; +op_b = -10; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = -100; +op_b = 0; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = MIN_NUM; +op_b = 1; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = MIN_NUM; +op_b = -1; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +//////////////////// +// a couple of random stimuli + +for (k = 0; k < 1000; k++) begin + + void'(randomize(op_a_i)); + void'(randomize(op_b_i)); + op_a = $signed(op_a_i); + op_b = $signed(op_b_i); + + in_vld_i = 1; + `APPL_WAIT_CYC(clk_i, 1) + in_vld_i = 0; + `APPL_WAIT_SIG(clk_i, in_rdy_o) + +end + +`APPL_WAIT_CYC(clk_i, 400) + +/////////////////////////////////////////////// diff --git a/tb/tb_serdiv/hdl/tb_udiv.sv b/tb/tb_serdiv/hdl/tb_udiv.sv new file mode 100644 index 0000000000..1bee977c9a --- /dev/null +++ b/tb/tb_serdiv/hdl/tb_udiv.sv @@ -0,0 +1,127 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner (schaffner@iis.ee.ethz.ch), ETH Zurich +// Andreas Traber (traber@iis.ee.ethz.ch), ETH Zurich +// +// Date: 18.10.2018 +// Description: testbench for serial 64bit divider + +/////////////////////////////////////////////// +// unsigned division test + +// init +num_stim = 6+1000; + +test_name = "udiv test"; + +acq_trig <= 1; +`APPL_WAIT_CYC(clk_i, 2) +acq_trig <= 0; +`APPL_WAIT_CYC(clk_i, 2) + +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +opcode_i = 0; + +op_a = 100; +op_b = 2; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = MAX_NUM64; +op_b = 1; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = 1; +op_b = MAX_NUM64; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = 0; +op_b = 5456; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = 875; +op_b = 0; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = 0; +op_b = 0; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + + +//////////////////// +// a couple of random stimuli + +for (k = 0; k < 1000; k++) begin + + void'(randomize(op_a_i)); + void'(randomize(op_b_i)); + op_a = op_a_i; + op_b = op_b_i; + + in_vld_i = 1; + `APPL_WAIT_CYC(clk_i, 1) + in_vld_i = 0; + `APPL_WAIT_SIG(clk_i, in_rdy_o) + +end + +`APPL_WAIT_CYC(clk_i, 400) + +/////////////////////////////////////////////// diff --git a/tb/tb_serdiv/hdl/tb_urem.sv b/tb/tb_serdiv/hdl/tb_urem.sv new file mode 100644 index 0000000000..e413c27f42 --- /dev/null +++ b/tb/tb_serdiv/hdl/tb_urem.sv @@ -0,0 +1,127 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner (schaffner@iis.ee.ethz.ch), ETH Zurich +// Andreas Traber (traber@iis.ee.ethz.ch), ETH Zurich +// +// Date: 18.10.2018 +// Description: testbench for serial 64bit divider + +/////////////////////////////////////////////// +// unsigned division test + +// init +num_stim = 6+1000; + +test_name = "urem test"; + +acq_trig <= 1; +`APPL_WAIT_CYC(clk_i, 2) +acq_trig <= 0; +`APPL_WAIT_CYC(clk_i, 2) + +/////////////////////////////////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +opcode_i = 2; + +op_a = 100; +op_b = 2; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = MAX_NUM64; +op_b = 1; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = 1; +op_b = MAX_NUM64; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = 0; +op_b = 5456; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = 875; +op_b = 0; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +//////////////////// +`APPL_WAIT_SIG(clk_i, in_rdy_o) + +op_a = 0; +op_b = 0; + +op_a_i = op_a; +op_b_i = op_b; + +in_vld_i = 1; +`APPL_WAIT_CYC(clk_i, 1) +in_vld_i = 0; +`APPL_WAIT_SIG(clk_i, in_rdy_o) + + +//////////////////// +// a couple of random stimuli + +for (k = 0; k < 1000; k++) begin + + `APPL_WAIT_SIG(clk_i, in_rdy_o) + + void'(randomize(op_a_i)); + void'(randomize(op_b_i)); + op_a = op_a_i; + op_b = op_b_i; + + in_vld_i = 1; + `APPL_WAIT_CYC(clk_i, 1) + in_vld_i = 0; + `APPL_WAIT_SIG(clk_i, in_rdy_o) + +end + +`APPL_WAIT_CYC(clk_i, 400) +/////////////////////////////////////////////// diff --git a/tb/tb_serdiv/tb.list b/tb/tb_serdiv/tb.list new file mode 100644 index 0000000000..913bb7b3e6 --- /dev/null +++ b/tb/tb_serdiv/tb.list @@ -0,0 +1,7 @@ +../../include/riscv_pkg.sv +../../src/debug/dm_pkg.sv +../../include/ariane_pkg.sv +../../src/common_cells/src/lzc.sv +../../src/serdiv.sv +hdl/tb_pkg.sv +hdl/tb.sv diff --git a/tb/tb_serpent_dcache/.gitignore b/tb/tb_serpent_dcache/.gitignore new file mode 100644 index 0000000000..f8cb654656 --- /dev/null +++ b/tb/tb_serpent_dcache/.gitignore @@ -0,0 +1,7 @@ +work +*.rep +transcript +*.ini +*.wlf +*.log + diff --git a/tb/tb_serpent_dcache/Makefile b/tb/tb_serpent_dcache/Makefile new file mode 100755 index 0000000000..f50c9e254b --- /dev/null +++ b/tb/tb_serpent_dcache/Makefile @@ -0,0 +1,42 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# Copyright and related rights are licensed under the Solderpad Hardware +# License, Version 0.51 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +# or agreed to in writing, software, hardware and materials distributed under +# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. +# +# Author: Michael Schaffner , ETH Zurich +# Date: 15.08.2018 +# Description: Makefile for the dcache testbench. + +library ?= work +toplevel ?= tb +src-list := tb.list +inc-path := $(shell pwd)/hdl/ +src := $(shell xargs printf '\n%s' < $(src-list) | cut -b 1-) +compile_flag += +cover+i_dut -incr -64 -nologo +sim_opts += -64 -coverage -classdebug -voptargs="+acc" +questa_version ?= ${QUESTASIM_VERSION} +incdir += ../common/ + +build: clean + vlib${questa_version} $(library) + vlog${questa_version} -work $(library) -pedanticerrors $(src) $(compile_flag) +incdir+$(incdir) + touch $(library)/.build + +# this starts modelsim with gui +sim: build + vsim${questa_version} -lib $(library) $(toplevel) -do "do wave.do" $(sim_opts) + +# batch mode without gui +simc: build + vsim${questa_version} -lib $(library) $(toplevel) -c -do "run -all; exit" $(sim_opts) + +clean: + rm -rf $(library) + +.PHONY: clean simc sim build + diff --git a/tb/tb_serpent_dcache/hdl/tb.sv b/tb/tb_serpent_dcache/hdl/tb.sv new file mode 100644 index 0000000000..9c0a388e0f --- /dev/null +++ b/tb/tb_serpent_dcache/hdl/tb.sv @@ -0,0 +1,633 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: testbench for piton_icache. includes the following tests: +// +// 0) random accesses with disabled cache +// 1) random accesses with enabled cache to cacheable and noncacheable memory +// 2) linear, wrapping sweep with enabled cache +// 3) 1) with random stalls on the memory side and TLB side +// 4) nr 3) with random invalidations +// +// note that we use a simplified address translation scheme to emulate the TLB. +// (random offsets). + +`include "tb.svh" + +import ariane_pkg::*; +import serpent_cache_pkg::*; +import tb_pkg::*; + +module tb; + + // leave this + timeunit 1ps; + timeprecision 1ps; + + // memory configuration (64bit words) + parameter MemBytes = 2**DCACHE_INDEX_WIDTH * 4 * 32; + parameter MemWords = MemBytes>>3; + // noncacheable portion + parameter logic [63:0] CachedAddrBeg = MemBytes>>3;//1/8th of the memory is NC + parameter logic [63:0] CachedAddrEnd = 64'hFFFF_FFFF_FFFF_FFFF; + + // contention and invalidation rates (in %) + parameter MemRandHitRate = 75; + parameter MemRandInvRate = 10; + parameter TlbHitRate = 95; + + // parameters for random read sequences (in %) + parameter FlushRate = 10; + parameter KillRate = 5; + + parameter Verbose = 0; + +/////////////////////////////////////////////////////////////////////////////// +// MUT signal declarations +/////////////////////////////////////////////////////////////////////////////// + + logic enable_i; + logic flush_i; + logic flush_ack_o; + logic miss_o; + logic wbuffer_empty_o; + amo_req_t amo_req_i; + amo_resp_t amo_resp_o; + dcache_req_i_t [2:0] req_ports_i; + dcache_req_o_t [2:0] req_ports_o; + logic mem_rtrn_vld_i; + dcache_rtrn_t mem_rtrn_i; + logic mem_data_req_o; + logic mem_data_ack_i; + dcache_req_t mem_data_o; + +/////////////////////////////////////////////////////////////////////////////// +// TB signal declarations +/////////////////////////////////////////////////////////////////////////////// + + logic [63:0] mem_array[MemWords-1:0]; + + string test_name; + logic clk_i, rst_ni; + logic [31:0] seq_num_resp, seq_num_write; + seq_t [2:0] seq_type; + logic [2:0] seq_done; + logic [6:0] req_rate[2:0]; + logic seq_run, seq_last; + logic end_of_sim; + + logic mem_rand_en; + logic inv_rand_en; + logic amo_rand_en; + logic tlb_rand_en; + + logic write_en; + logic [63:0] write_paddr, write_data; + logic [7:0] write_be; + + logic check_en; + logic [7:0] commit_be; + logic [63:0] commit_paddr; + logic commit_en; + + typedef struct packed { + logic [1:0] size; + logic [63:0] paddr; + } resp_fifo_t; + + logic [63:0] act_paddr[1:0]; + logic [63:0] exp_rdata[1:0]; + logic [63:0] exp_paddr[1:0]; + resp_fifo_t fifo_data_in[1:0]; + resp_fifo_t fifo_data[1:0]; + logic [1:0] fifo_push, fifo_pop, fifo_flush; + logic [2:0] flush; + logic flush_rand_en; + +/////////////////////////////////////////////////////////////////////////////// +// helper tasks +/////////////////////////////////////////////////////////////////////////////// + + task automatic runSeq(input int nReadVectors, input int nWriteVectors = 0, input logic last =1'b0); + seq_last = last; + seq_run = 1'b1; + seq_num_resp = nReadVectors; + seq_num_write = nWriteVectors; + `APPL_WAIT_CYC(clk_i,1) + seq_run = 1'b0; + `APPL_WAIT_SIG(clk_i, &seq_done) + `APPL_WAIT_CYC(clk_i,1) + endtask : runSeq + + task automatic flushCache(); + flush[2] = 1'b1; + `APPL_WAIT_SIG(clk_i, flush_ack_o); + flush[2] = 0'b0; + `APPL_WAIT_CYC(clk_i,1) + endtask : flushCache + + task automatic memCheck(); + check_en = 1'b1; + `APPL_WAIT_CYC(clk_i,1) + check_en = 0'b0; + `APPL_WAIT_CYC(clk_i,1) + endtask : memCheck + + +/////////////////////////////////////////////////////////////////////////////// +// Clock Process +/////////////////////////////////////////////////////////////////////////////// + + always @* + begin + do begin + clk_i = 1;#(CLK_HI); + clk_i = 0;#(CLK_LO); + end while (end_of_sim == 1'b0); + repeat (100) begin + // generate a few extra cycle to allow + // response acquisition to complete + clk_i = 1;#(CLK_HI); + clk_i = 0;#(CLK_LO); + end + end + +/////////////////////////////////////////////////////////////////////////////// +// memory emulation +/////////////////////////////////////////////////////////////////////////////// + + tb_mem #( + .MemRandHitRate ( MemRandHitRate ), + .MemRandInvRate ( MemRandInvRate ), + .MemWords ( MemWords ), + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ) + ) i_tb_mem ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .mem_rand_en_i ( mem_rand_en ), + .inv_rand_en_i ( inv_rand_en ), + .amo_rand_en_i ( amo_rand_en ), + .mem_data_req_i ( mem_data_req_o ), + .mem_data_ack_o ( mem_data_ack_i ), + .mem_data_i ( mem_data_o ), + .mem_rtrn_vld_o ( mem_rtrn_vld_i ), + .mem_rtrn_o ( mem_rtrn_i ), + // for verification + .seq_last_i ( seq_last ), + .check_en_i ( check_en ), + .commit_en_i ( commit_en ), + .commit_be_i ( commit_be ), + .commit_paddr_i ( commit_paddr ), + .write_en_i ( write_en ), + .write_be_i ( write_be ), + .write_data_i ( write_data ), + .write_paddr_i ( write_paddr ), + .mem_array_o ( mem_array ) + ); + +/////////////////////////////////////////////////////////////////////////////// +// MUT +/////////////////////////////////////////////////////////////////////////////// + + serpent_dcache #( + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ) + ) i_dut ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( flush_i ), + .flush_ack_o ( flush_ack_o ), + .enable_i ( enable_i ), + .miss_o ( miss_o ), + .wbuffer_empty_o ( wbuffer_empty_o ), + .amo_req_i ( amo_req_i ), + .amo_resp_o ( amo_resp_o ), + .req_ports_i ( req_ports_i ), + .req_ports_o ( req_ports_o ), + .mem_rtrn_vld_i ( mem_rtrn_vld_i ), + .mem_rtrn_i ( mem_rtrn_i ), + .mem_data_req_o ( mem_data_req_o ), + .mem_data_ack_i ( mem_data_ack_i ), + .mem_data_o ( mem_data_o ) + ); + +/////////////////////////////////////////////////////////////////////////////// +// port emulation programs +/////////////////////////////////////////////////////////////////////////////// + + // get actual paddr from read controllers + assign act_paddr[0] = {i_dut.genblk1[0].i_serpent_dcache_ctrl.address_tag_d, + i_dut.genblk1[0].i_serpent_dcache_ctrl.address_idx_q, + i_dut.genblk1[0].i_serpent_dcache_ctrl.address_off_q}; + assign act_paddr[1] = {i_dut.genblk1[1].i_serpent_dcache_ctrl.address_tag_d, + i_dut.genblk1[1].i_serpent_dcache_ctrl.address_idx_q, + i_dut.genblk1[1].i_serpent_dcache_ctrl.address_off_q}; + + // generate fifo queues for expected responses + generate + for(genvar k=0; k<2;k++) begin + assign fifo_data_in[k] = {req_ports_i[k].data_size, + exp_paddr[k]}; + + assign exp_rdata[k] = mem_array[fifo_data[k].paddr>>3]; + assign fifo_push[k] = req_ports_i[k].data_req & req_ports_o[k].data_gnt; + assign fifo_flush[k] = req_ports_i[k].kill_req; + assign fifo_pop[k] = req_ports_o[k].data_rvalid; + + fifo_v2 #( + .dtype(resp_fifo_t) + ) i_resp_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( fifo_flush[k] ), + .testmode_i ( '0 ), + .full_o ( ), + .empty_o ( ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( fifo_data_in[k] ), + .push_i ( fifo_push[k] ), + .data_o ( fifo_data[k] ), + .pop_i ( fifo_pop[k] ) + ); + end + endgenerate + + tb_readport #( + .PortName ( "RD0" ), + .FlushRate ( FlushRate ), + .KillRate ( KillRate ), + .TlbHitRate ( TlbHitRate ), + .MemWords ( MemWords ), + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ), + .RndSeed ( 5555555 ), + .Verbose ( Verbose ) + ) i_tb_readport0 ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_name_i ( test_name ), + .req_rate_i ( req_rate[0] ), + .seq_type_i ( seq_type[0] ), + .tlb_rand_en_i ( tlb_rand_en ), + .flush_rand_en_i ( flush_rand_en ), + .seq_run_i ( seq_run ), + .seq_num_resp_i ( seq_num_resp ), + .seq_last_i ( seq_last ), + .seq_done_o ( seq_done[0] ), + .exp_paddr_o ( exp_paddr[0] ), + .exp_size_i ( fifo_data[0].size ), + .exp_paddr_i ( fifo_data[0].paddr ), + .exp_rdata_i ( exp_rdata[0] ), + .act_paddr_i ( act_paddr[0] ), + .flush_o ( flush[0] ), + .flush_ack_i ( flush_ack_o ), + .dut_req_port_o ( req_ports_i[0] ), + .dut_req_port_i ( req_ports_o[0] ) + ); + + tb_readport #( + .PortName ( "RD1" ), + .FlushRate ( FlushRate ), + .KillRate ( KillRate ), + .TlbHitRate ( TlbHitRate ), + .MemWords ( MemWords ), + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ), + .RndSeed ( 3333333 ), + .Verbose ( Verbose ) + ) i_tb_readport1 ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_name_i ( test_name ), + .req_rate_i ( req_rate[1] ), + .seq_type_i ( seq_type[1] ), + .tlb_rand_en_i ( tlb_rand_en ), + .flush_rand_en_i ( flush_rand_en ), + .seq_run_i ( seq_run ), + .seq_num_resp_i ( seq_num_resp ), + .seq_last_i ( seq_last ), + .exp_paddr_o ( exp_paddr[1] ), + .exp_size_i ( fifo_data[1].size ), + .exp_paddr_i ( fifo_data[1].paddr ), + .exp_rdata_i ( exp_rdata[1] ), + .act_paddr_i ( act_paddr[1] ), + .seq_done_o ( seq_done[1] ), + .flush_o ( flush[1] ), + .flush_ack_i ( flush_ack_o ), + .dut_req_port_o ( req_ports_i[1] ), + .dut_req_port_i ( req_ports_o[1] ) + ); + + tb_writeport #( + .PortName ( "WR0" ), + .MemWords ( MemWords ), + .CachedAddrBeg ( CachedAddrBeg ), + .CachedAddrEnd ( CachedAddrEnd ), + .RndSeed ( 7777777 ), + .Verbose ( Verbose ) + ) i_tb_writeport ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_name_i ( test_name ), + .req_rate_i ( req_rate[2] ), + .seq_type_i ( seq_type[2] ), + .seq_run_i ( seq_run ), + .seq_num_vect_i ( seq_num_write ), + .seq_last_i ( seq_last ), + .seq_done_o ( seq_done[2] ), + .dut_req_port_o ( req_ports_i[2] ), + .dut_req_port_i ( req_ports_o[2] ) + ); + + assign write_en = req_ports_i[2].data_req & req_ports_o[2].data_gnt & req_ports_i[2].data_we; + assign write_paddr = {req_ports_i[2].address_tag, req_ports_i[2].address_index}; + assign write_data = req_ports_i[2].data_wdata; + assign write_be = req_ports_i[2].data_be; + + // generate write buffer commit signals based on internal eviction status + assign commit_be = i_dut.i_serpent_dcache_wbuffer.wr_data_be_o; + assign commit_paddr = i_dut.i_serpent_dcache_wbuffer.wr_paddr; + assign commit_en = i_dut.i_serpent_dcache_wbuffer.evict; + + // TODO: implement AMO agent + assign amo_req_i.req = '0; + assign amo_req_i.amo_op = AMO_NONE; + assign amo_req_i.size = '0; + assign amo_req_i.operand_a = '0; + assign amo_req_i.operand_b = '0; + // amo_resp_o + + assign flush_i = |flush; + +/////////////////////////////////////////////////////////////////////////////// +// simulation coordinator process +/////////////////////////////////////////////////////////////////////////////// + +// TODO: implement CSR / controller +// flush_i, flush_ack_o, enable_i, miss_o, wbuffer_empty_o + + + initial begin : p_stim + test_name = ""; + seq_type = '{default: RANDOM_SEQ}; + req_rate = '{default: 7'd75}; + seq_run = 1'b0; + seq_last = 1'b0; + seq_num_resp = '0; + seq_num_write = '0; + check_en = '0; + // seq_done + end_of_sim = 0; + rst_ni = 0; + // randomization settings + mem_rand_en = 0; + tlb_rand_en = 0; + inv_rand_en = 0; + amo_rand_en = 0; + flush_rand_en = 0; + // cache ctrl + flush[2] = 0; + // flush_ack_o + // wbuffer_empty_o + enable_i = 0; + // miss_o + + // print some info + $display("TB> current configuration:"); + $display("TB> MemWords %d", MemWords); + $display("TB> CachedAddrBeg %16X", CachedAddrBeg); + $display("TB> CachedAddrEnd %16X", CachedAddrEnd); + $display("TB> MemRandHitRate %d", MemRandHitRate); + $display("TB> MemRandInvRate %d", MemRandInvRate); + + // reset cycles + `APPL_WAIT_CYC(clk_i,100) + rst_ni = 1'b1; + `APPL_WAIT_CYC(clk_i,100) + + $display("TB> start with test sequences"); + // apply each test until seq_num_resp memory + // requests have successfully completed + /////////////////////////////////////////////// + test_name = "TEST 0 -- random read -- disabled cache"; + // config + enable_i = 0; + seq_type = '{default: RANDOM_SEQ}; + req_rate = '{default: 7'd50}; + runSeq(10000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 1 -- sequential read -- disabled cache"; + // config + enable_i = 0; + seq_type = '{default: LINEAR_SEQ}; + req_rate = '{default: 7'd50}; + runSeq(10000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 2 -- random read -- enabled cache"; + // config + enable_i = 1; + seq_type = '{default: RANDOM_SEQ}; + req_rate = '{default: 7'd50}; + runSeq(10000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 3 -- linear read -- enabled cache"; + // config + enable_i = 1; + seq_type = '{default: LINEAR_SEQ}; + req_rate = '{default: 7'd50}; + runSeq(10000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 4 -- random read -- enabled cache + tlb, mem contentions"; + // config + enable_i = 1; + tlb_rand_en = 1; + mem_rand_en = 1; + seq_type = '{default: RANDOM_SEQ}; + req_rate = '{default: 7'd50}; + runSeq(10000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 5 -- linear read -- enabled cache + tlb, mem contentions"; + // config + enable_i = 1; + tlb_rand_en = 1; + mem_rand_en = 1; + seq_type = '{default: LINEAR_SEQ}; + req_rate = '{default: 7'd50}; + runSeq(10000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 6 -- random read -- enabled cache + tlb, mem contentions + invalidations"; + // config + enable_i = 1; + tlb_rand_en = 1; + mem_rand_en = 1; + inv_rand_en = 1; + seq_type = '{default: RANDOM_SEQ}; + req_rate = '{default: 7'd50}; + runSeq(10000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 7 -- random read/write -- disabled cache"; + // config + enable_i = 0; + tlb_rand_en = 0; + mem_rand_en = 0; + inv_rand_en = 0; + seq_type = '{default: RANDOM_SEQ}; + req_rate = '{default: 7'd25}; + runSeq(10000,10000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 8 -- random read/write -- enabled cache"; + // config + enable_i = 1; + tlb_rand_en = 0; + mem_rand_en = 0; + inv_rand_en = 0; + seq_type = '{default: RANDOM_SEQ}; + req_rate = '{default: 7'd25}; + runSeq(10000,20000);// last sequence flag, terminates agents + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 9 -- random read/write -- enabled cache + tlb, mem contentions + invalidations"; + // config + enable_i = 1; + tlb_rand_en = 1; + mem_rand_en = 1; + inv_rand_en = 1; + seq_type = '{default: RANDOM_SEQ}; + req_rate = '{default: 7'd25}; + runSeq(10000,20000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 10 -- linear burst write -- enabled cache"; + // config + enable_i = 1; + tlb_rand_en = 0; + mem_rand_en = 0; + inv_rand_en = 0; + seq_type = '{LINEAR_SEQ, IDLE_SEQ, IDLE_SEQ}; + req_rate = '{100, 0, 0}; + runSeq(0,5000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 11 -- linear burst write with hot cache"; + // config + enable_i = 1; + tlb_rand_en = 0; + mem_rand_en = 0; + inv_rand_en = 0; + seq_type = '{IDLE_SEQ, IDLE_SEQ, LINEAR_SEQ}; + req_rate = '{default:100}; + runSeq((CachedAddrBeg>>3)+(2**(DCACHE_INDEX_WIDTH-3))*DCACHE_SET_ASSOC,0); + seq_type = '{LINEAR_SEQ, IDLE_SEQ, IDLE_SEQ}; + runSeq(0,(CachedAddrBeg>>3)+(2**(DCACHE_INDEX_WIDTH-3))*DCACHE_SET_ASSOC,1); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 12 -- random write bursts -- enabled cache"; + // config + enable_i = 1; + tlb_rand_en = 0; + mem_rand_en = 0; + inv_rand_en = 0; + seq_type = '{BURST_SEQ, RANDOM_SEQ, RANDOM_SEQ}; + req_rate = '{75, 0, 0}; + runSeq(0,5000,0); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 13 -- random write bursts -- enabled cache + tlb, mem contentions + invalidations"; + // config + enable_i = 1; + tlb_rand_en = 1; + mem_rand_en = 1; + inv_rand_en = 1; + seq_type = '{BURST_SEQ, IDLE_SEQ, IDLE_SEQ}; + req_rate = '{75, 0, 0}; + runSeq(0,5000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 14 -- random write/read-- enabled cache + tlb, mem contentions + invalidations"; + // config + enable_i = 1; + tlb_rand_en = 1; + mem_rand_en = 1; + inv_rand_en = 1; + seq_type = '{RANDOM_SEQ, RANDOM_SEQ, RANDOM_SEQ}; + req_rate = '{default:25}; + runSeq(5000,5000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 15 -- short wrapping sequences to provoke writebuffer hits"; + // config + enable_i = 1; + tlb_rand_en = 0; + mem_rand_en = 0; + inv_rand_en = 0; + seq_type = '{WRAP_SEQ, IDLE_SEQ, WRAP_SEQ}; + req_rate = '{100,0,20}; + runSeq(5000,5000); + flushCache(); + memCheck(); + /////////////////////////////////////////////// + test_name = "TEST 16 -- random write/read-- enabled cache + tlb, mem contentions + invalidations + random flushes"; + // config + enable_i = 1; + tlb_rand_en = 1; + mem_rand_en = 1; + inv_rand_en = 1; + flush_rand_en = 1; + seq_type = '{RANDOM_SEQ, RANDOM_SEQ, RANDOM_SEQ}; + req_rate = '{default:25}; + runSeq(5000,5000,1);// last sequence flag, terminates agents + flushCache(); + memCheck(); + /////////////////////////////////////////////// + end_of_sim = 1; + $display("TB> end test sequences"); + end + + +endmodule + + + + + + + + + + + + diff --git a/tb/tb_serpent_dcache/hdl/tb_mem.sv b/tb/tb_serpent_dcache/hdl/tb_mem.sv new file mode 100644 index 0000000000..9cb7a200d6 --- /dev/null +++ b/tb/tb_serpent_dcache/hdl/tb_mem.sv @@ -0,0 +1,364 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: simple emulation layer for the memory subsystem. +// + + +`include "tb.svh" + +import ariane_pkg::*; +import serpent_cache_pkg::*; +import tb_pkg::*; + +module tb_mem #( + parameter string MemName = "TB_MEM", + parameter MemRandHitRate = 10, //in percent + parameter MemRandInvRate = 5, //in percent + parameter MemWords = 1024*1024,// in 64bit words + parameter logic [63:0] CachedAddrBeg = MemWords/2, + parameter logic [63:0] CachedAddrEnd = 64'hFFFF_FFFF_FFFF_FFFF +) ( + input logic clk_i, + input logic rst_ni, + // randomization settings + input logic mem_rand_en_i, + input logic inv_rand_en_i, + input logic amo_rand_en_i, + // dcache interface + output logic mem_rtrn_vld_o, + output dcache_rtrn_t mem_rtrn_o, + input logic mem_data_req_i, + output logic mem_data_ack_o, + input dcache_req_t mem_data_i, + // expected response interface + input logic seq_last_i, + input logic check_en_i, + input logic commit_en_i, + input logic [7:0] commit_be_i, + input logic [63:0] commit_paddr_i, + input logic write_en_i, + input logic [7:0] write_be_i, + input logic [63:0] write_data_i, + input logic [63:0] write_paddr_i, + output logic [63:0] mem_array_o[MemWords-1:0] +); + + // leave this + timeunit 1ps; + timeprecision 1ps; + + logic mem_ready_q, mem_inv_q; + logic [63:0] rand_addr_q; + + dcache_req_t outfifo_data; + logic outfifo_pop, outfifo_push, outfifo_full, outfifo_empty; + dcache_rtrn_t infifo_data; + logic infifo_pop, infifo_push, infifo_full, infifo_empty; + + logic initialized_q; + logic write_en; + + logic [63:0] mem_array_q[MemWords-1:0]; + + // this shadow memory provides a view that is consistent with the one from the core + // i.e., pending writes are present in this view, and invalidations will not overwrite + // the corresponding bytes until they have been commited to the normal memory. + logic [63:0] mem_array_shadow_q[MemWords-1:0]; + logic [7:0] mem_array_dirty_q[MemWords-1:0]; + + assign mem_array_o = mem_array_shadow_q; + + // sequential process holding the state of the memory readout process + always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlb_rand + automatic int rnd = 0; + automatic logic [63:0] val; + automatic logic [63:0] lval; + + if(~rst_ni) begin + mem_ready_q <= '0; + mem_inv_q <= '0; + rand_addr_q <= '0; + initialized_q <= '0; + end else begin + + // fill the memory once with random data + if (initialized_q) begin + // commit "virtual" writes (i.e., clear the dirty flags) + if(commit_en_i) begin + for(int k=0; k<8; k++) begin + if(commit_be_i[k]) begin + mem_array_dirty_q[commit_paddr_i>>3][k] <= 1'b0; + end + end + end + + // "virtual" writes coming from TB agent, used to generate expected responses + if(write_en_i) begin + for(int k=0; k<8; k++) begin + if(write_be_i[k]) begin + mem_array_shadow_q[write_paddr_i>>3][k*8 +: 8] <= write_data_i[k*8 +: 8]; + mem_array_dirty_q[write_paddr_i>>3][k] <= 1'b1; + end + end + end + + // "real" writes coming via the miss controller + if(write_en) begin + unique case(outfifo_data.size) + 3'b000: mem_array_q[outfifo_data.paddr>>3][outfifo_data.paddr[2:0]*8 +: 8] = outfifo_data.data[outfifo_data.paddr[2:0]*8 +: 8]; + 3'b001: mem_array_q[outfifo_data.paddr>>3][outfifo_data.paddr[2:1]*16 +: 16] = outfifo_data.data[outfifo_data.paddr[2:1]*16 +: 16]; + 3'b010: mem_array_q[outfifo_data.paddr>>3][outfifo_data.paddr[2:2]*32 +: 32] = outfifo_data.data[outfifo_data.paddr[2:2]*32 +: 32]; + 3'b011: mem_array_q[outfifo_data.paddr>>3] = outfifo_data.data[0 +: 64]; + default: begin + $fatal(1,"unsupported transfer size for write"); + end + endcase // infifo_data.size + end + // initialization with random data + end else begin + mem_array_dirty_q <= '{default:'0}; + + for (int k=0; k 0; rnd <= 100;}); + if(rnd < MemRandHitRate) begin + mem_ready_q <= '1; + end else begin + mem_ready_q <= '0; + end + end else begin + mem_ready_q <= '1; + end + + // generate random invalidations + if (inv_rand_en_i) begin + void'(randomize(rnd) with {rnd > 0; rnd <= 100;}); + if(rnd < MemRandInvRate) begin + mem_inv_q <= '1; + void'(randomize(lval) with {lval>=0; lval<(MemWords>>3);}); + void'(randomize(val)); + rand_addr_q <= lval<<3; + + // with the current TB setup, we cannot invalidate a memory location if a write response to the same address is + // in flight, since this could lead to an incosistent state between the real memory and the shadow memory view. + // the workaround is not to overwrite shadow memory regions that are still pending in the write buffer + // this can be improved. + for(int k=0; k<8; k++) begin + if(~mem_array_dirty_q[lval][k]) begin + mem_array_q [lval][k*8 +: 8] <= val[k*8 +: 8]; + mem_array_shadow_q[lval][k*8 +: 8] <= val[k*8 +: 8]; + end + end + end else begin + mem_inv_q <= '0; + end + end else begin + mem_inv_q <= '0; + end + end + end + + + // readout process + always_comb begin : proc_mem + infifo_push = 0; + infifo_data = '0; + outfifo_pop = 0; + infifo_data.rtype = DCACHE_LOAD_ACK; + infifo_data.data = 'x; + write_en = '0; + + // TODO: atomic request + // DCACHE_ATOMIC_REQ + // DCACHE_ATOMIC_ACK + + // TODO: stores + // DCACHE_STORE_REQ + // DCACHE_STORE_ACK + + // TODO: interrupts + // DCACHE_INT_REQ + // DCACHE_INT_ACK + + // generate random invalidation + if (mem_inv_q) begin + + infifo_data.rtype = DCACHE_INV_REQ; + + // since we do not keep a mirror tag table here, + // we allways invalidate all ways of the aliased index. + // this is not entirely correct and will produce + // too many invalidations + infifo_data.inv.idx = rand_addr_q[DCACHE_INDEX_WIDTH-1:0]; + infifo_data.inv.all = '1; + infifo_push = 1'b1; + + end else if ((~outfifo_empty) && (~infifo_full) && mem_ready_q) begin + + outfifo_pop = 1'b1; + infifo_push = 1'b1; + + unique case (outfifo_data.rtype) + DCACHE_LOAD_REQ: begin + infifo_data.tid = outfifo_data.tid; + infifo_data.nc = outfifo_data.nc; + infifo_data.data = 'x; + unique case(outfifo_data.size) + 3'b000: for(int k=0;k<64;k+=8) infifo_data.data[outfifo_data.paddr[2:0]*8 +: 8] = mem_array_q[outfifo_data.paddr>>3][outfifo_data.paddr[2:0]*8 +: 8]; + 3'b001: for(int k=0;k<64;k+=16) infifo_data.data[outfifo_data.paddr[2:1]*16+:16] = mem_array_q[outfifo_data.paddr>>3][outfifo_data.paddr[2:1]*16+:16]; + 3'b010: for(int k=0;k<64;k+=32) infifo_data.data[outfifo_data.paddr[2] *32+:32] = mem_array_q[outfifo_data.paddr>>3][outfifo_data.paddr[2] *32+:32]; + 3'b011: infifo_data.data[0+:64] = mem_array_q[outfifo_data.paddr>>3]; + 3'b111: for(int k=0; k>3) + k]; + default: $fatal(1,"unsupported transfer size for read"); + endcase // infifo_data.size + end + DCACHE_STORE_REQ: begin + infifo_data.tid = outfifo_data.tid; + infifo_data.rtype = DCACHE_STORE_ACK; + infifo_data.nc = outfifo_data.nc; + write_en = 1'b1; + end + // DCACHE_ATOMIC_REQ: $fatal(1, "DCACHE_ATOMIC_REQ not implemented yet"); + // DCACHE_INT_REQ: $fatal(1, "DCACHE_INT_REQ not implemented yet"); + default: begin + // $fatal(1, "unsupported request type"); + end + endcase // outfifo_data.rtype + end + end + + fifo_v2 #( + .dtype(dcache_req_t), + .DEPTH(2) + ) i_outfifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( outfifo_full ), + .empty_o ( outfifo_empty ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( mem_data_i ), + .push_i ( outfifo_push ), + .data_o ( outfifo_data ), + .pop_i ( outfifo_pop ) + ); + + assign outfifo_push = mem_data_req_i & (~outfifo_full); + assign mem_data_ack_o = outfifo_push; + + fifo_v2 #( + .dtype(dcache_rtrn_t), + .DEPTH(2) + ) i_infifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( infifo_full ), + .empty_o ( infifo_empty ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( infifo_data ), + .push_i ( infifo_push ), + .data_o ( mem_rtrn_o ), + .pop_i ( infifo_pop ) + ); + + assign infifo_pop = ~infifo_empty; + assign mem_rtrn_vld_o = infifo_pop; + + +/////////////////////////////////////////////////////// +// checker process +/////////////////////////////////////////////////////// + + initial begin + bit ok; + progress status; + status = new(MemName); + + `ACQ_WAIT_CYC(clk_i,10) + `ACQ_WAIT_SIG(clk_i,~rst_ni) + + while(~seq_last_i) begin + `ACQ_WAIT_SIG(clk_i,check_en_i) + status.reset(MemWords); + // crosscheck whether shadow and real memory arrays still match + for(int k=0; k dirty bytes at k=%016X: real[k>>3]=%016X, shadow[k>>3]=%016X, dirty[k>>3]=%02X", + MemName, k<<3, mem_array_q[k], mem_array_shadow_q[k], mem_array_dirty_q[k]); + end + status.addRes(!ok); + status.print(); + end + end + status.printToFile({MemName, "_summary.rep"}, 1); + + if(status.totErrCnt == 0) begin + $display("%s> ----------------------------------------------------------------------", MemName); + $display("%s> PASSED %0d VECTORS", MemName, status.totAcqCnt); + $display("%s> ----------------------------------------------------------------------\n", MemName); + end else begin + $display("%s> ----------------------------------------------------------------------\n", MemName); + $display("%s> FAILED %0d OF %0d VECTORS\n", MemName , status.totErrCnt, status.totAcqCnt); + $display("%s> ----------------------------------------------------------------------\n", MemName); + end + end + + + + +/////////////////////////////////////////////////////// +// assertions +/////////////////////////////////////////////////////// + +//pragma translate_off +`ifndef verilator + + nc_region: assert property ( + @(posedge clk_i) disable iff (~rst_ni) mem_data_req_i |-> mem_data_i.paddr >= CachedAddrEnd || mem_data_i.paddr < CachedAddrBeg |-> mem_data_i.nc) + else $fatal(1, "cached access into noncached region"); + + cached_reads: assert property ( + @(posedge clk_i) disable iff (~rst_ni) mem_data_req_i |-> mem_data_i.rtype==DCACHE_LOAD_REQ |-> ~mem_data_i.nc |-> mem_data_i.size == 3'b111) + else $fatal(1, "cached read accesses always have to be one CL wide"); + + nc_reads: assert property ( + @(posedge clk_i) disable iff (~rst_ni) mem_data_req_i |-> mem_data_i.rtype==DCACHE_LOAD_REQ |-> mem_data_i.nc |-> mem_data_i.size inside {3'b000, 3'b001, 3'b010, 3'b011}) + else $fatal(1, "nc read size can only be one of the following: byte, halfword, word, dword"); + + write_size: assert property ( + @(posedge clk_i) disable iff (~rst_ni) mem_data_req_i |-> mem_data_i.rtype==DCACHE_STORE_REQ |-> mem_data_i.size inside {3'b000, 3'b001, 3'b010, 3'b011}) + else $fatal(1, "write size can only be one of the following: byte, halfword, word, dword"); + + addr_range: assert property ( + @(posedge clk_i) disable iff (~rst_ni) mem_data_req_i |-> mem_data_i.rtype inside {DCACHE_STORE_REQ, DCACHE_STORE_REQ} |-> mem_data_i.paddr < (MemWords<<3)) + else $fatal(1, "address is out of bounds"); + +`endif +//pragma translate_on + +endmodule // mem_emul diff --git a/tb/tb_serpent_dcache/hdl/tb_pkg.sv b/tb/tb_serpent_dcache/hdl/tb_pkg.sv new file mode 100644 index 0000000000..1ee8f9686d --- /dev/null +++ b/tb/tb_serpent_dcache/hdl/tb_pkg.sv @@ -0,0 +1,146 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: testbench package with some helper functions. + + +package tb_pkg; + + // // for abs(double) function + // import mti_cstdlib::*; + + // for timestamps + import "DPI-C" \time = function int _time (inout int tloc[4]); + import "DPI-C" function string ctime(inout int tloc[4]); + +/////////////////////////////////////////////////////////////////////////////// +// parameters +/////////////////////////////////////////////////////////////////////////////// + + // creates a 10ns ATI timing cycle + time CLK_HI = 5ns; // set clock high time + time CLK_LO = 5ns; // set clock low time + time CLK_PERIOD = CLK_HI+CLK_LO; + time APPL_DEL = 2ns; // set stimuli application delay + time ACQ_DEL = 8ns; // set response aquisition delay + + parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation... + + // tb_readport sequences + typedef enum logic [2:0] { RANDOM_SEQ, LINEAR_SEQ, BURST_SEQ, IDLE_SEQ, WRAP_SEQ } seq_t; + +/////////////////////////////////////////////////////////////////////////////// +// progress +/////////////////////////////////////////////////////////////////////////////// + + class progress; + real newState, oldState; + longint numResp, acqCnt, errCnt, totAcqCnt, totErrCnt; + string name; + + function new(string name); + begin + this.name = name; + this.acqCnt = 0; + this.errCnt = 0; + this.newState = 0.0; + this.oldState = 0.0; + this.numResp = 1; + this.totAcqCnt = 0; + this.totErrCnt = 0; + + end + endfunction : new + + function void reset(longint numResp_); + begin + this.acqCnt = 0; + this.errCnt = 0; + this.newState = 0.0; + this.oldState = 0.0; + this.numResp = numResp_; + end + endfunction : reset + + function void addRes(int isError); + begin + this.acqCnt++; + this.totAcqCnt++; + this.errCnt += isError; + this.totErrCnt += isError; + + if(ERROR_CNT_STOP_LEVEL <= this.errCnt && ERROR_CNT_STOP_LEVEL > 0) begin + $error("%s> simulation stopped (ERROR_CNT_STOP_LEVEL = %d reached).", this.name, ERROR_CNT_STOP_LEVEL); + $stop(); + end + end + endfunction : addRes + + function void print(); + begin + this.newState = $itor(this.acqCnt) / $itor(this.numResp); + if(this.newState - this.oldState >= 0.01) begin + $display("%s> validated %03d%% -- %01d failed (%03.3f%%) ", + this.name, + $rtoi(this.newState*100.0), + this.errCnt, + $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); + // $fflush(); + this.oldState = this.newState; + end + end + endfunction : print + + function void printToFile(string file, bit summary = 0); + begin + int fptr; + + // sanitize string + for(fptr=0; fptr<$size(file);fptr++) begin + if(file[fptr] == " " || file[fptr] == "/" || file[fptr] == "\\") begin + file[fptr] = "_"; + end + end + + + fptr = $fopen(file,"w"); + if(summary) begin + $fdisplay(fptr, "Simulation Summary of %s", this.name); + $fdisplay(fptr, "total: %01d of %01d vectors failed (%03.3f%%) ", + this.totErrCnt, + this.totAcqCnt, + $itor(this.totErrCnt) / ($itor(this.totAcqCnt) * 100.0 + 0.000000001)); + if(this.totErrCnt == 0) begin + $fdisplay(fptr, "CI: PASSED"); + end else begin + $fdisplay(fptr, "CI: FAILED"); + end + end else begin + $fdisplay(fptr, "test name: %s", file); + $fdisplay(fptr, "this test: %01d of %01d vectors failed (%03.3f%%) ", + this.errCnt, + this.acqCnt, + $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); + + $fdisplay(fptr, "total so far: %01d of %01d vectors failed (%03.3f%%) ", + this.totErrCnt, + this.totAcqCnt, + $itor(this.totErrCnt) / $itor(this.totAcqCnt) * 100.0); + end + $fclose(fptr); + end + endfunction : printToFile + + endclass : progress + +endpackage : tb_pkg + diff --git a/tb/tb_serpent_dcache/hdl/tb_readport.sv b/tb/tb_serpent_dcache/hdl/tb_readport.sv new file mode 100644 index 0000000000..cc71cd4edb --- /dev/null +++ b/tb/tb_serpent_dcache/hdl/tb_readport.sv @@ -0,0 +1,388 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: program that emulates a cache readport. the program can generate +// randomized or linear read sequences, and it checks the returned responses against +// the expected responses coming directly from the emulated memory (tb_mem). +// + +`include "tb.svh" + +import ariane_pkg::*; +import serpent_cache_pkg::*; +import tb_pkg::*; + +program tb_readport #( + parameter string PortName = "read port 0", + parameter FlushRate = 1, + parameter KillRate = 5, + parameter TlbHitRate = 95, + parameter MemWords = 1024*1024,// in 64bit words + parameter logic [63:0] CachedAddrBeg = 0, + parameter logic [63:0] CachedAddrEnd = 0, + parameter RndSeed = 1110, + parameter Verbose = 0 +) ( + input logic clk_i, + input logic rst_ni, + + // to testbench master + ref string test_name_i, + input logic [6:0] req_rate_i, //a rate between 0 and 100 percent + input seq_t seq_type_i, + input logic tlb_rand_en_i, + input logic flush_rand_en_i, + input logic seq_run_i, + input logic [31:0] seq_num_resp_i, + input logic seq_last_i, + output logic seq_done_o, + + // expresp interface + output logic [63:0] exp_paddr_o, + input logic [1:0] exp_size_i, + input logic [63:0] exp_rdata_i, + input logic [63:0] exp_paddr_i, + input logic [63:0] act_paddr_i, + + // interface to DUT + output logic flush_o, + input logic flush_ack_i, + output dcache_req_i_t dut_req_port_o, + input dcache_req_o_t dut_req_port_i +); + + // leave this + timeunit 1ps; + timeprecision 1ps; + + logic [63:0] paddr; + logic seq_end_req, seq_end_ack, prog_end; + logic [DCACHE_TAG_WIDTH-1:0] tag_q; + logic [DCACHE_TAG_WIDTH-1:0] tag_vld_q; + + +/////////////////////////////////////////////////////////////////////////////// +// Randomly delay the tag by at least one cycle +/////////////////////////////////////////////////////////////////////////////// + + // // TODO: add randomization + initial begin : p_tag_delay + logic [63:0] tmp_paddr, val; + int unsigned cnt; + logic tmp_vld; + + tag_q <= '0; + tag_vld_q <= 1'b0; + + `APPL_WAIT_CYC(clk_i, 10) + `APPL_WAIT_SIG(clk_i,~rst_ni) + `APPL_WAIT_CYC(clk_i,1) + + tmp_vld = 0; + cnt = 0; + forever begin + `APPL_WAIT_CYC(clk_i,1) + + if(cnt==0) begin + if(tmp_vld) begin + tmp_vld = 0; + tag_q <= tmp_paddr[DCACHE_TAG_WIDTH+DCACHE_INDEX_WIDTH-1:DCACHE_INDEX_WIDTH]; + tag_vld_q <= 1'b1; + end else begin + tag_vld_q <= 1'b0; + end + + `APPL_ACQ_WAIT; + if(dut_req_port_o.data_req) begin + tmp_paddr = paddr; + tmp_vld = 1; + + if(tlb_rand_en_i) begin + void'(randomize(val) with {val>0; val<=100;}); + if(val>=TlbHitRate) begin + void'(randomize(cnt) with {cnt>0; cnt<=50;}); + end + end + end + end else begin + tag_vld_q <= 1'b0; + cnt -= 1; + `APPL_ACQ_WAIT; + end + + if(dut_req_port_o.kill_req) begin + tmp_vld = 0; + cnt = 0; + end + end + end + + assign dut_req_port_o.address_tag = tag_q; + assign dut_req_port_o.tag_valid = tag_vld_q; + assign dut_req_port_o.address_index = paddr[DCACHE_INDEX_WIDTH-1:0]; + assign exp_paddr_o = paddr; + +/////////////////////////////////////////////////////////////////////////////// +// Helper tasks +/////////////////////////////////////////////////////////////////////////////// + + task automatic flushCache(); + flush_o = 1'b1; + `APPL_WAIT_SIG(clk_i, flush_ack_i); + flush_o = 0'b0; + `APPL_WAIT_CYC(clk_i,1) + endtask : flushCache + + + task automatic genRandReq(); + automatic logic [63:0] val; + automatic logic [1:0] size; + + void'($urandom(RndSeed)); + + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.kill_req = '0; + + while(~seq_end_req) begin + // randomize request + dut_req_port_o.data_req = '0; + // generate random control events + void'(randomize(val) with {val > 0; val <= 100;}); + if(val < KillRate) begin + dut_req_port_o.kill_req = 1'b1; + `APPL_WAIT_CYC(clk_i,1) + dut_req_port_o.kill_req = 1'b0; + end else begin + void'(randomize(val) with {val > 0; val <= 100;}); + if(val < FlushRate && flush_rand_en_i) begin + flushCache(); + end else begin + void'(randomize(val) with {val > 0; val <= 100;}); + if(val < req_rate_i) begin + dut_req_port_o.data_req = 1'b1; + // generate random address + void'(randomize(val) with {val >= 0; val < (MemWords<<3);}); + void'(randomize(size)); + + dut_req_port_o.data_size = size; + paddr = val; + + // align to size + unique case(size) + 2'b01: paddr[0] = 1'b0; + 2'b10: paddr[1:0] = 2'b00; + 2'b11: paddr[2:0] = 3'b000; + default: ; + endcase + + `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) + end + `APPL_WAIT_CYC(clk_i,1) + end + end + end + + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.kill_req = '0; + + endtask : genRandReq + + task automatic genSeqRead(); + automatic logic [63:0] val; + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.kill_req = '0; + val = '0; + while(~seq_end_req) begin + dut_req_port_o.data_req = 1'b1; + dut_req_port_o.data_size = 2'b11; + paddr = val; + // generate linear read + val = (val + 8) % (MemWords<<3); + `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) + `APPL_WAIT_CYC(clk_i,1) + end + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.kill_req = '0; + endtask : genSeqRead + + task automatic genWrapSeq(); + automatic logic [63:0] val; + paddr = CachedAddrBeg; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.kill_req = '0; + val = '0; + while(~seq_end_req) begin + dut_req_port_o.data_req = 1'b1; + dut_req_port_o.data_size = 2'b11; + paddr = val; + // generate wrapping read of 1 cachelines + paddr = CachedAddrBeg + val; + val = (val + 8) % (1*(DCACHE_LINE_WIDTH/64)*8); + `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) + `APPL_WAIT_CYC(clk_i,1) + end + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.kill_req = '0; + endtask : genWrapSeq + + +/////////////////////////////////////////////////////////////////////////////// +// Sequence application +/////////////////////////////////////////////////////////////////////////////// + + initial begin : p_stim + paddr = '0; + dut_req_port_o.data_wdata = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_we = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.kill_req = '0; + seq_end_ack = '0; + flush_o = '0; + + // print some info + $display("%s> current configuration:", PortName); + $display("%s> KillRate %d", PortName, KillRate); + $display("%s> FlushRate %d", PortName, FlushRate); + $display("%s> TlbHitRate %d", PortName, TlbHitRate); + $display("%s> RndSeed %d", PortName, RndSeed); + + `APPL_WAIT_CYC(clk_i,1) + `APPL_WAIT_SIG(clk_i,~rst_ni) + + $display("%s> starting application", PortName); + while(~seq_last_i) begin + `APPL_WAIT_SIG(clk_i,seq_run_i) + unique case(seq_type_i) + RANDOM_SEQ: begin + $display("%s> start random sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i); + genRandReq(); + end + LINEAR_SEQ: begin + $display("%s> start linear sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i); + genSeqRead(); + end + WRAP_SEQ: begin + $display("%s> start wrapping sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i); + genWrapSeq(); + end + IDLE_SEQ: begin + `APPL_WAIT_SIG(clk_i,seq_end_req) + end + BURST_SEQ: begin + $fatal(1, "Burst sequence not implemented for read port agent"); + end + endcase // seq_type_i + seq_end_ack = 1'b1; + $display("%s> stop sequence", PortName); + `APPL_WAIT_CYC(clk_i,1) + seq_end_ack = 1'b0; + end + $display("%s> ending application", PortName); + end + + +/////////////////////////////////////////////////////////////////////////////// +// Response acquisition +/////////////////////////////////////////////////////////////////////////////// + + initial begin : p_acq + bit ok; + progress status; + string failingTests, tmpstr1, tmpstr2; + int n; + logic [63:0] exp_rdata, exp_paddr; + logic [1:0] exp_size; + + status = new(PortName); + failingTests = ""; + seq_done_o = 1'b0; + seq_end_req = 1'b0; + prog_end = 1'b0; + + `ACQ_WAIT_CYC(clk_i,1) + `ACQ_WAIT_SIG(clk_i,~rst_ni) + + /////////////////////////////////////////////// + // loop over tests + n=0; + while(~seq_last_i) begin + `ACQ_WAIT_SIG(clk_i,seq_run_i) + seq_done_o = 1'b0; + + $display("%s> %s", PortName, test_name_i); + status.reset(seq_num_resp_i); + for (int k=0;k %s", PortName, tmpstr1); + $display("%s> %s", PortName, tmpstr2); + end + + if(!ok) begin + failingTests = $psprintf("%s%s> %s\n%s> %s\n", failingTests, PortName, tmpstr1, PortName, tmpstr2); + end + status.addRes(!ok); + status.print(); + end + seq_end_req = 1'b1; + `ACQ_WAIT_SIG(clk_i, seq_end_ack) + seq_end_req = 1'b0; + + `ACQ_WAIT_CYC(clk_i,1) + seq_done_o = 1'b1; + n++; + end + /////////////////////////////////////////////// + + status.printToFile({PortName, "_summary.rep"}, 1); + + if(status.totErrCnt == 0) begin + $display("%s> ----------------------------------------------------------------------", PortName); + $display("%s> PASSED %0d VECTORS", PortName, status.totAcqCnt); + $display("%s> ----------------------------------------------------------------------\n", PortName); + end else begin + $display("%s> ----------------------------------------------------------------------\n", PortName); + $display("%s> FAILED %0d OF %0d VECTORS\n", PortName , status.totErrCnt, status.totAcqCnt); + $display("%s> failing tests:", PortName); + $display("%s", failingTests); + $display("%s> ----------------------------------------------------------------------\n", PortName); + end + prog_end = 1'b1; + end + +endprogram // tb_readport diff --git a/tb/tb_serpent_dcache/hdl/tb_writeport.sv b/tb/tb_serpent_dcache/hdl/tb_writeport.sv new file mode 100644 index 0000000000..205708393c --- /dev/null +++ b/tb/tb_serpent_dcache/hdl/tb_writeport.sv @@ -0,0 +1,281 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: program that emulates a cache write port. the program can generate +// randomized or linear read sequences. +// + +`include "tb.svh" + +import ariane_pkg::*; +import serpent_cache_pkg::*; +import tb_pkg::*; + +program tb_writeport #( + parameter string PortName = "write port 0", + parameter MemWords = 1024*1024,// in 64bit words + parameter logic [63:0] CachedAddrBeg = 0, + parameter logic [63:0] CachedAddrEnd = 0, + parameter RndSeed = 1110, + parameter Verbose = 0 +) ( + input logic clk_i, + input logic rst_ni, + + // to testbench master + ref string test_name_i, + input logic [6:0] req_rate_i, + input seq_t seq_type_i, + input logic seq_run_i, + input logic [31:0] seq_num_vect_i, + input logic seq_last_i, + output logic seq_done_o, + + // interface to DUT + output dcache_req_i_t dut_req_port_o, + input dcache_req_o_t dut_req_port_i + ); + + // leave this + timeunit 1ps; + timeprecision 1ps; + + logic [63:0] paddr; + + assign dut_req_port_o.address_tag = paddr[DCACHE_TAG_WIDTH+DCACHE_INDEX_WIDTH-1:DCACHE_INDEX_WIDTH]; + assign dut_req_port_o.address_index = paddr[DCACHE_INDEX_WIDTH-1:0]; + assign dut_req_port_o.data_we = dut_req_port_o.data_req; + +/////////////////////////////////////////////////////////////////////////////// +// Helper tasks +/////////////////////////////////////////////////////////////////////////////// + + + task automatic applyRandData(); + automatic logic [63:0] val; + automatic logic [7:0] be; + automatic logic [1:0] size; + + void'(randomize(size)); + // align to size, set correct byte enables + be = '0; + unique case(size) + 2'b00: be[paddr[2:0] +: 1] = '1; + 2'b01: be[paddr[2:1]<<1 +: 2] = '1; + 2'b10: be[paddr[2:2]<<2 +: 4] = '1; + 2'b11: be = '1; + default: ; + endcase + paddr[2:0] = '0; + + + void'(randomize(val)); + for(int k=0; k<8; k++) begin + if( be[k] ) begin + dut_req_port_o.data_wdata[k*8 +: 8] = val[k*8 +: 8]; + end + end + + dut_req_port_o.data_be = be; + dut_req_port_o.data_size = size; + endtask : applyRandData + + + task automatic genRandReq(); + automatic logic [63:0] val; + + void'($urandom(RndSeed)); + + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + + repeat(seq_num_vect_i) begin + // randomize request + dut_req_port_o.data_req = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + void'(randomize(val) with {val > 0; val <= 100;}); + if(val < req_rate_i) begin + dut_req_port_o.data_req = 1'b1; + // generate random address + void'(randomize(paddr) with {paddr >= 0; paddr < (MemWords<<3);}); + applyRandData(); + `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) + end + `APPL_WAIT_CYC(clk_i,1) + end + + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + + endtask : genRandReq + + task automatic genSeqWrite(); + automatic logic [63:0] val; + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + val = '0; + repeat(seq_num_vect_i) begin + dut_req_port_o.data_req = 1'b1; + dut_req_port_o.data_size = 2'b11; + dut_req_port_o.data_be = '1; + dut_req_port_o.data_wdata = val; + paddr = val; + // generate linear read + val = (val + 8) % (MemWords<<3); + `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) + `APPL_WAIT_CYC(clk_i,1) + end + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + endtask : genSeqWrite + + task automatic genWrapSeq(); + automatic logic [63:0] val; + void'($urandom(RndSeed)); + + paddr = CachedAddrBeg; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + val = '0; + repeat(seq_num_vect_i) begin + dut_req_port_o.data_req = 1'b1; + applyRandData(); + // generate wrapping read of 1 cacheline + paddr = CachedAddrBeg + val; + val = (val + 8) % (1*(DCACHE_LINE_WIDTH/64)*8); + `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) + `APPL_WAIT_CYC(clk_i,1) + end + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + + endtask : genWrapSeq + + task automatic genSeqBurst(); + automatic logic [63:0] val; + automatic logic [7:0] be; + automatic logic [1:0] size; + automatic int cnt, burst_len; + + void'($urandom(RndSeed)); + + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + cnt = 0; + while(cnt < seq_num_vect_i) begin + // randomize request + dut_req_port_o.data_req = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + void'(randomize(val) with {val > 0; val <= 100;}); + if(val < req_rate_i) begin + dut_req_port_o.data_req = 1'b1; + // generate random address base + void'(randomize(paddr) with {paddr >= 0; paddr < (MemWords<<3);}); + + // do a random burst + void'(randomize(burst_len) with {burst_len >= 0; burst_len < 100;}); + for(int k=0; k=0 val<=8;};); + paddr += 8; + cnt ++; + end + end + `APPL_WAIT_CYC(clk_i,1) + end + + paddr = '0; + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = 'x; + endtask : genSeqBurst + + +/////////////////////////////////////////////////////////////////////////////// +// Sequence application +/////////////////////////////////////////////////////////////////////////////// + + initial begin : p_stim + paddr = '0; + + dut_req_port_o.data_req = '0; + dut_req_port_o.data_size = '0; + dut_req_port_o.data_be = '0; + dut_req_port_o.data_wdata = '0; + dut_req_port_o.tag_valid = '0; + dut_req_port_o.kill_req = '0; + + seq_done_o = 1'b0; + + // print some info + $display("%s> current configuration:", PortName); + $display("%s> RndSeed %d", PortName, RndSeed); + + `APPL_WAIT_CYC(clk_i,1) + `APPL_WAIT_SIG(clk_i,~rst_ni) + + $display("%s> starting application", PortName); + while(~seq_last_i) begin + `APPL_WAIT_SIG(clk_i,seq_run_i) + seq_done_o = 1'b0; + unique case(seq_type_i) + RANDOM_SEQ: begin + $display("%s> start random sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); + genRandReq(); + end + LINEAR_SEQ: begin + $display("%s> start linear sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); + genSeqWrite(); + end + WRAP_SEQ: begin + $display("%s> start wrapping sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); + genWrapSeq(); + end + IDLE_SEQ: ;// do nothing + BURST_SEQ: begin + $display("%s> start burst sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); + genSeqBurst(); + end + endcase // seq_type_i + seq_done_o = 1'b1; + $display("%s> stop sequence", PortName); + `APPL_WAIT_CYC(clk_i,1) + end + $display("%s> ending application", PortName); + end + +endprogram // tb_readport diff --git a/tb/tb_serpent_dcache/tb.list b/tb/tb_serpent_dcache/tb.list new file mode 100644 index 0000000000..e08cfbd4b3 --- /dev/null +++ b/tb/tb_serpent_dcache/tb.list @@ -0,0 +1,21 @@ +../../include/riscv_pkg.sv +../../src/debug/dm_pkg.sv +../../include/ariane_pkg.sv +../../include/serpent_cache_pkg.sv +../../src/fpga-support/rtl/SyncSpRamBeNx64.sv +../../src/cache_subsystem/serpent_dcache_ctrl.sv +../../src/cache_subsystem/serpent_dcache_mem.sv +../../src/cache_subsystem/serpent_dcache_missunit.sv +../../src/cache_subsystem/serpent_dcache_wbuffer.sv +../../src/cache_subsystem/serpent_dcache.sv +../../src/common_cells/src/lfsr_8bit.sv +../../src/common_cells/src/fifo_v2.sv +../../src/common_cells/src/fifo_v3.sv +../../src/common_cells/src/lzc.sv +../../src/common_cells/src/rrarbiter.sv +../../src/util/sram.sv +hdl/tb_pkg.sv +hdl/tb_mem.sv +hdl/tb_readport.sv +hdl/tb_writeport.sv +hdl/tb.sv diff --git a/tb/tb_serpent_dcache/wave.do b/tb/tb_serpent_dcache/wave.do new file mode 100644 index 0000000000..cdf0b0634f --- /dev/null +++ b/tb/tb_serpent_dcache/wave.do @@ -0,0 +1,474 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb/KILL_RATE +add wave -noupdate /tb/MEM_BYTES +add wave -noupdate /tb/MEM_RAND_HIT_RATE +add wave -noupdate /tb/MEM_RAND_INV_RATE +add wave -noupdate /tb/MEM_WORDS +add wave -noupdate /tb/NC_ADDR_BEGIN +add wave -noupdate /tb/amo_ack_o +add wave -noupdate /tb/amo_rand_en +add wave -noupdate /tb/amo_req_i +add wave -noupdate /tb/clk_i +add wave -noupdate /tb/enable_i +add wave -noupdate /tb/end_of_sim +add wave -noupdate /tb/flush_ack_o +add wave -noupdate /tb/flush_i +add wave -noupdate /tb/inv_rand_en +add wave -noupdate /tb/mem_array +add wave -noupdate /tb/mem_data_ack_i +add wave -noupdate /tb/mem_data_o +add wave -noupdate /tb/mem_data_req_o +add wave -noupdate /tb/mem_rand_en +add wave -noupdate -expand /tb/mem_rtrn_i +add wave -noupdate /tb/mem_rtrn_vld_i +add wave -noupdate /tb/miss_o +add wave -noupdate /tb/req_ports_i +add wave -noupdate /tb/req_ports_o +add wave -noupdate /tb/rst_ni +add wave -noupdate /tb/seq_done +add wave -noupdate /tb/seq_last +add wave -noupdate /tb/seq_num_resp +add wave -noupdate /tb/seq_run +add wave -noupdate /tb/seq_type +add wave -noupdate /tb/test_name +add wave -noupdate /tb/wbuffer_empty_o +add wave -noupdate -divider Programs +add wave -noupdate -group Writeport /tb/i_tb_writeport/clk_i +add wave -noupdate -group Writeport /tb/i_tb_writeport/rst_ni +add wave -noupdate -group Writeport /tb/i_tb_writeport/req_rate_i +add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_type_i +add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_run_i +add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_num_vect_i +add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_last_i +add wave -noupdate -group Writeport /tb/i_tb_writeport/dut_req_port_i +add wave -noupdate -group Writeport /tb/i_tb_writeport/MEM_WORDS +add wave -noupdate -group Writeport /tb/i_tb_writeport/RND_SEED +add wave -noupdate -group Writeport /tb/i_tb_writeport/VERBOSE +add wave -noupdate -group Writeport /tb/i_tb_writeport/test_name_i +add wave -noupdate -group Writeport /tb/i_tb_writeport/paddr +add wave -noupdate -group Writeport /tb/i_tb_writeport/seq_done_o +add wave -noupdate -group Writeport /tb/i_tb_writeport/dut_req_port_o +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/clk_i +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/rst_ni +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_type_i +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_run_i +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_num_resp_i +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_last_i +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_done_o +add wave -noupdate -group {Readport 0} -expand /tb/i_tb_readport0/dut_req_port_o +add wave -noupdate -group {Readport 0} -expand /tb/i_tb_readport0/dut_req_port_i +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/paddr +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_end_req +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/seq_end_ack +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/tag_q +add wave -noupdate -group {Readport 0} /tb/i_tb_readport0/tag_vld_q +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/clk_i +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/rst_ni +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_type_i +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_run_i +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_num_resp_i +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_last_i +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_done_o +add wave -noupdate -group {Readport 1} -expand /tb/i_tb_readport1/dut_req_port_o +add wave -noupdate -group {Readport 1} -expand /tb/i_tb_readport1/dut_req_port_i +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/paddr +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_end_req +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/seq_end_ack +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/tag_q +add wave -noupdate -group {Readport 1} /tb/i_tb_readport1/tag_vld_q +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/clk_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/rst_ni +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rand_en_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/inv_rand_en_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/amo_rand_en_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_req_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/seq_last_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/check_en_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_en_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_be_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/commit_paddr_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_en_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_be_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_data_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_paddr_i +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_RAND_HIT_RATE +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_RAND_INV_RATE +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/MEM_WORDS +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/NC_ADDR_BEGIN +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/NC_ADDR_GE_LT +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_ready_q +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_inv_q +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/rand_addr_q +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_data +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_pop +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_push +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_full +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/outfifo_empty +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_data +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_pop +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_push +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_full +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/infifo_empty +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/initialized_q +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/write_en +add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_q +add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_shadow_q +add wave -noupdate -group i_tb_mem -color Magenta /tb/i_tb_mem/mem_array_dirty_q +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rtrn_vld_o +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_rtrn_o +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_data_ack_o +add wave -noupdate -group i_tb_mem /tb/i_tb_mem/mem_array_o +add wave -noupdate -divider Modules +add wave -noupdate -group i_dut /tb/i_dut/clk_i +add wave -noupdate -group i_dut /tb/i_dut/rst_ni +add wave -noupdate -group i_dut /tb/i_dut/enable_i +add wave -noupdate -group i_dut /tb/i_dut/flush_i +add wave -noupdate -group i_dut /tb/i_dut/amo_req_i +add wave -noupdate -group i_dut /tb/i_dut/req_ports_i +add wave -noupdate -group i_dut /tb/i_dut/mem_rtrn_vld_i +add wave -noupdate -group i_dut /tb/i_dut/mem_rtrn_i +add wave -noupdate -group i_dut /tb/i_dut/mem_data_ack_i +add wave -noupdate -group i_dut /tb/i_dut/NC_ADDR_BEGIN +add wave -noupdate -group i_dut /tb/i_dut/NC_ADDR_GE_LT +add wave -noupdate -group i_dut /tb/i_dut/NUM_PORTS +add wave -noupdate -group i_dut /tb/i_dut/cache_en +add wave -noupdate -group i_dut /tb/i_dut/flush_en +add wave -noupdate -group i_dut /tb/i_dut/wr_cl_vld +add wave -noupdate -group i_dut /tb/i_dut/wr_cl_tag +add wave -noupdate -group i_dut /tb/i_dut/wr_cl_idx +add wave -noupdate -group i_dut /tb/i_dut/wr_cl_off +add wave -noupdate -group i_dut /tb/i_dut/wr_cl_data +add wave -noupdate -group i_dut /tb/i_dut/wr_cl_data_be +add wave -noupdate -group i_dut /tb/i_dut/wr_vld_bits +add wave -noupdate -group i_dut /tb/i_dut/wr_req +add wave -noupdate -group i_dut /tb/i_dut/wr_ack +add wave -noupdate -group i_dut /tb/i_dut/wr_idx +add wave -noupdate -group i_dut /tb/i_dut/wr_off +add wave -noupdate -group i_dut /tb/i_dut/wr_data +add wave -noupdate -group i_dut /tb/i_dut/wr_data_be +add wave -noupdate -group i_dut /tb/i_dut/miss_req +add wave -noupdate -group i_dut /tb/i_dut/miss_ack +add wave -noupdate -group i_dut /tb/i_dut/miss_nc +add wave -noupdate -group i_dut /tb/i_dut/miss_we +add wave -noupdate -group i_dut /tb/i_dut/miss_wdata +add wave -noupdate -group i_dut /tb/i_dut/miss_paddr +add wave -noupdate -group i_dut /tb/i_dut/miss_vld_bits +add wave -noupdate -group i_dut /tb/i_dut/miss_size +add wave -noupdate -group i_dut /tb/i_dut/miss_wr_id +add wave -noupdate -group i_dut /tb/i_dut/miss_rtrn_vld +add wave -noupdate -group i_dut /tb/i_dut/miss_rtrn_id +add wave -noupdate -group i_dut /tb/i_dut/rd_req +add wave -noupdate -group i_dut /tb/i_dut/rd_ack +add wave -noupdate -group i_dut /tb/i_dut/rd_tag +add wave -noupdate -group i_dut /tb/i_dut/rd_idx +add wave -noupdate -group i_dut /tb/i_dut/rd_off +add wave -noupdate -group i_dut /tb/i_dut/rd_data +add wave -noupdate -group i_dut /tb/i_dut/rd_vld_bits +add wave -noupdate -group i_dut /tb/i_dut/rd_hit_oh +add wave -noupdate -group i_dut /tb/i_dut/wbuffer_data +add wave -noupdate -group i_dut /tb/i_dut/flush_ack_o +add wave -noupdate -group i_dut /tb/i_dut/miss_o +add wave -noupdate -group i_dut /tb/i_dut/wbuffer_empty_o +add wave -noupdate -group i_dut /tb/i_dut/amo_ack_o +add wave -noupdate -group i_dut /tb/i_dut/req_ports_o +add wave -noupdate -group i_dut /tb/i_dut/mem_data_req_o +add wave -noupdate -group i_dut /tb/i_dut/mem_data_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/clk_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rst_ni +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/cache_en_i +add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_serpent_dcache_wbuffer/req_port_i +add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_serpent_dcache_wbuffer/req_port_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_ack_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_rtrn_vld_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_rtrn_id_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_ack_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_data_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_vld_bits_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_hit_oh_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_ack_i +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/empty_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_paddr_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_req_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_we_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_wdata_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_vld_bits_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_nc_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_size_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/miss_wr_id_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_tag_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_idx_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_off_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_req_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_req_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_idx_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_off_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_data_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_data_be_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wbuffer_data_o +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/NC_ADDR_BEGIN +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/NC_ADDR_GE_LT +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_stat_d +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_stat_q +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wbuffer_q +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wbuffer_d +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/valid +add wave -noupdate -group i_wbuffer -color Magenta /tb/i_dut/i_serpent_dcache_wbuffer/debug_paddr +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/dirty +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tocheck +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wbuffer_hit_oh +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/inval_hit +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/bdirty +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/next_ptr +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/dirty_ptr +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/hit_ptr +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_ptr +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/check_ptr_d +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/check_ptr_q +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rtrn_ptr +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_cnt_q +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_cnt_d +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_id_q +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_id_d +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rtrn_id +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/bdirty_off +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/tx_be +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/wr_paddr +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rd_paddr +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/check_en_d +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/check_en_q +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/full +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/dirty_rd_en +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rdy +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/rtrn_empty +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/evict +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/nc_pending_d +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/nc_pending_q +add wave -noupdate -group i_wbuffer /tb/i_dut/i_serpent_dcache_wbuffer/addr_is_nc +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/clk_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/rst_ni +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/enable_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wbuffer_empty_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_req_i +add wave -noupdate -group i_missunit -expand /tb/i_dut/i_serpent_dcache_missunit/miss_req_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_nc_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_we_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_wdata_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_paddr_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_vld_bits_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_size_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_wr_id_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_rtrn_vld_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_rtrn_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_data_ack_i +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_ack_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/cache_en_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_en_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_ack_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_ack_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_replay_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_rtrn_vld_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_rtrn_id_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_vld_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_nc_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_we_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_tag_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_idx_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_off_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_data_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_cl_data_be_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/wr_vld_bits_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_data_req_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mem_data_o +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/NUM_PORTS +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/state_d +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/state_q +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_d +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_q +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/repl_way +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/inv_way +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/rnd_way +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_vld_d +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_vld_q +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mshr_allocate +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/update_lfsr +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/all_ways_valid +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/enable_d +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/enable_q +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_ack_d +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_ack_q +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_sel +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/flush_done +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/mask_reads +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_is_write +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_data +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_port_idx +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/cnt_d +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/cnt_q +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/miss_req +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/inv_vld +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/cl_write_en +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/load_ack +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/store_ack +add wave -noupdate -group i_missunit /tb/i_dut/i_serpent_dcache_missunit/amo_ack +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/clk_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rst_ni +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_tag_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_idx_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_off_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_req_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_vld_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_tag_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_idx_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_off_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_data_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_cl_data_be_i +add wave -noupdate -expand -group i_mem -expand /tb/i_dut/i_serpent_dcache_mem/wr_vld_bits_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_req_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_idx_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_off_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_data_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_data_be_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_data_i +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_ack_o +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_vld_bits_o +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_hit_oh_o +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rd_data_o +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wr_ack_o +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/NUM_PORTS +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_req +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_we +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_be +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_idx +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_idx_d +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_idx_q +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_off_d +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_off_q +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_wdata +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/bank_rdata +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rdata_cl +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_req +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_we +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_wdata +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/tag_rdata +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_addr +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_sel_d +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_sel_q +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_hit_oh +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_be +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_rdata +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/rdata +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_cmp_addr +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_bvalid +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/wbuffer_data +add wave -noupdate -expand -group i_mem /tb/i_dut/i_serpent_dcache_mem/vld_tag_rdata +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/clk_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rst_ni} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/flush_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/cache_en_i} +add wave -noupdate -group i_ctrl0 -expand {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/req_port_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_ack_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_replay_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_rtrn_vld_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_ack_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_data_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_vld_bits_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_hit_oh_i} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/req_port_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_req_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_we_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_wdata_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_vld_bits_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_paddr_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_nc_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_size_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/miss_wr_id_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_tag_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_idx_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_off_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_req_o} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/NC_ADDR_BEGIN} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/NC_ADDR_GE_LT} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/state_d} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/state_q} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_tag_d} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_tag_q} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_idx_d} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_idx_q} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_off_d} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/address_off_q} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/vld_data_d} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/vld_data_q} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/save_tag} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_req_d} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/rd_req_q} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/data_size_d} +add wave -noupdate -group i_ctrl0 {/tb/i_dut/genblk1[0]/i_serpent_dcache_ctrl/data_size_q} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/clk_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rst_ni} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/flush_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/cache_en_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/req_port_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_ack_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_replay_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_rtrn_vld_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_ack_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_data_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_vld_bits_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_hit_oh_i} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/req_port_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_req_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_we_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_wdata_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_vld_bits_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_paddr_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_nc_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_size_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/miss_wr_id_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_tag_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_idx_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_off_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_req_o} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/NC_ADDR_BEGIN} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/NC_ADDR_GE_LT} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/state_d} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/state_q} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_tag_d} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_tag_q} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_idx_d} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_idx_q} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_off_d} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/address_off_q} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/vld_data_d} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/vld_data_q} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/save_tag} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_req_d} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/rd_req_q} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/data_size_d} +add wave -noupdate -group i_ctrl1 {/tb/i_dut/genblk1[1]/i_serpent_dcache_ctrl/data_size_q} +TreeUpdate [SetDefaultTree] +quietly WaveActivateNextPane +add wave -noupdate {/tb/i_tb_mem/mem_array_q[6741]} +add wave -noupdate {/tb/i_tb_mem/mem_array_shadow_q[6741]} +add wave -noupdate {/tb/i_tb_mem/mem_array_dirty_q[6741]} +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {31432807547 ps} 0} {{Cursor 2} {29040000 ps} 0} {{Cursor 3} {1027790000 ps} 0} +quietly wave cursor active 2 +configure wave -namecolwidth 375 +configure wave -valuecolwidth 224 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {103267500 ps} diff --git a/tb/tb_serpent_icache/.gitignore b/tb/tb_serpent_icache/.gitignore new file mode 100644 index 0000000000..f8cb654656 --- /dev/null +++ b/tb/tb_serpent_icache/.gitignore @@ -0,0 +1,7 @@ +work +*.rep +transcript +*.ini +*.wlf +*.log + diff --git a/tb/tb_serpent_icache/Makefile b/tb/tb_serpent_icache/Makefile new file mode 100755 index 0000000000..7a1c9af735 --- /dev/null +++ b/tb/tb_serpent_icache/Makefile @@ -0,0 +1,42 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# Copyright and related rights are licensed under the Solderpad Hardware +# License, Version 0.51 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +# or agreed to in writing, software, hardware and materials distributed under +# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. +# +# Author: Michael Schaffner , ETH Zurich +# Date: 15.08.2018 +# Description: Makefile for the icache testbench. + + +library ?= work +toplevel ?= tb +src-list := tb.list +src := $(shell xargs printf '\n%s' < $(src-list) | cut -b 1-) +compile_flag += +cover+/dut -incr -64 -nologo +sim_opts += -64 -coverage -classdebug -voptargs="+acc" +questa_version ?= ${QUESTASIM_VERSION} +incdir += ../common/ + +build: clean + vlib${questa_version} $(library) + vlog${questa_version} -work $(library) -pedanticerrors $(src) $(compile_flag) +incdir+$(incdir) + touch $(library)/.build + +# this starts modelsim with gui +sim: build + vsim${questa_version} -lib $(library) $(toplevel) -do "do wave.do" $(sim_opts) + +# batch mode without gui +simc: build + vsim${questa_version} -lib $(library) $(toplevel) -c -do "run -all; exit" $(sim_opts) + +clean: + rm -rf $(library) + +.PHONY: clean simc sim build + diff --git a/tb/tb_serpent_icache/hdl/mem_emul.sv b/tb/tb_serpent_icache/hdl/mem_emul.sv new file mode 100644 index 0000000000..cf42797142 --- /dev/null +++ b/tb/tb_serpent_icache/hdl/mem_emul.sv @@ -0,0 +1,263 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: simple emulation layer for the memory subsystem. +// + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module mem_emul #( + parameter MemRandHitRate = 10, //in percent + parameter MemRandInvRate = 5, //in percent + parameter MemWords = 1024*1024,// in 32bit words + parameter logic [63:0] CachedAddrBeg = MemWords/2 +) ( + input logic clk_i, + input logic rst_ni, + // some tb signals to enable randomization, etc + input logic mem_rand_en_i, + input logic io_rand_en_i, + input logic inv_rand_en_i, + input logic [63:0] tlb_offset_i, + // stimuli interface to get expected responses + input logic [63:0] stim_vaddr_i, + input logic stim_push_i, + input logic stim_flush_i, + output logic stim_full_o, + output logic [63:0] exp_data_o, + output logic [63:0] exp_vaddr_o, + output logic exp_empty_o, + input logic exp_pop_i, + // icache interface + output logic mem_rtrn_vld_o, + output icache_rtrn_t mem_rtrn_o, + input logic mem_data_req_i, + output logic mem_data_ack_o, + input icache_req_t mem_data_i +); + + logic mem_ready_q, mem_inv_q; + logic [63:0] rand_addr_q; + + icache_req_t outfifo_data; + logic outfifo_pop, outfifo_push, outfifo_full, outfifo_empty; + icache_rtrn_t infifo_data; + logic infifo_pop, infifo_push, infifo_full, infifo_empty; + + logic [63:0] stim_addr; + logic exp_empty; + + logic [31:0] mem_array [MemWords-1:0]; + logic [31:0] mem_array_shadow [MemWords-1:0]; + logic initialized_q; + + logic [31:0] inval_addr_queue[$]; + logic [31:0] inval_data_queue[$]; + + // sequential process holding the state of the memory readout process + always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlb_rand + automatic bit ok = 0; + automatic int rnd = 0; + automatic logic [31:0] val; + automatic logic [63:0] lval; + + if(~rst_ni) begin + mem_ready_q <= '0; + mem_inv_q <= '0; + rand_addr_q <= '0; + initialized_q <= '0; + end else begin + + // fill the memory once with random data + if (~initialized_q) begin + for (int k=0; k 0; rnd <= 100;}; + if(rnd < MemRandHitRate) begin + mem_ready_q <= '1; + end else + mem_ready_q <= '0; + end else begin + mem_ready_q <= '1; + end + + // generate random invalidations + + if (inv_rand_en_i) begin + if (infifo_push) begin + // update coherent memory view for expected responses + while(inval_addr_queue.size()>0)begin + lval = inval_addr_queue.pop_back(); + val = inval_data_queue.pop_back(); + mem_array_shadow[lval] <= val; + end + end + + ok = randomize(rnd) with {rnd > 0; rnd <= 100;}; + if(rnd < MemRandInvRate) begin + mem_inv_q = '1; + ok = randomize(lval) with {lval>=0; lval>2]; + end + infifo_data.data[0 +:32] = mem_array[outfifo_data.paddr>>2]; + end else begin + infifo_data.nc = outfifo_data.nc; + // replicate words (this is done in openpiton, too) + for (int k=0; k>2) + k]; + end + end + end + end + + fifo_v2 #( + .dtype(icache_req_t), + .DEPTH(2) + ) i_outfifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( outfifo_full ), + .empty_o ( outfifo_empty ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( mem_data_i ), + .push_i ( outfifo_push ), + .data_o ( outfifo_data ), + .pop_i ( outfifo_pop ) + ); + + assign outfifo_push = mem_data_req_i & (~outfifo_full); + assign mem_data_ack_o = outfifo_push; + + fifo_v2 #( + .dtype(icache_rtrn_t), + .DEPTH(2) + ) i_infifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( 1'b0 ), + .testmode_i ( 1'b0 ), + .full_o ( infifo_full ), + .empty_o ( infifo_empty ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( infifo_data ), + .push_i ( infifo_push ), + .data_o ( mem_rtrn_o ), + .pop_i ( infifo_pop ) + ); + + assign infifo_pop = ~infifo_empty; + assign mem_rtrn_vld_o = infifo_pop; + + // this is to readout the expected responses + fifo_v2 #( + .DATA_WIDTH(64), + .DEPTH(3) + ) i_stimuli_fifo ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( stim_flush_i ), + .testmode_i ( 1'b0 ), + .full_o ( stim_full_o ), + .empty_o ( exp_empty ), + .alm_full_o ( ), + .alm_empty_o ( ), + .data_i ( stim_vaddr_i ), + .push_i ( stim_push_i ), + .data_o ( stim_addr ), + .pop_i ( exp_pop_i ) + ); + + assign exp_empty_o = exp_empty | stim_flush_i; + // use last seen memory state in case random invalidations are present + assign exp_data_o = (inv_rand_en_i) ? mem_array_shadow[(stim_addr>>2) + (tlb_offset_i>>2)] : + mem_array [(stim_addr>>2) + (tlb_offset_i>>2)]; + assign exp_vaddr_o = stim_addr; + + align0: assert property ( + @(posedge clk_i) disable iff (~rst_ni) ~exp_empty |-> stim_addr[1:0] == 0) + else $fatal(1,"stim_addr is not 32bit word aligned"); + + align1: assert property ( + @(posedge clk_i) disable iff (~rst_ni) ~outfifo_empty |-> outfifo_data.paddr[1:0] == 0) + else $fatal(1,"paddr is not 32bit word aligned"); + + +endmodule // mem_emul diff --git a/tb/tb_serpent_icache/hdl/tb.sv b/tb/tb_serpent_icache/hdl/tb.sv new file mode 100644 index 0000000000..dbf50148b8 --- /dev/null +++ b/tb/tb_serpent_icache/hdl/tb.sv @@ -0,0 +1,438 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: testbench for piton_icache. includes the following tests: +// +// 0) random accesses with disabled cache +// 1) random accesses with enabled cache to cacheable and noncacheable memory +// 2) linear, wrapping sweep with enabled cache +// 3) 1) with random stalls on the memory side and TLB side +// 4) nr 3) with random invalidations +// +// note that we use a simplified address translation scheme to emulate the TLB. +// (random offsets). + +import ariane_pkg::*; +import serpent_cache_pkg::*; +import tb_pkg::*; + +`include "tb.svh" + +module tb; + + // leave this + timeunit 1ps; + timeprecision 1ps; + + // number of 32bit words + parameter MemBytes = 2**ICACHE_INDEX_WIDTH * 4 * 32; + parameter MemWords = MemBytes>>2; + parameter logic [63:0] CachedAddrBeg = MemBytes/4; + parameter logic [63:0] CachedAddrEnd = 64'hFFFF_FFFF_FFFF_FFFF; + + // rates are in percent + parameter TlbRandHitRate = 50; + parameter MemRandHitRate = 50; + parameter MemRandInvRate = 10; + + parameter SeqRate = 90; + parameter S1KillRate = 5; + parameter S2KillRate = 5; + parameter FlushRate = 1; + + parameter logic [63:0] TlbOffset = 4*1024;//use multiples of 4kB pages! + + +/////////////////////////////////////////////////////////////////////////////// +// MUT signal declarations +/////////////////////////////////////////////////////////////////////////////// + + logic clk_i; + logic rst_ni; + logic flush_i; + logic en_i; + logic miss_o; + icache_areq_i_t areq_i; + icache_areq_o_t areq_o; + icache_dreq_i_t dreq_i; + icache_dreq_o_t dreq_o; + logic mem_rtrn_vld_i; + icache_rtrn_t mem_rtrn_i; + logic mem_data_req_o; + logic mem_data_ack_i; + icache_req_t mem_data_o; + + +/////////////////////////////////////////////////////////////////////////////// +// TB signal declarations +/////////////////////////////////////////////////////////////////////////////// + + logic stim_start, stim_end, end_of_sim, acq_done; + logic [63:0] num_vectors; + string test_name; + + logic mem_rand_en; + logic inv_rand_en; + logic io_rand_en; + logic tlb_rand_en; + logic exception_en; + + logic [63:0] stim_vaddr; + logic [63:0] exp_data; + logic [63:0] exp_vaddr; + logic stim_push, stim_flush, stim_full; + logic exp_empty, exp_pop; + + logic dut_out_vld, dut_in_rdy; + +/////////////////////////////////////////////////////////////////////////////// +// Clock Process +/////////////////////////////////////////////////////////////////////////////// + + always @* + begin + do begin + clk_i = 1;#(CLK_HI); + clk_i = 0;#(CLK_LO); + end while (end_of_sim == 1'b0); + repeat (100) begin + // generate a few extra cycle to allow response acquisition to complete + clk_i = 1;#(CLK_HI); + clk_i = 0;#(CLK_LO); + end + end + +/////////////////////////////////////////////////////////////////////////////// +// Helper tasks +/////////////////////////////////////////////////////////////////////////////// + + // prepare tasks... + + task automatic genRandReq(); + automatic bit ok; + automatic logic [63:0] val; + dreq_i.req = 0; + dreq_i.kill_s1 = 0; + dreq_i.kill_s2 = 0; + num_vectors = 100000; + stim_end = 0; + + stim_start = 1; + `APPL_WAIT_CYC(clk_i,10) + stim_start = 0; + + // start with clean cache + flush_i = 1; + `APPL_WAIT_CYC(clk_i,1) + flush_i = 0; + + while(~acq_done) begin + // randomize request + dreq_i.req = 0; + ok = randomize(val) with {val > 0; val <= 100;}; + if (val < SeqRate) begin + dreq_i.req = 1; + // generate random address + ok = randomize(val) with {val >= 0; val < (MemBytes-TlbOffset)>>2;}; + dreq_i.vaddr = val<<2;// align to 4Byte + // generate random control events + ok = randomize(val) with {val > 0; val <= 100;}; + dreq_i.kill_s1 = (val < S1KillRate); + ok = randomize(val) with {val > 0; val <= 100;}; + dreq_i.kill_s2 = (val < S2KillRate); + ok = randomize(val) with {val > 0; val <= 100;}; + flush_i = (val < FlushRate); + `APPL_WAIT_SIG(clk_i, dut_in_rdy) + end else begin + `APPL_WAIT_CYC(clk_i,1) + end + end + stim_end = 1; + endtask : genRandReq + + + task automatic genSeqRead(); + automatic bit ok; + automatic logic [63:0] val; + automatic logic [63:0] addr; + dreq_i.req = 0; + dreq_i.kill_s1 = 0; + dreq_i.kill_s2 = 0; + num_vectors = 32*4*1024; + addr = 0; + stim_end = 0; + + stim_start = 1; + `APPL_WAIT_CYC(clk_i,10) + stim_start = 0; + + // start with clean cache + flush_i = 1; + `APPL_WAIT_CYC(clk_i,1) + flush_i = 0; + + while(~acq_done) begin + dreq_i.req = 1; + dreq_i.vaddr = addr; + // generate linear read + addr = (addr + 4) % (MemBytes - TlbOffset); + `APPL_WAIT_SIG(clk_i, dut_in_rdy) + end + stim_end = 1; + endtask : genSeqRead + + +/////////////////////////////////////////////////////////////////////////////// +// TLB and memory emulation +/////////////////////////////////////////////////////////////////////////////// + + tlb_emul #( + .TlbRandHitRate(TlbRandHitRate) + ) i_tlb_emul ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .tlb_rand_en_i ( tlb_rand_en ), + .exception_en_i ( exception_en ), + .tlb_offset_i ( TlbOffset ), + // icache interface + .req_i ( areq_o ), + .req_o ( areq_i ) + ); + + mem_emul #( + .MemRandHitRate ( MemRandHitRate ), + .MemRandInvRate ( MemRandInvRate ), + .MemWords ( MemWords ), + .CachedAddrBeg ( CachedAddrBeg ) + ) i_mem_emul ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .mem_rand_en_i ( mem_rand_en ), + .io_rand_en_i ( io_rand_en ), + .inv_rand_en_i ( inv_rand_en ), + .tlb_offset_i ( TlbOffset ), + .stim_vaddr_i ( stim_vaddr ), + .stim_push_i ( stim_push ), + .stim_flush_i ( stim_flush ), + .stim_full_o ( stim_full ), + .exp_data_o ( exp_data ), + .exp_vaddr_o ( exp_vaddr ), + .exp_empty_o ( exp_empty ), + .exp_pop_i ( exp_pop ), + .mem_data_req_i ( mem_data_req_o ), + .mem_data_ack_o ( mem_data_ack_i ), + .mem_data_i ( mem_data_o ), + .mem_rtrn_vld_o ( mem_rtrn_vld_i ), + .mem_rtrn_o ( mem_rtrn_i ) + ); + +/////////////////////////////////////////////////////////////////////////////// +// MUT +/////////////////////////////////////////////////////////////////////////////// + + serpent_icache #( + .CachedAddrBeg(CachedAddrBeg), + .CachedAddrEnd(CachedAddrEnd) + ) dut ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .flush_i ( flush_i ), + .en_i ( en_i ), + .miss_o ( miss_o ), + .areq_i ( areq_i ), + .areq_o ( areq_o ), + .dreq_i ( dreq_i ), + .dreq_o ( dreq_o ), + .mem_rtrn_vld_i ( mem_rtrn_vld_i ), + .mem_rtrn_i ( mem_rtrn_i ), + .mem_data_req_o ( mem_data_req_o ), + .mem_data_ack_i ( mem_data_ack_i ), + .mem_data_o ( mem_data_o ) + ); + + // connect interface to expected response channel of memory emulation + assign stim_vaddr = dreq_i.vaddr; + assign stim_push = dreq_i.req & dreq_o.ready & (~dreq_i.kill_s1) & (~flush_i); + assign stim_flush = 0; + assign exp_pop = (dreq_o.valid | dreq_i.kill_s2) & (~exp_empty); + +/////////////////////////////////////////////////////////////////////////////// +// stimuli application process +/////////////////////////////////////////////////////////////////////////////// + + assign dut_in_rdy = dreq_o.ready; + + initial // process runs just once + begin : p_stim + end_of_sim = 0; + num_vectors = 0; + stim_start = 0; + stim_end = 0; + + rst_ni = 0; + + mem_rand_en = 0; + tlb_rand_en = 0; + inv_rand_en = 0; + exception_en = 0; + io_rand_en = 0; + + dreq_i.req = 0; + dreq_i.kill_s1 = 0; + dreq_i.kill_s2 = 0; + dreq_i.vaddr = 0; + flush_i = 0; + en_i = 0; + + // print some info + $display("TB> current configuration:"); + $display("TB> MemWords %d", MemWords); + $display("TB> CachedAddrBeg %16X", CachedAddrBeg); + $display("TB> TlbRandHitRate %d", TlbRandHitRate); + $display("TB> MemRandHitRate %d", MemRandHitRate); + $display("TB> MemRandInvRate %d", MemRandInvRate); + $display("TB> S1KillRate %d", S1KillRate); + $display("TB> S2KillRate %d", S2KillRate); + $display("TB> FlushRate %d", FlushRate); + + `APPL_WAIT_CYC(clk_i,100); + $display("TB> choose TLB offset %16X", TlbOffset); + + // reset cycles + `APPL_WAIT_CYC(clk_i,100); + rst_ni = 1'b1; + `APPL_WAIT_CYC(clk_i,100); + + $display("TB> stimuli application started"); + // apply each test until NUM_ACCESSES memory + // requests have successfully completed + /////////////////////////////////////////////// + // TEST 0 + en_i = 0; + genRandReq(); + `APPL_WAIT_CYC(clk_i,40); + /////////////////////////////////////////////// + // TEST 1 + test_name = "TEST1, enabled cache"; + en_i = 1; + genRandReq(); + `APPL_WAIT_CYC(clk_i,40); + /////////////////////////////////////////////// + // TEST 2 + test_name = "TEST2, enabled cache, sequential reads"; + en_i = 1; + genSeqRead(); + `APPL_WAIT_CYC(clk_i,40); + /////////////////////////////////////////////// + // TEST 3 + test_name = "TEST3, enabled cache, random stalls in mem and TLB side"; + en_i = 1; + mem_rand_en = 1; + tlb_rand_en = 1; + genRandReq(); + `APPL_WAIT_CYC(clk_i,40); + /////////////////////////////////////////////// + // TEST 4 + test_name = "TEST4, +random invalidations"; + en_i = 1; + mem_rand_en = 1; + tlb_rand_en = 1; + inv_rand_en = 1; + genRandReq(); + `APPL_WAIT_CYC(clk_i,40); + /////////////////////////////////////////////// + end_of_sim = 1; + $display("TB> stimuli application ended"); + end + +/////////////////////////////////////////////////////////////////////////////// +// stimuli acquisition process +/////////////////////////////////////////////////////////////////////////////// + + assign dut_out_vld = dreq_o.valid; + + initial // process runs just once + begin : p_acq + + bit ok; + progress status; + string failingTests, tmpstr; + int n; + + status = new(); + failingTests = ""; + acq_done = 0; + + /////////////////////////////////////////////// + // loop over tests + n=0; + while (~end_of_sim) begin + // wait for stimuli application + `ACQ_WAIT_SIG(clk_i, stim_start); + $display("TB: ----------------------------------------------------------------------\n"); + $display("TB> %s", test_name); + + status.reset(num_vectors); + acq_done = 0; + for (int k=0;k %s", tmpstr); + end + status.addRes(!ok); + status.print(); + end + acq_done = 1; + n++; + // wait for stimuli application end + `ACQ_WAIT_SIG(clk_i, stim_end); + `ACQ_WAIT_CYC(clk_i,100); + end + /////////////////////////////////////////////// + + status.printToFile("summary.rep", 1); + + if(status.totErrCnt == 0) begin + $display("TB: ----------------------------------------------------------------------\n"); + $display("TB: PASSED %0d VECTORS", status.totAcqCnt); + $display("TB: ----------------------------------------------------------------------\n"); + end else begin + $display("TB: ----------------------------------------------------------------------\n"); + $display("TB: FAILED %0d OF %0d VECTORS\n", status.totErrCnt, status.totAcqCnt); + $display("TB: failing tests:"); + $display("%s", failingTests); + $display("TB: ----------------------------------------------------------------------\n"); + end + end + +endmodule + + + + + + + + + + + + diff --git a/tb/tb_serpent_icache/hdl/tb_pkg.sv b/tb/tb_serpent_icache/hdl/tb_pkg.sv new file mode 100644 index 0000000000..ae461862ab --- /dev/null +++ b/tb/tb_serpent_icache/hdl/tb_pkg.sv @@ -0,0 +1,139 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: testbench package with some helper functions. + + +package tb_pkg; + + // // for abs(double) function + // import mti_cstdlib::*; + + // for timestamps + import "DPI-C" \time = function int _time (inout int tloc[4]); + import "DPI-C" function string ctime(inout int tloc[4]); + +/////////////////////////////////////////////////////////////////////////////// +// parameters +/////////////////////////////////////////////////////////////////////////////// + + // creates a 10ns ATI timing cycle + time CLK_HI = 5ns; // set clock high time + time CLK_LO = 5ns; // set clock low time + time APPL_DEL = 2ns; // set stimuli application delay + time ACQ_DEL = 8ns; // set response aquisition delay + + parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation... + +/////////////////////////////////////////////////////////////////////////////// +// progress +/////////////////////////////////////////////////////////////////////////////// + + class progress; + real newState, oldState; + longint numResp, acqCnt, errCnt, totAcqCnt, totErrCnt; + + function new(); + begin + this.acqCnt = 0; + this.errCnt = 0; + this.newState = 0.0; + this.oldState = 0.0; + this.numResp = 1; + this.totAcqCnt = 0; + this.totErrCnt = 0; + + end + endfunction : new + + function void reset(longint numResp_); + begin + this.acqCnt = 0; + this.errCnt = 0; + this.newState = 0.0; + this.oldState = 0.0; + this.numResp = numResp_; + end + endfunction : reset + + function void addRes(int isError); + begin + this.acqCnt++; + this.totAcqCnt++; + this.errCnt += isError; + this.totErrCnt += isError; + + if(ERROR_CNT_STOP_LEVEL <= this.errCnt && ERROR_CNT_STOP_LEVEL > 0) begin + $error("TB> simulation stopped (ERROR_CNT_STOP_LEVEL = %d reached).", ERROR_CNT_STOP_LEVEL); + $stop(); + end + end + endfunction : addRes + + function void print(); + begin + this.newState = $itor(this.acqCnt) / $itor(this.numResp); + if(this.newState - this.oldState >= 0.01) begin + $display("TB> validated %03d%% -- %01d failed (%03.3f%%) ", + $rtoi(this.newState*100.0), + this.errCnt, + $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); + // $fflush(); + this.oldState = this.newState; + end + end + endfunction : print + + function void printToFile(string file, bit summary = 0); + begin + int fptr; + + // sanitize string + for(fptr=0; fptr<$size(file);fptr++) begin + if(file[fptr] == " " || file[fptr] == "/" || file[fptr] == "\\") begin + file[fptr] = "_"; + end + end + + + fptr = $fopen(file,"w"); + if(summary) begin + $fdisplay(fptr, "Simulation Summary"); + $fdisplay(fptr, "total: %01d of %01d vectors failed (%03.3f%%) ", + this.totErrCnt, + this.totAcqCnt, + $itor(this.totErrCnt) / $itor(this.totAcqCnt) * 100.0); + if(this.totErrCnt == 0) begin + $fdisplay(fptr, "CI: PASSED"); + end else begin + $fdisplay(fptr, "CI: FAILED"); + end + end else begin + $fdisplay(fptr, "test name: %s", file); + $fdisplay(fptr, "this test: %01d of %01d vectors failed (%03.3f%%) ", + this.errCnt, + this.acqCnt, + $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); + + $fdisplay(fptr, "total so far: %01d of %01d vectors failed (%03.3f%%) ", + this.totErrCnt, + this.totAcqCnt, + $itor(this.totErrCnt) / $itor(this.totAcqCnt) * 100.0); + end + $fclose(fptr); + end + endfunction : printToFile + + endclass : progress + +endpackage : tb_pkg + diff --git a/tb/tb_serpent_icache/hdl/tlb_emul.sv b/tb/tb_serpent_icache/hdl/tlb_emul.sv new file mode 100644 index 0000000000..e296bc85b3 --- /dev/null +++ b/tb/tb_serpent_icache/hdl/tlb_emul.sv @@ -0,0 +1,70 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Date: 15.08.2018 +// Description: simple emulation layer for the tlb. +// + +import ariane_pkg::*; +import serpent_cache_pkg::*; + +module tlb_emul #( + parameter TlbRandHitRate = 10 //in percent +) ( + input logic clk_i, + input logic rst_ni, + + input logic tlb_rand_en_i, + input logic exception_en_i, + input logic [63:0] tlb_offset_i, + + // icache interface + input icache_areq_o_t req_i, + output icache_areq_i_t req_o +); + +logic tlb_ready_d, tlb_ready_q; + +always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlb_rand + automatic bit ok = 0; + automatic int rnd = 0; + + assert(TlbRandHitRate<=100 && TlbRandHitRate>=0) else + $fatal("TlbRandHitRate must be a percentage"); + + if(~rst_ni) begin + tlb_ready_q <= '0; + end else begin + if (tlb_rand_en_i) begin + ok = randomize(rnd) with {rnd > 0; rnd <= 100;}; + if(rnd < TlbRandHitRate) begin + tlb_ready_q = '1; + end else + tlb_ready_q = '0; + end else begin + tlb_ready_q = '1; + end + end +end + +// TODO: add random exceptions +always_comb begin : proc_tlb + req_o.fetch_valid = '0; + req_o.fetch_paddr = '0; + req_o.fetch_exception = '0; + + if (req_i.fetch_req && tlb_ready_q) begin + req_o.fetch_valid = 1'b1; + req_o.fetch_paddr = req_i.fetch_vaddr + tlb_offset_i; + end +end + +endmodule // tlb_emul diff --git a/tb/tb_serpent_icache/tb.list b/tb/tb_serpent_icache/tb.list new file mode 100644 index 0000000000..f5d018585f --- /dev/null +++ b/tb/tb_serpent_icache/tb.list @@ -0,0 +1,15 @@ +../../include/riscv_pkg.sv +../../src/debug/dm_pkg.sv +../../include/ariane_pkg.sv +../../include/serpent_cache_pkg.sv +../../src/fpga-support/rtl/SyncSpRamBeNx64.sv +../../src/cache_subsystem/serpent_icache.sv +../../src/common_cells/src/lfsr_8bit.sv +../../src/common_cells/src/fifo_v2.sv +../../src/common_cells/src/fifo_v3.sv +../../src/common_cells/src/lzc.sv +../../src/util/sram.sv +hdl/mem_emul.sv +hdl/tlb_emul.sv +hdl/tb_pkg.sv +hdl/tb.sv diff --git a/tb/tb_serpent_icache/wave.do b/tb/tb_serpent_icache/wave.do new file mode 100644 index 0000000000..982d8d75fc --- /dev/null +++ b/tb/tb_serpent_icache/wave.do @@ -0,0 +1,160 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group TB /tb/clk_i +add wave -noupdate -group TB /tb/rst_ni +add wave -noupdate -group TB /tb/flush_i +add wave -noupdate -group TB /tb/en_i +add wave -noupdate -group TB /tb/miss_o +add wave -noupdate -group TB /tb/areq_i +add wave -noupdate -group TB /tb/areq_o +add wave -noupdate -group TB /tb/dreq_i +add wave -noupdate -group TB /tb/dreq_o +add wave -noupdate -group TB /tb/mem_rtrn_vld_i +add wave -noupdate -group TB /tb/mem_rtrn_i +add wave -noupdate -group TB /tb/mem_data_req_o +add wave -noupdate -group TB /tb/mem_data_ack_i +add wave -noupdate -group TB /tb/mem_data_o +add wave -noupdate -group TB /tb/stim_start +add wave -noupdate -group TB /tb/stim_end +add wave -noupdate -group TB /tb/end_of_sim +add wave -noupdate -group TB /tb/acq_done +add wave -noupdate -group TB /tb/mem_rand_en +add wave -noupdate -group TB /tb/inv_rand_en +add wave -noupdate -group TB /tb/io_rand_en +add wave -noupdate -group TB /tb/tlb_rand_en +add wave -noupdate -group TB /tb/exception_en +add wave -noupdate -group TB /tb/tlb_offset +add wave -noupdate -group TB /tb/stim_vaddr +add wave -noupdate -group TB /tb/exp_data +add wave -noupdate -group TB /tb/exp_vaddr +add wave -noupdate -group TB /tb/stim_push +add wave -noupdate -group TB /tb/stim_flush +add wave -noupdate -group TB /tb/stim_full +add wave -noupdate -group TB /tb/exp_empty +add wave -noupdate -group TB /tb/exp_pop +add wave -noupdate -group TB /tb/dut_out_vld +add wave -noupdate -group TB /tb/dut_in_rdy +add wave -noupdate -expand -group icache /tb/dut/clk_i +add wave -noupdate -expand -group icache /tb/dut/rst_ni +add wave -noupdate -expand -group icache /tb/dut/flush_i +add wave -noupdate -expand -group icache /tb/dut/en_i +add wave -noupdate -expand -group icache /tb/dut/areq_i +add wave -noupdate -expand -group icache /tb/dut/dreq_i +add wave -noupdate -expand -group icache /tb/dut/mem_rtrn_vld_i +add wave -noupdate -expand -group icache /tb/dut/mem_rtrn_i +add wave -noupdate -expand -group icache /tb/dut/mem_data_ack_i +add wave -noupdate -expand -group icache /tb/dut/NC_ADDR_BEGIN +add wave -noupdate -expand -group icache /tb/dut/NC_ADDR_GE_LE +add wave -noupdate -expand -group icache /tb/dut/cache_en_d +add wave -noupdate -expand -group icache /tb/dut/cache_en_q +add wave -noupdate -expand -group icache /tb/dut/exception_d +add wave -noupdate -expand -group icache /tb/dut/exception_q +add wave -noupdate -expand -group icache /tb/dut/paddr_vld_d +add wave -noupdate -expand -group icache /tb/dut/paddr_vld_q +add wave -noupdate -expand -group icache /tb/dut/vaddr_d +add wave -noupdate -expand -group icache /tb/dut/vaddr_q +add wave -noupdate -expand -group icache /tb/dut/paddr_is_io +add wave -noupdate -expand -group icache /tb/dut/paddr_is_nc +add wave -noupdate -expand -group icache /tb/dut/cl_hit +add wave -noupdate -expand -group icache /tb/dut/cache_rden +add wave -noupdate -expand -group icache /tb/dut/cache_wren +add wave -noupdate -expand -group icache /tb/dut/cmp_en_d +add wave -noupdate -expand -group icache /tb/dut/cmp_en_q +add wave -noupdate -expand -group icache /tb/dut/flush_d +add wave -noupdate -expand -group icache /tb/dut/flush_q +add wave -noupdate -expand -group icache /tb/dut/update_lfsr +add wave -noupdate -expand -group icache /tb/dut/inv_way +add wave -noupdate -expand -group icache /tb/dut/rnd_way +add wave -noupdate -expand -group icache /tb/dut/repl_way +add wave -noupdate -expand -group icache /tb/dut/all_ways_valid +add wave -noupdate -expand -group icache /tb/dut/inv_en +add wave -noupdate -expand -group icache /tb/dut/flush_en +add wave -noupdate -expand -group icache /tb/dut/flush_done +add wave -noupdate -expand -group icache /tb/dut/flush_cnt_d +add wave -noupdate -expand -group icache /tb/dut/flush_cnt_q +add wave -noupdate -expand -group icache /tb/dut/cl_we +add wave -noupdate -expand -group icache /tb/dut/cl_req +add wave -noupdate -expand -group icache /tb/dut/cl_index +add wave -noupdate -expand -group icache /tb/dut/cl_offset_d +add wave -noupdate -expand -group icache /tb/dut/cl_offset_q +add wave -noupdate -expand -group icache /tb/dut/cl_tag_d +add wave -noupdate -expand -group icache /tb/dut/cl_tag_q +add wave -noupdate -expand -group icache /tb/dut/cl_tag_rdata +add wave -noupdate -expand -group icache /tb/dut/cl_rdata +add wave -noupdate -expand -group icache /tb/dut/cl_sel +add wave -noupdate -expand -group icache /tb/dut/vld_biten +add wave -noupdate -expand -group icache /tb/dut/vld_we +add wave -noupdate -expand -group icache /tb/dut/vld_req +add wave -noupdate -expand -group icache /tb/dut/vld_wdata +add wave -noupdate -expand -group icache /tb/dut/vld_rdata +add wave -noupdate -expand -group icache /tb/dut/vld_addr +add wave -noupdate -expand -group icache /tb/dut/state_d +add wave -noupdate -expand -group icache /tb/dut/state_q +add wave -noupdate -expand -group icache /tb/dut/miss_o +add wave -noupdate -expand -group icache /tb/dut/areq_o +add wave -noupdate -expand -group icache /tb/dut/dreq_o +add wave -noupdate -expand -group icache /tb/dut/mem_data_req_o +add wave -noupdate -expand -group icache /tb/dut/mem_data_o +add wave -noupdate -group mem_emul /tb/i_mem_emul/clk_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/rst_ni +add wave -noupdate -group mem_emul /tb/i_mem_emul/mem_rand_en_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/io_rand_en_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/inv_rand_en_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/tlb_offset_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/stim_vaddr_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/stim_push_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/stim_flush_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/stim_full_o +add wave -noupdate -group mem_emul /tb/i_mem_emul/exp_data_o +add wave -noupdate -group mem_emul /tb/i_mem_emul/exp_vaddr_o +add wave -noupdate -group mem_emul /tb/i_mem_emul/exp_empty_o +add wave -noupdate -group mem_emul /tb/i_mem_emul/exp_pop_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/mem_rtrn_vld_o +add wave -noupdate -group mem_emul -expand /tb/i_mem_emul/mem_rtrn_o +add wave -noupdate -group mem_emul /tb/i_mem_emul/mem_data_req_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/mem_data_ack_o +add wave -noupdate -group mem_emul /tb/i_mem_emul/mem_data_i +add wave -noupdate -group mem_emul /tb/i_mem_emul/mem_ready_q +add wave -noupdate -group mem_emul /tb/i_mem_emul/mem_inv_q +add wave -noupdate -group mem_emul /tb/i_mem_emul/rand_addr_q +add wave -noupdate -group mem_emul /tb/i_mem_emul/rand_data_q +add wave -noupdate -group mem_emul /tb/i_mem_emul/outfifo_data +add wave -noupdate -group mem_emul /tb/i_mem_emul/outfifo_pop +add wave -noupdate -group mem_emul /tb/i_mem_emul/outfifo_push +add wave -noupdate -group mem_emul /tb/i_mem_emul/outfifo_full +add wave -noupdate -group mem_emul /tb/i_mem_emul/outfifo_empty +add wave -noupdate -group mem_emul /tb/i_mem_emul/infifo_data +add wave -noupdate -group mem_emul /tb/i_mem_emul/infifo_pop +add wave -noupdate -group mem_emul /tb/i_mem_emul/infifo_push +add wave -noupdate -group mem_emul /tb/i_mem_emul/infifo_full +add wave -noupdate -group mem_emul /tb/i_mem_emul/infifo_empty +add wave -noupdate -group mem_emul /tb/i_mem_emul/stim_addr +add wave -noupdate -group mem_emul /tb/i_mem_emul/exp_empty +add wave -noupdate -group mem_emul /tb/i_mem_emul/initialized_q +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/clk_i +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/rst_ni +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/tlb_rand_en_i +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/exception_en_i +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/tlb_offset_i +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/req_i +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/req_o +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/tlb_ready_d +add wave -noupdate -group tlb_emul /tb/i_tlb_emul/tlb_ready_q +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3047 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 208 +configure wave -valuecolwidth 420 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {3049926 ps} {3050004 ps}