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Cannot simulate with QuestaSim #891
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Hello |
Update: so removing the lines suggested only brings the error to the next "-- PSL *" comment until none of the source files in /snap/hardware/hdl/core/ have them anymore.. Found out why, looks like there is a naming conflict with https://en.wikipedia.org/wiki/Property_Specification_Language that Questa expects. To prevent this, in modelsim.ini I uncomment "EmbeddedPsl = 0" Since "make model" resets the modelsim.ini file, atm I manually run vsim and run compile.do and elaborate.do Also, the output is generated in a different directory than run_sim seems to expect
Also, I believe that simulation target should be "top_opt" and not "top" as in run_sim After this, calling run_sim, Questa seems to start without errors but pauses at 0ps. I believe that at this point a new terminal should pop up, but it doesn't. Manually hitting "run all" gives a fatal error on core/top.sv, "Null foreign function encountered when calling 'psl_bfm_init'. Maybe DCI related? |
Hi @BasF0 |
When trying to start simulation of an example with QuestaSim it fails with message:
In the compile_questa.log the first error is:
Which fails to compile top, thus failing simulation. The line mentioned is a comment, so I'm not sure what is going on there.
occurs on latest master: 1507cb1
also tried one of the early commits mentioning questasim, same error: 1ebc208
Tried with FPGA= Xilinx U200, Nallatech 250S, hdl_helloworld, hls_helloworld examples..
Vivado v2018.3, QuestaSim-64 10.6a
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