diff --git a/Makefile.am b/Makefile.am
index 7725b0e70..7a5798742 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -62,8 +62,9 @@ endif
 DT = fake.dts fake-backend.dts fake2.dts fake2-backend.dts \
      p8-cronus.dts cronus.dts \
      p8-fsi.dts p8-i2c.dts p8-kernel.dts \
-     p9w-fsi.dts p9r-fsi.dts p9z-fsi.dts bmc-kernel.dts \
-     bmc-sbefifo.dts \
+     p9w-fsi.dts p9r-fsi.dts p9z-fsi.dts \
+     bmc-kernel.dts bmc-kernel-rainier.dts bmc-kernel-everest.dts \
+     bmc-sbefifo.dts bmc-sbefifo-rainier.dts bmc-sbefifo-everest.dts \
      p8-host.dts p9-host.dts p10-host.dts p8.dts p9.dts p10.dts
 
 DT_sources = $(DT:.dts=.dtb.S)
diff --git a/bmc-kernel-everest.dts.m4 b/bmc-kernel-everest.dts.m4
new file mode 100644
index 000000000..e07a98d9c
--- /dev/null
+++ b/bmc-kernel-everest.dts.m4
@@ -0,0 +1,269 @@
+dnl
+dnl PIB([addr], [index], [path-index])
+dnl
+define(`PIB',
+`
+	pib@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		reg = <0x0 0x$1 0x7>;
+		compatible = "ibm,kernel-pib";
+		index = <0x$2>;
+		device-path = "/dev/scom$3";
+		system-path = "/proc$2/pib";
+	};
+')dnl
+
+
+dnl
+dnl PIB_ODY([index], [proc], [path-index], port)
+dnl
+define(`PIB_ODY',
+`
+	pib_ody@$3$4 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+		compatible = "ibm,kernel-pib-ody";
+		index = <0x$1>;
+		proc = <0x$2>;
+		port = <$4>;
+		device-path = "/dev/scom$3$4";
+		system-path = "/proc$2/ocmb$1";
+	};
+')dnl
+
+
+dnl
+dnl SBEFIFO([index], [path-index])
+dnl
+define(`SBEFIFO',
+`
+	sbefifo@2400 { /* Bogus address */
+		reg = <0x0 0x2400 0x7>;
+		compatible = "ibm,kernel-sbefifo";
+		index = <0x$1>;
+		device-path = "/dev/sbefifo$2";
+
+		sbefifo-mem {
+			compatible = "ibm,sbefifo-mem";
+			index = <0x$1>;
+			system-path = "/mem$1";
+		};
+
+		sbefifo-pba {
+			compatible = "ibm,sbefifo-mem-pba";
+			index = <0x$1>;
+			system-path = "/mempba$1";
+		};
+
+		sbefifo-chipop {
+			compatible = "ibm,sbefifo-chipop";
+			index = <0x$1>;
+		};
+	};
+')dnl
+
+dnl
+dnl FSI_PRE([addr], [index], [path-index])
+dnl
+define(`FSI_PRE',
+`
+	fsi@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		reg = <0x0 0x$1 0x8000>;
+		compatible = "ibm,kernel-fsi";
+		device-path = "/fsi0/slave@00:00/raw";
+		index = <0x$2>;
+		system-path = "/proc$2/fsi";
+		status = "mustexist";
+
+		PIB(1000, $2, $3)
+		SBEFIFO($2, $3)
+')dnl
+
+dnl
+dnl FSI_POST()
+dnl
+define(`FSI_POST',
+`
+	};
+')dnl
+
+dnl
+dnl BMC_I2CBUS([index])
+dnl
+define(`BMC_I2CBUS',
+`
+	bmc-i2c-bus$1 {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		index = <$1>;
+		compatible = "ibm,kernel-i2c-bus";
+		device-path = "/dev/i2c-$1";
+		system-path = "/bmc0/i2c-$1";
+	};
+')dnl
+
+
+dnl
+dnl HMFSI([addr], [port], [index], [path-index])
+dnl
+define(`HMFSI',
+`
+	hmfsi@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		reg = <0x0 0x$1 0x8000>;
+		compatible = "ibm,fsi-hmfsi";
+		port = <0x$2>;
+		index = <0x$3>;
+		system-path = "/proc$3/fsi";
+
+		PIB(1000, $3, $4)
+		SBEFIFO($3, $4)
+	};
+')dnl
+
+//ody ocmb chips are defined in system device tree. The pdbg targets
+//that captures the device path to communicate with system ody ocmb
+//chips will be defined in backend device tree.
+
+//ody ocmb system device tree targets need to be mapped to backend
+//ody pib device tree targets for communication with the ody ocmb targets.
+//Mapping is done based on proc, ocmb chip index of the ody ocmb system target
+//with the proc, ocmb index and port number defined in the backend kernel device
+//tree
+
+//for get or put scom in kernel mode device path defined in PIBODY will be used
+//for cfam device-path specified in HMFSIODY will be used
+dnl
+dnl HMFSI_ODY([index], [proc], [path-index], [port])
+dnl
+define(`HMFSI_ODY',
+`
+	hmfsi-ody@$3$4 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-fsi-ody";
+		device-path = "/i2cr$3$4/slave@00:00/raw";
+		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+		index = <0x$1>;
+		proc = <0x$2>;
+		port = <$4>;
+		system-path = "/proc$2/ocmb$1/fsi";
+
+		PIB_ODY($1, $2, $3, $4)
+		/*SBE_FIFO not required in kernel mode */
+	};
+')dnl
+
+/dts-v1/;
+
+/ {
+	#address-cells = <0x1>;
+	#size-cells = <0x0>;
+
+	BMC_I2CBUS(0)
+	BMC_I2CBUS(1)
+	BMC_I2CBUS(2)
+	BMC_I2CBUS(3)
+	BMC_I2CBUS(4)
+	BMC_I2CBUS(5)
+	BMC_I2CBUS(6)
+	BMC_I2CBUS(7)
+	BMC_I2CBUS(8)
+	BMC_I2CBUS(9)
+	BMC_I2CBUS(10)
+	BMC_I2CBUS(11)
+	BMC_I2CBUS(12)
+	BMC_I2CBUS(13)
+	BMC_I2CBUS(14)
+	BMC_I2CBUS(15)
+
+	FSI_PRE(0, 0, 1)
+
+	HMFSI(100000, 1, 1, 2)
+	HMFSI(180000, 2, 2, 3)
+	HMFSI(200000, 3, 3, 4)
+	HMFSI(280000, 4, 4, 5)
+	HMFSI(300000, 5, 5, 6)
+	HMFSI(380000, 6, 6, 7)
+	HMFSI(400000, 7, 7, 8)
+
+	FSI_POST()
+
+	HMFSI_ODY(0, 0, 1, 00)
+	HMFSI_ODY(1, 0, 1, 01)
+	HMFSI_ODY(2, 0, 1, 10)
+	HMFSI_ODY(3, 0, 1, 11)
+	HMFSI_ODY(4, 0, 1, 12)
+	HMFSI_ODY(5, 0, 1, 13)
+	HMFSI_ODY(6, 0, 1, 14)
+	HMFSI_ODY(7, 0, 1, 15)
+
+	HMFSI_ODY(0, 1, 2, 02)
+	HMFSI_ODY(1, 1, 2, 03)
+	HMFSI_ODY(2, 1, 2, 10)
+	HMFSI_ODY(3, 1, 2, 11)
+	HMFSI_ODY(4, 1, 2, 14)
+	HMFSI_ODY(5, 1, 2, 15)
+	HMFSI_ODY(6, 1, 2, 16)
+	HMFSI_ODY(7, 1, 2, 17)
+
+
+	HMFSI_ODY(0, 2, 3, 00)
+	HMFSI_ODY(1, 2, 3, 01)
+	HMFSI_ODY(2, 2, 3, 10)
+	HMFSI_ODY(3, 2, 3, 11)
+	HMFSI_ODY(4, 2, 3, 12)
+	HMFSI_ODY(5, 2, 3, 13)
+	HMFSI_ODY(6, 2, 3, 14)
+	HMFSI_ODY(7, 2, 3, 15)
+
+	HMFSI_ODY(0, 3, 4, 02)
+	HMFSI_ODY(1, 3, 4, 03)
+	HMFSI_ODY(2, 3, 4, 10)
+	HMFSI_ODY(3, 3, 4, 11)
+	HMFSI_ODY(4, 3, 4, 14)
+	HMFSI_ODY(5, 3, 4, 15)
+	HMFSI_ODY(6, 3, 4, 16)
+	HMFSI_ODY(7, 3, 4, 17)
+
+	HMFSI_ODY(0, 4, 5, 00)
+	HMFSI_ODY(1, 4, 5, 01)
+	HMFSI_ODY(2, 4, 5, 10)
+	HMFSI_ODY(3, 4, 5, 11)
+	HMFSI_ODY(4, 4, 5, 12)
+	HMFSI_ODY(5, 4, 5, 13)
+	HMFSI_ODY(6, 4, 5, 14)
+	HMFSI_ODY(7, 4, 5, 15)
+
+	HMFSI_ODY(0, 5, 6, 02)
+	HMFSI_ODY(1, 5, 6, 03)
+	HMFSI_ODY(2, 5, 6, 10)
+	HMFSI_ODY(3, 5, 6, 11)
+	HMFSI_ODY(4, 5, 6, 14)
+	HMFSI_ODY(5, 5, 6, 15)
+	HMFSI_ODY(6, 5, 6, 16)
+	HMFSI_ODY(7, 5, 6, 17)
+
+	HMFSI_ODY(0, 6, 7, 00)
+	HMFSI_ODY(1, 6, 7, 01)
+	HMFSI_ODY(2, 6, 7, 10)
+	HMFSI_ODY(3, 6, 7, 11)
+	HMFSI_ODY(4, 6, 7, 12)
+	HMFSI_ODY(5, 6, 7, 13)
+	HMFSI_ODY(6, 6, 7, 14)
+	HMFSI_ODY(7, 6, 7, 15)
+
+	HMFSI_ODY(0, 7, 8, 02)
+	HMFSI_ODY(1, 7, 8, 03)
+	HMFSI_ODY(2, 7, 8, 10)
+	HMFSI_ODY(3, 7, 8, 11)
+	HMFSI_ODY(4, 7, 8, 14)
+	HMFSI_ODY(5, 7, 8, 15)
+	HMFSI_ODY(6, 7, 8, 16)
+	HMFSI_ODY(7, 7, 8, 17)
+};
diff --git a/bmc-kernel-rainier.dts.m4 b/bmc-kernel-rainier.dts.m4
new file mode 100644
index 000000000..6905b541f
--- /dev/null
+++ b/bmc-kernel-rainier.dts.m4
@@ -0,0 +1,232 @@
+dnl
+dnl PIB([addr], [index], [path-index])
+dnl
+define(`PIB',
+`
+	pib@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		reg = <0x0 0x$1 0x7>;
+		compatible = "ibm,kernel-pib";
+		index = <0x$2>;
+		device-path = "/dev/scom$3";
+		system-path = "/proc$2/pib";
+	};
+')dnl
+
+
+dnl
+dnl PIB_ODY([index], [proc], [path-index], port)
+dnl
+define(`PIB_ODY',
+`
+	pib_ody@$3$4 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+		compatible = "ibm,kernel-pib-ody";
+		index = <0x$1>;
+		proc = <0x$2>;
+		port = <$4>;
+		device-path = "/dev/scom$3$4";
+		system-path = "/proc$2/ocmb$1";
+	};
+')dnl
+
+
+dnl
+dnl SBEFIFO([index], [path-index])
+dnl
+define(`SBEFIFO',
+`
+	sbefifo@2400 { /* Bogus address */
+		reg = <0x0 0x2400 0x7>;
+		compatible = "ibm,kernel-sbefifo";
+		index = <0x$1>;
+		device-path = "/dev/sbefifo$2";
+
+		sbefifo-mem {
+			compatible = "ibm,sbefifo-mem";
+			index = <0x$1>;
+			system-path = "/mem$1";
+		};
+
+		sbefifo-pba {
+			compatible = "ibm,sbefifo-mem-pba";
+			index = <0x$1>;
+			system-path = "/mempba$1";
+		};
+
+		sbefifo-chipop {
+			compatible = "ibm,sbefifo-chipop";
+			index = <0x$1>;
+		};
+	};
+')dnl
+
+dnl
+dnl FSI_PRE([addr], [index], [path-index])
+dnl
+define(`FSI_PRE',
+`
+	fsi@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		reg = <0x0 0x$1 0x8000>;
+		compatible = "ibm,kernel-fsi";
+		device-path = "/fsi0/slave@00:00/raw";
+		index = <0x$2>;
+		system-path = "/proc$2/fsi";
+		status = "mustexist";
+
+		PIB(1000, $2, $3)
+		SBEFIFO($2, $3)
+')dnl
+
+dnl
+dnl FSI_POST()
+dnl
+define(`FSI_POST',
+`
+	};
+')dnl
+
+dnl
+dnl BMC_I2CBUS([index])
+dnl
+define(`BMC_I2CBUS',
+`
+	bmc-i2c-bus$1 {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		index = <$1>;
+		compatible = "ibm,kernel-i2c-bus";
+		device-path = "/dev/i2c-$1";
+		system-path = "/bmc0/i2c-$1";
+	};
+')dnl
+
+
+dnl
+dnl HMFSI([addr], [port], [index], [path-index])
+dnl
+define(`HMFSI',
+`
+	hmfsi@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		reg = <0x0 0x$1 0x8000>;
+		compatible = "ibm,fsi-hmfsi";
+		port = <0x$2>;
+		index = <0x$3>;
+		system-path = "/proc$3/fsi";
+
+		PIB(1000, $3, $4)
+		SBEFIFO($3, $4)
+	};
+')dnl
+
+//ody ocmb chips are defined in system device tree. The pdbg targets
+//that captures the device path to communicate with system ody ocmb
+//chips will be defined in backend device tree.
+
+//ody ocmb system device tree targets need to be mapped to backend
+//ody pib device tree targets for communication with the ody ocmb targets.
+//Mapping is done based on proc, ocmb chip index of the ody ocmb system target
+//with the proc, ocmb index and port number defined in the backend kernel device
+//tree
+
+//for get or put scom in kernel mode device path defined in PIBODY will be used
+//for cfam device-path specified in HMFSIODY will be used
+dnl
+dnl HMFSI_ODY([index], [proc], [path-index], [port])
+dnl
+define(`HMFSI_ODY',
+`
+	hmfsi-ody@$3$4 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-fsi-ody";
+		device-path = "/i2cr$3$4/slave@00:00/raw";
+		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+		index = <0x$1>;
+		proc = <0x$2>;
+		port = <$4>;
+		system-path = "/proc$2/ocmb$1/fsi";
+
+		PIB_ODY($1, $2, $3, $4)
+		/*SBE_FIFO not required in kernel mode */
+	};
+')dnl
+
+/dts-v1/;
+
+/ {
+	#address-cells = <0x1>;
+	#size-cells = <0x0>;
+
+	BMC_I2CBUS(0)
+	BMC_I2CBUS(1)
+	BMC_I2CBUS(2)
+	BMC_I2CBUS(3)
+	BMC_I2CBUS(4)
+	BMC_I2CBUS(5)
+	BMC_I2CBUS(6)
+	BMC_I2CBUS(7)
+	BMC_I2CBUS(8)
+	BMC_I2CBUS(9)
+	BMC_I2CBUS(10)
+	BMC_I2CBUS(11)
+	BMC_I2CBUS(12)
+	BMC_I2CBUS(13)
+	BMC_I2CBUS(14)
+	BMC_I2CBUS(15)
+
+	FSI_PRE(0, 0, 1)
+
+	HMFSI(100000, 1, 1, 2)
+	HMFSI(180000, 2, 2, 3)
+	HMFSI(200000, 3, 3, 4)
+	HMFSI(280000, 4, 4, 5)
+	HMFSI(300000, 5, 5, 6)
+	HMFSI(380000, 6, 6, 7)
+	HMFSI(400000, 7, 7, 8)
+
+	FSI_POST()
+
+	HMFSI_ODY(0, 0, 1, 11)
+	HMFSI_ODY(1, 0, 1, 10)
+	HMFSI_ODY(2, 0, 1, 12)
+	HMFSI_ODY(3, 0, 1, 13)
+	HMFSI_ODY(4, 0, 1, 15)
+	HMFSI_ODY(5, 0, 1, 00)
+	HMFSI_ODY(6, 0, 1, 14)
+	HMFSI_ODY(7, 0, 1, 01)
+
+	HMFSI_ODY(0, 1, 2, 02)
+	HMFSI_ODY(1, 1, 2, 10)
+	HMFSI_ODY(2, 1, 2, 14)
+	HMFSI_ODY(3, 1, 2, 17)
+	HMFSI_ODY(4, 1, 2, 15)
+	HMFSI_ODY(5, 1, 2, 11)
+	HMFSI_ODY(6, 1, 2, 03)
+	HMFSI_ODY(7, 1, 2, 16)
+
+	HMFSI_ODY(0, 2, 3, 11)
+	HMFSI_ODY(1, 2, 3, 10)
+	HMFSI_ODY(2, 2, 3, 12)
+	HMFSI_ODY(3, 2, 3, 13)
+	HMFSI_ODY(4, 2, 3, 15)
+	HMFSI_ODY(5, 2, 3, 00)
+	HMFSI_ODY(6, 2, 3, 14)
+	HMFSI_ODY(7, 2, 3, 01)
+
+	HMFSI_ODY(0, 3, 4, 02)
+	HMFSI_ODY(1, 3, 4, 10)
+	HMFSI_ODY(2, 3, 4, 14)
+	HMFSI_ODY(3, 3, 4, 17)
+	HMFSI_ODY(4, 3, 4, 15)
+	HMFSI_ODY(5, 3, 4, 11)
+	HMFSI_ODY(6, 3, 4, 03)
+	HMFSI_ODY(7, 3, 4, 16)
+};
diff --git a/bmc-kernel.dts.m4 b/bmc-kernel.dts.m4
index e07a98d9c..0e9d8bc17 100644
--- a/bmc-kernel.dts.m4
+++ b/bmc-kernel.dts.m4
@@ -14,26 +14,6 @@ define(`PIB',
 	};
 ')dnl
 
-
-dnl
-dnl PIB_ODY([index], [proc], [path-index], port)
-dnl
-define(`PIB_ODY',
-`
-	pib_ody@$3$4 {
-		#address-cells = <0x2>;
-		#size-cells = <0x1>;
-		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
-		compatible = "ibm,kernel-pib-ody";
-		index = <0x$1>;
-		proc = <0x$2>;
-		port = <$4>;
-		device-path = "/dev/scom$3$4";
-		system-path = "/proc$2/ocmb$1";
-	};
-')dnl
-
-
 dnl
 dnl SBEFIFO([index], [path-index])
 dnl
@@ -126,39 +106,6 @@ define(`HMFSI',
 	};
 ')dnl
 
-//ody ocmb chips are defined in system device tree. The pdbg targets
-//that captures the device path to communicate with system ody ocmb
-//chips will be defined in backend device tree.
-
-//ody ocmb system device tree targets need to be mapped to backend
-//ody pib device tree targets for communication with the ody ocmb targets.
-//Mapping is done based on proc, ocmb chip index of the ody ocmb system target
-//with the proc, ocmb index and port number defined in the backend kernel device
-//tree
-
-//for get or put scom in kernel mode device path defined in PIBODY will be used
-//for cfam device-path specified in HMFSIODY will be used
-dnl
-dnl HMFSI_ODY([index], [proc], [path-index], [port])
-dnl
-define(`HMFSI_ODY',
-`
-	hmfsi-ody@$3$4 {
-		#address-cells = <0x2>;
-		#size-cells = <0x1>;
-		compatible = "ibm,kernel-fsi-ody";
-		device-path = "/i2cr$3$4/slave@00:00/raw";
-		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
-		index = <0x$1>;
-		proc = <0x$2>;
-		port = <$4>;
-		system-path = "/proc$2/ocmb$1/fsi";
-
-		PIB_ODY($1, $2, $3, $4)
-		/*SBE_FIFO not required in kernel mode */
-	};
-')dnl
-
 /dts-v1/;
 
 / {
@@ -193,77 +140,4 @@ define(`HMFSI_ODY',
 	HMFSI(400000, 7, 7, 8)
 
 	FSI_POST()
-
-	HMFSI_ODY(0, 0, 1, 00)
-	HMFSI_ODY(1, 0, 1, 01)
-	HMFSI_ODY(2, 0, 1, 10)
-	HMFSI_ODY(3, 0, 1, 11)
-	HMFSI_ODY(4, 0, 1, 12)
-	HMFSI_ODY(5, 0, 1, 13)
-	HMFSI_ODY(6, 0, 1, 14)
-	HMFSI_ODY(7, 0, 1, 15)
-
-	HMFSI_ODY(0, 1, 2, 02)
-	HMFSI_ODY(1, 1, 2, 03)
-	HMFSI_ODY(2, 1, 2, 10)
-	HMFSI_ODY(3, 1, 2, 11)
-	HMFSI_ODY(4, 1, 2, 14)
-	HMFSI_ODY(5, 1, 2, 15)
-	HMFSI_ODY(6, 1, 2, 16)
-	HMFSI_ODY(7, 1, 2, 17)
-
-
-	HMFSI_ODY(0, 2, 3, 00)
-	HMFSI_ODY(1, 2, 3, 01)
-	HMFSI_ODY(2, 2, 3, 10)
-	HMFSI_ODY(3, 2, 3, 11)
-	HMFSI_ODY(4, 2, 3, 12)
-	HMFSI_ODY(5, 2, 3, 13)
-	HMFSI_ODY(6, 2, 3, 14)
-	HMFSI_ODY(7, 2, 3, 15)
-
-	HMFSI_ODY(0, 3, 4, 02)
-	HMFSI_ODY(1, 3, 4, 03)
-	HMFSI_ODY(2, 3, 4, 10)
-	HMFSI_ODY(3, 3, 4, 11)
-	HMFSI_ODY(4, 3, 4, 14)
-	HMFSI_ODY(5, 3, 4, 15)
-	HMFSI_ODY(6, 3, 4, 16)
-	HMFSI_ODY(7, 3, 4, 17)
-
-	HMFSI_ODY(0, 4, 5, 00)
-	HMFSI_ODY(1, 4, 5, 01)
-	HMFSI_ODY(2, 4, 5, 10)
-	HMFSI_ODY(3, 4, 5, 11)
-	HMFSI_ODY(4, 4, 5, 12)
-	HMFSI_ODY(5, 4, 5, 13)
-	HMFSI_ODY(6, 4, 5, 14)
-	HMFSI_ODY(7, 4, 5, 15)
-
-	HMFSI_ODY(0, 5, 6, 02)
-	HMFSI_ODY(1, 5, 6, 03)
-	HMFSI_ODY(2, 5, 6, 10)
-	HMFSI_ODY(3, 5, 6, 11)
-	HMFSI_ODY(4, 5, 6, 14)
-	HMFSI_ODY(5, 5, 6, 15)
-	HMFSI_ODY(6, 5, 6, 16)
-	HMFSI_ODY(7, 5, 6, 17)
-
-	HMFSI_ODY(0, 6, 7, 00)
-	HMFSI_ODY(1, 6, 7, 01)
-	HMFSI_ODY(2, 6, 7, 10)
-	HMFSI_ODY(3, 6, 7, 11)
-	HMFSI_ODY(4, 6, 7, 12)
-	HMFSI_ODY(5, 6, 7, 13)
-	HMFSI_ODY(6, 6, 7, 14)
-	HMFSI_ODY(7, 6, 7, 15)
-
-	HMFSI_ODY(0, 7, 8, 02)
-	HMFSI_ODY(1, 7, 8, 03)
-	HMFSI_ODY(2, 7, 8, 10)
-	HMFSI_ODY(3, 7, 8, 11)
-	HMFSI_ODY(4, 7, 8, 14)
-	HMFSI_ODY(5, 7, 8, 15)
-	HMFSI_ODY(6, 7, 8, 16)
-	HMFSI_ODY(7, 7, 8, 17)
 };
diff --git a/bmc-sbefifo-everest.dts.m4 b/bmc-sbefifo-everest.dts.m4
new file mode 100644
index 000000000..1541cdfa4
--- /dev/null
+++ b/bmc-sbefifo-everest.dts.m4
@@ -0,0 +1,261 @@
+dnl
+dnl SBEFIFO([index], [path-index])
+dnl
+define(`SBEFIFO',
+`
+	sbefifo@2400 { /* Bogus address */
+		reg = <0x0 0x2400 0x7>;
+		compatible = "ibm,kernel-sbefifo";
+		index = <0x$1>;
+		device-path = "/dev/sbefifo$2";
+
+		sbefifo-pib {
+			#address-cells = <0x2>;
+			#size-cells = <0x1>;
+			compatible = "ibm,sbefifo-pib";
+			index = <0x$1>;
+			system-path = "/proc$1/pib";
+		};
+
+		sbefifo-mem {
+			compatible = "ibm,sbefifo-mem";
+			index = <0x$1>;
+			system-path = "/mem$1";
+		};
+
+		sbefifo-pba {
+			compatible = "ibm,sbefifo-mem-pba";
+			index = <0x$1>;
+			system-path = "/mempba$1";
+		};
+
+		sbefifo-chipop {
+			compatible = "ibm,sbefifo-chipop";
+			index = <0x$1>;
+		};
+	};
+')dnl
+
+dnl
+dnl FSI_PRE([addr], [index], [path-index])
+dnl
+define(`FSI_PRE',
+`
+	fsi@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-fsi";
+		device-path = "/fsi0/slave@00:00/raw";
+		reg = <0x0 0x$1 0x8000>;
+		index = <0x$2>;
+		status = "mustexist";
+		system-path = "/proc$2/fsi";
+
+		SBEFIFO($2, $3)
+')dnl
+
+dnl
+dnl FSI_POST()
+dnl
+define(`FSI_POST',
+`
+	};
+')dnl
+
+dnl
+dnl HMFSI([addr], [port], [index], [path-index])
+dnl
+define(`HMFSI',
+`
+	hmfsi@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-fsi";
+		device-path = "/fsi1/slave@0$2:00/raw";
+		reg = <0x0 0x$1 0x8000>;
+		port = <0x$2>;
+		index = <0x$3>;
+		system-path = "/proc$3/fsi";
+
+		SBEFIFO($3, $4)
+	};
+')dnl
+
+//ocmb ody ddr5 chip SBE instance will be mapped to /dev/sbefifoXYY
+//device path where X is proc and YY is port. BMC need to use this
+//path for get/put scom to SBE instance of the ocmb ddr5 chip.
+
+//ody ocmb chips will be defined in system device tree, where as how
+//the sbe instances of these ody ocmb chips will be defined in this
+//backend device tree
+
+//ody ocmb system device tree targets will be mapped to backend
+//ody sbefifo device tree targets based on proc, ocmb chip index
+dnl
+dnl HMFSI_ODY([index], [proc], [path-index], [port])
+dnl
+define(`HMFSI_ODY',
+`
+    hmfsi-ody@$3$4 {
+        #address-cells = <0x2>;
+        #size-cells = <0x1>;
+        compatible = "ibm,kernel-fsi-ody";
+        device-path = "/i2cr$3$4/slave@00:00/raw";
+        reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+        index = <0x$1>;
+        proc = <0x$2>;
+        port = <$4>;
+
+        SBEFIFO_ODY($1, $2, $3, $4)
+    };
+')dnl
+
+dnl
+dnl SBEFIFO_ODY([index], [proc], [path-index], [port] [])
+dnl
+define(`SBEFIFO_ODY',
+`
+	sbefifo-ody@$3$4{ /* Bogus address */
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-sbefifo-ody";
+		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+		index = <0x$1>;
+		proc = <0x$2>;
+		port = <$4>;
+		device-path = "/dev/sbefifo$3$4";
+
+		sbefifo-chipop-ody {
+			compatible = "ibm,sbefifo-chipop-ody";
+			index = <0x$1>;
+			proc = <0x$2>;
+			port = <$4>;
+		};
+	};
+
+')dnl
+
+dnl
+dnl BMC_I2CBUS([index])
+dnl
+define(`BMC_I2CBUS',
+`
+	bmc-i2c-bus$1 {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		index = <$1>;
+		compatible = "ibm,kernel-i2c-bus";
+		device-path = "/dev/i2c-$1";
+		system-path = "/bmc0/i2c-$1";
+	};
+')dnl
+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <0x1>;
+	#size-cells = <0x0>;
+
+	BMC_I2CBUS(0)
+	BMC_I2CBUS(1)
+	BMC_I2CBUS(2)
+	BMC_I2CBUS(3)
+	BMC_I2CBUS(4)
+	BMC_I2CBUS(5)
+	BMC_I2CBUS(6)
+	BMC_I2CBUS(7)
+	BMC_I2CBUS(8)
+	BMC_I2CBUS(9)
+	BMC_I2CBUS(10)
+	BMC_I2CBUS(11)
+	BMC_I2CBUS(12)
+	BMC_I2CBUS(13)
+	BMC_I2CBUS(14)
+	BMC_I2CBUS(15)
+
+	FSI_PRE(0, 0, 1)
+
+	HMFSI(100000, 1, 1, 2)
+	HMFSI(180000, 2, 2, 3)
+	HMFSI(200000, 3, 3, 4)
+	HMFSI(280000, 4, 4, 5)
+	HMFSI(300000, 5, 5, 6)
+	HMFSI(380000, 6, 6, 7)
+	HMFSI(400000, 7, 7, 8)
+
+	FSI_POST()
+
+	HMFSI_ODY(0, 0, 1, 00)
+	HMFSI_ODY(1, 0, 1, 01)
+	HMFSI_ODY(2, 0, 1, 10)
+	HMFSI_ODY(3, 0, 1, 11)
+	HMFSI_ODY(4, 0, 1, 12)
+	HMFSI_ODY(5, 0, 1, 13)
+	HMFSI_ODY(6, 0, 1, 14)
+	HMFSI_ODY(7, 0, 1, 15)
+
+	HMFSI_ODY(0, 1, 2, 02)
+	HMFSI_ODY(1, 1, 2, 03)
+	HMFSI_ODY(2, 1, 2, 10)
+	HMFSI_ODY(3, 1, 2, 11)
+	HMFSI_ODY(4, 1, 2, 14)
+	HMFSI_ODY(5, 1, 2, 15)
+	HMFSI_ODY(6, 1, 2, 16)
+	HMFSI_ODY(7, 1, 2, 17)
+
+
+	HMFSI_ODY(0, 2, 3, 00)
+	HMFSI_ODY(1, 2, 3, 01)
+	HMFSI_ODY(2, 2, 3, 10)
+	HMFSI_ODY(3, 2, 3, 11)
+	HMFSI_ODY(4, 2, 3, 12)
+	HMFSI_ODY(5, 2, 3, 13)
+	HMFSI_ODY(6, 2, 3, 14)
+	HMFSI_ODY(7, 2, 3, 15)
+
+	HMFSI_ODY(0, 3, 4, 02)
+	HMFSI_ODY(1, 3, 4, 03)
+	HMFSI_ODY(2, 3, 4, 10)
+	HMFSI_ODY(3, 3, 4, 11)
+	HMFSI_ODY(4, 3, 4, 14)
+	HMFSI_ODY(5, 3, 4, 15)
+	HMFSI_ODY(6, 3, 4, 16)
+	HMFSI_ODY(7, 3, 4, 17)
+
+	HMFSI_ODY(0, 4, 5, 00)
+	HMFSI_ODY(1, 4, 5, 01)
+	HMFSI_ODY(2, 4, 5, 10)
+	HMFSI_ODY(3, 4, 5, 11)
+	HMFSI_ODY(4, 4, 5, 12)
+	HMFSI_ODY(5, 4, 5, 13)
+	HMFSI_ODY(6, 4, 5, 14)
+	HMFSI_ODY(7, 4, 5, 15)
+
+	HMFSI_ODY(0, 5, 6, 02)
+	HMFSI_ODY(1, 5, 6, 03)
+	HMFSI_ODY(2, 5, 6, 10)
+	HMFSI_ODY(3, 5, 6, 11)
+	HMFSI_ODY(4, 5, 6, 14)
+	HMFSI_ODY(5, 5, 6, 15)
+	HMFSI_ODY(6, 5, 6, 16)
+	HMFSI_ODY(7, 5, 6, 17)
+
+	HMFSI_ODY(0, 6, 7, 00)
+	HMFSI_ODY(1, 6, 7, 01)
+	HMFSI_ODY(2, 6, 7, 10)
+	HMFSI_ODY(3, 6, 7, 11)
+	HMFSI_ODY(4, 6, 7, 12)
+	HMFSI_ODY(5, 6, 7, 13)
+	HMFSI_ODY(6, 6, 7, 14)
+	HMFSI_ODY(7, 6, 7, 15)
+
+	HMFSI_ODY(0, 7, 8, 02)
+	HMFSI_ODY(1, 7, 8, 03)
+	HMFSI_ODY(2, 7, 8, 10)
+	HMFSI_ODY(3, 7, 8, 11)
+	HMFSI_ODY(4, 7, 8, 14)
+	HMFSI_ODY(5, 7, 8, 15)
+	HMFSI_ODY(6, 7, 8, 16)
+	HMFSI_ODY(7, 7, 8, 17)
+};
diff --git a/bmc-sbefifo-rainier.dts.m4 b/bmc-sbefifo-rainier.dts.m4
new file mode 100644
index 000000000..7e5abacb4
--- /dev/null
+++ b/bmc-sbefifo-rainier.dts.m4
@@ -0,0 +1,224 @@
+dnl
+dnl SBEFIFO([index], [path-index])
+dnl
+define(`SBEFIFO',
+`
+	sbefifo@2400 { /* Bogus address */
+		reg = <0x0 0x2400 0x7>;
+		compatible = "ibm,kernel-sbefifo";
+		index = <0x$1>;
+		device-path = "/dev/sbefifo$2";
+
+		sbefifo-pib {
+			#address-cells = <0x2>;
+			#size-cells = <0x1>;
+			compatible = "ibm,sbefifo-pib";
+			index = <0x$1>;
+			system-path = "/proc$1/pib";
+		};
+
+		sbefifo-mem {
+			compatible = "ibm,sbefifo-mem";
+			index = <0x$1>;
+			system-path = "/mem$1";
+		};
+
+		sbefifo-pba {
+			compatible = "ibm,sbefifo-mem-pba";
+			index = <0x$1>;
+			system-path = "/mempba$1";
+		};
+
+		sbefifo-chipop {
+			compatible = "ibm,sbefifo-chipop";
+			index = <0x$1>;
+		};
+	};
+')dnl
+
+dnl
+dnl FSI_PRE([addr], [index], [path-index])
+dnl
+define(`FSI_PRE',
+`
+	fsi@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-fsi";
+		device-path = "/fsi0/slave@00:00/raw";
+		reg = <0x0 0x$1 0x8000>;
+		index = <0x$2>;
+		status = "mustexist";
+		system-path = "/proc$2/fsi";
+
+		SBEFIFO($2, $3)
+')dnl
+
+dnl
+dnl FSI_POST()
+dnl
+define(`FSI_POST',
+`
+	};
+')dnl
+
+dnl
+dnl HMFSI([addr], [port], [index], [path-index])
+dnl
+define(`HMFSI',
+`
+	hmfsi@$1 {
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-fsi";
+		device-path = "/fsi1/slave@0$2:00/raw";
+		reg = <0x0 0x$1 0x8000>;
+		port = <0x$2>;
+		index = <0x$3>;
+		system-path = "/proc$3/fsi";
+
+		SBEFIFO($3, $4)
+	};
+')dnl
+
+//ocmb ody ddr5 chip SBE instance will be mapped to /dev/sbefifoXYY
+//device path where X is proc and YY is port. BMC need to use this
+//path for get/put scom to SBE instance of the ocmb ddr5 chip.
+
+//ody ocmb chips will be defined in system device tree, where as how
+//the sbe instances of these ody ocmb chips will be defined in this
+//backend device tree
+
+//ody ocmb system device tree targets will be mapped to backend
+//ody sbefifo device tree targets based on proc, ocmb chip index
+dnl
+dnl HMFSI_ODY([index], [proc], [path-index], [port])
+dnl
+define(`HMFSI_ODY',
+`
+    hmfsi-ody@$3$4 {
+        #address-cells = <0x2>;
+        #size-cells = <0x1>;
+        compatible = "ibm,kernel-fsi-ody";
+        device-path = "/i2cr$3$4/slave@00:00/raw";
+        reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+        index = <0x$1>;
+        proc = <0x$2>;
+        port = <$4>;
+
+        SBEFIFO_ODY($1, $2, $3, $4)
+    };
+')dnl
+
+dnl
+dnl SBEFIFO_ODY([index], [proc], [path-index], [port] [])
+dnl
+define(`SBEFIFO_ODY',
+`
+	sbefifo-ody@$3$4{ /* Bogus address */
+		#address-cells = <0x2>;
+		#size-cells = <0x1>;
+		compatible = "ibm,kernel-sbefifo-ody";
+		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
+		index = <0x$1>;
+		proc = <0x$2>;
+		port = <$4>;
+		device-path = "/dev/sbefifo$3$4";
+
+		sbefifo-chipop-ody {
+			compatible = "ibm,sbefifo-chipop-ody";
+			index = <0x$1>;
+			proc = <0x$2>;
+			port = <$4>;
+		};
+	};
+
+')dnl
+
+dnl
+dnl BMC_I2CBUS([index])
+dnl
+define(`BMC_I2CBUS',
+`
+	bmc-i2c-bus$1 {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		index = <$1>;
+		compatible = "ibm,kernel-i2c-bus";
+		device-path = "/dev/i2c-$1";
+		system-path = "/bmc0/i2c-$1";
+	};
+')dnl
+
+
+/dts-v1/;
+
+/ {
+	#address-cells = <0x1>;
+	#size-cells = <0x0>;
+
+	BMC_I2CBUS(0)
+	BMC_I2CBUS(1)
+	BMC_I2CBUS(2)
+	BMC_I2CBUS(3)
+	BMC_I2CBUS(4)
+	BMC_I2CBUS(5)
+	BMC_I2CBUS(6)
+	BMC_I2CBUS(7)
+	BMC_I2CBUS(8)
+	BMC_I2CBUS(9)
+	BMC_I2CBUS(10)
+	BMC_I2CBUS(11)
+	BMC_I2CBUS(12)
+	BMC_I2CBUS(13)
+	BMC_I2CBUS(14)
+	BMC_I2CBUS(15)
+
+	FSI_PRE(0, 0, 1)
+
+	HMFSI(100000, 1, 1, 2)
+	HMFSI(180000, 2, 2, 3)
+	HMFSI(200000, 3, 3, 4)
+	HMFSI(280000, 4, 4, 5)
+	HMFSI(300000, 5, 5, 6)
+	HMFSI(380000, 6, 6, 7)
+	HMFSI(400000, 7, 7, 8)
+
+	FSI_POST()
+
+	HMFSI_ODY(0, 0, 1, 11)
+	HMFSI_ODY(1, 0, 1, 10)
+	HMFSI_ODY(2, 0, 1, 12)
+	HMFSI_ODY(3, 0, 1, 13)
+	HMFSI_ODY(4, 0, 1, 15)
+	HMFSI_ODY(5, 0, 1, 00)
+	HMFSI_ODY(6, 0, 1, 14)
+	HMFSI_ODY(7, 0, 1, 01)
+
+	HMFSI_ODY(0, 1, 2, 02)
+	HMFSI_ODY(1, 1, 2, 10)
+	HMFSI_ODY(2, 1, 2, 14)
+	HMFSI_ODY(3, 1, 2, 17)
+	HMFSI_ODY(4, 1, 2, 15)
+	HMFSI_ODY(5, 1, 2, 11)
+	HMFSI_ODY(6, 1, 2, 03)
+	HMFSI_ODY(7, 1, 2, 16)
+
+	HMFSI_ODY(0, 2, 3, 11)
+	HMFSI_ODY(1, 2, 3, 10)
+	HMFSI_ODY(2, 2, 3, 12)
+	HMFSI_ODY(3, 2, 3, 13)
+	HMFSI_ODY(4, 2, 3, 15)
+	HMFSI_ODY(5, 2, 3, 00)
+	HMFSI_ODY(6, 2, 3, 14)
+	HMFSI_ODY(7, 2, 3, 01)
+
+	HMFSI_ODY(0, 3, 4, 02)
+	HMFSI_ODY(1, 3, 4, 10)
+	HMFSI_ODY(2, 3, 4, 14)
+	HMFSI_ODY(3, 3, 4, 17)
+	HMFSI_ODY(4, 3, 4, 15)
+	HMFSI_ODY(5, 3, 4, 11)
+	HMFSI_ODY(6, 3, 4, 03)
+	HMFSI_ODY(7, 3, 4, 16)
+};
diff --git a/bmc-sbefifo.dts.m4 b/bmc-sbefifo.dts.m4
index 1541cdfa4..462a25050 100644
--- a/bmc-sbefifo.dts.m4
+++ b/bmc-sbefifo.dts.m4
@@ -81,60 +81,6 @@ define(`HMFSI',
 	};
 ')dnl
 
-//ocmb ody ddr5 chip SBE instance will be mapped to /dev/sbefifoXYY
-//device path where X is proc and YY is port. BMC need to use this
-//path for get/put scom to SBE instance of the ocmb ddr5 chip.
-
-//ody ocmb chips will be defined in system device tree, where as how
-//the sbe instances of these ody ocmb chips will be defined in this
-//backend device tree
-
-//ody ocmb system device tree targets will be mapped to backend
-//ody sbefifo device tree targets based on proc, ocmb chip index
-dnl
-dnl HMFSI_ODY([index], [proc], [path-index], [port])
-dnl
-define(`HMFSI_ODY',
-`
-    hmfsi-ody@$3$4 {
-        #address-cells = <0x2>;
-        #size-cells = <0x1>;
-        compatible = "ibm,kernel-fsi-ody";
-        device-path = "/i2cr$3$4/slave@00:00/raw";
-        reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
-        index = <0x$1>;
-        proc = <0x$2>;
-        port = <$4>;
-
-        SBEFIFO_ODY($1, $2, $3, $4)
-    };
-')dnl
-
-dnl
-dnl SBEFIFO_ODY([index], [proc], [path-index], [port] [])
-dnl
-define(`SBEFIFO_ODY',
-`
-	sbefifo-ody@$3$4{ /* Bogus address */
-		#address-cells = <0x2>;
-		#size-cells = <0x1>;
-		compatible = "ibm,kernel-sbefifo-ody";
-		reg = <0x0 0x$1 0x8000>; /*dummy to fix dts warning*/
-		index = <0x$1>;
-		proc = <0x$2>;
-		port = <$4>;
-		device-path = "/dev/sbefifo$3$4";
-
-		sbefifo-chipop-ody {
-			compatible = "ibm,sbefifo-chipop-ody";
-			index = <0x$1>;
-			proc = <0x$2>;
-			port = <$4>;
-		};
-	};
-
-')dnl
-
 dnl
 dnl BMC_I2CBUS([index])
 dnl
@@ -185,77 +131,4 @@ define(`BMC_I2CBUS',
 	HMFSI(400000, 7, 7, 8)
 
 	FSI_POST()
-
-	HMFSI_ODY(0, 0, 1, 00)
-	HMFSI_ODY(1, 0, 1, 01)
-	HMFSI_ODY(2, 0, 1, 10)
-	HMFSI_ODY(3, 0, 1, 11)
-	HMFSI_ODY(4, 0, 1, 12)
-	HMFSI_ODY(5, 0, 1, 13)
-	HMFSI_ODY(6, 0, 1, 14)
-	HMFSI_ODY(7, 0, 1, 15)
-
-	HMFSI_ODY(0, 1, 2, 02)
-	HMFSI_ODY(1, 1, 2, 03)
-	HMFSI_ODY(2, 1, 2, 10)
-	HMFSI_ODY(3, 1, 2, 11)
-	HMFSI_ODY(4, 1, 2, 14)
-	HMFSI_ODY(5, 1, 2, 15)
-	HMFSI_ODY(6, 1, 2, 16)
-	HMFSI_ODY(7, 1, 2, 17)
-
-
-	HMFSI_ODY(0, 2, 3, 00)
-	HMFSI_ODY(1, 2, 3, 01)
-	HMFSI_ODY(2, 2, 3, 10)
-	HMFSI_ODY(3, 2, 3, 11)
-	HMFSI_ODY(4, 2, 3, 12)
-	HMFSI_ODY(5, 2, 3, 13)
-	HMFSI_ODY(6, 2, 3, 14)
-	HMFSI_ODY(7, 2, 3, 15)
-
-	HMFSI_ODY(0, 3, 4, 02)
-	HMFSI_ODY(1, 3, 4, 03)
-	HMFSI_ODY(2, 3, 4, 10)
-	HMFSI_ODY(3, 3, 4, 11)
-	HMFSI_ODY(4, 3, 4, 14)
-	HMFSI_ODY(5, 3, 4, 15)
-	HMFSI_ODY(6, 3, 4, 16)
-	HMFSI_ODY(7, 3, 4, 17)
-
-	HMFSI_ODY(0, 4, 5, 00)
-	HMFSI_ODY(1, 4, 5, 01)
-	HMFSI_ODY(2, 4, 5, 10)
-	HMFSI_ODY(3, 4, 5, 11)
-	HMFSI_ODY(4, 4, 5, 12)
-	HMFSI_ODY(5, 4, 5, 13)
-	HMFSI_ODY(6, 4, 5, 14)
-	HMFSI_ODY(7, 4, 5, 15)
-
-	HMFSI_ODY(0, 5, 6, 02)
-	HMFSI_ODY(1, 5, 6, 03)
-	HMFSI_ODY(2, 5, 6, 10)
-	HMFSI_ODY(3, 5, 6, 11)
-	HMFSI_ODY(4, 5, 6, 14)
-	HMFSI_ODY(5, 5, 6, 15)
-	HMFSI_ODY(6, 5, 6, 16)
-	HMFSI_ODY(7, 5, 6, 17)
-
-	HMFSI_ODY(0, 6, 7, 00)
-	HMFSI_ODY(1, 6, 7, 01)
-	HMFSI_ODY(2, 6, 7, 10)
-	HMFSI_ODY(3, 6, 7, 11)
-	HMFSI_ODY(4, 6, 7, 12)
-	HMFSI_ODY(5, 6, 7, 13)
-	HMFSI_ODY(6, 6, 7, 14)
-	HMFSI_ODY(7, 6, 7, 15)
-
-	HMFSI_ODY(0, 7, 8, 02)
-	HMFSI_ODY(1, 7, 8, 03)
-	HMFSI_ODY(2, 7, 8, 10)
-	HMFSI_ODY(3, 7, 8, 11)
-	HMFSI_ODY(4, 7, 8, 14)
-	HMFSI_ODY(5, 7, 8, 15)
-	HMFSI_ODY(6, 7, 8, 16)
-	HMFSI_ODY(7, 7, 8, 17)
 };
diff --git a/libpdbg/dtb.c b/libpdbg/dtb.c
index 2ca99f3df..953ea3f1e 100644
--- a/libpdbg/dtb.c
+++ b/libpdbg/dtb.c
@@ -40,13 +40,16 @@
 #include "p9r-fsi.dt.h"
 #include "p9z-fsi.dt.h"
 #include "bmc-kernel.dt.h"
+#include "bmc-kernel-rainier.dt.h"
+#include "bmc-kernel-everest.dt.h"
 #include "p8-host.dt.h"
 #include "p9-host.dt.h"
 #include "p10-host.dt.h"
 #include "p8-cronus.dt.h"
 #include "cronus.dt.h"
 #include "bmc-sbefifo.dt.h"
-
+#include "bmc-sbefifo-rainier.dt.h"
+#include "bmc-sbefifo-everest.dt.h"
 #include "p8.dt.h"
 #include "p9.dt.h"
 #include "p10.dt.h"
@@ -60,6 +63,9 @@ static const char *pdbg_backend_option;
 
 static const uint16_t ODYSSEY_CHIP_ID = 0x60C0;
 static const uint8_t ATTR_TYPE_OCMB_CHIP = 75;
+static const char* RAINIER_2U = "Rainier 2U";
+static const char* RAINIER_4U = "Rainier 4U";
+static const char* EVEREST = "Everest";
 
 static struct pdbg_dtb pdbg_dtb = {
 	.backend = {
@@ -107,6 +113,44 @@ static bool get_chipid(uint32_t *chip_id)
 	return true;
 }
 
+static char* get_p10_system_type()
+{
+	FILE* file = fopen("/proc/device-tree/model", "r");
+	if (file == NULL) {
+		pdbg_log(PDBG_ERROR, "Unable to read device-tree model file: %s", strerror(errno));
+		return "";
+	}
+
+	// Determine the size of the file
+	fseek(file, 0, SEEK_END);
+	long file_size = ftell(file);
+	fseek(file, 0, SEEK_SET);
+
+	// Allocate memory for the file content
+	char* buffer = (char*)malloc(file_size + 1);
+
+	if (buffer == NULL) {
+		pdbg_log(PDBG_ERROR, "Memory allocation failed");
+		return "";
+	}
+
+	// Read the file content into the buffer
+	size_t bytes_read = fread(buffer, 1, file_size, file);
+
+	if (bytes_read != file_size) {
+		pdbg_log(PDBG_ERROR, "Error reading file");
+		return "";
+	}
+
+	// Null-terminate the buffer to create a valid C-string
+	buffer[bytes_read] = '\0';
+
+	// Close the file
+	fclose(file);
+
+	return buffer;
+}
+
 /* Determines the most appropriate backend for the host system we are
  * running on. */
 static enum pdbg_backend default_backend(void)
@@ -258,8 +302,21 @@ static void bmc_target(struct pdbg_dtb *dtb)
 				dtb->system.fdt = &_binary_p9_dtb_o_start;
 		} else if (!strcmp(pdbg_backend_option, "p10")) {
 			pdbg_proc = PDBG_PROC_P10;
-			if (!dtb->backend.fdt)
-				dtb->backend.fdt = &_binary_bmc_kernel_dtb_o_start;
+			if (!dtb->backend.fdt) {
+				char *system_type = get_p10_system_type();
+				if (strcmp(system_type, EVEREST) == 0) {
+					pdbg_log(PDBG_INFO, "bmc_target - loading bmc kernel everest target");
+					dtb->backend.fdt = &_binary_bmc_kernel_everest_dtb_o_start;
+				} else if (strcmp(system_type, RAINIER_2U) == 0 ||
+					strcmp(system_type, RAINIER_4U) == 0) {
+					pdbg_log(PDBG_INFO, "bmc_target - loading bmc kernel rainier target");
+					dtb->backend.fdt = &_binary_bmc_kernel_rainier_dtb_o_start;
+				} else {
+					pdbg_log(PDBG_INFO, "bmc_target - loading bmc kernel target");
+					dtb->backend.fdt = &_binary_bmc_kernel_dtb_o_start;
+				}
+				free(system_type);
+			}
 			if (!dtb->system.fdt)
 				dtb->system.fdt = &_binary_p10_dtb_o_start;
 		} else {
@@ -277,8 +334,21 @@ static void bmc_target(struct pdbg_dtb *dtb)
 	case CHIP_ID_P10:
 		pdbg_log(PDBG_INFO, "Found a POWER10 OpenBMC based system\n");
 		pdbg_proc = PDBG_PROC_P10;
-		if (!dtb->backend.fdt)
-			dtb->backend.fdt = &_binary_bmc_kernel_dtb_o_start;
+		if (!dtb->backend.fdt) {
+			char *system_type = get_p10_system_type();
+			if (strcmp(system_type, EVEREST) == 0) {
+				pdbg_log(PDBG_INFO, "bmc_target - loading bmc kernel everest target");
+				dtb->backend.fdt = &_binary_bmc_kernel_everest_dtb_o_start;
+			} else if (strcmp(system_type, RAINIER_2U) == 0 ||
+				strcmp(system_type, RAINIER_4U) == 0) {
+				pdbg_log(PDBG_INFO, "bmc_target - loading bmc kernel rainier target");
+				dtb->backend.fdt = &_binary_bmc_kernel_rainier_dtb_o_start;
+			} else {
+				pdbg_log(PDBG_INFO, "bmc_target - loading bmc kernel target");
+				dtb->backend.fdt = &_binary_bmc_kernel_dtb_o_start;
+			}
+			free(system_type);
+		}
 		if (!dtb->system.fdt)
 			dtb->system.fdt = &_binary_p10_dtb_o_start;
 		break;
@@ -321,8 +391,23 @@ static void sbefifo_target(struct pdbg_dtb *dtb)
 				dtb->system.fdt = &_binary_p9_dtb_o_start;
 		} else if (!strcmp(pdbg_backend_option, "p10")) {
 			pdbg_proc = PDBG_PROC_P10;
-			if (!dtb->backend.fdt)
-				dtb->backend.fdt = &_binary_bmc_sbefifo_dtb_o_start;
+			if (!dtb->backend.fdt) {
+				char *system_type = get_p10_system_type();
+				if (strcmp(system_type, EVEREST) == 0) {
+					pdbg_log(PDBG_INFO,
+						"sbefifo_target - loading bmc sbefifo everest target");
+					dtb->backend.fdt = &_binary_bmc_sbefifo_everest_dtb_o_start;
+				} else if (strcmp(system_type, RAINIER_2U) == 0 ||
+							strcmp(system_type, RAINIER_4U) == 0) {
+					pdbg_log(PDBG_INFO,
+						"sbefifo_target - loading bmc sbefifo rainier target");
+					dtb->backend.fdt = &_binary_bmc_sbefifo_rainier_dtb_o_start;
+				} else {
+					pdbg_log(PDBG_INFO, "sbefifo_target - loading bmc sbefifo target");
+					dtb->backend.fdt = &_binary_bmc_sbefifo_dtb_o_start;
+				}
+				free(system_type);
+			}
 			if (!dtb->system.fdt)
 				dtb->system.fdt = &_binary_p10_dtb_o_start;
 		} else {
@@ -340,8 +425,23 @@ static void sbefifo_target(struct pdbg_dtb *dtb)
 	case CHIP_ID_P10:
 		pdbg_log(PDBG_INFO, "Found a POWER10 OpenBMC based system\n");
 		pdbg_proc = PDBG_PROC_P10;
-		if (!dtb->backend.fdt)
-			dtb->backend.fdt = &_binary_bmc_sbefifo_dtb_o_start;
+		if (!dtb->backend.fdt) {
+			char *system_type = get_p10_system_type();
+			if (strcmp(system_type, EVEREST) == 0) {
+				pdbg_log(PDBG_INFO,
+					"sbefifo_target - loading bmc sbefifo everest target");
+				dtb->backend.fdt = &_binary_bmc_sbefifo_everest_dtb_o_start;
+			} else if (strcmp(system_type, RAINIER_2U) == 0 ||
+				strcmp(system_type, RAINIER_4U) == 0) {
+				pdbg_log(PDBG_INFO,
+					"sbefifo_target - loading bmc sbefifo rainier target");
+				dtb->backend.fdt = &_binary_bmc_sbefifo_rainier_dtb_o_start;
+			} else {
+				pdbg_log(PDBG_INFO, "sbefifo_target - loading bmc sbefifo target");
+				dtb->backend.fdt = &_binary_bmc_sbefifo_dtb_o_start;
+			}
+			free(system_type);
+		}
 		if (!dtb->system.fdt)
 			dtb->system.fdt = &_binary_p10_dtb_o_start;
 		break;
diff --git a/libpdbg/target.c b/libpdbg/target.c
index 6961f8649..b96321462 100644
--- a/libpdbg/target.c
+++ b/libpdbg/target.c
@@ -869,13 +869,15 @@ struct pdbg_target *get_backend_target(const char* class,
 
 	uint32_t ocmb_proc = pdbg_target_index(pdbg_target_parent("proc",
 							ocmb));
-	uint32_t ocmb_index = pdbg_target_index(ocmb) % 0x8;
+	uint32_t fapi_pos = 0;
+	pdbg_target_get_attribute(ocmb, "ATTR_FAPI_POS", 4, 1, &fapi_pos);
+	fapi_pos = fapi_pos % 0x8;
 	struct pdbg_target *target;
 	pdbg_for_each_class_target(class, target) {
 		uint32_t index = pdbg_target_index(target);
 		uint32_t proc = 0;
 		if(!pdbg_target_u32_property(target, "proc", &proc)) {
-			if(index == ocmb_index && proc == ocmb_proc) {
+			if(index == fapi_pos && proc == ocmb_proc) {
 				return target;
 			}
 		}