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README
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NOTES:
This file gives all information necessary for using the tools required for
the VLSI3 Functional Unit project
Project Notes:
PDK Database: $PROJECT_ROOT/synthesis/cp65npksdst_tt1p2v25c.db
Do not place the pdk database in the SVN repository.
Standard Cell Verilog Files: on vlsi003 located in:
/s0/robin/cp65npksdsta03/
TOOL LIST
primetime:
description: Can do power analysis of an individual block or can run it on the
entire functional unit. Execute the primetime scripts from the
pt_scripts directory.
syntax: pt_shell -file <filename>.tcl
setup: source /usr/nikola/groups/vlsi/pkgs/primetime/primetime.cshrc
design compiler:
description: Each individual block can be compiled separately or the entire
functional unit can be compiled for a better synthesis. To run
synthesis, execute these scripts from the synthesis directory.
syntax: dc_shell-t -f compile_<block>.tcl
setup: source /usr/nikola/groups/vlsi/pkgs/synopsys_syn/synopsys_syn.cshrc
vcs:
description: Run VCS from the same directory as the design files (verilog/synthesis).
Be sure to include your design files in the testbench file. The simv
executable file is then created in that same directory. Run simv to
run the testbench.
syntax: vcs +v2k <testbench_filename>.v
simv
setup: source /usr/nikola/groups/vlsi/pkgs/vcs/vcs.cshrc
encounter:
description: Run Encounter from the schematic directory. You can then import a
design and specify all the necessary files relative to that schematic
directory. If you are missing any files, you can get them from the
locations specified below in ~cbolson1/vlsi_fu/.
demo: /s0/robin/cp65npksdsta03/demo/pnr/soce/
syntax: encounter
setup: source /usr/nikola/groups/vlsi/pkgs/cadence_soc/soc.cshrc
locations: lib: $ROOT/schematic/lib/
db: $ROOT/synthesis/db/
sdb: $ROOT/synthesis/sdb/
lef: $ROOT/schematic/lef/
uncertain: capTable = "captables/${mStack}/${mStack}_captables.dat"
coreOr = aspect
steps: design->import_design
floorplan->specify floorplan->Ratio,coreUtilization,core_to_boundary, Advanced->Row Height
floorplan->connect global nets
power->power planning->add rings (use M4/5 width=8,space=1,offset=1)
power->power planning->add stripes (M5,horizontal,width=8,space=1,Y offset from bottom=5)
route->special route-> deselect pad pins
place->standard cells and blocks
place->filler->add filler
route->NanoRoute->route
verify->verify geometery
save -> gds
V2LVS
setup: source /usr/nikola/groups/pkgs/calibre/calibre.cshrc
syntax: v2lvs -i -v ../synthesis/<cellname>.vh -s0 VSS -s1 VDD -s design_model.inc -o <cellname>.sp -lsr cp65npksdst.lvs