From 7a660e6489913e3d6c9f112e3ee99e1b41a08756 Mon Sep 17 00:00:00 2001 From: Tom French Date: Thu, 4 Jan 2024 18:01:53 +0000 Subject: [PATCH 1/2] chore: clippy and general cleanup of debugger --- Cargo.lock | 1 - .../execution_success/regression/new | 5103 ++++++++++++++++ .../execution_success/regression/new-acir | 202 + .../execution_success/regression/old | 5180 +++++++++++++++++ .../execution_success/regression/old-acir | 288 + tooling/debugger/Cargo.toml | 1 - tooling/debugger/build.rs | 10 - tooling/debugger/tests/debug.rs | 4 +- 8 files changed, 10775 insertions(+), 14 deletions(-) create mode 100644 test_programs/execution_success/regression/new create mode 100644 test_programs/execution_success/regression/new-acir create mode 100644 test_programs/execution_success/regression/old create mode 100644 test_programs/execution_success/regression/old-acir diff --git a/Cargo.lock b/Cargo.lock index 3266f4e652e..7a3fc491912 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -2801,7 +2801,6 @@ dependencies = [ "noirc_printable_type", "owo-colors", "rexpect", - "rustc_version", "serde_json", "tempfile", "test-binary", diff --git a/test_programs/execution_success/regression/new b/test_programs/execution_success/regression/new new file mode 100644 index 00000000000..f41afd662c6 --- /dev/null +++ b/test_programs/execution_success/regression/new @@ -0,0 +1,5103 @@ +Initial SSA: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + v3, v4 = call f1(v0, v1) + inc_rc v3 + inc_rc v3 + v6 = eq v4, Field 5 + constrain v4 == Field 5 + v10 = array_get v3, index Field 0 + v11 = array_get v3, index Field 1 + v13 = array_get v3, index Field 2 + v15 = array_get v3, index Field 3 + v17 = array_get v3, index Field 4 + v25 = allocate + store u1 1 at v25 + jmp b1(Field 0) + b1(v26: Field): + v27 = lt v26, Field 5 + jmpif v27 then: b2, else: b3 + b2(): + v28 = array_get [v10, v11, v13, v15, v17], index v26 + v29 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v26 + v30 = eq v28, v29 + v31 = load v25 + v32 = mul v31, v30 + store v32 at v25 + v33 = add v26, Field 1 + jmp b1(v33) + b3(): + v34 = load v25 + constrain v34 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v57, v58 = call f2([u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], Field 20) + inc_rc v57 + v61 = allocate + store u1 1 at v61 + jmp b4(Field 0) + b4(v62: Field): + v64 = lt v62, Field 2⁵ + jmpif v64 then: b5, else: b6 + b5(): + v65 = array_get v57, index v62 + v66 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v62 + v67 = eq v65, v66 + v68 = load v61 + v69 = mul v68, v67 + store v69 at v61 + v70 = add v62, Field 1 + jmp b4(v70) + b6(): + v71 = load v61 + constrain v71 == u1 1 + v73 = eq v58, Field 21 + constrain v58 == Field 21 + v75 = call f3() + v77 = eq v75, u64 1 + constrain v75 == u64 1 + v79 = call f4() + v81 = eq v79, u64 2⁴ + constrain v79 == u64 2⁴ + v84 = call f5(u64 0) + v85 = eq v84, u64 1 + constrain v84 == u64 1 + v88 = call f5(u64 4) + v89 = eq v88, u64 2⁴ + constrain v88 == u64 2⁴ + return +} +acir fn compact_decode f1 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + v11 = truncate v1 to 64 bits, max_bit_size: 254 + v12 = cast v11 as u64 + inc_rc v0 + v13 = lt u64 5, v12 + v14 = not v13 + constrain v13 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v18 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v18 + v20 = array_get v0, index Field 0 + v31 = div v20, Field 2⁴ + v32 = cast v20 as u4 + v33 = truncate v32 to 1 bits, max_bit_size: 4 + v34 = cast v33 as u1 + jmpif v34 then: b1, else: b2 + b1(): + v35 = load v18 + v36 = array_get v0, index Field 0 + v38 = and v36, u8 15 + v39 = truncate v38 to 4 bits, max_bit_size: 8 + v40 = cast v39 as u4 + v41 = array_set v35, index Field 0, value v40 + store v41 at v18 + inc_rc v0 + jmp b3(Field 1) + b3(v42: Field): + v43 = lt v42, Field 5 + jmpif v43 then: b4, else: b5 + b4(): + v44 = truncate v42 to 64 bits, max_bit_size: 254 + v45 = cast v44 as u64 + v46 = truncate v1 to 64 bits, max_bit_size: 254 + v47 = cast v46 as u64 + v48 = lt v45, v47 + jmpif v48 then: b6, else: b7 + b6(): + v49 = array_get v0, index v42 + v50 = load v18 + v51 = mul Field 2, v42 + v52 = sub v51, Field 1 + v54 = div v49, Field 2⁴ + v55 = cast v49 as u4 + v56 = array_set v50, index v52, value v55 + v57 = add v52, Field 1 + store v56 at v18 + v58 = load v18 + v59 = mul Field 2, v42 + v60 = and v49, u8 15 + v61 = truncate v60 to 4 bits, max_bit_size: 8 + v62 = cast v61 as u4 + v63 = array_set v58, index v59, value v62 + v64 = add v59, Field 1 + store v63 at v18 + jmp b7() + b7(): + v65 = add v42, Field 1 + jmp b3(v65) + b5(): + jmp b8() + b8(): + v92 = load v18 + v93 = mul Field 2, v1 + v94 = cast v34 as Field + v95 = add v93, v94 + v96 = sub v95, Field 2 + inc_rc v92 + return v92, v96 + b2(): + jmp b9(u64 0) + b9(v66: u64): + v68 = lt v66, u64 2 + jmpif v68 then: b10, else: b11 + b10(): + v69 = truncate v1 to 64 bits, max_bit_size: 254 + v70 = cast v69 as u64 + v72 = sub v70, u64 1 + range_check v72 to 64 bits + v73 = lt v66, v72 + jmpif v73 then: b12, else: b13 + b12(): + v74 = add v66, u64 1 + range_check v74 to 64 bits + v75 = array_get v0, index v74 + v76 = load v18 + v77 = mul u64 2, v66 + range_check v77 to 64 bits + v79 = div v75, Field 2⁴ + v80 = cast v75 as u4 + v81 = array_set v76, index v77, value v80 + v82 = add v77, Field 1 + store v81 at v18 + v83 = load v18 + v84 = mul u64 2, v66 + range_check v84 to 64 bits + v85 = add v84, u64 1 + range_check v85 to 64 bits + v86 = and v75, u8 15 + v87 = truncate v86 to 4 bits, max_bit_size: 8 + v88 = cast v87 as u4 + v89 = array_set v83, index v85, value v88 + v90 = add v85, Field 1 + store v89 at v18 + jmp b13() + b13(): + v91 = add v66, Field 1 + jmp b9(v91) + b11(): + jmp b8() +} +acir fn enc f2 { + b0(v0: [u8; 32], v1: Field): + inc_rc v0 + v5 = truncate v1 to 8 bits, max_bit_size: 254 + v6 = cast v5 as u8 + v7 = lt u8 2⁵, v6 + v8 = not v7 + constrain v7 == u1 0 + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v13 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v13 + v15 = eq v1, Field 0 + jmpif v15 then: b1, else: b2 + b1(): + v16 = load v13 + inc_rc v16 + jmp b3(v16, v1) + b3(v41: [u8; 32], v42: Field): + return v41, v42 + b2(): + v17 = truncate v1 to 8 bits, max_bit_size: 254 + v18 = cast v17 as u8 + v20 = lt v18, u8 31 + jmpif v20 then: b4, else: b5 + b4(): + v21 = load v13 + v23 = truncate v1 to 8 bits, max_bit_size: 254 + v24 = cast v23 as u8 + v25 = add u8 2⁷, v24 + range_check v25 to 8 bits + v27 = array_set v21, index Field 0, value v25 + store v27 at v13 + inc_rc v0 + jmp b6(Field 1) + b6(v28: Field): + v29 = lt v28, Field 2⁵ + jmpif v29 then: b7, else: b8 + b7(): + v30 = load v13 + v31 = sub v28, Field 1 + v32 = array_get v0, index v31 + v33 = array_set v30, index v28, value v32 + v34 = add v28, Field 1 + store v33 at v13 + v35 = add v28, Field 1 + jmp b6(v35) + b8(): + v36 = load v13 + v37 = add v1, Field 1 + inc_rc v36 + jmp b9(v36, v37) + b9(v39: [u8; 32], v40: Field): + jmp b3(v39, v40) + b5(): + v38 = load v13 + inc_rc v38 + jmp b9(v38, Field 2⁵) +} +acir fn bitshift_literal_0 f3 { + b0(): + v1 = allocate + store u64 0 at v1 + v2 = load v1 + v7 = or v2, u64 1 + store v7 at v1 + v8 = load v1 + return v8 +} +acir fn bitshift_literal_4 f4 { + b0(): + v1 = allocate + store u64 0 at v1 + v2 = load v1 + v9 = or v2, u64 2⁴ + store v9 at v1 + v10 = load v1 + return v10 +} +acir fn bitshift_variable f5 { + b0(v0: u64): + v2 = allocate + store u64 0 at v2 + v3 = load v2 + v7 = lt v0, u64 2⁶ + v9 = cast v7 as u64 + v12, v13 = call to_le_bits(v0, Field 2⁶) + v16 = array_get v13, index Field 63 + v17 = mul Field 2, v16 + v18 = sub Field 1, v16 + v19 = add v17, v18 + v20 = mul v19, v19 + v21 = mul v20, Field 2 + v23 = array_get v13, index Field 62 + v24 = mul v21, v23 + v25 = sub Field 1, v23 + v26 = mul v25, v20 + v27 = add v24, v26 + v28 = mul v27, v27 + v29 = mul v28, Field 2 + v31 = array_get v13, index Field 61 + v32 = mul v29, v31 + v33 = sub Field 1, v31 + v34 = mul v33, v28 + v35 = add v32, v34 + v36 = mul v35, v35 + v37 = mul v36, Field 2 + v39 = array_get v13, index Field 60 + v40 = mul v37, v39 + v41 = sub Field 1, v39 + v42 = mul v41, v36 + v43 = add v40, v42 + v44 = mul v43, v43 + v45 = mul v44, Field 2 + v47 = array_get v13, index Field 59 + v48 = mul v45, v47 + v49 = sub Field 1, v47 + v50 = mul v49, v44 + v51 = add v48, v50 + v52 = mul v51, v51 + v53 = mul v52, Field 2 + v55 = array_get v13, index Field 58 + v56 = mul v53, v55 + v57 = sub Field 1, v55 + v58 = mul v57, v52 + v59 = add v56, v58 + v60 = mul v59, v59 + v61 = mul v60, Field 2 + v63 = array_get v13, index Field 57 + v64 = mul v61, v63 + v65 = sub Field 1, v63 + v66 = mul v65, v60 + v67 = add v64, v66 + v68 = mul v67, v67 + v69 = mul v68, Field 2 + v71 = array_get v13, index Field 56 + v72 = mul v69, v71 + v73 = sub Field 1, v71 + v74 = mul v73, v68 + v75 = add v72, v74 + v76 = mul v75, v75 + v77 = mul v76, Field 2 + v79 = array_get v13, index Field 55 + v80 = mul v77, v79 + v81 = sub Field 1, v79 + v82 = mul v81, v76 + v83 = add v80, v82 + v84 = mul v83, v83 + v85 = mul v84, Field 2 + v87 = array_get v13, index Field 54 + v88 = mul v85, v87 + v89 = sub Field 1, v87 + v90 = mul v89, v84 + v91 = add v88, v90 + v92 = mul v91, v91 + v93 = mul v92, Field 2 + v95 = array_get v13, index Field 53 + v96 = mul v93, v95 + v97 = sub Field 1, v95 + v98 = mul v97, v92 + v99 = add v96, v98 + v100 = mul v99, v99 + v101 = mul v100, Field 2 + v103 = array_get v13, index Field 52 + v104 = mul v101, v103 + v105 = sub Field 1, v103 + v106 = mul v105, v100 + v107 = add v104, v106 + v108 = mul v107, v107 + v109 = mul v108, Field 2 + v111 = array_get v13, index Field 51 + v112 = mul v109, v111 + v113 = sub Field 1, v111 + v114 = mul v113, v108 + v115 = add v112, v114 + v116 = mul v115, v115 + v117 = mul v116, Field 2 + v119 = array_get v13, index Field 50 + v120 = mul v117, v119 + v121 = sub Field 1, v119 + v122 = mul v121, v116 + v123 = add v120, v122 + v124 = mul v123, v123 + v125 = mul v124, Field 2 + v127 = array_get v13, index Field 49 + v128 = mul v125, v127 + v129 = sub Field 1, v127 + v130 = mul v129, v124 + v131 = add v128, v130 + v132 = mul v131, v131 + v133 = mul v132, Field 2 + v135 = array_get v13, index Field 2⁴×3 + v136 = mul v133, v135 + v137 = sub Field 1, v135 + v138 = mul v137, v132 + v139 = add v136, v138 + v140 = mul v139, v139 + v141 = mul v140, Field 2 + v143 = array_get v13, index Field 47 + v144 = mul v141, v143 + v145 = sub Field 1, v143 + v146 = mul v145, v140 + v147 = add v144, v146 + v148 = mul v147, v147 + v149 = mul v148, Field 2 + v151 = array_get v13, index Field 46 + v152 = mul v149, v151 + v153 = sub Field 1, v151 + v154 = mul v153, v148 + v155 = add v152, v154 + v156 = mul v155, v155 + v157 = mul v156, Field 2 + v159 = array_get v13, index Field 45 + v160 = mul v157, v159 + v161 = sub Field 1, v159 + v162 = mul v161, v156 + v163 = add v160, v162 + v164 = mul v163, v163 + v165 = mul v164, Field 2 + v167 = array_get v13, index Field 44 + v168 = mul v165, v167 + v169 = sub Field 1, v167 + v170 = mul v169, v164 + v171 = add v168, v170 + v172 = mul v171, v171 + v173 = mul v172, Field 2 + v175 = array_get v13, index Field 43 + v176 = mul v173, v175 + v177 = sub Field 1, v175 + v178 = mul v177, v172 + v179 = add v176, v178 + v180 = mul v179, v179 + v181 = mul v180, Field 2 + v183 = array_get v13, index Field 42 + v184 = mul v181, v183 + v185 = sub Field 1, v183 + v186 = mul v185, v180 + v187 = add v184, v186 + v188 = mul v187, v187 + v189 = mul v188, Field 2 + v191 = array_get v13, index Field 41 + v192 = mul v189, v191 + v193 = sub Field 1, v191 + v194 = mul v193, v188 + v195 = add v192, v194 + v196 = mul v195, v195 + v197 = mul v196, Field 2 + v199 = array_get v13, index Field 40 + v200 = mul v197, v199 + v201 = sub Field 1, v199 + v202 = mul v201, v196 + v203 = add v200, v202 + v204 = mul v203, v203 + v205 = mul v204, Field 2 + v207 = array_get v13, index Field 39 + v208 = mul v205, v207 + v209 = sub Field 1, v207 + v210 = mul v209, v204 + v211 = add v208, v210 + v212 = mul v211, v211 + v213 = mul v212, Field 2 + v215 = array_get v13, index Field 38 + v216 = mul v213, v215 + v217 = sub Field 1, v215 + v218 = mul v217, v212 + v219 = add v216, v218 + v220 = mul v219, v219 + v221 = mul v220, Field 2 + v223 = array_get v13, index Field 37 + v224 = mul v221, v223 + v225 = sub Field 1, v223 + v226 = mul v225, v220 + v227 = add v224, v226 + v228 = mul v227, v227 + v229 = mul v228, Field 2 + v231 = array_get v13, index Field 36 + v232 = mul v229, v231 + v233 = sub Field 1, v231 + v234 = mul v233, v228 + v235 = add v232, v234 + v236 = mul v235, v235 + v237 = mul v236, Field 2 + v239 = array_get v13, index Field 35 + v240 = mul v237, v239 + v241 = sub Field 1, v239 + v242 = mul v241, v236 + v243 = add v240, v242 + v244 = mul v243, v243 + v245 = mul v244, Field 2 + v247 = array_get v13, index Field 34 + v248 = mul v245, v247 + v249 = sub Field 1, v247 + v250 = mul v249, v244 + v251 = add v248, v250 + v252 = mul v251, v251 + v253 = mul v252, Field 2 + v255 = array_get v13, index Field 33 + v256 = mul v253, v255 + v257 = sub Field 1, v255 + v258 = mul v257, v252 + v259 = add v256, v258 + v260 = mul v259, v259 + v261 = mul v260, Field 2 + v263 = array_get v13, index Field 2⁵ + v264 = mul v261, v263 + v265 = sub Field 1, v263 + v266 = mul v265, v260 + v267 = add v264, v266 + v268 = mul v267, v267 + v269 = mul v268, Field 2 + v271 = array_get v13, index Field 31 + v272 = mul v269, v271 + v273 = sub Field 1, v271 + v274 = mul v273, v268 + v275 = add v272, v274 + v276 = mul v275, v275 + v277 = mul v276, Field 2 + v279 = array_get v13, index Field 30 + v280 = mul v277, v279 + v281 = sub Field 1, v279 + v282 = mul v281, v276 + v283 = add v280, v282 + v284 = mul v283, v283 + v285 = mul v284, Field 2 + v287 = array_get v13, index Field 29 + v288 = mul v285, v287 + v289 = sub Field 1, v287 + v290 = mul v289, v284 + v291 = add v288, v290 + v292 = mul v291, v291 + v293 = mul v292, Field 2 + v295 = array_get v13, index Field 28 + v296 = mul v293, v295 + v297 = sub Field 1, v295 + v298 = mul v297, v292 + v299 = add v296, v298 + v300 = mul v299, v299 + v301 = mul v300, Field 2 + v303 = array_get v13, index Field 27 + v304 = mul v301, v303 + v305 = sub Field 1, v303 + v306 = mul v305, v300 + v307 = add v304, v306 + v308 = mul v307, v307 + v309 = mul v308, Field 2 + v311 = array_get v13, index Field 26 + v312 = mul v309, v311 + v313 = sub Field 1, v311 + v314 = mul v313, v308 + v315 = add v312, v314 + v316 = mul v315, v315 + v317 = mul v316, Field 2 + v319 = array_get v13, index Field 25 + v320 = mul v317, v319 + v321 = sub Field 1, v319 + v322 = mul v321, v316 + v323 = add v320, v322 + v324 = mul v323, v323 + v325 = mul v324, Field 2 + v327 = array_get v13, index Field 24 + v328 = mul v325, v327 + v329 = sub Field 1, v327 + v330 = mul v329, v324 + v331 = add v328, v330 + v332 = mul v331, v331 + v333 = mul v332, Field 2 + v335 = array_get v13, index Field 23 + v336 = mul v333, v335 + v337 = sub Field 1, v335 + v338 = mul v337, v332 + v339 = add v336, v338 + v340 = mul v339, v339 + v341 = mul v340, Field 2 + v343 = array_get v13, index Field 22 + v344 = mul v341, v343 + v345 = sub Field 1, v343 + v346 = mul v345, v340 + v347 = add v344, v346 + v348 = mul v347, v347 + v349 = mul v348, Field 2 + v351 = array_get v13, index Field 21 + v352 = mul v349, v351 + v353 = sub Field 1, v351 + v354 = mul v353, v348 + v355 = add v352, v354 + v356 = mul v355, v355 + v357 = mul v356, Field 2 + v359 = array_get v13, index Field 20 + v360 = mul v357, v359 + v361 = sub Field 1, v359 + v362 = mul v361, v356 + v363 = add v360, v362 + v364 = mul v363, v363 + v365 = mul v364, Field 2 + v367 = array_get v13, index Field 19 + v368 = mul v365, v367 + v369 = sub Field 1, v367 + v370 = mul v369, v364 + v371 = add v368, v370 + v372 = mul v371, v371 + v373 = mul v372, Field 2 + v375 = array_get v13, index Field 18 + v376 = mul v373, v375 + v377 = sub Field 1, v375 + v378 = mul v377, v372 + v379 = add v376, v378 + v380 = mul v379, v379 + v381 = mul v380, Field 2 + v383 = array_get v13, index Field 17 + v384 = mul v381, v383 + v385 = sub Field 1, v383 + v386 = mul v385, v380 + v387 = add v384, v386 + v388 = mul v387, v387 + v389 = mul v388, Field 2 + v391 = array_get v13, index Field 2⁴ + v392 = mul v389, v391 + v393 = sub Field 1, v391 + v394 = mul v393, v388 + v395 = add v392, v394 + v396 = mul v395, v395 + v397 = mul v396, Field 2 + v399 = array_get v13, index Field 15 + v400 = mul v397, v399 + v401 = sub Field 1, v399 + v402 = mul v401, v396 + v403 = add v400, v402 + v404 = mul v403, v403 + v405 = mul v404, Field 2 + v407 = array_get v13, index Field 14 + v408 = mul v405, v407 + v409 = sub Field 1, v407 + v410 = mul v409, v404 + v411 = add v408, v410 + v412 = mul v411, v411 + v413 = mul v412, Field 2 + v415 = array_get v13, index Field 13 + v416 = mul v413, v415 + v417 = sub Field 1, v415 + v418 = mul v417, v412 + v419 = add v416, v418 + v420 = mul v419, v419 + v421 = mul v420, Field 2 + v423 = array_get v13, index Field 12 + v424 = mul v421, v423 + v425 = sub Field 1, v423 + v426 = mul v425, v420 + v427 = add v424, v426 + v428 = mul v427, v427 + v429 = mul v428, Field 2 + v431 = array_get v13, index Field 11 + v432 = mul v429, v431 + v433 = sub Field 1, v431 + v434 = mul v433, v428 + v435 = add v432, v434 + v436 = mul v435, v435 + v437 = mul v436, Field 2 + v439 = array_get v13, index Field 10 + v440 = mul v437, v439 + v441 = sub Field 1, v439 + v442 = mul v441, v436 + v443 = add v440, v442 + v444 = mul v443, v443 + v445 = mul v444, Field 2 + v447 = array_get v13, index Field 9 + v448 = mul v445, v447 + v449 = sub Field 1, v447 + v450 = mul v449, v444 + v451 = add v448, v450 + v452 = mul v451, v451 + v453 = mul v452, Field 2 + v455 = array_get v13, index Field 8 + v456 = mul v453, v455 + v457 = sub Field 1, v455 + v458 = mul v457, v452 + v459 = add v456, v458 + v460 = mul v459, v459 + v461 = mul v460, Field 2 + v463 = array_get v13, index Field 7 + v464 = mul v461, v463 + v465 = sub Field 1, v463 + v466 = mul v465, v460 + v467 = add v464, v466 + v468 = mul v467, v467 + v469 = mul v468, Field 2 + v471 = array_get v13, index Field 6 + v472 = mul v469, v471 + v473 = sub Field 1, v471 + v474 = mul v473, v468 + v475 = add v472, v474 + v476 = mul v475, v475 + v477 = mul v476, Field 2 + v479 = array_get v13, index Field 5 + v480 = mul v477, v479 + v481 = sub Field 1, v479 + v482 = mul v481, v476 + v483 = add v480, v482 + v484 = mul v483, v483 + v485 = mul v484, Field 2 + v487 = array_get v13, index Field 4 + v488 = mul v485, v487 + v489 = sub Field 1, v487 + v490 = mul v489, v484 + v491 = add v488, v490 + v492 = mul v491, v491 + v493 = mul v492, Field 2 + v495 = array_get v13, index Field 3 + v496 = mul v493, v495 + v497 = sub Field 1, v495 + v498 = mul v497, v492 + v499 = add v496, v498 + v500 = mul v499, v499 + v501 = mul v500, Field 2 + v502 = array_get v13, index Field 2 + v503 = mul v501, v502 + v504 = sub Field 1, v502 + v505 = mul v504, v500 + v506 = add v503, v505 + v507 = mul v506, v506 + v508 = mul v507, Field 2 + v509 = array_get v13, index Field 1 + v510 = mul v508, v509 + v511 = sub Field 1, v509 + v512 = mul v511, v507 + v513 = add v510, v512 + v514 = mul v513, v513 + v515 = mul v514, Field 2 + v517 = array_get v13, index Field 0 + v518 = mul v515, v517 + v519 = sub Field 1, v517 + v520 = mul v519, v514 + v521 = add v518, v520 + v522 = truncate v521 to 64 bits, max_bit_size: 254 + v523 = cast v522 as u64 + v524 = mul v9, v523 + v525 = truncate v524 to 64 bits, max_bit_size: 254 + v526 = lt v0, u64 2⁶ + constrain v526 == u1 1 'attempt to bit-shift with overflow' + v527 = or v3, v525 + store v527 at v2 + v528 = load v2 + return v528 +} + +After Defunctionalization: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + v3, v4 = call f1(v0, v1) + inc_rc v3 + inc_rc v3 + v6 = eq v4, Field 5 + constrain v4 == Field 5 + v10 = array_get v3, index Field 0 + v11 = array_get v3, index Field 1 + v13 = array_get v3, index Field 2 + v15 = array_get v3, index Field 3 + v17 = array_get v3, index Field 4 + v25 = allocate + store u1 1 at v25 + jmp b1(Field 0) + b1(v26: Field): + v27 = lt v26, Field 5 + jmpif v27 then: b2, else: b3 + b2(): + v28 = array_get [v10, v11, v13, v15, v17], index v26 + v29 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v26 + v30 = eq v28, v29 + v31 = load v25 + v32 = mul v31, v30 + store v32 at v25 + v33 = add v26, Field 1 + jmp b1(v33) + b3(): + v34 = load v25 + constrain v34 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v57, v58 = call f2([u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], Field 20) + inc_rc v57 + v61 = allocate + store u1 1 at v61 + jmp b4(Field 0) + b4(v62: Field): + v64 = lt v62, Field 2⁵ + jmpif v64 then: b5, else: b6 + b5(): + v65 = array_get v57, index v62 + v66 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v62 + v67 = eq v65, v66 + v68 = load v61 + v69 = mul v68, v67 + store v69 at v61 + v70 = add v62, Field 1 + jmp b4(v70) + b6(): + v71 = load v61 + constrain v71 == u1 1 + v73 = eq v58, Field 21 + constrain v58 == Field 21 + v75 = call f3() + v77 = eq v75, u64 1 + constrain v75 == u64 1 + v79 = call f4() + v81 = eq v79, u64 2⁴ + constrain v79 == u64 2⁴ + v84 = call f5(u64 0) + v85 = eq v84, u64 1 + constrain v84 == u64 1 + v88 = call f5(u64 4) + v89 = eq v88, u64 2⁴ + constrain v88 == u64 2⁴ + return +} +acir fn compact_decode f1 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + v11 = truncate v1 to 64 bits, max_bit_size: 254 + v12 = cast v11 as u64 + inc_rc v0 + v13 = lt u64 5, v12 + v14 = not v13 + constrain v13 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v18 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v18 + v20 = array_get v0, index Field 0 + v31 = div v20, Field 2⁴ + v32 = cast v20 as u4 + v33 = truncate v32 to 1 bits, max_bit_size: 4 + v34 = cast v33 as u1 + jmpif v34 then: b1, else: b2 + b1(): + v35 = load v18 + v36 = array_get v0, index Field 0 + v38 = and v36, u8 15 + v39 = truncate v38 to 4 bits, max_bit_size: 8 + v40 = cast v39 as u4 + v41 = array_set v35, index Field 0, value v40 + store v41 at v18 + inc_rc v0 + jmp b3(Field 1) + b3(v42: Field): + v43 = lt v42, Field 5 + jmpif v43 then: b4, else: b5 + b4(): + v44 = truncate v42 to 64 bits, max_bit_size: 254 + v45 = cast v44 as u64 + v46 = truncate v1 to 64 bits, max_bit_size: 254 + v47 = cast v46 as u64 + v48 = lt v45, v47 + jmpif v48 then: b6, else: b7 + b6(): + v49 = array_get v0, index v42 + v50 = load v18 + v51 = mul Field 2, v42 + v52 = sub v51, Field 1 + v54 = div v49, Field 2⁴ + v55 = cast v49 as u4 + v56 = array_set v50, index v52, value v55 + v57 = add v52, Field 1 + store v56 at v18 + v58 = load v18 + v59 = mul Field 2, v42 + v60 = and v49, u8 15 + v61 = truncate v60 to 4 bits, max_bit_size: 8 + v62 = cast v61 as u4 + v63 = array_set v58, index v59, value v62 + v64 = add v59, Field 1 + store v63 at v18 + jmp b7() + b7(): + v65 = add v42, Field 1 + jmp b3(v65) + b5(): + jmp b8() + b8(): + v92 = load v18 + v93 = mul Field 2, v1 + v94 = cast v34 as Field + v95 = add v93, v94 + v96 = sub v95, Field 2 + inc_rc v92 + return v92, v96 + b2(): + jmp b9(u64 0) + b9(v66: u64): + v68 = lt v66, u64 2 + jmpif v68 then: b10, else: b11 + b10(): + v69 = truncate v1 to 64 bits, max_bit_size: 254 + v70 = cast v69 as u64 + v72 = sub v70, u64 1 + range_check v72 to 64 bits + v73 = lt v66, v72 + jmpif v73 then: b12, else: b13 + b12(): + v74 = add v66, u64 1 + range_check v74 to 64 bits + v75 = array_get v0, index v74 + v76 = load v18 + v77 = mul u64 2, v66 + range_check v77 to 64 bits + v79 = div v75, Field 2⁴ + v80 = cast v75 as u4 + v81 = array_set v76, index v77, value v80 + v82 = add v77, Field 1 + store v81 at v18 + v83 = load v18 + v84 = mul u64 2, v66 + range_check v84 to 64 bits + v85 = add v84, u64 1 + range_check v85 to 64 bits + v86 = and v75, u8 15 + v87 = truncate v86 to 4 bits, max_bit_size: 8 + v88 = cast v87 as u4 + v89 = array_set v83, index v85, value v88 + v90 = add v85, Field 1 + store v89 at v18 + jmp b13() + b13(): + v91 = add v66, Field 1 + jmp b9(v91) + b11(): + jmp b8() +} +acir fn enc f2 { + b0(v0: [u8; 32], v1: Field): + inc_rc v0 + v5 = truncate v1 to 8 bits, max_bit_size: 254 + v6 = cast v5 as u8 + v7 = lt u8 2⁵, v6 + v8 = not v7 + constrain v7 == u1 0 + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v13 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v13 + v15 = eq v1, Field 0 + jmpif v15 then: b1, else: b2 + b1(): + v16 = load v13 + inc_rc v16 + jmp b3(v16, v1) + b3(v41: [u8; 32], v42: Field): + return v41, v42 + b2(): + v17 = truncate v1 to 8 bits, max_bit_size: 254 + v18 = cast v17 as u8 + v20 = lt v18, u8 31 + jmpif v20 then: b4, else: b5 + b4(): + v21 = load v13 + v23 = truncate v1 to 8 bits, max_bit_size: 254 + v24 = cast v23 as u8 + v25 = add u8 2⁷, v24 + range_check v25 to 8 bits + v27 = array_set v21, index Field 0, value v25 + store v27 at v13 + inc_rc v0 + jmp b6(Field 1) + b6(v28: Field): + v29 = lt v28, Field 2⁵ + jmpif v29 then: b7, else: b8 + b7(): + v30 = load v13 + v31 = sub v28, Field 1 + v32 = array_get v0, index v31 + v33 = array_set v30, index v28, value v32 + v34 = add v28, Field 1 + store v33 at v13 + v35 = add v28, Field 1 + jmp b6(v35) + b8(): + v36 = load v13 + v37 = add v1, Field 1 + inc_rc v36 + jmp b9(v36, v37) + b9(v39: [u8; 32], v40: Field): + jmp b3(v39, v40) + b5(): + v38 = load v13 + inc_rc v38 + jmp b9(v38, Field 2⁵) +} +acir fn bitshift_literal_0 f3 { + b0(): + v1 = allocate + store u64 0 at v1 + v2 = load v1 + v7 = or v2, u64 1 + store v7 at v1 + v8 = load v1 + return v8 +} +acir fn bitshift_literal_4 f4 { + b0(): + v1 = allocate + store u64 0 at v1 + v2 = load v1 + v9 = or v2, u64 2⁴ + store v9 at v1 + v10 = load v1 + return v10 +} +acir fn bitshift_variable f5 { + b0(v0: u64): + v2 = allocate + store u64 0 at v2 + v3 = load v2 + v7 = lt v0, u64 2⁶ + v9 = cast v7 as u64 + v12, v13 = call to_le_bits(v0, Field 2⁶) + v16 = array_get v13, index Field 63 + v17 = mul Field 2, v16 + v18 = sub Field 1, v16 + v19 = add v17, v18 + v20 = mul v19, v19 + v21 = mul v20, Field 2 + v23 = array_get v13, index Field 62 + v24 = mul v21, v23 + v25 = sub Field 1, v23 + v26 = mul v25, v20 + v27 = add v24, v26 + v28 = mul v27, v27 + v29 = mul v28, Field 2 + v31 = array_get v13, index Field 61 + v32 = mul v29, v31 + v33 = sub Field 1, v31 + v34 = mul v33, v28 + v35 = add v32, v34 + v36 = mul v35, v35 + v37 = mul v36, Field 2 + v39 = array_get v13, index Field 60 + v40 = mul v37, v39 + v41 = sub Field 1, v39 + v42 = mul v41, v36 + v43 = add v40, v42 + v44 = mul v43, v43 + v45 = mul v44, Field 2 + v47 = array_get v13, index Field 59 + v48 = mul v45, v47 + v49 = sub Field 1, v47 + v50 = mul v49, v44 + v51 = add v48, v50 + v52 = mul v51, v51 + v53 = mul v52, Field 2 + v55 = array_get v13, index Field 58 + v56 = mul v53, v55 + v57 = sub Field 1, v55 + v58 = mul v57, v52 + v59 = add v56, v58 + v60 = mul v59, v59 + v61 = mul v60, Field 2 + v63 = array_get v13, index Field 57 + v64 = mul v61, v63 + v65 = sub Field 1, v63 + v66 = mul v65, v60 + v67 = add v64, v66 + v68 = mul v67, v67 + v69 = mul v68, Field 2 + v71 = array_get v13, index Field 56 + v72 = mul v69, v71 + v73 = sub Field 1, v71 + v74 = mul v73, v68 + v75 = add v72, v74 + v76 = mul v75, v75 + v77 = mul v76, Field 2 + v79 = array_get v13, index Field 55 + v80 = mul v77, v79 + v81 = sub Field 1, v79 + v82 = mul v81, v76 + v83 = add v80, v82 + v84 = mul v83, v83 + v85 = mul v84, Field 2 + v87 = array_get v13, index Field 54 + v88 = mul v85, v87 + v89 = sub Field 1, v87 + v90 = mul v89, v84 + v91 = add v88, v90 + v92 = mul v91, v91 + v93 = mul v92, Field 2 + v95 = array_get v13, index Field 53 + v96 = mul v93, v95 + v97 = sub Field 1, v95 + v98 = mul v97, v92 + v99 = add v96, v98 + v100 = mul v99, v99 + v101 = mul v100, Field 2 + v103 = array_get v13, index Field 52 + v104 = mul v101, v103 + v105 = sub Field 1, v103 + v106 = mul v105, v100 + v107 = add v104, v106 + v108 = mul v107, v107 + v109 = mul v108, Field 2 + v111 = array_get v13, index Field 51 + v112 = mul v109, v111 + v113 = sub Field 1, v111 + v114 = mul v113, v108 + v115 = add v112, v114 + v116 = mul v115, v115 + v117 = mul v116, Field 2 + v119 = array_get v13, index Field 50 + v120 = mul v117, v119 + v121 = sub Field 1, v119 + v122 = mul v121, v116 + v123 = add v120, v122 + v124 = mul v123, v123 + v125 = mul v124, Field 2 + v127 = array_get v13, index Field 49 + v128 = mul v125, v127 + v129 = sub Field 1, v127 + v130 = mul v129, v124 + v131 = add v128, v130 + v132 = mul v131, v131 + v133 = mul v132, Field 2 + v135 = array_get v13, index Field 2⁴×3 + v136 = mul v133, v135 + v137 = sub Field 1, v135 + v138 = mul v137, v132 + v139 = add v136, v138 + v140 = mul v139, v139 + v141 = mul v140, Field 2 + v143 = array_get v13, index Field 47 + v144 = mul v141, v143 + v145 = sub Field 1, v143 + v146 = mul v145, v140 + v147 = add v144, v146 + v148 = mul v147, v147 + v149 = mul v148, Field 2 + v151 = array_get v13, index Field 46 + v152 = mul v149, v151 + v153 = sub Field 1, v151 + v154 = mul v153, v148 + v155 = add v152, v154 + v156 = mul v155, v155 + v157 = mul v156, Field 2 + v159 = array_get v13, index Field 45 + v160 = mul v157, v159 + v161 = sub Field 1, v159 + v162 = mul v161, v156 + v163 = add v160, v162 + v164 = mul v163, v163 + v165 = mul v164, Field 2 + v167 = array_get v13, index Field 44 + v168 = mul v165, v167 + v169 = sub Field 1, v167 + v170 = mul v169, v164 + v171 = add v168, v170 + v172 = mul v171, v171 + v173 = mul v172, Field 2 + v175 = array_get v13, index Field 43 + v176 = mul v173, v175 + v177 = sub Field 1, v175 + v178 = mul v177, v172 + v179 = add v176, v178 + v180 = mul v179, v179 + v181 = mul v180, Field 2 + v183 = array_get v13, index Field 42 + v184 = mul v181, v183 + v185 = sub Field 1, v183 + v186 = mul v185, v180 + v187 = add v184, v186 + v188 = mul v187, v187 + v189 = mul v188, Field 2 + v191 = array_get v13, index Field 41 + v192 = mul v189, v191 + v193 = sub Field 1, v191 + v194 = mul v193, v188 + v195 = add v192, v194 + v196 = mul v195, v195 + v197 = mul v196, Field 2 + v199 = array_get v13, index Field 40 + v200 = mul v197, v199 + v201 = sub Field 1, v199 + v202 = mul v201, v196 + v203 = add v200, v202 + v204 = mul v203, v203 + v205 = mul v204, Field 2 + v207 = array_get v13, index Field 39 + v208 = mul v205, v207 + v209 = sub Field 1, v207 + v210 = mul v209, v204 + v211 = add v208, v210 + v212 = mul v211, v211 + v213 = mul v212, Field 2 + v215 = array_get v13, index Field 38 + v216 = mul v213, v215 + v217 = sub Field 1, v215 + v218 = mul v217, v212 + v219 = add v216, v218 + v220 = mul v219, v219 + v221 = mul v220, Field 2 + v223 = array_get v13, index Field 37 + v224 = mul v221, v223 + v225 = sub Field 1, v223 + v226 = mul v225, v220 + v227 = add v224, v226 + v228 = mul v227, v227 + v229 = mul v228, Field 2 + v231 = array_get v13, index Field 36 + v232 = mul v229, v231 + v233 = sub Field 1, v231 + v234 = mul v233, v228 + v235 = add v232, v234 + v236 = mul v235, v235 + v237 = mul v236, Field 2 + v239 = array_get v13, index Field 35 + v240 = mul v237, v239 + v241 = sub Field 1, v239 + v242 = mul v241, v236 + v243 = add v240, v242 + v244 = mul v243, v243 + v245 = mul v244, Field 2 + v247 = array_get v13, index Field 34 + v248 = mul v245, v247 + v249 = sub Field 1, v247 + v250 = mul v249, v244 + v251 = add v248, v250 + v252 = mul v251, v251 + v253 = mul v252, Field 2 + v255 = array_get v13, index Field 33 + v256 = mul v253, v255 + v257 = sub Field 1, v255 + v258 = mul v257, v252 + v259 = add v256, v258 + v260 = mul v259, v259 + v261 = mul v260, Field 2 + v263 = array_get v13, index Field 2⁵ + v264 = mul v261, v263 + v265 = sub Field 1, v263 + v266 = mul v265, v260 + v267 = add v264, v266 + v268 = mul v267, v267 + v269 = mul v268, Field 2 + v271 = array_get v13, index Field 31 + v272 = mul v269, v271 + v273 = sub Field 1, v271 + v274 = mul v273, v268 + v275 = add v272, v274 + v276 = mul v275, v275 + v277 = mul v276, Field 2 + v279 = array_get v13, index Field 30 + v280 = mul v277, v279 + v281 = sub Field 1, v279 + v282 = mul v281, v276 + v283 = add v280, v282 + v284 = mul v283, v283 + v285 = mul v284, Field 2 + v287 = array_get v13, index Field 29 + v288 = mul v285, v287 + v289 = sub Field 1, v287 + v290 = mul v289, v284 + v291 = add v288, v290 + v292 = mul v291, v291 + v293 = mul v292, Field 2 + v295 = array_get v13, index Field 28 + v296 = mul v293, v295 + v297 = sub Field 1, v295 + v298 = mul v297, v292 + v299 = add v296, v298 + v300 = mul v299, v299 + v301 = mul v300, Field 2 + v303 = array_get v13, index Field 27 + v304 = mul v301, v303 + v305 = sub Field 1, v303 + v306 = mul v305, v300 + v307 = add v304, v306 + v308 = mul v307, v307 + v309 = mul v308, Field 2 + v311 = array_get v13, index Field 26 + v312 = mul v309, v311 + v313 = sub Field 1, v311 + v314 = mul v313, v308 + v315 = add v312, v314 + v316 = mul v315, v315 + v317 = mul v316, Field 2 + v319 = array_get v13, index Field 25 + v320 = mul v317, v319 + v321 = sub Field 1, v319 + v322 = mul v321, v316 + v323 = add v320, v322 + v324 = mul v323, v323 + v325 = mul v324, Field 2 + v327 = array_get v13, index Field 24 + v328 = mul v325, v327 + v329 = sub Field 1, v327 + v330 = mul v329, v324 + v331 = add v328, v330 + v332 = mul v331, v331 + v333 = mul v332, Field 2 + v335 = array_get v13, index Field 23 + v336 = mul v333, v335 + v337 = sub Field 1, v335 + v338 = mul v337, v332 + v339 = add v336, v338 + v340 = mul v339, v339 + v341 = mul v340, Field 2 + v343 = array_get v13, index Field 22 + v344 = mul v341, v343 + v345 = sub Field 1, v343 + v346 = mul v345, v340 + v347 = add v344, v346 + v348 = mul v347, v347 + v349 = mul v348, Field 2 + v351 = array_get v13, index Field 21 + v352 = mul v349, v351 + v353 = sub Field 1, v351 + v354 = mul v353, v348 + v355 = add v352, v354 + v356 = mul v355, v355 + v357 = mul v356, Field 2 + v359 = array_get v13, index Field 20 + v360 = mul v357, v359 + v361 = sub Field 1, v359 + v362 = mul v361, v356 + v363 = add v360, v362 + v364 = mul v363, v363 + v365 = mul v364, Field 2 + v367 = array_get v13, index Field 19 + v368 = mul v365, v367 + v369 = sub Field 1, v367 + v370 = mul v369, v364 + v371 = add v368, v370 + v372 = mul v371, v371 + v373 = mul v372, Field 2 + v375 = array_get v13, index Field 18 + v376 = mul v373, v375 + v377 = sub Field 1, v375 + v378 = mul v377, v372 + v379 = add v376, v378 + v380 = mul v379, v379 + v381 = mul v380, Field 2 + v383 = array_get v13, index Field 17 + v384 = mul v381, v383 + v385 = sub Field 1, v383 + v386 = mul v385, v380 + v387 = add v384, v386 + v388 = mul v387, v387 + v389 = mul v388, Field 2 + v391 = array_get v13, index Field 2⁴ + v392 = mul v389, v391 + v393 = sub Field 1, v391 + v394 = mul v393, v388 + v395 = add v392, v394 + v396 = mul v395, v395 + v397 = mul v396, Field 2 + v399 = array_get v13, index Field 15 + v400 = mul v397, v399 + v401 = sub Field 1, v399 + v402 = mul v401, v396 + v403 = add v400, v402 + v404 = mul v403, v403 + v405 = mul v404, Field 2 + v407 = array_get v13, index Field 14 + v408 = mul v405, v407 + v409 = sub Field 1, v407 + v410 = mul v409, v404 + v411 = add v408, v410 + v412 = mul v411, v411 + v413 = mul v412, Field 2 + v415 = array_get v13, index Field 13 + v416 = mul v413, v415 + v417 = sub Field 1, v415 + v418 = mul v417, v412 + v419 = add v416, v418 + v420 = mul v419, v419 + v421 = mul v420, Field 2 + v423 = array_get v13, index Field 12 + v424 = mul v421, v423 + v425 = sub Field 1, v423 + v426 = mul v425, v420 + v427 = add v424, v426 + v428 = mul v427, v427 + v429 = mul v428, Field 2 + v431 = array_get v13, index Field 11 + v432 = mul v429, v431 + v433 = sub Field 1, v431 + v434 = mul v433, v428 + v435 = add v432, v434 + v436 = mul v435, v435 + v437 = mul v436, Field 2 + v439 = array_get v13, index Field 10 + v440 = mul v437, v439 + v441 = sub Field 1, v439 + v442 = mul v441, v436 + v443 = add v440, v442 + v444 = mul v443, v443 + v445 = mul v444, Field 2 + v447 = array_get v13, index Field 9 + v448 = mul v445, v447 + v449 = sub Field 1, v447 + v450 = mul v449, v444 + v451 = add v448, v450 + v452 = mul v451, v451 + v453 = mul v452, Field 2 + v455 = array_get v13, index Field 8 + v456 = mul v453, v455 + v457 = sub Field 1, v455 + v458 = mul v457, v452 + v459 = add v456, v458 + v460 = mul v459, v459 + v461 = mul v460, Field 2 + v463 = array_get v13, index Field 7 + v464 = mul v461, v463 + v465 = sub Field 1, v463 + v466 = mul v465, v460 + v467 = add v464, v466 + v468 = mul v467, v467 + v469 = mul v468, Field 2 + v471 = array_get v13, index Field 6 + v472 = mul v469, v471 + v473 = sub Field 1, v471 + v474 = mul v473, v468 + v475 = add v472, v474 + v476 = mul v475, v475 + v477 = mul v476, Field 2 + v479 = array_get v13, index Field 5 + v480 = mul v477, v479 + v481 = sub Field 1, v479 + v482 = mul v481, v476 + v483 = add v480, v482 + v484 = mul v483, v483 + v485 = mul v484, Field 2 + v487 = array_get v13, index Field 4 + v488 = mul v485, v487 + v489 = sub Field 1, v487 + v490 = mul v489, v484 + v491 = add v488, v490 + v492 = mul v491, v491 + v493 = mul v492, Field 2 + v495 = array_get v13, index Field 3 + v496 = mul v493, v495 + v497 = sub Field 1, v495 + v498 = mul v497, v492 + v499 = add v496, v498 + v500 = mul v499, v499 + v501 = mul v500, Field 2 + v502 = array_get v13, index Field 2 + v503 = mul v501, v502 + v504 = sub Field 1, v502 + v505 = mul v504, v500 + v506 = add v503, v505 + v507 = mul v506, v506 + v508 = mul v507, Field 2 + v509 = array_get v13, index Field 1 + v510 = mul v508, v509 + v511 = sub Field 1, v509 + v512 = mul v511, v507 + v513 = add v510, v512 + v514 = mul v513, v513 + v515 = mul v514, Field 2 + v517 = array_get v13, index Field 0 + v518 = mul v515, v517 + v519 = sub Field 1, v517 + v520 = mul v519, v514 + v521 = add v518, v520 + v522 = truncate v521 to 64 bits, max_bit_size: 254 + v523 = cast v522 as u64 + v524 = mul v9, v523 + v525 = truncate v524 to 64 bits, max_bit_size: 254 + v526 = lt v0, u64 2⁶ + constrain v526 == u1 1 'attempt to bit-shift with overflow' + v527 = or v3, v525 + store v527 at v2 + v528 = load v2 + return v528 +} + +After Inlining: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v3 = truncate v1 to 64 bits, max_bit_size: 254 + v4 = cast v3 as u64 + inc_rc v0 + v6 = lt u64 5, v4 + v7 = not v6 + constrain v6 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v11 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v11 + v13 = array_get v0, index Field 0 + v15 = div v13, Field 2⁴ + v16 = cast v13 as u4 + v17 = truncate v16 to 1 bits, max_bit_size: 4 + v18 = cast v17 as u1 + jmpif v18 then: b1, else: b2 + b1(): + v53 = load v11 + v54 = array_get v0, index Field 0 + v55 = and v54, u8 15 + v56 = truncate v55 to 4 bits, max_bit_size: 8 + v57 = cast v56 as u4 + v58 = array_set v53, index Field 0, value v57 + store v58 at v11 + inc_rc v0 + jmp b9(Field 1) + b9(v59: Field): + v61 = lt v59, Field 5 + jmpif v61 then: b10, else: b11 + b10(): + v62 = truncate v59 to 64 bits, max_bit_size: 254 + v63 = cast v62 as u64 + v64 = truncate v1 to 64 bits, max_bit_size: 254 + v65 = cast v64 as u64 + v66 = lt v63, v65 + jmpif v66 then: b12, else: b13 + b12(): + v68 = array_get v0, index v59 + v69 = load v11 + v70 = mul Field 2, v59 + v71 = sub v70, Field 1 + v72 = div v68, Field 2⁴ + v73 = cast v68 as u4 + v74 = array_set v69, index v71, value v73 + v75 = add v71, Field 1 + store v74 at v11 + v76 = load v11 + v77 = mul Field 2, v59 + v78 = and v68, u8 15 + v79 = truncate v78 to 4 bits, max_bit_size: 8 + v80 = cast v79 as u4 + v81 = array_set v76, index v77, value v80 + v82 = add v77, Field 1 + store v81 at v11 + jmp b13() + b13(): + v67 = add v59, Field 1 + jmp b9(v67) + b11(): + jmp b6() + b6(): + v23 = load v11 + v25 = mul Field 2, v1 + v26 = cast v18 as Field + v27 = add v25, v26 + v28 = sub v27, Field 2 + inc_rc v23 + inc_rc v23 + inc_rc v23 + v83 = eq v28, Field 5 + constrain v28 == Field 5 + v84 = array_get v23, index Field 0 + v85 = array_get v23, index Field 1 + v86 = array_get v23, index Field 2 + v88 = array_get v23, index Field 3 + v90 = array_get v23, index Field 4 + v91 = allocate + store u1 1 at v91 + jmp b14(Field 0) + b14(v93: Field): + v94 = lt v93, Field 5 + jmpif v94 then: b15, else: b16 + b15(): + v239 = array_get [v84, v85, v86, v88, v90], index v93 + v246 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v93 + v247 = eq v239, v246 + v248 = load v91 + v249 = mul v248, v247 + store v249 at v91 + v250 = add v93, Field 1 + jmp b14(v250) + b16(): + v95 = load v91 + constrain v95 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v121 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v121 + jmp b17() + b17(): + jmp b18() + b18(): + v123 = load v121 + range_check u8 148 to 8 bits + v125 = array_set v123, index Field 0, value u8 148 + store v125 at v121 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + jmp b19(Field 1) + b19(v126: Field): + v128 = lt v126, Field 2⁵ + jmpif v128 then: b20, else: b21 + b20(): + v135 = load v121 + v136 = sub v126, Field 1 + v137 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v136 + v138 = array_set v135, index v126, value v137 + v139 = add v126, Field 1 + store v138 at v121 + v140 = add v126, Field 1 + jmp b19(v140) + b21(): + v129 = load v121 + inc_rc v129 + jmp b22(v129, Field 21) + b22(v131: [u8; 32], v132: Field): + jmp b23(v131, v132) + b23(v133: [u8; 32], v134: Field): + inc_rc v133 + v141 = allocate + store u1 1 at v141 + jmp b24(Field 0) + b24(v142: Field): + v143 = lt v142, Field 2⁵ + jmpif v143 then: b25, else: b26 + b25(): + v231 = array_get v133, index v142 + v233 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v142 + v234 = eq v231, v233 + v235 = load v141 + v236 = mul v235, v234 + store v236 at v141 + v237 = add v142, Field 1 + jmp b24(v237) + b26(): + v144 = load v141 + constrain v144 == u1 1 + v145 = eq v134, Field 21 + constrain v134 == Field 21 + v147 = allocate + store u64 0 at v147 + v148 = load v147 + v149 = or v148, u64 1 + store v149 at v147 + v150 = load v147 + v151 = eq v150, u64 1 + constrain v150 == u64 1 + v153 = allocate + store u64 0 at v153 + v154 = load v153 + v156 = or v154, u64 2⁴ + store v156 at v153 + v157 = load v153 + v158 = eq v157, u64 2⁴ + constrain v157 == u64 2⁴ + v160 = allocate + store u64 0 at v160 + v161 = load v160 + v220 = or v161, u64 1 + store v220 at v160 + v221 = load v160 + v222 = eq v221, u64 1 + constrain v221 == u64 1 + v225 = allocate + store u64 0 at v225 + v226 = load v225 + v228 = or v226, u64 2⁴ + store v228 at v225 + v229 = load v225 + v230 = eq v229, u64 2⁴ + constrain v229 == u64 2⁴ + return + b2(): + jmp b3(u64 0) + b3(v19: u64): + v22 = lt v19, u64 2 + jmpif v22 then: b4, else: b5 + b4(): + v29 = truncate v1 to 64 bits, max_bit_size: 254 + v30 = cast v29 as u64 + v32 = sub v30, u64 1 + range_check v32 to 64 bits + v33 = lt v19, v32 + jmpif v33 then: b7, else: b8 + b7(): + v36 = add v19, u64 1 + range_check v36 to 64 bits + v37 = array_get v0, index v36 + v38 = load v11 + v39 = mul u64 2, v19 + range_check v39 to 64 bits + v40 = div v37, Field 2⁴ + v41 = cast v37 as u4 + v42 = array_set v38, index v39, value v41 + v43 = add v39, Field 1 + store v42 at v11 + v44 = load v11 + v45 = mul u64 2, v19 + range_check v45 to 64 bits + v46 = add v45, u64 1 + range_check v46 to 64 bits + v48 = and v37, u8 15 + v49 = truncate v48 to 4 bits, max_bit_size: 8 + v50 = cast v49 as u4 + v51 = array_set v44, index v46, value v50 + v52 = add v46, Field 1 + store v51 at v11 + jmp b8() + b8(): + v35 = add v19, Field 1 + jmp b3(v35) + b5(): + jmp b6() +} + +After Mem2Reg: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v251 = truncate v1 to 64 bits, max_bit_size: 254 + v252 = cast v251 as u64 + inc_rc v0 + v253 = lt u64 5, v252 + v254 = not v253 + constrain v253 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v256 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 + v258 = array_get v0, index Field 0 + v259 = div v258, Field 2⁴ + v260 = cast v258 as u4 + v261 = truncate v260 to 1 bits, max_bit_size: 4 + v262 = cast v261 as u1 + jmpif v262 then: b1, else: b2 + b1(): + v286 = array_get v0, index Field 0 + v287 = and v286, u8 15 + v288 = truncate v287 to 4 bits, max_bit_size: 8 + v289 = cast v288 as u4 + store [v289, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 + inc_rc v0 + jmp b9(Field 1) + b9(v59: Field): + v293 = lt v59, Field 5 + jmpif v293 then: b10, else: b11 + b10(): + v359 = truncate v59 to 64 bits, max_bit_size: 254 + v360 = cast v359 as u64 + v361 = truncate v1 to 64 bits, max_bit_size: 254 + v362 = cast v361 as u64 + v363 = lt v360, v362 + jmpif v363 then: b12, else: b13 + b12(): + v364 = array_get v0, index v59 + v365 = load v256 + v366 = mul Field 2, v59 + v367 = sub v366, Field 1 + v368 = div v364, Field 2⁴ + v369 = cast v364 as u4 + v370 = array_set v365, index v367, value v369 + v371 = add v367, Field 1 + v373 = mul Field 2, v59 + v374 = and v364, u8 15 + v375 = truncate v374 to 4 bits, max_bit_size: 8 + v376 = cast v375 as u4 + v377 = array_set v370, index v373, value v376 + v378 = add v373, Field 1 + store v377 at v256 + jmp b13() + b13(): + v379 = add v59, Field 1 + jmp b9(v379) + b11(): + jmp b6() + b6(): + v294 = load v256 + v295 = mul Field 2, v1 + v296 = cast v262 as Field + v297 = add v295, v296 + v298 = sub v297, Field 2 + inc_rc v294 + inc_rc v294 + inc_rc v294 + v299 = eq v298, Field 5 + constrain v298 == Field 5 + v300 = array_get v294, index Field 0 + v301 = array_get v294, index Field 1 + v302 = array_get v294, index Field 2 + v303 = array_get v294, index Field 3 + v304 = array_get v294, index Field 4 + v305 = allocate + store u1 1 at v305 + jmp b14(Field 0) + b14(v93: Field): + v306 = lt v93, Field 5 + jmpif v306 then: b15, else: b16 + b15(): + v352 = array_get [v300, v301, v302, v303, v304], index v93 + v354 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v93 + v355 = eq v352, v354 + v356 = load v305 + v357 = mul v356, v355 + store v357 at v305 + v358 = add v93, Field 1 + jmp b14(v358) + b16(): + v307 = load v305 + constrain v307 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v312 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 + jmp b17() + b17(): + jmp b18() + b18(): + range_check u8 148 to 8 bits + store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + jmp b19(Field 1) + b19(v126: Field): + v319 = lt v126, Field 2⁵ + jmpif v319 then: b20, else: b21 + b20(): + v344 = load v312 + v345 = sub v126, Field 1 + v347 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v345 + v348 = array_set v344, index v126, value v347 + v349 = add v126, Field 1 + store v348 at v312 + v350 = add v126, Field 1 + jmp b19(v350) + b21(): + v320 = load v312 + inc_rc v320 + jmp b22(v320, Field 21) + b22(v131: [u8; 32], v132: Field): + jmp b23(v131, v132) + b23(v133: [u8; 32], v134: Field): + inc_rc v133 + v321 = allocate + store u1 1 at v321 + jmp b24(Field 0) + b24(v142: Field): + v322 = lt v142, Field 2⁵ + jmpif v322 then: b25, else: b26 + b25(): + v337 = array_get v133, index v142 + v339 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v142 + v340 = eq v337, v339 + v341 = load v321 + v342 = mul v341, v340 + store v342 at v321 + v343 = add v142, Field 1 + jmp b24(v343) + b26(): + v323 = load v321 + constrain v323 == u1 1 + v324 = eq v134, Field 21 + constrain v134 == Field 21 + v325 = allocate + store u64 1 at v325 + v328 = allocate + store u64 2⁴ at v328 + v331 = allocate + store u64 1 at v331 + v334 = allocate + store u64 2⁴ at v334 + return + b2(): + jmp b3(u64 0) + b3(v19: u64): + v263 = lt v19, u64 2 + jmpif v263 then: b4, else: b5 + b4(): + v264 = truncate v1 to 64 bits, max_bit_size: 254 + v265 = cast v264 as u64 + v266 = sub v265, u64 1 + range_check v266 to 64 bits + v267 = lt v19, v266 + jmpif v267 then: b7, else: b8 + b7(): + v268 = add v19, u64 1 + range_check v268 to 64 bits + v269 = array_get v0, index v268 + v270 = load v256 + v271 = mul u64 2, v19 + range_check v271 to 64 bits + v272 = div v269, Field 2⁴ + v273 = cast v269 as u4 + v274 = array_set v270, index v271, value v273 + v275 = add v271, Field 1 + v277 = mul u64 2, v19 + range_check v277 to 64 bits + v278 = add v277, u64 1 + range_check v278 to 64 bits + v279 = and v269, u8 15 + v280 = truncate v279 to 4 bits, max_bit_size: 8 + v281 = cast v280 as u4 + v282 = array_set v274, index v278, value v281 + v283 = add v278, Field 1 + store v282 at v256 + jmp b8() + b8(): + v284 = add v19, Field 1 + jmp b3(v284) + b5(): + jmp b6() +} + +After Assert Constant: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v251 = truncate v1 to 64 bits, max_bit_size: 254 + v252 = cast v251 as u64 + inc_rc v0 + v253 = lt u64 5, v252 + v254 = not v253 + constrain v253 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v256 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 + v258 = array_get v0, index Field 0 + v259 = div v258, Field 2⁴ + v260 = cast v258 as u4 + v261 = truncate v260 to 1 bits, max_bit_size: 4 + v262 = cast v261 as u1 + jmpif v262 then: b1, else: b2 + b1(): + v286 = array_get v0, index Field 0 + v287 = and v286, u8 15 + v288 = truncate v287 to 4 bits, max_bit_size: 8 + v289 = cast v288 as u4 + store [v289, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 + inc_rc v0 + jmp b9(Field 1) + b9(v59: Field): + v293 = lt v59, Field 5 + jmpif v293 then: b10, else: b11 + b10(): + v359 = truncate v59 to 64 bits, max_bit_size: 254 + v360 = cast v359 as u64 + v361 = truncate v1 to 64 bits, max_bit_size: 254 + v362 = cast v361 as u64 + v363 = lt v360, v362 + jmpif v363 then: b12, else: b13 + b12(): + v364 = array_get v0, index v59 + v365 = load v256 + v366 = mul Field 2, v59 + v367 = sub v366, Field 1 + v368 = div v364, Field 2⁴ + v369 = cast v364 as u4 + v370 = array_set v365, index v367, value v369 + v371 = add v367, Field 1 + v373 = mul Field 2, v59 + v374 = and v364, u8 15 + v375 = truncate v374 to 4 bits, max_bit_size: 8 + v376 = cast v375 as u4 + v377 = array_set v370, index v373, value v376 + v378 = add v373, Field 1 + store v377 at v256 + jmp b13() + b13(): + v379 = add v59, Field 1 + jmp b9(v379) + b11(): + jmp b6() + b6(): + v294 = load v256 + v295 = mul Field 2, v1 + v296 = cast v262 as Field + v297 = add v295, v296 + v298 = sub v297, Field 2 + inc_rc v294 + inc_rc v294 + inc_rc v294 + v299 = eq v298, Field 5 + constrain v298 == Field 5 + v300 = array_get v294, index Field 0 + v301 = array_get v294, index Field 1 + v302 = array_get v294, index Field 2 + v303 = array_get v294, index Field 3 + v304 = array_get v294, index Field 4 + v305 = allocate + store u1 1 at v305 + jmp b14(Field 0) + b14(v93: Field): + v306 = lt v93, Field 5 + jmpif v306 then: b15, else: b16 + b15(): + v352 = array_get [v300, v301, v302, v303, v304], index v93 + v354 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v93 + v355 = eq v352, v354 + v356 = load v305 + v357 = mul v356, v355 + store v357 at v305 + v358 = add v93, Field 1 + jmp b14(v358) + b16(): + v307 = load v305 + constrain v307 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v312 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 + jmp b17() + b17(): + jmp b18() + b18(): + range_check u8 148 to 8 bits + store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + jmp b19(Field 1) + b19(v126: Field): + v319 = lt v126, Field 2⁵ + jmpif v319 then: b20, else: b21 + b20(): + v344 = load v312 + v345 = sub v126, Field 1 + v347 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v345 + v348 = array_set v344, index v126, value v347 + v349 = add v126, Field 1 + store v348 at v312 + v350 = add v126, Field 1 + jmp b19(v350) + b21(): + v320 = load v312 + inc_rc v320 + jmp b22(v320, Field 21) + b22(v131: [u8; 32], v132: Field): + jmp b23(v131, v132) + b23(v133: [u8; 32], v134: Field): + inc_rc v133 + v321 = allocate + store u1 1 at v321 + jmp b24(Field 0) + b24(v142: Field): + v322 = lt v142, Field 2⁵ + jmpif v322 then: b25, else: b26 + b25(): + v337 = array_get v133, index v142 + v339 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v142 + v340 = eq v337, v339 + v341 = load v321 + v342 = mul v341, v340 + store v342 at v321 + v343 = add v142, Field 1 + jmp b24(v343) + b26(): + v323 = load v321 + constrain v323 == u1 1 + v324 = eq v134, Field 21 + constrain v134 == Field 21 + v325 = allocate + store u64 1 at v325 + v328 = allocate + store u64 2⁴ at v328 + v331 = allocate + store u64 1 at v331 + v334 = allocate + store u64 2⁴ at v334 + return + b2(): + jmp b3(u64 0) + b3(v19: u64): + v263 = lt v19, u64 2 + jmpif v263 then: b4, else: b5 + b4(): + v264 = truncate v1 to 64 bits, max_bit_size: 254 + v265 = cast v264 as u64 + v266 = sub v265, u64 1 + range_check v266 to 64 bits + v267 = lt v19, v266 + jmpif v267 then: b7, else: b8 + b7(): + v268 = add v19, u64 1 + range_check v268 to 64 bits + v269 = array_get v0, index v268 + v270 = load v256 + v271 = mul u64 2, v19 + range_check v271 to 64 bits + v272 = div v269, Field 2⁴ + v273 = cast v269 as u4 + v274 = array_set v270, index v271, value v273 + v275 = add v271, Field 1 + v277 = mul u64 2, v19 + range_check v277 to 64 bits + v278 = add v277, u64 1 + range_check v278 to 64 bits + v279 = and v269, u8 15 + v280 = truncate v279 to 4 bits, max_bit_size: 8 + v281 = cast v280 as u4 + v282 = array_set v274, index v278, value v281 + v283 = add v278, Field 1 + store v282 at v256 + jmp b8() + b8(): + v284 = add v19, Field 1 + jmp b3(v284) + b5(): + jmp b6() +} + +After Unrolling: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v251 = truncate v1 to 64 bits, max_bit_size: 254 + v252 = cast v251 as u64 + inc_rc v0 + v253 = lt u64 5, v252 + v254 = not v253 + constrain v253 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v256 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 + v258 = array_get v0, index Field 0 + v259 = div v258, Field 2⁴ + v260 = cast v258 as u4 + v261 = truncate v260 to 1 bits, max_bit_size: 4 + v262 = cast v261 as u1 + jmpif v262 then: b1, else: b2 + b1(): + v286 = array_get v0, index Field 0 + v287 = and v286, u8 15 + v288 = truncate v287 to 4 bits, max_bit_size: 8 + v289 = cast v288 as u4 + store [v289, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 + inc_rc v0 + v381 = truncate v1 to 64 bits, max_bit_size: 254 + v382 = cast v381 as u64 + v383 = lt u64 1, v382 + jmpif v383 then: b29, else: b30 + b29(): + v385 = array_get v0, index Field 1 + v386 = load v256 + v387 = div v385, Field 2⁴ + v388 = cast v385 as u4 + v389 = array_set v386, index Field 1, value v388 + v390 = and v385, u8 15 + v391 = truncate v390 to 4 bits, max_bit_size: 8 + v392 = cast v391 as u4 + v393 = array_set v389, index Field 2, value v392 + store v393 at v256 + jmp b30() + b30(): + v394 = truncate v1 to 64 bits, max_bit_size: 254 + v395 = cast v394 as u64 + v396 = lt u64 2, v395 + jmpif v396 then: b34, else: b35 + b34(): + v398 = array_get v0, index Field 2 + v399 = load v256 + v400 = div v398, Field 2⁴ + v401 = cast v398 as u4 + v402 = array_set v399, index Field 3, value v401 + v403 = and v398, u8 15 + v404 = truncate v403 to 4 bits, max_bit_size: 8 + v405 = cast v404 as u4 + v406 = array_set v402, index Field 4, value v405 + store v406 at v256 + jmp b35() + b35(): + v408 = truncate v1 to 64 bits, max_bit_size: 254 + v409 = cast v408 as u64 + v410 = lt u64 3, v409 + jmpif v410 then: b39, else: b40 + b39(): + v412 = array_get v0, index Field 3 + v413 = load v256 + v414 = div v412, Field 2⁴ + v415 = cast v412 as u4 + v416 = array_set v413, index Field 5, value v415 + v417 = and v412, u8 15 + v418 = truncate v417 to 4 bits, max_bit_size: 8 + v419 = cast v418 as u4 + v420 = array_set v416, index Field 6, value v419 + store v420 at v256 + jmp b40() + b40(): + v421 = truncate v1 to 64 bits, max_bit_size: 254 + v422 = cast v421 as u64 + v423 = lt u64 4, v422 + jmpif v423 then: b44, else: b45 + b44(): + v425 = array_get v0, index Field 4 + v426 = load v256 + v427 = div v425, Field 2⁴ + v428 = cast v425 as u4 + v429 = array_set v426, index Field 7, value v428 + v430 = and v425, u8 15 + v431 = truncate v430 to 4 bits, max_bit_size: 8 + v432 = cast v431 as u4 + v433 = array_set v429, index Field 8, value v432 + store v433 at v256 + jmp b45() + b45(): + jmp b11() + b11(): + jmp b6() + b6(): + v294 = load v256 + v295 = mul Field 2, v1 + v296 = cast v262 as Field + v297 = add v295, v296 + v298 = sub v297, Field 2 + inc_rc v294 + inc_rc v294 + inc_rc v294 + v299 = eq v298, Field 5 + constrain v298 == Field 5 + v300 = array_get v294, index Field 0 + v301 = array_get v294, index Field 1 + v302 = array_get v294, index Field 2 + v303 = array_get v294, index Field 3 + v304 = array_get v294, index Field 4 + v305 = allocate + store u1 1 at v305 + v780 = eq v300, u4 15 + v781 = load v305 + v782 = mul v781, v780 + store v782 at v305 + v786 = eq v301, u4 1 + v787 = load v305 + v788 = mul v787, v786 + store v788 at v305 + v792 = eq v302, u4 12 + v793 = load v305 + v794 = mul v793, v792 + store v794 at v305 + v798 = eq v303, u4 11 + v799 = load v305 + v800 = mul v799, v798 + store v800 at v305 + v804 = eq v304, u4 8 + v805 = load v305 + v806 = mul v805, v804 + store v806 at v305 + jmp b16() + b16(): + v307 = load v305 + constrain v307 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v312 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 + jmp b17() + b17(): + jmp b18() + b18(): + range_check u8 148 to 8 bits + store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v654 = load v312 + v656 = array_set v654, index Field 1, value u8 184 + store v656 at v312 + v658 = load v312 + v660 = array_set v658, index Field 2, value u8 143 + store v660 at v312 + v662 = load v312 + v664 = array_set v662, index Field 3, value u8 97 + store v664 at v312 + v666 = load v312 + v668 = array_set v666, index Field 4, value u8 230 + store v668 at v312 + v670 = load v312 + v672 = array_set v670, index Field 5, value u8 251 + store v672 at v312 + v674 = load v312 + v676 = array_set v674, index Field 6, value u8 218 + store v676 at v312 + v678 = load v312 + v680 = array_set v678, index Field 7, value u8 131 + store v680 at v312 + v682 = load v312 + v684 = array_set v682, index Field 8, value u8 251 + store v684 at v312 + v686 = load v312 + v688 = array_set v686, index Field 9, value u8 255 + store v688 at v312 + v690 = load v312 + v692 = array_set v690, index Field 10, value u8 250 + store v692 at v312 + v694 = load v312 + v696 = array_set v694, index Field 11, value u8 190 + store v696 at v312 + v698 = load v312 + v700 = array_set v698, index Field 12, value u8 54 + store v700 at v312 + v702 = load v312 + v704 = array_set v702, index Field 13, value u8 65 + store v704 at v312 + v706 = load v312 + v708 = array_set v706, index Field 14, value u8 18 + store v708 at v312 + v710 = load v312 + v712 = array_set v710, index Field 15, value u8 19 + store v712 at v312 + v714 = load v312 + v716 = array_set v714, index Field 2⁴, value u8 116 + store v716 at v312 + v718 = load v312 + v720 = array_set v718, index Field 17, value u8 2⁷ + store v720 at v312 + v722 = load v312 + v724 = array_set v722, index Field 18, value u8 57 + store v724 at v312 + v726 = load v312 + v728 = array_set v726, index Field 19, value u8 2⁷ + store v728 at v312 + v730 = load v312 + v732 = array_set v730, index Field 20, value u8 24 + store v732 at v312 + v734 = load v312 + v736 = array_set v734, index Field 21, value u8 0 + store v736 at v312 + v738 = load v312 + v740 = array_set v738, index Field 22, value u8 0 + store v740 at v312 + v742 = load v312 + v744 = array_set v742, index Field 23, value u8 0 + store v744 at v312 + v746 = load v312 + v748 = array_set v746, index Field 24, value u8 0 + store v748 at v312 + v750 = load v312 + v752 = array_set v750, index Field 25, value u8 0 + store v752 at v312 + v754 = load v312 + v756 = array_set v754, index Field 26, value u8 0 + store v756 at v312 + v758 = load v312 + v760 = array_set v758, index Field 27, value u8 0 + store v760 at v312 + v762 = load v312 + v764 = array_set v762, index Field 28, value u8 0 + store v764 at v312 + v766 = load v312 + v768 = array_set v766, index Field 29, value u8 0 + store v768 at v312 + v770 = load v312 + v772 = array_set v770, index Field 30, value u8 0 + store v772 at v312 + v774 = load v312 + v776 = array_set v774, index Field 31, value u8 0 + store v776 at v312 + jmp b21() + b21(): + v320 = load v312 + inc_rc v320 + jmp b22(v320, Field 21) + b22(v131: [u8; 32], v132: Field): + jmp b23(v131, v132) + b23(v133: [u8; 32], v134: Field): + inc_rc v133 + v321 = allocate + store u1 1 at v321 + v462 = array_get v133, index Field 0 + v464 = eq v462, u8 148 + v465 = load v321 + v466 = mul v465, v464 + store v466 at v321 + v468 = array_get v133, index Field 1 + v470 = eq v468, u8 184 + v471 = load v321 + v472 = mul v471, v470 + store v472 at v321 + v474 = array_get v133, index Field 2 + v476 = eq v474, u8 143 + v477 = load v321 + v478 = mul v477, v476 + store v478 at v321 + v480 = array_get v133, index Field 3 + v482 = eq v480, u8 97 + v483 = load v321 + v484 = mul v483, v482 + store v484 at v321 + v486 = array_get v133, index Field 4 + v488 = eq v486, u8 230 + v489 = load v321 + v490 = mul v489, v488 + store v490 at v321 + v492 = array_get v133, index Field 5 + v494 = eq v492, u8 251 + v495 = load v321 + v496 = mul v495, v494 + store v496 at v321 + v498 = array_get v133, index Field 6 + v500 = eq v498, u8 218 + v501 = load v321 + v502 = mul v501, v500 + store v502 at v321 + v504 = array_get v133, index Field 7 + v506 = eq v504, u8 131 + v507 = load v321 + v508 = mul v507, v506 + store v508 at v321 + v510 = array_get v133, index Field 8 + v512 = eq v510, u8 251 + v513 = load v321 + v514 = mul v513, v512 + store v514 at v321 + v516 = array_get v133, index Field 9 + v518 = eq v516, u8 255 + v519 = load v321 + v520 = mul v519, v518 + store v520 at v321 + v522 = array_get v133, index Field 10 + v524 = eq v522, u8 250 + v525 = load v321 + v526 = mul v525, v524 + store v526 at v321 + v528 = array_get v133, index Field 11 + v530 = eq v528, u8 190 + v531 = load v321 + v532 = mul v531, v530 + store v532 at v321 + v534 = array_get v133, index Field 12 + v536 = eq v534, u8 54 + v537 = load v321 + v538 = mul v537, v536 + store v538 at v321 + v540 = array_get v133, index Field 13 + v542 = eq v540, u8 65 + v543 = load v321 + v544 = mul v543, v542 + store v544 at v321 + v546 = array_get v133, index Field 14 + v548 = eq v546, u8 18 + v549 = load v321 + v550 = mul v549, v548 + store v550 at v321 + v552 = array_get v133, index Field 15 + v554 = eq v552, u8 19 + v555 = load v321 + v556 = mul v555, v554 + store v556 at v321 + v558 = array_get v133, index Field 2⁴ + v560 = eq v558, u8 116 + v561 = load v321 + v562 = mul v561, v560 + store v562 at v321 + v564 = array_get v133, index Field 17 + v566 = eq v564, u8 2⁷ + v567 = load v321 + v568 = mul v567, v566 + store v568 at v321 + v570 = array_get v133, index Field 18 + v572 = eq v570, u8 57 + v573 = load v321 + v574 = mul v573, v572 + store v574 at v321 + v576 = array_get v133, index Field 19 + v578 = eq v576, u8 2⁷ + v579 = load v321 + v580 = mul v579, v578 + store v580 at v321 + v582 = array_get v133, index Field 20 + v584 = eq v582, u8 24 + v585 = load v321 + v586 = mul v585, v584 + store v586 at v321 + v588 = array_get v133, index Field 21 + v590 = eq v588, u8 0 + v591 = load v321 + v592 = mul v591, v590 + store v592 at v321 + v594 = array_get v133, index Field 22 + v596 = eq v594, u8 0 + v597 = load v321 + v598 = mul v597, v596 + store v598 at v321 + v600 = array_get v133, index Field 23 + v602 = eq v600, u8 0 + v603 = load v321 + v604 = mul v603, v602 + store v604 at v321 + v606 = array_get v133, index Field 24 + v608 = eq v606, u8 0 + v609 = load v321 + v610 = mul v609, v608 + store v610 at v321 + v612 = array_get v133, index Field 25 + v614 = eq v612, u8 0 + v615 = load v321 + v616 = mul v615, v614 + store v616 at v321 + v618 = array_get v133, index Field 26 + v620 = eq v618, u8 0 + v621 = load v321 + v622 = mul v621, v620 + store v622 at v321 + v624 = array_get v133, index Field 27 + v626 = eq v624, u8 0 + v627 = load v321 + v628 = mul v627, v626 + store v628 at v321 + v630 = array_get v133, index Field 28 + v632 = eq v630, u8 0 + v633 = load v321 + v634 = mul v633, v632 + store v634 at v321 + v636 = array_get v133, index Field 29 + v638 = eq v636, u8 0 + v639 = load v321 + v640 = mul v639, v638 + store v640 at v321 + v642 = array_get v133, index Field 30 + v644 = eq v642, u8 0 + v645 = load v321 + v646 = mul v645, v644 + store v646 at v321 + v648 = array_get v133, index Field 31 + v650 = eq v648, u8 0 + v651 = load v321 + v652 = mul v651, v650 + store v652 at v321 + jmp b26() + b26(): + v323 = load v321 + constrain v323 == u1 1 + v324 = eq v134, Field 21 + constrain v134 == Field 21 + v325 = allocate + store u64 1 at v325 + v328 = allocate + store u64 2⁴ at v328 + v331 = allocate + store u64 1 at v331 + v334 = allocate + store u64 2⁴ at v334 + return + b2(): + v434 = truncate v1 to 64 bits, max_bit_size: 254 + v435 = cast v434 as u64 + v436 = sub v435, u64 1 + range_check v436 to 64 bits + v437 = lt u64 0, v436 + jmpif v437 then: b51, else: b52 + b51(): + v439 = array_get v0, index u64 1 + v440 = load v256 + v441 = div v439, Field 2⁴ + v442 = cast v439 as u4 + v443 = array_set v440, index u64 0, value v442 + v444 = and v439, u8 15 + v445 = truncate v444 to 4 bits, max_bit_size: 8 + v446 = cast v445 as u4 + v447 = array_set v443, index u64 1, value v446 + store v447 at v256 + jmp b52() + b52(): + v448 = truncate v1 to 64 bits, max_bit_size: 254 + v449 = cast v448 as u64 + v450 = sub v449, u64 1 + range_check v450 to 64 bits + v451 = lt u64 1, v450 + jmpif v451 then: b56, else: b57 + b56(): + v453 = array_get v0, index u64 2 + v454 = load v256 + v455 = div v453, Field 2⁴ + v456 = cast v453 as u4 + v457 = array_set v454, index u64 2, value v456 + v458 = and v453, u8 15 + v459 = truncate v458 to 4 bits, max_bit_size: 8 + v460 = cast v459 as u4 + v461 = array_set v457, index u64 3, value v460 + store v461 at v256 + jmp b57() + b57(): + jmp b5() + b5(): + jmp b6() +} + +After Simplifying: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v251 = truncate v1 to 64 bits, max_bit_size: 254 + v252 = cast v251 as u64 + inc_rc v0 + v253 = lt u64 5, v252 + v254 = not v253 + constrain v253 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v256 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 + v258 = array_get v0, index Field 0 + v259 = div v258, Field 2⁴ + v260 = cast v258 as u4 + v261 = truncate v260 to 1 bits, max_bit_size: 4 + v262 = cast v261 as u1 + jmpif v262 then: b1, else: b2 + b1(): + v286 = array_get v0, index Field 0 + v287 = and v286, u8 15 + v288 = truncate v287 to 4 bits, max_bit_size: 8 + v289 = cast v288 as u4 + store [v289, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 + inc_rc v0 + v381 = truncate v1 to 64 bits, max_bit_size: 254 + v382 = cast v381 as u64 + v383 = lt u64 1, v382 + jmpif v383 then: b29, else: b30 + b29(): + v385 = array_get v0, index Field 1 + v386 = load v256 + v387 = div v385, Field 2⁴ + v388 = cast v385 as u4 + v389 = array_set v386, index Field 1, value v388 + v390 = and v385, u8 15 + v391 = truncate v390 to 4 bits, max_bit_size: 8 + v392 = cast v391 as u4 + v393 = array_set v389, index Field 2, value v392 + store v393 at v256 + jmp b30() + b30(): + v394 = truncate v1 to 64 bits, max_bit_size: 254 + v395 = cast v394 as u64 + v396 = lt u64 2, v395 + jmpif v396 then: b34, else: b35 + b34(): + v398 = array_get v0, index Field 2 + v399 = load v256 + v400 = div v398, Field 2⁴ + v401 = cast v398 as u4 + v402 = array_set v399, index Field 3, value v401 + v403 = and v398, u8 15 + v404 = truncate v403 to 4 bits, max_bit_size: 8 + v405 = cast v404 as u4 + v406 = array_set v402, index Field 4, value v405 + store v406 at v256 + jmp b35() + b35(): + v408 = truncate v1 to 64 bits, max_bit_size: 254 + v409 = cast v408 as u64 + v410 = lt u64 3, v409 + jmpif v410 then: b39, else: b40 + b39(): + v412 = array_get v0, index Field 3 + v413 = load v256 + v414 = div v412, Field 2⁴ + v415 = cast v412 as u4 + v416 = array_set v413, index Field 5, value v415 + v417 = and v412, u8 15 + v418 = truncate v417 to 4 bits, max_bit_size: 8 + v419 = cast v418 as u4 + v420 = array_set v416, index Field 6, value v419 + store v420 at v256 + jmp b40() + b40(): + v421 = truncate v1 to 64 bits, max_bit_size: 254 + v422 = cast v421 as u64 + v423 = lt u64 4, v422 + jmpif v423 then: b44, else: b45 + b44(): + v425 = array_get v0, index Field 4 + v426 = load v256 + v427 = div v425, Field 2⁴ + v428 = cast v425 as u4 + v429 = array_set v426, index Field 7, value v428 + v430 = and v425, u8 15 + v431 = truncate v430 to 4 bits, max_bit_size: 8 + v432 = cast v431 as u4 + v433 = array_set v429, index Field 8, value v432 + store v433 at v256 + jmp b45() + b45(): + jmp b6() + b6(): + v294 = load v256 + v295 = mul Field 2, v1 + v296 = cast v262 as Field + v297 = add v295, v296 + v298 = sub v297, Field 2 + inc_rc v294 + inc_rc v294 + inc_rc v294 + v299 = eq v298, Field 5 + constrain v298 == Field 5 + v300 = array_get v294, index Field 0 + v301 = array_get v294, index Field 1 + v302 = array_get v294, index Field 2 + v303 = array_get v294, index Field 3 + v304 = array_get v294, index Field 4 + v305 = allocate + store u1 1 at v305 + v780 = eq v300, u4 15 + v781 = load v305 + v782 = mul v781, v780 + store v782 at v305 + v786 = eq v301, u4 1 + v787 = load v305 + v788 = mul v787, v786 + store v788 at v305 + v792 = eq v302, u4 12 + v793 = load v305 + v794 = mul v793, v792 + store v794 at v305 + v798 = eq v303, u4 11 + v799 = load v305 + v800 = mul v799, v798 + store v800 at v305 + v804 = eq v304, u4 8 + v805 = load v305 + v806 = mul v805, v804 + store v806 at v305 + v307 = load v305 + constrain v307 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v312 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 + range_check u8 148 to 8 bits + store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v654 = load v312 + v656 = array_set v654, index Field 1, value u8 184 + store v656 at v312 + v658 = load v312 + v660 = array_set v658, index Field 2, value u8 143 + store v660 at v312 + v662 = load v312 + v664 = array_set v662, index Field 3, value u8 97 + store v664 at v312 + v666 = load v312 + v668 = array_set v666, index Field 4, value u8 230 + store v668 at v312 + v670 = load v312 + v672 = array_set v670, index Field 5, value u8 251 + store v672 at v312 + v674 = load v312 + v676 = array_set v674, index Field 6, value u8 218 + store v676 at v312 + v678 = load v312 + v680 = array_set v678, index Field 7, value u8 131 + store v680 at v312 + v682 = load v312 + v684 = array_set v682, index Field 8, value u8 251 + store v684 at v312 + v686 = load v312 + v688 = array_set v686, index Field 9, value u8 255 + store v688 at v312 + v690 = load v312 + v692 = array_set v690, index Field 10, value u8 250 + store v692 at v312 + v694 = load v312 + v696 = array_set v694, index Field 11, value u8 190 + store v696 at v312 + v698 = load v312 + v700 = array_set v698, index Field 12, value u8 54 + store v700 at v312 + v702 = load v312 + v704 = array_set v702, index Field 13, value u8 65 + store v704 at v312 + v706 = load v312 + v708 = array_set v706, index Field 14, value u8 18 + store v708 at v312 + v710 = load v312 + v712 = array_set v710, index Field 15, value u8 19 + store v712 at v312 + v714 = load v312 + v716 = array_set v714, index Field 2⁴, value u8 116 + store v716 at v312 + v718 = load v312 + v720 = array_set v718, index Field 17, value u8 2⁷ + store v720 at v312 + v722 = load v312 + v724 = array_set v722, index Field 18, value u8 57 + store v724 at v312 + v726 = load v312 + v728 = array_set v726, index Field 19, value u8 2⁷ + store v728 at v312 + v730 = load v312 + v732 = array_set v730, index Field 20, value u8 24 + store v732 at v312 + v734 = load v312 + v736 = array_set v734, index Field 21, value u8 0 + store v736 at v312 + v738 = load v312 + v740 = array_set v738, index Field 22, value u8 0 + store v740 at v312 + v742 = load v312 + v744 = array_set v742, index Field 23, value u8 0 + store v744 at v312 + v746 = load v312 + v748 = array_set v746, index Field 24, value u8 0 + store v748 at v312 + v750 = load v312 + v752 = array_set v750, index Field 25, value u8 0 + store v752 at v312 + v754 = load v312 + v756 = array_set v754, index Field 26, value u8 0 + store v756 at v312 + v758 = load v312 + v760 = array_set v758, index Field 27, value u8 0 + store v760 at v312 + v762 = load v312 + v764 = array_set v762, index Field 28, value u8 0 + store v764 at v312 + v766 = load v312 + v768 = array_set v766, index Field 29, value u8 0 + store v768 at v312 + v770 = load v312 + v772 = array_set v770, index Field 30, value u8 0 + store v772 at v312 + v774 = load v312 + v776 = array_set v774, index Field 31, value u8 0 + store v776 at v312 + v320 = load v312 + inc_rc v320 + inc_rc v320 + v321 = allocate + store u1 1 at v321 + v462 = array_get v320, index Field 0 + v464 = eq v462, u8 148 + v465 = load v321 + v466 = mul v465, v464 + store v466 at v321 + v468 = array_get v320, index Field 1 + v470 = eq v468, u8 184 + v471 = load v321 + v472 = mul v471, v470 + store v472 at v321 + v474 = array_get v320, index Field 2 + v476 = eq v474, u8 143 + v477 = load v321 + v478 = mul v477, v476 + store v478 at v321 + v480 = array_get v320, index Field 3 + v482 = eq v480, u8 97 + v483 = load v321 + v484 = mul v483, v482 + store v484 at v321 + v486 = array_get v320, index Field 4 + v488 = eq v486, u8 230 + v489 = load v321 + v490 = mul v489, v488 + store v490 at v321 + v492 = array_get v320, index Field 5 + v494 = eq v492, u8 251 + v495 = load v321 + v496 = mul v495, v494 + store v496 at v321 + v498 = array_get v320, index Field 6 + v500 = eq v498, u8 218 + v501 = load v321 + v502 = mul v501, v500 + store v502 at v321 + v504 = array_get v320, index Field 7 + v506 = eq v504, u8 131 + v507 = load v321 + v508 = mul v507, v506 + store v508 at v321 + v510 = array_get v320, index Field 8 + v512 = eq v510, u8 251 + v513 = load v321 + v514 = mul v513, v512 + store v514 at v321 + v516 = array_get v320, index Field 9 + v518 = eq v516, u8 255 + v519 = load v321 + v520 = mul v519, v518 + store v520 at v321 + v522 = array_get v320, index Field 10 + v524 = eq v522, u8 250 + v525 = load v321 + v526 = mul v525, v524 + store v526 at v321 + v528 = array_get v320, index Field 11 + v530 = eq v528, u8 190 + v531 = load v321 + v532 = mul v531, v530 + store v532 at v321 + v534 = array_get v320, index Field 12 + v536 = eq v534, u8 54 + v537 = load v321 + v538 = mul v537, v536 + store v538 at v321 + v540 = array_get v320, index Field 13 + v542 = eq v540, u8 65 + v543 = load v321 + v544 = mul v543, v542 + store v544 at v321 + v546 = array_get v320, index Field 14 + v548 = eq v546, u8 18 + v549 = load v321 + v550 = mul v549, v548 + store v550 at v321 + v552 = array_get v320, index Field 15 + v554 = eq v552, u8 19 + v555 = load v321 + v556 = mul v555, v554 + store v556 at v321 + v558 = array_get v320, index Field 2⁴ + v560 = eq v558, u8 116 + v561 = load v321 + v562 = mul v561, v560 + store v562 at v321 + v564 = array_get v320, index Field 17 + v566 = eq v564, u8 2⁷ + v567 = load v321 + v568 = mul v567, v566 + store v568 at v321 + v570 = array_get v320, index Field 18 + v572 = eq v570, u8 57 + v573 = load v321 + v574 = mul v573, v572 + store v574 at v321 + v576 = array_get v320, index Field 19 + v578 = eq v576, u8 2⁷ + v579 = load v321 + v580 = mul v579, v578 + store v580 at v321 + v582 = array_get v320, index Field 20 + v584 = eq v582, u8 24 + v585 = load v321 + v586 = mul v585, v584 + store v586 at v321 + v588 = array_get v320, index Field 21 + v590 = eq v588, u8 0 + v591 = load v321 + v592 = mul v591, v590 + store v592 at v321 + v594 = array_get v320, index Field 22 + v596 = eq v594, u8 0 + v597 = load v321 + v598 = mul v597, v596 + store v598 at v321 + v600 = array_get v320, index Field 23 + v602 = eq v600, u8 0 + v603 = load v321 + v604 = mul v603, v602 + store v604 at v321 + v606 = array_get v320, index Field 24 + v608 = eq v606, u8 0 + v609 = load v321 + v610 = mul v609, v608 + store v610 at v321 + v612 = array_get v320, index Field 25 + v614 = eq v612, u8 0 + v615 = load v321 + v616 = mul v615, v614 + store v616 at v321 + v618 = array_get v320, index Field 26 + v620 = eq v618, u8 0 + v621 = load v321 + v622 = mul v621, v620 + store v622 at v321 + v624 = array_get v320, index Field 27 + v626 = eq v624, u8 0 + v627 = load v321 + v628 = mul v627, v626 + store v628 at v321 + v630 = array_get v320, index Field 28 + v632 = eq v630, u8 0 + v633 = load v321 + v634 = mul v633, v632 + store v634 at v321 + v636 = array_get v320, index Field 29 + v638 = eq v636, u8 0 + v639 = load v321 + v640 = mul v639, v638 + store v640 at v321 + v642 = array_get v320, index Field 30 + v644 = eq v642, u8 0 + v645 = load v321 + v646 = mul v645, v644 + store v646 at v321 + v648 = array_get v320, index Field 31 + v650 = eq v648, u8 0 + v651 = load v321 + v652 = mul v651, v650 + store v652 at v321 + v323 = load v321 + constrain v323 == u1 1 + v324 = eq Field 21, Field 21 + constrain Field 21 == Field 21 + v325 = allocate + store u64 1 at v325 + v328 = allocate + store u64 2⁴ at v328 + v331 = allocate + store u64 1 at v331 + v334 = allocate + store u64 2⁴ at v334 + return + b2(): + v434 = truncate v1 to 64 bits, max_bit_size: 254 + v435 = cast v434 as u64 + v436 = sub v435, u64 1 + range_check v436 to 64 bits + v437 = lt u64 0, v436 + jmpif v437 then: b51, else: b52 + b51(): + v439 = array_get v0, index u64 1 + v440 = load v256 + v441 = div v439, Field 2⁴ + v442 = cast v439 as u4 + v443 = array_set v440, index u64 0, value v442 + v444 = and v439, u8 15 + v445 = truncate v444 to 4 bits, max_bit_size: 8 + v446 = cast v445 as u4 + v447 = array_set v443, index u64 1, value v446 + store v447 at v256 + jmp b52() + b52(): + v448 = truncate v1 to 64 bits, max_bit_size: 254 + v449 = cast v448 as u64 + v450 = sub v449, u64 1 + range_check v450 to 64 bits + v451 = lt u64 1, v450 + jmpif v451 then: b56, else: b57 + b56(): + v453 = array_get v0, index u64 2 + v454 = load v256 + v455 = div v453, Field 2⁴ + v456 = cast v453 as u4 + v457 = array_set v454, index u64 2, value v456 + v458 = and v453, u8 15 + v459 = truncate v458 to 4 bits, max_bit_size: 8 + v460 = cast v459 as u4 + v461 = array_set v457, index u64 3, value v460 + store v461 at v256 + jmp b57() + b57(): + jmp b6() +} + +After Mem2Reg: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v808 = truncate v1 to 64 bits, max_bit_size: 254 + v809 = cast v808 as u64 + inc_rc v0 + v810 = lt u64 5, v809 + v811 = not v810 + constrain v810 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v813 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 + v815 = array_get v0, index Field 0 + v816 = div v815, Field 2⁴ + v817 = cast v815 as u4 + v818 = truncate v817 to 1 bits, max_bit_size: 4 + v819 = cast v818 as u1 + jmpif v819 then: b1, else: b2 + b1(): + v849 = array_get v0, index Field 0 + v850 = and v849, u8 15 + v851 = truncate v850 to 4 bits, max_bit_size: 8 + v852 = cast v851 as u4 + store [v852, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 + inc_rc v0 + v854 = truncate v1 to 64 bits, max_bit_size: 254 + v855 = cast v854 as u64 + v856 = lt u64 1, v855 + jmpif v856 then: b29, else: b30 + b29(): + v857 = array_get v0, index Field 1 + v859 = div v857, Field 2⁴ + v860 = cast v857 as u4 + v863 = and v857, u8 15 + v864 = truncate v863 to 4 bits, max_bit_size: 8 + v865 = cast v864 as u4 + store [v852, v860, v865, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 + jmp b30() + b30(): + v869 = truncate v1 to 64 bits, max_bit_size: 254 + v870 = cast v869 as u64 + v871 = lt u64 2, v870 + jmpif v871 then: b34, else: b35 + b34(): + v872 = array_get v0, index Field 2 + v873 = load v813 + v874 = div v872, Field 2⁴ + v875 = cast v872 as u4 + v876 = array_set v873, index Field 3, value v875 + v877 = and v872, u8 15 + v878 = truncate v877 to 4 bits, max_bit_size: 8 + v879 = cast v878 as u4 + v880 = array_set v876, index Field 4, value v879 + store v880 at v813 + jmp b35() + b35(): + v881 = truncate v1 to 64 bits, max_bit_size: 254 + v882 = cast v881 as u64 + v883 = lt u64 3, v882 + jmpif v883 then: b39, else: b40 + b39(): + v884 = array_get v0, index Field 3 + v885 = load v813 + v886 = div v884, Field 2⁴ + v887 = cast v884 as u4 + v888 = array_set v885, index Field 5, value v887 + v889 = and v884, u8 15 + v890 = truncate v889 to 4 bits, max_bit_size: 8 + v891 = cast v890 as u4 + v892 = array_set v888, index Field 6, value v891 + store v892 at v813 + jmp b40() + b40(): + v893 = truncate v1 to 64 bits, max_bit_size: 254 + v894 = cast v893 as u64 + v895 = lt u64 4, v894 + jmpif v895 then: b44, else: b45 + b44(): + v896 = array_get v0, index Field 4 + v897 = load v813 + v898 = div v896, Field 2⁴ + v899 = cast v896 as u4 + v900 = array_set v897, index Field 7, value v899 + v901 = and v896, u8 15 + v902 = truncate v901 to 4 bits, max_bit_size: 8 + v903 = cast v902 as u4 + v904 = array_set v900, index Field 8, value v903 + store v904 at v813 + jmp b45() + b45(): + jmp b6() + b6(): + v905 = load v813 + v906 = mul Field 2, v1 + v907 = cast v819 as Field + v908 = add v906, v907 + v909 = sub v908, Field 2 + inc_rc v905 + inc_rc v905 + inc_rc v905 + v910 = eq v909, Field 5 + constrain v909 == Field 5 + v911 = array_get v905, index Field 0 + v912 = array_get v905, index Field 1 + v913 = array_get v905, index Field 2 + v914 = array_get v905, index Field 3 + v915 = array_get v905, index Field 4 + v916 = allocate + v917 = eq v911, u4 15 + v919 = eq v912, u4 1 + v921 = mul v917, v919 + v922 = eq v913, u4 12 + v924 = mul v921, v922 + v925 = eq v914, u4 11 + v927 = mul v924, v925 + v928 = eq v915, u4 8 + v930 = mul v927, v928 + store v930 at v916 + constrain v930 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v936 = allocate + range_check u8 148 to 8 bits + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + store [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v936 + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v1067 = allocate + store u1 1 at v1067 + v1133 = allocate + store u64 1 at v1133 + v1134 = allocate + store u64 2⁴ at v1134 + v1135 = allocate + store u64 1 at v1135 + v1136 = allocate + store u64 2⁴ at v1136 + return + b2(): + v820 = truncate v1 to 64 bits, max_bit_size: 254 + v821 = cast v820 as u64 + v822 = sub v821, u64 1 + range_check v822 to 64 bits + v823 = lt u64 0, v822 + jmpif v823 then: b51, else: b52 + b51(): + v824 = array_get v0, index u64 1 + v826 = div v824, Field 2⁴ + v827 = cast v824 as u4 + v830 = and v824, u8 15 + v831 = truncate v830 to 4 bits, max_bit_size: 8 + v832 = cast v831 as u4 + store [v827, v832, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 + jmp b52() + b52(): + v836 = truncate v1 to 64 bits, max_bit_size: 254 + v837 = cast v836 as u64 + v838 = sub v837, u64 1 + range_check v838 to 64 bits + v839 = lt u64 1, v838 + jmpif v839 then: b56, else: b57 + b56(): + v840 = array_get v0, index u64 2 + v841 = load v813 + v842 = div v840, Field 2⁴ + v843 = cast v840 as u4 + v844 = array_set v841, index u64 2, value v843 + v845 = and v840, u8 15 + v846 = truncate v845 to 4 bits, max_bit_size: 8 + v847 = cast v846 as u4 + v848 = array_set v844, index u64 3, value v847 + store v848 at v813 + jmp b57() + b57(): + jmp b6() +} + +After Flattening: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v808 = truncate v1 to 64 bits, max_bit_size: 254 + v809 = cast v808 as u64 + inc_rc v0 + v810 = lt u64 5, v809 + v811 = not v810 + constrain v810 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v813 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 + v815 = array_get v0, index Field 0 + v816 = div v815, Field 2⁴ + v817 = cast v815 as u4 + v818 = truncate v817 to 1 bits, max_bit_size: 4 + v819 = cast v818 as u1 + enable_side_effects v819 + v1139 = array_get v0, index Field 0 + v1140 = and v1139, u8 15 + v1141 = truncate v1140 to 4 bits, max_bit_size: 8 + v1142 = cast v1141 as u4 + v1144 = load v813 + store [v1142, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 + inc_rc v0 + v1145 = truncate v1 to 64 bits, max_bit_size: 254 + v1146 = cast v1145 as u64 + v1147 = lt u64 1, v1146 + v1149 = mul v819, v1147 + enable_side_effects v1149 + v1150 = array_get v0, index Field 1 + v1151 = div v1150, Field 2⁴ + v1152 = cast v1150 as u4 + v1153 = and v1150, u8 15 + v1154 = truncate v1153 to 4 bits, max_bit_size: 8 + v1155 = cast v1154 as u4 + v1157 = load v813 + store [v1142, v1152, v1155, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 + v1158 = not v1147 + store v1157 at v813 + enable_side_effects v819 + v1159 = array_get v1157, index Field 0 + v1160 = cast v1147 as u4 + v1161 = cast v1158 as u4 + v1162 = mul v1160, v1142 + v1163 = mul v1161, v1159 + v1164 = add v1162, v1163 + v1165 = array_get v1157, index Field 1 + v1166 = cast v1147 as u4 + v1167 = cast v1158 as u4 + v1168 = mul v1166, v1152 + v1169 = mul v1167, v1165 + v1170 = add v1168, v1169 + v1171 = array_get v1157, index Field 2 + v1172 = cast v1147 as u4 + v1173 = cast v1158 as u4 + v1174 = mul v1172, v1155 + v1175 = mul v1173, v1171 + v1176 = add v1174, v1175 + v1177 = array_get v1157, index Field 3 + v1178 = cast v1147 as u4 + v1179 = cast v1158 as u4 + v1180 = mul v1179, v1177 + v1181 = array_get v1157, index Field 4 + v1182 = cast v1147 as u4 + v1183 = cast v1158 as u4 + v1184 = mul v1183, v1181 + v1185 = array_get v1157, index Field 5 + v1186 = cast v1147 as u4 + v1187 = cast v1158 as u4 + v1188 = mul v1187, v1185 + v1189 = array_get v1157, index Field 6 + v1190 = cast v1147 as u4 + v1191 = cast v1158 as u4 + v1192 = mul v1191, v1189 + v1193 = array_get v1157, index Field 7 + v1194 = cast v1147 as u4 + v1195 = cast v1158 as u4 + v1196 = mul v1195, v1193 + v1197 = array_get v1157, index Field 8 + v1198 = cast v1147 as u4 + v1199 = cast v1158 as u4 + v1200 = mul v1199, v1197 + v1201 = array_get v1157, index Field 9 + v1202 = cast v1147 as u4 + v1203 = cast v1158 as u4 + v1204 = mul v1203, v1201 + v1205 = array_get v1157, index Field 10 + v1206 = cast v1147 as u4 + v1207 = cast v1158 as u4 + v1208 = mul v1207, v1205 + v1209 = array_get v1157, index Field 11 + v1210 = cast v1147 as u4 + v1211 = cast v1158 as u4 + v1212 = mul v1211, v1209 + v1213 = array_get v1157, index Field 12 + v1214 = cast v1147 as u4 + v1215 = cast v1158 as u4 + v1216 = mul v1215, v1213 + v1217 = array_get v1157, index Field 13 + v1218 = cast v1147 as u4 + v1219 = cast v1158 as u4 + v1220 = mul v1219, v1217 + v1221 = array_get v1157, index Field 14 + v1222 = cast v1147 as u4 + v1223 = cast v1158 as u4 + v1224 = mul v1223, v1221 + v1225 = array_get v1157, index Field 15 + v1226 = cast v1147 as u4 + v1227 = cast v1158 as u4 + v1228 = mul v1227, v1225 + store [v1164, v1170, v1176, v1180, v1184, v1188, v1192, v1196, v1200, v1204, v1208, v1212, v1216, v1220, v1224, v1228] at v813 + v1230 = truncate v1 to 64 bits, max_bit_size: 254 + v1231 = cast v1230 as u64 + v1232 = lt u64 2, v1231 + v1233 = mul v819, v1232 + enable_side_effects v1233 + v1234 = array_get v0, index Field 2 + v1235 = load v813 + v1236 = div v1234, Field 2⁴ + v1237 = cast v1234 as u4 + v1238 = array_set v1235, index Field 3, value v1237 + v1239 = and v1234, u8 15 + v1240 = truncate v1239 to 4 bits, max_bit_size: 8 + v1241 = cast v1240 as u4 + v1242 = array_set v1238, index Field 4, value v1241 + v1243 = load v813 + store v1242 at v813 + v1244 = not v1232 + store v1243 at v813 + enable_side_effects v819 + v1245 = array_get v1242, index Field 0 + v1246 = array_get v1243, index Field 0 + v1247 = cast v1232 as u4 + v1248 = cast v1244 as u4 + v1249 = mul v1247, v1245 + v1250 = mul v1248, v1246 + v1251 = add v1249, v1250 + v1252 = array_get v1242, index Field 1 + v1253 = array_get v1243, index Field 1 + v1254 = cast v1232 as u4 + v1255 = cast v1244 as u4 + v1256 = mul v1254, v1252 + v1257 = mul v1255, v1253 + v1258 = add v1256, v1257 + v1259 = array_get v1242, index Field 2 + v1260 = array_get v1243, index Field 2 + v1261 = cast v1232 as u4 + v1262 = cast v1244 as u4 + v1263 = mul v1261, v1259 + v1264 = mul v1262, v1260 + v1265 = add v1263, v1264 + v1266 = array_get v1242, index Field 3 + v1267 = array_get v1243, index Field 3 + v1268 = cast v1232 as u4 + v1269 = cast v1244 as u4 + v1270 = mul v1268, v1266 + v1271 = mul v1269, v1267 + v1272 = add v1270, v1271 + v1273 = array_get v1242, index Field 4 + v1274 = array_get v1243, index Field 4 + v1275 = cast v1232 as u4 + v1276 = cast v1244 as u4 + v1277 = mul v1275, v1273 + v1278 = mul v1276, v1274 + v1279 = add v1277, v1278 + v1280 = array_get v1242, index Field 5 + v1281 = array_get v1243, index Field 5 + v1282 = cast v1232 as u4 + v1283 = cast v1244 as u4 + v1284 = mul v1282, v1280 + v1285 = mul v1283, v1281 + v1286 = add v1284, v1285 + v1287 = array_get v1242, index Field 6 + v1288 = array_get v1243, index Field 6 + v1289 = cast v1232 as u4 + v1290 = cast v1244 as u4 + v1291 = mul v1289, v1287 + v1292 = mul v1290, v1288 + v1293 = add v1291, v1292 + v1294 = array_get v1242, index Field 7 + v1295 = array_get v1243, index Field 7 + v1296 = cast v1232 as u4 + v1297 = cast v1244 as u4 + v1298 = mul v1296, v1294 + v1299 = mul v1297, v1295 + v1300 = add v1298, v1299 + v1301 = array_get v1242, index Field 8 + v1302 = array_get v1243, index Field 8 + v1303 = cast v1232 as u4 + v1304 = cast v1244 as u4 + v1305 = mul v1303, v1301 + v1306 = mul v1304, v1302 + v1307 = add v1305, v1306 + v1308 = array_get v1242, index Field 9 + v1309 = array_get v1243, index Field 9 + v1310 = cast v1232 as u4 + v1311 = cast v1244 as u4 + v1312 = mul v1310, v1308 + v1313 = mul v1311, v1309 + v1314 = add v1312, v1313 + v1315 = array_get v1242, index Field 10 + v1316 = array_get v1243, index Field 10 + v1317 = cast v1232 as u4 + v1318 = cast v1244 as u4 + v1319 = mul v1317, v1315 + v1320 = mul v1318, v1316 + v1321 = add v1319, v1320 + v1322 = array_get v1242, index Field 11 + v1323 = array_get v1243, index Field 11 + v1324 = cast v1232 as u4 + v1325 = cast v1244 as u4 + v1326 = mul v1324, v1322 + v1327 = mul v1325, v1323 + v1328 = add v1326, v1327 + v1329 = array_get v1242, index Field 12 + v1330 = array_get v1243, index Field 12 + v1331 = cast v1232 as u4 + v1332 = cast v1244 as u4 + v1333 = mul v1331, v1329 + v1334 = mul v1332, v1330 + v1335 = add v1333, v1334 + v1336 = array_get v1242, index Field 13 + v1337 = array_get v1243, index Field 13 + v1338 = cast v1232 as u4 + v1339 = cast v1244 as u4 + v1340 = mul v1338, v1336 + v1341 = mul v1339, v1337 + v1342 = add v1340, v1341 + v1343 = array_get v1242, index Field 14 + v1344 = array_get v1243, index Field 14 + v1345 = cast v1232 as u4 + v1346 = cast v1244 as u4 + v1347 = mul v1345, v1343 + v1348 = mul v1346, v1344 + v1349 = add v1347, v1348 + v1350 = array_get v1242, index Field 15 + v1351 = array_get v1243, index Field 15 + v1352 = cast v1232 as u4 + v1353 = cast v1244 as u4 + v1354 = mul v1352, v1350 + v1355 = mul v1353, v1351 + v1356 = add v1354, v1355 + store [v1251, v1258, v1265, v1272, v1279, v1286, v1293, v1300, v1307, v1314, v1321, v1328, v1335, v1342, v1349, v1356] at v813 + v1358 = truncate v1 to 64 bits, max_bit_size: 254 + v1359 = cast v1358 as u64 + v1360 = lt u64 3, v1359 + v1361 = mul v819, v1360 + enable_side_effects v1361 + v1362 = array_get v0, index Field 3 + v1363 = load v813 + v1364 = div v1362, Field 2⁴ + v1365 = cast v1362 as u4 + v1366 = array_set v1363, index Field 5, value v1365 + v1367 = and v1362, u8 15 + v1368 = truncate v1367 to 4 bits, max_bit_size: 8 + v1369 = cast v1368 as u4 + v1370 = array_set v1366, index Field 6, value v1369 + v1371 = load v813 + store v1370 at v813 + v1372 = not v1360 + store v1371 at v813 + enable_side_effects v819 + v1373 = array_get v1370, index Field 0 + v1374 = array_get v1371, index Field 0 + v1375 = cast v1360 as u4 + v1376 = cast v1372 as u4 + v1377 = mul v1375, v1373 + v1378 = mul v1376, v1374 + v1379 = add v1377, v1378 + v1380 = array_get v1370, index Field 1 + v1381 = array_get v1371, index Field 1 + v1382 = cast v1360 as u4 + v1383 = cast v1372 as u4 + v1384 = mul v1382, v1380 + v1385 = mul v1383, v1381 + v1386 = add v1384, v1385 + v1387 = array_get v1370, index Field 2 + v1388 = array_get v1371, index Field 2 + v1389 = cast v1360 as u4 + v1390 = cast v1372 as u4 + v1391 = mul v1389, v1387 + v1392 = mul v1390, v1388 + v1393 = add v1391, v1392 + v1394 = array_get v1370, index Field 3 + v1395 = array_get v1371, index Field 3 + v1396 = cast v1360 as u4 + v1397 = cast v1372 as u4 + v1398 = mul v1396, v1394 + v1399 = mul v1397, v1395 + v1400 = add v1398, v1399 + v1401 = array_get v1370, index Field 4 + v1402 = array_get v1371, index Field 4 + v1403 = cast v1360 as u4 + v1404 = cast v1372 as u4 + v1405 = mul v1403, v1401 + v1406 = mul v1404, v1402 + v1407 = add v1405, v1406 + v1408 = array_get v1370, index Field 5 + v1409 = array_get v1371, index Field 5 + v1410 = cast v1360 as u4 + v1411 = cast v1372 as u4 + v1412 = mul v1410, v1408 + v1413 = mul v1411, v1409 + v1414 = add v1412, v1413 + v1415 = array_get v1370, index Field 6 + v1416 = array_get v1371, index Field 6 + v1417 = cast v1360 as u4 + v1418 = cast v1372 as u4 + v1419 = mul v1417, v1415 + v1420 = mul v1418, v1416 + v1421 = add v1419, v1420 + v1422 = array_get v1370, index Field 7 + v1423 = array_get v1371, index Field 7 + v1424 = cast v1360 as u4 + v1425 = cast v1372 as u4 + v1426 = mul v1424, v1422 + v1427 = mul v1425, v1423 + v1428 = add v1426, v1427 + v1429 = array_get v1370, index Field 8 + v1430 = array_get v1371, index Field 8 + v1431 = cast v1360 as u4 + v1432 = cast v1372 as u4 + v1433 = mul v1431, v1429 + v1434 = mul v1432, v1430 + v1435 = add v1433, v1434 + v1436 = array_get v1370, index Field 9 + v1437 = array_get v1371, index Field 9 + v1438 = cast v1360 as u4 + v1439 = cast v1372 as u4 + v1440 = mul v1438, v1436 + v1441 = mul v1439, v1437 + v1442 = add v1440, v1441 + v1443 = array_get v1370, index Field 10 + v1444 = array_get v1371, index Field 10 + v1445 = cast v1360 as u4 + v1446 = cast v1372 as u4 + v1447 = mul v1445, v1443 + v1448 = mul v1446, v1444 + v1449 = add v1447, v1448 + v1450 = array_get v1370, index Field 11 + v1451 = array_get v1371, index Field 11 + v1452 = cast v1360 as u4 + v1453 = cast v1372 as u4 + v1454 = mul v1452, v1450 + v1455 = mul v1453, v1451 + v1456 = add v1454, v1455 + v1457 = array_get v1370, index Field 12 + v1458 = array_get v1371, index Field 12 + v1459 = cast v1360 as u4 + v1460 = cast v1372 as u4 + v1461 = mul v1459, v1457 + v1462 = mul v1460, v1458 + v1463 = add v1461, v1462 + v1464 = array_get v1370, index Field 13 + v1465 = array_get v1371, index Field 13 + v1466 = cast v1360 as u4 + v1467 = cast v1372 as u4 + v1468 = mul v1466, v1464 + v1469 = mul v1467, v1465 + v1470 = add v1468, v1469 + v1471 = array_get v1370, index Field 14 + v1472 = array_get v1371, index Field 14 + v1473 = cast v1360 as u4 + v1474 = cast v1372 as u4 + v1475 = mul v1473, v1471 + v1476 = mul v1474, v1472 + v1477 = add v1475, v1476 + v1478 = array_get v1370, index Field 15 + v1479 = array_get v1371, index Field 15 + v1480 = cast v1360 as u4 + v1481 = cast v1372 as u4 + v1482 = mul v1480, v1478 + v1483 = mul v1481, v1479 + v1484 = add v1482, v1483 + store [v1379, v1386, v1393, v1400, v1407, v1414, v1421, v1428, v1435, v1442, v1449, v1456, v1463, v1470, v1477, v1484] at v813 + v1486 = truncate v1 to 64 bits, max_bit_size: 254 + v1487 = cast v1486 as u64 + v1488 = lt u64 4, v1487 + v1489 = mul v819, v1488 + enable_side_effects v1489 + v1490 = array_get v0, index Field 4 + v1491 = load v813 + v1492 = div v1490, Field 2⁴ + v1493 = cast v1490 as u4 + v1494 = array_set v1491, index Field 7, value v1493 + v1495 = and v1490, u8 15 + v1496 = truncate v1495 to 4 bits, max_bit_size: 8 + v1497 = cast v1496 as u4 + v1498 = array_set v1494, index Field 8, value v1497 + v1499 = load v813 + store v1498 at v813 + v1500 = not v1488 + store v1499 at v813 + enable_side_effects v819 + v1501 = array_get v1498, index Field 0 + v1502 = array_get v1499, index Field 0 + v1503 = cast v1488 as u4 + v1504 = cast v1500 as u4 + v1505 = mul v1503, v1501 + v1506 = mul v1504, v1502 + v1507 = add v1505, v1506 + v1508 = array_get v1498, index Field 1 + v1509 = array_get v1499, index Field 1 + v1510 = cast v1488 as u4 + v1511 = cast v1500 as u4 + v1512 = mul v1510, v1508 + v1513 = mul v1511, v1509 + v1514 = add v1512, v1513 + v1515 = array_get v1498, index Field 2 + v1516 = array_get v1499, index Field 2 + v1517 = cast v1488 as u4 + v1518 = cast v1500 as u4 + v1519 = mul v1517, v1515 + v1520 = mul v1518, v1516 + v1521 = add v1519, v1520 + v1522 = array_get v1498, index Field 3 + v1523 = array_get v1499, index Field 3 + v1524 = cast v1488 as u4 + v1525 = cast v1500 as u4 + v1526 = mul v1524, v1522 + v1527 = mul v1525, v1523 + v1528 = add v1526, v1527 + v1529 = array_get v1498, index Field 4 + v1530 = array_get v1499, index Field 4 + v1531 = cast v1488 as u4 + v1532 = cast v1500 as u4 + v1533 = mul v1531, v1529 + v1534 = mul v1532, v1530 + v1535 = add v1533, v1534 + v1536 = array_get v1498, index Field 5 + v1537 = array_get v1499, index Field 5 + v1538 = cast v1488 as u4 + v1539 = cast v1500 as u4 + v1540 = mul v1538, v1536 + v1541 = mul v1539, v1537 + v1542 = add v1540, v1541 + v1543 = array_get v1498, index Field 6 + v1544 = array_get v1499, index Field 6 + v1545 = cast v1488 as u4 + v1546 = cast v1500 as u4 + v1547 = mul v1545, v1543 + v1548 = mul v1546, v1544 + v1549 = add v1547, v1548 + v1550 = array_get v1498, index Field 7 + v1551 = array_get v1499, index Field 7 + v1552 = cast v1488 as u4 + v1553 = cast v1500 as u4 + v1554 = mul v1552, v1550 + v1555 = mul v1553, v1551 + v1556 = add v1554, v1555 + v1557 = array_get v1498, index Field 8 + v1558 = array_get v1499, index Field 8 + v1559 = cast v1488 as u4 + v1560 = cast v1500 as u4 + v1561 = mul v1559, v1557 + v1562 = mul v1560, v1558 + v1563 = add v1561, v1562 + v1564 = array_get v1498, index Field 9 + v1565 = array_get v1499, index Field 9 + v1566 = cast v1488 as u4 + v1567 = cast v1500 as u4 + v1568 = mul v1566, v1564 + v1569 = mul v1567, v1565 + v1570 = add v1568, v1569 + v1571 = array_get v1498, index Field 10 + v1572 = array_get v1499, index Field 10 + v1573 = cast v1488 as u4 + v1574 = cast v1500 as u4 + v1575 = mul v1573, v1571 + v1576 = mul v1574, v1572 + v1577 = add v1575, v1576 + v1578 = array_get v1498, index Field 11 + v1579 = array_get v1499, index Field 11 + v1580 = cast v1488 as u4 + v1581 = cast v1500 as u4 + v1582 = mul v1580, v1578 + v1583 = mul v1581, v1579 + v1584 = add v1582, v1583 + v1585 = array_get v1498, index Field 12 + v1586 = array_get v1499, index Field 12 + v1587 = cast v1488 as u4 + v1588 = cast v1500 as u4 + v1589 = mul v1587, v1585 + v1590 = mul v1588, v1586 + v1591 = add v1589, v1590 + v1592 = array_get v1498, index Field 13 + v1593 = array_get v1499, index Field 13 + v1594 = cast v1488 as u4 + v1595 = cast v1500 as u4 + v1596 = mul v1594, v1592 + v1597 = mul v1595, v1593 + v1598 = add v1596, v1597 + v1599 = array_get v1498, index Field 14 + v1600 = array_get v1499, index Field 14 + v1601 = cast v1488 as u4 + v1602 = cast v1500 as u4 + v1603 = mul v1601, v1599 + v1604 = mul v1602, v1600 + v1605 = add v1603, v1604 + v1606 = array_get v1498, index Field 15 + v1607 = array_get v1499, index Field 15 + v1608 = cast v1488 as u4 + v1609 = cast v1500 as u4 + v1610 = mul v1608, v1606 + v1611 = mul v1609, v1607 + v1612 = add v1610, v1611 + store [v1507, v1514, v1521, v1528, v1535, v1542, v1549, v1556, v1563, v1570, v1577, v1584, v1591, v1598, v1605, v1612] at v813 + v1614 = not v819 + store v1144 at v813 + enable_side_effects v1614 + v1615 = truncate v1 to 64 bits, max_bit_size: 254 + v1616 = cast v1615 as u64 + v1617 = sub v1616, u64 1 + v1618 = cast v1614 as u64 + v1619 = mul v1617, v1618 + range_check v1619 to 64 bits + v1620 = lt u64 0, v1617 + v1621 = mul v1614, v1620 + enable_side_effects v1621 + v1622 = array_get v0, index u64 1 + v1623 = div v1622, Field 2⁴ + v1624 = cast v1622 as u4 + v1625 = and v1622, u8 15 + v1626 = truncate v1625 to 4 bits, max_bit_size: 8 + v1627 = cast v1626 as u4 + v1629 = load v813 + store [v1624, v1627, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 + v1630 = not v1620 + store v1629 at v813 + enable_side_effects v1614 + v1631 = array_get v1629, index Field 0 + v1632 = cast v1620 as u4 + v1633 = cast v1630 as u4 + v1634 = mul v1632, v1624 + v1635 = mul v1633, v1631 + v1636 = add v1634, v1635 + v1637 = array_get v1629, index Field 1 + v1638 = cast v1620 as u4 + v1639 = cast v1630 as u4 + v1640 = mul v1638, v1627 + v1641 = mul v1639, v1637 + v1642 = add v1640, v1641 + v1643 = array_get v1629, index Field 2 + v1644 = cast v1620 as u4 + v1645 = cast v1630 as u4 + v1646 = mul v1645, v1643 + v1647 = array_get v1629, index Field 3 + v1648 = cast v1620 as u4 + v1649 = cast v1630 as u4 + v1650 = mul v1649, v1647 + v1651 = array_get v1629, index Field 4 + v1652 = cast v1620 as u4 + v1653 = cast v1630 as u4 + v1654 = mul v1653, v1651 + v1655 = array_get v1629, index Field 5 + v1656 = cast v1620 as u4 + v1657 = cast v1630 as u4 + v1658 = mul v1657, v1655 + v1659 = array_get v1629, index Field 6 + v1660 = cast v1620 as u4 + v1661 = cast v1630 as u4 + v1662 = mul v1661, v1659 + v1663 = array_get v1629, index Field 7 + v1664 = cast v1620 as u4 + v1665 = cast v1630 as u4 + v1666 = mul v1665, v1663 + v1667 = array_get v1629, index Field 8 + v1668 = cast v1620 as u4 + v1669 = cast v1630 as u4 + v1670 = mul v1669, v1667 + v1671 = array_get v1629, index Field 9 + v1672 = cast v1620 as u4 + v1673 = cast v1630 as u4 + v1674 = mul v1673, v1671 + v1675 = array_get v1629, index Field 10 + v1676 = cast v1620 as u4 + v1677 = cast v1630 as u4 + v1678 = mul v1677, v1675 + v1679 = array_get v1629, index Field 11 + v1680 = cast v1620 as u4 + v1681 = cast v1630 as u4 + v1682 = mul v1681, v1679 + v1683 = array_get v1629, index Field 12 + v1684 = cast v1620 as u4 + v1685 = cast v1630 as u4 + v1686 = mul v1685, v1683 + v1687 = array_get v1629, index Field 13 + v1688 = cast v1620 as u4 + v1689 = cast v1630 as u4 + v1690 = mul v1689, v1687 + v1691 = array_get v1629, index Field 14 + v1692 = cast v1620 as u4 + v1693 = cast v1630 as u4 + v1694 = mul v1693, v1691 + v1695 = array_get v1629, index Field 15 + v1696 = cast v1620 as u4 + v1697 = cast v1630 as u4 + v1698 = mul v1697, v1695 + store [v1636, v1642, v1646, v1650, v1654, v1658, v1662, v1666, v1670, v1674, v1678, v1682, v1686, v1690, v1694, v1698] at v813 + v1700 = truncate v1 to 64 bits, max_bit_size: 254 + v1701 = cast v1700 as u64 + v1702 = sub v1701, u64 1 + v1703 = cast v1614 as u64 + v1704 = mul v1702, v1703 + range_check v1704 to 64 bits + v1705 = lt u64 1, v1702 + v1706 = mul v1614, v1705 + enable_side_effects v1706 + v1707 = array_get v0, index u64 2 + v1708 = load v813 + v1709 = div v1707, Field 2⁴ + v1710 = cast v1707 as u4 + v1711 = array_set v1708, index u64 2, value v1710 + v1712 = and v1707, u8 15 + v1713 = truncate v1712 to 4 bits, max_bit_size: 8 + v1714 = cast v1713 as u4 + v1715 = array_set v1711, index u64 3, value v1714 + v1716 = load v813 + store v1715 at v813 + v1717 = not v1705 + store v1716 at v813 + enable_side_effects v1614 + v1718 = array_get v1715, index Field 0 + v1719 = array_get v1716, index Field 0 + v1720 = cast v1705 as u4 + v1721 = cast v1717 as u4 + v1722 = mul v1720, v1718 + v1723 = mul v1721, v1719 + v1724 = add v1722, v1723 + v1725 = array_get v1715, index Field 1 + v1726 = array_get v1716, index Field 1 + v1727 = cast v1705 as u4 + v1728 = cast v1717 as u4 + v1729 = mul v1727, v1725 + v1730 = mul v1728, v1726 + v1731 = add v1729, v1730 + v1732 = array_get v1715, index Field 2 + v1733 = array_get v1716, index Field 2 + v1734 = cast v1705 as u4 + v1735 = cast v1717 as u4 + v1736 = mul v1734, v1732 + v1737 = mul v1735, v1733 + v1738 = add v1736, v1737 + v1739 = array_get v1715, index Field 3 + v1740 = array_get v1716, index Field 3 + v1741 = cast v1705 as u4 + v1742 = cast v1717 as u4 + v1743 = mul v1741, v1739 + v1744 = mul v1742, v1740 + v1745 = add v1743, v1744 + v1746 = array_get v1715, index Field 4 + v1747 = array_get v1716, index Field 4 + v1748 = cast v1705 as u4 + v1749 = cast v1717 as u4 + v1750 = mul v1748, v1746 + v1751 = mul v1749, v1747 + v1752 = add v1750, v1751 + v1753 = array_get v1715, index Field 5 + v1754 = array_get v1716, index Field 5 + v1755 = cast v1705 as u4 + v1756 = cast v1717 as u4 + v1757 = mul v1755, v1753 + v1758 = mul v1756, v1754 + v1759 = add v1757, v1758 + v1760 = array_get v1715, index Field 6 + v1761 = array_get v1716, index Field 6 + v1762 = cast v1705 as u4 + v1763 = cast v1717 as u4 + v1764 = mul v1762, v1760 + v1765 = mul v1763, v1761 + v1766 = add v1764, v1765 + v1767 = array_get v1715, index Field 7 + v1768 = array_get v1716, index Field 7 + v1769 = cast v1705 as u4 + v1770 = cast v1717 as u4 + v1771 = mul v1769, v1767 + v1772 = mul v1770, v1768 + v1773 = add v1771, v1772 + v1774 = array_get v1715, index Field 8 + v1775 = array_get v1716, index Field 8 + v1776 = cast v1705 as u4 + v1777 = cast v1717 as u4 + v1778 = mul v1776, v1774 + v1779 = mul v1777, v1775 + v1780 = add v1778, v1779 + v1781 = array_get v1715, index Field 9 + v1782 = array_get v1716, index Field 9 + v1783 = cast v1705 as u4 + v1784 = cast v1717 as u4 + v1785 = mul v1783, v1781 + v1786 = mul v1784, v1782 + v1787 = add v1785, v1786 + v1788 = array_get v1715, index Field 10 + v1789 = array_get v1716, index Field 10 + v1790 = cast v1705 as u4 + v1791 = cast v1717 as u4 + v1792 = mul v1790, v1788 + v1793 = mul v1791, v1789 + v1794 = add v1792, v1793 + v1795 = array_get v1715, index Field 11 + v1796 = array_get v1716, index Field 11 + v1797 = cast v1705 as u4 + v1798 = cast v1717 as u4 + v1799 = mul v1797, v1795 + v1800 = mul v1798, v1796 + v1801 = add v1799, v1800 + v1802 = array_get v1715, index Field 12 + v1803 = array_get v1716, index Field 12 + v1804 = cast v1705 as u4 + v1805 = cast v1717 as u4 + v1806 = mul v1804, v1802 + v1807 = mul v1805, v1803 + v1808 = add v1806, v1807 + v1809 = array_get v1715, index Field 13 + v1810 = array_get v1716, index Field 13 + v1811 = cast v1705 as u4 + v1812 = cast v1717 as u4 + v1813 = mul v1811, v1809 + v1814 = mul v1812, v1810 + v1815 = add v1813, v1814 + v1816 = array_get v1715, index Field 14 + v1817 = array_get v1716, index Field 14 + v1818 = cast v1705 as u4 + v1819 = cast v1717 as u4 + v1820 = mul v1818, v1816 + v1821 = mul v1819, v1817 + v1822 = add v1820, v1821 + v1823 = array_get v1715, index Field 15 + v1824 = array_get v1716, index Field 15 + v1825 = cast v1705 as u4 + v1826 = cast v1717 as u4 + v1827 = mul v1825, v1823 + v1828 = mul v1826, v1824 + v1829 = add v1827, v1828 + store [v1724, v1731, v1738, v1745, v1752, v1759, v1766, v1773, v1780, v1787, v1794, v1801, v1808, v1815, v1822, v1829] at v813 + enable_side_effects u1 1 + v1831 = cast v819 as u4 + v1832 = cast v1614 as u4 + v1833 = mul v1831, v1507 + v1834 = mul v1832, v1724 + v1835 = add v1833, v1834 + v1836 = cast v819 as u4 + v1837 = cast v1614 as u4 + v1838 = mul v1836, v1514 + v1839 = mul v1837, v1731 + v1840 = add v1838, v1839 + v1841 = cast v819 as u4 + v1842 = cast v1614 as u4 + v1843 = mul v1841, v1521 + v1844 = mul v1842, v1738 + v1845 = add v1843, v1844 + v1846 = cast v819 as u4 + v1847 = cast v1614 as u4 + v1848 = mul v1846, v1528 + v1849 = mul v1847, v1745 + v1850 = add v1848, v1849 + v1851 = cast v819 as u4 + v1852 = cast v1614 as u4 + v1853 = mul v1851, v1535 + v1854 = mul v1852, v1752 + v1855 = add v1853, v1854 + v1856 = cast v819 as u4 + v1857 = cast v1614 as u4 + v1858 = mul v1856, v1542 + v1859 = mul v1857, v1759 + v1860 = add v1858, v1859 + v1861 = cast v819 as u4 + v1862 = cast v1614 as u4 + v1863 = mul v1861, v1549 + v1864 = mul v1862, v1766 + v1865 = add v1863, v1864 + v1866 = cast v819 as u4 + v1867 = cast v1614 as u4 + v1868 = mul v1866, v1556 + v1869 = mul v1867, v1773 + v1870 = add v1868, v1869 + v1871 = cast v819 as u4 + v1872 = cast v1614 as u4 + v1873 = mul v1871, v1563 + v1874 = mul v1872, v1780 + v1875 = add v1873, v1874 + v1876 = cast v819 as u4 + v1877 = cast v1614 as u4 + v1878 = mul v1876, v1570 + v1879 = mul v1877, v1787 + v1880 = add v1878, v1879 + v1881 = cast v819 as u4 + v1882 = cast v1614 as u4 + v1883 = mul v1881, v1577 + v1884 = mul v1882, v1794 + v1885 = add v1883, v1884 + v1886 = cast v819 as u4 + v1887 = cast v1614 as u4 + v1888 = mul v1886, v1584 + v1889 = mul v1887, v1801 + v1890 = add v1888, v1889 + v1891 = cast v819 as u4 + v1892 = cast v1614 as u4 + v1893 = mul v1891, v1591 + v1894 = mul v1892, v1808 + v1895 = add v1893, v1894 + v1896 = cast v819 as u4 + v1897 = cast v1614 as u4 + v1898 = mul v1896, v1598 + v1899 = mul v1897, v1815 + v1900 = add v1898, v1899 + v1901 = cast v819 as u4 + v1902 = cast v1614 as u4 + v1903 = mul v1901, v1605 + v1904 = mul v1902, v1822 + v1905 = add v1903, v1904 + v1906 = cast v819 as u4 + v1907 = cast v1614 as u4 + v1908 = mul v1906, v1612 + v1909 = mul v1907, v1829 + v1910 = add v1908, v1909 + store [v1835, v1840, v1845, v1850, v1855, v1860, v1865, v1870, v1875, v1880, v1885, v1890, v1895, v1900, v1905, v1910] at v813 + v1912 = load v813 + v1913 = mul Field 2, v1 + v1914 = cast v819 as Field + v1915 = add v1913, v1914 + v1916 = sub v1915, Field 2 + inc_rc v1912 + inc_rc v1912 + inc_rc v1912 + v1917 = eq v1916, Field 5 + constrain v1916 == Field 5 + v1918 = array_get v1912, index Field 0 + v1919 = array_get v1912, index Field 1 + v1920 = array_get v1912, index Field 2 + v1921 = array_get v1912, index Field 3 + v1922 = array_get v1912, index Field 4 + v1923 = allocate + v1924 = eq v1918, u4 15 + v1925 = eq v1919, u4 1 + v1926 = mul v1924, v1925 + v1927 = eq v1920, u4 12 + v1928 = mul v1926, v1927 + v1929 = eq v1921, u4 11 + v1930 = mul v1928, v1929 + v1931 = eq v1922, u4 8 + v1932 = mul v1930, v1931 + store v1932 at v1923 + constrain v1932 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v1937 = allocate + range_check u8 148 to 8 bits + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + store [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v1937 + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v1942 = allocate + store u1 1 at v1942 + v1943 = allocate + store u64 1 at v1943 + v1944 = allocate + store u64 2⁴ at v1944 + v1945 = allocate + store u64 1 at v1945 + v1946 = allocate + store u64 2⁴ at v1946 + return +} + +After Mem2Reg: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v1947 = truncate v1 to 64 bits, max_bit_size: 254 + v1948 = cast v1947 as u64 + inc_rc v0 + v1949 = lt u64 5, v1948 + v1950 = not v1949 + constrain v1949 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v1952 = allocate + v1954 = array_get v0, index Field 0 + v1955 = div v1954, Field 2⁴ + v1956 = cast v1954 as u4 + v1957 = truncate v1956 to 1 bits, max_bit_size: 4 + v1958 = cast v1957 as u1 + enable_side_effects v1958 + v1959 = array_get v0, index Field 0 + v1960 = and v1959, u8 15 + v1961 = truncate v1960 to 4 bits, max_bit_size: 8 + v1962 = cast v1961 as u4 + inc_rc v0 + v1965 = truncate v1 to 64 bits, max_bit_size: 254 + v1966 = cast v1965 as u64 + v1967 = lt u64 1, v1966 + v1968 = mul v1958, v1967 + enable_side_effects v1968 + v1969 = array_get v0, index Field 1 + v1970 = div v1969, Field 2⁴ + v1971 = cast v1969 as u4 + v1972 = and v1969, u8 15 + v1973 = truncate v1972 to 4 bits, max_bit_size: 8 + v1974 = cast v1973 as u4 + v1977 = not v1967 + enable_side_effects v1958 + v1980 = cast v1967 as u4 + v1981 = cast v1977 as u4 + v1982 = mul v1980, v1962 + v1983 = mul v1981, v1962 + v1984 = add v1982, v1983 + v1986 = cast v1967 as u4 + v1987 = cast v1977 as u4 + v1988 = mul v1986, v1971 + v1990 = cast v1967 as u4 + v1991 = cast v1977 as u4 + v1992 = mul v1990, v1974 + v1994 = cast v1967 as u4 + v1995 = cast v1977 as u4 + v1997 = cast v1967 as u4 + v1998 = cast v1977 as u4 + v2000 = cast v1967 as u4 + v2001 = cast v1977 as u4 + v2003 = cast v1967 as u4 + v2004 = cast v1977 as u4 + v2006 = cast v1967 as u4 + v2007 = cast v1977 as u4 + v2009 = cast v1967 as u4 + v2010 = cast v1977 as u4 + v2012 = cast v1967 as u4 + v2013 = cast v1977 as u4 + v2015 = cast v1967 as u4 + v2016 = cast v1977 as u4 + v2018 = cast v1967 as u4 + v2019 = cast v1977 as u4 + v2021 = cast v1967 as u4 + v2022 = cast v1977 as u4 + v2024 = cast v1967 as u4 + v2025 = cast v1977 as u4 + v2027 = cast v1967 as u4 + v2028 = cast v1977 as u4 + v2030 = cast v1967 as u4 + v2031 = cast v1977 as u4 + v2033 = truncate v1 to 64 bits, max_bit_size: 254 + v2034 = cast v2033 as u64 + v2035 = lt u64 2, v2034 + v2036 = mul v1958, v2035 + enable_side_effects v2036 + v2037 = array_get v0, index Field 2 + v2039 = div v2037, Field 2⁴ + v2040 = cast v2037 as u4 + v2043 = and v2037, u8 15 + v2044 = truncate v2043 to 4 bits, max_bit_size: 8 + v2045 = cast v2044 as u4 + v2050 = not v2035 + enable_side_effects v1958 + v2054 = cast v2035 as u4 + v2055 = cast v2050 as u4 + v2056 = mul v2054, v1984 + v2057 = mul v2055, v1984 + v2058 = add v2056, v2057 + v2061 = cast v2035 as u4 + v2062 = cast v2050 as u4 + v2063 = mul v2061, v1988 + v2064 = mul v2062, v1988 + v2065 = add v2063, v2064 + v2068 = cast v2035 as u4 + v2069 = cast v2050 as u4 + v2070 = mul v2068, v1992 + v2071 = mul v2069, v1992 + v2072 = add v2070, v2071 + v2075 = cast v2035 as u4 + v2076 = cast v2050 as u4 + v2077 = mul v2075, v2040 + v2080 = cast v2035 as u4 + v2081 = cast v2050 as u4 + v2082 = mul v2080, v2045 + v2085 = cast v2035 as u4 + v2086 = cast v2050 as u4 + v2089 = cast v2035 as u4 + v2090 = cast v2050 as u4 + v2093 = cast v2035 as u4 + v2094 = cast v2050 as u4 + v2097 = cast v2035 as u4 + v2098 = cast v2050 as u4 + v2101 = cast v2035 as u4 + v2102 = cast v2050 as u4 + v2105 = cast v2035 as u4 + v2106 = cast v2050 as u4 + v2109 = cast v2035 as u4 + v2110 = cast v2050 as u4 + v2113 = cast v2035 as u4 + v2114 = cast v2050 as u4 + v2117 = cast v2035 as u4 + v2118 = cast v2050 as u4 + v2121 = cast v2035 as u4 + v2122 = cast v2050 as u4 + v2125 = cast v2035 as u4 + v2126 = cast v2050 as u4 + v2128 = truncate v1 to 64 bits, max_bit_size: 254 + v2129 = cast v2128 as u64 + v2130 = lt u64 3, v2129 + v2131 = mul v1958, v2130 + enable_side_effects v2131 + v2132 = array_get v0, index Field 3 + v2134 = div v2132, Field 2⁴ + v2135 = cast v2132 as u4 + v2138 = and v2132, u8 15 + v2139 = truncate v2138 to 4 bits, max_bit_size: 8 + v2140 = cast v2139 as u4 + v2145 = not v2130 + enable_side_effects v1958 + v2149 = cast v2130 as u4 + v2150 = cast v2145 as u4 + v2151 = mul v2149, v2058 + v2152 = mul v2150, v2058 + v2153 = add v2151, v2152 + v2156 = cast v2130 as u4 + v2157 = cast v2145 as u4 + v2158 = mul v2156, v2065 + v2159 = mul v2157, v2065 + v2160 = add v2158, v2159 + v2163 = cast v2130 as u4 + v2164 = cast v2145 as u4 + v2165 = mul v2163, v2072 + v2166 = mul v2164, v2072 + v2167 = add v2165, v2166 + v2170 = cast v2130 as u4 + v2171 = cast v2145 as u4 + v2172 = mul v2170, v2077 + v2173 = mul v2171, v2077 + v2174 = add v2172, v2173 + v2177 = cast v2130 as u4 + v2178 = cast v2145 as u4 + v2179 = mul v2177, v2082 + v2180 = mul v2178, v2082 + v2181 = add v2179, v2180 + v2184 = cast v2130 as u4 + v2185 = cast v2145 as u4 + v2186 = mul v2184, v2135 + v2189 = cast v2130 as u4 + v2190 = cast v2145 as u4 + v2191 = mul v2189, v2140 + v2194 = cast v2130 as u4 + v2195 = cast v2145 as u4 + v2198 = cast v2130 as u4 + v2199 = cast v2145 as u4 + v2202 = cast v2130 as u4 + v2203 = cast v2145 as u4 + v2206 = cast v2130 as u4 + v2207 = cast v2145 as u4 + v2210 = cast v2130 as u4 + v2211 = cast v2145 as u4 + v2214 = cast v2130 as u4 + v2215 = cast v2145 as u4 + v2218 = cast v2130 as u4 + v2219 = cast v2145 as u4 + v2222 = cast v2130 as u4 + v2223 = cast v2145 as u4 + v2226 = cast v2130 as u4 + v2227 = cast v2145 as u4 + v2229 = truncate v1 to 64 bits, max_bit_size: 254 + v2230 = cast v2229 as u64 + v2231 = lt u64 4, v2230 + v2232 = mul v1958, v2231 + enable_side_effects v2232 + v2233 = array_get v0, index Field 4 + v2235 = div v2233, Field 2⁴ + v2236 = cast v2233 as u4 + v2239 = and v2233, u8 15 + v2240 = truncate v2239 to 4 bits, max_bit_size: 8 + v2241 = cast v2240 as u4 + v2246 = not v2231 + enable_side_effects v1958 + v2250 = cast v2231 as u4 + v2251 = cast v2246 as u4 + v2252 = mul v2250, v2153 + v2253 = mul v2251, v2153 + v2254 = add v2252, v2253 + v2257 = cast v2231 as u4 + v2258 = cast v2246 as u4 + v2259 = mul v2257, v2160 + v2260 = mul v2258, v2160 + v2261 = add v2259, v2260 + v2264 = cast v2231 as u4 + v2265 = cast v2246 as u4 + v2266 = mul v2264, v2167 + v2267 = mul v2265, v2167 + v2268 = add v2266, v2267 + v2271 = cast v2231 as u4 + v2272 = cast v2246 as u4 + v2273 = mul v2271, v2174 + v2274 = mul v2272, v2174 + v2275 = add v2273, v2274 + v2278 = cast v2231 as u4 + v2279 = cast v2246 as u4 + v2280 = mul v2278, v2181 + v2281 = mul v2279, v2181 + v2282 = add v2280, v2281 + v2285 = cast v2231 as u4 + v2286 = cast v2246 as u4 + v2287 = mul v2285, v2186 + v2288 = mul v2286, v2186 + v2289 = add v2287, v2288 + v2292 = cast v2231 as u4 + v2293 = cast v2246 as u4 + v2294 = mul v2292, v2191 + v2295 = mul v2293, v2191 + v2296 = add v2294, v2295 + v2299 = cast v2231 as u4 + v2300 = cast v2246 as u4 + v2301 = mul v2299, v2236 + v2304 = cast v2231 as u4 + v2305 = cast v2246 as u4 + v2306 = mul v2304, v2241 + v2309 = cast v2231 as u4 + v2310 = cast v2246 as u4 + v2313 = cast v2231 as u4 + v2314 = cast v2246 as u4 + v2317 = cast v2231 as u4 + v2318 = cast v2246 as u4 + v2321 = cast v2231 as u4 + v2322 = cast v2246 as u4 + v2325 = cast v2231 as u4 + v2326 = cast v2246 as u4 + v2329 = cast v2231 as u4 + v2330 = cast v2246 as u4 + v2333 = cast v2231 as u4 + v2334 = cast v2246 as u4 + v2336 = not v1958 + enable_side_effects v2336 + v2338 = truncate v1 to 64 bits, max_bit_size: 254 + v2339 = cast v2338 as u64 + v2340 = sub v2339, u64 1 + v2341 = cast v2336 as u64 + v2342 = mul v2340, v2341 + range_check v2342 to 64 bits + v2343 = lt u64 0, v2340 + v2344 = mul v2336, v2343 + enable_side_effects v2344 + v2345 = array_get v0, index u64 1 + v2346 = div v2345, Field 2⁴ + v2347 = cast v2345 as u4 + v2348 = and v2345, u8 15 + v2349 = truncate v2348 to 4 bits, max_bit_size: 8 + v2350 = cast v2349 as u4 + v2353 = not v2343 + enable_side_effects v2336 + v2356 = cast v2343 as u4 + v2357 = cast v2353 as u4 + v2358 = mul v2356, v2347 + v2360 = cast v2343 as u4 + v2361 = cast v2353 as u4 + v2362 = mul v2360, v2350 + v2364 = cast v2343 as u4 + v2365 = cast v2353 as u4 + v2367 = cast v2343 as u4 + v2368 = cast v2353 as u4 + v2370 = cast v2343 as u4 + v2371 = cast v2353 as u4 + v2373 = cast v2343 as u4 + v2374 = cast v2353 as u4 + v2376 = cast v2343 as u4 + v2377 = cast v2353 as u4 + v2379 = cast v2343 as u4 + v2380 = cast v2353 as u4 + v2382 = cast v2343 as u4 + v2383 = cast v2353 as u4 + v2385 = cast v2343 as u4 + v2386 = cast v2353 as u4 + v2388 = cast v2343 as u4 + v2389 = cast v2353 as u4 + v2391 = cast v2343 as u4 + v2392 = cast v2353 as u4 + v2394 = cast v2343 as u4 + v2395 = cast v2353 as u4 + v2397 = cast v2343 as u4 + v2398 = cast v2353 as u4 + v2400 = cast v2343 as u4 + v2401 = cast v2353 as u4 + v2403 = cast v2343 as u4 + v2404 = cast v2353 as u4 + v2406 = truncate v1 to 64 bits, max_bit_size: 254 + v2407 = cast v2406 as u64 + v2408 = sub v2407, u64 1 + v2409 = cast v2336 as u64 + v2410 = mul v2408, v2409 + range_check v2410 to 64 bits + v2411 = lt u64 1, v2408 + v2412 = mul v2336, v2411 + enable_side_effects v2412 + v2413 = array_get v0, index u64 2 + v2415 = div v2413, Field 2⁴ + v2416 = cast v2413 as u4 + v2419 = and v2413, u8 15 + v2420 = truncate v2419 to 4 bits, max_bit_size: 8 + v2421 = cast v2420 as u4 + v2426 = not v2411 + enable_side_effects v2336 + v2430 = cast v2411 as u4 + v2431 = cast v2426 as u4 + v2432 = mul v2430, v2358 + v2433 = mul v2431, v2358 + v2434 = add v2432, v2433 + v2437 = cast v2411 as u4 + v2438 = cast v2426 as u4 + v2439 = mul v2437, v2362 + v2440 = mul v2438, v2362 + v2441 = add v2439, v2440 + v2444 = cast v2411 as u4 + v2445 = cast v2426 as u4 + v2446 = mul v2444, v2416 + v2449 = cast v2411 as u4 + v2450 = cast v2426 as u4 + v2451 = mul v2449, v2421 + v2454 = cast v2411 as u4 + v2455 = cast v2426 as u4 + v2458 = cast v2411 as u4 + v2459 = cast v2426 as u4 + v2462 = cast v2411 as u4 + v2463 = cast v2426 as u4 + v2466 = cast v2411 as u4 + v2467 = cast v2426 as u4 + v2470 = cast v2411 as u4 + v2471 = cast v2426 as u4 + v2474 = cast v2411 as u4 + v2475 = cast v2426 as u4 + v2478 = cast v2411 as u4 + v2479 = cast v2426 as u4 + v2482 = cast v2411 as u4 + v2483 = cast v2426 as u4 + v2486 = cast v2411 as u4 + v2487 = cast v2426 as u4 + v2490 = cast v2411 as u4 + v2491 = cast v2426 as u4 + v2494 = cast v2411 as u4 + v2495 = cast v2426 as u4 + v2498 = cast v2411 as u4 + v2499 = cast v2426 as u4 + enable_side_effects u1 1 + v2501 = cast v1958 as u4 + v2502 = cast v2336 as u4 + v2503 = mul v2501, v2254 + v2504 = mul v2502, v2434 + v2505 = add v2503, v2504 + v2506 = cast v1958 as u4 + v2507 = cast v2336 as u4 + v2508 = mul v2506, v2261 + v2509 = mul v2507, v2441 + v2510 = add v2508, v2509 + v2511 = cast v1958 as u4 + v2512 = cast v2336 as u4 + v2513 = mul v2511, v2268 + v2514 = mul v2512, v2446 + v2515 = add v2513, v2514 + v2516 = cast v1958 as u4 + v2517 = cast v2336 as u4 + v2518 = mul v2516, v2275 + v2519 = mul v2517, v2451 + v2520 = add v2518, v2519 + v2521 = cast v1958 as u4 + v2522 = cast v2336 as u4 + v2523 = mul v2521, v2282 + v2524 = cast v1958 as u4 + v2525 = cast v2336 as u4 + v2526 = mul v2524, v2289 + v2527 = cast v1958 as u4 + v2528 = cast v2336 as u4 + v2529 = mul v2527, v2296 + v2530 = cast v1958 as u4 + v2531 = cast v2336 as u4 + v2532 = mul v2530, v2301 + v2533 = cast v1958 as u4 + v2534 = cast v2336 as u4 + v2535 = mul v2533, v2306 + v2536 = cast v1958 as u4 + v2537 = cast v2336 as u4 + v2538 = cast v1958 as u4 + v2539 = cast v2336 as u4 + v2540 = cast v1958 as u4 + v2541 = cast v2336 as u4 + v2542 = cast v1958 as u4 + v2543 = cast v2336 as u4 + v2544 = cast v1958 as u4 + v2545 = cast v2336 as u4 + v2546 = cast v1958 as u4 + v2547 = cast v2336 as u4 + v2548 = cast v1958 as u4 + v2549 = cast v2336 as u4 + v2552 = mul Field 2, v1 + v2553 = cast v1958 as Field + v2554 = add v2552, v2553 + v2555 = sub v2554, Field 2 + inc_rc [v2505, v2510, v2515, v2520, v2523, v2526, v2529, v2532, v2535, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + inc_rc [v2505, v2510, v2515, v2520, v2523, v2526, v2529, v2532, v2535, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + inc_rc [v2505, v2510, v2515, v2520, v2523, v2526, v2529, v2532, v2535, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v2559 = eq v2555, Field 5 + constrain v2555 == Field 5 + v2565 = allocate + v2566 = eq v2505, u4 15 + v2567 = eq v2510, u4 1 + v2568 = mul v2566, v2567 + v2569 = eq v2515, u4 12 + v2570 = mul v2568, v2569 + v2571 = eq v2520, u4 11 + v2572 = mul v2570, v2571 + v2573 = eq v2523, u4 8 + v2574 = mul v2572, v2573 + constrain v2574 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v2579 = allocate + range_check u8 148 to 8 bits + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v2584 = allocate + v2585 = allocate + v2586 = allocate + v2587 = allocate + v2588 = allocate + return +} + +After Constant Folding: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v2589 = truncate v1 to 64 bits, max_bit_size: 254 + v2590 = cast v2589 as u64 + inc_rc v0 + v2591 = lt u64 5, v2590 + v2592 = not v2591 + constrain v2591 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v2593 = allocate + v2594 = array_get v0, index Field 0 + v2595 = div v2594, Field 2⁴ + v2596 = cast v2594 as u4 + v2597 = truncate v2596 to 1 bits, max_bit_size: 4 + v2598 = cast v2597 as u1 + enable_side_effects v2598 + v2599 = and v2594, u8 15 + v2600 = truncate v2599 to 4 bits, max_bit_size: 8 + v2601 = cast v2600 as u4 + inc_rc v0 + v2602 = lt u64 1, v2590 + v2603 = mul v2598, v2602 + enable_side_effects v2603 + v2604 = array_get v0, index Field 1 + v2605 = div v2604, Field 2⁴ + v2606 = cast v2604 as u4 + v2607 = and v2604, u8 15 + v2608 = truncate v2607 to 4 bits, max_bit_size: 8 + v2609 = cast v2608 as u4 + v2610 = not v2602 + enable_side_effects v2598 + v2611 = cast v2602 as u4 + v2612 = cast v2610 as u4 + v2613 = mul v2611, v2601 + v2614 = mul v2612, v2601 + v2615 = add v2613, v2614 + v2616 = mul v2611, v2606 + v2617 = mul v2611, v2609 + v2618 = lt u64 2, v2590 + v2619 = mul v2598, v2618 + enable_side_effects v2619 + v2620 = array_get v0, index Field 2 + v2621 = div v2620, Field 2⁴ + v2622 = cast v2620 as u4 + v2623 = and v2620, u8 15 + v2624 = truncate v2623 to 4 bits, max_bit_size: 8 + v2625 = cast v2624 as u4 + v2626 = not v2618 + enable_side_effects v2598 + v2627 = cast v2618 as u4 + v2628 = cast v2626 as u4 + v2629 = mul v2627, v2615 + v2630 = mul v2628, v2615 + v2631 = add v2629, v2630 + v2632 = mul v2627, v2616 + v2633 = mul v2628, v2616 + v2634 = add v2632, v2633 + v2635 = mul v2627, v2617 + v2636 = mul v2628, v2617 + v2637 = add v2635, v2636 + v2638 = mul v2627, v2622 + v2639 = mul v2627, v2625 + v2640 = lt u64 3, v2590 + v2641 = mul v2598, v2640 + enable_side_effects v2641 + v2642 = array_get v0, index Field 3 + v2643 = div v2642, Field 2⁴ + v2644 = cast v2642 as u4 + v2645 = and v2642, u8 15 + v2646 = truncate v2645 to 4 bits, max_bit_size: 8 + v2647 = cast v2646 as u4 + v2648 = not v2640 + enable_side_effects v2598 + v2649 = cast v2640 as u4 + v2650 = cast v2648 as u4 + v2651 = mul v2649, v2631 + v2652 = mul v2650, v2631 + v2653 = add v2651, v2652 + v2654 = mul v2649, v2634 + v2655 = mul v2650, v2634 + v2656 = add v2654, v2655 + v2657 = mul v2649, v2637 + v2658 = mul v2650, v2637 + v2659 = add v2657, v2658 + v2660 = mul v2649, v2638 + v2661 = mul v2650, v2638 + v2662 = add v2660, v2661 + v2663 = mul v2649, v2639 + v2664 = mul v2650, v2639 + v2665 = add v2663, v2664 + v2666 = mul v2649, v2644 + v2667 = mul v2649, v2647 + v2668 = lt u64 4, v2590 + v2669 = mul v2598, v2668 + enable_side_effects v2669 + v2670 = array_get v0, index Field 4 + v2671 = div v2670, Field 2⁴ + v2672 = cast v2670 as u4 + v2673 = and v2670, u8 15 + v2674 = truncate v2673 to 4 bits, max_bit_size: 8 + v2675 = cast v2674 as u4 + v2676 = not v2668 + enable_side_effects v2598 + v2677 = cast v2668 as u4 + v2678 = cast v2676 as u4 + v2679 = mul v2677, v2653 + v2680 = mul v2678, v2653 + v2681 = add v2679, v2680 + v2682 = mul v2677, v2656 + v2683 = mul v2678, v2656 + v2684 = add v2682, v2683 + v2685 = mul v2677, v2659 + v2686 = mul v2678, v2659 + v2687 = add v2685, v2686 + v2688 = mul v2677, v2662 + v2689 = mul v2678, v2662 + v2690 = add v2688, v2689 + v2691 = mul v2677, v2665 + v2692 = mul v2678, v2665 + v2693 = add v2691, v2692 + v2694 = mul v2677, v2666 + v2695 = mul v2678, v2666 + v2696 = add v2694, v2695 + v2697 = mul v2677, v2667 + v2698 = mul v2678, v2667 + v2699 = add v2697, v2698 + v2700 = mul v2677, v2672 + v2701 = mul v2677, v2675 + v2702 = not v2598 + enable_side_effects v2702 + v2703 = sub v2590, u64 1 + v2704 = cast v2702 as u64 + v2705 = mul v2703, v2704 + range_check v2705 to 64 bits + v2706 = lt u64 0, v2703 + v2707 = mul v2702, v2706 + enable_side_effects v2707 + v2708 = array_get v0, index u64 1 + v2709 = div v2708, Field 2⁴ + v2710 = cast v2708 as u4 + v2711 = and v2708, u8 15 + v2712 = truncate v2711 to 4 bits, max_bit_size: 8 + v2713 = cast v2712 as u4 + v2714 = not v2706 + enable_side_effects v2702 + v2715 = cast v2706 as u4 + v2716 = cast v2714 as u4 + v2717 = mul v2715, v2710 + v2718 = mul v2715, v2713 + range_check v2705 to 64 bits + v2719 = lt u64 1, v2703 + v2720 = mul v2702, v2719 + enable_side_effects v2720 + v2721 = array_get v0, index u64 2 + v2722 = div v2721, Field 2⁴ + v2723 = cast v2721 as u4 + v2724 = and v2721, u8 15 + v2725 = truncate v2724 to 4 bits, max_bit_size: 8 + v2726 = cast v2725 as u4 + v2727 = not v2719 + enable_side_effects v2702 + v2728 = cast v2719 as u4 + v2729 = cast v2727 as u4 + v2730 = mul v2728, v2717 + v2731 = mul v2729, v2717 + v2732 = add v2730, v2731 + v2733 = mul v2728, v2718 + v2734 = mul v2729, v2718 + v2735 = add v2733, v2734 + v2736 = mul v2728, v2723 + v2737 = mul v2728, v2726 + enable_side_effects u1 1 + v2738 = cast v2598 as u4 + v2739 = cast v2702 as u4 + v2740 = mul v2738, v2681 + v2741 = mul v2739, v2732 + v2742 = add v2740, v2741 + v2743 = mul v2738, v2684 + v2744 = mul v2739, v2735 + v2745 = add v2743, v2744 + v2746 = mul v2738, v2687 + v2747 = mul v2739, v2736 + v2748 = add v2746, v2747 + v2749 = mul v2738, v2690 + v2750 = mul v2739, v2737 + v2751 = add v2749, v2750 + v2752 = mul v2738, v2693 + v2753 = mul v2738, v2696 + v2754 = mul v2738, v2699 + v2755 = mul v2738, v2700 + v2756 = mul v2738, v2701 + v2757 = mul Field 2, v1 + v2758 = cast v2598 as Field + v2759 = add v2757, v2758 + v2760 = sub v2759, Field 2 + inc_rc [v2742, v2745, v2748, v2751, v2752, v2753, v2754, v2755, v2756, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + inc_rc [v2742, v2745, v2748, v2751, v2752, v2753, v2754, v2755, v2756, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + inc_rc [v2742, v2745, v2748, v2751, v2752, v2753, v2754, v2755, v2756, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v2761 = eq v2760, Field 5 + constrain v2760 == Field 5 + v2762 = allocate + v2763 = eq v2742, u4 15 + v2764 = eq v2745, u4 1 + v2765 = mul v2763, v2764 + v2766 = eq v2748, u4 12 + v2767 = mul v2765, v2766 + v2768 = eq v2751, u4 11 + v2769 = mul v2767, v2768 + v2770 = eq v2752, u4 8 + v2771 = mul v2769, v2770 + constrain v2771 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v2772 = allocate + range_check u8 148 to 8 bits + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v2773 = allocate + v2774 = allocate + v2775 = allocate + v2776 = allocate + v2777 = allocate + return +} + +After Dead Instruction Elimination: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v2589 = truncate v1 to 64 bits, max_bit_size: 254 + v2590 = cast v2589 as u64 + inc_rc v0 + v2591 = lt u64 5, v2590 + constrain v2591 == u1 0 + v2594 = array_get v0, index Field 0 + v2596 = cast v2594 as u4 + v2597 = truncate v2596 to 1 bits, max_bit_size: 4 + v2598 = cast v2597 as u1 + enable_side_effects v2598 + v2599 = and v2594, u8 15 + v2600 = truncate v2599 to 4 bits, max_bit_size: 8 + v2601 = cast v2600 as u4 + inc_rc v0 + v2602 = lt u64 1, v2590 + v2603 = mul v2598, v2602 + enable_side_effects v2603 + v2604 = array_get v0, index Field 1 + v2606 = cast v2604 as u4 + v2607 = and v2604, u8 15 + v2608 = truncate v2607 to 4 bits, max_bit_size: 8 + v2609 = cast v2608 as u4 + v2610 = not v2602 + enable_side_effects v2598 + v2611 = cast v2602 as u4 + v2612 = cast v2610 as u4 + v2613 = mul v2611, v2601 + v2614 = mul v2612, v2601 + v2615 = add v2613, v2614 + v2616 = mul v2611, v2606 + v2617 = mul v2611, v2609 + v2618 = lt u64 2, v2590 + v2619 = mul v2598, v2618 + enable_side_effects v2619 + v2620 = array_get v0, index Field 2 + v2622 = cast v2620 as u4 + v2623 = and v2620, u8 15 + v2624 = truncate v2623 to 4 bits, max_bit_size: 8 + v2625 = cast v2624 as u4 + v2626 = not v2618 + enable_side_effects v2598 + v2627 = cast v2618 as u4 + v2628 = cast v2626 as u4 + v2629 = mul v2627, v2615 + v2630 = mul v2628, v2615 + v2631 = add v2629, v2630 + v2632 = mul v2627, v2616 + v2633 = mul v2628, v2616 + v2634 = add v2632, v2633 + v2635 = mul v2627, v2617 + v2636 = mul v2628, v2617 + v2637 = add v2635, v2636 + v2638 = mul v2627, v2622 + v2639 = mul v2627, v2625 + v2640 = lt u64 3, v2590 + v2641 = mul v2598, v2640 + enable_side_effects v2641 + v2648 = not v2640 + enable_side_effects v2598 + v2649 = cast v2640 as u4 + v2650 = cast v2648 as u4 + v2651 = mul v2649, v2631 + v2652 = mul v2650, v2631 + v2653 = add v2651, v2652 + v2654 = mul v2649, v2634 + v2655 = mul v2650, v2634 + v2656 = add v2654, v2655 + v2657 = mul v2649, v2637 + v2658 = mul v2650, v2637 + v2659 = add v2657, v2658 + v2660 = mul v2649, v2638 + v2661 = mul v2650, v2638 + v2662 = add v2660, v2661 + v2663 = mul v2649, v2639 + v2664 = mul v2650, v2639 + v2665 = add v2663, v2664 + v2668 = lt u64 4, v2590 + v2669 = mul v2598, v2668 + enable_side_effects v2669 + v2676 = not v2668 + enable_side_effects v2598 + v2677 = cast v2668 as u4 + v2678 = cast v2676 as u4 + v2679 = mul v2677, v2653 + v2680 = mul v2678, v2653 + v2681 = add v2679, v2680 + v2682 = mul v2677, v2656 + v2683 = mul v2678, v2656 + v2684 = add v2682, v2683 + v2685 = mul v2677, v2659 + v2686 = mul v2678, v2659 + v2687 = add v2685, v2686 + v2688 = mul v2677, v2662 + v2689 = mul v2678, v2662 + v2690 = add v2688, v2689 + v2691 = mul v2677, v2665 + v2692 = mul v2678, v2665 + v2693 = add v2691, v2692 + v2702 = not v2598 + enable_side_effects v2702 + v2703 = sub v2590, u64 1 + v2704 = cast v2702 as u64 + v2705 = mul v2703, v2704 + range_check v2705 to 64 bits + v2706 = lt u64 0, v2703 + v2707 = mul v2702, v2706 + enable_side_effects v2707 + v2708 = array_get v0, index u64 1 + v2710 = cast v2708 as u4 + v2711 = and v2708, u8 15 + v2712 = truncate v2711 to 4 bits, max_bit_size: 8 + v2713 = cast v2712 as u4 + enable_side_effects v2702 + v2715 = cast v2706 as u4 + v2717 = mul v2715, v2710 + v2718 = mul v2715, v2713 + range_check v2705 to 64 bits + v2719 = lt u64 1, v2703 + v2720 = mul v2702, v2719 + enable_side_effects v2720 + v2721 = array_get v0, index u64 2 + v2723 = cast v2721 as u4 + v2724 = and v2721, u8 15 + v2725 = truncate v2724 to 4 bits, max_bit_size: 8 + v2726 = cast v2725 as u4 + v2727 = not v2719 + enable_side_effects v2702 + v2728 = cast v2719 as u4 + v2729 = cast v2727 as u4 + v2730 = mul v2728, v2717 + v2731 = mul v2729, v2717 + v2732 = add v2730, v2731 + v2733 = mul v2728, v2718 + v2734 = mul v2729, v2718 + v2735 = add v2733, v2734 + v2736 = mul v2728, v2723 + v2737 = mul v2728, v2726 + enable_side_effects u1 1 + v2738 = cast v2598 as u4 + v2739 = cast v2702 as u4 + v2740 = mul v2738, v2681 + v2741 = mul v2739, v2732 + v2742 = add v2740, v2741 + v2743 = mul v2738, v2684 + v2744 = mul v2739, v2735 + v2745 = add v2743, v2744 + v2746 = mul v2738, v2687 + v2747 = mul v2739, v2736 + v2748 = add v2746, v2747 + v2749 = mul v2738, v2690 + v2750 = mul v2739, v2737 + v2751 = add v2749, v2750 + v2752 = mul v2738, v2693 + v2757 = mul Field 2, v1 + v2758 = cast v2598 as Field + v2759 = add v2757, v2758 + v2760 = sub v2759, Field 2 + constrain v2760 == Field 5 + v2763 = eq v2742, u4 15 + v2764 = eq v2745, u4 1 + v2765 = mul v2763, v2764 + v2766 = eq v2748, u4 12 + v2767 = mul v2765, v2766 + v2768 = eq v2751, u4 11 + v2769 = mul v2767, v2768 + v2770 = eq v2752, u4 8 + v2771 = mul v2769, v2770 + constrain v2771 == u1 1 + range_check u8 148 to 8 bits + return +} + +After Fill Internal Slice Dummy Data: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v2778 = truncate v1 to 64 bits, max_bit_size: 254 + v2779 = cast v2778 as u64 + inc_rc v0 + v2780 = lt u64 5, v2779 + constrain v2780 == u1 0 + v2781 = array_get v0, index Field 0 + v2782 = cast v2781 as u4 + v2783 = truncate v2782 to 1 bits, max_bit_size: 4 + v2784 = cast v2783 as u1 + enable_side_effects v2784 + v2785 = and v2781, u8 15 + v2786 = truncate v2785 to 4 bits, max_bit_size: 8 + v2787 = cast v2786 as u4 + inc_rc v0 + v2788 = lt u64 1, v2779 + v2789 = mul v2784, v2788 + enable_side_effects v2789 + v2790 = array_get v0, index Field 1 + v2791 = cast v2790 as u4 + v2792 = and v2790, u8 15 + v2793 = truncate v2792 to 4 bits, max_bit_size: 8 + v2794 = cast v2793 as u4 + v2795 = not v2788 + enable_side_effects v2784 + v2796 = cast v2788 as u4 + v2797 = cast v2795 as u4 + v2798 = mul v2796, v2787 + v2799 = mul v2797, v2787 + v2800 = add v2798, v2799 + v2801 = mul v2796, v2791 + v2802 = mul v2796, v2794 + v2803 = lt u64 2, v2779 + v2804 = mul v2784, v2803 + enable_side_effects v2804 + v2805 = array_get v0, index Field 2 + v2806 = cast v2805 as u4 + v2807 = and v2805, u8 15 + v2808 = truncate v2807 to 4 bits, max_bit_size: 8 + v2809 = cast v2808 as u4 + v2810 = not v2803 + enable_side_effects v2784 + v2811 = cast v2803 as u4 + v2812 = cast v2810 as u4 + v2813 = mul v2811, v2800 + v2814 = mul v2812, v2800 + v2815 = add v2813, v2814 + v2816 = mul v2811, v2801 + v2817 = mul v2812, v2801 + v2818 = add v2816, v2817 + v2819 = mul v2811, v2802 + v2820 = mul v2812, v2802 + v2821 = add v2819, v2820 + v2822 = mul v2811, v2806 + v2823 = mul v2811, v2809 + v2824 = lt u64 3, v2779 + v2825 = mul v2784, v2824 + enable_side_effects v2825 + v2826 = not v2824 + enable_side_effects v2784 + v2827 = cast v2824 as u4 + v2828 = cast v2826 as u4 + v2829 = mul v2827, v2815 + v2830 = mul v2828, v2815 + v2831 = add v2829, v2830 + v2832 = mul v2827, v2818 + v2833 = mul v2828, v2818 + v2834 = add v2832, v2833 + v2835 = mul v2827, v2821 + v2836 = mul v2828, v2821 + v2837 = add v2835, v2836 + v2838 = mul v2827, v2822 + v2839 = mul v2828, v2822 + v2840 = add v2838, v2839 + v2841 = mul v2827, v2823 + v2842 = mul v2828, v2823 + v2843 = add v2841, v2842 + v2844 = lt u64 4, v2779 + v2845 = mul v2784, v2844 + enable_side_effects v2845 + v2846 = not v2844 + enable_side_effects v2784 + v2847 = cast v2844 as u4 + v2848 = cast v2846 as u4 + v2849 = mul v2847, v2831 + v2850 = mul v2848, v2831 + v2851 = add v2849, v2850 + v2852 = mul v2847, v2834 + v2853 = mul v2848, v2834 + v2854 = add v2852, v2853 + v2855 = mul v2847, v2837 + v2856 = mul v2848, v2837 + v2857 = add v2855, v2856 + v2858 = mul v2847, v2840 + v2859 = mul v2848, v2840 + v2860 = add v2858, v2859 + v2861 = mul v2847, v2843 + v2862 = mul v2848, v2843 + v2863 = add v2861, v2862 + v2864 = not v2784 + enable_side_effects v2864 + v2865 = sub v2779, u64 1 + v2866 = cast v2864 as u64 + v2867 = mul v2865, v2866 + range_check v2867 to 64 bits + v2868 = lt u64 0, v2865 + v2869 = mul v2864, v2868 + enable_side_effects v2869 + v2870 = array_get v0, index u64 1 + v2871 = cast v2870 as u4 + v2872 = and v2870, u8 15 + v2873 = truncate v2872 to 4 bits, max_bit_size: 8 + v2874 = cast v2873 as u4 + enable_side_effects v2864 + v2875 = cast v2868 as u4 + v2876 = mul v2875, v2871 + v2877 = mul v2875, v2874 + range_check v2867 to 64 bits + v2878 = lt u64 1, v2865 + v2879 = mul v2864, v2878 + enable_side_effects v2879 + v2880 = array_get v0, index u64 2 + v2881 = cast v2880 as u4 + v2882 = and v2880, u8 15 + v2883 = truncate v2882 to 4 bits, max_bit_size: 8 + v2884 = cast v2883 as u4 + v2885 = not v2878 + enable_side_effects v2864 + v2886 = cast v2878 as u4 + v2887 = cast v2885 as u4 + v2888 = mul v2886, v2876 + v2889 = mul v2887, v2876 + v2890 = add v2888, v2889 + v2891 = mul v2886, v2877 + v2892 = mul v2887, v2877 + v2893 = add v2891, v2892 + v2894 = mul v2886, v2881 + v2895 = mul v2886, v2884 + enable_side_effects u1 1 + v2896 = cast v2784 as u4 + v2897 = cast v2864 as u4 + v2898 = mul v2896, v2851 + v2899 = mul v2897, v2890 + v2900 = add v2898, v2899 + v2901 = mul v2896, v2854 + v2902 = mul v2897, v2893 + v2903 = add v2901, v2902 + v2904 = mul v2896, v2857 + v2905 = mul v2897, v2894 + v2906 = add v2904, v2905 + v2907 = mul v2896, v2860 + v2908 = mul v2897, v2895 + v2909 = add v2907, v2908 + v2910 = mul v2896, v2863 + v2911 = mul Field 2, v1 + v2912 = cast v2784 as Field + v2913 = add v2911, v2912 + v2914 = sub v2913, Field 2 + constrain v2914 == Field 5 + v2915 = eq v2900, u4 15 + v2916 = eq v2903, u4 1 + v2917 = mul v2915, v2916 + v2918 = eq v2906, u4 12 + v2919 = mul v2917, v2918 + v2920 = eq v2909, u4 11 + v2921 = mul v2919, v2920 + v2922 = eq v2910, u4 8 + v2923 = mul v2921, v2922 + constrain v2923 == u1 1 + range_check u8 148 to 8 bits + return +} + diff --git a/test_programs/execution_success/regression/new-acir b/test_programs/execution_success/regression/new-acir new file mode 100644 index 00000000000..9f6cc42b863 --- /dev/null +++ b/test_programs/execution_success/regression/new-acir @@ -0,0 +1,202 @@ +Compiled ACIR for main (unoptimized): +current witness index : 100 +public parameters indices : [] +return value indices : [] +BLACKBOX::RANGE [(_1, num_bits: 8)] [ ] +BLACKBOX::RANGE [(_2, num_bits: 8)] [ ] +BLACKBOX::RANGE [(_3, num_bits: 8)] [ ] +BLACKBOX::RANGE [(_4, num_bits: 8)] [ ] +BLACKBOX::RANGE [(_5, num_bits: 8)] [ ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(6))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(7)), Simple(Witness(8))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 255, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 255, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 255, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_7, num_bits: 190)] [ ] +BLACKBOX::RANGE [(_8, num_bits: 64)] [ ] +EXPR [ (1, _6) (-2⁶⁴, _7) (-1, _8) 0 ] +EXPR [ (1, _7) (-1, _9) -1186564023676924939888766319973246049704924238154051448977 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(9))], q_c: 0 })] +outputs: [Simple(Witness(10))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _9, _10) (1, _11) -1 ] +EXPR [ (1, _9, _11) 0 ] +EXPR [ (-1, _8, _11) (2¹⁶×74637766815744, _11) (-1, _12) 0 ] +BLACKBOX::RANGE [(_12, num_bits: 65)] [ ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551621 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(13)), Simple(Witness(14))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_14, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _13) (-1, _14) 18446744073709551621 ] +EXPR [ (-1, _13) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(1))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2 })] +outputs: [Simple(Witness(15)), Simple(Witness(16))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 5, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 5, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 5, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_15, num_bits: 3)] [ ] +EXPR [ (1, _16, _16) (-1, _16) 0 ] +EXPR [ (1, _1) (-2, _15) (-1, _16) 0 ] +EXPR [ (-1, _17) 15 ] +BLACKBOX::AND [(_1, num_bits: 8), (_17, num_bits: 8)] [ _18] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(18))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(19)), Simple(Witness(20))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_19, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_20, num_bits: 4)] [ ] +EXPR [ (1, _18) (-2⁴, _19) (-1, _20) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551617 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(21)), Simple(Witness(22))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _21, _21) (-1, _21) 0 ] +BLACKBOX::RANGE [(_22, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _21) (-1, _22) 18446744073709551617 ] +EXPR [ (-1, _21) (-1, _23) 1 ] +BLACKBOX::AND [(_2, num_bits: 8), (_17, num_bits: 8)] [ _24] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(24))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(25)), Simple(Witness(26))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_25, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_26, num_bits: 4)] [ ] +EXPR [ (1, _24) (-2⁴, _25) (-1, _26) 0 ] +EXPR [ (-1, _23) (-1, _27) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551618 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(28)), Simple(Witness(29))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _28, _28) (-1, _28) 0 ] +BLACKBOX::RANGE [(_29, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _28) (-1, _29) 18446744073709551618 ] +EXPR [ (-1, _28) (-1, _30) 1 ] +BLACKBOX::AND [(_3, num_bits: 8), (_17, num_bits: 8)] [ _31] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(31))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(32)), Simple(Witness(33))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_32, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_33, num_bits: 4)] [ ] +EXPR [ (1, _31) (-2⁴, _32) (-1, _33) 0 ] +EXPR [ (1, _20, _23) (1, _20, _27) (-1, _34) 0 ] +EXPR [ (-1, _30) (-1, _35) 1 ] +EXPR [ (1, _2, _23) (-1, _36) 0 ] +EXPR [ (1, _23, _26) (-1, _37) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551619 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(38)), Simple(Witness(39))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _38, _38) (-1, _38) 0 ] +BLACKBOX::RANGE [(_39, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _38) (-1, _39) 18446744073709551619 ] +EXPR [ (-1, _38) (-1, _40) 1 ] +EXPR [ (1, _30, _34) (1, _34, _35) (-1, _41) 0 ] +EXPR [ (-1, _40) (-1, _42) 1 ] +EXPR [ (1, _30, _36) (1, _35, _36) (-1, _43) 0 ] +EXPR [ (1, _30, _37) (1, _35, _37) (-1, _44) 0 ] +EXPR [ (1, _3, _30) (-1, _45) 0 ] +EXPR [ (1, _30, _33) (-1, _46) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551620 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(47)), Simple(Witness(48))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _47, _47) (-1, _47) 0 ] +BLACKBOX::RANGE [(_48, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _47) (-1, _48) 18446744073709551620 ] +EXPR [ (-1, _47) (-1, _49) 1 ] +EXPR [ (1, _40, _41) (1, _41, _42) (-1, _50) 0 ] +EXPR [ (-1, _49) (-1, _51) 1 ] +EXPR [ (1, _40, _43) (1, _42, _43) (-1, _52) 0 ] +EXPR [ (1, _40, _44) (1, _42, _44) (-1, _53) 0 ] +EXPR [ (1, _40, _45) (1, _42, _45) (-1, _54) 0 ] +EXPR [ (1, _40, _46) (1, _42, _46) (-1, _55) 0 ] +EXPR [ (1, _8) (-1, _56) -1 ] +EXPR [ (-1, _16) (-1, _57) 1 ] +EXPR [ (1, _56, _57) (-1, _58) 0 ] +BLACKBOX::RANGE [(_58, num_bits: 64)] [ ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(56))], q_c: 2⁶⁴ }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(59)), Simple(Witness(60))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _59, _59) (-1, _59) 0 ] +BLACKBOX::RANGE [(_60, num_bits: 64)] [ ] +EXPR [ (-1, _56) (-2⁶⁴, _59) (-1, _60) 2⁶⁴ ] +EXPR [ (-1, _59) (-1, _61) 1 ] +BLACKBOX::AND [(_2, num_bits: 8), (_17, num_bits: 8)] [ _62] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(62))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(63)), Simple(Witness(64))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_63, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_64, num_bits: 4)] [ ] +EXPR [ (1, _62) (-2⁴, _63) (-1, _64) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(56))], q_c: 18446744073709551617 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(65)), Simple(Witness(66))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _65, _65) (-1, _65) 0 ] +BLACKBOX::RANGE [(_66, num_bits: 64)] [ ] +EXPR [ (-1, _56) (-2⁶⁴, _65) (-1, _66) 18446744073709551617 ] +EXPR [ (-1, _65) (-1, _67) 1 ] +BLACKBOX::AND [(_3, num_bits: 8), (_17, num_bits: 8)] [ _68] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(68))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(69)), Simple(Witness(70))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_69, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_70, num_bits: 4)] [ ] +EXPR [ (1, _68) (-2⁴, _69) (-1, _70) 0 ] +EXPR [ (1, _2, _61) (-1, _71) 0 ] +EXPR [ (-1, _67) (-1, _72) 1 ] +EXPR [ (1, _61, _64) (-1, _73) 0 ] +EXPR [ (1, _49, _50) (1, _50, _51) (-1, _74) 0 ] +EXPR [ (1, _67, _71) (1, _71, _72) (-1, _75) 0 ] +EXPR [ (1, _49, _52) (1, _51, _52) (-1, _76) 0 ] +EXPR [ (1, _67, _73) (1, _72, _73) (-1, _77) 0 ] +EXPR [ (1, _49, _53) (1, _51, _53) (-1, _78) 0 ] +EXPR [ (1, _3, _67) (-1, _79) 0 ] +EXPR [ (1, _49, _54) (1, _51, _54) (-1, _80) 0 ] +EXPR [ (1, _67, _70) (-1, _81) 0 ] +EXPR [ (1, _49, _55) (1, _51, _55) (-1, _82) 0 ] +EXPR [ (2, _6) (1, _16) -7 ] +EXPR [ (-1, _16, _74) (-1, _57, _75) (-1, _83) 15 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(83))], q_c: 0 })] +outputs: [Simple(Witness(84))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _83, _84) (1, _85) -1 ] +EXPR [ (1, _83, _85) 0 ] +EXPR [ (-1, _16, _76) (-1, _57, _77) (-1, _86) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(86))], q_c: 0 })] +outputs: [Simple(Witness(87))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _86, _87) (1, _88) -1 ] +EXPR [ (1, _86, _88) 0 ] +EXPR [ (-1, _16, _78) (-1, _57, _79) (-1, _89) 12 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(89))], q_c: 0 })] +outputs: [Simple(Witness(90))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _89, _90) (1, _91) -1 ] +EXPR [ (1, _89, _91) 0 ] +EXPR [ (1, _85, _88) (-1, _92) 0 ] +EXPR [ (-1, _16, _80) (-1, _57, _81) (-1, _93) 11 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(93))], q_c: 0 })] +outputs: [Simple(Witness(94))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _93, _94) (1, _95) -1 ] +EXPR [ (1, _93, _95) 0 ] +EXPR [ (1, _91, _92) (-1, _96) 0 ] +EXPR [ (-1, _16, _82) (-1, _97) 8 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(97))], q_c: 0 })] +outputs: [Simple(Witness(98))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _97, _98) (1, _99) -1 ] +EXPR [ (1, _97, _99) 0 ] +EXPR [ (1, _95, _96) (-1, _100) 0 ] +EXPR [ (1, _99, _100) -1 ] + diff --git a/test_programs/execution_success/regression/old b/test_programs/execution_success/regression/old new file mode 100644 index 00000000000..2bd4842862d --- /dev/null +++ b/test_programs/execution_success/regression/old @@ -0,0 +1,5180 @@ +Initial SSA: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + v3, v4 = call f1(v0, v1) + inc_rc v3 + inc_rc v3 + v6 = eq v4, Field 5 + constrain v4 == Field 5 + v10 = array_get v3, index Field 0 + v11 = array_get v3, index Field 1 + v13 = array_get v3, index Field 2 + v15 = array_get v3, index Field 3 + v17 = array_get v3, index Field 4 + v25 = allocate + store u1 1 at v25 + jmp b1(Field 0) + b1(v26: Field): + v27 = lt v26, Field 5 + jmpif v27 then: b2, else: b3 + b2(): + v28 = array_get [v10, v11, v13, v15, v17], index v26 + v29 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v26 + v30 = eq v28, v29 + v31 = load v25 + v32 = mul v31, v30 + store v32 at v25 + v33 = add v26, Field 1 + jmp b1(v33) + b3(): + v34 = load v25 + constrain v34 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v57, v58 = call f2([u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], Field 20) + inc_rc v57 + v61 = allocate + store u1 1 at v61 + jmp b4(Field 0) + b4(v62: Field): + v64 = lt v62, Field 2⁵ + jmpif v64 then: b5, else: b6 + b5(): + v65 = array_get v57, index v62 + v66 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v62 + v67 = eq v65, v66 + v68 = load v61 + v69 = mul v68, v67 + store v69 at v61 + v70 = add v62, Field 1 + jmp b4(v70) + b6(): + v71 = load v61 + constrain v71 == u1 1 + v73 = eq v58, Field 21 + constrain v58 == Field 21 + v75 = call f3() + v77 = eq v75, u64 1 + constrain v75 == u64 1 + v79 = call f4() + v81 = eq v79, u64 2⁴ + constrain v79 == u64 2⁴ + v84 = call f5(u64 0) + v85 = eq v84, u64 1 + constrain v84 == u64 1 + v88 = call f5(u64 4) + v89 = eq v88, u64 2⁴ + constrain v88 == u64 2⁴ + return +} +acir fn compact_decode f1 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + v11 = truncate v1 to 64 bits, max_bit_size: 254 + v12 = cast v11 as u64 + inc_rc v0 + v13 = lt u64 5, v12 + v14 = not v13 + constrain v13 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v18 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v18 + v20 = array_get v0, index Field 0 + v31 = div v20, Field 2⁴ + v32 = truncate v31 to 4 bits, max_bit_size: 8 + v33 = cast v32 as u4 + v34 = truncate v33 to 1 bits, max_bit_size: 4 + v35 = cast v34 as u1 + jmpif v35 then: b1, else: b2 + b1(): + v36 = load v18 + v37 = array_get v0, index Field 0 + v39 = and v37, u8 15 + v40 = truncate v39 to 4 bits, max_bit_size: 8 + v41 = cast v40 as u4 + v42 = array_set v36, index Field 0, value v41 + store v42 at v18 + inc_rc v0 + jmp b3(Field 1) + b3(v43: Field): + v44 = lt v43, Field 5 + jmpif v44 then: b4, else: b5 + b4(): + v45 = truncate v43 to 64 bits, max_bit_size: 254 + v46 = cast v45 as u64 + v47 = truncate v1 to 64 bits, max_bit_size: 254 + v48 = cast v47 as u64 + v49 = lt v46, v48 + jmpif v49 then: b6, else: b7 + b6(): + v50 = array_get v0, index v43 + v51 = load v18 + v52 = mul Field 2, v43 + v53 = sub v52, Field 1 + v55 = div v50, Field 2⁴ + v56 = truncate v55 to 4 bits, max_bit_size: 8 + v57 = cast v56 as u4 + v58 = array_set v51, index v53, value v57 + v59 = add v53, Field 1 + store v58 at v18 + v60 = load v18 + v61 = mul Field 2, v43 + v62 = and v50, u8 15 + v63 = truncate v62 to 4 bits, max_bit_size: 8 + v64 = cast v63 as u4 + v65 = array_set v60, index v61, value v64 + v66 = add v61, Field 1 + store v65 at v18 + jmp b7() + b7(): + v67 = add v43, Field 1 + jmp b3(v67) + b5(): + jmp b8() + b8(): + v95 = load v18 + v96 = mul Field 2, v1 + v97 = cast v35 as Field + v98 = add v96, v97 + v99 = sub v98, Field 2 + inc_rc v95 + return v95, v99 + b2(): + jmp b9(u64 0) + b9(v68: u64): + v70 = lt v68, u64 2 + jmpif v70 then: b10, else: b11 + b10(): + v71 = truncate v1 to 64 bits, max_bit_size: 254 + v72 = cast v71 as u64 + v74 = sub v72, u64 1 + range_check v74 to 64 bits + v75 = lt v68, v74 + jmpif v75 then: b12, else: b13 + b12(): + v76 = add v68, u64 1 + range_check v76 to 64 bits + v77 = array_get v0, index v76 + v78 = load v18 + v79 = mul u64 2, v68 + range_check v79 to 64 bits + v81 = div v77, Field 2⁴ + v82 = truncate v81 to 4 bits, max_bit_size: 8 + v83 = cast v82 as u4 + v84 = array_set v78, index v79, value v83 + v85 = add v79, Field 1 + store v84 at v18 + v86 = load v18 + v87 = mul u64 2, v68 + range_check v87 to 64 bits + v88 = add v87, u64 1 + range_check v88 to 64 bits + v89 = and v77, u8 15 + v90 = truncate v89 to 4 bits, max_bit_size: 8 + v91 = cast v90 as u4 + v92 = array_set v86, index v88, value v91 + v93 = add v88, Field 1 + store v92 at v18 + jmp b13() + b13(): + v94 = add v68, Field 1 + jmp b9(v94) + b11(): + jmp b8() +} +acir fn enc f2 { + b0(v0: [u8; 32], v1: Field): + inc_rc v0 + v5 = truncate v1 to 8 bits, max_bit_size: 254 + v6 = cast v5 as u8 + v7 = lt u8 2⁵, v6 + v8 = not v7 + constrain v7 == u1 0 + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v13 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v13 + v15 = eq v1, Field 0 + jmpif v15 then: b1, else: b2 + b1(): + v16 = load v13 + inc_rc v16 + jmp b3(v16, v1) + b3(v41: [u8; 32], v42: Field): + return v41, v42 + b2(): + v17 = truncate v1 to 8 bits, max_bit_size: 254 + v18 = cast v17 as u8 + v20 = lt v18, u8 31 + jmpif v20 then: b4, else: b5 + b4(): + v21 = load v13 + v23 = truncate v1 to 8 bits, max_bit_size: 254 + v24 = cast v23 as u8 + v25 = add u8 2⁷, v24 + range_check v25 to 8 bits + v27 = array_set v21, index Field 0, value v25 + store v27 at v13 + inc_rc v0 + jmp b6(Field 1) + b6(v28: Field): + v29 = lt v28, Field 2⁵ + jmpif v29 then: b7, else: b8 + b7(): + v30 = load v13 + v31 = sub v28, Field 1 + v32 = array_get v0, index v31 + v33 = array_set v30, index v28, value v32 + v34 = add v28, Field 1 + store v33 at v13 + v35 = add v28, Field 1 + jmp b6(v35) + b8(): + v36 = load v13 + v37 = add v1, Field 1 + inc_rc v36 + jmp b9(v36, v37) + b9(v39: [u8; 32], v40: Field): + jmp b3(v39, v40) + b5(): + v38 = load v13 + inc_rc v38 + jmp b9(v38, Field 2⁵) +} +acir fn bitshift_literal_0 f3 { + b0(): + v1 = allocate + store u64 0 at v1 + v2 = load v1 + v7 = or v2, u64 1 + store v7 at v1 + v8 = load v1 + return v8 +} +acir fn bitshift_literal_4 f4 { + b0(): + v1 = allocate + store u64 0 at v1 + v2 = load v1 + v9 = or v2, u64 2⁴ + store v9 at v1 + v10 = load v1 + return v10 +} +acir fn bitshift_variable f5 { + b0(v0: u64): + v2 = allocate + store u64 0 at v2 + v3 = load v2 + v7 = lt v0, u64 2⁶ + v9 = cast v7 as u64 + v12, v13 = call to_le_bits(v0, Field 2⁶) + v16 = array_get v13, index Field 63 + v17 = mul Field 2, v16 + v18 = sub Field 1, v16 + v19 = add v17, v18 + v20 = mul v19, v19 + v21 = mul v20, Field 2 + v23 = array_get v13, index Field 62 + v24 = mul v21, v23 + v25 = sub Field 1, v23 + v26 = mul v25, v20 + v27 = add v24, v26 + v28 = mul v27, v27 + v29 = mul v28, Field 2 + v31 = array_get v13, index Field 61 + v32 = mul v29, v31 + v33 = sub Field 1, v31 + v34 = mul v33, v28 + v35 = add v32, v34 + v36 = mul v35, v35 + v37 = mul v36, Field 2 + v39 = array_get v13, index Field 60 + v40 = mul v37, v39 + v41 = sub Field 1, v39 + v42 = mul v41, v36 + v43 = add v40, v42 + v44 = mul v43, v43 + v45 = mul v44, Field 2 + v47 = array_get v13, index Field 59 + v48 = mul v45, v47 + v49 = sub Field 1, v47 + v50 = mul v49, v44 + v51 = add v48, v50 + v52 = mul v51, v51 + v53 = mul v52, Field 2 + v55 = array_get v13, index Field 58 + v56 = mul v53, v55 + v57 = sub Field 1, v55 + v58 = mul v57, v52 + v59 = add v56, v58 + v60 = mul v59, v59 + v61 = mul v60, Field 2 + v63 = array_get v13, index Field 57 + v64 = mul v61, v63 + v65 = sub Field 1, v63 + v66 = mul v65, v60 + v67 = add v64, v66 + v68 = mul v67, v67 + v69 = mul v68, Field 2 + v71 = array_get v13, index Field 56 + v72 = mul v69, v71 + v73 = sub Field 1, v71 + v74 = mul v73, v68 + v75 = add v72, v74 + v76 = mul v75, v75 + v77 = mul v76, Field 2 + v79 = array_get v13, index Field 55 + v80 = mul v77, v79 + v81 = sub Field 1, v79 + v82 = mul v81, v76 + v83 = add v80, v82 + v84 = mul v83, v83 + v85 = mul v84, Field 2 + v87 = array_get v13, index Field 54 + v88 = mul v85, v87 + v89 = sub Field 1, v87 + v90 = mul v89, v84 + v91 = add v88, v90 + v92 = mul v91, v91 + v93 = mul v92, Field 2 + v95 = array_get v13, index Field 53 + v96 = mul v93, v95 + v97 = sub Field 1, v95 + v98 = mul v97, v92 + v99 = add v96, v98 + v100 = mul v99, v99 + v101 = mul v100, Field 2 + v103 = array_get v13, index Field 52 + v104 = mul v101, v103 + v105 = sub Field 1, v103 + v106 = mul v105, v100 + v107 = add v104, v106 + v108 = mul v107, v107 + v109 = mul v108, Field 2 + v111 = array_get v13, index Field 51 + v112 = mul v109, v111 + v113 = sub Field 1, v111 + v114 = mul v113, v108 + v115 = add v112, v114 + v116 = mul v115, v115 + v117 = mul v116, Field 2 + v119 = array_get v13, index Field 50 + v120 = mul v117, v119 + v121 = sub Field 1, v119 + v122 = mul v121, v116 + v123 = add v120, v122 + v124 = mul v123, v123 + v125 = mul v124, Field 2 + v127 = array_get v13, index Field 49 + v128 = mul v125, v127 + v129 = sub Field 1, v127 + v130 = mul v129, v124 + v131 = add v128, v130 + v132 = mul v131, v131 + v133 = mul v132, Field 2 + v135 = array_get v13, index Field 2⁴×3 + v136 = mul v133, v135 + v137 = sub Field 1, v135 + v138 = mul v137, v132 + v139 = add v136, v138 + v140 = mul v139, v139 + v141 = mul v140, Field 2 + v143 = array_get v13, index Field 47 + v144 = mul v141, v143 + v145 = sub Field 1, v143 + v146 = mul v145, v140 + v147 = add v144, v146 + v148 = mul v147, v147 + v149 = mul v148, Field 2 + v151 = array_get v13, index Field 46 + v152 = mul v149, v151 + v153 = sub Field 1, v151 + v154 = mul v153, v148 + v155 = add v152, v154 + v156 = mul v155, v155 + v157 = mul v156, Field 2 + v159 = array_get v13, index Field 45 + v160 = mul v157, v159 + v161 = sub Field 1, v159 + v162 = mul v161, v156 + v163 = add v160, v162 + v164 = mul v163, v163 + v165 = mul v164, Field 2 + v167 = array_get v13, index Field 44 + v168 = mul v165, v167 + v169 = sub Field 1, v167 + v170 = mul v169, v164 + v171 = add v168, v170 + v172 = mul v171, v171 + v173 = mul v172, Field 2 + v175 = array_get v13, index Field 43 + v176 = mul v173, v175 + v177 = sub Field 1, v175 + v178 = mul v177, v172 + v179 = add v176, v178 + v180 = mul v179, v179 + v181 = mul v180, Field 2 + v183 = array_get v13, index Field 42 + v184 = mul v181, v183 + v185 = sub Field 1, v183 + v186 = mul v185, v180 + v187 = add v184, v186 + v188 = mul v187, v187 + v189 = mul v188, Field 2 + v191 = array_get v13, index Field 41 + v192 = mul v189, v191 + v193 = sub Field 1, v191 + v194 = mul v193, v188 + v195 = add v192, v194 + v196 = mul v195, v195 + v197 = mul v196, Field 2 + v199 = array_get v13, index Field 40 + v200 = mul v197, v199 + v201 = sub Field 1, v199 + v202 = mul v201, v196 + v203 = add v200, v202 + v204 = mul v203, v203 + v205 = mul v204, Field 2 + v207 = array_get v13, index Field 39 + v208 = mul v205, v207 + v209 = sub Field 1, v207 + v210 = mul v209, v204 + v211 = add v208, v210 + v212 = mul v211, v211 + v213 = mul v212, Field 2 + v215 = array_get v13, index Field 38 + v216 = mul v213, v215 + v217 = sub Field 1, v215 + v218 = mul v217, v212 + v219 = add v216, v218 + v220 = mul v219, v219 + v221 = mul v220, Field 2 + v223 = array_get v13, index Field 37 + v224 = mul v221, v223 + v225 = sub Field 1, v223 + v226 = mul v225, v220 + v227 = add v224, v226 + v228 = mul v227, v227 + v229 = mul v228, Field 2 + v231 = array_get v13, index Field 36 + v232 = mul v229, v231 + v233 = sub Field 1, v231 + v234 = mul v233, v228 + v235 = add v232, v234 + v236 = mul v235, v235 + v237 = mul v236, Field 2 + v239 = array_get v13, index Field 35 + v240 = mul v237, v239 + v241 = sub Field 1, v239 + v242 = mul v241, v236 + v243 = add v240, v242 + v244 = mul v243, v243 + v245 = mul v244, Field 2 + v247 = array_get v13, index Field 34 + v248 = mul v245, v247 + v249 = sub Field 1, v247 + v250 = mul v249, v244 + v251 = add v248, v250 + v252 = mul v251, v251 + v253 = mul v252, Field 2 + v255 = array_get v13, index Field 33 + v256 = mul v253, v255 + v257 = sub Field 1, v255 + v258 = mul v257, v252 + v259 = add v256, v258 + v260 = mul v259, v259 + v261 = mul v260, Field 2 + v263 = array_get v13, index Field 2⁵ + v264 = mul v261, v263 + v265 = sub Field 1, v263 + v266 = mul v265, v260 + v267 = add v264, v266 + v268 = mul v267, v267 + v269 = mul v268, Field 2 + v271 = array_get v13, index Field 31 + v272 = mul v269, v271 + v273 = sub Field 1, v271 + v274 = mul v273, v268 + v275 = add v272, v274 + v276 = mul v275, v275 + v277 = mul v276, Field 2 + v279 = array_get v13, index Field 30 + v280 = mul v277, v279 + v281 = sub Field 1, v279 + v282 = mul v281, v276 + v283 = add v280, v282 + v284 = mul v283, v283 + v285 = mul v284, Field 2 + v287 = array_get v13, index Field 29 + v288 = mul v285, v287 + v289 = sub Field 1, v287 + v290 = mul v289, v284 + v291 = add v288, v290 + v292 = mul v291, v291 + v293 = mul v292, Field 2 + v295 = array_get v13, index Field 28 + v296 = mul v293, v295 + v297 = sub Field 1, v295 + v298 = mul v297, v292 + v299 = add v296, v298 + v300 = mul v299, v299 + v301 = mul v300, Field 2 + v303 = array_get v13, index Field 27 + v304 = mul v301, v303 + v305 = sub Field 1, v303 + v306 = mul v305, v300 + v307 = add v304, v306 + v308 = mul v307, v307 + v309 = mul v308, Field 2 + v311 = array_get v13, index Field 26 + v312 = mul v309, v311 + v313 = sub Field 1, v311 + v314 = mul v313, v308 + v315 = add v312, v314 + v316 = mul v315, v315 + v317 = mul v316, Field 2 + v319 = array_get v13, index Field 25 + v320 = mul v317, v319 + v321 = sub Field 1, v319 + v322 = mul v321, v316 + v323 = add v320, v322 + v324 = mul v323, v323 + v325 = mul v324, Field 2 + v327 = array_get v13, index Field 24 + v328 = mul v325, v327 + v329 = sub Field 1, v327 + v330 = mul v329, v324 + v331 = add v328, v330 + v332 = mul v331, v331 + v333 = mul v332, Field 2 + v335 = array_get v13, index Field 23 + v336 = mul v333, v335 + v337 = sub Field 1, v335 + v338 = mul v337, v332 + v339 = add v336, v338 + v340 = mul v339, v339 + v341 = mul v340, Field 2 + v343 = array_get v13, index Field 22 + v344 = mul v341, v343 + v345 = sub Field 1, v343 + v346 = mul v345, v340 + v347 = add v344, v346 + v348 = mul v347, v347 + v349 = mul v348, Field 2 + v351 = array_get v13, index Field 21 + v352 = mul v349, v351 + v353 = sub Field 1, v351 + v354 = mul v353, v348 + v355 = add v352, v354 + v356 = mul v355, v355 + v357 = mul v356, Field 2 + v359 = array_get v13, index Field 20 + v360 = mul v357, v359 + v361 = sub Field 1, v359 + v362 = mul v361, v356 + v363 = add v360, v362 + v364 = mul v363, v363 + v365 = mul v364, Field 2 + v367 = array_get v13, index Field 19 + v368 = mul v365, v367 + v369 = sub Field 1, v367 + v370 = mul v369, v364 + v371 = add v368, v370 + v372 = mul v371, v371 + v373 = mul v372, Field 2 + v375 = array_get v13, index Field 18 + v376 = mul v373, v375 + v377 = sub Field 1, v375 + v378 = mul v377, v372 + v379 = add v376, v378 + v380 = mul v379, v379 + v381 = mul v380, Field 2 + v383 = array_get v13, index Field 17 + v384 = mul v381, v383 + v385 = sub Field 1, v383 + v386 = mul v385, v380 + v387 = add v384, v386 + v388 = mul v387, v387 + v389 = mul v388, Field 2 + v391 = array_get v13, index Field 2⁴ + v392 = mul v389, v391 + v393 = sub Field 1, v391 + v394 = mul v393, v388 + v395 = add v392, v394 + v396 = mul v395, v395 + v397 = mul v396, Field 2 + v399 = array_get v13, index Field 15 + v400 = mul v397, v399 + v401 = sub Field 1, v399 + v402 = mul v401, v396 + v403 = add v400, v402 + v404 = mul v403, v403 + v405 = mul v404, Field 2 + v407 = array_get v13, index Field 14 + v408 = mul v405, v407 + v409 = sub Field 1, v407 + v410 = mul v409, v404 + v411 = add v408, v410 + v412 = mul v411, v411 + v413 = mul v412, Field 2 + v415 = array_get v13, index Field 13 + v416 = mul v413, v415 + v417 = sub Field 1, v415 + v418 = mul v417, v412 + v419 = add v416, v418 + v420 = mul v419, v419 + v421 = mul v420, Field 2 + v423 = array_get v13, index Field 12 + v424 = mul v421, v423 + v425 = sub Field 1, v423 + v426 = mul v425, v420 + v427 = add v424, v426 + v428 = mul v427, v427 + v429 = mul v428, Field 2 + v431 = array_get v13, index Field 11 + v432 = mul v429, v431 + v433 = sub Field 1, v431 + v434 = mul v433, v428 + v435 = add v432, v434 + v436 = mul v435, v435 + v437 = mul v436, Field 2 + v439 = array_get v13, index Field 10 + v440 = mul v437, v439 + v441 = sub Field 1, v439 + v442 = mul v441, v436 + v443 = add v440, v442 + v444 = mul v443, v443 + v445 = mul v444, Field 2 + v447 = array_get v13, index Field 9 + v448 = mul v445, v447 + v449 = sub Field 1, v447 + v450 = mul v449, v444 + v451 = add v448, v450 + v452 = mul v451, v451 + v453 = mul v452, Field 2 + v455 = array_get v13, index Field 8 + v456 = mul v453, v455 + v457 = sub Field 1, v455 + v458 = mul v457, v452 + v459 = add v456, v458 + v460 = mul v459, v459 + v461 = mul v460, Field 2 + v463 = array_get v13, index Field 7 + v464 = mul v461, v463 + v465 = sub Field 1, v463 + v466 = mul v465, v460 + v467 = add v464, v466 + v468 = mul v467, v467 + v469 = mul v468, Field 2 + v471 = array_get v13, index Field 6 + v472 = mul v469, v471 + v473 = sub Field 1, v471 + v474 = mul v473, v468 + v475 = add v472, v474 + v476 = mul v475, v475 + v477 = mul v476, Field 2 + v479 = array_get v13, index Field 5 + v480 = mul v477, v479 + v481 = sub Field 1, v479 + v482 = mul v481, v476 + v483 = add v480, v482 + v484 = mul v483, v483 + v485 = mul v484, Field 2 + v487 = array_get v13, index Field 4 + v488 = mul v485, v487 + v489 = sub Field 1, v487 + v490 = mul v489, v484 + v491 = add v488, v490 + v492 = mul v491, v491 + v493 = mul v492, Field 2 + v495 = array_get v13, index Field 3 + v496 = mul v493, v495 + v497 = sub Field 1, v495 + v498 = mul v497, v492 + v499 = add v496, v498 + v500 = mul v499, v499 + v501 = mul v500, Field 2 + v502 = array_get v13, index Field 2 + v503 = mul v501, v502 + v504 = sub Field 1, v502 + v505 = mul v504, v500 + v506 = add v503, v505 + v507 = mul v506, v506 + v508 = mul v507, Field 2 + v509 = array_get v13, index Field 1 + v510 = mul v508, v509 + v511 = sub Field 1, v509 + v512 = mul v511, v507 + v513 = add v510, v512 + v514 = mul v513, v513 + v515 = mul v514, Field 2 + v517 = array_get v13, index Field 0 + v518 = mul v515, v517 + v519 = sub Field 1, v517 + v520 = mul v519, v514 + v521 = add v518, v520 + v522 = truncate v521 to 64 bits, max_bit_size: 254 + v523 = cast v522 as u64 + v524 = mul v9, v523 + v525 = truncate v524 to 64 bits, max_bit_size: 254 + v526 = lt v0, u64 2⁶ + constrain v526 == u1 1 'attempt to bit-shift with overflow' + v527 = or v3, v525 + store v527 at v2 + v528 = load v2 + return v528 +} + +After Defunctionalization: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + v3, v4 = call f1(v0, v1) + inc_rc v3 + inc_rc v3 + v6 = eq v4, Field 5 + constrain v4 == Field 5 + v10 = array_get v3, index Field 0 + v11 = array_get v3, index Field 1 + v13 = array_get v3, index Field 2 + v15 = array_get v3, index Field 3 + v17 = array_get v3, index Field 4 + v25 = allocate + store u1 1 at v25 + jmp b1(Field 0) + b1(v26: Field): + v27 = lt v26, Field 5 + jmpif v27 then: b2, else: b3 + b2(): + v28 = array_get [v10, v11, v13, v15, v17], index v26 + v29 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v26 + v30 = eq v28, v29 + v31 = load v25 + v32 = mul v31, v30 + store v32 at v25 + v33 = add v26, Field 1 + jmp b1(v33) + b3(): + v34 = load v25 + constrain v34 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v57, v58 = call f2([u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], Field 20) + inc_rc v57 + v61 = allocate + store u1 1 at v61 + jmp b4(Field 0) + b4(v62: Field): + v64 = lt v62, Field 2⁵ + jmpif v64 then: b5, else: b6 + b5(): + v65 = array_get v57, index v62 + v66 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v62 + v67 = eq v65, v66 + v68 = load v61 + v69 = mul v68, v67 + store v69 at v61 + v70 = add v62, Field 1 + jmp b4(v70) + b6(): + v71 = load v61 + constrain v71 == u1 1 + v73 = eq v58, Field 21 + constrain v58 == Field 21 + v75 = call f3() + v77 = eq v75, u64 1 + constrain v75 == u64 1 + v79 = call f4() + v81 = eq v79, u64 2⁴ + constrain v79 == u64 2⁴ + v84 = call f5(u64 0) + v85 = eq v84, u64 1 + constrain v84 == u64 1 + v88 = call f5(u64 4) + v89 = eq v88, u64 2⁴ + constrain v88 == u64 2⁴ + return +} +acir fn compact_decode f1 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + v11 = truncate v1 to 64 bits, max_bit_size: 254 + v12 = cast v11 as u64 + inc_rc v0 + v13 = lt u64 5, v12 + v14 = not v13 + constrain v13 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v18 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v18 + v20 = array_get v0, index Field 0 + v31 = div v20, Field 2⁴ + v32 = truncate v31 to 4 bits, max_bit_size: 8 + v33 = cast v32 as u4 + v34 = truncate v33 to 1 bits, max_bit_size: 4 + v35 = cast v34 as u1 + jmpif v35 then: b1, else: b2 + b1(): + v36 = load v18 + v37 = array_get v0, index Field 0 + v39 = and v37, u8 15 + v40 = truncate v39 to 4 bits, max_bit_size: 8 + v41 = cast v40 as u4 + v42 = array_set v36, index Field 0, value v41 + store v42 at v18 + inc_rc v0 + jmp b3(Field 1) + b3(v43: Field): + v44 = lt v43, Field 5 + jmpif v44 then: b4, else: b5 + b4(): + v45 = truncate v43 to 64 bits, max_bit_size: 254 + v46 = cast v45 as u64 + v47 = truncate v1 to 64 bits, max_bit_size: 254 + v48 = cast v47 as u64 + v49 = lt v46, v48 + jmpif v49 then: b6, else: b7 + b6(): + v50 = array_get v0, index v43 + v51 = load v18 + v52 = mul Field 2, v43 + v53 = sub v52, Field 1 + v55 = div v50, Field 2⁴ + v56 = truncate v55 to 4 bits, max_bit_size: 8 + v57 = cast v56 as u4 + v58 = array_set v51, index v53, value v57 + v59 = add v53, Field 1 + store v58 at v18 + v60 = load v18 + v61 = mul Field 2, v43 + v62 = and v50, u8 15 + v63 = truncate v62 to 4 bits, max_bit_size: 8 + v64 = cast v63 as u4 + v65 = array_set v60, index v61, value v64 + v66 = add v61, Field 1 + store v65 at v18 + jmp b7() + b7(): + v67 = add v43, Field 1 + jmp b3(v67) + b5(): + jmp b8() + b8(): + v95 = load v18 + v96 = mul Field 2, v1 + v97 = cast v35 as Field + v98 = add v96, v97 + v99 = sub v98, Field 2 + inc_rc v95 + return v95, v99 + b2(): + jmp b9(u64 0) + b9(v68: u64): + v70 = lt v68, u64 2 + jmpif v70 then: b10, else: b11 + b10(): + v71 = truncate v1 to 64 bits, max_bit_size: 254 + v72 = cast v71 as u64 + v74 = sub v72, u64 1 + range_check v74 to 64 bits + v75 = lt v68, v74 + jmpif v75 then: b12, else: b13 + b12(): + v76 = add v68, u64 1 + range_check v76 to 64 bits + v77 = array_get v0, index v76 + v78 = load v18 + v79 = mul u64 2, v68 + range_check v79 to 64 bits + v81 = div v77, Field 2⁴ + v82 = truncate v81 to 4 bits, max_bit_size: 8 + v83 = cast v82 as u4 + v84 = array_set v78, index v79, value v83 + v85 = add v79, Field 1 + store v84 at v18 + v86 = load v18 + v87 = mul u64 2, v68 + range_check v87 to 64 bits + v88 = add v87, u64 1 + range_check v88 to 64 bits + v89 = and v77, u8 15 + v90 = truncate v89 to 4 bits, max_bit_size: 8 + v91 = cast v90 as u4 + v92 = array_set v86, index v88, value v91 + v93 = add v88, Field 1 + store v92 at v18 + jmp b13() + b13(): + v94 = add v68, Field 1 + jmp b9(v94) + b11(): + jmp b8() +} +acir fn enc f2 { + b0(v0: [u8; 32], v1: Field): + inc_rc v0 + v5 = truncate v1 to 8 bits, max_bit_size: 254 + v6 = cast v5 as u8 + v7 = lt u8 2⁵, v6 + v8 = not v7 + constrain v7 == u1 0 + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v13 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v13 + v15 = eq v1, Field 0 + jmpif v15 then: b1, else: b2 + b1(): + v16 = load v13 + inc_rc v16 + jmp b3(v16, v1) + b3(v41: [u8; 32], v42: Field): + return v41, v42 + b2(): + v17 = truncate v1 to 8 bits, max_bit_size: 254 + v18 = cast v17 as u8 + v20 = lt v18, u8 31 + jmpif v20 then: b4, else: b5 + b4(): + v21 = load v13 + v23 = truncate v1 to 8 bits, max_bit_size: 254 + v24 = cast v23 as u8 + v25 = add u8 2⁷, v24 + range_check v25 to 8 bits + v27 = array_set v21, index Field 0, value v25 + store v27 at v13 + inc_rc v0 + jmp b6(Field 1) + b6(v28: Field): + v29 = lt v28, Field 2⁵ + jmpif v29 then: b7, else: b8 + b7(): + v30 = load v13 + v31 = sub v28, Field 1 + v32 = array_get v0, index v31 + v33 = array_set v30, index v28, value v32 + v34 = add v28, Field 1 + store v33 at v13 + v35 = add v28, Field 1 + jmp b6(v35) + b8(): + v36 = load v13 + v37 = add v1, Field 1 + inc_rc v36 + jmp b9(v36, v37) + b9(v39: [u8; 32], v40: Field): + jmp b3(v39, v40) + b5(): + v38 = load v13 + inc_rc v38 + jmp b9(v38, Field 2⁵) +} +acir fn bitshift_literal_0 f3 { + b0(): + v1 = allocate + store u64 0 at v1 + v2 = load v1 + v7 = or v2, u64 1 + store v7 at v1 + v8 = load v1 + return v8 +} +acir fn bitshift_literal_4 f4 { + b0(): + v1 = allocate + store u64 0 at v1 + v2 = load v1 + v9 = or v2, u64 2⁴ + store v9 at v1 + v10 = load v1 + return v10 +} +acir fn bitshift_variable f5 { + b0(v0: u64): + v2 = allocate + store u64 0 at v2 + v3 = load v2 + v7 = lt v0, u64 2⁶ + v9 = cast v7 as u64 + v12, v13 = call to_le_bits(v0, Field 2⁶) + v16 = array_get v13, index Field 63 + v17 = mul Field 2, v16 + v18 = sub Field 1, v16 + v19 = add v17, v18 + v20 = mul v19, v19 + v21 = mul v20, Field 2 + v23 = array_get v13, index Field 62 + v24 = mul v21, v23 + v25 = sub Field 1, v23 + v26 = mul v25, v20 + v27 = add v24, v26 + v28 = mul v27, v27 + v29 = mul v28, Field 2 + v31 = array_get v13, index Field 61 + v32 = mul v29, v31 + v33 = sub Field 1, v31 + v34 = mul v33, v28 + v35 = add v32, v34 + v36 = mul v35, v35 + v37 = mul v36, Field 2 + v39 = array_get v13, index Field 60 + v40 = mul v37, v39 + v41 = sub Field 1, v39 + v42 = mul v41, v36 + v43 = add v40, v42 + v44 = mul v43, v43 + v45 = mul v44, Field 2 + v47 = array_get v13, index Field 59 + v48 = mul v45, v47 + v49 = sub Field 1, v47 + v50 = mul v49, v44 + v51 = add v48, v50 + v52 = mul v51, v51 + v53 = mul v52, Field 2 + v55 = array_get v13, index Field 58 + v56 = mul v53, v55 + v57 = sub Field 1, v55 + v58 = mul v57, v52 + v59 = add v56, v58 + v60 = mul v59, v59 + v61 = mul v60, Field 2 + v63 = array_get v13, index Field 57 + v64 = mul v61, v63 + v65 = sub Field 1, v63 + v66 = mul v65, v60 + v67 = add v64, v66 + v68 = mul v67, v67 + v69 = mul v68, Field 2 + v71 = array_get v13, index Field 56 + v72 = mul v69, v71 + v73 = sub Field 1, v71 + v74 = mul v73, v68 + v75 = add v72, v74 + v76 = mul v75, v75 + v77 = mul v76, Field 2 + v79 = array_get v13, index Field 55 + v80 = mul v77, v79 + v81 = sub Field 1, v79 + v82 = mul v81, v76 + v83 = add v80, v82 + v84 = mul v83, v83 + v85 = mul v84, Field 2 + v87 = array_get v13, index Field 54 + v88 = mul v85, v87 + v89 = sub Field 1, v87 + v90 = mul v89, v84 + v91 = add v88, v90 + v92 = mul v91, v91 + v93 = mul v92, Field 2 + v95 = array_get v13, index Field 53 + v96 = mul v93, v95 + v97 = sub Field 1, v95 + v98 = mul v97, v92 + v99 = add v96, v98 + v100 = mul v99, v99 + v101 = mul v100, Field 2 + v103 = array_get v13, index Field 52 + v104 = mul v101, v103 + v105 = sub Field 1, v103 + v106 = mul v105, v100 + v107 = add v104, v106 + v108 = mul v107, v107 + v109 = mul v108, Field 2 + v111 = array_get v13, index Field 51 + v112 = mul v109, v111 + v113 = sub Field 1, v111 + v114 = mul v113, v108 + v115 = add v112, v114 + v116 = mul v115, v115 + v117 = mul v116, Field 2 + v119 = array_get v13, index Field 50 + v120 = mul v117, v119 + v121 = sub Field 1, v119 + v122 = mul v121, v116 + v123 = add v120, v122 + v124 = mul v123, v123 + v125 = mul v124, Field 2 + v127 = array_get v13, index Field 49 + v128 = mul v125, v127 + v129 = sub Field 1, v127 + v130 = mul v129, v124 + v131 = add v128, v130 + v132 = mul v131, v131 + v133 = mul v132, Field 2 + v135 = array_get v13, index Field 2⁴×3 + v136 = mul v133, v135 + v137 = sub Field 1, v135 + v138 = mul v137, v132 + v139 = add v136, v138 + v140 = mul v139, v139 + v141 = mul v140, Field 2 + v143 = array_get v13, index Field 47 + v144 = mul v141, v143 + v145 = sub Field 1, v143 + v146 = mul v145, v140 + v147 = add v144, v146 + v148 = mul v147, v147 + v149 = mul v148, Field 2 + v151 = array_get v13, index Field 46 + v152 = mul v149, v151 + v153 = sub Field 1, v151 + v154 = mul v153, v148 + v155 = add v152, v154 + v156 = mul v155, v155 + v157 = mul v156, Field 2 + v159 = array_get v13, index Field 45 + v160 = mul v157, v159 + v161 = sub Field 1, v159 + v162 = mul v161, v156 + v163 = add v160, v162 + v164 = mul v163, v163 + v165 = mul v164, Field 2 + v167 = array_get v13, index Field 44 + v168 = mul v165, v167 + v169 = sub Field 1, v167 + v170 = mul v169, v164 + v171 = add v168, v170 + v172 = mul v171, v171 + v173 = mul v172, Field 2 + v175 = array_get v13, index Field 43 + v176 = mul v173, v175 + v177 = sub Field 1, v175 + v178 = mul v177, v172 + v179 = add v176, v178 + v180 = mul v179, v179 + v181 = mul v180, Field 2 + v183 = array_get v13, index Field 42 + v184 = mul v181, v183 + v185 = sub Field 1, v183 + v186 = mul v185, v180 + v187 = add v184, v186 + v188 = mul v187, v187 + v189 = mul v188, Field 2 + v191 = array_get v13, index Field 41 + v192 = mul v189, v191 + v193 = sub Field 1, v191 + v194 = mul v193, v188 + v195 = add v192, v194 + v196 = mul v195, v195 + v197 = mul v196, Field 2 + v199 = array_get v13, index Field 40 + v200 = mul v197, v199 + v201 = sub Field 1, v199 + v202 = mul v201, v196 + v203 = add v200, v202 + v204 = mul v203, v203 + v205 = mul v204, Field 2 + v207 = array_get v13, index Field 39 + v208 = mul v205, v207 + v209 = sub Field 1, v207 + v210 = mul v209, v204 + v211 = add v208, v210 + v212 = mul v211, v211 + v213 = mul v212, Field 2 + v215 = array_get v13, index Field 38 + v216 = mul v213, v215 + v217 = sub Field 1, v215 + v218 = mul v217, v212 + v219 = add v216, v218 + v220 = mul v219, v219 + v221 = mul v220, Field 2 + v223 = array_get v13, index Field 37 + v224 = mul v221, v223 + v225 = sub Field 1, v223 + v226 = mul v225, v220 + v227 = add v224, v226 + v228 = mul v227, v227 + v229 = mul v228, Field 2 + v231 = array_get v13, index Field 36 + v232 = mul v229, v231 + v233 = sub Field 1, v231 + v234 = mul v233, v228 + v235 = add v232, v234 + v236 = mul v235, v235 + v237 = mul v236, Field 2 + v239 = array_get v13, index Field 35 + v240 = mul v237, v239 + v241 = sub Field 1, v239 + v242 = mul v241, v236 + v243 = add v240, v242 + v244 = mul v243, v243 + v245 = mul v244, Field 2 + v247 = array_get v13, index Field 34 + v248 = mul v245, v247 + v249 = sub Field 1, v247 + v250 = mul v249, v244 + v251 = add v248, v250 + v252 = mul v251, v251 + v253 = mul v252, Field 2 + v255 = array_get v13, index Field 33 + v256 = mul v253, v255 + v257 = sub Field 1, v255 + v258 = mul v257, v252 + v259 = add v256, v258 + v260 = mul v259, v259 + v261 = mul v260, Field 2 + v263 = array_get v13, index Field 2⁵ + v264 = mul v261, v263 + v265 = sub Field 1, v263 + v266 = mul v265, v260 + v267 = add v264, v266 + v268 = mul v267, v267 + v269 = mul v268, Field 2 + v271 = array_get v13, index Field 31 + v272 = mul v269, v271 + v273 = sub Field 1, v271 + v274 = mul v273, v268 + v275 = add v272, v274 + v276 = mul v275, v275 + v277 = mul v276, Field 2 + v279 = array_get v13, index Field 30 + v280 = mul v277, v279 + v281 = sub Field 1, v279 + v282 = mul v281, v276 + v283 = add v280, v282 + v284 = mul v283, v283 + v285 = mul v284, Field 2 + v287 = array_get v13, index Field 29 + v288 = mul v285, v287 + v289 = sub Field 1, v287 + v290 = mul v289, v284 + v291 = add v288, v290 + v292 = mul v291, v291 + v293 = mul v292, Field 2 + v295 = array_get v13, index Field 28 + v296 = mul v293, v295 + v297 = sub Field 1, v295 + v298 = mul v297, v292 + v299 = add v296, v298 + v300 = mul v299, v299 + v301 = mul v300, Field 2 + v303 = array_get v13, index Field 27 + v304 = mul v301, v303 + v305 = sub Field 1, v303 + v306 = mul v305, v300 + v307 = add v304, v306 + v308 = mul v307, v307 + v309 = mul v308, Field 2 + v311 = array_get v13, index Field 26 + v312 = mul v309, v311 + v313 = sub Field 1, v311 + v314 = mul v313, v308 + v315 = add v312, v314 + v316 = mul v315, v315 + v317 = mul v316, Field 2 + v319 = array_get v13, index Field 25 + v320 = mul v317, v319 + v321 = sub Field 1, v319 + v322 = mul v321, v316 + v323 = add v320, v322 + v324 = mul v323, v323 + v325 = mul v324, Field 2 + v327 = array_get v13, index Field 24 + v328 = mul v325, v327 + v329 = sub Field 1, v327 + v330 = mul v329, v324 + v331 = add v328, v330 + v332 = mul v331, v331 + v333 = mul v332, Field 2 + v335 = array_get v13, index Field 23 + v336 = mul v333, v335 + v337 = sub Field 1, v335 + v338 = mul v337, v332 + v339 = add v336, v338 + v340 = mul v339, v339 + v341 = mul v340, Field 2 + v343 = array_get v13, index Field 22 + v344 = mul v341, v343 + v345 = sub Field 1, v343 + v346 = mul v345, v340 + v347 = add v344, v346 + v348 = mul v347, v347 + v349 = mul v348, Field 2 + v351 = array_get v13, index Field 21 + v352 = mul v349, v351 + v353 = sub Field 1, v351 + v354 = mul v353, v348 + v355 = add v352, v354 + v356 = mul v355, v355 + v357 = mul v356, Field 2 + v359 = array_get v13, index Field 20 + v360 = mul v357, v359 + v361 = sub Field 1, v359 + v362 = mul v361, v356 + v363 = add v360, v362 + v364 = mul v363, v363 + v365 = mul v364, Field 2 + v367 = array_get v13, index Field 19 + v368 = mul v365, v367 + v369 = sub Field 1, v367 + v370 = mul v369, v364 + v371 = add v368, v370 + v372 = mul v371, v371 + v373 = mul v372, Field 2 + v375 = array_get v13, index Field 18 + v376 = mul v373, v375 + v377 = sub Field 1, v375 + v378 = mul v377, v372 + v379 = add v376, v378 + v380 = mul v379, v379 + v381 = mul v380, Field 2 + v383 = array_get v13, index Field 17 + v384 = mul v381, v383 + v385 = sub Field 1, v383 + v386 = mul v385, v380 + v387 = add v384, v386 + v388 = mul v387, v387 + v389 = mul v388, Field 2 + v391 = array_get v13, index Field 2⁴ + v392 = mul v389, v391 + v393 = sub Field 1, v391 + v394 = mul v393, v388 + v395 = add v392, v394 + v396 = mul v395, v395 + v397 = mul v396, Field 2 + v399 = array_get v13, index Field 15 + v400 = mul v397, v399 + v401 = sub Field 1, v399 + v402 = mul v401, v396 + v403 = add v400, v402 + v404 = mul v403, v403 + v405 = mul v404, Field 2 + v407 = array_get v13, index Field 14 + v408 = mul v405, v407 + v409 = sub Field 1, v407 + v410 = mul v409, v404 + v411 = add v408, v410 + v412 = mul v411, v411 + v413 = mul v412, Field 2 + v415 = array_get v13, index Field 13 + v416 = mul v413, v415 + v417 = sub Field 1, v415 + v418 = mul v417, v412 + v419 = add v416, v418 + v420 = mul v419, v419 + v421 = mul v420, Field 2 + v423 = array_get v13, index Field 12 + v424 = mul v421, v423 + v425 = sub Field 1, v423 + v426 = mul v425, v420 + v427 = add v424, v426 + v428 = mul v427, v427 + v429 = mul v428, Field 2 + v431 = array_get v13, index Field 11 + v432 = mul v429, v431 + v433 = sub Field 1, v431 + v434 = mul v433, v428 + v435 = add v432, v434 + v436 = mul v435, v435 + v437 = mul v436, Field 2 + v439 = array_get v13, index Field 10 + v440 = mul v437, v439 + v441 = sub Field 1, v439 + v442 = mul v441, v436 + v443 = add v440, v442 + v444 = mul v443, v443 + v445 = mul v444, Field 2 + v447 = array_get v13, index Field 9 + v448 = mul v445, v447 + v449 = sub Field 1, v447 + v450 = mul v449, v444 + v451 = add v448, v450 + v452 = mul v451, v451 + v453 = mul v452, Field 2 + v455 = array_get v13, index Field 8 + v456 = mul v453, v455 + v457 = sub Field 1, v455 + v458 = mul v457, v452 + v459 = add v456, v458 + v460 = mul v459, v459 + v461 = mul v460, Field 2 + v463 = array_get v13, index Field 7 + v464 = mul v461, v463 + v465 = sub Field 1, v463 + v466 = mul v465, v460 + v467 = add v464, v466 + v468 = mul v467, v467 + v469 = mul v468, Field 2 + v471 = array_get v13, index Field 6 + v472 = mul v469, v471 + v473 = sub Field 1, v471 + v474 = mul v473, v468 + v475 = add v472, v474 + v476 = mul v475, v475 + v477 = mul v476, Field 2 + v479 = array_get v13, index Field 5 + v480 = mul v477, v479 + v481 = sub Field 1, v479 + v482 = mul v481, v476 + v483 = add v480, v482 + v484 = mul v483, v483 + v485 = mul v484, Field 2 + v487 = array_get v13, index Field 4 + v488 = mul v485, v487 + v489 = sub Field 1, v487 + v490 = mul v489, v484 + v491 = add v488, v490 + v492 = mul v491, v491 + v493 = mul v492, Field 2 + v495 = array_get v13, index Field 3 + v496 = mul v493, v495 + v497 = sub Field 1, v495 + v498 = mul v497, v492 + v499 = add v496, v498 + v500 = mul v499, v499 + v501 = mul v500, Field 2 + v502 = array_get v13, index Field 2 + v503 = mul v501, v502 + v504 = sub Field 1, v502 + v505 = mul v504, v500 + v506 = add v503, v505 + v507 = mul v506, v506 + v508 = mul v507, Field 2 + v509 = array_get v13, index Field 1 + v510 = mul v508, v509 + v511 = sub Field 1, v509 + v512 = mul v511, v507 + v513 = add v510, v512 + v514 = mul v513, v513 + v515 = mul v514, Field 2 + v517 = array_get v13, index Field 0 + v518 = mul v515, v517 + v519 = sub Field 1, v517 + v520 = mul v519, v514 + v521 = add v518, v520 + v522 = truncate v521 to 64 bits, max_bit_size: 254 + v523 = cast v522 as u64 + v524 = mul v9, v523 + v525 = truncate v524 to 64 bits, max_bit_size: 254 + v526 = lt v0, u64 2⁶ + constrain v526 == u1 1 'attempt to bit-shift with overflow' + v527 = or v3, v525 + store v527 at v2 + v528 = load v2 + return v528 +} + +After Inlining: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v3 = truncate v1 to 64 bits, max_bit_size: 254 + v4 = cast v3 as u64 + inc_rc v0 + v6 = lt u64 5, v4 + v7 = not v6 + constrain v6 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v11 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v11 + v13 = array_get v0, index Field 0 + v15 = div v13, Field 2⁴ + v16 = truncate v15 to 4 bits, max_bit_size: 8 + v17 = cast v16 as u4 + v18 = truncate v17 to 1 bits, max_bit_size: 4 + v19 = cast v18 as u1 + jmpif v19 then: b1, else: b2 + b1(): + v55 = load v11 + v56 = array_get v0, index Field 0 + v57 = and v56, u8 15 + v58 = truncate v57 to 4 bits, max_bit_size: 8 + v59 = cast v58 as u4 + v60 = array_set v55, index Field 0, value v59 + store v60 at v11 + inc_rc v0 + jmp b9(Field 1) + b9(v61: Field): + v63 = lt v61, Field 5 + jmpif v63 then: b10, else: b11 + b10(): + v64 = truncate v61 to 64 bits, max_bit_size: 254 + v65 = cast v64 as u64 + v66 = truncate v1 to 64 bits, max_bit_size: 254 + v67 = cast v66 as u64 + v68 = lt v65, v67 + jmpif v68 then: b12, else: b13 + b12(): + v70 = array_get v0, index v61 + v71 = load v11 + v72 = mul Field 2, v61 + v73 = sub v72, Field 1 + v74 = div v70, Field 2⁴ + v75 = truncate v74 to 4 bits, max_bit_size: 8 + v76 = cast v75 as u4 + v77 = array_set v71, index v73, value v76 + v78 = add v73, Field 1 + store v77 at v11 + v79 = load v11 + v80 = mul Field 2, v61 + v81 = and v70, u8 15 + v82 = truncate v81 to 4 bits, max_bit_size: 8 + v83 = cast v82 as u4 + v84 = array_set v79, index v80, value v83 + v85 = add v80, Field 1 + store v84 at v11 + jmp b13() + b13(): + v69 = add v61, Field 1 + jmp b9(v69) + b11(): + jmp b6() + b6(): + v24 = load v11 + v26 = mul Field 2, v1 + v27 = cast v19 as Field + v28 = add v26, v27 + v29 = sub v28, Field 2 + inc_rc v24 + inc_rc v24 + inc_rc v24 + v86 = eq v29, Field 5 + constrain v29 == Field 5 + v87 = array_get v24, index Field 0 + v88 = array_get v24, index Field 1 + v89 = array_get v24, index Field 2 + v91 = array_get v24, index Field 3 + v93 = array_get v24, index Field 4 + v94 = allocate + store u1 1 at v94 + jmp b14(Field 0) + b14(v96: Field): + v97 = lt v96, Field 5 + jmpif v97 then: b15, else: b16 + b15(): + v242 = array_get [v87, v88, v89, v91, v93], index v96 + v249 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v96 + v250 = eq v242, v249 + v251 = load v94 + v252 = mul v251, v250 + store v252 at v94 + v253 = add v96, Field 1 + jmp b14(v253) + b16(): + v98 = load v94 + constrain v98 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v124 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v124 + jmp b17() + b17(): + jmp b18() + b18(): + v126 = load v124 + range_check u8 148 to 8 bits + v128 = array_set v126, index Field 0, value u8 148 + store v128 at v124 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + jmp b19(Field 1) + b19(v129: Field): + v131 = lt v129, Field 2⁵ + jmpif v131 then: b20, else: b21 + b20(): + v138 = load v124 + v139 = sub v129, Field 1 + v140 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v139 + v141 = array_set v138, index v129, value v140 + v142 = add v129, Field 1 + store v141 at v124 + v143 = add v129, Field 1 + jmp b19(v143) + b21(): + v132 = load v124 + inc_rc v132 + jmp b22(v132, Field 21) + b22(v134: [u8; 32], v135: Field): + jmp b23(v134, v135) + b23(v136: [u8; 32], v137: Field): + inc_rc v136 + v144 = allocate + store u1 1 at v144 + jmp b24(Field 0) + b24(v145: Field): + v146 = lt v145, Field 2⁵ + jmpif v146 then: b25, else: b26 + b25(): + v234 = array_get v136, index v145 + v236 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v145 + v237 = eq v234, v236 + v238 = load v144 + v239 = mul v238, v237 + store v239 at v144 + v240 = add v145, Field 1 + jmp b24(v240) + b26(): + v147 = load v144 + constrain v147 == u1 1 + v148 = eq v137, Field 21 + constrain v137 == Field 21 + v150 = allocate + store u64 0 at v150 + v151 = load v150 + v152 = or v151, u64 1 + store v152 at v150 + v153 = load v150 + v154 = eq v153, u64 1 + constrain v153 == u64 1 + v156 = allocate + store u64 0 at v156 + v157 = load v156 + v159 = or v157, u64 2⁴ + store v159 at v156 + v160 = load v156 + v161 = eq v160, u64 2⁴ + constrain v160 == u64 2⁴ + v163 = allocate + store u64 0 at v163 + v164 = load v163 + v223 = or v164, u64 1 + store v223 at v163 + v224 = load v163 + v225 = eq v224, u64 1 + constrain v224 == u64 1 + v228 = allocate + store u64 0 at v228 + v229 = load v228 + v231 = or v229, u64 2⁴ + store v231 at v228 + v232 = load v228 + v233 = eq v232, u64 2⁴ + constrain v232 == u64 2⁴ + return + b2(): + jmp b3(u64 0) + b3(v20: u64): + v23 = lt v20, u64 2 + jmpif v23 then: b4, else: b5 + b4(): + v30 = truncate v1 to 64 bits, max_bit_size: 254 + v31 = cast v30 as u64 + v33 = sub v31, u64 1 + range_check v33 to 64 bits + v34 = lt v20, v33 + jmpif v34 then: b7, else: b8 + b7(): + v37 = add v20, u64 1 + range_check v37 to 64 bits + v38 = array_get v0, index v37 + v39 = load v11 + v40 = mul u64 2, v20 + range_check v40 to 64 bits + v41 = div v38, Field 2⁴ + v42 = truncate v41 to 4 bits, max_bit_size: 8 + v43 = cast v42 as u4 + v44 = array_set v39, index v40, value v43 + v45 = add v40, Field 1 + store v44 at v11 + v46 = load v11 + v47 = mul u64 2, v20 + range_check v47 to 64 bits + v48 = add v47, u64 1 + range_check v48 to 64 bits + v50 = and v38, u8 15 + v51 = truncate v50 to 4 bits, max_bit_size: 8 + v52 = cast v51 as u4 + v53 = array_set v46, index v48, value v52 + v54 = add v48, Field 1 + store v53 at v11 + jmp b8() + b8(): + v36 = add v20, Field 1 + jmp b3(v36) + b5(): + jmp b6() +} + +After Mem2Reg: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v254 = truncate v1 to 64 bits, max_bit_size: 254 + v255 = cast v254 as u64 + inc_rc v0 + v256 = lt u64 5, v255 + v257 = not v256 + constrain v256 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v259 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 + v261 = array_get v0, index Field 0 + v262 = div v261, Field 2⁴ + v263 = truncate v262 to 4 bits, max_bit_size: 8 + v264 = cast v263 as u4 + v265 = truncate v264 to 1 bits, max_bit_size: 4 + v266 = cast v265 as u1 + jmpif v266 then: b1, else: b2 + b1(): + v291 = array_get v0, index Field 0 + v292 = and v291, u8 15 + v293 = truncate v292 to 4 bits, max_bit_size: 8 + v294 = cast v293 as u4 + store [v294, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 + inc_rc v0 + jmp b9(Field 1) + b9(v61: Field): + v298 = lt v61, Field 5 + jmpif v298 then: b10, else: b11 + b10(): + v364 = truncate v61 to 64 bits, max_bit_size: 254 + v365 = cast v364 as u64 + v366 = truncate v1 to 64 bits, max_bit_size: 254 + v367 = cast v366 as u64 + v368 = lt v365, v367 + jmpif v368 then: b12, else: b13 + b12(): + v369 = array_get v0, index v61 + v370 = load v259 + v371 = mul Field 2, v61 + v372 = sub v371, Field 1 + v373 = div v369, Field 2⁴ + v374 = truncate v373 to 4 bits, max_bit_size: 8 + v375 = cast v374 as u4 + v376 = array_set v370, index v372, value v375 + v377 = add v372, Field 1 + v379 = mul Field 2, v61 + v380 = and v369, u8 15 + v381 = truncate v380 to 4 bits, max_bit_size: 8 + v382 = cast v381 as u4 + v383 = array_set v376, index v379, value v382 + v384 = add v379, Field 1 + store v383 at v259 + jmp b13() + b13(): + v385 = add v61, Field 1 + jmp b9(v385) + b11(): + jmp b6() + b6(): + v299 = load v259 + v300 = mul Field 2, v1 + v301 = cast v266 as Field + v302 = add v300, v301 + v303 = sub v302, Field 2 + inc_rc v299 + inc_rc v299 + inc_rc v299 + v304 = eq v303, Field 5 + constrain v303 == Field 5 + v305 = array_get v299, index Field 0 + v306 = array_get v299, index Field 1 + v307 = array_get v299, index Field 2 + v308 = array_get v299, index Field 3 + v309 = array_get v299, index Field 4 + v310 = allocate + store u1 1 at v310 + jmp b14(Field 0) + b14(v96: Field): + v311 = lt v96, Field 5 + jmpif v311 then: b15, else: b16 + b15(): + v357 = array_get [v305, v306, v307, v308, v309], index v96 + v359 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v96 + v360 = eq v357, v359 + v361 = load v310 + v362 = mul v361, v360 + store v362 at v310 + v363 = add v96, Field 1 + jmp b14(v363) + b16(): + v312 = load v310 + constrain v312 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v317 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 + jmp b17() + b17(): + jmp b18() + b18(): + range_check u8 148 to 8 bits + store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + jmp b19(Field 1) + b19(v129: Field): + v324 = lt v129, Field 2⁵ + jmpif v324 then: b20, else: b21 + b20(): + v349 = load v317 + v350 = sub v129, Field 1 + v352 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v350 + v353 = array_set v349, index v129, value v352 + v354 = add v129, Field 1 + store v353 at v317 + v355 = add v129, Field 1 + jmp b19(v355) + b21(): + v325 = load v317 + inc_rc v325 + jmp b22(v325, Field 21) + b22(v134: [u8; 32], v135: Field): + jmp b23(v134, v135) + b23(v136: [u8; 32], v137: Field): + inc_rc v136 + v326 = allocate + store u1 1 at v326 + jmp b24(Field 0) + b24(v145: Field): + v327 = lt v145, Field 2⁵ + jmpif v327 then: b25, else: b26 + b25(): + v342 = array_get v136, index v145 + v344 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v145 + v345 = eq v342, v344 + v346 = load v326 + v347 = mul v346, v345 + store v347 at v326 + v348 = add v145, Field 1 + jmp b24(v348) + b26(): + v328 = load v326 + constrain v328 == u1 1 + v329 = eq v137, Field 21 + constrain v137 == Field 21 + v330 = allocate + store u64 1 at v330 + v333 = allocate + store u64 2⁴ at v333 + v336 = allocate + store u64 1 at v336 + v339 = allocate + store u64 2⁴ at v339 + return + b2(): + jmp b3(u64 0) + b3(v20: u64): + v267 = lt v20, u64 2 + jmpif v267 then: b4, else: b5 + b4(): + v268 = truncate v1 to 64 bits, max_bit_size: 254 + v269 = cast v268 as u64 + v270 = sub v269, u64 1 + range_check v270 to 64 bits + v271 = lt v20, v270 + jmpif v271 then: b7, else: b8 + b7(): + v272 = add v20, u64 1 + range_check v272 to 64 bits + v273 = array_get v0, index v272 + v274 = load v259 + v275 = mul u64 2, v20 + range_check v275 to 64 bits + v276 = div v273, Field 2⁴ + v277 = truncate v276 to 4 bits, max_bit_size: 8 + v278 = cast v277 as u4 + v279 = array_set v274, index v275, value v278 + v280 = add v275, Field 1 + v282 = mul u64 2, v20 + range_check v282 to 64 bits + v283 = add v282, u64 1 + range_check v283 to 64 bits + v284 = and v273, u8 15 + v285 = truncate v284 to 4 bits, max_bit_size: 8 + v286 = cast v285 as u4 + v287 = array_set v279, index v283, value v286 + v288 = add v283, Field 1 + store v287 at v259 + jmp b8() + b8(): + v289 = add v20, Field 1 + jmp b3(v289) + b5(): + jmp b6() +} + +After Assert Constant: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v254 = truncate v1 to 64 bits, max_bit_size: 254 + v255 = cast v254 as u64 + inc_rc v0 + v256 = lt u64 5, v255 + v257 = not v256 + constrain v256 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v259 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 + v261 = array_get v0, index Field 0 + v262 = div v261, Field 2⁴ + v263 = truncate v262 to 4 bits, max_bit_size: 8 + v264 = cast v263 as u4 + v265 = truncate v264 to 1 bits, max_bit_size: 4 + v266 = cast v265 as u1 + jmpif v266 then: b1, else: b2 + b1(): + v291 = array_get v0, index Field 0 + v292 = and v291, u8 15 + v293 = truncate v292 to 4 bits, max_bit_size: 8 + v294 = cast v293 as u4 + store [v294, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 + inc_rc v0 + jmp b9(Field 1) + b9(v61: Field): + v298 = lt v61, Field 5 + jmpif v298 then: b10, else: b11 + b10(): + v364 = truncate v61 to 64 bits, max_bit_size: 254 + v365 = cast v364 as u64 + v366 = truncate v1 to 64 bits, max_bit_size: 254 + v367 = cast v366 as u64 + v368 = lt v365, v367 + jmpif v368 then: b12, else: b13 + b12(): + v369 = array_get v0, index v61 + v370 = load v259 + v371 = mul Field 2, v61 + v372 = sub v371, Field 1 + v373 = div v369, Field 2⁴ + v374 = truncate v373 to 4 bits, max_bit_size: 8 + v375 = cast v374 as u4 + v376 = array_set v370, index v372, value v375 + v377 = add v372, Field 1 + v379 = mul Field 2, v61 + v380 = and v369, u8 15 + v381 = truncate v380 to 4 bits, max_bit_size: 8 + v382 = cast v381 as u4 + v383 = array_set v376, index v379, value v382 + v384 = add v379, Field 1 + store v383 at v259 + jmp b13() + b13(): + v385 = add v61, Field 1 + jmp b9(v385) + b11(): + jmp b6() + b6(): + v299 = load v259 + v300 = mul Field 2, v1 + v301 = cast v266 as Field + v302 = add v300, v301 + v303 = sub v302, Field 2 + inc_rc v299 + inc_rc v299 + inc_rc v299 + v304 = eq v303, Field 5 + constrain v303 == Field 5 + v305 = array_get v299, index Field 0 + v306 = array_get v299, index Field 1 + v307 = array_get v299, index Field 2 + v308 = array_get v299, index Field 3 + v309 = array_get v299, index Field 4 + v310 = allocate + store u1 1 at v310 + jmp b14(Field 0) + b14(v96: Field): + v311 = lt v96, Field 5 + jmpif v311 then: b15, else: b16 + b15(): + v357 = array_get [v305, v306, v307, v308, v309], index v96 + v359 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v96 + v360 = eq v357, v359 + v361 = load v310 + v362 = mul v361, v360 + store v362 at v310 + v363 = add v96, Field 1 + jmp b14(v363) + b16(): + v312 = load v310 + constrain v312 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v317 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 + jmp b17() + b17(): + jmp b18() + b18(): + range_check u8 148 to 8 bits + store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + jmp b19(Field 1) + b19(v129: Field): + v324 = lt v129, Field 2⁵ + jmpif v324 then: b20, else: b21 + b20(): + v349 = load v317 + v350 = sub v129, Field 1 + v352 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v350 + v353 = array_set v349, index v129, value v352 + v354 = add v129, Field 1 + store v353 at v317 + v355 = add v129, Field 1 + jmp b19(v355) + b21(): + v325 = load v317 + inc_rc v325 + jmp b22(v325, Field 21) + b22(v134: [u8; 32], v135: Field): + jmp b23(v134, v135) + b23(v136: [u8; 32], v137: Field): + inc_rc v136 + v326 = allocate + store u1 1 at v326 + jmp b24(Field 0) + b24(v145: Field): + v327 = lt v145, Field 2⁵ + jmpif v327 then: b25, else: b26 + b25(): + v342 = array_get v136, index v145 + v344 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v145 + v345 = eq v342, v344 + v346 = load v326 + v347 = mul v346, v345 + store v347 at v326 + v348 = add v145, Field 1 + jmp b24(v348) + b26(): + v328 = load v326 + constrain v328 == u1 1 + v329 = eq v137, Field 21 + constrain v137 == Field 21 + v330 = allocate + store u64 1 at v330 + v333 = allocate + store u64 2⁴ at v333 + v336 = allocate + store u64 1 at v336 + v339 = allocate + store u64 2⁴ at v339 + return + b2(): + jmp b3(u64 0) + b3(v20: u64): + v267 = lt v20, u64 2 + jmpif v267 then: b4, else: b5 + b4(): + v268 = truncate v1 to 64 bits, max_bit_size: 254 + v269 = cast v268 as u64 + v270 = sub v269, u64 1 + range_check v270 to 64 bits + v271 = lt v20, v270 + jmpif v271 then: b7, else: b8 + b7(): + v272 = add v20, u64 1 + range_check v272 to 64 bits + v273 = array_get v0, index v272 + v274 = load v259 + v275 = mul u64 2, v20 + range_check v275 to 64 bits + v276 = div v273, Field 2⁴ + v277 = truncate v276 to 4 bits, max_bit_size: 8 + v278 = cast v277 as u4 + v279 = array_set v274, index v275, value v278 + v280 = add v275, Field 1 + v282 = mul u64 2, v20 + range_check v282 to 64 bits + v283 = add v282, u64 1 + range_check v283 to 64 bits + v284 = and v273, u8 15 + v285 = truncate v284 to 4 bits, max_bit_size: 8 + v286 = cast v285 as u4 + v287 = array_set v279, index v283, value v286 + v288 = add v283, Field 1 + store v287 at v259 + jmp b8() + b8(): + v289 = add v20, Field 1 + jmp b3(v289) + b5(): + jmp b6() +} + +After Unrolling: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v254 = truncate v1 to 64 bits, max_bit_size: 254 + v255 = cast v254 as u64 + inc_rc v0 + v256 = lt u64 5, v255 + v257 = not v256 + constrain v256 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v259 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 + v261 = array_get v0, index Field 0 + v262 = div v261, Field 2⁴ + v263 = truncate v262 to 4 bits, max_bit_size: 8 + v264 = cast v263 as u4 + v265 = truncate v264 to 1 bits, max_bit_size: 4 + v266 = cast v265 as u1 + jmpif v266 then: b1, else: b2 + b1(): + v291 = array_get v0, index Field 0 + v292 = and v291, u8 15 + v293 = truncate v292 to 4 bits, max_bit_size: 8 + v294 = cast v293 as u4 + store [v294, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 + inc_rc v0 + v387 = truncate v1 to 64 bits, max_bit_size: 254 + v388 = cast v387 as u64 + v389 = lt u64 1, v388 + jmpif v389 then: b29, else: b30 + b29(): + v391 = array_get v0, index Field 1 + v392 = load v259 + v393 = div v391, Field 2⁴ + v394 = truncate v393 to 4 bits, max_bit_size: 8 + v395 = cast v394 as u4 + v396 = array_set v392, index Field 1, value v395 + v397 = and v391, u8 15 + v398 = truncate v397 to 4 bits, max_bit_size: 8 + v399 = cast v398 as u4 + v400 = array_set v396, index Field 2, value v399 + store v400 at v259 + jmp b30() + b30(): + v401 = truncate v1 to 64 bits, max_bit_size: 254 + v402 = cast v401 as u64 + v403 = lt u64 2, v402 + jmpif v403 then: b34, else: b35 + b34(): + v405 = array_get v0, index Field 2 + v406 = load v259 + v407 = div v405, Field 2⁴ + v408 = truncate v407 to 4 bits, max_bit_size: 8 + v409 = cast v408 as u4 + v410 = array_set v406, index Field 3, value v409 + v411 = and v405, u8 15 + v412 = truncate v411 to 4 bits, max_bit_size: 8 + v413 = cast v412 as u4 + v414 = array_set v410, index Field 4, value v413 + store v414 at v259 + jmp b35() + b35(): + v416 = truncate v1 to 64 bits, max_bit_size: 254 + v417 = cast v416 as u64 + v418 = lt u64 3, v417 + jmpif v418 then: b39, else: b40 + b39(): + v420 = array_get v0, index Field 3 + v421 = load v259 + v422 = div v420, Field 2⁴ + v423 = truncate v422 to 4 bits, max_bit_size: 8 + v424 = cast v423 as u4 + v425 = array_set v421, index Field 5, value v424 + v426 = and v420, u8 15 + v427 = truncate v426 to 4 bits, max_bit_size: 8 + v428 = cast v427 as u4 + v429 = array_set v425, index Field 6, value v428 + store v429 at v259 + jmp b40() + b40(): + v430 = truncate v1 to 64 bits, max_bit_size: 254 + v431 = cast v430 as u64 + v432 = lt u64 4, v431 + jmpif v432 then: b44, else: b45 + b44(): + v434 = array_get v0, index Field 4 + v435 = load v259 + v436 = div v434, Field 2⁴ + v437 = truncate v436 to 4 bits, max_bit_size: 8 + v438 = cast v437 as u4 + v439 = array_set v435, index Field 7, value v438 + v440 = and v434, u8 15 + v441 = truncate v440 to 4 bits, max_bit_size: 8 + v442 = cast v441 as u4 + v443 = array_set v439, index Field 8, value v442 + store v443 at v259 + jmp b45() + b45(): + jmp b11() + b11(): + jmp b6() + b6(): + v299 = load v259 + v300 = mul Field 2, v1 + v301 = cast v266 as Field + v302 = add v300, v301 + v303 = sub v302, Field 2 + inc_rc v299 + inc_rc v299 + inc_rc v299 + v304 = eq v303, Field 5 + constrain v303 == Field 5 + v305 = array_get v299, index Field 0 + v306 = array_get v299, index Field 1 + v307 = array_get v299, index Field 2 + v308 = array_get v299, index Field 3 + v309 = array_get v299, index Field 4 + v310 = allocate + store u1 1 at v310 + v792 = eq v305, u4 15 + v793 = load v310 + v794 = mul v793, v792 + store v794 at v310 + v798 = eq v306, u4 1 + v799 = load v310 + v800 = mul v799, v798 + store v800 at v310 + v804 = eq v307, u4 12 + v805 = load v310 + v806 = mul v805, v804 + store v806 at v310 + v810 = eq v308, u4 11 + v811 = load v310 + v812 = mul v811, v810 + store v812 at v310 + v816 = eq v309, u4 8 + v817 = load v310 + v818 = mul v817, v816 + store v818 at v310 + jmp b16() + b16(): + v312 = load v310 + constrain v312 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v317 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 + jmp b17() + b17(): + jmp b18() + b18(): + range_check u8 148 to 8 bits + store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v666 = load v317 + v668 = array_set v666, index Field 1, value u8 184 + store v668 at v317 + v670 = load v317 + v672 = array_set v670, index Field 2, value u8 143 + store v672 at v317 + v674 = load v317 + v676 = array_set v674, index Field 3, value u8 97 + store v676 at v317 + v678 = load v317 + v680 = array_set v678, index Field 4, value u8 230 + store v680 at v317 + v682 = load v317 + v684 = array_set v682, index Field 5, value u8 251 + store v684 at v317 + v686 = load v317 + v688 = array_set v686, index Field 6, value u8 218 + store v688 at v317 + v690 = load v317 + v692 = array_set v690, index Field 7, value u8 131 + store v692 at v317 + v694 = load v317 + v696 = array_set v694, index Field 8, value u8 251 + store v696 at v317 + v698 = load v317 + v700 = array_set v698, index Field 9, value u8 255 + store v700 at v317 + v702 = load v317 + v704 = array_set v702, index Field 10, value u8 250 + store v704 at v317 + v706 = load v317 + v708 = array_set v706, index Field 11, value u8 190 + store v708 at v317 + v710 = load v317 + v712 = array_set v710, index Field 12, value u8 54 + store v712 at v317 + v714 = load v317 + v716 = array_set v714, index Field 13, value u8 65 + store v716 at v317 + v718 = load v317 + v720 = array_set v718, index Field 14, value u8 18 + store v720 at v317 + v722 = load v317 + v724 = array_set v722, index Field 15, value u8 19 + store v724 at v317 + v726 = load v317 + v728 = array_set v726, index Field 2⁴, value u8 116 + store v728 at v317 + v730 = load v317 + v732 = array_set v730, index Field 17, value u8 2⁷ + store v732 at v317 + v734 = load v317 + v736 = array_set v734, index Field 18, value u8 57 + store v736 at v317 + v738 = load v317 + v740 = array_set v738, index Field 19, value u8 2⁷ + store v740 at v317 + v742 = load v317 + v744 = array_set v742, index Field 20, value u8 24 + store v744 at v317 + v746 = load v317 + v748 = array_set v746, index Field 21, value u8 0 + store v748 at v317 + v750 = load v317 + v752 = array_set v750, index Field 22, value u8 0 + store v752 at v317 + v754 = load v317 + v756 = array_set v754, index Field 23, value u8 0 + store v756 at v317 + v758 = load v317 + v760 = array_set v758, index Field 24, value u8 0 + store v760 at v317 + v762 = load v317 + v764 = array_set v762, index Field 25, value u8 0 + store v764 at v317 + v766 = load v317 + v768 = array_set v766, index Field 26, value u8 0 + store v768 at v317 + v770 = load v317 + v772 = array_set v770, index Field 27, value u8 0 + store v772 at v317 + v774 = load v317 + v776 = array_set v774, index Field 28, value u8 0 + store v776 at v317 + v778 = load v317 + v780 = array_set v778, index Field 29, value u8 0 + store v780 at v317 + v782 = load v317 + v784 = array_set v782, index Field 30, value u8 0 + store v784 at v317 + v786 = load v317 + v788 = array_set v786, index Field 31, value u8 0 + store v788 at v317 + jmp b21() + b21(): + v325 = load v317 + inc_rc v325 + jmp b22(v325, Field 21) + b22(v134: [u8; 32], v135: Field): + jmp b23(v134, v135) + b23(v136: [u8; 32], v137: Field): + inc_rc v136 + v326 = allocate + store u1 1 at v326 + v474 = array_get v136, index Field 0 + v476 = eq v474, u8 148 + v477 = load v326 + v478 = mul v477, v476 + store v478 at v326 + v480 = array_get v136, index Field 1 + v482 = eq v480, u8 184 + v483 = load v326 + v484 = mul v483, v482 + store v484 at v326 + v486 = array_get v136, index Field 2 + v488 = eq v486, u8 143 + v489 = load v326 + v490 = mul v489, v488 + store v490 at v326 + v492 = array_get v136, index Field 3 + v494 = eq v492, u8 97 + v495 = load v326 + v496 = mul v495, v494 + store v496 at v326 + v498 = array_get v136, index Field 4 + v500 = eq v498, u8 230 + v501 = load v326 + v502 = mul v501, v500 + store v502 at v326 + v504 = array_get v136, index Field 5 + v506 = eq v504, u8 251 + v507 = load v326 + v508 = mul v507, v506 + store v508 at v326 + v510 = array_get v136, index Field 6 + v512 = eq v510, u8 218 + v513 = load v326 + v514 = mul v513, v512 + store v514 at v326 + v516 = array_get v136, index Field 7 + v518 = eq v516, u8 131 + v519 = load v326 + v520 = mul v519, v518 + store v520 at v326 + v522 = array_get v136, index Field 8 + v524 = eq v522, u8 251 + v525 = load v326 + v526 = mul v525, v524 + store v526 at v326 + v528 = array_get v136, index Field 9 + v530 = eq v528, u8 255 + v531 = load v326 + v532 = mul v531, v530 + store v532 at v326 + v534 = array_get v136, index Field 10 + v536 = eq v534, u8 250 + v537 = load v326 + v538 = mul v537, v536 + store v538 at v326 + v540 = array_get v136, index Field 11 + v542 = eq v540, u8 190 + v543 = load v326 + v544 = mul v543, v542 + store v544 at v326 + v546 = array_get v136, index Field 12 + v548 = eq v546, u8 54 + v549 = load v326 + v550 = mul v549, v548 + store v550 at v326 + v552 = array_get v136, index Field 13 + v554 = eq v552, u8 65 + v555 = load v326 + v556 = mul v555, v554 + store v556 at v326 + v558 = array_get v136, index Field 14 + v560 = eq v558, u8 18 + v561 = load v326 + v562 = mul v561, v560 + store v562 at v326 + v564 = array_get v136, index Field 15 + v566 = eq v564, u8 19 + v567 = load v326 + v568 = mul v567, v566 + store v568 at v326 + v570 = array_get v136, index Field 2⁴ + v572 = eq v570, u8 116 + v573 = load v326 + v574 = mul v573, v572 + store v574 at v326 + v576 = array_get v136, index Field 17 + v578 = eq v576, u8 2⁷ + v579 = load v326 + v580 = mul v579, v578 + store v580 at v326 + v582 = array_get v136, index Field 18 + v584 = eq v582, u8 57 + v585 = load v326 + v586 = mul v585, v584 + store v586 at v326 + v588 = array_get v136, index Field 19 + v590 = eq v588, u8 2⁷ + v591 = load v326 + v592 = mul v591, v590 + store v592 at v326 + v594 = array_get v136, index Field 20 + v596 = eq v594, u8 24 + v597 = load v326 + v598 = mul v597, v596 + store v598 at v326 + v600 = array_get v136, index Field 21 + v602 = eq v600, u8 0 + v603 = load v326 + v604 = mul v603, v602 + store v604 at v326 + v606 = array_get v136, index Field 22 + v608 = eq v606, u8 0 + v609 = load v326 + v610 = mul v609, v608 + store v610 at v326 + v612 = array_get v136, index Field 23 + v614 = eq v612, u8 0 + v615 = load v326 + v616 = mul v615, v614 + store v616 at v326 + v618 = array_get v136, index Field 24 + v620 = eq v618, u8 0 + v621 = load v326 + v622 = mul v621, v620 + store v622 at v326 + v624 = array_get v136, index Field 25 + v626 = eq v624, u8 0 + v627 = load v326 + v628 = mul v627, v626 + store v628 at v326 + v630 = array_get v136, index Field 26 + v632 = eq v630, u8 0 + v633 = load v326 + v634 = mul v633, v632 + store v634 at v326 + v636 = array_get v136, index Field 27 + v638 = eq v636, u8 0 + v639 = load v326 + v640 = mul v639, v638 + store v640 at v326 + v642 = array_get v136, index Field 28 + v644 = eq v642, u8 0 + v645 = load v326 + v646 = mul v645, v644 + store v646 at v326 + v648 = array_get v136, index Field 29 + v650 = eq v648, u8 0 + v651 = load v326 + v652 = mul v651, v650 + store v652 at v326 + v654 = array_get v136, index Field 30 + v656 = eq v654, u8 0 + v657 = load v326 + v658 = mul v657, v656 + store v658 at v326 + v660 = array_get v136, index Field 31 + v662 = eq v660, u8 0 + v663 = load v326 + v664 = mul v663, v662 + store v664 at v326 + jmp b26() + b26(): + v328 = load v326 + constrain v328 == u1 1 + v329 = eq v137, Field 21 + constrain v137 == Field 21 + v330 = allocate + store u64 1 at v330 + v333 = allocate + store u64 2⁴ at v333 + v336 = allocate + store u64 1 at v336 + v339 = allocate + store u64 2⁴ at v339 + return + b2(): + v444 = truncate v1 to 64 bits, max_bit_size: 254 + v445 = cast v444 as u64 + v446 = sub v445, u64 1 + range_check v446 to 64 bits + v447 = lt u64 0, v446 + jmpif v447 then: b51, else: b52 + b51(): + v449 = array_get v0, index u64 1 + v450 = load v259 + v451 = div v449, Field 2⁴ + v452 = truncate v451 to 4 bits, max_bit_size: 8 + v453 = cast v452 as u4 + v454 = array_set v450, index u64 0, value v453 + v455 = and v449, u8 15 + v456 = truncate v455 to 4 bits, max_bit_size: 8 + v457 = cast v456 as u4 + v458 = array_set v454, index u64 1, value v457 + store v458 at v259 + jmp b52() + b52(): + v459 = truncate v1 to 64 bits, max_bit_size: 254 + v460 = cast v459 as u64 + v461 = sub v460, u64 1 + range_check v461 to 64 bits + v462 = lt u64 1, v461 + jmpif v462 then: b56, else: b57 + b56(): + v464 = array_get v0, index u64 2 + v465 = load v259 + v466 = div v464, Field 2⁴ + v467 = truncate v466 to 4 bits, max_bit_size: 8 + v468 = cast v467 as u4 + v469 = array_set v465, index u64 2, value v468 + v470 = and v464, u8 15 + v471 = truncate v470 to 4 bits, max_bit_size: 8 + v472 = cast v471 as u4 + v473 = array_set v469, index u64 3, value v472 + store v473 at v259 + jmp b57() + b57(): + jmp b5() + b5(): + jmp b6() +} + +After Simplifying: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v254 = truncate v1 to 64 bits, max_bit_size: 254 + v255 = cast v254 as u64 + inc_rc v0 + v256 = lt u64 5, v255 + v257 = not v256 + constrain v256 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v259 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 + v261 = array_get v0, index Field 0 + v262 = div v261, Field 2⁴ + v263 = truncate v262 to 4 bits, max_bit_size: 8 + v264 = cast v263 as u4 + v265 = truncate v264 to 1 bits, max_bit_size: 4 + v266 = cast v265 as u1 + jmpif v266 then: b1, else: b2 + b1(): + v291 = array_get v0, index Field 0 + v292 = and v291, u8 15 + v293 = truncate v292 to 4 bits, max_bit_size: 8 + v294 = cast v293 as u4 + store [v294, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 + inc_rc v0 + v387 = truncate v1 to 64 bits, max_bit_size: 254 + v388 = cast v387 as u64 + v389 = lt u64 1, v388 + jmpif v389 then: b29, else: b30 + b29(): + v391 = array_get v0, index Field 1 + v392 = load v259 + v393 = div v391, Field 2⁴ + v394 = truncate v393 to 4 bits, max_bit_size: 8 + v395 = cast v394 as u4 + v396 = array_set v392, index Field 1, value v395 + v397 = and v391, u8 15 + v398 = truncate v397 to 4 bits, max_bit_size: 8 + v399 = cast v398 as u4 + v400 = array_set v396, index Field 2, value v399 + store v400 at v259 + jmp b30() + b30(): + v401 = truncate v1 to 64 bits, max_bit_size: 254 + v402 = cast v401 as u64 + v403 = lt u64 2, v402 + jmpif v403 then: b34, else: b35 + b34(): + v405 = array_get v0, index Field 2 + v406 = load v259 + v407 = div v405, Field 2⁴ + v408 = truncate v407 to 4 bits, max_bit_size: 8 + v409 = cast v408 as u4 + v410 = array_set v406, index Field 3, value v409 + v411 = and v405, u8 15 + v412 = truncate v411 to 4 bits, max_bit_size: 8 + v413 = cast v412 as u4 + v414 = array_set v410, index Field 4, value v413 + store v414 at v259 + jmp b35() + b35(): + v416 = truncate v1 to 64 bits, max_bit_size: 254 + v417 = cast v416 as u64 + v418 = lt u64 3, v417 + jmpif v418 then: b39, else: b40 + b39(): + v420 = array_get v0, index Field 3 + v421 = load v259 + v422 = div v420, Field 2⁴ + v423 = truncate v422 to 4 bits, max_bit_size: 8 + v424 = cast v423 as u4 + v425 = array_set v421, index Field 5, value v424 + v426 = and v420, u8 15 + v427 = truncate v426 to 4 bits, max_bit_size: 8 + v428 = cast v427 as u4 + v429 = array_set v425, index Field 6, value v428 + store v429 at v259 + jmp b40() + b40(): + v430 = truncate v1 to 64 bits, max_bit_size: 254 + v431 = cast v430 as u64 + v432 = lt u64 4, v431 + jmpif v432 then: b44, else: b45 + b44(): + v434 = array_get v0, index Field 4 + v435 = load v259 + v436 = div v434, Field 2⁴ + v437 = truncate v436 to 4 bits, max_bit_size: 8 + v438 = cast v437 as u4 + v439 = array_set v435, index Field 7, value v438 + v440 = and v434, u8 15 + v441 = truncate v440 to 4 bits, max_bit_size: 8 + v442 = cast v441 as u4 + v443 = array_set v439, index Field 8, value v442 + store v443 at v259 + jmp b45() + b45(): + jmp b6() + b6(): + v299 = load v259 + v300 = mul Field 2, v1 + v301 = cast v266 as Field + v302 = add v300, v301 + v303 = sub v302, Field 2 + inc_rc v299 + inc_rc v299 + inc_rc v299 + v304 = eq v303, Field 5 + constrain v303 == Field 5 + v305 = array_get v299, index Field 0 + v306 = array_get v299, index Field 1 + v307 = array_get v299, index Field 2 + v308 = array_get v299, index Field 3 + v309 = array_get v299, index Field 4 + v310 = allocate + store u1 1 at v310 + v792 = eq v305, u4 15 + v793 = load v310 + v794 = mul v793, v792 + store v794 at v310 + v798 = eq v306, u4 1 + v799 = load v310 + v800 = mul v799, v798 + store v800 at v310 + v804 = eq v307, u4 12 + v805 = load v310 + v806 = mul v805, v804 + store v806 at v310 + v810 = eq v308, u4 11 + v811 = load v310 + v812 = mul v811, v810 + store v812 at v310 + v816 = eq v309, u4 8 + v817 = load v310 + v818 = mul v817, v816 + store v818 at v310 + v312 = load v310 + constrain v312 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v317 = allocate + store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 + range_check u8 148 to 8 bits + store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v666 = load v317 + v668 = array_set v666, index Field 1, value u8 184 + store v668 at v317 + v670 = load v317 + v672 = array_set v670, index Field 2, value u8 143 + store v672 at v317 + v674 = load v317 + v676 = array_set v674, index Field 3, value u8 97 + store v676 at v317 + v678 = load v317 + v680 = array_set v678, index Field 4, value u8 230 + store v680 at v317 + v682 = load v317 + v684 = array_set v682, index Field 5, value u8 251 + store v684 at v317 + v686 = load v317 + v688 = array_set v686, index Field 6, value u8 218 + store v688 at v317 + v690 = load v317 + v692 = array_set v690, index Field 7, value u8 131 + store v692 at v317 + v694 = load v317 + v696 = array_set v694, index Field 8, value u8 251 + store v696 at v317 + v698 = load v317 + v700 = array_set v698, index Field 9, value u8 255 + store v700 at v317 + v702 = load v317 + v704 = array_set v702, index Field 10, value u8 250 + store v704 at v317 + v706 = load v317 + v708 = array_set v706, index Field 11, value u8 190 + store v708 at v317 + v710 = load v317 + v712 = array_set v710, index Field 12, value u8 54 + store v712 at v317 + v714 = load v317 + v716 = array_set v714, index Field 13, value u8 65 + store v716 at v317 + v718 = load v317 + v720 = array_set v718, index Field 14, value u8 18 + store v720 at v317 + v722 = load v317 + v724 = array_set v722, index Field 15, value u8 19 + store v724 at v317 + v726 = load v317 + v728 = array_set v726, index Field 2⁴, value u8 116 + store v728 at v317 + v730 = load v317 + v732 = array_set v730, index Field 17, value u8 2⁷ + store v732 at v317 + v734 = load v317 + v736 = array_set v734, index Field 18, value u8 57 + store v736 at v317 + v738 = load v317 + v740 = array_set v738, index Field 19, value u8 2⁷ + store v740 at v317 + v742 = load v317 + v744 = array_set v742, index Field 20, value u8 24 + store v744 at v317 + v746 = load v317 + v748 = array_set v746, index Field 21, value u8 0 + store v748 at v317 + v750 = load v317 + v752 = array_set v750, index Field 22, value u8 0 + store v752 at v317 + v754 = load v317 + v756 = array_set v754, index Field 23, value u8 0 + store v756 at v317 + v758 = load v317 + v760 = array_set v758, index Field 24, value u8 0 + store v760 at v317 + v762 = load v317 + v764 = array_set v762, index Field 25, value u8 0 + store v764 at v317 + v766 = load v317 + v768 = array_set v766, index Field 26, value u8 0 + store v768 at v317 + v770 = load v317 + v772 = array_set v770, index Field 27, value u8 0 + store v772 at v317 + v774 = load v317 + v776 = array_set v774, index Field 28, value u8 0 + store v776 at v317 + v778 = load v317 + v780 = array_set v778, index Field 29, value u8 0 + store v780 at v317 + v782 = load v317 + v784 = array_set v782, index Field 30, value u8 0 + store v784 at v317 + v786 = load v317 + v788 = array_set v786, index Field 31, value u8 0 + store v788 at v317 + v325 = load v317 + inc_rc v325 + inc_rc v325 + v326 = allocate + store u1 1 at v326 + v474 = array_get v325, index Field 0 + v476 = eq v474, u8 148 + v477 = load v326 + v478 = mul v477, v476 + store v478 at v326 + v480 = array_get v325, index Field 1 + v482 = eq v480, u8 184 + v483 = load v326 + v484 = mul v483, v482 + store v484 at v326 + v486 = array_get v325, index Field 2 + v488 = eq v486, u8 143 + v489 = load v326 + v490 = mul v489, v488 + store v490 at v326 + v492 = array_get v325, index Field 3 + v494 = eq v492, u8 97 + v495 = load v326 + v496 = mul v495, v494 + store v496 at v326 + v498 = array_get v325, index Field 4 + v500 = eq v498, u8 230 + v501 = load v326 + v502 = mul v501, v500 + store v502 at v326 + v504 = array_get v325, index Field 5 + v506 = eq v504, u8 251 + v507 = load v326 + v508 = mul v507, v506 + store v508 at v326 + v510 = array_get v325, index Field 6 + v512 = eq v510, u8 218 + v513 = load v326 + v514 = mul v513, v512 + store v514 at v326 + v516 = array_get v325, index Field 7 + v518 = eq v516, u8 131 + v519 = load v326 + v520 = mul v519, v518 + store v520 at v326 + v522 = array_get v325, index Field 8 + v524 = eq v522, u8 251 + v525 = load v326 + v526 = mul v525, v524 + store v526 at v326 + v528 = array_get v325, index Field 9 + v530 = eq v528, u8 255 + v531 = load v326 + v532 = mul v531, v530 + store v532 at v326 + v534 = array_get v325, index Field 10 + v536 = eq v534, u8 250 + v537 = load v326 + v538 = mul v537, v536 + store v538 at v326 + v540 = array_get v325, index Field 11 + v542 = eq v540, u8 190 + v543 = load v326 + v544 = mul v543, v542 + store v544 at v326 + v546 = array_get v325, index Field 12 + v548 = eq v546, u8 54 + v549 = load v326 + v550 = mul v549, v548 + store v550 at v326 + v552 = array_get v325, index Field 13 + v554 = eq v552, u8 65 + v555 = load v326 + v556 = mul v555, v554 + store v556 at v326 + v558 = array_get v325, index Field 14 + v560 = eq v558, u8 18 + v561 = load v326 + v562 = mul v561, v560 + store v562 at v326 + v564 = array_get v325, index Field 15 + v566 = eq v564, u8 19 + v567 = load v326 + v568 = mul v567, v566 + store v568 at v326 + v570 = array_get v325, index Field 2⁴ + v572 = eq v570, u8 116 + v573 = load v326 + v574 = mul v573, v572 + store v574 at v326 + v576 = array_get v325, index Field 17 + v578 = eq v576, u8 2⁷ + v579 = load v326 + v580 = mul v579, v578 + store v580 at v326 + v582 = array_get v325, index Field 18 + v584 = eq v582, u8 57 + v585 = load v326 + v586 = mul v585, v584 + store v586 at v326 + v588 = array_get v325, index Field 19 + v590 = eq v588, u8 2⁷ + v591 = load v326 + v592 = mul v591, v590 + store v592 at v326 + v594 = array_get v325, index Field 20 + v596 = eq v594, u8 24 + v597 = load v326 + v598 = mul v597, v596 + store v598 at v326 + v600 = array_get v325, index Field 21 + v602 = eq v600, u8 0 + v603 = load v326 + v604 = mul v603, v602 + store v604 at v326 + v606 = array_get v325, index Field 22 + v608 = eq v606, u8 0 + v609 = load v326 + v610 = mul v609, v608 + store v610 at v326 + v612 = array_get v325, index Field 23 + v614 = eq v612, u8 0 + v615 = load v326 + v616 = mul v615, v614 + store v616 at v326 + v618 = array_get v325, index Field 24 + v620 = eq v618, u8 0 + v621 = load v326 + v622 = mul v621, v620 + store v622 at v326 + v624 = array_get v325, index Field 25 + v626 = eq v624, u8 0 + v627 = load v326 + v628 = mul v627, v626 + store v628 at v326 + v630 = array_get v325, index Field 26 + v632 = eq v630, u8 0 + v633 = load v326 + v634 = mul v633, v632 + store v634 at v326 + v636 = array_get v325, index Field 27 + v638 = eq v636, u8 0 + v639 = load v326 + v640 = mul v639, v638 + store v640 at v326 + v642 = array_get v325, index Field 28 + v644 = eq v642, u8 0 + v645 = load v326 + v646 = mul v645, v644 + store v646 at v326 + v648 = array_get v325, index Field 29 + v650 = eq v648, u8 0 + v651 = load v326 + v652 = mul v651, v650 + store v652 at v326 + v654 = array_get v325, index Field 30 + v656 = eq v654, u8 0 + v657 = load v326 + v658 = mul v657, v656 + store v658 at v326 + v660 = array_get v325, index Field 31 + v662 = eq v660, u8 0 + v663 = load v326 + v664 = mul v663, v662 + store v664 at v326 + v328 = load v326 + constrain v328 == u1 1 + v329 = eq Field 21, Field 21 + constrain Field 21 == Field 21 + v330 = allocate + store u64 1 at v330 + v333 = allocate + store u64 2⁴ at v333 + v336 = allocate + store u64 1 at v336 + v339 = allocate + store u64 2⁴ at v339 + return + b2(): + v444 = truncate v1 to 64 bits, max_bit_size: 254 + v445 = cast v444 as u64 + v446 = sub v445, u64 1 + range_check v446 to 64 bits + v447 = lt u64 0, v446 + jmpif v447 then: b51, else: b52 + b51(): + v449 = array_get v0, index u64 1 + v450 = load v259 + v451 = div v449, Field 2⁴ + v452 = truncate v451 to 4 bits, max_bit_size: 8 + v453 = cast v452 as u4 + v454 = array_set v450, index u64 0, value v453 + v455 = and v449, u8 15 + v456 = truncate v455 to 4 bits, max_bit_size: 8 + v457 = cast v456 as u4 + v458 = array_set v454, index u64 1, value v457 + store v458 at v259 + jmp b52() + b52(): + v459 = truncate v1 to 64 bits, max_bit_size: 254 + v460 = cast v459 as u64 + v461 = sub v460, u64 1 + range_check v461 to 64 bits + v462 = lt u64 1, v461 + jmpif v462 then: b56, else: b57 + b56(): + v464 = array_get v0, index u64 2 + v465 = load v259 + v466 = div v464, Field 2⁴ + v467 = truncate v466 to 4 bits, max_bit_size: 8 + v468 = cast v467 as u4 + v469 = array_set v465, index u64 2, value v468 + v470 = and v464, u8 15 + v471 = truncate v470 to 4 bits, max_bit_size: 8 + v472 = cast v471 as u4 + v473 = array_set v469, index u64 3, value v472 + store v473 at v259 + jmp b57() + b57(): + jmp b6() +} + +After Mem2Reg: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v820 = truncate v1 to 64 bits, max_bit_size: 254 + v821 = cast v820 as u64 + inc_rc v0 + v822 = lt u64 5, v821 + v823 = not v822 + constrain v822 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v825 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 + v827 = array_get v0, index Field 0 + v828 = div v827, Field 2⁴ + v829 = truncate v828 to 4 bits, max_bit_size: 8 + v830 = cast v829 as u4 + v831 = truncate v830 to 1 bits, max_bit_size: 4 + v832 = cast v831 as u1 + jmpif v832 then: b1, else: b2 + b1(): + v864 = array_get v0, index Field 0 + v865 = and v864, u8 15 + v866 = truncate v865 to 4 bits, max_bit_size: 8 + v867 = cast v866 as u4 + store [v867, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 + inc_rc v0 + v869 = truncate v1 to 64 bits, max_bit_size: 254 + v870 = cast v869 as u64 + v871 = lt u64 1, v870 + jmpif v871 then: b29, else: b30 + b29(): + v872 = array_get v0, index Field 1 + v874 = div v872, Field 2⁴ + v875 = truncate v874 to 4 bits, max_bit_size: 8 + v876 = cast v875 as u4 + v879 = and v872, u8 15 + v880 = truncate v879 to 4 bits, max_bit_size: 8 + v881 = cast v880 as u4 + store [v867, v876, v881, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 + jmp b30() + b30(): + v885 = truncate v1 to 64 bits, max_bit_size: 254 + v886 = cast v885 as u64 + v887 = lt u64 2, v886 + jmpif v887 then: b34, else: b35 + b34(): + v888 = array_get v0, index Field 2 + v889 = load v825 + v890 = div v888, Field 2⁴ + v891 = truncate v890 to 4 bits, max_bit_size: 8 + v892 = cast v891 as u4 + v893 = array_set v889, index Field 3, value v892 + v894 = and v888, u8 15 + v895 = truncate v894 to 4 bits, max_bit_size: 8 + v896 = cast v895 as u4 + v897 = array_set v893, index Field 4, value v896 + store v897 at v825 + jmp b35() + b35(): + v898 = truncate v1 to 64 bits, max_bit_size: 254 + v899 = cast v898 as u64 + v900 = lt u64 3, v899 + jmpif v900 then: b39, else: b40 + b39(): + v901 = array_get v0, index Field 3 + v902 = load v825 + v903 = div v901, Field 2⁴ + v904 = truncate v903 to 4 bits, max_bit_size: 8 + v905 = cast v904 as u4 + v906 = array_set v902, index Field 5, value v905 + v907 = and v901, u8 15 + v908 = truncate v907 to 4 bits, max_bit_size: 8 + v909 = cast v908 as u4 + v910 = array_set v906, index Field 6, value v909 + store v910 at v825 + jmp b40() + b40(): + v911 = truncate v1 to 64 bits, max_bit_size: 254 + v912 = cast v911 as u64 + v913 = lt u64 4, v912 + jmpif v913 then: b44, else: b45 + b44(): + v914 = array_get v0, index Field 4 + v915 = load v825 + v916 = div v914, Field 2⁴ + v917 = truncate v916 to 4 bits, max_bit_size: 8 + v918 = cast v917 as u4 + v919 = array_set v915, index Field 7, value v918 + v920 = and v914, u8 15 + v921 = truncate v920 to 4 bits, max_bit_size: 8 + v922 = cast v921 as u4 + v923 = array_set v919, index Field 8, value v922 + store v923 at v825 + jmp b45() + b45(): + jmp b6() + b6(): + v924 = load v825 + v925 = mul Field 2, v1 + v926 = cast v832 as Field + v927 = add v925, v926 + v928 = sub v927, Field 2 + inc_rc v924 + inc_rc v924 + inc_rc v924 + v929 = eq v928, Field 5 + constrain v928 == Field 5 + v930 = array_get v924, index Field 0 + v931 = array_get v924, index Field 1 + v932 = array_get v924, index Field 2 + v933 = array_get v924, index Field 3 + v934 = array_get v924, index Field 4 + v935 = allocate + v936 = eq v930, u4 15 + v938 = eq v931, u4 1 + v940 = mul v936, v938 + v941 = eq v932, u4 12 + v943 = mul v940, v941 + v944 = eq v933, u4 11 + v946 = mul v943, v944 + v947 = eq v934, u4 8 + v949 = mul v946, v947 + store v949 at v935 + constrain v949 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v955 = allocate + range_check u8 148 to 8 bits + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + store [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v955 + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v1086 = allocate + store u1 1 at v1086 + v1152 = allocate + store u64 1 at v1152 + v1153 = allocate + store u64 2⁴ at v1153 + v1154 = allocate + store u64 1 at v1154 + v1155 = allocate + store u64 2⁴ at v1155 + return + b2(): + v833 = truncate v1 to 64 bits, max_bit_size: 254 + v834 = cast v833 as u64 + v835 = sub v834, u64 1 + range_check v835 to 64 bits + v836 = lt u64 0, v835 + jmpif v836 then: b51, else: b52 + b51(): + v837 = array_get v0, index u64 1 + v839 = div v837, Field 2⁴ + v840 = truncate v839 to 4 bits, max_bit_size: 8 + v841 = cast v840 as u4 + v844 = and v837, u8 15 + v845 = truncate v844 to 4 bits, max_bit_size: 8 + v846 = cast v845 as u4 + store [v841, v846, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 + jmp b52() + b52(): + v850 = truncate v1 to 64 bits, max_bit_size: 254 + v851 = cast v850 as u64 + v852 = sub v851, u64 1 + range_check v852 to 64 bits + v853 = lt u64 1, v852 + jmpif v853 then: b56, else: b57 + b56(): + v854 = array_get v0, index u64 2 + v855 = load v825 + v856 = div v854, Field 2⁴ + v857 = truncate v856 to 4 bits, max_bit_size: 8 + v858 = cast v857 as u4 + v859 = array_set v855, index u64 2, value v858 + v860 = and v854, u8 15 + v861 = truncate v860 to 4 bits, max_bit_size: 8 + v862 = cast v861 as u4 + v863 = array_set v859, index u64 3, value v862 + store v863 at v825 + jmp b57() + b57(): + jmp b6() +} + +After Flattening: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v820 = truncate v1 to 64 bits, max_bit_size: 254 + v821 = cast v820 as u64 + inc_rc v0 + v822 = lt u64 5, v821 + v823 = not v822 + constrain v822 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v825 = allocate + store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 + v827 = array_get v0, index Field 0 + v828 = div v827, Field 2⁴ + v829 = truncate v828 to 4 bits, max_bit_size: 8 + v830 = cast v829 as u4 + v831 = truncate v830 to 1 bits, max_bit_size: 4 + v832 = cast v831 as u1 + enable_side_effects v832 + v1158 = array_get v0, index Field 0 + v1159 = and v1158, u8 15 + v1160 = truncate v1159 to 4 bits, max_bit_size: 8 + v1161 = cast v1160 as u4 + v1163 = load v825 + store [v1161, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 + inc_rc v0 + v1164 = truncate v1 to 64 bits, max_bit_size: 254 + v1165 = cast v1164 as u64 + v1166 = lt u64 1, v1165 + v1168 = mul v832, v1166 + enable_side_effects v1168 + v1169 = array_get v0, index Field 1 + v1170 = div v1169, Field 2⁴ + v1171 = truncate v1170 to 4 bits, max_bit_size: 8 + v1172 = cast v1171 as u4 + v1173 = and v1169, u8 15 + v1174 = truncate v1173 to 4 bits, max_bit_size: 8 + v1175 = cast v1174 as u4 + v1177 = load v825 + store [v1161, v1172, v1175, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 + v1178 = not v1166 + store v1177 at v825 + enable_side_effects v832 + v1179 = array_get v1177, index Field 0 + v1180 = cast v1166 as u4 + v1181 = cast v1178 as u4 + v1182 = mul v1180, v1161 + v1183 = mul v1181, v1179 + v1184 = add v1182, v1183 + v1185 = array_get v1177, index Field 1 + v1186 = cast v1166 as u4 + v1187 = cast v1178 as u4 + v1188 = mul v1186, v1172 + v1189 = mul v1187, v1185 + v1190 = add v1188, v1189 + v1191 = array_get v1177, index Field 2 + v1192 = cast v1166 as u4 + v1193 = cast v1178 as u4 + v1194 = mul v1192, v1175 + v1195 = mul v1193, v1191 + v1196 = add v1194, v1195 + v1197 = array_get v1177, index Field 3 + v1198 = cast v1166 as u4 + v1199 = cast v1178 as u4 + v1200 = mul v1199, v1197 + v1201 = array_get v1177, index Field 4 + v1202 = cast v1166 as u4 + v1203 = cast v1178 as u4 + v1204 = mul v1203, v1201 + v1205 = array_get v1177, index Field 5 + v1206 = cast v1166 as u4 + v1207 = cast v1178 as u4 + v1208 = mul v1207, v1205 + v1209 = array_get v1177, index Field 6 + v1210 = cast v1166 as u4 + v1211 = cast v1178 as u4 + v1212 = mul v1211, v1209 + v1213 = array_get v1177, index Field 7 + v1214 = cast v1166 as u4 + v1215 = cast v1178 as u4 + v1216 = mul v1215, v1213 + v1217 = array_get v1177, index Field 8 + v1218 = cast v1166 as u4 + v1219 = cast v1178 as u4 + v1220 = mul v1219, v1217 + v1221 = array_get v1177, index Field 9 + v1222 = cast v1166 as u4 + v1223 = cast v1178 as u4 + v1224 = mul v1223, v1221 + v1225 = array_get v1177, index Field 10 + v1226 = cast v1166 as u4 + v1227 = cast v1178 as u4 + v1228 = mul v1227, v1225 + v1229 = array_get v1177, index Field 11 + v1230 = cast v1166 as u4 + v1231 = cast v1178 as u4 + v1232 = mul v1231, v1229 + v1233 = array_get v1177, index Field 12 + v1234 = cast v1166 as u4 + v1235 = cast v1178 as u4 + v1236 = mul v1235, v1233 + v1237 = array_get v1177, index Field 13 + v1238 = cast v1166 as u4 + v1239 = cast v1178 as u4 + v1240 = mul v1239, v1237 + v1241 = array_get v1177, index Field 14 + v1242 = cast v1166 as u4 + v1243 = cast v1178 as u4 + v1244 = mul v1243, v1241 + v1245 = array_get v1177, index Field 15 + v1246 = cast v1166 as u4 + v1247 = cast v1178 as u4 + v1248 = mul v1247, v1245 + store [v1184, v1190, v1196, v1200, v1204, v1208, v1212, v1216, v1220, v1224, v1228, v1232, v1236, v1240, v1244, v1248] at v825 + v1250 = truncate v1 to 64 bits, max_bit_size: 254 + v1251 = cast v1250 as u64 + v1252 = lt u64 2, v1251 + v1253 = mul v832, v1252 + enable_side_effects v1253 + v1254 = array_get v0, index Field 2 + v1255 = load v825 + v1256 = div v1254, Field 2⁴ + v1257 = truncate v1256 to 4 bits, max_bit_size: 8 + v1258 = cast v1257 as u4 + v1259 = array_set v1255, index Field 3, value v1258 + v1260 = and v1254, u8 15 + v1261 = truncate v1260 to 4 bits, max_bit_size: 8 + v1262 = cast v1261 as u4 + v1263 = array_set v1259, index Field 4, value v1262 + v1264 = load v825 + store v1263 at v825 + v1265 = not v1252 + store v1264 at v825 + enable_side_effects v832 + v1266 = array_get v1263, index Field 0 + v1267 = array_get v1264, index Field 0 + v1268 = cast v1252 as u4 + v1269 = cast v1265 as u4 + v1270 = mul v1268, v1266 + v1271 = mul v1269, v1267 + v1272 = add v1270, v1271 + v1273 = array_get v1263, index Field 1 + v1274 = array_get v1264, index Field 1 + v1275 = cast v1252 as u4 + v1276 = cast v1265 as u4 + v1277 = mul v1275, v1273 + v1278 = mul v1276, v1274 + v1279 = add v1277, v1278 + v1280 = array_get v1263, index Field 2 + v1281 = array_get v1264, index Field 2 + v1282 = cast v1252 as u4 + v1283 = cast v1265 as u4 + v1284 = mul v1282, v1280 + v1285 = mul v1283, v1281 + v1286 = add v1284, v1285 + v1287 = array_get v1263, index Field 3 + v1288 = array_get v1264, index Field 3 + v1289 = cast v1252 as u4 + v1290 = cast v1265 as u4 + v1291 = mul v1289, v1287 + v1292 = mul v1290, v1288 + v1293 = add v1291, v1292 + v1294 = array_get v1263, index Field 4 + v1295 = array_get v1264, index Field 4 + v1296 = cast v1252 as u4 + v1297 = cast v1265 as u4 + v1298 = mul v1296, v1294 + v1299 = mul v1297, v1295 + v1300 = add v1298, v1299 + v1301 = array_get v1263, index Field 5 + v1302 = array_get v1264, index Field 5 + v1303 = cast v1252 as u4 + v1304 = cast v1265 as u4 + v1305 = mul v1303, v1301 + v1306 = mul v1304, v1302 + v1307 = add v1305, v1306 + v1308 = array_get v1263, index Field 6 + v1309 = array_get v1264, index Field 6 + v1310 = cast v1252 as u4 + v1311 = cast v1265 as u4 + v1312 = mul v1310, v1308 + v1313 = mul v1311, v1309 + v1314 = add v1312, v1313 + v1315 = array_get v1263, index Field 7 + v1316 = array_get v1264, index Field 7 + v1317 = cast v1252 as u4 + v1318 = cast v1265 as u4 + v1319 = mul v1317, v1315 + v1320 = mul v1318, v1316 + v1321 = add v1319, v1320 + v1322 = array_get v1263, index Field 8 + v1323 = array_get v1264, index Field 8 + v1324 = cast v1252 as u4 + v1325 = cast v1265 as u4 + v1326 = mul v1324, v1322 + v1327 = mul v1325, v1323 + v1328 = add v1326, v1327 + v1329 = array_get v1263, index Field 9 + v1330 = array_get v1264, index Field 9 + v1331 = cast v1252 as u4 + v1332 = cast v1265 as u4 + v1333 = mul v1331, v1329 + v1334 = mul v1332, v1330 + v1335 = add v1333, v1334 + v1336 = array_get v1263, index Field 10 + v1337 = array_get v1264, index Field 10 + v1338 = cast v1252 as u4 + v1339 = cast v1265 as u4 + v1340 = mul v1338, v1336 + v1341 = mul v1339, v1337 + v1342 = add v1340, v1341 + v1343 = array_get v1263, index Field 11 + v1344 = array_get v1264, index Field 11 + v1345 = cast v1252 as u4 + v1346 = cast v1265 as u4 + v1347 = mul v1345, v1343 + v1348 = mul v1346, v1344 + v1349 = add v1347, v1348 + v1350 = array_get v1263, index Field 12 + v1351 = array_get v1264, index Field 12 + v1352 = cast v1252 as u4 + v1353 = cast v1265 as u4 + v1354 = mul v1352, v1350 + v1355 = mul v1353, v1351 + v1356 = add v1354, v1355 + v1357 = array_get v1263, index Field 13 + v1358 = array_get v1264, index Field 13 + v1359 = cast v1252 as u4 + v1360 = cast v1265 as u4 + v1361 = mul v1359, v1357 + v1362 = mul v1360, v1358 + v1363 = add v1361, v1362 + v1364 = array_get v1263, index Field 14 + v1365 = array_get v1264, index Field 14 + v1366 = cast v1252 as u4 + v1367 = cast v1265 as u4 + v1368 = mul v1366, v1364 + v1369 = mul v1367, v1365 + v1370 = add v1368, v1369 + v1371 = array_get v1263, index Field 15 + v1372 = array_get v1264, index Field 15 + v1373 = cast v1252 as u4 + v1374 = cast v1265 as u4 + v1375 = mul v1373, v1371 + v1376 = mul v1374, v1372 + v1377 = add v1375, v1376 + store [v1272, v1279, v1286, v1293, v1300, v1307, v1314, v1321, v1328, v1335, v1342, v1349, v1356, v1363, v1370, v1377] at v825 + v1379 = truncate v1 to 64 bits, max_bit_size: 254 + v1380 = cast v1379 as u64 + v1381 = lt u64 3, v1380 + v1382 = mul v832, v1381 + enable_side_effects v1382 + v1383 = array_get v0, index Field 3 + v1384 = load v825 + v1385 = div v1383, Field 2⁴ + v1386 = truncate v1385 to 4 bits, max_bit_size: 8 + v1387 = cast v1386 as u4 + v1388 = array_set v1384, index Field 5, value v1387 + v1389 = and v1383, u8 15 + v1390 = truncate v1389 to 4 bits, max_bit_size: 8 + v1391 = cast v1390 as u4 + v1392 = array_set v1388, index Field 6, value v1391 + v1393 = load v825 + store v1392 at v825 + v1394 = not v1381 + store v1393 at v825 + enable_side_effects v832 + v1395 = array_get v1392, index Field 0 + v1396 = array_get v1393, index Field 0 + v1397 = cast v1381 as u4 + v1398 = cast v1394 as u4 + v1399 = mul v1397, v1395 + v1400 = mul v1398, v1396 + v1401 = add v1399, v1400 + v1402 = array_get v1392, index Field 1 + v1403 = array_get v1393, index Field 1 + v1404 = cast v1381 as u4 + v1405 = cast v1394 as u4 + v1406 = mul v1404, v1402 + v1407 = mul v1405, v1403 + v1408 = add v1406, v1407 + v1409 = array_get v1392, index Field 2 + v1410 = array_get v1393, index Field 2 + v1411 = cast v1381 as u4 + v1412 = cast v1394 as u4 + v1413 = mul v1411, v1409 + v1414 = mul v1412, v1410 + v1415 = add v1413, v1414 + v1416 = array_get v1392, index Field 3 + v1417 = array_get v1393, index Field 3 + v1418 = cast v1381 as u4 + v1419 = cast v1394 as u4 + v1420 = mul v1418, v1416 + v1421 = mul v1419, v1417 + v1422 = add v1420, v1421 + v1423 = array_get v1392, index Field 4 + v1424 = array_get v1393, index Field 4 + v1425 = cast v1381 as u4 + v1426 = cast v1394 as u4 + v1427 = mul v1425, v1423 + v1428 = mul v1426, v1424 + v1429 = add v1427, v1428 + v1430 = array_get v1392, index Field 5 + v1431 = array_get v1393, index Field 5 + v1432 = cast v1381 as u4 + v1433 = cast v1394 as u4 + v1434 = mul v1432, v1430 + v1435 = mul v1433, v1431 + v1436 = add v1434, v1435 + v1437 = array_get v1392, index Field 6 + v1438 = array_get v1393, index Field 6 + v1439 = cast v1381 as u4 + v1440 = cast v1394 as u4 + v1441 = mul v1439, v1437 + v1442 = mul v1440, v1438 + v1443 = add v1441, v1442 + v1444 = array_get v1392, index Field 7 + v1445 = array_get v1393, index Field 7 + v1446 = cast v1381 as u4 + v1447 = cast v1394 as u4 + v1448 = mul v1446, v1444 + v1449 = mul v1447, v1445 + v1450 = add v1448, v1449 + v1451 = array_get v1392, index Field 8 + v1452 = array_get v1393, index Field 8 + v1453 = cast v1381 as u4 + v1454 = cast v1394 as u4 + v1455 = mul v1453, v1451 + v1456 = mul v1454, v1452 + v1457 = add v1455, v1456 + v1458 = array_get v1392, index Field 9 + v1459 = array_get v1393, index Field 9 + v1460 = cast v1381 as u4 + v1461 = cast v1394 as u4 + v1462 = mul v1460, v1458 + v1463 = mul v1461, v1459 + v1464 = add v1462, v1463 + v1465 = array_get v1392, index Field 10 + v1466 = array_get v1393, index Field 10 + v1467 = cast v1381 as u4 + v1468 = cast v1394 as u4 + v1469 = mul v1467, v1465 + v1470 = mul v1468, v1466 + v1471 = add v1469, v1470 + v1472 = array_get v1392, index Field 11 + v1473 = array_get v1393, index Field 11 + v1474 = cast v1381 as u4 + v1475 = cast v1394 as u4 + v1476 = mul v1474, v1472 + v1477 = mul v1475, v1473 + v1478 = add v1476, v1477 + v1479 = array_get v1392, index Field 12 + v1480 = array_get v1393, index Field 12 + v1481 = cast v1381 as u4 + v1482 = cast v1394 as u4 + v1483 = mul v1481, v1479 + v1484 = mul v1482, v1480 + v1485 = add v1483, v1484 + v1486 = array_get v1392, index Field 13 + v1487 = array_get v1393, index Field 13 + v1488 = cast v1381 as u4 + v1489 = cast v1394 as u4 + v1490 = mul v1488, v1486 + v1491 = mul v1489, v1487 + v1492 = add v1490, v1491 + v1493 = array_get v1392, index Field 14 + v1494 = array_get v1393, index Field 14 + v1495 = cast v1381 as u4 + v1496 = cast v1394 as u4 + v1497 = mul v1495, v1493 + v1498 = mul v1496, v1494 + v1499 = add v1497, v1498 + v1500 = array_get v1392, index Field 15 + v1501 = array_get v1393, index Field 15 + v1502 = cast v1381 as u4 + v1503 = cast v1394 as u4 + v1504 = mul v1502, v1500 + v1505 = mul v1503, v1501 + v1506 = add v1504, v1505 + store [v1401, v1408, v1415, v1422, v1429, v1436, v1443, v1450, v1457, v1464, v1471, v1478, v1485, v1492, v1499, v1506] at v825 + v1508 = truncate v1 to 64 bits, max_bit_size: 254 + v1509 = cast v1508 as u64 + v1510 = lt u64 4, v1509 + v1511 = mul v832, v1510 + enable_side_effects v1511 + v1512 = array_get v0, index Field 4 + v1513 = load v825 + v1514 = div v1512, Field 2⁴ + v1515 = truncate v1514 to 4 bits, max_bit_size: 8 + v1516 = cast v1515 as u4 + v1517 = array_set v1513, index Field 7, value v1516 + v1518 = and v1512, u8 15 + v1519 = truncate v1518 to 4 bits, max_bit_size: 8 + v1520 = cast v1519 as u4 + v1521 = array_set v1517, index Field 8, value v1520 + v1522 = load v825 + store v1521 at v825 + v1523 = not v1510 + store v1522 at v825 + enable_side_effects v832 + v1524 = array_get v1521, index Field 0 + v1525 = array_get v1522, index Field 0 + v1526 = cast v1510 as u4 + v1527 = cast v1523 as u4 + v1528 = mul v1526, v1524 + v1529 = mul v1527, v1525 + v1530 = add v1528, v1529 + v1531 = array_get v1521, index Field 1 + v1532 = array_get v1522, index Field 1 + v1533 = cast v1510 as u4 + v1534 = cast v1523 as u4 + v1535 = mul v1533, v1531 + v1536 = mul v1534, v1532 + v1537 = add v1535, v1536 + v1538 = array_get v1521, index Field 2 + v1539 = array_get v1522, index Field 2 + v1540 = cast v1510 as u4 + v1541 = cast v1523 as u4 + v1542 = mul v1540, v1538 + v1543 = mul v1541, v1539 + v1544 = add v1542, v1543 + v1545 = array_get v1521, index Field 3 + v1546 = array_get v1522, index Field 3 + v1547 = cast v1510 as u4 + v1548 = cast v1523 as u4 + v1549 = mul v1547, v1545 + v1550 = mul v1548, v1546 + v1551 = add v1549, v1550 + v1552 = array_get v1521, index Field 4 + v1553 = array_get v1522, index Field 4 + v1554 = cast v1510 as u4 + v1555 = cast v1523 as u4 + v1556 = mul v1554, v1552 + v1557 = mul v1555, v1553 + v1558 = add v1556, v1557 + v1559 = array_get v1521, index Field 5 + v1560 = array_get v1522, index Field 5 + v1561 = cast v1510 as u4 + v1562 = cast v1523 as u4 + v1563 = mul v1561, v1559 + v1564 = mul v1562, v1560 + v1565 = add v1563, v1564 + v1566 = array_get v1521, index Field 6 + v1567 = array_get v1522, index Field 6 + v1568 = cast v1510 as u4 + v1569 = cast v1523 as u4 + v1570 = mul v1568, v1566 + v1571 = mul v1569, v1567 + v1572 = add v1570, v1571 + v1573 = array_get v1521, index Field 7 + v1574 = array_get v1522, index Field 7 + v1575 = cast v1510 as u4 + v1576 = cast v1523 as u4 + v1577 = mul v1575, v1573 + v1578 = mul v1576, v1574 + v1579 = add v1577, v1578 + v1580 = array_get v1521, index Field 8 + v1581 = array_get v1522, index Field 8 + v1582 = cast v1510 as u4 + v1583 = cast v1523 as u4 + v1584 = mul v1582, v1580 + v1585 = mul v1583, v1581 + v1586 = add v1584, v1585 + v1587 = array_get v1521, index Field 9 + v1588 = array_get v1522, index Field 9 + v1589 = cast v1510 as u4 + v1590 = cast v1523 as u4 + v1591 = mul v1589, v1587 + v1592 = mul v1590, v1588 + v1593 = add v1591, v1592 + v1594 = array_get v1521, index Field 10 + v1595 = array_get v1522, index Field 10 + v1596 = cast v1510 as u4 + v1597 = cast v1523 as u4 + v1598 = mul v1596, v1594 + v1599 = mul v1597, v1595 + v1600 = add v1598, v1599 + v1601 = array_get v1521, index Field 11 + v1602 = array_get v1522, index Field 11 + v1603 = cast v1510 as u4 + v1604 = cast v1523 as u4 + v1605 = mul v1603, v1601 + v1606 = mul v1604, v1602 + v1607 = add v1605, v1606 + v1608 = array_get v1521, index Field 12 + v1609 = array_get v1522, index Field 12 + v1610 = cast v1510 as u4 + v1611 = cast v1523 as u4 + v1612 = mul v1610, v1608 + v1613 = mul v1611, v1609 + v1614 = add v1612, v1613 + v1615 = array_get v1521, index Field 13 + v1616 = array_get v1522, index Field 13 + v1617 = cast v1510 as u4 + v1618 = cast v1523 as u4 + v1619 = mul v1617, v1615 + v1620 = mul v1618, v1616 + v1621 = add v1619, v1620 + v1622 = array_get v1521, index Field 14 + v1623 = array_get v1522, index Field 14 + v1624 = cast v1510 as u4 + v1625 = cast v1523 as u4 + v1626 = mul v1624, v1622 + v1627 = mul v1625, v1623 + v1628 = add v1626, v1627 + v1629 = array_get v1521, index Field 15 + v1630 = array_get v1522, index Field 15 + v1631 = cast v1510 as u4 + v1632 = cast v1523 as u4 + v1633 = mul v1631, v1629 + v1634 = mul v1632, v1630 + v1635 = add v1633, v1634 + store [v1530, v1537, v1544, v1551, v1558, v1565, v1572, v1579, v1586, v1593, v1600, v1607, v1614, v1621, v1628, v1635] at v825 + v1637 = not v832 + store v1163 at v825 + enable_side_effects v1637 + v1638 = truncate v1 to 64 bits, max_bit_size: 254 + v1639 = cast v1638 as u64 + v1640 = sub v1639, u64 1 + v1641 = cast v1637 as u64 + v1642 = mul v1640, v1641 + range_check v1642 to 64 bits + v1643 = lt u64 0, v1640 + v1644 = mul v1637, v1643 + enable_side_effects v1644 + v1645 = array_get v0, index u64 1 + v1646 = div v1645, Field 2⁴ + v1647 = truncate v1646 to 4 bits, max_bit_size: 8 + v1648 = cast v1647 as u4 + v1649 = and v1645, u8 15 + v1650 = truncate v1649 to 4 bits, max_bit_size: 8 + v1651 = cast v1650 as u4 + v1653 = load v825 + store [v1648, v1651, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 + v1654 = not v1643 + store v1653 at v825 + enable_side_effects v1637 + v1655 = array_get v1653, index Field 0 + v1656 = cast v1643 as u4 + v1657 = cast v1654 as u4 + v1658 = mul v1656, v1648 + v1659 = mul v1657, v1655 + v1660 = add v1658, v1659 + v1661 = array_get v1653, index Field 1 + v1662 = cast v1643 as u4 + v1663 = cast v1654 as u4 + v1664 = mul v1662, v1651 + v1665 = mul v1663, v1661 + v1666 = add v1664, v1665 + v1667 = array_get v1653, index Field 2 + v1668 = cast v1643 as u4 + v1669 = cast v1654 as u4 + v1670 = mul v1669, v1667 + v1671 = array_get v1653, index Field 3 + v1672 = cast v1643 as u4 + v1673 = cast v1654 as u4 + v1674 = mul v1673, v1671 + v1675 = array_get v1653, index Field 4 + v1676 = cast v1643 as u4 + v1677 = cast v1654 as u4 + v1678 = mul v1677, v1675 + v1679 = array_get v1653, index Field 5 + v1680 = cast v1643 as u4 + v1681 = cast v1654 as u4 + v1682 = mul v1681, v1679 + v1683 = array_get v1653, index Field 6 + v1684 = cast v1643 as u4 + v1685 = cast v1654 as u4 + v1686 = mul v1685, v1683 + v1687 = array_get v1653, index Field 7 + v1688 = cast v1643 as u4 + v1689 = cast v1654 as u4 + v1690 = mul v1689, v1687 + v1691 = array_get v1653, index Field 8 + v1692 = cast v1643 as u4 + v1693 = cast v1654 as u4 + v1694 = mul v1693, v1691 + v1695 = array_get v1653, index Field 9 + v1696 = cast v1643 as u4 + v1697 = cast v1654 as u4 + v1698 = mul v1697, v1695 + v1699 = array_get v1653, index Field 10 + v1700 = cast v1643 as u4 + v1701 = cast v1654 as u4 + v1702 = mul v1701, v1699 + v1703 = array_get v1653, index Field 11 + v1704 = cast v1643 as u4 + v1705 = cast v1654 as u4 + v1706 = mul v1705, v1703 + v1707 = array_get v1653, index Field 12 + v1708 = cast v1643 as u4 + v1709 = cast v1654 as u4 + v1710 = mul v1709, v1707 + v1711 = array_get v1653, index Field 13 + v1712 = cast v1643 as u4 + v1713 = cast v1654 as u4 + v1714 = mul v1713, v1711 + v1715 = array_get v1653, index Field 14 + v1716 = cast v1643 as u4 + v1717 = cast v1654 as u4 + v1718 = mul v1717, v1715 + v1719 = array_get v1653, index Field 15 + v1720 = cast v1643 as u4 + v1721 = cast v1654 as u4 + v1722 = mul v1721, v1719 + store [v1660, v1666, v1670, v1674, v1678, v1682, v1686, v1690, v1694, v1698, v1702, v1706, v1710, v1714, v1718, v1722] at v825 + v1724 = truncate v1 to 64 bits, max_bit_size: 254 + v1725 = cast v1724 as u64 + v1726 = sub v1725, u64 1 + v1727 = cast v1637 as u64 + v1728 = mul v1726, v1727 + range_check v1728 to 64 bits + v1729 = lt u64 1, v1726 + v1730 = mul v1637, v1729 + enable_side_effects v1730 + v1731 = array_get v0, index u64 2 + v1732 = load v825 + v1733 = div v1731, Field 2⁴ + v1734 = truncate v1733 to 4 bits, max_bit_size: 8 + v1735 = cast v1734 as u4 + v1736 = array_set v1732, index u64 2, value v1735 + v1737 = and v1731, u8 15 + v1738 = truncate v1737 to 4 bits, max_bit_size: 8 + v1739 = cast v1738 as u4 + v1740 = array_set v1736, index u64 3, value v1739 + v1741 = load v825 + store v1740 at v825 + v1742 = not v1729 + store v1741 at v825 + enable_side_effects v1637 + v1743 = array_get v1740, index Field 0 + v1744 = array_get v1741, index Field 0 + v1745 = cast v1729 as u4 + v1746 = cast v1742 as u4 + v1747 = mul v1745, v1743 + v1748 = mul v1746, v1744 + v1749 = add v1747, v1748 + v1750 = array_get v1740, index Field 1 + v1751 = array_get v1741, index Field 1 + v1752 = cast v1729 as u4 + v1753 = cast v1742 as u4 + v1754 = mul v1752, v1750 + v1755 = mul v1753, v1751 + v1756 = add v1754, v1755 + v1757 = array_get v1740, index Field 2 + v1758 = array_get v1741, index Field 2 + v1759 = cast v1729 as u4 + v1760 = cast v1742 as u4 + v1761 = mul v1759, v1757 + v1762 = mul v1760, v1758 + v1763 = add v1761, v1762 + v1764 = array_get v1740, index Field 3 + v1765 = array_get v1741, index Field 3 + v1766 = cast v1729 as u4 + v1767 = cast v1742 as u4 + v1768 = mul v1766, v1764 + v1769 = mul v1767, v1765 + v1770 = add v1768, v1769 + v1771 = array_get v1740, index Field 4 + v1772 = array_get v1741, index Field 4 + v1773 = cast v1729 as u4 + v1774 = cast v1742 as u4 + v1775 = mul v1773, v1771 + v1776 = mul v1774, v1772 + v1777 = add v1775, v1776 + v1778 = array_get v1740, index Field 5 + v1779 = array_get v1741, index Field 5 + v1780 = cast v1729 as u4 + v1781 = cast v1742 as u4 + v1782 = mul v1780, v1778 + v1783 = mul v1781, v1779 + v1784 = add v1782, v1783 + v1785 = array_get v1740, index Field 6 + v1786 = array_get v1741, index Field 6 + v1787 = cast v1729 as u4 + v1788 = cast v1742 as u4 + v1789 = mul v1787, v1785 + v1790 = mul v1788, v1786 + v1791 = add v1789, v1790 + v1792 = array_get v1740, index Field 7 + v1793 = array_get v1741, index Field 7 + v1794 = cast v1729 as u4 + v1795 = cast v1742 as u4 + v1796 = mul v1794, v1792 + v1797 = mul v1795, v1793 + v1798 = add v1796, v1797 + v1799 = array_get v1740, index Field 8 + v1800 = array_get v1741, index Field 8 + v1801 = cast v1729 as u4 + v1802 = cast v1742 as u4 + v1803 = mul v1801, v1799 + v1804 = mul v1802, v1800 + v1805 = add v1803, v1804 + v1806 = array_get v1740, index Field 9 + v1807 = array_get v1741, index Field 9 + v1808 = cast v1729 as u4 + v1809 = cast v1742 as u4 + v1810 = mul v1808, v1806 + v1811 = mul v1809, v1807 + v1812 = add v1810, v1811 + v1813 = array_get v1740, index Field 10 + v1814 = array_get v1741, index Field 10 + v1815 = cast v1729 as u4 + v1816 = cast v1742 as u4 + v1817 = mul v1815, v1813 + v1818 = mul v1816, v1814 + v1819 = add v1817, v1818 + v1820 = array_get v1740, index Field 11 + v1821 = array_get v1741, index Field 11 + v1822 = cast v1729 as u4 + v1823 = cast v1742 as u4 + v1824 = mul v1822, v1820 + v1825 = mul v1823, v1821 + v1826 = add v1824, v1825 + v1827 = array_get v1740, index Field 12 + v1828 = array_get v1741, index Field 12 + v1829 = cast v1729 as u4 + v1830 = cast v1742 as u4 + v1831 = mul v1829, v1827 + v1832 = mul v1830, v1828 + v1833 = add v1831, v1832 + v1834 = array_get v1740, index Field 13 + v1835 = array_get v1741, index Field 13 + v1836 = cast v1729 as u4 + v1837 = cast v1742 as u4 + v1838 = mul v1836, v1834 + v1839 = mul v1837, v1835 + v1840 = add v1838, v1839 + v1841 = array_get v1740, index Field 14 + v1842 = array_get v1741, index Field 14 + v1843 = cast v1729 as u4 + v1844 = cast v1742 as u4 + v1845 = mul v1843, v1841 + v1846 = mul v1844, v1842 + v1847 = add v1845, v1846 + v1848 = array_get v1740, index Field 15 + v1849 = array_get v1741, index Field 15 + v1850 = cast v1729 as u4 + v1851 = cast v1742 as u4 + v1852 = mul v1850, v1848 + v1853 = mul v1851, v1849 + v1854 = add v1852, v1853 + store [v1749, v1756, v1763, v1770, v1777, v1784, v1791, v1798, v1805, v1812, v1819, v1826, v1833, v1840, v1847, v1854] at v825 + enable_side_effects u1 1 + v1856 = cast v832 as u4 + v1857 = cast v1637 as u4 + v1858 = mul v1856, v1530 + v1859 = mul v1857, v1749 + v1860 = add v1858, v1859 + v1861 = cast v832 as u4 + v1862 = cast v1637 as u4 + v1863 = mul v1861, v1537 + v1864 = mul v1862, v1756 + v1865 = add v1863, v1864 + v1866 = cast v832 as u4 + v1867 = cast v1637 as u4 + v1868 = mul v1866, v1544 + v1869 = mul v1867, v1763 + v1870 = add v1868, v1869 + v1871 = cast v832 as u4 + v1872 = cast v1637 as u4 + v1873 = mul v1871, v1551 + v1874 = mul v1872, v1770 + v1875 = add v1873, v1874 + v1876 = cast v832 as u4 + v1877 = cast v1637 as u4 + v1878 = mul v1876, v1558 + v1879 = mul v1877, v1777 + v1880 = add v1878, v1879 + v1881 = cast v832 as u4 + v1882 = cast v1637 as u4 + v1883 = mul v1881, v1565 + v1884 = mul v1882, v1784 + v1885 = add v1883, v1884 + v1886 = cast v832 as u4 + v1887 = cast v1637 as u4 + v1888 = mul v1886, v1572 + v1889 = mul v1887, v1791 + v1890 = add v1888, v1889 + v1891 = cast v832 as u4 + v1892 = cast v1637 as u4 + v1893 = mul v1891, v1579 + v1894 = mul v1892, v1798 + v1895 = add v1893, v1894 + v1896 = cast v832 as u4 + v1897 = cast v1637 as u4 + v1898 = mul v1896, v1586 + v1899 = mul v1897, v1805 + v1900 = add v1898, v1899 + v1901 = cast v832 as u4 + v1902 = cast v1637 as u4 + v1903 = mul v1901, v1593 + v1904 = mul v1902, v1812 + v1905 = add v1903, v1904 + v1906 = cast v832 as u4 + v1907 = cast v1637 as u4 + v1908 = mul v1906, v1600 + v1909 = mul v1907, v1819 + v1910 = add v1908, v1909 + v1911 = cast v832 as u4 + v1912 = cast v1637 as u4 + v1913 = mul v1911, v1607 + v1914 = mul v1912, v1826 + v1915 = add v1913, v1914 + v1916 = cast v832 as u4 + v1917 = cast v1637 as u4 + v1918 = mul v1916, v1614 + v1919 = mul v1917, v1833 + v1920 = add v1918, v1919 + v1921 = cast v832 as u4 + v1922 = cast v1637 as u4 + v1923 = mul v1921, v1621 + v1924 = mul v1922, v1840 + v1925 = add v1923, v1924 + v1926 = cast v832 as u4 + v1927 = cast v1637 as u4 + v1928 = mul v1926, v1628 + v1929 = mul v1927, v1847 + v1930 = add v1928, v1929 + v1931 = cast v832 as u4 + v1932 = cast v1637 as u4 + v1933 = mul v1931, v1635 + v1934 = mul v1932, v1854 + v1935 = add v1933, v1934 + store [v1860, v1865, v1870, v1875, v1880, v1885, v1890, v1895, v1900, v1905, v1910, v1915, v1920, v1925, v1930, v1935] at v825 + v1937 = load v825 + v1938 = mul Field 2, v1 + v1939 = cast v832 as Field + v1940 = add v1938, v1939 + v1941 = sub v1940, Field 2 + inc_rc v1937 + inc_rc v1937 + inc_rc v1937 + v1942 = eq v1941, Field 5 + constrain v1941 == Field 5 + v1943 = array_get v1937, index Field 0 + v1944 = array_get v1937, index Field 1 + v1945 = array_get v1937, index Field 2 + v1946 = array_get v1937, index Field 3 + v1947 = array_get v1937, index Field 4 + v1948 = allocate + v1949 = eq v1943, u4 15 + v1950 = eq v1944, u4 1 + v1951 = mul v1949, v1950 + v1952 = eq v1945, u4 12 + v1953 = mul v1951, v1952 + v1954 = eq v1946, u4 11 + v1955 = mul v1953, v1954 + v1956 = eq v1947, u4 8 + v1957 = mul v1955, v1956 + store v1957 at v1948 + constrain v1957 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v1962 = allocate + range_check u8 148 to 8 bits + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + store [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v1962 + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v1967 = allocate + store u1 1 at v1967 + v1968 = allocate + store u64 1 at v1968 + v1969 = allocate + store u64 2⁴ at v1969 + v1970 = allocate + store u64 1 at v1970 + v1971 = allocate + store u64 2⁴ at v1971 + return +} + +After Mem2Reg: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v1972 = truncate v1 to 64 bits, max_bit_size: 254 + v1973 = cast v1972 as u64 + inc_rc v0 + v1974 = lt u64 5, v1973 + v1975 = not v1974 + constrain v1974 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v1977 = allocate + v1979 = array_get v0, index Field 0 + v1980 = div v1979, Field 2⁴ + v1981 = truncate v1980 to 4 bits, max_bit_size: 8 + v1982 = cast v1981 as u4 + v1983 = truncate v1982 to 1 bits, max_bit_size: 4 + v1984 = cast v1983 as u1 + enable_side_effects v1984 + v1985 = array_get v0, index Field 0 + v1986 = and v1985, u8 15 + v1987 = truncate v1986 to 4 bits, max_bit_size: 8 + v1988 = cast v1987 as u4 + inc_rc v0 + v1991 = truncate v1 to 64 bits, max_bit_size: 254 + v1992 = cast v1991 as u64 + v1993 = lt u64 1, v1992 + v1994 = mul v1984, v1993 + enable_side_effects v1994 + v1995 = array_get v0, index Field 1 + v1996 = div v1995, Field 2⁴ + v1997 = truncate v1996 to 4 bits, max_bit_size: 8 + v1998 = cast v1997 as u4 + v1999 = and v1995, u8 15 + v2000 = truncate v1999 to 4 bits, max_bit_size: 8 + v2001 = cast v2000 as u4 + v2004 = not v1993 + enable_side_effects v1984 + v2007 = cast v1993 as u4 + v2008 = cast v2004 as u4 + v2009 = mul v2007, v1988 + v2010 = mul v2008, v1988 + v2011 = add v2009, v2010 + v2013 = cast v1993 as u4 + v2014 = cast v2004 as u4 + v2015 = mul v2013, v1998 + v2017 = cast v1993 as u4 + v2018 = cast v2004 as u4 + v2019 = mul v2017, v2001 + v2021 = cast v1993 as u4 + v2022 = cast v2004 as u4 + v2024 = cast v1993 as u4 + v2025 = cast v2004 as u4 + v2027 = cast v1993 as u4 + v2028 = cast v2004 as u4 + v2030 = cast v1993 as u4 + v2031 = cast v2004 as u4 + v2033 = cast v1993 as u4 + v2034 = cast v2004 as u4 + v2036 = cast v1993 as u4 + v2037 = cast v2004 as u4 + v2039 = cast v1993 as u4 + v2040 = cast v2004 as u4 + v2042 = cast v1993 as u4 + v2043 = cast v2004 as u4 + v2045 = cast v1993 as u4 + v2046 = cast v2004 as u4 + v2048 = cast v1993 as u4 + v2049 = cast v2004 as u4 + v2051 = cast v1993 as u4 + v2052 = cast v2004 as u4 + v2054 = cast v1993 as u4 + v2055 = cast v2004 as u4 + v2057 = cast v1993 as u4 + v2058 = cast v2004 as u4 + v2060 = truncate v1 to 64 bits, max_bit_size: 254 + v2061 = cast v2060 as u64 + v2062 = lt u64 2, v2061 + v2063 = mul v1984, v2062 + enable_side_effects v2063 + v2064 = array_get v0, index Field 2 + v2066 = div v2064, Field 2⁴ + v2067 = truncate v2066 to 4 bits, max_bit_size: 8 + v2068 = cast v2067 as u4 + v2071 = and v2064, u8 15 + v2072 = truncate v2071 to 4 bits, max_bit_size: 8 + v2073 = cast v2072 as u4 + v2078 = not v2062 + enable_side_effects v1984 + v2082 = cast v2062 as u4 + v2083 = cast v2078 as u4 + v2084 = mul v2082, v2011 + v2085 = mul v2083, v2011 + v2086 = add v2084, v2085 + v2089 = cast v2062 as u4 + v2090 = cast v2078 as u4 + v2091 = mul v2089, v2015 + v2092 = mul v2090, v2015 + v2093 = add v2091, v2092 + v2096 = cast v2062 as u4 + v2097 = cast v2078 as u4 + v2098 = mul v2096, v2019 + v2099 = mul v2097, v2019 + v2100 = add v2098, v2099 + v2103 = cast v2062 as u4 + v2104 = cast v2078 as u4 + v2105 = mul v2103, v2068 + v2108 = cast v2062 as u4 + v2109 = cast v2078 as u4 + v2110 = mul v2108, v2073 + v2113 = cast v2062 as u4 + v2114 = cast v2078 as u4 + v2117 = cast v2062 as u4 + v2118 = cast v2078 as u4 + v2121 = cast v2062 as u4 + v2122 = cast v2078 as u4 + v2125 = cast v2062 as u4 + v2126 = cast v2078 as u4 + v2129 = cast v2062 as u4 + v2130 = cast v2078 as u4 + v2133 = cast v2062 as u4 + v2134 = cast v2078 as u4 + v2137 = cast v2062 as u4 + v2138 = cast v2078 as u4 + v2141 = cast v2062 as u4 + v2142 = cast v2078 as u4 + v2145 = cast v2062 as u4 + v2146 = cast v2078 as u4 + v2149 = cast v2062 as u4 + v2150 = cast v2078 as u4 + v2153 = cast v2062 as u4 + v2154 = cast v2078 as u4 + v2156 = truncate v1 to 64 bits, max_bit_size: 254 + v2157 = cast v2156 as u64 + v2158 = lt u64 3, v2157 + v2159 = mul v1984, v2158 + enable_side_effects v2159 + v2160 = array_get v0, index Field 3 + v2162 = div v2160, Field 2⁴ + v2163 = truncate v2162 to 4 bits, max_bit_size: 8 + v2164 = cast v2163 as u4 + v2167 = and v2160, u8 15 + v2168 = truncate v2167 to 4 bits, max_bit_size: 8 + v2169 = cast v2168 as u4 + v2174 = not v2158 + enable_side_effects v1984 + v2178 = cast v2158 as u4 + v2179 = cast v2174 as u4 + v2180 = mul v2178, v2086 + v2181 = mul v2179, v2086 + v2182 = add v2180, v2181 + v2185 = cast v2158 as u4 + v2186 = cast v2174 as u4 + v2187 = mul v2185, v2093 + v2188 = mul v2186, v2093 + v2189 = add v2187, v2188 + v2192 = cast v2158 as u4 + v2193 = cast v2174 as u4 + v2194 = mul v2192, v2100 + v2195 = mul v2193, v2100 + v2196 = add v2194, v2195 + v2199 = cast v2158 as u4 + v2200 = cast v2174 as u4 + v2201 = mul v2199, v2105 + v2202 = mul v2200, v2105 + v2203 = add v2201, v2202 + v2206 = cast v2158 as u4 + v2207 = cast v2174 as u4 + v2208 = mul v2206, v2110 + v2209 = mul v2207, v2110 + v2210 = add v2208, v2209 + v2213 = cast v2158 as u4 + v2214 = cast v2174 as u4 + v2215 = mul v2213, v2164 + v2218 = cast v2158 as u4 + v2219 = cast v2174 as u4 + v2220 = mul v2218, v2169 + v2223 = cast v2158 as u4 + v2224 = cast v2174 as u4 + v2227 = cast v2158 as u4 + v2228 = cast v2174 as u4 + v2231 = cast v2158 as u4 + v2232 = cast v2174 as u4 + v2235 = cast v2158 as u4 + v2236 = cast v2174 as u4 + v2239 = cast v2158 as u4 + v2240 = cast v2174 as u4 + v2243 = cast v2158 as u4 + v2244 = cast v2174 as u4 + v2247 = cast v2158 as u4 + v2248 = cast v2174 as u4 + v2251 = cast v2158 as u4 + v2252 = cast v2174 as u4 + v2255 = cast v2158 as u4 + v2256 = cast v2174 as u4 + v2258 = truncate v1 to 64 bits, max_bit_size: 254 + v2259 = cast v2258 as u64 + v2260 = lt u64 4, v2259 + v2261 = mul v1984, v2260 + enable_side_effects v2261 + v2262 = array_get v0, index Field 4 + v2264 = div v2262, Field 2⁴ + v2265 = truncate v2264 to 4 bits, max_bit_size: 8 + v2266 = cast v2265 as u4 + v2269 = and v2262, u8 15 + v2270 = truncate v2269 to 4 bits, max_bit_size: 8 + v2271 = cast v2270 as u4 + v2276 = not v2260 + enable_side_effects v1984 + v2280 = cast v2260 as u4 + v2281 = cast v2276 as u4 + v2282 = mul v2280, v2182 + v2283 = mul v2281, v2182 + v2284 = add v2282, v2283 + v2287 = cast v2260 as u4 + v2288 = cast v2276 as u4 + v2289 = mul v2287, v2189 + v2290 = mul v2288, v2189 + v2291 = add v2289, v2290 + v2294 = cast v2260 as u4 + v2295 = cast v2276 as u4 + v2296 = mul v2294, v2196 + v2297 = mul v2295, v2196 + v2298 = add v2296, v2297 + v2301 = cast v2260 as u4 + v2302 = cast v2276 as u4 + v2303 = mul v2301, v2203 + v2304 = mul v2302, v2203 + v2305 = add v2303, v2304 + v2308 = cast v2260 as u4 + v2309 = cast v2276 as u4 + v2310 = mul v2308, v2210 + v2311 = mul v2309, v2210 + v2312 = add v2310, v2311 + v2315 = cast v2260 as u4 + v2316 = cast v2276 as u4 + v2317 = mul v2315, v2215 + v2318 = mul v2316, v2215 + v2319 = add v2317, v2318 + v2322 = cast v2260 as u4 + v2323 = cast v2276 as u4 + v2324 = mul v2322, v2220 + v2325 = mul v2323, v2220 + v2326 = add v2324, v2325 + v2329 = cast v2260 as u4 + v2330 = cast v2276 as u4 + v2331 = mul v2329, v2266 + v2334 = cast v2260 as u4 + v2335 = cast v2276 as u4 + v2336 = mul v2334, v2271 + v2339 = cast v2260 as u4 + v2340 = cast v2276 as u4 + v2343 = cast v2260 as u4 + v2344 = cast v2276 as u4 + v2347 = cast v2260 as u4 + v2348 = cast v2276 as u4 + v2351 = cast v2260 as u4 + v2352 = cast v2276 as u4 + v2355 = cast v2260 as u4 + v2356 = cast v2276 as u4 + v2359 = cast v2260 as u4 + v2360 = cast v2276 as u4 + v2363 = cast v2260 as u4 + v2364 = cast v2276 as u4 + v2366 = not v1984 + enable_side_effects v2366 + v2368 = truncate v1 to 64 bits, max_bit_size: 254 + v2369 = cast v2368 as u64 + v2370 = sub v2369, u64 1 + v2371 = cast v2366 as u64 + v2372 = mul v2370, v2371 + range_check v2372 to 64 bits + v2373 = lt u64 0, v2370 + v2374 = mul v2366, v2373 + enable_side_effects v2374 + v2375 = array_get v0, index u64 1 + v2376 = div v2375, Field 2⁴ + v2377 = truncate v2376 to 4 bits, max_bit_size: 8 + v2378 = cast v2377 as u4 + v2379 = and v2375, u8 15 + v2380 = truncate v2379 to 4 bits, max_bit_size: 8 + v2381 = cast v2380 as u4 + v2384 = not v2373 + enable_side_effects v2366 + v2387 = cast v2373 as u4 + v2388 = cast v2384 as u4 + v2389 = mul v2387, v2378 + v2391 = cast v2373 as u4 + v2392 = cast v2384 as u4 + v2393 = mul v2391, v2381 + v2395 = cast v2373 as u4 + v2396 = cast v2384 as u4 + v2398 = cast v2373 as u4 + v2399 = cast v2384 as u4 + v2401 = cast v2373 as u4 + v2402 = cast v2384 as u4 + v2404 = cast v2373 as u4 + v2405 = cast v2384 as u4 + v2407 = cast v2373 as u4 + v2408 = cast v2384 as u4 + v2410 = cast v2373 as u4 + v2411 = cast v2384 as u4 + v2413 = cast v2373 as u4 + v2414 = cast v2384 as u4 + v2416 = cast v2373 as u4 + v2417 = cast v2384 as u4 + v2419 = cast v2373 as u4 + v2420 = cast v2384 as u4 + v2422 = cast v2373 as u4 + v2423 = cast v2384 as u4 + v2425 = cast v2373 as u4 + v2426 = cast v2384 as u4 + v2428 = cast v2373 as u4 + v2429 = cast v2384 as u4 + v2431 = cast v2373 as u4 + v2432 = cast v2384 as u4 + v2434 = cast v2373 as u4 + v2435 = cast v2384 as u4 + v2437 = truncate v1 to 64 bits, max_bit_size: 254 + v2438 = cast v2437 as u64 + v2439 = sub v2438, u64 1 + v2440 = cast v2366 as u64 + v2441 = mul v2439, v2440 + range_check v2441 to 64 bits + v2442 = lt u64 1, v2439 + v2443 = mul v2366, v2442 + enable_side_effects v2443 + v2444 = array_get v0, index u64 2 + v2446 = div v2444, Field 2⁴ + v2447 = truncate v2446 to 4 bits, max_bit_size: 8 + v2448 = cast v2447 as u4 + v2451 = and v2444, u8 15 + v2452 = truncate v2451 to 4 bits, max_bit_size: 8 + v2453 = cast v2452 as u4 + v2458 = not v2442 + enable_side_effects v2366 + v2462 = cast v2442 as u4 + v2463 = cast v2458 as u4 + v2464 = mul v2462, v2389 + v2465 = mul v2463, v2389 + v2466 = add v2464, v2465 + v2469 = cast v2442 as u4 + v2470 = cast v2458 as u4 + v2471 = mul v2469, v2393 + v2472 = mul v2470, v2393 + v2473 = add v2471, v2472 + v2476 = cast v2442 as u4 + v2477 = cast v2458 as u4 + v2478 = mul v2476, v2448 + v2481 = cast v2442 as u4 + v2482 = cast v2458 as u4 + v2483 = mul v2481, v2453 + v2486 = cast v2442 as u4 + v2487 = cast v2458 as u4 + v2490 = cast v2442 as u4 + v2491 = cast v2458 as u4 + v2494 = cast v2442 as u4 + v2495 = cast v2458 as u4 + v2498 = cast v2442 as u4 + v2499 = cast v2458 as u4 + v2502 = cast v2442 as u4 + v2503 = cast v2458 as u4 + v2506 = cast v2442 as u4 + v2507 = cast v2458 as u4 + v2510 = cast v2442 as u4 + v2511 = cast v2458 as u4 + v2514 = cast v2442 as u4 + v2515 = cast v2458 as u4 + v2518 = cast v2442 as u4 + v2519 = cast v2458 as u4 + v2522 = cast v2442 as u4 + v2523 = cast v2458 as u4 + v2526 = cast v2442 as u4 + v2527 = cast v2458 as u4 + v2530 = cast v2442 as u4 + v2531 = cast v2458 as u4 + enable_side_effects u1 1 + v2533 = cast v1984 as u4 + v2534 = cast v2366 as u4 + v2535 = mul v2533, v2284 + v2536 = mul v2534, v2466 + v2537 = add v2535, v2536 + v2538 = cast v1984 as u4 + v2539 = cast v2366 as u4 + v2540 = mul v2538, v2291 + v2541 = mul v2539, v2473 + v2542 = add v2540, v2541 + v2543 = cast v1984 as u4 + v2544 = cast v2366 as u4 + v2545 = mul v2543, v2298 + v2546 = mul v2544, v2478 + v2547 = add v2545, v2546 + v2548 = cast v1984 as u4 + v2549 = cast v2366 as u4 + v2550 = mul v2548, v2305 + v2551 = mul v2549, v2483 + v2552 = add v2550, v2551 + v2553 = cast v1984 as u4 + v2554 = cast v2366 as u4 + v2555 = mul v2553, v2312 + v2556 = cast v1984 as u4 + v2557 = cast v2366 as u4 + v2558 = mul v2556, v2319 + v2559 = cast v1984 as u4 + v2560 = cast v2366 as u4 + v2561 = mul v2559, v2326 + v2562 = cast v1984 as u4 + v2563 = cast v2366 as u4 + v2564 = mul v2562, v2331 + v2565 = cast v1984 as u4 + v2566 = cast v2366 as u4 + v2567 = mul v2565, v2336 + v2568 = cast v1984 as u4 + v2569 = cast v2366 as u4 + v2570 = cast v1984 as u4 + v2571 = cast v2366 as u4 + v2572 = cast v1984 as u4 + v2573 = cast v2366 as u4 + v2574 = cast v1984 as u4 + v2575 = cast v2366 as u4 + v2576 = cast v1984 as u4 + v2577 = cast v2366 as u4 + v2578 = cast v1984 as u4 + v2579 = cast v2366 as u4 + v2580 = cast v1984 as u4 + v2581 = cast v2366 as u4 + v2584 = mul Field 2, v1 + v2585 = cast v1984 as Field + v2586 = add v2584, v2585 + v2587 = sub v2586, Field 2 + inc_rc [v2537, v2542, v2547, v2552, v2555, v2558, v2561, v2564, v2567, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + inc_rc [v2537, v2542, v2547, v2552, v2555, v2558, v2561, v2564, v2567, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + inc_rc [v2537, v2542, v2547, v2552, v2555, v2558, v2561, v2564, v2567, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v2591 = eq v2587, Field 5 + constrain v2587 == Field 5 + v2597 = allocate + v2598 = eq v2537, u4 15 + v2599 = eq v2542, u4 1 + v2600 = mul v2598, v2599 + v2601 = eq v2547, u4 12 + v2602 = mul v2600, v2601 + v2603 = eq v2552, u4 11 + v2604 = mul v2602, v2603 + v2605 = eq v2555, u4 8 + v2606 = mul v2604, v2605 + constrain v2606 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v2611 = allocate + range_check u8 148 to 8 bits + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v2616 = allocate + v2617 = allocate + v2618 = allocate + v2619 = allocate + v2620 = allocate + return +} + +After Constant Folding: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v2621 = truncate v1 to 64 bits, max_bit_size: 254 + v2622 = cast v2621 as u64 + inc_rc v0 + v2623 = lt u64 5, v2622 + v2624 = not v2623 + constrain v2623 == u1 0 + inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v2625 = allocate + v2626 = array_get v0, index Field 0 + v2627 = div v2626, Field 2⁴ + v2628 = truncate v2627 to 4 bits, max_bit_size: 8 + v2629 = cast v2628 as u4 + v2630 = truncate v2629 to 1 bits, max_bit_size: 4 + v2631 = cast v2630 as u1 + enable_side_effects v2631 + v2632 = and v2626, u8 15 + v2633 = truncate v2632 to 4 bits, max_bit_size: 8 + v2634 = cast v2633 as u4 + inc_rc v0 + v2635 = lt u64 1, v2622 + v2636 = mul v2631, v2635 + enable_side_effects v2636 + v2637 = array_get v0, index Field 1 + v2638 = div v2637, Field 2⁴ + v2639 = truncate v2638 to 4 bits, max_bit_size: 8 + v2640 = cast v2639 as u4 + v2641 = and v2637, u8 15 + v2642 = truncate v2641 to 4 bits, max_bit_size: 8 + v2643 = cast v2642 as u4 + v2644 = not v2635 + enable_side_effects v2631 + v2645 = cast v2635 as u4 + v2646 = cast v2644 as u4 + v2647 = mul v2645, v2634 + v2648 = mul v2646, v2634 + v2649 = add v2647, v2648 + v2650 = mul v2645, v2640 + v2651 = mul v2645, v2643 + v2652 = lt u64 2, v2622 + v2653 = mul v2631, v2652 + enable_side_effects v2653 + v2654 = array_get v0, index Field 2 + v2655 = div v2654, Field 2⁴ + v2656 = truncate v2655 to 4 bits, max_bit_size: 8 + v2657 = cast v2656 as u4 + v2658 = and v2654, u8 15 + v2659 = truncate v2658 to 4 bits, max_bit_size: 8 + v2660 = cast v2659 as u4 + v2661 = not v2652 + enable_side_effects v2631 + v2662 = cast v2652 as u4 + v2663 = cast v2661 as u4 + v2664 = mul v2662, v2649 + v2665 = mul v2663, v2649 + v2666 = add v2664, v2665 + v2667 = mul v2662, v2650 + v2668 = mul v2663, v2650 + v2669 = add v2667, v2668 + v2670 = mul v2662, v2651 + v2671 = mul v2663, v2651 + v2672 = add v2670, v2671 + v2673 = mul v2662, v2657 + v2674 = mul v2662, v2660 + v2675 = lt u64 3, v2622 + v2676 = mul v2631, v2675 + enable_side_effects v2676 + v2677 = array_get v0, index Field 3 + v2678 = div v2677, Field 2⁴ + v2679 = truncate v2678 to 4 bits, max_bit_size: 8 + v2680 = cast v2679 as u4 + v2681 = and v2677, u8 15 + v2682 = truncate v2681 to 4 bits, max_bit_size: 8 + v2683 = cast v2682 as u4 + v2684 = not v2675 + enable_side_effects v2631 + v2685 = cast v2675 as u4 + v2686 = cast v2684 as u4 + v2687 = mul v2685, v2666 + v2688 = mul v2686, v2666 + v2689 = add v2687, v2688 + v2690 = mul v2685, v2669 + v2691 = mul v2686, v2669 + v2692 = add v2690, v2691 + v2693 = mul v2685, v2672 + v2694 = mul v2686, v2672 + v2695 = add v2693, v2694 + v2696 = mul v2685, v2673 + v2697 = mul v2686, v2673 + v2698 = add v2696, v2697 + v2699 = mul v2685, v2674 + v2700 = mul v2686, v2674 + v2701 = add v2699, v2700 + v2702 = mul v2685, v2680 + v2703 = mul v2685, v2683 + v2704 = lt u64 4, v2622 + v2705 = mul v2631, v2704 + enable_side_effects v2705 + v2706 = array_get v0, index Field 4 + v2707 = div v2706, Field 2⁴ + v2708 = truncate v2707 to 4 bits, max_bit_size: 8 + v2709 = cast v2708 as u4 + v2710 = and v2706, u8 15 + v2711 = truncate v2710 to 4 bits, max_bit_size: 8 + v2712 = cast v2711 as u4 + v2713 = not v2704 + enable_side_effects v2631 + v2714 = cast v2704 as u4 + v2715 = cast v2713 as u4 + v2716 = mul v2714, v2689 + v2717 = mul v2715, v2689 + v2718 = add v2716, v2717 + v2719 = mul v2714, v2692 + v2720 = mul v2715, v2692 + v2721 = add v2719, v2720 + v2722 = mul v2714, v2695 + v2723 = mul v2715, v2695 + v2724 = add v2722, v2723 + v2725 = mul v2714, v2698 + v2726 = mul v2715, v2698 + v2727 = add v2725, v2726 + v2728 = mul v2714, v2701 + v2729 = mul v2715, v2701 + v2730 = add v2728, v2729 + v2731 = mul v2714, v2702 + v2732 = mul v2715, v2702 + v2733 = add v2731, v2732 + v2734 = mul v2714, v2703 + v2735 = mul v2715, v2703 + v2736 = add v2734, v2735 + v2737 = mul v2714, v2709 + v2738 = mul v2714, v2712 + v2739 = not v2631 + enable_side_effects v2739 + v2740 = sub v2622, u64 1 + v2741 = cast v2739 as u64 + v2742 = mul v2740, v2741 + range_check v2742 to 64 bits + v2743 = lt u64 0, v2740 + v2744 = mul v2739, v2743 + enable_side_effects v2744 + v2745 = array_get v0, index u64 1 + v2746 = div v2745, Field 2⁴ + v2747 = truncate v2746 to 4 bits, max_bit_size: 8 + v2748 = cast v2747 as u4 + v2749 = and v2745, u8 15 + v2750 = truncate v2749 to 4 bits, max_bit_size: 8 + v2751 = cast v2750 as u4 + v2752 = not v2743 + enable_side_effects v2739 + v2753 = cast v2743 as u4 + v2754 = cast v2752 as u4 + v2755 = mul v2753, v2748 + v2756 = mul v2753, v2751 + range_check v2742 to 64 bits + v2757 = lt u64 1, v2740 + v2758 = mul v2739, v2757 + enable_side_effects v2758 + v2759 = array_get v0, index u64 2 + v2760 = div v2759, Field 2⁴ + v2761 = truncate v2760 to 4 bits, max_bit_size: 8 + v2762 = cast v2761 as u4 + v2763 = and v2759, u8 15 + v2764 = truncate v2763 to 4 bits, max_bit_size: 8 + v2765 = cast v2764 as u4 + v2766 = not v2757 + enable_side_effects v2739 + v2767 = cast v2757 as u4 + v2768 = cast v2766 as u4 + v2769 = mul v2767, v2755 + v2770 = mul v2768, v2755 + v2771 = add v2769, v2770 + v2772 = mul v2767, v2756 + v2773 = mul v2768, v2756 + v2774 = add v2772, v2773 + v2775 = mul v2767, v2762 + v2776 = mul v2767, v2765 + enable_side_effects u1 1 + v2777 = cast v2631 as u4 + v2778 = cast v2739 as u4 + v2779 = mul v2777, v2718 + v2780 = mul v2778, v2771 + v2781 = add v2779, v2780 + v2782 = mul v2777, v2721 + v2783 = mul v2778, v2774 + v2784 = add v2782, v2783 + v2785 = mul v2777, v2724 + v2786 = mul v2778, v2775 + v2787 = add v2785, v2786 + v2788 = mul v2777, v2727 + v2789 = mul v2778, v2776 + v2790 = add v2788, v2789 + v2791 = mul v2777, v2730 + v2792 = mul v2777, v2733 + v2793 = mul v2777, v2736 + v2794 = mul v2777, v2737 + v2795 = mul v2777, v2738 + v2796 = mul Field 2, v1 + v2797 = cast v2631 as Field + v2798 = add v2796, v2797 + v2799 = sub v2798, Field 2 + inc_rc [v2781, v2784, v2787, v2790, v2791, v2792, v2793, v2794, v2795, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + inc_rc [v2781, v2784, v2787, v2790, v2791, v2792, v2793, v2794, v2795, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + inc_rc [v2781, v2784, v2787, v2790, v2791, v2792, v2793, v2794, v2795, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] + v2800 = eq v2799, Field 5 + constrain v2799 == Field 5 + v2801 = allocate + v2802 = eq v2781, u4 15 + v2803 = eq v2784, u4 1 + v2804 = mul v2802, v2803 + v2805 = eq v2787, u4 12 + v2806 = mul v2804, v2805 + v2807 = eq v2790, u4 11 + v2808 = mul v2806, v2807 + v2809 = eq v2791, u4 8 + v2810 = mul v2808, v2809 + constrain v2810 == u1 1 + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v2811 = allocate + range_check u8 148 to 8 bits + inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] + v2812 = allocate + v2813 = allocate + v2814 = allocate + v2815 = allocate + v2816 = allocate + return +} + +After Dead Instruction Elimination: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v2621 = truncate v1 to 64 bits, max_bit_size: 254 + v2622 = cast v2621 as u64 + inc_rc v0 + v2623 = lt u64 5, v2622 + constrain v2623 == u1 0 + v2626 = array_get v0, index Field 0 + v2627 = div v2626, Field 2⁴ + v2628 = truncate v2627 to 4 bits, max_bit_size: 8 + v2629 = cast v2628 as u4 + v2630 = truncate v2629 to 1 bits, max_bit_size: 4 + v2631 = cast v2630 as u1 + enable_side_effects v2631 + v2632 = and v2626, u8 15 + v2633 = truncate v2632 to 4 bits, max_bit_size: 8 + v2634 = cast v2633 as u4 + inc_rc v0 + v2635 = lt u64 1, v2622 + v2636 = mul v2631, v2635 + enable_side_effects v2636 + v2637 = array_get v0, index Field 1 + v2638 = div v2637, Field 2⁴ + v2639 = truncate v2638 to 4 bits, max_bit_size: 8 + v2640 = cast v2639 as u4 + v2641 = and v2637, u8 15 + v2642 = truncate v2641 to 4 bits, max_bit_size: 8 + v2643 = cast v2642 as u4 + v2644 = not v2635 + enable_side_effects v2631 + v2645 = cast v2635 as u4 + v2646 = cast v2644 as u4 + v2647 = mul v2645, v2634 + v2648 = mul v2646, v2634 + v2649 = add v2647, v2648 + v2650 = mul v2645, v2640 + v2651 = mul v2645, v2643 + v2652 = lt u64 2, v2622 + v2653 = mul v2631, v2652 + enable_side_effects v2653 + v2654 = array_get v0, index Field 2 + v2655 = div v2654, Field 2⁴ + v2656 = truncate v2655 to 4 bits, max_bit_size: 8 + v2657 = cast v2656 as u4 + v2658 = and v2654, u8 15 + v2659 = truncate v2658 to 4 bits, max_bit_size: 8 + v2660 = cast v2659 as u4 + v2661 = not v2652 + enable_side_effects v2631 + v2662 = cast v2652 as u4 + v2663 = cast v2661 as u4 + v2664 = mul v2662, v2649 + v2665 = mul v2663, v2649 + v2666 = add v2664, v2665 + v2667 = mul v2662, v2650 + v2668 = mul v2663, v2650 + v2669 = add v2667, v2668 + v2670 = mul v2662, v2651 + v2671 = mul v2663, v2651 + v2672 = add v2670, v2671 + v2673 = mul v2662, v2657 + v2674 = mul v2662, v2660 + v2675 = lt u64 3, v2622 + v2676 = mul v2631, v2675 + enable_side_effects v2676 + v2684 = not v2675 + enable_side_effects v2631 + v2685 = cast v2675 as u4 + v2686 = cast v2684 as u4 + v2687 = mul v2685, v2666 + v2688 = mul v2686, v2666 + v2689 = add v2687, v2688 + v2690 = mul v2685, v2669 + v2691 = mul v2686, v2669 + v2692 = add v2690, v2691 + v2693 = mul v2685, v2672 + v2694 = mul v2686, v2672 + v2695 = add v2693, v2694 + v2696 = mul v2685, v2673 + v2697 = mul v2686, v2673 + v2698 = add v2696, v2697 + v2699 = mul v2685, v2674 + v2700 = mul v2686, v2674 + v2701 = add v2699, v2700 + v2704 = lt u64 4, v2622 + v2705 = mul v2631, v2704 + enable_side_effects v2705 + v2713 = not v2704 + enable_side_effects v2631 + v2714 = cast v2704 as u4 + v2715 = cast v2713 as u4 + v2716 = mul v2714, v2689 + v2717 = mul v2715, v2689 + v2718 = add v2716, v2717 + v2719 = mul v2714, v2692 + v2720 = mul v2715, v2692 + v2721 = add v2719, v2720 + v2722 = mul v2714, v2695 + v2723 = mul v2715, v2695 + v2724 = add v2722, v2723 + v2725 = mul v2714, v2698 + v2726 = mul v2715, v2698 + v2727 = add v2725, v2726 + v2728 = mul v2714, v2701 + v2729 = mul v2715, v2701 + v2730 = add v2728, v2729 + v2739 = not v2631 + enable_side_effects v2739 + v2740 = sub v2622, u64 1 + v2741 = cast v2739 as u64 + v2742 = mul v2740, v2741 + range_check v2742 to 64 bits + v2743 = lt u64 0, v2740 + v2744 = mul v2739, v2743 + enable_side_effects v2744 + v2745 = array_get v0, index u64 1 + v2746 = div v2745, Field 2⁴ + v2747 = truncate v2746 to 4 bits, max_bit_size: 8 + v2748 = cast v2747 as u4 + v2749 = and v2745, u8 15 + v2750 = truncate v2749 to 4 bits, max_bit_size: 8 + v2751 = cast v2750 as u4 + enable_side_effects v2739 + v2753 = cast v2743 as u4 + v2755 = mul v2753, v2748 + v2756 = mul v2753, v2751 + range_check v2742 to 64 bits + v2757 = lt u64 1, v2740 + v2758 = mul v2739, v2757 + enable_side_effects v2758 + v2759 = array_get v0, index u64 2 + v2760 = div v2759, Field 2⁴ + v2761 = truncate v2760 to 4 bits, max_bit_size: 8 + v2762 = cast v2761 as u4 + v2763 = and v2759, u8 15 + v2764 = truncate v2763 to 4 bits, max_bit_size: 8 + v2765 = cast v2764 as u4 + v2766 = not v2757 + enable_side_effects v2739 + v2767 = cast v2757 as u4 + v2768 = cast v2766 as u4 + v2769 = mul v2767, v2755 + v2770 = mul v2768, v2755 + v2771 = add v2769, v2770 + v2772 = mul v2767, v2756 + v2773 = mul v2768, v2756 + v2774 = add v2772, v2773 + v2775 = mul v2767, v2762 + v2776 = mul v2767, v2765 + enable_side_effects u1 1 + v2777 = cast v2631 as u4 + v2778 = cast v2739 as u4 + v2779 = mul v2777, v2718 + v2780 = mul v2778, v2771 + v2781 = add v2779, v2780 + v2782 = mul v2777, v2721 + v2783 = mul v2778, v2774 + v2784 = add v2782, v2783 + v2785 = mul v2777, v2724 + v2786 = mul v2778, v2775 + v2787 = add v2785, v2786 + v2788 = mul v2777, v2727 + v2789 = mul v2778, v2776 + v2790 = add v2788, v2789 + v2791 = mul v2777, v2730 + v2796 = mul Field 2, v1 + v2797 = cast v2631 as Field + v2798 = add v2796, v2797 + v2799 = sub v2798, Field 2 + constrain v2799 == Field 5 + v2802 = eq v2781, u4 15 + v2803 = eq v2784, u4 1 + v2804 = mul v2802, v2803 + v2805 = eq v2787, u4 12 + v2806 = mul v2804, v2805 + v2807 = eq v2790, u4 11 + v2808 = mul v2806, v2807 + v2809 = eq v2791, u4 8 + v2810 = mul v2808, v2809 + constrain v2810 == u1 1 + range_check u8 148 to 8 bits + return +} + +After Fill Internal Slice Dummy Data: +acir fn main f0 { + b0(v0: [u8; 5], v1: Field): + inc_rc v0 + inc_rc v0 + v2817 = truncate v1 to 64 bits, max_bit_size: 254 + v2818 = cast v2817 as u64 + inc_rc v0 + v2819 = lt u64 5, v2818 + constrain v2819 == u1 0 + v2820 = array_get v0, index Field 0 + v2821 = div v2820, Field 2⁴ + v2822 = truncate v2821 to 4 bits, max_bit_size: 8 + v2823 = cast v2822 as u4 + v2824 = truncate v2823 to 1 bits, max_bit_size: 4 + v2825 = cast v2824 as u1 + enable_side_effects v2825 + v2826 = and v2820, u8 15 + v2827 = truncate v2826 to 4 bits, max_bit_size: 8 + v2828 = cast v2827 as u4 + inc_rc v0 + v2829 = lt u64 1, v2818 + v2830 = mul v2825, v2829 + enable_side_effects v2830 + v2831 = array_get v0, index Field 1 + v2832 = div v2831, Field 2⁴ + v2833 = truncate v2832 to 4 bits, max_bit_size: 8 + v2834 = cast v2833 as u4 + v2835 = and v2831, u8 15 + v2836 = truncate v2835 to 4 bits, max_bit_size: 8 + v2837 = cast v2836 as u4 + v2838 = not v2829 + enable_side_effects v2825 + v2839 = cast v2829 as u4 + v2840 = cast v2838 as u4 + v2841 = mul v2839, v2828 + v2842 = mul v2840, v2828 + v2843 = add v2841, v2842 + v2844 = mul v2839, v2834 + v2845 = mul v2839, v2837 + v2846 = lt u64 2, v2818 + v2847 = mul v2825, v2846 + enable_side_effects v2847 + v2848 = array_get v0, index Field 2 + v2849 = div v2848, Field 2⁴ + v2850 = truncate v2849 to 4 bits, max_bit_size: 8 + v2851 = cast v2850 as u4 + v2852 = and v2848, u8 15 + v2853 = truncate v2852 to 4 bits, max_bit_size: 8 + v2854 = cast v2853 as u4 + v2855 = not v2846 + enable_side_effects v2825 + v2856 = cast v2846 as u4 + v2857 = cast v2855 as u4 + v2858 = mul v2856, v2843 + v2859 = mul v2857, v2843 + v2860 = add v2858, v2859 + v2861 = mul v2856, v2844 + v2862 = mul v2857, v2844 + v2863 = add v2861, v2862 + v2864 = mul v2856, v2845 + v2865 = mul v2857, v2845 + v2866 = add v2864, v2865 + v2867 = mul v2856, v2851 + v2868 = mul v2856, v2854 + v2869 = lt u64 3, v2818 + v2870 = mul v2825, v2869 + enable_side_effects v2870 + v2871 = not v2869 + enable_side_effects v2825 + v2872 = cast v2869 as u4 + v2873 = cast v2871 as u4 + v2874 = mul v2872, v2860 + v2875 = mul v2873, v2860 + v2876 = add v2874, v2875 + v2877 = mul v2872, v2863 + v2878 = mul v2873, v2863 + v2879 = add v2877, v2878 + v2880 = mul v2872, v2866 + v2881 = mul v2873, v2866 + v2882 = add v2880, v2881 + v2883 = mul v2872, v2867 + v2884 = mul v2873, v2867 + v2885 = add v2883, v2884 + v2886 = mul v2872, v2868 + v2887 = mul v2873, v2868 + v2888 = add v2886, v2887 + v2889 = lt u64 4, v2818 + v2890 = mul v2825, v2889 + enable_side_effects v2890 + v2891 = not v2889 + enable_side_effects v2825 + v2892 = cast v2889 as u4 + v2893 = cast v2891 as u4 + v2894 = mul v2892, v2876 + v2895 = mul v2893, v2876 + v2896 = add v2894, v2895 + v2897 = mul v2892, v2879 + v2898 = mul v2893, v2879 + v2899 = add v2897, v2898 + v2900 = mul v2892, v2882 + v2901 = mul v2893, v2882 + v2902 = add v2900, v2901 + v2903 = mul v2892, v2885 + v2904 = mul v2893, v2885 + v2905 = add v2903, v2904 + v2906 = mul v2892, v2888 + v2907 = mul v2893, v2888 + v2908 = add v2906, v2907 + v2909 = not v2825 + enable_side_effects v2909 + v2910 = sub v2818, u64 1 + v2911 = cast v2909 as u64 + v2912 = mul v2910, v2911 + range_check v2912 to 64 bits + v2913 = lt u64 0, v2910 + v2914 = mul v2909, v2913 + enable_side_effects v2914 + v2915 = array_get v0, index u64 1 + v2916 = div v2915, Field 2⁴ + v2917 = truncate v2916 to 4 bits, max_bit_size: 8 + v2918 = cast v2917 as u4 + v2919 = and v2915, u8 15 + v2920 = truncate v2919 to 4 bits, max_bit_size: 8 + v2921 = cast v2920 as u4 + enable_side_effects v2909 + v2922 = cast v2913 as u4 + v2923 = mul v2922, v2918 + v2924 = mul v2922, v2921 + range_check v2912 to 64 bits + v2925 = lt u64 1, v2910 + v2926 = mul v2909, v2925 + enable_side_effects v2926 + v2927 = array_get v0, index u64 2 + v2928 = div v2927, Field 2⁴ + v2929 = truncate v2928 to 4 bits, max_bit_size: 8 + v2930 = cast v2929 as u4 + v2931 = and v2927, u8 15 + v2932 = truncate v2931 to 4 bits, max_bit_size: 8 + v2933 = cast v2932 as u4 + v2934 = not v2925 + enable_side_effects v2909 + v2935 = cast v2925 as u4 + v2936 = cast v2934 as u4 + v2937 = mul v2935, v2923 + v2938 = mul v2936, v2923 + v2939 = add v2937, v2938 + v2940 = mul v2935, v2924 + v2941 = mul v2936, v2924 + v2942 = add v2940, v2941 + v2943 = mul v2935, v2930 + v2944 = mul v2935, v2933 + enable_side_effects u1 1 + v2945 = cast v2825 as u4 + v2946 = cast v2909 as u4 + v2947 = mul v2945, v2896 + v2948 = mul v2946, v2939 + v2949 = add v2947, v2948 + v2950 = mul v2945, v2899 + v2951 = mul v2946, v2942 + v2952 = add v2950, v2951 + v2953 = mul v2945, v2902 + v2954 = mul v2946, v2943 + v2955 = add v2953, v2954 + v2956 = mul v2945, v2905 + v2957 = mul v2946, v2944 + v2958 = add v2956, v2957 + v2959 = mul v2945, v2908 + v2960 = mul Field 2, v1 + v2961 = cast v2825 as Field + v2962 = add v2960, v2961 + v2963 = sub v2962, Field 2 + constrain v2963 == Field 5 + v2964 = eq v2949, u4 15 + v2965 = eq v2952, u4 1 + v2966 = mul v2964, v2965 + v2967 = eq v2955, u4 12 + v2968 = mul v2966, v2967 + v2969 = eq v2958, u4 11 + v2970 = mul v2968, v2969 + v2971 = eq v2959, u4 8 + v2972 = mul v2970, v2971 + constrain v2972 == u1 1 + range_check u8 148 to 8 bits + return +} + diff --git a/test_programs/execution_success/regression/old-acir b/test_programs/execution_success/regression/old-acir new file mode 100644 index 00000000000..44e1ded5777 --- /dev/null +++ b/test_programs/execution_success/regression/old-acir @@ -0,0 +1,288 @@ +Compiled ACIR for main (unoptimized): +current witness index : 132 +public parameters indices : [] +return value indices : [] +BLACKBOX::RANGE [(_1, num_bits: 8)] [ ] +BLACKBOX::RANGE [(_2, num_bits: 8)] [ ] +BLACKBOX::RANGE [(_3, num_bits: 8)] [ ] +BLACKBOX::RANGE [(_4, num_bits: 8)] [ ] +BLACKBOX::RANGE [(_5, num_bits: 8)] [ ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(6))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(7)), Simple(Witness(8))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 255, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 255, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 255, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_7, num_bits: 190)] [ ] +BLACKBOX::RANGE [(_8, num_bits: 64)] [ ] +EXPR [ (1, _6) (-2⁶⁴, _7) (-1, _8) 0 ] +EXPR [ (1, _7) (-1, _9) -1186564023676924939888766319973246049704924238154051448977 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(9))], q_c: 0 })] +outputs: [Simple(Witness(10))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _9, _10) (1, _11) -1 ] +EXPR [ (1, _9, _11) 0 ] +EXPR [ (-1, _8, _11) (2¹⁶×74637766815744, _11) (-1, _12) 0 ] +BLACKBOX::RANGE [(_12, num_bits: 65)] [ ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551621 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(13)), Simple(Witness(14))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_14, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _13) (-1, _14) 18446744073709551621 ] +EXPR [ (-1, _13) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(1))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(15)), Simple(Witness(16))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_15, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_16, num_bits: 4)] [ ] +EXPR [ (1, _1) (-2⁴, _15) (-1, _16) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(15))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(17)), Simple(Witness(18))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_17, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_18, num_bits: 4)] [ ] +EXPR [ (1, _15) (-2⁴, _17) (-1, _18) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(18))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2 })] +outputs: [Simple(Witness(19)), Simple(Witness(20))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 5, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 5, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 5, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_19, num_bits: 3)] [ ] +EXPR [ (1, _20, _20) (-1, _20) 0 ] +EXPR [ (1, _18) (-2, _19) (-1, _20) 0 ] +EXPR [ (-1, _21) 15 ] +BLACKBOX::AND [(_1, num_bits: 8), (_21, num_bits: 8)] [ _22] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(22))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(23)), Simple(Witness(24))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_23, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_24, num_bits: 4)] [ ] +EXPR [ (1, _22) (-2⁴, _23) (-1, _24) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551617 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(25)), Simple(Witness(26))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _25, _25) (-1, _25) 0 ] +BLACKBOX::RANGE [(_26, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _25) (-1, _26) 18446744073709551617 ] +EXPR [ (-1, _25) (-1, _27) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(2))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(28)), Simple(Witness(29))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_28, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_29, num_bits: 5)] [ ] +EXPR [ (1, _20, _27) (1, _29) (-1, _30) 15 ] +BLACKBOX::RANGE [(_30, num_bits: 5)] [ ] +EXPR [ (2⁴, _28) (1, _29) (-1, _31) 0 ] +EXPR [ (1, _20, _27) (-1, _32) 0 ] +EXPR [ (1, _2, _32) (-1, _31, _32) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(28))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(33)), Simple(Witness(34))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_33, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_34, num_bits: 4)] [ ] +EXPR [ (1, _28) (-2⁴, _33) (-1, _34) 0 ] +BLACKBOX::AND [(_2, num_bits: 8), (_21, num_bits: 8)] [ _35] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(35))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(36)), Simple(Witness(37))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_36, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_37, num_bits: 4)] [ ] +EXPR [ (1, _35) (-2⁴, _36) (-1, _37) 0 ] +EXPR [ (-1, _27) (-1, _38) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551618 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(39)), Simple(Witness(40))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _39, _39) (-1, _39) 0 ] +BLACKBOX::RANGE [(_40, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _39) (-1, _40) 18446744073709551618 ] +EXPR [ (-1, _39) (-1, _41) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(3))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(42)), Simple(Witness(43))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_42, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_43, num_bits: 5)] [ ] +EXPR [ (1, _20, _41) (1, _43) (-1, _44) 15 ] +BLACKBOX::RANGE [(_44, num_bits: 5)] [ ] +EXPR [ (2⁴, _42) (1, _43) (-1, _45) 0 ] +EXPR [ (1, _20, _41) (-1, _46) 0 ] +EXPR [ (1, _3, _46) (-1, _45, _46) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(42))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(47)), Simple(Witness(48))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_47, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_48, num_bits: 4)] [ ] +EXPR [ (1, _42) (-2⁴, _47) (-1, _48) 0 ] +BLACKBOX::AND [(_3, num_bits: 8), (_21, num_bits: 8)] [ _49] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(49))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(50)), Simple(Witness(51))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_50, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_51, num_bits: 4)] [ ] +EXPR [ (1, _49) (-2⁴, _50) (-1, _51) 0 ] +EXPR [ (1, _24, _27) (1, _24, _38) (-1, _52) 0 ] +EXPR [ (-1, _41) (-1, _53) 1 ] +EXPR [ (1, _27, _34) (-1, _54) 0 ] +EXPR [ (1, _27, _37) (-1, _55) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551619 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(56)), Simple(Witness(57))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _56, _56) (-1, _56) 0 ] +BLACKBOX::RANGE [(_57, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _56) (-1, _57) 18446744073709551619 ] +EXPR [ (-1, _56) (-1, _58) 1 ] +EXPR [ (1, _41, _52) (1, _52, _53) (-1, _59) 0 ] +EXPR [ (-1, _58) (-1, _60) 1 ] +EXPR [ (1, _41, _54) (1, _53, _54) (-1, _61) 0 ] +EXPR [ (1, _41, _55) (1, _53, _55) (-1, _62) 0 ] +EXPR [ (1, _41, _48) (-1, _63) 0 ] +EXPR [ (1, _41, _51) (-1, _64) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551620 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(65)), Simple(Witness(66))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _65, _65) (-1, _65) 0 ] +BLACKBOX::RANGE [(_66, num_bits: 64)] [ ] +EXPR [ (-1, _8) (-2⁶⁴, _65) (-1, _66) 18446744073709551620 ] +EXPR [ (-1, _65) (-1, _67) 1 ] +EXPR [ (1, _58, _59) (1, _59, _60) (-1, _68) 0 ] +EXPR [ (-1, _67) (-1, _69) 1 ] +EXPR [ (1, _58, _61) (1, _60, _61) (-1, _70) 0 ] +EXPR [ (1, _58, _62) (1, _60, _62) (-1, _71) 0 ] +EXPR [ (1, _58, _63) (1, _60, _63) (-1, _72) 0 ] +EXPR [ (1, _58, _64) (1, _60, _64) (-1, _73) 0 ] +EXPR [ (1, _8) (-1, _74) -1 ] +EXPR [ (-1, _20) (-1, _75) 1 ] +EXPR [ (1, _74, _75) (-1, _76) 0 ] +BLACKBOX::RANGE [(_76, num_bits: 64)] [ ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(74))], q_c: 2⁶⁴ }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(77)), Simple(Witness(78))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _77, _77) (-1, _77) 0 ] +BLACKBOX::RANGE [(_78, num_bits: 64)] [ ] +EXPR [ (-1, _74) (-2⁶⁴, _77) (-1, _78) 2⁶⁴ ] +EXPR [ (-1, _77) (-1, _79) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(2))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(80)), Simple(Witness(81))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_80, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_81, num_bits: 5)] [ ] +EXPR [ (1, _75, _79) (1, _81) (-1, _82) 15 ] +BLACKBOX::RANGE [(_82, num_bits: 5)] [ ] +EXPR [ (2⁴, _80) (1, _81) (-1, _83) 0 ] +EXPR [ (1, _75, _79) (-1, _84) 0 ] +EXPR [ (1, _2, _84) (-1, _83, _84) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(80))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(85)), Simple(Witness(86))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_85, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_86, num_bits: 4)] [ ] +EXPR [ (1, _80) (-2⁴, _85) (-1, _86) 0 ] +BLACKBOX::AND [(_2, num_bits: 8), (_21, num_bits: 8)] [ _87] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(87))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(88)), Simple(Witness(89))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_88, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_89, num_bits: 4)] [ ] +EXPR [ (1, _87) (-2⁴, _88) (-1, _89) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(74))], q_c: 18446744073709551617 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] +outputs: [Simple(Witness(90)), Simple(Witness(91))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +EXPR [ (1, _90, _90) (-1, _90) 0 ] +BLACKBOX::RANGE [(_91, num_bits: 64)] [ ] +EXPR [ (-1, _74) (-2⁶⁴, _90) (-1, _91) 18446744073709551617 ] +EXPR [ (-1, _90) (-1, _92) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(3))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(93)), Simple(Witness(94))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_93, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_94, num_bits: 5)] [ ] +EXPR [ (1, _75, _92) (1, _94) (-1, _95) 15 ] +BLACKBOX::RANGE [(_95, num_bits: 5)] [ ] +EXPR [ (2⁴, _93) (1, _94) (-1, _96) 0 ] +EXPR [ (1, _75, _92) (-1, _97) 0 ] +EXPR [ (1, _3, _97) (-1, _96, _97) 0 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(93))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(98)), Simple(Witness(99))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_98, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_99, num_bits: 4)] [ ] +EXPR [ (1, _93) (-2⁴, _98) (-1, _99) 0 ] +BLACKBOX::AND [(_3, num_bits: 8), (_21, num_bits: 8)] [ _100] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(100))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] +outputs: [Simple(Witness(101)), Simple(Witness(102))] +[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] + +BLACKBOX::RANGE [(_101, num_bits: 4)] [ ] +BLACKBOX::RANGE [(_102, num_bits: 4)] [ ] +EXPR [ (1, _100) (-2⁴, _101) (-1, _102) 0 ] +EXPR [ (1, _79, _86) (-1, _103) 0 ] +EXPR [ (-1, _92) (-1, _104) 1 ] +EXPR [ (1, _79, _89) (-1, _105) 0 ] +EXPR [ (1, _67, _68) (1, _68, _69) (-1, _106) 0 ] +EXPR [ (1, _92, _103) (1, _103, _104) (-1, _107) 0 ] +EXPR [ (1, _67, _70) (1, _69, _70) (-1, _108) 0 ] +EXPR [ (1, _92, _105) (1, _104, _105) (-1, _109) 0 ] +EXPR [ (1, _67, _71) (1, _69, _71) (-1, _110) 0 ] +EXPR [ (1, _92, _99) (-1, _111) 0 ] +EXPR [ (1, _67, _72) (1, _69, _72) (-1, _112) 0 ] +EXPR [ (1, _92, _102) (-1, _113) 0 ] +EXPR [ (1, _67, _73) (1, _69, _73) (-1, _114) 0 ] +EXPR [ (2, _6) (1, _20) -7 ] +EXPR [ (-1, _20, _106) (-1, _75, _107) (-1, _115) 15 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(115))], q_c: 0 })] +outputs: [Simple(Witness(116))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _115, _116) (1, _117) -1 ] +EXPR [ (1, _115, _117) 0 ] +EXPR [ (-1, _20, _108) (-1, _75, _109) (-1, _118) 1 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(118))], q_c: 0 })] +outputs: [Simple(Witness(119))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _118, _119) (1, _120) -1 ] +EXPR [ (1, _118, _120) 0 ] +EXPR [ (-1, _20, _110) (-1, _75, _111) (-1, _121) 12 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(121))], q_c: 0 })] +outputs: [Simple(Witness(122))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _121, _122) (1, _123) -1 ] +EXPR [ (1, _121, _123) 0 ] +EXPR [ (1, _117, _120) (-1, _124) 0 ] +EXPR [ (-1, _20, _112) (-1, _75, _113) (-1, _125) 11 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(125))], q_c: 0 })] +outputs: [Simple(Witness(126))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _125, _126) (1, _127) -1 ] +EXPR [ (1, _125, _127) 0 ] +EXPR [ (1, _123, _124) (-1, _128) 0 ] +EXPR [ (-1, _20, _114) (-1, _129) 8 ] +BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(129))], q_c: 0 })] +outputs: [Simple(Witness(130))] +[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] + +EXPR [ (1, _129, _130) (1, _131) -1 ] +EXPR [ (1, _129, _131) 0 ] +EXPR [ (1, _127, _128) (-1, _132) 0 ] +EXPR [ (1, _131, _132) -1 ] + diff --git a/tooling/debugger/Cargo.toml b/tooling/debugger/Cargo.toml index 4d37f801d78..4d240c61f90 100644 --- a/tooling/debugger/Cargo.toml +++ b/tooling/debugger/Cargo.toml @@ -7,7 +7,6 @@ edition.workspace = true license.workspace = true [build-dependencies] -rustc_version = "0.4.0" build-data.workspace = true [dependencies] diff --git a/tooling/debugger/build.rs b/tooling/debugger/build.rs index 5d14ec2bae2..cedeebcae86 100644 --- a/tooling/debugger/build.rs +++ b/tooling/debugger/build.rs @@ -1,24 +1,14 @@ -use rustc_version::{version, Version}; use std::fs::File; use std::io::Write; use std::path::{Path, PathBuf}; use std::{env, fs}; -fn check_rustc_version() { - assert!( - version().unwrap() >= Version::parse("1.71.1").unwrap(), - "The minimal supported rustc version is 1.71.1." - ); -} - const GIT_COMMIT: &&str = &"GIT_COMMIT"; fn main() { // Rebuild if the tests have changed println!("cargo:rerun-if-changed=tests"); - check_rustc_version(); - // Only use build_data if the environment variable isn't set // The environment variable is always set when working via Nix if std::env::var(GIT_COMMIT).is_err() { diff --git a/tooling/debugger/tests/debug.rs b/tooling/debugger/tests/debug.rs index b2f441f5606..e8b17b8a7af 100644 --- a/tooling/debugger/tests/debug.rs +++ b/tooling/debugger/tests/debug.rs @@ -28,7 +28,7 @@ mod tests { dbg_session .execute( &format!("{} debug --program-dir {}", nargo_bin, test_program_dir), - &format!(".*\\Starting debugger.*"), + ".*\\Starting debugger.*", ) .expect("Could not start debugger"); @@ -49,7 +49,7 @@ mod tests { // having successfully solved the circuit witness. dbg_session.send_line("quit").expect("Failed to quit debugger"); dbg_session - .exp_regex(&format!(".*Circuit witness successfully solved.*")) + .exp_regex(".*Circuit witness successfully solved.*") .expect("Expected circuit witness to be successfully solved."); } } From c16f9a6b28c1275579a78e5a3e0a1eddf4c92fd2 Mon Sep 17 00:00:00 2001 From: Tom French Date: Fri, 5 Jan 2024 14:06:07 +0000 Subject: [PATCH 2/2] chore: delete extra files --- .../execution_success/regression/new | 5103 ---------------- .../execution_success/regression/new-acir | 202 - .../execution_success/regression/old | 5180 ----------------- .../execution_success/regression/old-acir | 288 - 4 files changed, 10773 deletions(-) delete mode 100644 test_programs/execution_success/regression/new delete mode 100644 test_programs/execution_success/regression/new-acir delete mode 100644 test_programs/execution_success/regression/old delete mode 100644 test_programs/execution_success/regression/old-acir diff --git a/test_programs/execution_success/regression/new b/test_programs/execution_success/regression/new deleted file mode 100644 index f41afd662c6..00000000000 --- a/test_programs/execution_success/regression/new +++ /dev/null @@ -1,5103 +0,0 @@ -Initial SSA: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - v3, v4 = call f1(v0, v1) - inc_rc v3 - inc_rc v3 - v6 = eq v4, Field 5 - constrain v4 == Field 5 - v10 = array_get v3, index Field 0 - v11 = array_get v3, index Field 1 - v13 = array_get v3, index Field 2 - v15 = array_get v3, index Field 3 - v17 = array_get v3, index Field 4 - v25 = allocate - store u1 1 at v25 - jmp b1(Field 0) - b1(v26: Field): - v27 = lt v26, Field 5 - jmpif v27 then: b2, else: b3 - b2(): - v28 = array_get [v10, v11, v13, v15, v17], index v26 - v29 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v26 - v30 = eq v28, v29 - v31 = load v25 - v32 = mul v31, v30 - store v32 at v25 - v33 = add v26, Field 1 - jmp b1(v33) - b3(): - v34 = load v25 - constrain v34 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v57, v58 = call f2([u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], Field 20) - inc_rc v57 - v61 = allocate - store u1 1 at v61 - jmp b4(Field 0) - b4(v62: Field): - v64 = lt v62, Field 2⁵ - jmpif v64 then: b5, else: b6 - b5(): - v65 = array_get v57, index v62 - v66 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v62 - v67 = eq v65, v66 - v68 = load v61 - v69 = mul v68, v67 - store v69 at v61 - v70 = add v62, Field 1 - jmp b4(v70) - b6(): - v71 = load v61 - constrain v71 == u1 1 - v73 = eq v58, Field 21 - constrain v58 == Field 21 - v75 = call f3() - v77 = eq v75, u64 1 - constrain v75 == u64 1 - v79 = call f4() - v81 = eq v79, u64 2⁴ - constrain v79 == u64 2⁴ - v84 = call f5(u64 0) - v85 = eq v84, u64 1 - constrain v84 == u64 1 - v88 = call f5(u64 4) - v89 = eq v88, u64 2⁴ - constrain v88 == u64 2⁴ - return -} -acir fn compact_decode f1 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - v11 = truncate v1 to 64 bits, max_bit_size: 254 - v12 = cast v11 as u64 - inc_rc v0 - v13 = lt u64 5, v12 - v14 = not v13 - constrain v13 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v18 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v18 - v20 = array_get v0, index Field 0 - v31 = div v20, Field 2⁴ - v32 = cast v20 as u4 - v33 = truncate v32 to 1 bits, max_bit_size: 4 - v34 = cast v33 as u1 - jmpif v34 then: b1, else: b2 - b1(): - v35 = load v18 - v36 = array_get v0, index Field 0 - v38 = and v36, u8 15 - v39 = truncate v38 to 4 bits, max_bit_size: 8 - v40 = cast v39 as u4 - v41 = array_set v35, index Field 0, value v40 - store v41 at v18 - inc_rc v0 - jmp b3(Field 1) - b3(v42: Field): - v43 = lt v42, Field 5 - jmpif v43 then: b4, else: b5 - b4(): - v44 = truncate v42 to 64 bits, max_bit_size: 254 - v45 = cast v44 as u64 - v46 = truncate v1 to 64 bits, max_bit_size: 254 - v47 = cast v46 as u64 - v48 = lt v45, v47 - jmpif v48 then: b6, else: b7 - b6(): - v49 = array_get v0, index v42 - v50 = load v18 - v51 = mul Field 2, v42 - v52 = sub v51, Field 1 - v54 = div v49, Field 2⁴ - v55 = cast v49 as u4 - v56 = array_set v50, index v52, value v55 - v57 = add v52, Field 1 - store v56 at v18 - v58 = load v18 - v59 = mul Field 2, v42 - v60 = and v49, u8 15 - v61 = truncate v60 to 4 bits, max_bit_size: 8 - v62 = cast v61 as u4 - v63 = array_set v58, index v59, value v62 - v64 = add v59, Field 1 - store v63 at v18 - jmp b7() - b7(): - v65 = add v42, Field 1 - jmp b3(v65) - b5(): - jmp b8() - b8(): - v92 = load v18 - v93 = mul Field 2, v1 - v94 = cast v34 as Field - v95 = add v93, v94 - v96 = sub v95, Field 2 - inc_rc v92 - return v92, v96 - b2(): - jmp b9(u64 0) - b9(v66: u64): - v68 = lt v66, u64 2 - jmpif v68 then: b10, else: b11 - b10(): - v69 = truncate v1 to 64 bits, max_bit_size: 254 - v70 = cast v69 as u64 - v72 = sub v70, u64 1 - range_check v72 to 64 bits - v73 = lt v66, v72 - jmpif v73 then: b12, else: b13 - b12(): - v74 = add v66, u64 1 - range_check v74 to 64 bits - v75 = array_get v0, index v74 - v76 = load v18 - v77 = mul u64 2, v66 - range_check v77 to 64 bits - v79 = div v75, Field 2⁴ - v80 = cast v75 as u4 - v81 = array_set v76, index v77, value v80 - v82 = add v77, Field 1 - store v81 at v18 - v83 = load v18 - v84 = mul u64 2, v66 - range_check v84 to 64 bits - v85 = add v84, u64 1 - range_check v85 to 64 bits - v86 = and v75, u8 15 - v87 = truncate v86 to 4 bits, max_bit_size: 8 - v88 = cast v87 as u4 - v89 = array_set v83, index v85, value v88 - v90 = add v85, Field 1 - store v89 at v18 - jmp b13() - b13(): - v91 = add v66, Field 1 - jmp b9(v91) - b11(): - jmp b8() -} -acir fn enc f2 { - b0(v0: [u8; 32], v1: Field): - inc_rc v0 - v5 = truncate v1 to 8 bits, max_bit_size: 254 - v6 = cast v5 as u8 - v7 = lt u8 2⁵, v6 - v8 = not v7 - constrain v7 == u1 0 - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v13 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v13 - v15 = eq v1, Field 0 - jmpif v15 then: b1, else: b2 - b1(): - v16 = load v13 - inc_rc v16 - jmp b3(v16, v1) - b3(v41: [u8; 32], v42: Field): - return v41, v42 - b2(): - v17 = truncate v1 to 8 bits, max_bit_size: 254 - v18 = cast v17 as u8 - v20 = lt v18, u8 31 - jmpif v20 then: b4, else: b5 - b4(): - v21 = load v13 - v23 = truncate v1 to 8 bits, max_bit_size: 254 - v24 = cast v23 as u8 - v25 = add u8 2⁷, v24 - range_check v25 to 8 bits - v27 = array_set v21, index Field 0, value v25 - store v27 at v13 - inc_rc v0 - jmp b6(Field 1) - b6(v28: Field): - v29 = lt v28, Field 2⁵ - jmpif v29 then: b7, else: b8 - b7(): - v30 = load v13 - v31 = sub v28, Field 1 - v32 = array_get v0, index v31 - v33 = array_set v30, index v28, value v32 - v34 = add v28, Field 1 - store v33 at v13 - v35 = add v28, Field 1 - jmp b6(v35) - b8(): - v36 = load v13 - v37 = add v1, Field 1 - inc_rc v36 - jmp b9(v36, v37) - b9(v39: [u8; 32], v40: Field): - jmp b3(v39, v40) - b5(): - v38 = load v13 - inc_rc v38 - jmp b9(v38, Field 2⁵) -} -acir fn bitshift_literal_0 f3 { - b0(): - v1 = allocate - store u64 0 at v1 - v2 = load v1 - v7 = or v2, u64 1 - store v7 at v1 - v8 = load v1 - return v8 -} -acir fn bitshift_literal_4 f4 { - b0(): - v1 = allocate - store u64 0 at v1 - v2 = load v1 - v9 = or v2, u64 2⁴ - store v9 at v1 - v10 = load v1 - return v10 -} -acir fn bitshift_variable f5 { - b0(v0: u64): - v2 = allocate - store u64 0 at v2 - v3 = load v2 - v7 = lt v0, u64 2⁶ - v9 = cast v7 as u64 - v12, v13 = call to_le_bits(v0, Field 2⁶) - v16 = array_get v13, index Field 63 - v17 = mul Field 2, v16 - v18 = sub Field 1, v16 - v19 = add v17, v18 - v20 = mul v19, v19 - v21 = mul v20, Field 2 - v23 = array_get v13, index Field 62 - v24 = mul v21, v23 - v25 = sub Field 1, v23 - v26 = mul v25, v20 - v27 = add v24, v26 - v28 = mul v27, v27 - v29 = mul v28, Field 2 - v31 = array_get v13, index Field 61 - v32 = mul v29, v31 - v33 = sub Field 1, v31 - v34 = mul v33, v28 - v35 = add v32, v34 - v36 = mul v35, v35 - v37 = mul v36, Field 2 - v39 = array_get v13, index Field 60 - v40 = mul v37, v39 - v41 = sub Field 1, v39 - v42 = mul v41, v36 - v43 = add v40, v42 - v44 = mul v43, v43 - v45 = mul v44, Field 2 - v47 = array_get v13, index Field 59 - v48 = mul v45, v47 - v49 = sub Field 1, v47 - v50 = mul v49, v44 - v51 = add v48, v50 - v52 = mul v51, v51 - v53 = mul v52, Field 2 - v55 = array_get v13, index Field 58 - v56 = mul v53, v55 - v57 = sub Field 1, v55 - v58 = mul v57, v52 - v59 = add v56, v58 - v60 = mul v59, v59 - v61 = mul v60, Field 2 - v63 = array_get v13, index Field 57 - v64 = mul v61, v63 - v65 = sub Field 1, v63 - v66 = mul v65, v60 - v67 = add v64, v66 - v68 = mul v67, v67 - v69 = mul v68, Field 2 - v71 = array_get v13, index Field 56 - v72 = mul v69, v71 - v73 = sub Field 1, v71 - v74 = mul v73, v68 - v75 = add v72, v74 - v76 = mul v75, v75 - v77 = mul v76, Field 2 - v79 = array_get v13, index Field 55 - v80 = mul v77, v79 - v81 = sub Field 1, v79 - v82 = mul v81, v76 - v83 = add v80, v82 - v84 = mul v83, v83 - v85 = mul v84, Field 2 - v87 = array_get v13, index Field 54 - v88 = mul v85, v87 - v89 = sub Field 1, v87 - v90 = mul v89, v84 - v91 = add v88, v90 - v92 = mul v91, v91 - v93 = mul v92, Field 2 - v95 = array_get v13, index Field 53 - v96 = mul v93, v95 - v97 = sub Field 1, v95 - v98 = mul v97, v92 - v99 = add v96, v98 - v100 = mul v99, v99 - v101 = mul v100, Field 2 - v103 = array_get v13, index Field 52 - v104 = mul v101, v103 - v105 = sub Field 1, v103 - v106 = mul v105, v100 - v107 = add v104, v106 - v108 = mul v107, v107 - v109 = mul v108, Field 2 - v111 = array_get v13, index Field 51 - v112 = mul v109, v111 - v113 = sub Field 1, v111 - v114 = mul v113, v108 - v115 = add v112, v114 - v116 = mul v115, v115 - v117 = mul v116, Field 2 - v119 = array_get v13, index Field 50 - v120 = mul v117, v119 - v121 = sub Field 1, v119 - v122 = mul v121, v116 - v123 = add v120, v122 - v124 = mul v123, v123 - v125 = mul v124, Field 2 - v127 = array_get v13, index Field 49 - v128 = mul v125, v127 - v129 = sub Field 1, v127 - v130 = mul v129, v124 - v131 = add v128, v130 - v132 = mul v131, v131 - v133 = mul v132, Field 2 - v135 = array_get v13, index Field 2⁴×3 - v136 = mul v133, v135 - v137 = sub Field 1, v135 - v138 = mul v137, v132 - v139 = add v136, v138 - v140 = mul v139, v139 - v141 = mul v140, Field 2 - v143 = array_get v13, index Field 47 - v144 = mul v141, v143 - v145 = sub Field 1, v143 - v146 = mul v145, v140 - v147 = add v144, v146 - v148 = mul v147, v147 - v149 = mul v148, Field 2 - v151 = array_get v13, index Field 46 - v152 = mul v149, v151 - v153 = sub Field 1, v151 - v154 = mul v153, v148 - v155 = add v152, v154 - v156 = mul v155, v155 - v157 = mul v156, Field 2 - v159 = array_get v13, index Field 45 - v160 = mul v157, v159 - v161 = sub Field 1, v159 - v162 = mul v161, v156 - v163 = add v160, v162 - v164 = mul v163, v163 - v165 = mul v164, Field 2 - v167 = array_get v13, index Field 44 - v168 = mul v165, v167 - v169 = sub Field 1, v167 - v170 = mul v169, v164 - v171 = add v168, v170 - v172 = mul v171, v171 - v173 = mul v172, Field 2 - v175 = array_get v13, index Field 43 - v176 = mul v173, v175 - v177 = sub Field 1, v175 - v178 = mul v177, v172 - v179 = add v176, v178 - v180 = mul v179, v179 - v181 = mul v180, Field 2 - v183 = array_get v13, index Field 42 - v184 = mul v181, v183 - v185 = sub Field 1, v183 - v186 = mul v185, v180 - v187 = add v184, v186 - v188 = mul v187, v187 - v189 = mul v188, Field 2 - v191 = array_get v13, index Field 41 - v192 = mul v189, v191 - v193 = sub Field 1, v191 - v194 = mul v193, v188 - v195 = add v192, v194 - v196 = mul v195, v195 - v197 = mul v196, Field 2 - v199 = array_get v13, index Field 40 - v200 = mul v197, v199 - v201 = sub Field 1, v199 - v202 = mul v201, v196 - v203 = add v200, v202 - v204 = mul v203, v203 - v205 = mul v204, Field 2 - v207 = array_get v13, index Field 39 - v208 = mul v205, v207 - v209 = sub Field 1, v207 - v210 = mul v209, v204 - v211 = add v208, v210 - v212 = mul v211, v211 - v213 = mul v212, Field 2 - v215 = array_get v13, index Field 38 - v216 = mul v213, v215 - v217 = sub Field 1, v215 - v218 = mul v217, v212 - v219 = add v216, v218 - v220 = mul v219, v219 - v221 = mul v220, Field 2 - v223 = array_get v13, index Field 37 - v224 = mul v221, v223 - v225 = sub Field 1, v223 - v226 = mul v225, v220 - v227 = add v224, v226 - v228 = mul v227, v227 - v229 = mul v228, Field 2 - v231 = array_get v13, index Field 36 - v232 = mul v229, v231 - v233 = sub Field 1, v231 - v234 = mul v233, v228 - v235 = add v232, v234 - v236 = mul v235, v235 - v237 = mul v236, Field 2 - v239 = array_get v13, index Field 35 - v240 = mul v237, v239 - v241 = sub Field 1, v239 - v242 = mul v241, v236 - v243 = add v240, v242 - v244 = mul v243, v243 - v245 = mul v244, Field 2 - v247 = array_get v13, index Field 34 - v248 = mul v245, v247 - v249 = sub Field 1, v247 - v250 = mul v249, v244 - v251 = add v248, v250 - v252 = mul v251, v251 - v253 = mul v252, Field 2 - v255 = array_get v13, index Field 33 - v256 = mul v253, v255 - v257 = sub Field 1, v255 - v258 = mul v257, v252 - v259 = add v256, v258 - v260 = mul v259, v259 - v261 = mul v260, Field 2 - v263 = array_get v13, index Field 2⁵ - v264 = mul v261, v263 - v265 = sub Field 1, v263 - v266 = mul v265, v260 - v267 = add v264, v266 - v268 = mul v267, v267 - v269 = mul v268, Field 2 - v271 = array_get v13, index Field 31 - v272 = mul v269, v271 - v273 = sub Field 1, v271 - v274 = mul v273, v268 - v275 = add v272, v274 - v276 = mul v275, v275 - v277 = mul v276, Field 2 - v279 = array_get v13, index Field 30 - v280 = mul v277, v279 - v281 = sub Field 1, v279 - v282 = mul v281, v276 - v283 = add v280, v282 - v284 = mul v283, v283 - v285 = mul v284, Field 2 - v287 = array_get v13, index Field 29 - v288 = mul v285, v287 - v289 = sub Field 1, v287 - v290 = mul v289, v284 - v291 = add v288, v290 - v292 = mul v291, v291 - v293 = mul v292, Field 2 - v295 = array_get v13, index Field 28 - v296 = mul v293, v295 - v297 = sub Field 1, v295 - v298 = mul v297, v292 - v299 = add v296, v298 - v300 = mul v299, v299 - v301 = mul v300, Field 2 - v303 = array_get v13, index Field 27 - v304 = mul v301, v303 - v305 = sub Field 1, v303 - v306 = mul v305, v300 - v307 = add v304, v306 - v308 = mul v307, v307 - v309 = mul v308, Field 2 - v311 = array_get v13, index Field 26 - v312 = mul v309, v311 - v313 = sub Field 1, v311 - v314 = mul v313, v308 - v315 = add v312, v314 - v316 = mul v315, v315 - v317 = mul v316, Field 2 - v319 = array_get v13, index Field 25 - v320 = mul v317, v319 - v321 = sub Field 1, v319 - v322 = mul v321, v316 - v323 = add v320, v322 - v324 = mul v323, v323 - v325 = mul v324, Field 2 - v327 = array_get v13, index Field 24 - v328 = mul v325, v327 - v329 = sub Field 1, v327 - v330 = mul v329, v324 - v331 = add v328, v330 - v332 = mul v331, v331 - v333 = mul v332, Field 2 - v335 = array_get v13, index Field 23 - v336 = mul v333, v335 - v337 = sub Field 1, v335 - v338 = mul v337, v332 - v339 = add v336, v338 - v340 = mul v339, v339 - v341 = mul v340, Field 2 - v343 = array_get v13, index Field 22 - v344 = mul v341, v343 - v345 = sub Field 1, v343 - v346 = mul v345, v340 - v347 = add v344, v346 - v348 = mul v347, v347 - v349 = mul v348, Field 2 - v351 = array_get v13, index Field 21 - v352 = mul v349, v351 - v353 = sub Field 1, v351 - v354 = mul v353, v348 - v355 = add v352, v354 - v356 = mul v355, v355 - v357 = mul v356, Field 2 - v359 = array_get v13, index Field 20 - v360 = mul v357, v359 - v361 = sub Field 1, v359 - v362 = mul v361, v356 - v363 = add v360, v362 - v364 = mul v363, v363 - v365 = mul v364, Field 2 - v367 = array_get v13, index Field 19 - v368 = mul v365, v367 - v369 = sub Field 1, v367 - v370 = mul v369, v364 - v371 = add v368, v370 - v372 = mul v371, v371 - v373 = mul v372, Field 2 - v375 = array_get v13, index Field 18 - v376 = mul v373, v375 - v377 = sub Field 1, v375 - v378 = mul v377, v372 - v379 = add v376, v378 - v380 = mul v379, v379 - v381 = mul v380, Field 2 - v383 = array_get v13, index Field 17 - v384 = mul v381, v383 - v385 = sub Field 1, v383 - v386 = mul v385, v380 - v387 = add v384, v386 - v388 = mul v387, v387 - v389 = mul v388, Field 2 - v391 = array_get v13, index Field 2⁴ - v392 = mul v389, v391 - v393 = sub Field 1, v391 - v394 = mul v393, v388 - v395 = add v392, v394 - v396 = mul v395, v395 - v397 = mul v396, Field 2 - v399 = array_get v13, index Field 15 - v400 = mul v397, v399 - v401 = sub Field 1, v399 - v402 = mul v401, v396 - v403 = add v400, v402 - v404 = mul v403, v403 - v405 = mul v404, Field 2 - v407 = array_get v13, index Field 14 - v408 = mul v405, v407 - v409 = sub Field 1, v407 - v410 = mul v409, v404 - v411 = add v408, v410 - v412 = mul v411, v411 - v413 = mul v412, Field 2 - v415 = array_get v13, index Field 13 - v416 = mul v413, v415 - v417 = sub Field 1, v415 - v418 = mul v417, v412 - v419 = add v416, v418 - v420 = mul v419, v419 - v421 = mul v420, Field 2 - v423 = array_get v13, index Field 12 - v424 = mul v421, v423 - v425 = sub Field 1, v423 - v426 = mul v425, v420 - v427 = add v424, v426 - v428 = mul v427, v427 - v429 = mul v428, Field 2 - v431 = array_get v13, index Field 11 - v432 = mul v429, v431 - v433 = sub Field 1, v431 - v434 = mul v433, v428 - v435 = add v432, v434 - v436 = mul v435, v435 - v437 = mul v436, Field 2 - v439 = array_get v13, index Field 10 - v440 = mul v437, v439 - v441 = sub Field 1, v439 - v442 = mul v441, v436 - v443 = add v440, v442 - v444 = mul v443, v443 - v445 = mul v444, Field 2 - v447 = array_get v13, index Field 9 - v448 = mul v445, v447 - v449 = sub Field 1, v447 - v450 = mul v449, v444 - v451 = add v448, v450 - v452 = mul v451, v451 - v453 = mul v452, Field 2 - v455 = array_get v13, index Field 8 - v456 = mul v453, v455 - v457 = sub Field 1, v455 - v458 = mul v457, v452 - v459 = add v456, v458 - v460 = mul v459, v459 - v461 = mul v460, Field 2 - v463 = array_get v13, index Field 7 - v464 = mul v461, v463 - v465 = sub Field 1, v463 - v466 = mul v465, v460 - v467 = add v464, v466 - v468 = mul v467, v467 - v469 = mul v468, Field 2 - v471 = array_get v13, index Field 6 - v472 = mul v469, v471 - v473 = sub Field 1, v471 - v474 = mul v473, v468 - v475 = add v472, v474 - v476 = mul v475, v475 - v477 = mul v476, Field 2 - v479 = array_get v13, index Field 5 - v480 = mul v477, v479 - v481 = sub Field 1, v479 - v482 = mul v481, v476 - v483 = add v480, v482 - v484 = mul v483, v483 - v485 = mul v484, Field 2 - v487 = array_get v13, index Field 4 - v488 = mul v485, v487 - v489 = sub Field 1, v487 - v490 = mul v489, v484 - v491 = add v488, v490 - v492 = mul v491, v491 - v493 = mul v492, Field 2 - v495 = array_get v13, index Field 3 - v496 = mul v493, v495 - v497 = sub Field 1, v495 - v498 = mul v497, v492 - v499 = add v496, v498 - v500 = mul v499, v499 - v501 = mul v500, Field 2 - v502 = array_get v13, index Field 2 - v503 = mul v501, v502 - v504 = sub Field 1, v502 - v505 = mul v504, v500 - v506 = add v503, v505 - v507 = mul v506, v506 - v508 = mul v507, Field 2 - v509 = array_get v13, index Field 1 - v510 = mul v508, v509 - v511 = sub Field 1, v509 - v512 = mul v511, v507 - v513 = add v510, v512 - v514 = mul v513, v513 - v515 = mul v514, Field 2 - v517 = array_get v13, index Field 0 - v518 = mul v515, v517 - v519 = sub Field 1, v517 - v520 = mul v519, v514 - v521 = add v518, v520 - v522 = truncate v521 to 64 bits, max_bit_size: 254 - v523 = cast v522 as u64 - v524 = mul v9, v523 - v525 = truncate v524 to 64 bits, max_bit_size: 254 - v526 = lt v0, u64 2⁶ - constrain v526 == u1 1 'attempt to bit-shift with overflow' - v527 = or v3, v525 - store v527 at v2 - v528 = load v2 - return v528 -} - -After Defunctionalization: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - v3, v4 = call f1(v0, v1) - inc_rc v3 - inc_rc v3 - v6 = eq v4, Field 5 - constrain v4 == Field 5 - v10 = array_get v3, index Field 0 - v11 = array_get v3, index Field 1 - v13 = array_get v3, index Field 2 - v15 = array_get v3, index Field 3 - v17 = array_get v3, index Field 4 - v25 = allocate - store u1 1 at v25 - jmp b1(Field 0) - b1(v26: Field): - v27 = lt v26, Field 5 - jmpif v27 then: b2, else: b3 - b2(): - v28 = array_get [v10, v11, v13, v15, v17], index v26 - v29 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v26 - v30 = eq v28, v29 - v31 = load v25 - v32 = mul v31, v30 - store v32 at v25 - v33 = add v26, Field 1 - jmp b1(v33) - b3(): - v34 = load v25 - constrain v34 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v57, v58 = call f2([u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], Field 20) - inc_rc v57 - v61 = allocate - store u1 1 at v61 - jmp b4(Field 0) - b4(v62: Field): - v64 = lt v62, Field 2⁵ - jmpif v64 then: b5, else: b6 - b5(): - v65 = array_get v57, index v62 - v66 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v62 - v67 = eq v65, v66 - v68 = load v61 - v69 = mul v68, v67 - store v69 at v61 - v70 = add v62, Field 1 - jmp b4(v70) - b6(): - v71 = load v61 - constrain v71 == u1 1 - v73 = eq v58, Field 21 - constrain v58 == Field 21 - v75 = call f3() - v77 = eq v75, u64 1 - constrain v75 == u64 1 - v79 = call f4() - v81 = eq v79, u64 2⁴ - constrain v79 == u64 2⁴ - v84 = call f5(u64 0) - v85 = eq v84, u64 1 - constrain v84 == u64 1 - v88 = call f5(u64 4) - v89 = eq v88, u64 2⁴ - constrain v88 == u64 2⁴ - return -} -acir fn compact_decode f1 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - v11 = truncate v1 to 64 bits, max_bit_size: 254 - v12 = cast v11 as u64 - inc_rc v0 - v13 = lt u64 5, v12 - v14 = not v13 - constrain v13 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v18 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v18 - v20 = array_get v0, index Field 0 - v31 = div v20, Field 2⁴ - v32 = cast v20 as u4 - v33 = truncate v32 to 1 bits, max_bit_size: 4 - v34 = cast v33 as u1 - jmpif v34 then: b1, else: b2 - b1(): - v35 = load v18 - v36 = array_get v0, index Field 0 - v38 = and v36, u8 15 - v39 = truncate v38 to 4 bits, max_bit_size: 8 - v40 = cast v39 as u4 - v41 = array_set v35, index Field 0, value v40 - store v41 at v18 - inc_rc v0 - jmp b3(Field 1) - b3(v42: Field): - v43 = lt v42, Field 5 - jmpif v43 then: b4, else: b5 - b4(): - v44 = truncate v42 to 64 bits, max_bit_size: 254 - v45 = cast v44 as u64 - v46 = truncate v1 to 64 bits, max_bit_size: 254 - v47 = cast v46 as u64 - v48 = lt v45, v47 - jmpif v48 then: b6, else: b7 - b6(): - v49 = array_get v0, index v42 - v50 = load v18 - v51 = mul Field 2, v42 - v52 = sub v51, Field 1 - v54 = div v49, Field 2⁴ - v55 = cast v49 as u4 - v56 = array_set v50, index v52, value v55 - v57 = add v52, Field 1 - store v56 at v18 - v58 = load v18 - v59 = mul Field 2, v42 - v60 = and v49, u8 15 - v61 = truncate v60 to 4 bits, max_bit_size: 8 - v62 = cast v61 as u4 - v63 = array_set v58, index v59, value v62 - v64 = add v59, Field 1 - store v63 at v18 - jmp b7() - b7(): - v65 = add v42, Field 1 - jmp b3(v65) - b5(): - jmp b8() - b8(): - v92 = load v18 - v93 = mul Field 2, v1 - v94 = cast v34 as Field - v95 = add v93, v94 - v96 = sub v95, Field 2 - inc_rc v92 - return v92, v96 - b2(): - jmp b9(u64 0) - b9(v66: u64): - v68 = lt v66, u64 2 - jmpif v68 then: b10, else: b11 - b10(): - v69 = truncate v1 to 64 bits, max_bit_size: 254 - v70 = cast v69 as u64 - v72 = sub v70, u64 1 - range_check v72 to 64 bits - v73 = lt v66, v72 - jmpif v73 then: b12, else: b13 - b12(): - v74 = add v66, u64 1 - range_check v74 to 64 bits - v75 = array_get v0, index v74 - v76 = load v18 - v77 = mul u64 2, v66 - range_check v77 to 64 bits - v79 = div v75, Field 2⁴ - v80 = cast v75 as u4 - v81 = array_set v76, index v77, value v80 - v82 = add v77, Field 1 - store v81 at v18 - v83 = load v18 - v84 = mul u64 2, v66 - range_check v84 to 64 bits - v85 = add v84, u64 1 - range_check v85 to 64 bits - v86 = and v75, u8 15 - v87 = truncate v86 to 4 bits, max_bit_size: 8 - v88 = cast v87 as u4 - v89 = array_set v83, index v85, value v88 - v90 = add v85, Field 1 - store v89 at v18 - jmp b13() - b13(): - v91 = add v66, Field 1 - jmp b9(v91) - b11(): - jmp b8() -} -acir fn enc f2 { - b0(v0: [u8; 32], v1: Field): - inc_rc v0 - v5 = truncate v1 to 8 bits, max_bit_size: 254 - v6 = cast v5 as u8 - v7 = lt u8 2⁵, v6 - v8 = not v7 - constrain v7 == u1 0 - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v13 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v13 - v15 = eq v1, Field 0 - jmpif v15 then: b1, else: b2 - b1(): - v16 = load v13 - inc_rc v16 - jmp b3(v16, v1) - b3(v41: [u8; 32], v42: Field): - return v41, v42 - b2(): - v17 = truncate v1 to 8 bits, max_bit_size: 254 - v18 = cast v17 as u8 - v20 = lt v18, u8 31 - jmpif v20 then: b4, else: b5 - b4(): - v21 = load v13 - v23 = truncate v1 to 8 bits, max_bit_size: 254 - v24 = cast v23 as u8 - v25 = add u8 2⁷, v24 - range_check v25 to 8 bits - v27 = array_set v21, index Field 0, value v25 - store v27 at v13 - inc_rc v0 - jmp b6(Field 1) - b6(v28: Field): - v29 = lt v28, Field 2⁵ - jmpif v29 then: b7, else: b8 - b7(): - v30 = load v13 - v31 = sub v28, Field 1 - v32 = array_get v0, index v31 - v33 = array_set v30, index v28, value v32 - v34 = add v28, Field 1 - store v33 at v13 - v35 = add v28, Field 1 - jmp b6(v35) - b8(): - v36 = load v13 - v37 = add v1, Field 1 - inc_rc v36 - jmp b9(v36, v37) - b9(v39: [u8; 32], v40: Field): - jmp b3(v39, v40) - b5(): - v38 = load v13 - inc_rc v38 - jmp b9(v38, Field 2⁵) -} -acir fn bitshift_literal_0 f3 { - b0(): - v1 = allocate - store u64 0 at v1 - v2 = load v1 - v7 = or v2, u64 1 - store v7 at v1 - v8 = load v1 - return v8 -} -acir fn bitshift_literal_4 f4 { - b0(): - v1 = allocate - store u64 0 at v1 - v2 = load v1 - v9 = or v2, u64 2⁴ - store v9 at v1 - v10 = load v1 - return v10 -} -acir fn bitshift_variable f5 { - b0(v0: u64): - v2 = allocate - store u64 0 at v2 - v3 = load v2 - v7 = lt v0, u64 2⁶ - v9 = cast v7 as u64 - v12, v13 = call to_le_bits(v0, Field 2⁶) - v16 = array_get v13, index Field 63 - v17 = mul Field 2, v16 - v18 = sub Field 1, v16 - v19 = add v17, v18 - v20 = mul v19, v19 - v21 = mul v20, Field 2 - v23 = array_get v13, index Field 62 - v24 = mul v21, v23 - v25 = sub Field 1, v23 - v26 = mul v25, v20 - v27 = add v24, v26 - v28 = mul v27, v27 - v29 = mul v28, Field 2 - v31 = array_get v13, index Field 61 - v32 = mul v29, v31 - v33 = sub Field 1, v31 - v34 = mul v33, v28 - v35 = add v32, v34 - v36 = mul v35, v35 - v37 = mul v36, Field 2 - v39 = array_get v13, index Field 60 - v40 = mul v37, v39 - v41 = sub Field 1, v39 - v42 = mul v41, v36 - v43 = add v40, v42 - v44 = mul v43, v43 - v45 = mul v44, Field 2 - v47 = array_get v13, index Field 59 - v48 = mul v45, v47 - v49 = sub Field 1, v47 - v50 = mul v49, v44 - v51 = add v48, v50 - v52 = mul v51, v51 - v53 = mul v52, Field 2 - v55 = array_get v13, index Field 58 - v56 = mul v53, v55 - v57 = sub Field 1, v55 - v58 = mul v57, v52 - v59 = add v56, v58 - v60 = mul v59, v59 - v61 = mul v60, Field 2 - v63 = array_get v13, index Field 57 - v64 = mul v61, v63 - v65 = sub Field 1, v63 - v66 = mul v65, v60 - v67 = add v64, v66 - v68 = mul v67, v67 - v69 = mul v68, Field 2 - v71 = array_get v13, index Field 56 - v72 = mul v69, v71 - v73 = sub Field 1, v71 - v74 = mul v73, v68 - v75 = add v72, v74 - v76 = mul v75, v75 - v77 = mul v76, Field 2 - v79 = array_get v13, index Field 55 - v80 = mul v77, v79 - v81 = sub Field 1, v79 - v82 = mul v81, v76 - v83 = add v80, v82 - v84 = mul v83, v83 - v85 = mul v84, Field 2 - v87 = array_get v13, index Field 54 - v88 = mul v85, v87 - v89 = sub Field 1, v87 - v90 = mul v89, v84 - v91 = add v88, v90 - v92 = mul v91, v91 - v93 = mul v92, Field 2 - v95 = array_get v13, index Field 53 - v96 = mul v93, v95 - v97 = sub Field 1, v95 - v98 = mul v97, v92 - v99 = add v96, v98 - v100 = mul v99, v99 - v101 = mul v100, Field 2 - v103 = array_get v13, index Field 52 - v104 = mul v101, v103 - v105 = sub Field 1, v103 - v106 = mul v105, v100 - v107 = add v104, v106 - v108 = mul v107, v107 - v109 = mul v108, Field 2 - v111 = array_get v13, index Field 51 - v112 = mul v109, v111 - v113 = sub Field 1, v111 - v114 = mul v113, v108 - v115 = add v112, v114 - v116 = mul v115, v115 - v117 = mul v116, Field 2 - v119 = array_get v13, index Field 50 - v120 = mul v117, v119 - v121 = sub Field 1, v119 - v122 = mul v121, v116 - v123 = add v120, v122 - v124 = mul v123, v123 - v125 = mul v124, Field 2 - v127 = array_get v13, index Field 49 - v128 = mul v125, v127 - v129 = sub Field 1, v127 - v130 = mul v129, v124 - v131 = add v128, v130 - v132 = mul v131, v131 - v133 = mul v132, Field 2 - v135 = array_get v13, index Field 2⁴×3 - v136 = mul v133, v135 - v137 = sub Field 1, v135 - v138 = mul v137, v132 - v139 = add v136, v138 - v140 = mul v139, v139 - v141 = mul v140, Field 2 - v143 = array_get v13, index Field 47 - v144 = mul v141, v143 - v145 = sub Field 1, v143 - v146 = mul v145, v140 - v147 = add v144, v146 - v148 = mul v147, v147 - v149 = mul v148, Field 2 - v151 = array_get v13, index Field 46 - v152 = mul v149, v151 - v153 = sub Field 1, v151 - v154 = mul v153, v148 - v155 = add v152, v154 - v156 = mul v155, v155 - v157 = mul v156, Field 2 - v159 = array_get v13, index Field 45 - v160 = mul v157, v159 - v161 = sub Field 1, v159 - v162 = mul v161, v156 - v163 = add v160, v162 - v164 = mul v163, v163 - v165 = mul v164, Field 2 - v167 = array_get v13, index Field 44 - v168 = mul v165, v167 - v169 = sub Field 1, v167 - v170 = mul v169, v164 - v171 = add v168, v170 - v172 = mul v171, v171 - v173 = mul v172, Field 2 - v175 = array_get v13, index Field 43 - v176 = mul v173, v175 - v177 = sub Field 1, v175 - v178 = mul v177, v172 - v179 = add v176, v178 - v180 = mul v179, v179 - v181 = mul v180, Field 2 - v183 = array_get v13, index Field 42 - v184 = mul v181, v183 - v185 = sub Field 1, v183 - v186 = mul v185, v180 - v187 = add v184, v186 - v188 = mul v187, v187 - v189 = mul v188, Field 2 - v191 = array_get v13, index Field 41 - v192 = mul v189, v191 - v193 = sub Field 1, v191 - v194 = mul v193, v188 - v195 = add v192, v194 - v196 = mul v195, v195 - v197 = mul v196, Field 2 - v199 = array_get v13, index Field 40 - v200 = mul v197, v199 - v201 = sub Field 1, v199 - v202 = mul v201, v196 - v203 = add v200, v202 - v204 = mul v203, v203 - v205 = mul v204, Field 2 - v207 = array_get v13, index Field 39 - v208 = mul v205, v207 - v209 = sub Field 1, v207 - v210 = mul v209, v204 - v211 = add v208, v210 - v212 = mul v211, v211 - v213 = mul v212, Field 2 - v215 = array_get v13, index Field 38 - v216 = mul v213, v215 - v217 = sub Field 1, v215 - v218 = mul v217, v212 - v219 = add v216, v218 - v220 = mul v219, v219 - v221 = mul v220, Field 2 - v223 = array_get v13, index Field 37 - v224 = mul v221, v223 - v225 = sub Field 1, v223 - v226 = mul v225, v220 - v227 = add v224, v226 - v228 = mul v227, v227 - v229 = mul v228, Field 2 - v231 = array_get v13, index Field 36 - v232 = mul v229, v231 - v233 = sub Field 1, v231 - v234 = mul v233, v228 - v235 = add v232, v234 - v236 = mul v235, v235 - v237 = mul v236, Field 2 - v239 = array_get v13, index Field 35 - v240 = mul v237, v239 - v241 = sub Field 1, v239 - v242 = mul v241, v236 - v243 = add v240, v242 - v244 = mul v243, v243 - v245 = mul v244, Field 2 - v247 = array_get v13, index Field 34 - v248 = mul v245, v247 - v249 = sub Field 1, v247 - v250 = mul v249, v244 - v251 = add v248, v250 - v252 = mul v251, v251 - v253 = mul v252, Field 2 - v255 = array_get v13, index Field 33 - v256 = mul v253, v255 - v257 = sub Field 1, v255 - v258 = mul v257, v252 - v259 = add v256, v258 - v260 = mul v259, v259 - v261 = mul v260, Field 2 - v263 = array_get v13, index Field 2⁵ - v264 = mul v261, v263 - v265 = sub Field 1, v263 - v266 = mul v265, v260 - v267 = add v264, v266 - v268 = mul v267, v267 - v269 = mul v268, Field 2 - v271 = array_get v13, index Field 31 - v272 = mul v269, v271 - v273 = sub Field 1, v271 - v274 = mul v273, v268 - v275 = add v272, v274 - v276 = mul v275, v275 - v277 = mul v276, Field 2 - v279 = array_get v13, index Field 30 - v280 = mul v277, v279 - v281 = sub Field 1, v279 - v282 = mul v281, v276 - v283 = add v280, v282 - v284 = mul v283, v283 - v285 = mul v284, Field 2 - v287 = array_get v13, index Field 29 - v288 = mul v285, v287 - v289 = sub Field 1, v287 - v290 = mul v289, v284 - v291 = add v288, v290 - v292 = mul v291, v291 - v293 = mul v292, Field 2 - v295 = array_get v13, index Field 28 - v296 = mul v293, v295 - v297 = sub Field 1, v295 - v298 = mul v297, v292 - v299 = add v296, v298 - v300 = mul v299, v299 - v301 = mul v300, Field 2 - v303 = array_get v13, index Field 27 - v304 = mul v301, v303 - v305 = sub Field 1, v303 - v306 = mul v305, v300 - v307 = add v304, v306 - v308 = mul v307, v307 - v309 = mul v308, Field 2 - v311 = array_get v13, index Field 26 - v312 = mul v309, v311 - v313 = sub Field 1, v311 - v314 = mul v313, v308 - v315 = add v312, v314 - v316 = mul v315, v315 - v317 = mul v316, Field 2 - v319 = array_get v13, index Field 25 - v320 = mul v317, v319 - v321 = sub Field 1, v319 - v322 = mul v321, v316 - v323 = add v320, v322 - v324 = mul v323, v323 - v325 = mul v324, Field 2 - v327 = array_get v13, index Field 24 - v328 = mul v325, v327 - v329 = sub Field 1, v327 - v330 = mul v329, v324 - v331 = add v328, v330 - v332 = mul v331, v331 - v333 = mul v332, Field 2 - v335 = array_get v13, index Field 23 - v336 = mul v333, v335 - v337 = sub Field 1, v335 - v338 = mul v337, v332 - v339 = add v336, v338 - v340 = mul v339, v339 - v341 = mul v340, Field 2 - v343 = array_get v13, index Field 22 - v344 = mul v341, v343 - v345 = sub Field 1, v343 - v346 = mul v345, v340 - v347 = add v344, v346 - v348 = mul v347, v347 - v349 = mul v348, Field 2 - v351 = array_get v13, index Field 21 - v352 = mul v349, v351 - v353 = sub Field 1, v351 - v354 = mul v353, v348 - v355 = add v352, v354 - v356 = mul v355, v355 - v357 = mul v356, Field 2 - v359 = array_get v13, index Field 20 - v360 = mul v357, v359 - v361 = sub Field 1, v359 - v362 = mul v361, v356 - v363 = add v360, v362 - v364 = mul v363, v363 - v365 = mul v364, Field 2 - v367 = array_get v13, index Field 19 - v368 = mul v365, v367 - v369 = sub Field 1, v367 - v370 = mul v369, v364 - v371 = add v368, v370 - v372 = mul v371, v371 - v373 = mul v372, Field 2 - v375 = array_get v13, index Field 18 - v376 = mul v373, v375 - v377 = sub Field 1, v375 - v378 = mul v377, v372 - v379 = add v376, v378 - v380 = mul v379, v379 - v381 = mul v380, Field 2 - v383 = array_get v13, index Field 17 - v384 = mul v381, v383 - v385 = sub Field 1, v383 - v386 = mul v385, v380 - v387 = add v384, v386 - v388 = mul v387, v387 - v389 = mul v388, Field 2 - v391 = array_get v13, index Field 2⁴ - v392 = mul v389, v391 - v393 = sub Field 1, v391 - v394 = mul v393, v388 - v395 = add v392, v394 - v396 = mul v395, v395 - v397 = mul v396, Field 2 - v399 = array_get v13, index Field 15 - v400 = mul v397, v399 - v401 = sub Field 1, v399 - v402 = mul v401, v396 - v403 = add v400, v402 - v404 = mul v403, v403 - v405 = mul v404, Field 2 - v407 = array_get v13, index Field 14 - v408 = mul v405, v407 - v409 = sub Field 1, v407 - v410 = mul v409, v404 - v411 = add v408, v410 - v412 = mul v411, v411 - v413 = mul v412, Field 2 - v415 = array_get v13, index Field 13 - v416 = mul v413, v415 - v417 = sub Field 1, v415 - v418 = mul v417, v412 - v419 = add v416, v418 - v420 = mul v419, v419 - v421 = mul v420, Field 2 - v423 = array_get v13, index Field 12 - v424 = mul v421, v423 - v425 = sub Field 1, v423 - v426 = mul v425, v420 - v427 = add v424, v426 - v428 = mul v427, v427 - v429 = mul v428, Field 2 - v431 = array_get v13, index Field 11 - v432 = mul v429, v431 - v433 = sub Field 1, v431 - v434 = mul v433, v428 - v435 = add v432, v434 - v436 = mul v435, v435 - v437 = mul v436, Field 2 - v439 = array_get v13, index Field 10 - v440 = mul v437, v439 - v441 = sub Field 1, v439 - v442 = mul v441, v436 - v443 = add v440, v442 - v444 = mul v443, v443 - v445 = mul v444, Field 2 - v447 = array_get v13, index Field 9 - v448 = mul v445, v447 - v449 = sub Field 1, v447 - v450 = mul v449, v444 - v451 = add v448, v450 - v452 = mul v451, v451 - v453 = mul v452, Field 2 - v455 = array_get v13, index Field 8 - v456 = mul v453, v455 - v457 = sub Field 1, v455 - v458 = mul v457, v452 - v459 = add v456, v458 - v460 = mul v459, v459 - v461 = mul v460, Field 2 - v463 = array_get v13, index Field 7 - v464 = mul v461, v463 - v465 = sub Field 1, v463 - v466 = mul v465, v460 - v467 = add v464, v466 - v468 = mul v467, v467 - v469 = mul v468, Field 2 - v471 = array_get v13, index Field 6 - v472 = mul v469, v471 - v473 = sub Field 1, v471 - v474 = mul v473, v468 - v475 = add v472, v474 - v476 = mul v475, v475 - v477 = mul v476, Field 2 - v479 = array_get v13, index Field 5 - v480 = mul v477, v479 - v481 = sub Field 1, v479 - v482 = mul v481, v476 - v483 = add v480, v482 - v484 = mul v483, v483 - v485 = mul v484, Field 2 - v487 = array_get v13, index Field 4 - v488 = mul v485, v487 - v489 = sub Field 1, v487 - v490 = mul v489, v484 - v491 = add v488, v490 - v492 = mul v491, v491 - v493 = mul v492, Field 2 - v495 = array_get v13, index Field 3 - v496 = mul v493, v495 - v497 = sub Field 1, v495 - v498 = mul v497, v492 - v499 = add v496, v498 - v500 = mul v499, v499 - v501 = mul v500, Field 2 - v502 = array_get v13, index Field 2 - v503 = mul v501, v502 - v504 = sub Field 1, v502 - v505 = mul v504, v500 - v506 = add v503, v505 - v507 = mul v506, v506 - v508 = mul v507, Field 2 - v509 = array_get v13, index Field 1 - v510 = mul v508, v509 - v511 = sub Field 1, v509 - v512 = mul v511, v507 - v513 = add v510, v512 - v514 = mul v513, v513 - v515 = mul v514, Field 2 - v517 = array_get v13, index Field 0 - v518 = mul v515, v517 - v519 = sub Field 1, v517 - v520 = mul v519, v514 - v521 = add v518, v520 - v522 = truncate v521 to 64 bits, max_bit_size: 254 - v523 = cast v522 as u64 - v524 = mul v9, v523 - v525 = truncate v524 to 64 bits, max_bit_size: 254 - v526 = lt v0, u64 2⁶ - constrain v526 == u1 1 'attempt to bit-shift with overflow' - v527 = or v3, v525 - store v527 at v2 - v528 = load v2 - return v528 -} - -After Inlining: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v3 = truncate v1 to 64 bits, max_bit_size: 254 - v4 = cast v3 as u64 - inc_rc v0 - v6 = lt u64 5, v4 - v7 = not v6 - constrain v6 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v11 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v11 - v13 = array_get v0, index Field 0 - v15 = div v13, Field 2⁴ - v16 = cast v13 as u4 - v17 = truncate v16 to 1 bits, max_bit_size: 4 - v18 = cast v17 as u1 - jmpif v18 then: b1, else: b2 - b1(): - v53 = load v11 - v54 = array_get v0, index Field 0 - v55 = and v54, u8 15 - v56 = truncate v55 to 4 bits, max_bit_size: 8 - v57 = cast v56 as u4 - v58 = array_set v53, index Field 0, value v57 - store v58 at v11 - inc_rc v0 - jmp b9(Field 1) - b9(v59: Field): - v61 = lt v59, Field 5 - jmpif v61 then: b10, else: b11 - b10(): - v62 = truncate v59 to 64 bits, max_bit_size: 254 - v63 = cast v62 as u64 - v64 = truncate v1 to 64 bits, max_bit_size: 254 - v65 = cast v64 as u64 - v66 = lt v63, v65 - jmpif v66 then: b12, else: b13 - b12(): - v68 = array_get v0, index v59 - v69 = load v11 - v70 = mul Field 2, v59 - v71 = sub v70, Field 1 - v72 = div v68, Field 2⁴ - v73 = cast v68 as u4 - v74 = array_set v69, index v71, value v73 - v75 = add v71, Field 1 - store v74 at v11 - v76 = load v11 - v77 = mul Field 2, v59 - v78 = and v68, u8 15 - v79 = truncate v78 to 4 bits, max_bit_size: 8 - v80 = cast v79 as u4 - v81 = array_set v76, index v77, value v80 - v82 = add v77, Field 1 - store v81 at v11 - jmp b13() - b13(): - v67 = add v59, Field 1 - jmp b9(v67) - b11(): - jmp b6() - b6(): - v23 = load v11 - v25 = mul Field 2, v1 - v26 = cast v18 as Field - v27 = add v25, v26 - v28 = sub v27, Field 2 - inc_rc v23 - inc_rc v23 - inc_rc v23 - v83 = eq v28, Field 5 - constrain v28 == Field 5 - v84 = array_get v23, index Field 0 - v85 = array_get v23, index Field 1 - v86 = array_get v23, index Field 2 - v88 = array_get v23, index Field 3 - v90 = array_get v23, index Field 4 - v91 = allocate - store u1 1 at v91 - jmp b14(Field 0) - b14(v93: Field): - v94 = lt v93, Field 5 - jmpif v94 then: b15, else: b16 - b15(): - v239 = array_get [v84, v85, v86, v88, v90], index v93 - v246 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v93 - v247 = eq v239, v246 - v248 = load v91 - v249 = mul v248, v247 - store v249 at v91 - v250 = add v93, Field 1 - jmp b14(v250) - b16(): - v95 = load v91 - constrain v95 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v121 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v121 - jmp b17() - b17(): - jmp b18() - b18(): - v123 = load v121 - range_check u8 148 to 8 bits - v125 = array_set v123, index Field 0, value u8 148 - store v125 at v121 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - jmp b19(Field 1) - b19(v126: Field): - v128 = lt v126, Field 2⁵ - jmpif v128 then: b20, else: b21 - b20(): - v135 = load v121 - v136 = sub v126, Field 1 - v137 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v136 - v138 = array_set v135, index v126, value v137 - v139 = add v126, Field 1 - store v138 at v121 - v140 = add v126, Field 1 - jmp b19(v140) - b21(): - v129 = load v121 - inc_rc v129 - jmp b22(v129, Field 21) - b22(v131: [u8; 32], v132: Field): - jmp b23(v131, v132) - b23(v133: [u8; 32], v134: Field): - inc_rc v133 - v141 = allocate - store u1 1 at v141 - jmp b24(Field 0) - b24(v142: Field): - v143 = lt v142, Field 2⁵ - jmpif v143 then: b25, else: b26 - b25(): - v231 = array_get v133, index v142 - v233 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v142 - v234 = eq v231, v233 - v235 = load v141 - v236 = mul v235, v234 - store v236 at v141 - v237 = add v142, Field 1 - jmp b24(v237) - b26(): - v144 = load v141 - constrain v144 == u1 1 - v145 = eq v134, Field 21 - constrain v134 == Field 21 - v147 = allocate - store u64 0 at v147 - v148 = load v147 - v149 = or v148, u64 1 - store v149 at v147 - v150 = load v147 - v151 = eq v150, u64 1 - constrain v150 == u64 1 - v153 = allocate - store u64 0 at v153 - v154 = load v153 - v156 = or v154, u64 2⁴ - store v156 at v153 - v157 = load v153 - v158 = eq v157, u64 2⁴ - constrain v157 == u64 2⁴ - v160 = allocate - store u64 0 at v160 - v161 = load v160 - v220 = or v161, u64 1 - store v220 at v160 - v221 = load v160 - v222 = eq v221, u64 1 - constrain v221 == u64 1 - v225 = allocate - store u64 0 at v225 - v226 = load v225 - v228 = or v226, u64 2⁴ - store v228 at v225 - v229 = load v225 - v230 = eq v229, u64 2⁴ - constrain v229 == u64 2⁴ - return - b2(): - jmp b3(u64 0) - b3(v19: u64): - v22 = lt v19, u64 2 - jmpif v22 then: b4, else: b5 - b4(): - v29 = truncate v1 to 64 bits, max_bit_size: 254 - v30 = cast v29 as u64 - v32 = sub v30, u64 1 - range_check v32 to 64 bits - v33 = lt v19, v32 - jmpif v33 then: b7, else: b8 - b7(): - v36 = add v19, u64 1 - range_check v36 to 64 bits - v37 = array_get v0, index v36 - v38 = load v11 - v39 = mul u64 2, v19 - range_check v39 to 64 bits - v40 = div v37, Field 2⁴ - v41 = cast v37 as u4 - v42 = array_set v38, index v39, value v41 - v43 = add v39, Field 1 - store v42 at v11 - v44 = load v11 - v45 = mul u64 2, v19 - range_check v45 to 64 bits - v46 = add v45, u64 1 - range_check v46 to 64 bits - v48 = and v37, u8 15 - v49 = truncate v48 to 4 bits, max_bit_size: 8 - v50 = cast v49 as u4 - v51 = array_set v44, index v46, value v50 - v52 = add v46, Field 1 - store v51 at v11 - jmp b8() - b8(): - v35 = add v19, Field 1 - jmp b3(v35) - b5(): - jmp b6() -} - -After Mem2Reg: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v251 = truncate v1 to 64 bits, max_bit_size: 254 - v252 = cast v251 as u64 - inc_rc v0 - v253 = lt u64 5, v252 - v254 = not v253 - constrain v253 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v256 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 - v258 = array_get v0, index Field 0 - v259 = div v258, Field 2⁴ - v260 = cast v258 as u4 - v261 = truncate v260 to 1 bits, max_bit_size: 4 - v262 = cast v261 as u1 - jmpif v262 then: b1, else: b2 - b1(): - v286 = array_get v0, index Field 0 - v287 = and v286, u8 15 - v288 = truncate v287 to 4 bits, max_bit_size: 8 - v289 = cast v288 as u4 - store [v289, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 - inc_rc v0 - jmp b9(Field 1) - b9(v59: Field): - v293 = lt v59, Field 5 - jmpif v293 then: b10, else: b11 - b10(): - v359 = truncate v59 to 64 bits, max_bit_size: 254 - v360 = cast v359 as u64 - v361 = truncate v1 to 64 bits, max_bit_size: 254 - v362 = cast v361 as u64 - v363 = lt v360, v362 - jmpif v363 then: b12, else: b13 - b12(): - v364 = array_get v0, index v59 - v365 = load v256 - v366 = mul Field 2, v59 - v367 = sub v366, Field 1 - v368 = div v364, Field 2⁴ - v369 = cast v364 as u4 - v370 = array_set v365, index v367, value v369 - v371 = add v367, Field 1 - v373 = mul Field 2, v59 - v374 = and v364, u8 15 - v375 = truncate v374 to 4 bits, max_bit_size: 8 - v376 = cast v375 as u4 - v377 = array_set v370, index v373, value v376 - v378 = add v373, Field 1 - store v377 at v256 - jmp b13() - b13(): - v379 = add v59, Field 1 - jmp b9(v379) - b11(): - jmp b6() - b6(): - v294 = load v256 - v295 = mul Field 2, v1 - v296 = cast v262 as Field - v297 = add v295, v296 - v298 = sub v297, Field 2 - inc_rc v294 - inc_rc v294 - inc_rc v294 - v299 = eq v298, Field 5 - constrain v298 == Field 5 - v300 = array_get v294, index Field 0 - v301 = array_get v294, index Field 1 - v302 = array_get v294, index Field 2 - v303 = array_get v294, index Field 3 - v304 = array_get v294, index Field 4 - v305 = allocate - store u1 1 at v305 - jmp b14(Field 0) - b14(v93: Field): - v306 = lt v93, Field 5 - jmpif v306 then: b15, else: b16 - b15(): - v352 = array_get [v300, v301, v302, v303, v304], index v93 - v354 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v93 - v355 = eq v352, v354 - v356 = load v305 - v357 = mul v356, v355 - store v357 at v305 - v358 = add v93, Field 1 - jmp b14(v358) - b16(): - v307 = load v305 - constrain v307 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v312 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 - jmp b17() - b17(): - jmp b18() - b18(): - range_check u8 148 to 8 bits - store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - jmp b19(Field 1) - b19(v126: Field): - v319 = lt v126, Field 2⁵ - jmpif v319 then: b20, else: b21 - b20(): - v344 = load v312 - v345 = sub v126, Field 1 - v347 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v345 - v348 = array_set v344, index v126, value v347 - v349 = add v126, Field 1 - store v348 at v312 - v350 = add v126, Field 1 - jmp b19(v350) - b21(): - v320 = load v312 - inc_rc v320 - jmp b22(v320, Field 21) - b22(v131: [u8; 32], v132: Field): - jmp b23(v131, v132) - b23(v133: [u8; 32], v134: Field): - inc_rc v133 - v321 = allocate - store u1 1 at v321 - jmp b24(Field 0) - b24(v142: Field): - v322 = lt v142, Field 2⁵ - jmpif v322 then: b25, else: b26 - b25(): - v337 = array_get v133, index v142 - v339 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v142 - v340 = eq v337, v339 - v341 = load v321 - v342 = mul v341, v340 - store v342 at v321 - v343 = add v142, Field 1 - jmp b24(v343) - b26(): - v323 = load v321 - constrain v323 == u1 1 - v324 = eq v134, Field 21 - constrain v134 == Field 21 - v325 = allocate - store u64 1 at v325 - v328 = allocate - store u64 2⁴ at v328 - v331 = allocate - store u64 1 at v331 - v334 = allocate - store u64 2⁴ at v334 - return - b2(): - jmp b3(u64 0) - b3(v19: u64): - v263 = lt v19, u64 2 - jmpif v263 then: b4, else: b5 - b4(): - v264 = truncate v1 to 64 bits, max_bit_size: 254 - v265 = cast v264 as u64 - v266 = sub v265, u64 1 - range_check v266 to 64 bits - v267 = lt v19, v266 - jmpif v267 then: b7, else: b8 - b7(): - v268 = add v19, u64 1 - range_check v268 to 64 bits - v269 = array_get v0, index v268 - v270 = load v256 - v271 = mul u64 2, v19 - range_check v271 to 64 bits - v272 = div v269, Field 2⁴ - v273 = cast v269 as u4 - v274 = array_set v270, index v271, value v273 - v275 = add v271, Field 1 - v277 = mul u64 2, v19 - range_check v277 to 64 bits - v278 = add v277, u64 1 - range_check v278 to 64 bits - v279 = and v269, u8 15 - v280 = truncate v279 to 4 bits, max_bit_size: 8 - v281 = cast v280 as u4 - v282 = array_set v274, index v278, value v281 - v283 = add v278, Field 1 - store v282 at v256 - jmp b8() - b8(): - v284 = add v19, Field 1 - jmp b3(v284) - b5(): - jmp b6() -} - -After Assert Constant: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v251 = truncate v1 to 64 bits, max_bit_size: 254 - v252 = cast v251 as u64 - inc_rc v0 - v253 = lt u64 5, v252 - v254 = not v253 - constrain v253 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v256 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 - v258 = array_get v0, index Field 0 - v259 = div v258, Field 2⁴ - v260 = cast v258 as u4 - v261 = truncate v260 to 1 bits, max_bit_size: 4 - v262 = cast v261 as u1 - jmpif v262 then: b1, else: b2 - b1(): - v286 = array_get v0, index Field 0 - v287 = and v286, u8 15 - v288 = truncate v287 to 4 bits, max_bit_size: 8 - v289 = cast v288 as u4 - store [v289, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 - inc_rc v0 - jmp b9(Field 1) - b9(v59: Field): - v293 = lt v59, Field 5 - jmpif v293 then: b10, else: b11 - b10(): - v359 = truncate v59 to 64 bits, max_bit_size: 254 - v360 = cast v359 as u64 - v361 = truncate v1 to 64 bits, max_bit_size: 254 - v362 = cast v361 as u64 - v363 = lt v360, v362 - jmpif v363 then: b12, else: b13 - b12(): - v364 = array_get v0, index v59 - v365 = load v256 - v366 = mul Field 2, v59 - v367 = sub v366, Field 1 - v368 = div v364, Field 2⁴ - v369 = cast v364 as u4 - v370 = array_set v365, index v367, value v369 - v371 = add v367, Field 1 - v373 = mul Field 2, v59 - v374 = and v364, u8 15 - v375 = truncate v374 to 4 bits, max_bit_size: 8 - v376 = cast v375 as u4 - v377 = array_set v370, index v373, value v376 - v378 = add v373, Field 1 - store v377 at v256 - jmp b13() - b13(): - v379 = add v59, Field 1 - jmp b9(v379) - b11(): - jmp b6() - b6(): - v294 = load v256 - v295 = mul Field 2, v1 - v296 = cast v262 as Field - v297 = add v295, v296 - v298 = sub v297, Field 2 - inc_rc v294 - inc_rc v294 - inc_rc v294 - v299 = eq v298, Field 5 - constrain v298 == Field 5 - v300 = array_get v294, index Field 0 - v301 = array_get v294, index Field 1 - v302 = array_get v294, index Field 2 - v303 = array_get v294, index Field 3 - v304 = array_get v294, index Field 4 - v305 = allocate - store u1 1 at v305 - jmp b14(Field 0) - b14(v93: Field): - v306 = lt v93, Field 5 - jmpif v306 then: b15, else: b16 - b15(): - v352 = array_get [v300, v301, v302, v303, v304], index v93 - v354 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v93 - v355 = eq v352, v354 - v356 = load v305 - v357 = mul v356, v355 - store v357 at v305 - v358 = add v93, Field 1 - jmp b14(v358) - b16(): - v307 = load v305 - constrain v307 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v312 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 - jmp b17() - b17(): - jmp b18() - b18(): - range_check u8 148 to 8 bits - store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - jmp b19(Field 1) - b19(v126: Field): - v319 = lt v126, Field 2⁵ - jmpif v319 then: b20, else: b21 - b20(): - v344 = load v312 - v345 = sub v126, Field 1 - v347 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v345 - v348 = array_set v344, index v126, value v347 - v349 = add v126, Field 1 - store v348 at v312 - v350 = add v126, Field 1 - jmp b19(v350) - b21(): - v320 = load v312 - inc_rc v320 - jmp b22(v320, Field 21) - b22(v131: [u8; 32], v132: Field): - jmp b23(v131, v132) - b23(v133: [u8; 32], v134: Field): - inc_rc v133 - v321 = allocate - store u1 1 at v321 - jmp b24(Field 0) - b24(v142: Field): - v322 = lt v142, Field 2⁵ - jmpif v322 then: b25, else: b26 - b25(): - v337 = array_get v133, index v142 - v339 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v142 - v340 = eq v337, v339 - v341 = load v321 - v342 = mul v341, v340 - store v342 at v321 - v343 = add v142, Field 1 - jmp b24(v343) - b26(): - v323 = load v321 - constrain v323 == u1 1 - v324 = eq v134, Field 21 - constrain v134 == Field 21 - v325 = allocate - store u64 1 at v325 - v328 = allocate - store u64 2⁴ at v328 - v331 = allocate - store u64 1 at v331 - v334 = allocate - store u64 2⁴ at v334 - return - b2(): - jmp b3(u64 0) - b3(v19: u64): - v263 = lt v19, u64 2 - jmpif v263 then: b4, else: b5 - b4(): - v264 = truncate v1 to 64 bits, max_bit_size: 254 - v265 = cast v264 as u64 - v266 = sub v265, u64 1 - range_check v266 to 64 bits - v267 = lt v19, v266 - jmpif v267 then: b7, else: b8 - b7(): - v268 = add v19, u64 1 - range_check v268 to 64 bits - v269 = array_get v0, index v268 - v270 = load v256 - v271 = mul u64 2, v19 - range_check v271 to 64 bits - v272 = div v269, Field 2⁴ - v273 = cast v269 as u4 - v274 = array_set v270, index v271, value v273 - v275 = add v271, Field 1 - v277 = mul u64 2, v19 - range_check v277 to 64 bits - v278 = add v277, u64 1 - range_check v278 to 64 bits - v279 = and v269, u8 15 - v280 = truncate v279 to 4 bits, max_bit_size: 8 - v281 = cast v280 as u4 - v282 = array_set v274, index v278, value v281 - v283 = add v278, Field 1 - store v282 at v256 - jmp b8() - b8(): - v284 = add v19, Field 1 - jmp b3(v284) - b5(): - jmp b6() -} - -After Unrolling: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v251 = truncate v1 to 64 bits, max_bit_size: 254 - v252 = cast v251 as u64 - inc_rc v0 - v253 = lt u64 5, v252 - v254 = not v253 - constrain v253 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v256 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 - v258 = array_get v0, index Field 0 - v259 = div v258, Field 2⁴ - v260 = cast v258 as u4 - v261 = truncate v260 to 1 bits, max_bit_size: 4 - v262 = cast v261 as u1 - jmpif v262 then: b1, else: b2 - b1(): - v286 = array_get v0, index Field 0 - v287 = and v286, u8 15 - v288 = truncate v287 to 4 bits, max_bit_size: 8 - v289 = cast v288 as u4 - store [v289, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 - inc_rc v0 - v381 = truncate v1 to 64 bits, max_bit_size: 254 - v382 = cast v381 as u64 - v383 = lt u64 1, v382 - jmpif v383 then: b29, else: b30 - b29(): - v385 = array_get v0, index Field 1 - v386 = load v256 - v387 = div v385, Field 2⁴ - v388 = cast v385 as u4 - v389 = array_set v386, index Field 1, value v388 - v390 = and v385, u8 15 - v391 = truncate v390 to 4 bits, max_bit_size: 8 - v392 = cast v391 as u4 - v393 = array_set v389, index Field 2, value v392 - store v393 at v256 - jmp b30() - b30(): - v394 = truncate v1 to 64 bits, max_bit_size: 254 - v395 = cast v394 as u64 - v396 = lt u64 2, v395 - jmpif v396 then: b34, else: b35 - b34(): - v398 = array_get v0, index Field 2 - v399 = load v256 - v400 = div v398, Field 2⁴ - v401 = cast v398 as u4 - v402 = array_set v399, index Field 3, value v401 - v403 = and v398, u8 15 - v404 = truncate v403 to 4 bits, max_bit_size: 8 - v405 = cast v404 as u4 - v406 = array_set v402, index Field 4, value v405 - store v406 at v256 - jmp b35() - b35(): - v408 = truncate v1 to 64 bits, max_bit_size: 254 - v409 = cast v408 as u64 - v410 = lt u64 3, v409 - jmpif v410 then: b39, else: b40 - b39(): - v412 = array_get v0, index Field 3 - v413 = load v256 - v414 = div v412, Field 2⁴ - v415 = cast v412 as u4 - v416 = array_set v413, index Field 5, value v415 - v417 = and v412, u8 15 - v418 = truncate v417 to 4 bits, max_bit_size: 8 - v419 = cast v418 as u4 - v420 = array_set v416, index Field 6, value v419 - store v420 at v256 - jmp b40() - b40(): - v421 = truncate v1 to 64 bits, max_bit_size: 254 - v422 = cast v421 as u64 - v423 = lt u64 4, v422 - jmpif v423 then: b44, else: b45 - b44(): - v425 = array_get v0, index Field 4 - v426 = load v256 - v427 = div v425, Field 2⁴ - v428 = cast v425 as u4 - v429 = array_set v426, index Field 7, value v428 - v430 = and v425, u8 15 - v431 = truncate v430 to 4 bits, max_bit_size: 8 - v432 = cast v431 as u4 - v433 = array_set v429, index Field 8, value v432 - store v433 at v256 - jmp b45() - b45(): - jmp b11() - b11(): - jmp b6() - b6(): - v294 = load v256 - v295 = mul Field 2, v1 - v296 = cast v262 as Field - v297 = add v295, v296 - v298 = sub v297, Field 2 - inc_rc v294 - inc_rc v294 - inc_rc v294 - v299 = eq v298, Field 5 - constrain v298 == Field 5 - v300 = array_get v294, index Field 0 - v301 = array_get v294, index Field 1 - v302 = array_get v294, index Field 2 - v303 = array_get v294, index Field 3 - v304 = array_get v294, index Field 4 - v305 = allocate - store u1 1 at v305 - v780 = eq v300, u4 15 - v781 = load v305 - v782 = mul v781, v780 - store v782 at v305 - v786 = eq v301, u4 1 - v787 = load v305 - v788 = mul v787, v786 - store v788 at v305 - v792 = eq v302, u4 12 - v793 = load v305 - v794 = mul v793, v792 - store v794 at v305 - v798 = eq v303, u4 11 - v799 = load v305 - v800 = mul v799, v798 - store v800 at v305 - v804 = eq v304, u4 8 - v805 = load v305 - v806 = mul v805, v804 - store v806 at v305 - jmp b16() - b16(): - v307 = load v305 - constrain v307 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v312 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 - jmp b17() - b17(): - jmp b18() - b18(): - range_check u8 148 to 8 bits - store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v654 = load v312 - v656 = array_set v654, index Field 1, value u8 184 - store v656 at v312 - v658 = load v312 - v660 = array_set v658, index Field 2, value u8 143 - store v660 at v312 - v662 = load v312 - v664 = array_set v662, index Field 3, value u8 97 - store v664 at v312 - v666 = load v312 - v668 = array_set v666, index Field 4, value u8 230 - store v668 at v312 - v670 = load v312 - v672 = array_set v670, index Field 5, value u8 251 - store v672 at v312 - v674 = load v312 - v676 = array_set v674, index Field 6, value u8 218 - store v676 at v312 - v678 = load v312 - v680 = array_set v678, index Field 7, value u8 131 - store v680 at v312 - v682 = load v312 - v684 = array_set v682, index Field 8, value u8 251 - store v684 at v312 - v686 = load v312 - v688 = array_set v686, index Field 9, value u8 255 - store v688 at v312 - v690 = load v312 - v692 = array_set v690, index Field 10, value u8 250 - store v692 at v312 - v694 = load v312 - v696 = array_set v694, index Field 11, value u8 190 - store v696 at v312 - v698 = load v312 - v700 = array_set v698, index Field 12, value u8 54 - store v700 at v312 - v702 = load v312 - v704 = array_set v702, index Field 13, value u8 65 - store v704 at v312 - v706 = load v312 - v708 = array_set v706, index Field 14, value u8 18 - store v708 at v312 - v710 = load v312 - v712 = array_set v710, index Field 15, value u8 19 - store v712 at v312 - v714 = load v312 - v716 = array_set v714, index Field 2⁴, value u8 116 - store v716 at v312 - v718 = load v312 - v720 = array_set v718, index Field 17, value u8 2⁷ - store v720 at v312 - v722 = load v312 - v724 = array_set v722, index Field 18, value u8 57 - store v724 at v312 - v726 = load v312 - v728 = array_set v726, index Field 19, value u8 2⁷ - store v728 at v312 - v730 = load v312 - v732 = array_set v730, index Field 20, value u8 24 - store v732 at v312 - v734 = load v312 - v736 = array_set v734, index Field 21, value u8 0 - store v736 at v312 - v738 = load v312 - v740 = array_set v738, index Field 22, value u8 0 - store v740 at v312 - v742 = load v312 - v744 = array_set v742, index Field 23, value u8 0 - store v744 at v312 - v746 = load v312 - v748 = array_set v746, index Field 24, value u8 0 - store v748 at v312 - v750 = load v312 - v752 = array_set v750, index Field 25, value u8 0 - store v752 at v312 - v754 = load v312 - v756 = array_set v754, index Field 26, value u8 0 - store v756 at v312 - v758 = load v312 - v760 = array_set v758, index Field 27, value u8 0 - store v760 at v312 - v762 = load v312 - v764 = array_set v762, index Field 28, value u8 0 - store v764 at v312 - v766 = load v312 - v768 = array_set v766, index Field 29, value u8 0 - store v768 at v312 - v770 = load v312 - v772 = array_set v770, index Field 30, value u8 0 - store v772 at v312 - v774 = load v312 - v776 = array_set v774, index Field 31, value u8 0 - store v776 at v312 - jmp b21() - b21(): - v320 = load v312 - inc_rc v320 - jmp b22(v320, Field 21) - b22(v131: [u8; 32], v132: Field): - jmp b23(v131, v132) - b23(v133: [u8; 32], v134: Field): - inc_rc v133 - v321 = allocate - store u1 1 at v321 - v462 = array_get v133, index Field 0 - v464 = eq v462, u8 148 - v465 = load v321 - v466 = mul v465, v464 - store v466 at v321 - v468 = array_get v133, index Field 1 - v470 = eq v468, u8 184 - v471 = load v321 - v472 = mul v471, v470 - store v472 at v321 - v474 = array_get v133, index Field 2 - v476 = eq v474, u8 143 - v477 = load v321 - v478 = mul v477, v476 - store v478 at v321 - v480 = array_get v133, index Field 3 - v482 = eq v480, u8 97 - v483 = load v321 - v484 = mul v483, v482 - store v484 at v321 - v486 = array_get v133, index Field 4 - v488 = eq v486, u8 230 - v489 = load v321 - v490 = mul v489, v488 - store v490 at v321 - v492 = array_get v133, index Field 5 - v494 = eq v492, u8 251 - v495 = load v321 - v496 = mul v495, v494 - store v496 at v321 - v498 = array_get v133, index Field 6 - v500 = eq v498, u8 218 - v501 = load v321 - v502 = mul v501, v500 - store v502 at v321 - v504 = array_get v133, index Field 7 - v506 = eq v504, u8 131 - v507 = load v321 - v508 = mul v507, v506 - store v508 at v321 - v510 = array_get v133, index Field 8 - v512 = eq v510, u8 251 - v513 = load v321 - v514 = mul v513, v512 - store v514 at v321 - v516 = array_get v133, index Field 9 - v518 = eq v516, u8 255 - v519 = load v321 - v520 = mul v519, v518 - store v520 at v321 - v522 = array_get v133, index Field 10 - v524 = eq v522, u8 250 - v525 = load v321 - v526 = mul v525, v524 - store v526 at v321 - v528 = array_get v133, index Field 11 - v530 = eq v528, u8 190 - v531 = load v321 - v532 = mul v531, v530 - store v532 at v321 - v534 = array_get v133, index Field 12 - v536 = eq v534, u8 54 - v537 = load v321 - v538 = mul v537, v536 - store v538 at v321 - v540 = array_get v133, index Field 13 - v542 = eq v540, u8 65 - v543 = load v321 - v544 = mul v543, v542 - store v544 at v321 - v546 = array_get v133, index Field 14 - v548 = eq v546, u8 18 - v549 = load v321 - v550 = mul v549, v548 - store v550 at v321 - v552 = array_get v133, index Field 15 - v554 = eq v552, u8 19 - v555 = load v321 - v556 = mul v555, v554 - store v556 at v321 - v558 = array_get v133, index Field 2⁴ - v560 = eq v558, u8 116 - v561 = load v321 - v562 = mul v561, v560 - store v562 at v321 - v564 = array_get v133, index Field 17 - v566 = eq v564, u8 2⁷ - v567 = load v321 - v568 = mul v567, v566 - store v568 at v321 - v570 = array_get v133, index Field 18 - v572 = eq v570, u8 57 - v573 = load v321 - v574 = mul v573, v572 - store v574 at v321 - v576 = array_get v133, index Field 19 - v578 = eq v576, u8 2⁷ - v579 = load v321 - v580 = mul v579, v578 - store v580 at v321 - v582 = array_get v133, index Field 20 - v584 = eq v582, u8 24 - v585 = load v321 - v586 = mul v585, v584 - store v586 at v321 - v588 = array_get v133, index Field 21 - v590 = eq v588, u8 0 - v591 = load v321 - v592 = mul v591, v590 - store v592 at v321 - v594 = array_get v133, index Field 22 - v596 = eq v594, u8 0 - v597 = load v321 - v598 = mul v597, v596 - store v598 at v321 - v600 = array_get v133, index Field 23 - v602 = eq v600, u8 0 - v603 = load v321 - v604 = mul v603, v602 - store v604 at v321 - v606 = array_get v133, index Field 24 - v608 = eq v606, u8 0 - v609 = load v321 - v610 = mul v609, v608 - store v610 at v321 - v612 = array_get v133, index Field 25 - v614 = eq v612, u8 0 - v615 = load v321 - v616 = mul v615, v614 - store v616 at v321 - v618 = array_get v133, index Field 26 - v620 = eq v618, u8 0 - v621 = load v321 - v622 = mul v621, v620 - store v622 at v321 - v624 = array_get v133, index Field 27 - v626 = eq v624, u8 0 - v627 = load v321 - v628 = mul v627, v626 - store v628 at v321 - v630 = array_get v133, index Field 28 - v632 = eq v630, u8 0 - v633 = load v321 - v634 = mul v633, v632 - store v634 at v321 - v636 = array_get v133, index Field 29 - v638 = eq v636, u8 0 - v639 = load v321 - v640 = mul v639, v638 - store v640 at v321 - v642 = array_get v133, index Field 30 - v644 = eq v642, u8 0 - v645 = load v321 - v646 = mul v645, v644 - store v646 at v321 - v648 = array_get v133, index Field 31 - v650 = eq v648, u8 0 - v651 = load v321 - v652 = mul v651, v650 - store v652 at v321 - jmp b26() - b26(): - v323 = load v321 - constrain v323 == u1 1 - v324 = eq v134, Field 21 - constrain v134 == Field 21 - v325 = allocate - store u64 1 at v325 - v328 = allocate - store u64 2⁴ at v328 - v331 = allocate - store u64 1 at v331 - v334 = allocate - store u64 2⁴ at v334 - return - b2(): - v434 = truncate v1 to 64 bits, max_bit_size: 254 - v435 = cast v434 as u64 - v436 = sub v435, u64 1 - range_check v436 to 64 bits - v437 = lt u64 0, v436 - jmpif v437 then: b51, else: b52 - b51(): - v439 = array_get v0, index u64 1 - v440 = load v256 - v441 = div v439, Field 2⁴ - v442 = cast v439 as u4 - v443 = array_set v440, index u64 0, value v442 - v444 = and v439, u8 15 - v445 = truncate v444 to 4 bits, max_bit_size: 8 - v446 = cast v445 as u4 - v447 = array_set v443, index u64 1, value v446 - store v447 at v256 - jmp b52() - b52(): - v448 = truncate v1 to 64 bits, max_bit_size: 254 - v449 = cast v448 as u64 - v450 = sub v449, u64 1 - range_check v450 to 64 bits - v451 = lt u64 1, v450 - jmpif v451 then: b56, else: b57 - b56(): - v453 = array_get v0, index u64 2 - v454 = load v256 - v455 = div v453, Field 2⁴ - v456 = cast v453 as u4 - v457 = array_set v454, index u64 2, value v456 - v458 = and v453, u8 15 - v459 = truncate v458 to 4 bits, max_bit_size: 8 - v460 = cast v459 as u4 - v461 = array_set v457, index u64 3, value v460 - store v461 at v256 - jmp b57() - b57(): - jmp b5() - b5(): - jmp b6() -} - -After Simplifying: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v251 = truncate v1 to 64 bits, max_bit_size: 254 - v252 = cast v251 as u64 - inc_rc v0 - v253 = lt u64 5, v252 - v254 = not v253 - constrain v253 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v256 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 - v258 = array_get v0, index Field 0 - v259 = div v258, Field 2⁴ - v260 = cast v258 as u4 - v261 = truncate v260 to 1 bits, max_bit_size: 4 - v262 = cast v261 as u1 - jmpif v262 then: b1, else: b2 - b1(): - v286 = array_get v0, index Field 0 - v287 = and v286, u8 15 - v288 = truncate v287 to 4 bits, max_bit_size: 8 - v289 = cast v288 as u4 - store [v289, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v256 - inc_rc v0 - v381 = truncate v1 to 64 bits, max_bit_size: 254 - v382 = cast v381 as u64 - v383 = lt u64 1, v382 - jmpif v383 then: b29, else: b30 - b29(): - v385 = array_get v0, index Field 1 - v386 = load v256 - v387 = div v385, Field 2⁴ - v388 = cast v385 as u4 - v389 = array_set v386, index Field 1, value v388 - v390 = and v385, u8 15 - v391 = truncate v390 to 4 bits, max_bit_size: 8 - v392 = cast v391 as u4 - v393 = array_set v389, index Field 2, value v392 - store v393 at v256 - jmp b30() - b30(): - v394 = truncate v1 to 64 bits, max_bit_size: 254 - v395 = cast v394 as u64 - v396 = lt u64 2, v395 - jmpif v396 then: b34, else: b35 - b34(): - v398 = array_get v0, index Field 2 - v399 = load v256 - v400 = div v398, Field 2⁴ - v401 = cast v398 as u4 - v402 = array_set v399, index Field 3, value v401 - v403 = and v398, u8 15 - v404 = truncate v403 to 4 bits, max_bit_size: 8 - v405 = cast v404 as u4 - v406 = array_set v402, index Field 4, value v405 - store v406 at v256 - jmp b35() - b35(): - v408 = truncate v1 to 64 bits, max_bit_size: 254 - v409 = cast v408 as u64 - v410 = lt u64 3, v409 - jmpif v410 then: b39, else: b40 - b39(): - v412 = array_get v0, index Field 3 - v413 = load v256 - v414 = div v412, Field 2⁴ - v415 = cast v412 as u4 - v416 = array_set v413, index Field 5, value v415 - v417 = and v412, u8 15 - v418 = truncate v417 to 4 bits, max_bit_size: 8 - v419 = cast v418 as u4 - v420 = array_set v416, index Field 6, value v419 - store v420 at v256 - jmp b40() - b40(): - v421 = truncate v1 to 64 bits, max_bit_size: 254 - v422 = cast v421 as u64 - v423 = lt u64 4, v422 - jmpif v423 then: b44, else: b45 - b44(): - v425 = array_get v0, index Field 4 - v426 = load v256 - v427 = div v425, Field 2⁴ - v428 = cast v425 as u4 - v429 = array_set v426, index Field 7, value v428 - v430 = and v425, u8 15 - v431 = truncate v430 to 4 bits, max_bit_size: 8 - v432 = cast v431 as u4 - v433 = array_set v429, index Field 8, value v432 - store v433 at v256 - jmp b45() - b45(): - jmp b6() - b6(): - v294 = load v256 - v295 = mul Field 2, v1 - v296 = cast v262 as Field - v297 = add v295, v296 - v298 = sub v297, Field 2 - inc_rc v294 - inc_rc v294 - inc_rc v294 - v299 = eq v298, Field 5 - constrain v298 == Field 5 - v300 = array_get v294, index Field 0 - v301 = array_get v294, index Field 1 - v302 = array_get v294, index Field 2 - v303 = array_get v294, index Field 3 - v304 = array_get v294, index Field 4 - v305 = allocate - store u1 1 at v305 - v780 = eq v300, u4 15 - v781 = load v305 - v782 = mul v781, v780 - store v782 at v305 - v786 = eq v301, u4 1 - v787 = load v305 - v788 = mul v787, v786 - store v788 at v305 - v792 = eq v302, u4 12 - v793 = load v305 - v794 = mul v793, v792 - store v794 at v305 - v798 = eq v303, u4 11 - v799 = load v305 - v800 = mul v799, v798 - store v800 at v305 - v804 = eq v304, u4 8 - v805 = load v305 - v806 = mul v805, v804 - store v806 at v305 - v307 = load v305 - constrain v307 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v312 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 - range_check u8 148 to 8 bits - store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v312 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v654 = load v312 - v656 = array_set v654, index Field 1, value u8 184 - store v656 at v312 - v658 = load v312 - v660 = array_set v658, index Field 2, value u8 143 - store v660 at v312 - v662 = load v312 - v664 = array_set v662, index Field 3, value u8 97 - store v664 at v312 - v666 = load v312 - v668 = array_set v666, index Field 4, value u8 230 - store v668 at v312 - v670 = load v312 - v672 = array_set v670, index Field 5, value u8 251 - store v672 at v312 - v674 = load v312 - v676 = array_set v674, index Field 6, value u8 218 - store v676 at v312 - v678 = load v312 - v680 = array_set v678, index Field 7, value u8 131 - store v680 at v312 - v682 = load v312 - v684 = array_set v682, index Field 8, value u8 251 - store v684 at v312 - v686 = load v312 - v688 = array_set v686, index Field 9, value u8 255 - store v688 at v312 - v690 = load v312 - v692 = array_set v690, index Field 10, value u8 250 - store v692 at v312 - v694 = load v312 - v696 = array_set v694, index Field 11, value u8 190 - store v696 at v312 - v698 = load v312 - v700 = array_set v698, index Field 12, value u8 54 - store v700 at v312 - v702 = load v312 - v704 = array_set v702, index Field 13, value u8 65 - store v704 at v312 - v706 = load v312 - v708 = array_set v706, index Field 14, value u8 18 - store v708 at v312 - v710 = load v312 - v712 = array_set v710, index Field 15, value u8 19 - store v712 at v312 - v714 = load v312 - v716 = array_set v714, index Field 2⁴, value u8 116 - store v716 at v312 - v718 = load v312 - v720 = array_set v718, index Field 17, value u8 2⁷ - store v720 at v312 - v722 = load v312 - v724 = array_set v722, index Field 18, value u8 57 - store v724 at v312 - v726 = load v312 - v728 = array_set v726, index Field 19, value u8 2⁷ - store v728 at v312 - v730 = load v312 - v732 = array_set v730, index Field 20, value u8 24 - store v732 at v312 - v734 = load v312 - v736 = array_set v734, index Field 21, value u8 0 - store v736 at v312 - v738 = load v312 - v740 = array_set v738, index Field 22, value u8 0 - store v740 at v312 - v742 = load v312 - v744 = array_set v742, index Field 23, value u8 0 - store v744 at v312 - v746 = load v312 - v748 = array_set v746, index Field 24, value u8 0 - store v748 at v312 - v750 = load v312 - v752 = array_set v750, index Field 25, value u8 0 - store v752 at v312 - v754 = load v312 - v756 = array_set v754, index Field 26, value u8 0 - store v756 at v312 - v758 = load v312 - v760 = array_set v758, index Field 27, value u8 0 - store v760 at v312 - v762 = load v312 - v764 = array_set v762, index Field 28, value u8 0 - store v764 at v312 - v766 = load v312 - v768 = array_set v766, index Field 29, value u8 0 - store v768 at v312 - v770 = load v312 - v772 = array_set v770, index Field 30, value u8 0 - store v772 at v312 - v774 = load v312 - v776 = array_set v774, index Field 31, value u8 0 - store v776 at v312 - v320 = load v312 - inc_rc v320 - inc_rc v320 - v321 = allocate - store u1 1 at v321 - v462 = array_get v320, index Field 0 - v464 = eq v462, u8 148 - v465 = load v321 - v466 = mul v465, v464 - store v466 at v321 - v468 = array_get v320, index Field 1 - v470 = eq v468, u8 184 - v471 = load v321 - v472 = mul v471, v470 - store v472 at v321 - v474 = array_get v320, index Field 2 - v476 = eq v474, u8 143 - v477 = load v321 - v478 = mul v477, v476 - store v478 at v321 - v480 = array_get v320, index Field 3 - v482 = eq v480, u8 97 - v483 = load v321 - v484 = mul v483, v482 - store v484 at v321 - v486 = array_get v320, index Field 4 - v488 = eq v486, u8 230 - v489 = load v321 - v490 = mul v489, v488 - store v490 at v321 - v492 = array_get v320, index Field 5 - v494 = eq v492, u8 251 - v495 = load v321 - v496 = mul v495, v494 - store v496 at v321 - v498 = array_get v320, index Field 6 - v500 = eq v498, u8 218 - v501 = load v321 - v502 = mul v501, v500 - store v502 at v321 - v504 = array_get v320, index Field 7 - v506 = eq v504, u8 131 - v507 = load v321 - v508 = mul v507, v506 - store v508 at v321 - v510 = array_get v320, index Field 8 - v512 = eq v510, u8 251 - v513 = load v321 - v514 = mul v513, v512 - store v514 at v321 - v516 = array_get v320, index Field 9 - v518 = eq v516, u8 255 - v519 = load v321 - v520 = mul v519, v518 - store v520 at v321 - v522 = array_get v320, index Field 10 - v524 = eq v522, u8 250 - v525 = load v321 - v526 = mul v525, v524 - store v526 at v321 - v528 = array_get v320, index Field 11 - v530 = eq v528, u8 190 - v531 = load v321 - v532 = mul v531, v530 - store v532 at v321 - v534 = array_get v320, index Field 12 - v536 = eq v534, u8 54 - v537 = load v321 - v538 = mul v537, v536 - store v538 at v321 - v540 = array_get v320, index Field 13 - v542 = eq v540, u8 65 - v543 = load v321 - v544 = mul v543, v542 - store v544 at v321 - v546 = array_get v320, index Field 14 - v548 = eq v546, u8 18 - v549 = load v321 - v550 = mul v549, v548 - store v550 at v321 - v552 = array_get v320, index Field 15 - v554 = eq v552, u8 19 - v555 = load v321 - v556 = mul v555, v554 - store v556 at v321 - v558 = array_get v320, index Field 2⁴ - v560 = eq v558, u8 116 - v561 = load v321 - v562 = mul v561, v560 - store v562 at v321 - v564 = array_get v320, index Field 17 - v566 = eq v564, u8 2⁷ - v567 = load v321 - v568 = mul v567, v566 - store v568 at v321 - v570 = array_get v320, index Field 18 - v572 = eq v570, u8 57 - v573 = load v321 - v574 = mul v573, v572 - store v574 at v321 - v576 = array_get v320, index Field 19 - v578 = eq v576, u8 2⁷ - v579 = load v321 - v580 = mul v579, v578 - store v580 at v321 - v582 = array_get v320, index Field 20 - v584 = eq v582, u8 24 - v585 = load v321 - v586 = mul v585, v584 - store v586 at v321 - v588 = array_get v320, index Field 21 - v590 = eq v588, u8 0 - v591 = load v321 - v592 = mul v591, v590 - store v592 at v321 - v594 = array_get v320, index Field 22 - v596 = eq v594, u8 0 - v597 = load v321 - v598 = mul v597, v596 - store v598 at v321 - v600 = array_get v320, index Field 23 - v602 = eq v600, u8 0 - v603 = load v321 - v604 = mul v603, v602 - store v604 at v321 - v606 = array_get v320, index Field 24 - v608 = eq v606, u8 0 - v609 = load v321 - v610 = mul v609, v608 - store v610 at v321 - v612 = array_get v320, index Field 25 - v614 = eq v612, u8 0 - v615 = load v321 - v616 = mul v615, v614 - store v616 at v321 - v618 = array_get v320, index Field 26 - v620 = eq v618, u8 0 - v621 = load v321 - v622 = mul v621, v620 - store v622 at v321 - v624 = array_get v320, index Field 27 - v626 = eq v624, u8 0 - v627 = load v321 - v628 = mul v627, v626 - store v628 at v321 - v630 = array_get v320, index Field 28 - v632 = eq v630, u8 0 - v633 = load v321 - v634 = mul v633, v632 - store v634 at v321 - v636 = array_get v320, index Field 29 - v638 = eq v636, u8 0 - v639 = load v321 - v640 = mul v639, v638 - store v640 at v321 - v642 = array_get v320, index Field 30 - v644 = eq v642, u8 0 - v645 = load v321 - v646 = mul v645, v644 - store v646 at v321 - v648 = array_get v320, index Field 31 - v650 = eq v648, u8 0 - v651 = load v321 - v652 = mul v651, v650 - store v652 at v321 - v323 = load v321 - constrain v323 == u1 1 - v324 = eq Field 21, Field 21 - constrain Field 21 == Field 21 - v325 = allocate - store u64 1 at v325 - v328 = allocate - store u64 2⁴ at v328 - v331 = allocate - store u64 1 at v331 - v334 = allocate - store u64 2⁴ at v334 - return - b2(): - v434 = truncate v1 to 64 bits, max_bit_size: 254 - v435 = cast v434 as u64 - v436 = sub v435, u64 1 - range_check v436 to 64 bits - v437 = lt u64 0, v436 - jmpif v437 then: b51, else: b52 - b51(): - v439 = array_get v0, index u64 1 - v440 = load v256 - v441 = div v439, Field 2⁴ - v442 = cast v439 as u4 - v443 = array_set v440, index u64 0, value v442 - v444 = and v439, u8 15 - v445 = truncate v444 to 4 bits, max_bit_size: 8 - v446 = cast v445 as u4 - v447 = array_set v443, index u64 1, value v446 - store v447 at v256 - jmp b52() - b52(): - v448 = truncate v1 to 64 bits, max_bit_size: 254 - v449 = cast v448 as u64 - v450 = sub v449, u64 1 - range_check v450 to 64 bits - v451 = lt u64 1, v450 - jmpif v451 then: b56, else: b57 - b56(): - v453 = array_get v0, index u64 2 - v454 = load v256 - v455 = div v453, Field 2⁴ - v456 = cast v453 as u4 - v457 = array_set v454, index u64 2, value v456 - v458 = and v453, u8 15 - v459 = truncate v458 to 4 bits, max_bit_size: 8 - v460 = cast v459 as u4 - v461 = array_set v457, index u64 3, value v460 - store v461 at v256 - jmp b57() - b57(): - jmp b6() -} - -After Mem2Reg: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v808 = truncate v1 to 64 bits, max_bit_size: 254 - v809 = cast v808 as u64 - inc_rc v0 - v810 = lt u64 5, v809 - v811 = not v810 - constrain v810 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v813 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 - v815 = array_get v0, index Field 0 - v816 = div v815, Field 2⁴ - v817 = cast v815 as u4 - v818 = truncate v817 to 1 bits, max_bit_size: 4 - v819 = cast v818 as u1 - jmpif v819 then: b1, else: b2 - b1(): - v849 = array_get v0, index Field 0 - v850 = and v849, u8 15 - v851 = truncate v850 to 4 bits, max_bit_size: 8 - v852 = cast v851 as u4 - store [v852, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 - inc_rc v0 - v854 = truncate v1 to 64 bits, max_bit_size: 254 - v855 = cast v854 as u64 - v856 = lt u64 1, v855 - jmpif v856 then: b29, else: b30 - b29(): - v857 = array_get v0, index Field 1 - v859 = div v857, Field 2⁴ - v860 = cast v857 as u4 - v863 = and v857, u8 15 - v864 = truncate v863 to 4 bits, max_bit_size: 8 - v865 = cast v864 as u4 - store [v852, v860, v865, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 - jmp b30() - b30(): - v869 = truncate v1 to 64 bits, max_bit_size: 254 - v870 = cast v869 as u64 - v871 = lt u64 2, v870 - jmpif v871 then: b34, else: b35 - b34(): - v872 = array_get v0, index Field 2 - v873 = load v813 - v874 = div v872, Field 2⁴ - v875 = cast v872 as u4 - v876 = array_set v873, index Field 3, value v875 - v877 = and v872, u8 15 - v878 = truncate v877 to 4 bits, max_bit_size: 8 - v879 = cast v878 as u4 - v880 = array_set v876, index Field 4, value v879 - store v880 at v813 - jmp b35() - b35(): - v881 = truncate v1 to 64 bits, max_bit_size: 254 - v882 = cast v881 as u64 - v883 = lt u64 3, v882 - jmpif v883 then: b39, else: b40 - b39(): - v884 = array_get v0, index Field 3 - v885 = load v813 - v886 = div v884, Field 2⁴ - v887 = cast v884 as u4 - v888 = array_set v885, index Field 5, value v887 - v889 = and v884, u8 15 - v890 = truncate v889 to 4 bits, max_bit_size: 8 - v891 = cast v890 as u4 - v892 = array_set v888, index Field 6, value v891 - store v892 at v813 - jmp b40() - b40(): - v893 = truncate v1 to 64 bits, max_bit_size: 254 - v894 = cast v893 as u64 - v895 = lt u64 4, v894 - jmpif v895 then: b44, else: b45 - b44(): - v896 = array_get v0, index Field 4 - v897 = load v813 - v898 = div v896, Field 2⁴ - v899 = cast v896 as u4 - v900 = array_set v897, index Field 7, value v899 - v901 = and v896, u8 15 - v902 = truncate v901 to 4 bits, max_bit_size: 8 - v903 = cast v902 as u4 - v904 = array_set v900, index Field 8, value v903 - store v904 at v813 - jmp b45() - b45(): - jmp b6() - b6(): - v905 = load v813 - v906 = mul Field 2, v1 - v907 = cast v819 as Field - v908 = add v906, v907 - v909 = sub v908, Field 2 - inc_rc v905 - inc_rc v905 - inc_rc v905 - v910 = eq v909, Field 5 - constrain v909 == Field 5 - v911 = array_get v905, index Field 0 - v912 = array_get v905, index Field 1 - v913 = array_get v905, index Field 2 - v914 = array_get v905, index Field 3 - v915 = array_get v905, index Field 4 - v916 = allocate - v917 = eq v911, u4 15 - v919 = eq v912, u4 1 - v921 = mul v917, v919 - v922 = eq v913, u4 12 - v924 = mul v921, v922 - v925 = eq v914, u4 11 - v927 = mul v924, v925 - v928 = eq v915, u4 8 - v930 = mul v927, v928 - store v930 at v916 - constrain v930 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v936 = allocate - range_check u8 148 to 8 bits - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - store [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v936 - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v1067 = allocate - store u1 1 at v1067 - v1133 = allocate - store u64 1 at v1133 - v1134 = allocate - store u64 2⁴ at v1134 - v1135 = allocate - store u64 1 at v1135 - v1136 = allocate - store u64 2⁴ at v1136 - return - b2(): - v820 = truncate v1 to 64 bits, max_bit_size: 254 - v821 = cast v820 as u64 - v822 = sub v821, u64 1 - range_check v822 to 64 bits - v823 = lt u64 0, v822 - jmpif v823 then: b51, else: b52 - b51(): - v824 = array_get v0, index u64 1 - v826 = div v824, Field 2⁴ - v827 = cast v824 as u4 - v830 = and v824, u8 15 - v831 = truncate v830 to 4 bits, max_bit_size: 8 - v832 = cast v831 as u4 - store [v827, v832, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 - jmp b52() - b52(): - v836 = truncate v1 to 64 bits, max_bit_size: 254 - v837 = cast v836 as u64 - v838 = sub v837, u64 1 - range_check v838 to 64 bits - v839 = lt u64 1, v838 - jmpif v839 then: b56, else: b57 - b56(): - v840 = array_get v0, index u64 2 - v841 = load v813 - v842 = div v840, Field 2⁴ - v843 = cast v840 as u4 - v844 = array_set v841, index u64 2, value v843 - v845 = and v840, u8 15 - v846 = truncate v845 to 4 bits, max_bit_size: 8 - v847 = cast v846 as u4 - v848 = array_set v844, index u64 3, value v847 - store v848 at v813 - jmp b57() - b57(): - jmp b6() -} - -After Flattening: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v808 = truncate v1 to 64 bits, max_bit_size: 254 - v809 = cast v808 as u64 - inc_rc v0 - v810 = lt u64 5, v809 - v811 = not v810 - constrain v810 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v813 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 - v815 = array_get v0, index Field 0 - v816 = div v815, Field 2⁴ - v817 = cast v815 as u4 - v818 = truncate v817 to 1 bits, max_bit_size: 4 - v819 = cast v818 as u1 - enable_side_effects v819 - v1139 = array_get v0, index Field 0 - v1140 = and v1139, u8 15 - v1141 = truncate v1140 to 4 bits, max_bit_size: 8 - v1142 = cast v1141 as u4 - v1144 = load v813 - store [v1142, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 - inc_rc v0 - v1145 = truncate v1 to 64 bits, max_bit_size: 254 - v1146 = cast v1145 as u64 - v1147 = lt u64 1, v1146 - v1149 = mul v819, v1147 - enable_side_effects v1149 - v1150 = array_get v0, index Field 1 - v1151 = div v1150, Field 2⁴ - v1152 = cast v1150 as u4 - v1153 = and v1150, u8 15 - v1154 = truncate v1153 to 4 bits, max_bit_size: 8 - v1155 = cast v1154 as u4 - v1157 = load v813 - store [v1142, v1152, v1155, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 - v1158 = not v1147 - store v1157 at v813 - enable_side_effects v819 - v1159 = array_get v1157, index Field 0 - v1160 = cast v1147 as u4 - v1161 = cast v1158 as u4 - v1162 = mul v1160, v1142 - v1163 = mul v1161, v1159 - v1164 = add v1162, v1163 - v1165 = array_get v1157, index Field 1 - v1166 = cast v1147 as u4 - v1167 = cast v1158 as u4 - v1168 = mul v1166, v1152 - v1169 = mul v1167, v1165 - v1170 = add v1168, v1169 - v1171 = array_get v1157, index Field 2 - v1172 = cast v1147 as u4 - v1173 = cast v1158 as u4 - v1174 = mul v1172, v1155 - v1175 = mul v1173, v1171 - v1176 = add v1174, v1175 - v1177 = array_get v1157, index Field 3 - v1178 = cast v1147 as u4 - v1179 = cast v1158 as u4 - v1180 = mul v1179, v1177 - v1181 = array_get v1157, index Field 4 - v1182 = cast v1147 as u4 - v1183 = cast v1158 as u4 - v1184 = mul v1183, v1181 - v1185 = array_get v1157, index Field 5 - v1186 = cast v1147 as u4 - v1187 = cast v1158 as u4 - v1188 = mul v1187, v1185 - v1189 = array_get v1157, index Field 6 - v1190 = cast v1147 as u4 - v1191 = cast v1158 as u4 - v1192 = mul v1191, v1189 - v1193 = array_get v1157, index Field 7 - v1194 = cast v1147 as u4 - v1195 = cast v1158 as u4 - v1196 = mul v1195, v1193 - v1197 = array_get v1157, index Field 8 - v1198 = cast v1147 as u4 - v1199 = cast v1158 as u4 - v1200 = mul v1199, v1197 - v1201 = array_get v1157, index Field 9 - v1202 = cast v1147 as u4 - v1203 = cast v1158 as u4 - v1204 = mul v1203, v1201 - v1205 = array_get v1157, index Field 10 - v1206 = cast v1147 as u4 - v1207 = cast v1158 as u4 - v1208 = mul v1207, v1205 - v1209 = array_get v1157, index Field 11 - v1210 = cast v1147 as u4 - v1211 = cast v1158 as u4 - v1212 = mul v1211, v1209 - v1213 = array_get v1157, index Field 12 - v1214 = cast v1147 as u4 - v1215 = cast v1158 as u4 - v1216 = mul v1215, v1213 - v1217 = array_get v1157, index Field 13 - v1218 = cast v1147 as u4 - v1219 = cast v1158 as u4 - v1220 = mul v1219, v1217 - v1221 = array_get v1157, index Field 14 - v1222 = cast v1147 as u4 - v1223 = cast v1158 as u4 - v1224 = mul v1223, v1221 - v1225 = array_get v1157, index Field 15 - v1226 = cast v1147 as u4 - v1227 = cast v1158 as u4 - v1228 = mul v1227, v1225 - store [v1164, v1170, v1176, v1180, v1184, v1188, v1192, v1196, v1200, v1204, v1208, v1212, v1216, v1220, v1224, v1228] at v813 - v1230 = truncate v1 to 64 bits, max_bit_size: 254 - v1231 = cast v1230 as u64 - v1232 = lt u64 2, v1231 - v1233 = mul v819, v1232 - enable_side_effects v1233 - v1234 = array_get v0, index Field 2 - v1235 = load v813 - v1236 = div v1234, Field 2⁴ - v1237 = cast v1234 as u4 - v1238 = array_set v1235, index Field 3, value v1237 - v1239 = and v1234, u8 15 - v1240 = truncate v1239 to 4 bits, max_bit_size: 8 - v1241 = cast v1240 as u4 - v1242 = array_set v1238, index Field 4, value v1241 - v1243 = load v813 - store v1242 at v813 - v1244 = not v1232 - store v1243 at v813 - enable_side_effects v819 - v1245 = array_get v1242, index Field 0 - v1246 = array_get v1243, index Field 0 - v1247 = cast v1232 as u4 - v1248 = cast v1244 as u4 - v1249 = mul v1247, v1245 - v1250 = mul v1248, v1246 - v1251 = add v1249, v1250 - v1252 = array_get v1242, index Field 1 - v1253 = array_get v1243, index Field 1 - v1254 = cast v1232 as u4 - v1255 = cast v1244 as u4 - v1256 = mul v1254, v1252 - v1257 = mul v1255, v1253 - v1258 = add v1256, v1257 - v1259 = array_get v1242, index Field 2 - v1260 = array_get v1243, index Field 2 - v1261 = cast v1232 as u4 - v1262 = cast v1244 as u4 - v1263 = mul v1261, v1259 - v1264 = mul v1262, v1260 - v1265 = add v1263, v1264 - v1266 = array_get v1242, index Field 3 - v1267 = array_get v1243, index Field 3 - v1268 = cast v1232 as u4 - v1269 = cast v1244 as u4 - v1270 = mul v1268, v1266 - v1271 = mul v1269, v1267 - v1272 = add v1270, v1271 - v1273 = array_get v1242, index Field 4 - v1274 = array_get v1243, index Field 4 - v1275 = cast v1232 as u4 - v1276 = cast v1244 as u4 - v1277 = mul v1275, v1273 - v1278 = mul v1276, v1274 - v1279 = add v1277, v1278 - v1280 = array_get v1242, index Field 5 - v1281 = array_get v1243, index Field 5 - v1282 = cast v1232 as u4 - v1283 = cast v1244 as u4 - v1284 = mul v1282, v1280 - v1285 = mul v1283, v1281 - v1286 = add v1284, v1285 - v1287 = array_get v1242, index Field 6 - v1288 = array_get v1243, index Field 6 - v1289 = cast v1232 as u4 - v1290 = cast v1244 as u4 - v1291 = mul v1289, v1287 - v1292 = mul v1290, v1288 - v1293 = add v1291, v1292 - v1294 = array_get v1242, index Field 7 - v1295 = array_get v1243, index Field 7 - v1296 = cast v1232 as u4 - v1297 = cast v1244 as u4 - v1298 = mul v1296, v1294 - v1299 = mul v1297, v1295 - v1300 = add v1298, v1299 - v1301 = array_get v1242, index Field 8 - v1302 = array_get v1243, index Field 8 - v1303 = cast v1232 as u4 - v1304 = cast v1244 as u4 - v1305 = mul v1303, v1301 - v1306 = mul v1304, v1302 - v1307 = add v1305, v1306 - v1308 = array_get v1242, index Field 9 - v1309 = array_get v1243, index Field 9 - v1310 = cast v1232 as u4 - v1311 = cast v1244 as u4 - v1312 = mul v1310, v1308 - v1313 = mul v1311, v1309 - v1314 = add v1312, v1313 - v1315 = array_get v1242, index Field 10 - v1316 = array_get v1243, index Field 10 - v1317 = cast v1232 as u4 - v1318 = cast v1244 as u4 - v1319 = mul v1317, v1315 - v1320 = mul v1318, v1316 - v1321 = add v1319, v1320 - v1322 = array_get v1242, index Field 11 - v1323 = array_get v1243, index Field 11 - v1324 = cast v1232 as u4 - v1325 = cast v1244 as u4 - v1326 = mul v1324, v1322 - v1327 = mul v1325, v1323 - v1328 = add v1326, v1327 - v1329 = array_get v1242, index Field 12 - v1330 = array_get v1243, index Field 12 - v1331 = cast v1232 as u4 - v1332 = cast v1244 as u4 - v1333 = mul v1331, v1329 - v1334 = mul v1332, v1330 - v1335 = add v1333, v1334 - v1336 = array_get v1242, index Field 13 - v1337 = array_get v1243, index Field 13 - v1338 = cast v1232 as u4 - v1339 = cast v1244 as u4 - v1340 = mul v1338, v1336 - v1341 = mul v1339, v1337 - v1342 = add v1340, v1341 - v1343 = array_get v1242, index Field 14 - v1344 = array_get v1243, index Field 14 - v1345 = cast v1232 as u4 - v1346 = cast v1244 as u4 - v1347 = mul v1345, v1343 - v1348 = mul v1346, v1344 - v1349 = add v1347, v1348 - v1350 = array_get v1242, index Field 15 - v1351 = array_get v1243, index Field 15 - v1352 = cast v1232 as u4 - v1353 = cast v1244 as u4 - v1354 = mul v1352, v1350 - v1355 = mul v1353, v1351 - v1356 = add v1354, v1355 - store [v1251, v1258, v1265, v1272, v1279, v1286, v1293, v1300, v1307, v1314, v1321, v1328, v1335, v1342, v1349, v1356] at v813 - v1358 = truncate v1 to 64 bits, max_bit_size: 254 - v1359 = cast v1358 as u64 - v1360 = lt u64 3, v1359 - v1361 = mul v819, v1360 - enable_side_effects v1361 - v1362 = array_get v0, index Field 3 - v1363 = load v813 - v1364 = div v1362, Field 2⁴ - v1365 = cast v1362 as u4 - v1366 = array_set v1363, index Field 5, value v1365 - v1367 = and v1362, u8 15 - v1368 = truncate v1367 to 4 bits, max_bit_size: 8 - v1369 = cast v1368 as u4 - v1370 = array_set v1366, index Field 6, value v1369 - v1371 = load v813 - store v1370 at v813 - v1372 = not v1360 - store v1371 at v813 - enable_side_effects v819 - v1373 = array_get v1370, index Field 0 - v1374 = array_get v1371, index Field 0 - v1375 = cast v1360 as u4 - v1376 = cast v1372 as u4 - v1377 = mul v1375, v1373 - v1378 = mul v1376, v1374 - v1379 = add v1377, v1378 - v1380 = array_get v1370, index Field 1 - v1381 = array_get v1371, index Field 1 - v1382 = cast v1360 as u4 - v1383 = cast v1372 as u4 - v1384 = mul v1382, v1380 - v1385 = mul v1383, v1381 - v1386 = add v1384, v1385 - v1387 = array_get v1370, index Field 2 - v1388 = array_get v1371, index Field 2 - v1389 = cast v1360 as u4 - v1390 = cast v1372 as u4 - v1391 = mul v1389, v1387 - v1392 = mul v1390, v1388 - v1393 = add v1391, v1392 - v1394 = array_get v1370, index Field 3 - v1395 = array_get v1371, index Field 3 - v1396 = cast v1360 as u4 - v1397 = cast v1372 as u4 - v1398 = mul v1396, v1394 - v1399 = mul v1397, v1395 - v1400 = add v1398, v1399 - v1401 = array_get v1370, index Field 4 - v1402 = array_get v1371, index Field 4 - v1403 = cast v1360 as u4 - v1404 = cast v1372 as u4 - v1405 = mul v1403, v1401 - v1406 = mul v1404, v1402 - v1407 = add v1405, v1406 - v1408 = array_get v1370, index Field 5 - v1409 = array_get v1371, index Field 5 - v1410 = cast v1360 as u4 - v1411 = cast v1372 as u4 - v1412 = mul v1410, v1408 - v1413 = mul v1411, v1409 - v1414 = add v1412, v1413 - v1415 = array_get v1370, index Field 6 - v1416 = array_get v1371, index Field 6 - v1417 = cast v1360 as u4 - v1418 = cast v1372 as u4 - v1419 = mul v1417, v1415 - v1420 = mul v1418, v1416 - v1421 = add v1419, v1420 - v1422 = array_get v1370, index Field 7 - v1423 = array_get v1371, index Field 7 - v1424 = cast v1360 as u4 - v1425 = cast v1372 as u4 - v1426 = mul v1424, v1422 - v1427 = mul v1425, v1423 - v1428 = add v1426, v1427 - v1429 = array_get v1370, index Field 8 - v1430 = array_get v1371, index Field 8 - v1431 = cast v1360 as u4 - v1432 = cast v1372 as u4 - v1433 = mul v1431, v1429 - v1434 = mul v1432, v1430 - v1435 = add v1433, v1434 - v1436 = array_get v1370, index Field 9 - v1437 = array_get v1371, index Field 9 - v1438 = cast v1360 as u4 - v1439 = cast v1372 as u4 - v1440 = mul v1438, v1436 - v1441 = mul v1439, v1437 - v1442 = add v1440, v1441 - v1443 = array_get v1370, index Field 10 - v1444 = array_get v1371, index Field 10 - v1445 = cast v1360 as u4 - v1446 = cast v1372 as u4 - v1447 = mul v1445, v1443 - v1448 = mul v1446, v1444 - v1449 = add v1447, v1448 - v1450 = array_get v1370, index Field 11 - v1451 = array_get v1371, index Field 11 - v1452 = cast v1360 as u4 - v1453 = cast v1372 as u4 - v1454 = mul v1452, v1450 - v1455 = mul v1453, v1451 - v1456 = add v1454, v1455 - v1457 = array_get v1370, index Field 12 - v1458 = array_get v1371, index Field 12 - v1459 = cast v1360 as u4 - v1460 = cast v1372 as u4 - v1461 = mul v1459, v1457 - v1462 = mul v1460, v1458 - v1463 = add v1461, v1462 - v1464 = array_get v1370, index Field 13 - v1465 = array_get v1371, index Field 13 - v1466 = cast v1360 as u4 - v1467 = cast v1372 as u4 - v1468 = mul v1466, v1464 - v1469 = mul v1467, v1465 - v1470 = add v1468, v1469 - v1471 = array_get v1370, index Field 14 - v1472 = array_get v1371, index Field 14 - v1473 = cast v1360 as u4 - v1474 = cast v1372 as u4 - v1475 = mul v1473, v1471 - v1476 = mul v1474, v1472 - v1477 = add v1475, v1476 - v1478 = array_get v1370, index Field 15 - v1479 = array_get v1371, index Field 15 - v1480 = cast v1360 as u4 - v1481 = cast v1372 as u4 - v1482 = mul v1480, v1478 - v1483 = mul v1481, v1479 - v1484 = add v1482, v1483 - store [v1379, v1386, v1393, v1400, v1407, v1414, v1421, v1428, v1435, v1442, v1449, v1456, v1463, v1470, v1477, v1484] at v813 - v1486 = truncate v1 to 64 bits, max_bit_size: 254 - v1487 = cast v1486 as u64 - v1488 = lt u64 4, v1487 - v1489 = mul v819, v1488 - enable_side_effects v1489 - v1490 = array_get v0, index Field 4 - v1491 = load v813 - v1492 = div v1490, Field 2⁴ - v1493 = cast v1490 as u4 - v1494 = array_set v1491, index Field 7, value v1493 - v1495 = and v1490, u8 15 - v1496 = truncate v1495 to 4 bits, max_bit_size: 8 - v1497 = cast v1496 as u4 - v1498 = array_set v1494, index Field 8, value v1497 - v1499 = load v813 - store v1498 at v813 - v1500 = not v1488 - store v1499 at v813 - enable_side_effects v819 - v1501 = array_get v1498, index Field 0 - v1502 = array_get v1499, index Field 0 - v1503 = cast v1488 as u4 - v1504 = cast v1500 as u4 - v1505 = mul v1503, v1501 - v1506 = mul v1504, v1502 - v1507 = add v1505, v1506 - v1508 = array_get v1498, index Field 1 - v1509 = array_get v1499, index Field 1 - v1510 = cast v1488 as u4 - v1511 = cast v1500 as u4 - v1512 = mul v1510, v1508 - v1513 = mul v1511, v1509 - v1514 = add v1512, v1513 - v1515 = array_get v1498, index Field 2 - v1516 = array_get v1499, index Field 2 - v1517 = cast v1488 as u4 - v1518 = cast v1500 as u4 - v1519 = mul v1517, v1515 - v1520 = mul v1518, v1516 - v1521 = add v1519, v1520 - v1522 = array_get v1498, index Field 3 - v1523 = array_get v1499, index Field 3 - v1524 = cast v1488 as u4 - v1525 = cast v1500 as u4 - v1526 = mul v1524, v1522 - v1527 = mul v1525, v1523 - v1528 = add v1526, v1527 - v1529 = array_get v1498, index Field 4 - v1530 = array_get v1499, index Field 4 - v1531 = cast v1488 as u4 - v1532 = cast v1500 as u4 - v1533 = mul v1531, v1529 - v1534 = mul v1532, v1530 - v1535 = add v1533, v1534 - v1536 = array_get v1498, index Field 5 - v1537 = array_get v1499, index Field 5 - v1538 = cast v1488 as u4 - v1539 = cast v1500 as u4 - v1540 = mul v1538, v1536 - v1541 = mul v1539, v1537 - v1542 = add v1540, v1541 - v1543 = array_get v1498, index Field 6 - v1544 = array_get v1499, index Field 6 - v1545 = cast v1488 as u4 - v1546 = cast v1500 as u4 - v1547 = mul v1545, v1543 - v1548 = mul v1546, v1544 - v1549 = add v1547, v1548 - v1550 = array_get v1498, index Field 7 - v1551 = array_get v1499, index Field 7 - v1552 = cast v1488 as u4 - v1553 = cast v1500 as u4 - v1554 = mul v1552, v1550 - v1555 = mul v1553, v1551 - v1556 = add v1554, v1555 - v1557 = array_get v1498, index Field 8 - v1558 = array_get v1499, index Field 8 - v1559 = cast v1488 as u4 - v1560 = cast v1500 as u4 - v1561 = mul v1559, v1557 - v1562 = mul v1560, v1558 - v1563 = add v1561, v1562 - v1564 = array_get v1498, index Field 9 - v1565 = array_get v1499, index Field 9 - v1566 = cast v1488 as u4 - v1567 = cast v1500 as u4 - v1568 = mul v1566, v1564 - v1569 = mul v1567, v1565 - v1570 = add v1568, v1569 - v1571 = array_get v1498, index Field 10 - v1572 = array_get v1499, index Field 10 - v1573 = cast v1488 as u4 - v1574 = cast v1500 as u4 - v1575 = mul v1573, v1571 - v1576 = mul v1574, v1572 - v1577 = add v1575, v1576 - v1578 = array_get v1498, index Field 11 - v1579 = array_get v1499, index Field 11 - v1580 = cast v1488 as u4 - v1581 = cast v1500 as u4 - v1582 = mul v1580, v1578 - v1583 = mul v1581, v1579 - v1584 = add v1582, v1583 - v1585 = array_get v1498, index Field 12 - v1586 = array_get v1499, index Field 12 - v1587 = cast v1488 as u4 - v1588 = cast v1500 as u4 - v1589 = mul v1587, v1585 - v1590 = mul v1588, v1586 - v1591 = add v1589, v1590 - v1592 = array_get v1498, index Field 13 - v1593 = array_get v1499, index Field 13 - v1594 = cast v1488 as u4 - v1595 = cast v1500 as u4 - v1596 = mul v1594, v1592 - v1597 = mul v1595, v1593 - v1598 = add v1596, v1597 - v1599 = array_get v1498, index Field 14 - v1600 = array_get v1499, index Field 14 - v1601 = cast v1488 as u4 - v1602 = cast v1500 as u4 - v1603 = mul v1601, v1599 - v1604 = mul v1602, v1600 - v1605 = add v1603, v1604 - v1606 = array_get v1498, index Field 15 - v1607 = array_get v1499, index Field 15 - v1608 = cast v1488 as u4 - v1609 = cast v1500 as u4 - v1610 = mul v1608, v1606 - v1611 = mul v1609, v1607 - v1612 = add v1610, v1611 - store [v1507, v1514, v1521, v1528, v1535, v1542, v1549, v1556, v1563, v1570, v1577, v1584, v1591, v1598, v1605, v1612] at v813 - v1614 = not v819 - store v1144 at v813 - enable_side_effects v1614 - v1615 = truncate v1 to 64 bits, max_bit_size: 254 - v1616 = cast v1615 as u64 - v1617 = sub v1616, u64 1 - v1618 = cast v1614 as u64 - v1619 = mul v1617, v1618 - range_check v1619 to 64 bits - v1620 = lt u64 0, v1617 - v1621 = mul v1614, v1620 - enable_side_effects v1621 - v1622 = array_get v0, index u64 1 - v1623 = div v1622, Field 2⁴ - v1624 = cast v1622 as u4 - v1625 = and v1622, u8 15 - v1626 = truncate v1625 to 4 bits, max_bit_size: 8 - v1627 = cast v1626 as u4 - v1629 = load v813 - store [v1624, v1627, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v813 - v1630 = not v1620 - store v1629 at v813 - enable_side_effects v1614 - v1631 = array_get v1629, index Field 0 - v1632 = cast v1620 as u4 - v1633 = cast v1630 as u4 - v1634 = mul v1632, v1624 - v1635 = mul v1633, v1631 - v1636 = add v1634, v1635 - v1637 = array_get v1629, index Field 1 - v1638 = cast v1620 as u4 - v1639 = cast v1630 as u4 - v1640 = mul v1638, v1627 - v1641 = mul v1639, v1637 - v1642 = add v1640, v1641 - v1643 = array_get v1629, index Field 2 - v1644 = cast v1620 as u4 - v1645 = cast v1630 as u4 - v1646 = mul v1645, v1643 - v1647 = array_get v1629, index Field 3 - v1648 = cast v1620 as u4 - v1649 = cast v1630 as u4 - v1650 = mul v1649, v1647 - v1651 = array_get v1629, index Field 4 - v1652 = cast v1620 as u4 - v1653 = cast v1630 as u4 - v1654 = mul v1653, v1651 - v1655 = array_get v1629, index Field 5 - v1656 = cast v1620 as u4 - v1657 = cast v1630 as u4 - v1658 = mul v1657, v1655 - v1659 = array_get v1629, index Field 6 - v1660 = cast v1620 as u4 - v1661 = cast v1630 as u4 - v1662 = mul v1661, v1659 - v1663 = array_get v1629, index Field 7 - v1664 = cast v1620 as u4 - v1665 = cast v1630 as u4 - v1666 = mul v1665, v1663 - v1667 = array_get v1629, index Field 8 - v1668 = cast v1620 as u4 - v1669 = cast v1630 as u4 - v1670 = mul v1669, v1667 - v1671 = array_get v1629, index Field 9 - v1672 = cast v1620 as u4 - v1673 = cast v1630 as u4 - v1674 = mul v1673, v1671 - v1675 = array_get v1629, index Field 10 - v1676 = cast v1620 as u4 - v1677 = cast v1630 as u4 - v1678 = mul v1677, v1675 - v1679 = array_get v1629, index Field 11 - v1680 = cast v1620 as u4 - v1681 = cast v1630 as u4 - v1682 = mul v1681, v1679 - v1683 = array_get v1629, index Field 12 - v1684 = cast v1620 as u4 - v1685 = cast v1630 as u4 - v1686 = mul v1685, v1683 - v1687 = array_get v1629, index Field 13 - v1688 = cast v1620 as u4 - v1689 = cast v1630 as u4 - v1690 = mul v1689, v1687 - v1691 = array_get v1629, index Field 14 - v1692 = cast v1620 as u4 - v1693 = cast v1630 as u4 - v1694 = mul v1693, v1691 - v1695 = array_get v1629, index Field 15 - v1696 = cast v1620 as u4 - v1697 = cast v1630 as u4 - v1698 = mul v1697, v1695 - store [v1636, v1642, v1646, v1650, v1654, v1658, v1662, v1666, v1670, v1674, v1678, v1682, v1686, v1690, v1694, v1698] at v813 - v1700 = truncate v1 to 64 bits, max_bit_size: 254 - v1701 = cast v1700 as u64 - v1702 = sub v1701, u64 1 - v1703 = cast v1614 as u64 - v1704 = mul v1702, v1703 - range_check v1704 to 64 bits - v1705 = lt u64 1, v1702 - v1706 = mul v1614, v1705 - enable_side_effects v1706 - v1707 = array_get v0, index u64 2 - v1708 = load v813 - v1709 = div v1707, Field 2⁴ - v1710 = cast v1707 as u4 - v1711 = array_set v1708, index u64 2, value v1710 - v1712 = and v1707, u8 15 - v1713 = truncate v1712 to 4 bits, max_bit_size: 8 - v1714 = cast v1713 as u4 - v1715 = array_set v1711, index u64 3, value v1714 - v1716 = load v813 - store v1715 at v813 - v1717 = not v1705 - store v1716 at v813 - enable_side_effects v1614 - v1718 = array_get v1715, index Field 0 - v1719 = array_get v1716, index Field 0 - v1720 = cast v1705 as u4 - v1721 = cast v1717 as u4 - v1722 = mul v1720, v1718 - v1723 = mul v1721, v1719 - v1724 = add v1722, v1723 - v1725 = array_get v1715, index Field 1 - v1726 = array_get v1716, index Field 1 - v1727 = cast v1705 as u4 - v1728 = cast v1717 as u4 - v1729 = mul v1727, v1725 - v1730 = mul v1728, v1726 - v1731 = add v1729, v1730 - v1732 = array_get v1715, index Field 2 - v1733 = array_get v1716, index Field 2 - v1734 = cast v1705 as u4 - v1735 = cast v1717 as u4 - v1736 = mul v1734, v1732 - v1737 = mul v1735, v1733 - v1738 = add v1736, v1737 - v1739 = array_get v1715, index Field 3 - v1740 = array_get v1716, index Field 3 - v1741 = cast v1705 as u4 - v1742 = cast v1717 as u4 - v1743 = mul v1741, v1739 - v1744 = mul v1742, v1740 - v1745 = add v1743, v1744 - v1746 = array_get v1715, index Field 4 - v1747 = array_get v1716, index Field 4 - v1748 = cast v1705 as u4 - v1749 = cast v1717 as u4 - v1750 = mul v1748, v1746 - v1751 = mul v1749, v1747 - v1752 = add v1750, v1751 - v1753 = array_get v1715, index Field 5 - v1754 = array_get v1716, index Field 5 - v1755 = cast v1705 as u4 - v1756 = cast v1717 as u4 - v1757 = mul v1755, v1753 - v1758 = mul v1756, v1754 - v1759 = add v1757, v1758 - v1760 = array_get v1715, index Field 6 - v1761 = array_get v1716, index Field 6 - v1762 = cast v1705 as u4 - v1763 = cast v1717 as u4 - v1764 = mul v1762, v1760 - v1765 = mul v1763, v1761 - v1766 = add v1764, v1765 - v1767 = array_get v1715, index Field 7 - v1768 = array_get v1716, index Field 7 - v1769 = cast v1705 as u4 - v1770 = cast v1717 as u4 - v1771 = mul v1769, v1767 - v1772 = mul v1770, v1768 - v1773 = add v1771, v1772 - v1774 = array_get v1715, index Field 8 - v1775 = array_get v1716, index Field 8 - v1776 = cast v1705 as u4 - v1777 = cast v1717 as u4 - v1778 = mul v1776, v1774 - v1779 = mul v1777, v1775 - v1780 = add v1778, v1779 - v1781 = array_get v1715, index Field 9 - v1782 = array_get v1716, index Field 9 - v1783 = cast v1705 as u4 - v1784 = cast v1717 as u4 - v1785 = mul v1783, v1781 - v1786 = mul v1784, v1782 - v1787 = add v1785, v1786 - v1788 = array_get v1715, index Field 10 - v1789 = array_get v1716, index Field 10 - v1790 = cast v1705 as u4 - v1791 = cast v1717 as u4 - v1792 = mul v1790, v1788 - v1793 = mul v1791, v1789 - v1794 = add v1792, v1793 - v1795 = array_get v1715, index Field 11 - v1796 = array_get v1716, index Field 11 - v1797 = cast v1705 as u4 - v1798 = cast v1717 as u4 - v1799 = mul v1797, v1795 - v1800 = mul v1798, v1796 - v1801 = add v1799, v1800 - v1802 = array_get v1715, index Field 12 - v1803 = array_get v1716, index Field 12 - v1804 = cast v1705 as u4 - v1805 = cast v1717 as u4 - v1806 = mul v1804, v1802 - v1807 = mul v1805, v1803 - v1808 = add v1806, v1807 - v1809 = array_get v1715, index Field 13 - v1810 = array_get v1716, index Field 13 - v1811 = cast v1705 as u4 - v1812 = cast v1717 as u4 - v1813 = mul v1811, v1809 - v1814 = mul v1812, v1810 - v1815 = add v1813, v1814 - v1816 = array_get v1715, index Field 14 - v1817 = array_get v1716, index Field 14 - v1818 = cast v1705 as u4 - v1819 = cast v1717 as u4 - v1820 = mul v1818, v1816 - v1821 = mul v1819, v1817 - v1822 = add v1820, v1821 - v1823 = array_get v1715, index Field 15 - v1824 = array_get v1716, index Field 15 - v1825 = cast v1705 as u4 - v1826 = cast v1717 as u4 - v1827 = mul v1825, v1823 - v1828 = mul v1826, v1824 - v1829 = add v1827, v1828 - store [v1724, v1731, v1738, v1745, v1752, v1759, v1766, v1773, v1780, v1787, v1794, v1801, v1808, v1815, v1822, v1829] at v813 - enable_side_effects u1 1 - v1831 = cast v819 as u4 - v1832 = cast v1614 as u4 - v1833 = mul v1831, v1507 - v1834 = mul v1832, v1724 - v1835 = add v1833, v1834 - v1836 = cast v819 as u4 - v1837 = cast v1614 as u4 - v1838 = mul v1836, v1514 - v1839 = mul v1837, v1731 - v1840 = add v1838, v1839 - v1841 = cast v819 as u4 - v1842 = cast v1614 as u4 - v1843 = mul v1841, v1521 - v1844 = mul v1842, v1738 - v1845 = add v1843, v1844 - v1846 = cast v819 as u4 - v1847 = cast v1614 as u4 - v1848 = mul v1846, v1528 - v1849 = mul v1847, v1745 - v1850 = add v1848, v1849 - v1851 = cast v819 as u4 - v1852 = cast v1614 as u4 - v1853 = mul v1851, v1535 - v1854 = mul v1852, v1752 - v1855 = add v1853, v1854 - v1856 = cast v819 as u4 - v1857 = cast v1614 as u4 - v1858 = mul v1856, v1542 - v1859 = mul v1857, v1759 - v1860 = add v1858, v1859 - v1861 = cast v819 as u4 - v1862 = cast v1614 as u4 - v1863 = mul v1861, v1549 - v1864 = mul v1862, v1766 - v1865 = add v1863, v1864 - v1866 = cast v819 as u4 - v1867 = cast v1614 as u4 - v1868 = mul v1866, v1556 - v1869 = mul v1867, v1773 - v1870 = add v1868, v1869 - v1871 = cast v819 as u4 - v1872 = cast v1614 as u4 - v1873 = mul v1871, v1563 - v1874 = mul v1872, v1780 - v1875 = add v1873, v1874 - v1876 = cast v819 as u4 - v1877 = cast v1614 as u4 - v1878 = mul v1876, v1570 - v1879 = mul v1877, v1787 - v1880 = add v1878, v1879 - v1881 = cast v819 as u4 - v1882 = cast v1614 as u4 - v1883 = mul v1881, v1577 - v1884 = mul v1882, v1794 - v1885 = add v1883, v1884 - v1886 = cast v819 as u4 - v1887 = cast v1614 as u4 - v1888 = mul v1886, v1584 - v1889 = mul v1887, v1801 - v1890 = add v1888, v1889 - v1891 = cast v819 as u4 - v1892 = cast v1614 as u4 - v1893 = mul v1891, v1591 - v1894 = mul v1892, v1808 - v1895 = add v1893, v1894 - v1896 = cast v819 as u4 - v1897 = cast v1614 as u4 - v1898 = mul v1896, v1598 - v1899 = mul v1897, v1815 - v1900 = add v1898, v1899 - v1901 = cast v819 as u4 - v1902 = cast v1614 as u4 - v1903 = mul v1901, v1605 - v1904 = mul v1902, v1822 - v1905 = add v1903, v1904 - v1906 = cast v819 as u4 - v1907 = cast v1614 as u4 - v1908 = mul v1906, v1612 - v1909 = mul v1907, v1829 - v1910 = add v1908, v1909 - store [v1835, v1840, v1845, v1850, v1855, v1860, v1865, v1870, v1875, v1880, v1885, v1890, v1895, v1900, v1905, v1910] at v813 - v1912 = load v813 - v1913 = mul Field 2, v1 - v1914 = cast v819 as Field - v1915 = add v1913, v1914 - v1916 = sub v1915, Field 2 - inc_rc v1912 - inc_rc v1912 - inc_rc v1912 - v1917 = eq v1916, Field 5 - constrain v1916 == Field 5 - v1918 = array_get v1912, index Field 0 - v1919 = array_get v1912, index Field 1 - v1920 = array_get v1912, index Field 2 - v1921 = array_get v1912, index Field 3 - v1922 = array_get v1912, index Field 4 - v1923 = allocate - v1924 = eq v1918, u4 15 - v1925 = eq v1919, u4 1 - v1926 = mul v1924, v1925 - v1927 = eq v1920, u4 12 - v1928 = mul v1926, v1927 - v1929 = eq v1921, u4 11 - v1930 = mul v1928, v1929 - v1931 = eq v1922, u4 8 - v1932 = mul v1930, v1931 - store v1932 at v1923 - constrain v1932 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v1937 = allocate - range_check u8 148 to 8 bits - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - store [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v1937 - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v1942 = allocate - store u1 1 at v1942 - v1943 = allocate - store u64 1 at v1943 - v1944 = allocate - store u64 2⁴ at v1944 - v1945 = allocate - store u64 1 at v1945 - v1946 = allocate - store u64 2⁴ at v1946 - return -} - -After Mem2Reg: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v1947 = truncate v1 to 64 bits, max_bit_size: 254 - v1948 = cast v1947 as u64 - inc_rc v0 - v1949 = lt u64 5, v1948 - v1950 = not v1949 - constrain v1949 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v1952 = allocate - v1954 = array_get v0, index Field 0 - v1955 = div v1954, Field 2⁴ - v1956 = cast v1954 as u4 - v1957 = truncate v1956 to 1 bits, max_bit_size: 4 - v1958 = cast v1957 as u1 - enable_side_effects v1958 - v1959 = array_get v0, index Field 0 - v1960 = and v1959, u8 15 - v1961 = truncate v1960 to 4 bits, max_bit_size: 8 - v1962 = cast v1961 as u4 - inc_rc v0 - v1965 = truncate v1 to 64 bits, max_bit_size: 254 - v1966 = cast v1965 as u64 - v1967 = lt u64 1, v1966 - v1968 = mul v1958, v1967 - enable_side_effects v1968 - v1969 = array_get v0, index Field 1 - v1970 = div v1969, Field 2⁴ - v1971 = cast v1969 as u4 - v1972 = and v1969, u8 15 - v1973 = truncate v1972 to 4 bits, max_bit_size: 8 - v1974 = cast v1973 as u4 - v1977 = not v1967 - enable_side_effects v1958 - v1980 = cast v1967 as u4 - v1981 = cast v1977 as u4 - v1982 = mul v1980, v1962 - v1983 = mul v1981, v1962 - v1984 = add v1982, v1983 - v1986 = cast v1967 as u4 - v1987 = cast v1977 as u4 - v1988 = mul v1986, v1971 - v1990 = cast v1967 as u4 - v1991 = cast v1977 as u4 - v1992 = mul v1990, v1974 - v1994 = cast v1967 as u4 - v1995 = cast v1977 as u4 - v1997 = cast v1967 as u4 - v1998 = cast v1977 as u4 - v2000 = cast v1967 as u4 - v2001 = cast v1977 as u4 - v2003 = cast v1967 as u4 - v2004 = cast v1977 as u4 - v2006 = cast v1967 as u4 - v2007 = cast v1977 as u4 - v2009 = cast v1967 as u4 - v2010 = cast v1977 as u4 - v2012 = cast v1967 as u4 - v2013 = cast v1977 as u4 - v2015 = cast v1967 as u4 - v2016 = cast v1977 as u4 - v2018 = cast v1967 as u4 - v2019 = cast v1977 as u4 - v2021 = cast v1967 as u4 - v2022 = cast v1977 as u4 - v2024 = cast v1967 as u4 - v2025 = cast v1977 as u4 - v2027 = cast v1967 as u4 - v2028 = cast v1977 as u4 - v2030 = cast v1967 as u4 - v2031 = cast v1977 as u4 - v2033 = truncate v1 to 64 bits, max_bit_size: 254 - v2034 = cast v2033 as u64 - v2035 = lt u64 2, v2034 - v2036 = mul v1958, v2035 - enable_side_effects v2036 - v2037 = array_get v0, index Field 2 - v2039 = div v2037, Field 2⁴ - v2040 = cast v2037 as u4 - v2043 = and v2037, u8 15 - v2044 = truncate v2043 to 4 bits, max_bit_size: 8 - v2045 = cast v2044 as u4 - v2050 = not v2035 - enable_side_effects v1958 - v2054 = cast v2035 as u4 - v2055 = cast v2050 as u4 - v2056 = mul v2054, v1984 - v2057 = mul v2055, v1984 - v2058 = add v2056, v2057 - v2061 = cast v2035 as u4 - v2062 = cast v2050 as u4 - v2063 = mul v2061, v1988 - v2064 = mul v2062, v1988 - v2065 = add v2063, v2064 - v2068 = cast v2035 as u4 - v2069 = cast v2050 as u4 - v2070 = mul v2068, v1992 - v2071 = mul v2069, v1992 - v2072 = add v2070, v2071 - v2075 = cast v2035 as u4 - v2076 = cast v2050 as u4 - v2077 = mul v2075, v2040 - v2080 = cast v2035 as u4 - v2081 = cast v2050 as u4 - v2082 = mul v2080, v2045 - v2085 = cast v2035 as u4 - v2086 = cast v2050 as u4 - v2089 = cast v2035 as u4 - v2090 = cast v2050 as u4 - v2093 = cast v2035 as u4 - v2094 = cast v2050 as u4 - v2097 = cast v2035 as u4 - v2098 = cast v2050 as u4 - v2101 = cast v2035 as u4 - v2102 = cast v2050 as u4 - v2105 = cast v2035 as u4 - v2106 = cast v2050 as u4 - v2109 = cast v2035 as u4 - v2110 = cast v2050 as u4 - v2113 = cast v2035 as u4 - v2114 = cast v2050 as u4 - v2117 = cast v2035 as u4 - v2118 = cast v2050 as u4 - v2121 = cast v2035 as u4 - v2122 = cast v2050 as u4 - v2125 = cast v2035 as u4 - v2126 = cast v2050 as u4 - v2128 = truncate v1 to 64 bits, max_bit_size: 254 - v2129 = cast v2128 as u64 - v2130 = lt u64 3, v2129 - v2131 = mul v1958, v2130 - enable_side_effects v2131 - v2132 = array_get v0, index Field 3 - v2134 = div v2132, Field 2⁴ - v2135 = cast v2132 as u4 - v2138 = and v2132, u8 15 - v2139 = truncate v2138 to 4 bits, max_bit_size: 8 - v2140 = cast v2139 as u4 - v2145 = not v2130 - enable_side_effects v1958 - v2149 = cast v2130 as u4 - v2150 = cast v2145 as u4 - v2151 = mul v2149, v2058 - v2152 = mul v2150, v2058 - v2153 = add v2151, v2152 - v2156 = cast v2130 as u4 - v2157 = cast v2145 as u4 - v2158 = mul v2156, v2065 - v2159 = mul v2157, v2065 - v2160 = add v2158, v2159 - v2163 = cast v2130 as u4 - v2164 = cast v2145 as u4 - v2165 = mul v2163, v2072 - v2166 = mul v2164, v2072 - v2167 = add v2165, v2166 - v2170 = cast v2130 as u4 - v2171 = cast v2145 as u4 - v2172 = mul v2170, v2077 - v2173 = mul v2171, v2077 - v2174 = add v2172, v2173 - v2177 = cast v2130 as u4 - v2178 = cast v2145 as u4 - v2179 = mul v2177, v2082 - v2180 = mul v2178, v2082 - v2181 = add v2179, v2180 - v2184 = cast v2130 as u4 - v2185 = cast v2145 as u4 - v2186 = mul v2184, v2135 - v2189 = cast v2130 as u4 - v2190 = cast v2145 as u4 - v2191 = mul v2189, v2140 - v2194 = cast v2130 as u4 - v2195 = cast v2145 as u4 - v2198 = cast v2130 as u4 - v2199 = cast v2145 as u4 - v2202 = cast v2130 as u4 - v2203 = cast v2145 as u4 - v2206 = cast v2130 as u4 - v2207 = cast v2145 as u4 - v2210 = cast v2130 as u4 - v2211 = cast v2145 as u4 - v2214 = cast v2130 as u4 - v2215 = cast v2145 as u4 - v2218 = cast v2130 as u4 - v2219 = cast v2145 as u4 - v2222 = cast v2130 as u4 - v2223 = cast v2145 as u4 - v2226 = cast v2130 as u4 - v2227 = cast v2145 as u4 - v2229 = truncate v1 to 64 bits, max_bit_size: 254 - v2230 = cast v2229 as u64 - v2231 = lt u64 4, v2230 - v2232 = mul v1958, v2231 - enable_side_effects v2232 - v2233 = array_get v0, index Field 4 - v2235 = div v2233, Field 2⁴ - v2236 = cast v2233 as u4 - v2239 = and v2233, u8 15 - v2240 = truncate v2239 to 4 bits, max_bit_size: 8 - v2241 = cast v2240 as u4 - v2246 = not v2231 - enable_side_effects v1958 - v2250 = cast v2231 as u4 - v2251 = cast v2246 as u4 - v2252 = mul v2250, v2153 - v2253 = mul v2251, v2153 - v2254 = add v2252, v2253 - v2257 = cast v2231 as u4 - v2258 = cast v2246 as u4 - v2259 = mul v2257, v2160 - v2260 = mul v2258, v2160 - v2261 = add v2259, v2260 - v2264 = cast v2231 as u4 - v2265 = cast v2246 as u4 - v2266 = mul v2264, v2167 - v2267 = mul v2265, v2167 - v2268 = add v2266, v2267 - v2271 = cast v2231 as u4 - v2272 = cast v2246 as u4 - v2273 = mul v2271, v2174 - v2274 = mul v2272, v2174 - v2275 = add v2273, v2274 - v2278 = cast v2231 as u4 - v2279 = cast v2246 as u4 - v2280 = mul v2278, v2181 - v2281 = mul v2279, v2181 - v2282 = add v2280, v2281 - v2285 = cast v2231 as u4 - v2286 = cast v2246 as u4 - v2287 = mul v2285, v2186 - v2288 = mul v2286, v2186 - v2289 = add v2287, v2288 - v2292 = cast v2231 as u4 - v2293 = cast v2246 as u4 - v2294 = mul v2292, v2191 - v2295 = mul v2293, v2191 - v2296 = add v2294, v2295 - v2299 = cast v2231 as u4 - v2300 = cast v2246 as u4 - v2301 = mul v2299, v2236 - v2304 = cast v2231 as u4 - v2305 = cast v2246 as u4 - v2306 = mul v2304, v2241 - v2309 = cast v2231 as u4 - v2310 = cast v2246 as u4 - v2313 = cast v2231 as u4 - v2314 = cast v2246 as u4 - v2317 = cast v2231 as u4 - v2318 = cast v2246 as u4 - v2321 = cast v2231 as u4 - v2322 = cast v2246 as u4 - v2325 = cast v2231 as u4 - v2326 = cast v2246 as u4 - v2329 = cast v2231 as u4 - v2330 = cast v2246 as u4 - v2333 = cast v2231 as u4 - v2334 = cast v2246 as u4 - v2336 = not v1958 - enable_side_effects v2336 - v2338 = truncate v1 to 64 bits, max_bit_size: 254 - v2339 = cast v2338 as u64 - v2340 = sub v2339, u64 1 - v2341 = cast v2336 as u64 - v2342 = mul v2340, v2341 - range_check v2342 to 64 bits - v2343 = lt u64 0, v2340 - v2344 = mul v2336, v2343 - enable_side_effects v2344 - v2345 = array_get v0, index u64 1 - v2346 = div v2345, Field 2⁴ - v2347 = cast v2345 as u4 - v2348 = and v2345, u8 15 - v2349 = truncate v2348 to 4 bits, max_bit_size: 8 - v2350 = cast v2349 as u4 - v2353 = not v2343 - enable_side_effects v2336 - v2356 = cast v2343 as u4 - v2357 = cast v2353 as u4 - v2358 = mul v2356, v2347 - v2360 = cast v2343 as u4 - v2361 = cast v2353 as u4 - v2362 = mul v2360, v2350 - v2364 = cast v2343 as u4 - v2365 = cast v2353 as u4 - v2367 = cast v2343 as u4 - v2368 = cast v2353 as u4 - v2370 = cast v2343 as u4 - v2371 = cast v2353 as u4 - v2373 = cast v2343 as u4 - v2374 = cast v2353 as u4 - v2376 = cast v2343 as u4 - v2377 = cast v2353 as u4 - v2379 = cast v2343 as u4 - v2380 = cast v2353 as u4 - v2382 = cast v2343 as u4 - v2383 = cast v2353 as u4 - v2385 = cast v2343 as u4 - v2386 = cast v2353 as u4 - v2388 = cast v2343 as u4 - v2389 = cast v2353 as u4 - v2391 = cast v2343 as u4 - v2392 = cast v2353 as u4 - v2394 = cast v2343 as u4 - v2395 = cast v2353 as u4 - v2397 = cast v2343 as u4 - v2398 = cast v2353 as u4 - v2400 = cast v2343 as u4 - v2401 = cast v2353 as u4 - v2403 = cast v2343 as u4 - v2404 = cast v2353 as u4 - v2406 = truncate v1 to 64 bits, max_bit_size: 254 - v2407 = cast v2406 as u64 - v2408 = sub v2407, u64 1 - v2409 = cast v2336 as u64 - v2410 = mul v2408, v2409 - range_check v2410 to 64 bits - v2411 = lt u64 1, v2408 - v2412 = mul v2336, v2411 - enable_side_effects v2412 - v2413 = array_get v0, index u64 2 - v2415 = div v2413, Field 2⁴ - v2416 = cast v2413 as u4 - v2419 = and v2413, u8 15 - v2420 = truncate v2419 to 4 bits, max_bit_size: 8 - v2421 = cast v2420 as u4 - v2426 = not v2411 - enable_side_effects v2336 - v2430 = cast v2411 as u4 - v2431 = cast v2426 as u4 - v2432 = mul v2430, v2358 - v2433 = mul v2431, v2358 - v2434 = add v2432, v2433 - v2437 = cast v2411 as u4 - v2438 = cast v2426 as u4 - v2439 = mul v2437, v2362 - v2440 = mul v2438, v2362 - v2441 = add v2439, v2440 - v2444 = cast v2411 as u4 - v2445 = cast v2426 as u4 - v2446 = mul v2444, v2416 - v2449 = cast v2411 as u4 - v2450 = cast v2426 as u4 - v2451 = mul v2449, v2421 - v2454 = cast v2411 as u4 - v2455 = cast v2426 as u4 - v2458 = cast v2411 as u4 - v2459 = cast v2426 as u4 - v2462 = cast v2411 as u4 - v2463 = cast v2426 as u4 - v2466 = cast v2411 as u4 - v2467 = cast v2426 as u4 - v2470 = cast v2411 as u4 - v2471 = cast v2426 as u4 - v2474 = cast v2411 as u4 - v2475 = cast v2426 as u4 - v2478 = cast v2411 as u4 - v2479 = cast v2426 as u4 - v2482 = cast v2411 as u4 - v2483 = cast v2426 as u4 - v2486 = cast v2411 as u4 - v2487 = cast v2426 as u4 - v2490 = cast v2411 as u4 - v2491 = cast v2426 as u4 - v2494 = cast v2411 as u4 - v2495 = cast v2426 as u4 - v2498 = cast v2411 as u4 - v2499 = cast v2426 as u4 - enable_side_effects u1 1 - v2501 = cast v1958 as u4 - v2502 = cast v2336 as u4 - v2503 = mul v2501, v2254 - v2504 = mul v2502, v2434 - v2505 = add v2503, v2504 - v2506 = cast v1958 as u4 - v2507 = cast v2336 as u4 - v2508 = mul v2506, v2261 - v2509 = mul v2507, v2441 - v2510 = add v2508, v2509 - v2511 = cast v1958 as u4 - v2512 = cast v2336 as u4 - v2513 = mul v2511, v2268 - v2514 = mul v2512, v2446 - v2515 = add v2513, v2514 - v2516 = cast v1958 as u4 - v2517 = cast v2336 as u4 - v2518 = mul v2516, v2275 - v2519 = mul v2517, v2451 - v2520 = add v2518, v2519 - v2521 = cast v1958 as u4 - v2522 = cast v2336 as u4 - v2523 = mul v2521, v2282 - v2524 = cast v1958 as u4 - v2525 = cast v2336 as u4 - v2526 = mul v2524, v2289 - v2527 = cast v1958 as u4 - v2528 = cast v2336 as u4 - v2529 = mul v2527, v2296 - v2530 = cast v1958 as u4 - v2531 = cast v2336 as u4 - v2532 = mul v2530, v2301 - v2533 = cast v1958 as u4 - v2534 = cast v2336 as u4 - v2535 = mul v2533, v2306 - v2536 = cast v1958 as u4 - v2537 = cast v2336 as u4 - v2538 = cast v1958 as u4 - v2539 = cast v2336 as u4 - v2540 = cast v1958 as u4 - v2541 = cast v2336 as u4 - v2542 = cast v1958 as u4 - v2543 = cast v2336 as u4 - v2544 = cast v1958 as u4 - v2545 = cast v2336 as u4 - v2546 = cast v1958 as u4 - v2547 = cast v2336 as u4 - v2548 = cast v1958 as u4 - v2549 = cast v2336 as u4 - v2552 = mul Field 2, v1 - v2553 = cast v1958 as Field - v2554 = add v2552, v2553 - v2555 = sub v2554, Field 2 - inc_rc [v2505, v2510, v2515, v2520, v2523, v2526, v2529, v2532, v2535, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - inc_rc [v2505, v2510, v2515, v2520, v2523, v2526, v2529, v2532, v2535, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - inc_rc [v2505, v2510, v2515, v2520, v2523, v2526, v2529, v2532, v2535, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v2559 = eq v2555, Field 5 - constrain v2555 == Field 5 - v2565 = allocate - v2566 = eq v2505, u4 15 - v2567 = eq v2510, u4 1 - v2568 = mul v2566, v2567 - v2569 = eq v2515, u4 12 - v2570 = mul v2568, v2569 - v2571 = eq v2520, u4 11 - v2572 = mul v2570, v2571 - v2573 = eq v2523, u4 8 - v2574 = mul v2572, v2573 - constrain v2574 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v2579 = allocate - range_check u8 148 to 8 bits - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v2584 = allocate - v2585 = allocate - v2586 = allocate - v2587 = allocate - v2588 = allocate - return -} - -After Constant Folding: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v2589 = truncate v1 to 64 bits, max_bit_size: 254 - v2590 = cast v2589 as u64 - inc_rc v0 - v2591 = lt u64 5, v2590 - v2592 = not v2591 - constrain v2591 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v2593 = allocate - v2594 = array_get v0, index Field 0 - v2595 = div v2594, Field 2⁴ - v2596 = cast v2594 as u4 - v2597 = truncate v2596 to 1 bits, max_bit_size: 4 - v2598 = cast v2597 as u1 - enable_side_effects v2598 - v2599 = and v2594, u8 15 - v2600 = truncate v2599 to 4 bits, max_bit_size: 8 - v2601 = cast v2600 as u4 - inc_rc v0 - v2602 = lt u64 1, v2590 - v2603 = mul v2598, v2602 - enable_side_effects v2603 - v2604 = array_get v0, index Field 1 - v2605 = div v2604, Field 2⁴ - v2606 = cast v2604 as u4 - v2607 = and v2604, u8 15 - v2608 = truncate v2607 to 4 bits, max_bit_size: 8 - v2609 = cast v2608 as u4 - v2610 = not v2602 - enable_side_effects v2598 - v2611 = cast v2602 as u4 - v2612 = cast v2610 as u4 - v2613 = mul v2611, v2601 - v2614 = mul v2612, v2601 - v2615 = add v2613, v2614 - v2616 = mul v2611, v2606 - v2617 = mul v2611, v2609 - v2618 = lt u64 2, v2590 - v2619 = mul v2598, v2618 - enable_side_effects v2619 - v2620 = array_get v0, index Field 2 - v2621 = div v2620, Field 2⁴ - v2622 = cast v2620 as u4 - v2623 = and v2620, u8 15 - v2624 = truncate v2623 to 4 bits, max_bit_size: 8 - v2625 = cast v2624 as u4 - v2626 = not v2618 - enable_side_effects v2598 - v2627 = cast v2618 as u4 - v2628 = cast v2626 as u4 - v2629 = mul v2627, v2615 - v2630 = mul v2628, v2615 - v2631 = add v2629, v2630 - v2632 = mul v2627, v2616 - v2633 = mul v2628, v2616 - v2634 = add v2632, v2633 - v2635 = mul v2627, v2617 - v2636 = mul v2628, v2617 - v2637 = add v2635, v2636 - v2638 = mul v2627, v2622 - v2639 = mul v2627, v2625 - v2640 = lt u64 3, v2590 - v2641 = mul v2598, v2640 - enable_side_effects v2641 - v2642 = array_get v0, index Field 3 - v2643 = div v2642, Field 2⁴ - v2644 = cast v2642 as u4 - v2645 = and v2642, u8 15 - v2646 = truncate v2645 to 4 bits, max_bit_size: 8 - v2647 = cast v2646 as u4 - v2648 = not v2640 - enable_side_effects v2598 - v2649 = cast v2640 as u4 - v2650 = cast v2648 as u4 - v2651 = mul v2649, v2631 - v2652 = mul v2650, v2631 - v2653 = add v2651, v2652 - v2654 = mul v2649, v2634 - v2655 = mul v2650, v2634 - v2656 = add v2654, v2655 - v2657 = mul v2649, v2637 - v2658 = mul v2650, v2637 - v2659 = add v2657, v2658 - v2660 = mul v2649, v2638 - v2661 = mul v2650, v2638 - v2662 = add v2660, v2661 - v2663 = mul v2649, v2639 - v2664 = mul v2650, v2639 - v2665 = add v2663, v2664 - v2666 = mul v2649, v2644 - v2667 = mul v2649, v2647 - v2668 = lt u64 4, v2590 - v2669 = mul v2598, v2668 - enable_side_effects v2669 - v2670 = array_get v0, index Field 4 - v2671 = div v2670, Field 2⁴ - v2672 = cast v2670 as u4 - v2673 = and v2670, u8 15 - v2674 = truncate v2673 to 4 bits, max_bit_size: 8 - v2675 = cast v2674 as u4 - v2676 = not v2668 - enable_side_effects v2598 - v2677 = cast v2668 as u4 - v2678 = cast v2676 as u4 - v2679 = mul v2677, v2653 - v2680 = mul v2678, v2653 - v2681 = add v2679, v2680 - v2682 = mul v2677, v2656 - v2683 = mul v2678, v2656 - v2684 = add v2682, v2683 - v2685 = mul v2677, v2659 - v2686 = mul v2678, v2659 - v2687 = add v2685, v2686 - v2688 = mul v2677, v2662 - v2689 = mul v2678, v2662 - v2690 = add v2688, v2689 - v2691 = mul v2677, v2665 - v2692 = mul v2678, v2665 - v2693 = add v2691, v2692 - v2694 = mul v2677, v2666 - v2695 = mul v2678, v2666 - v2696 = add v2694, v2695 - v2697 = mul v2677, v2667 - v2698 = mul v2678, v2667 - v2699 = add v2697, v2698 - v2700 = mul v2677, v2672 - v2701 = mul v2677, v2675 - v2702 = not v2598 - enable_side_effects v2702 - v2703 = sub v2590, u64 1 - v2704 = cast v2702 as u64 - v2705 = mul v2703, v2704 - range_check v2705 to 64 bits - v2706 = lt u64 0, v2703 - v2707 = mul v2702, v2706 - enable_side_effects v2707 - v2708 = array_get v0, index u64 1 - v2709 = div v2708, Field 2⁴ - v2710 = cast v2708 as u4 - v2711 = and v2708, u8 15 - v2712 = truncate v2711 to 4 bits, max_bit_size: 8 - v2713 = cast v2712 as u4 - v2714 = not v2706 - enable_side_effects v2702 - v2715 = cast v2706 as u4 - v2716 = cast v2714 as u4 - v2717 = mul v2715, v2710 - v2718 = mul v2715, v2713 - range_check v2705 to 64 bits - v2719 = lt u64 1, v2703 - v2720 = mul v2702, v2719 - enable_side_effects v2720 - v2721 = array_get v0, index u64 2 - v2722 = div v2721, Field 2⁴ - v2723 = cast v2721 as u4 - v2724 = and v2721, u8 15 - v2725 = truncate v2724 to 4 bits, max_bit_size: 8 - v2726 = cast v2725 as u4 - v2727 = not v2719 - enable_side_effects v2702 - v2728 = cast v2719 as u4 - v2729 = cast v2727 as u4 - v2730 = mul v2728, v2717 - v2731 = mul v2729, v2717 - v2732 = add v2730, v2731 - v2733 = mul v2728, v2718 - v2734 = mul v2729, v2718 - v2735 = add v2733, v2734 - v2736 = mul v2728, v2723 - v2737 = mul v2728, v2726 - enable_side_effects u1 1 - v2738 = cast v2598 as u4 - v2739 = cast v2702 as u4 - v2740 = mul v2738, v2681 - v2741 = mul v2739, v2732 - v2742 = add v2740, v2741 - v2743 = mul v2738, v2684 - v2744 = mul v2739, v2735 - v2745 = add v2743, v2744 - v2746 = mul v2738, v2687 - v2747 = mul v2739, v2736 - v2748 = add v2746, v2747 - v2749 = mul v2738, v2690 - v2750 = mul v2739, v2737 - v2751 = add v2749, v2750 - v2752 = mul v2738, v2693 - v2753 = mul v2738, v2696 - v2754 = mul v2738, v2699 - v2755 = mul v2738, v2700 - v2756 = mul v2738, v2701 - v2757 = mul Field 2, v1 - v2758 = cast v2598 as Field - v2759 = add v2757, v2758 - v2760 = sub v2759, Field 2 - inc_rc [v2742, v2745, v2748, v2751, v2752, v2753, v2754, v2755, v2756, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - inc_rc [v2742, v2745, v2748, v2751, v2752, v2753, v2754, v2755, v2756, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - inc_rc [v2742, v2745, v2748, v2751, v2752, v2753, v2754, v2755, v2756, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v2761 = eq v2760, Field 5 - constrain v2760 == Field 5 - v2762 = allocate - v2763 = eq v2742, u4 15 - v2764 = eq v2745, u4 1 - v2765 = mul v2763, v2764 - v2766 = eq v2748, u4 12 - v2767 = mul v2765, v2766 - v2768 = eq v2751, u4 11 - v2769 = mul v2767, v2768 - v2770 = eq v2752, u4 8 - v2771 = mul v2769, v2770 - constrain v2771 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v2772 = allocate - range_check u8 148 to 8 bits - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v2773 = allocate - v2774 = allocate - v2775 = allocate - v2776 = allocate - v2777 = allocate - return -} - -After Dead Instruction Elimination: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v2589 = truncate v1 to 64 bits, max_bit_size: 254 - v2590 = cast v2589 as u64 - inc_rc v0 - v2591 = lt u64 5, v2590 - constrain v2591 == u1 0 - v2594 = array_get v0, index Field 0 - v2596 = cast v2594 as u4 - v2597 = truncate v2596 to 1 bits, max_bit_size: 4 - v2598 = cast v2597 as u1 - enable_side_effects v2598 - v2599 = and v2594, u8 15 - v2600 = truncate v2599 to 4 bits, max_bit_size: 8 - v2601 = cast v2600 as u4 - inc_rc v0 - v2602 = lt u64 1, v2590 - v2603 = mul v2598, v2602 - enable_side_effects v2603 - v2604 = array_get v0, index Field 1 - v2606 = cast v2604 as u4 - v2607 = and v2604, u8 15 - v2608 = truncate v2607 to 4 bits, max_bit_size: 8 - v2609 = cast v2608 as u4 - v2610 = not v2602 - enable_side_effects v2598 - v2611 = cast v2602 as u4 - v2612 = cast v2610 as u4 - v2613 = mul v2611, v2601 - v2614 = mul v2612, v2601 - v2615 = add v2613, v2614 - v2616 = mul v2611, v2606 - v2617 = mul v2611, v2609 - v2618 = lt u64 2, v2590 - v2619 = mul v2598, v2618 - enable_side_effects v2619 - v2620 = array_get v0, index Field 2 - v2622 = cast v2620 as u4 - v2623 = and v2620, u8 15 - v2624 = truncate v2623 to 4 bits, max_bit_size: 8 - v2625 = cast v2624 as u4 - v2626 = not v2618 - enable_side_effects v2598 - v2627 = cast v2618 as u4 - v2628 = cast v2626 as u4 - v2629 = mul v2627, v2615 - v2630 = mul v2628, v2615 - v2631 = add v2629, v2630 - v2632 = mul v2627, v2616 - v2633 = mul v2628, v2616 - v2634 = add v2632, v2633 - v2635 = mul v2627, v2617 - v2636 = mul v2628, v2617 - v2637 = add v2635, v2636 - v2638 = mul v2627, v2622 - v2639 = mul v2627, v2625 - v2640 = lt u64 3, v2590 - v2641 = mul v2598, v2640 - enable_side_effects v2641 - v2648 = not v2640 - enable_side_effects v2598 - v2649 = cast v2640 as u4 - v2650 = cast v2648 as u4 - v2651 = mul v2649, v2631 - v2652 = mul v2650, v2631 - v2653 = add v2651, v2652 - v2654 = mul v2649, v2634 - v2655 = mul v2650, v2634 - v2656 = add v2654, v2655 - v2657 = mul v2649, v2637 - v2658 = mul v2650, v2637 - v2659 = add v2657, v2658 - v2660 = mul v2649, v2638 - v2661 = mul v2650, v2638 - v2662 = add v2660, v2661 - v2663 = mul v2649, v2639 - v2664 = mul v2650, v2639 - v2665 = add v2663, v2664 - v2668 = lt u64 4, v2590 - v2669 = mul v2598, v2668 - enable_side_effects v2669 - v2676 = not v2668 - enable_side_effects v2598 - v2677 = cast v2668 as u4 - v2678 = cast v2676 as u4 - v2679 = mul v2677, v2653 - v2680 = mul v2678, v2653 - v2681 = add v2679, v2680 - v2682 = mul v2677, v2656 - v2683 = mul v2678, v2656 - v2684 = add v2682, v2683 - v2685 = mul v2677, v2659 - v2686 = mul v2678, v2659 - v2687 = add v2685, v2686 - v2688 = mul v2677, v2662 - v2689 = mul v2678, v2662 - v2690 = add v2688, v2689 - v2691 = mul v2677, v2665 - v2692 = mul v2678, v2665 - v2693 = add v2691, v2692 - v2702 = not v2598 - enable_side_effects v2702 - v2703 = sub v2590, u64 1 - v2704 = cast v2702 as u64 - v2705 = mul v2703, v2704 - range_check v2705 to 64 bits - v2706 = lt u64 0, v2703 - v2707 = mul v2702, v2706 - enable_side_effects v2707 - v2708 = array_get v0, index u64 1 - v2710 = cast v2708 as u4 - v2711 = and v2708, u8 15 - v2712 = truncate v2711 to 4 bits, max_bit_size: 8 - v2713 = cast v2712 as u4 - enable_side_effects v2702 - v2715 = cast v2706 as u4 - v2717 = mul v2715, v2710 - v2718 = mul v2715, v2713 - range_check v2705 to 64 bits - v2719 = lt u64 1, v2703 - v2720 = mul v2702, v2719 - enable_side_effects v2720 - v2721 = array_get v0, index u64 2 - v2723 = cast v2721 as u4 - v2724 = and v2721, u8 15 - v2725 = truncate v2724 to 4 bits, max_bit_size: 8 - v2726 = cast v2725 as u4 - v2727 = not v2719 - enable_side_effects v2702 - v2728 = cast v2719 as u4 - v2729 = cast v2727 as u4 - v2730 = mul v2728, v2717 - v2731 = mul v2729, v2717 - v2732 = add v2730, v2731 - v2733 = mul v2728, v2718 - v2734 = mul v2729, v2718 - v2735 = add v2733, v2734 - v2736 = mul v2728, v2723 - v2737 = mul v2728, v2726 - enable_side_effects u1 1 - v2738 = cast v2598 as u4 - v2739 = cast v2702 as u4 - v2740 = mul v2738, v2681 - v2741 = mul v2739, v2732 - v2742 = add v2740, v2741 - v2743 = mul v2738, v2684 - v2744 = mul v2739, v2735 - v2745 = add v2743, v2744 - v2746 = mul v2738, v2687 - v2747 = mul v2739, v2736 - v2748 = add v2746, v2747 - v2749 = mul v2738, v2690 - v2750 = mul v2739, v2737 - v2751 = add v2749, v2750 - v2752 = mul v2738, v2693 - v2757 = mul Field 2, v1 - v2758 = cast v2598 as Field - v2759 = add v2757, v2758 - v2760 = sub v2759, Field 2 - constrain v2760 == Field 5 - v2763 = eq v2742, u4 15 - v2764 = eq v2745, u4 1 - v2765 = mul v2763, v2764 - v2766 = eq v2748, u4 12 - v2767 = mul v2765, v2766 - v2768 = eq v2751, u4 11 - v2769 = mul v2767, v2768 - v2770 = eq v2752, u4 8 - v2771 = mul v2769, v2770 - constrain v2771 == u1 1 - range_check u8 148 to 8 bits - return -} - -After Fill Internal Slice Dummy Data: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v2778 = truncate v1 to 64 bits, max_bit_size: 254 - v2779 = cast v2778 as u64 - inc_rc v0 - v2780 = lt u64 5, v2779 - constrain v2780 == u1 0 - v2781 = array_get v0, index Field 0 - v2782 = cast v2781 as u4 - v2783 = truncate v2782 to 1 bits, max_bit_size: 4 - v2784 = cast v2783 as u1 - enable_side_effects v2784 - v2785 = and v2781, u8 15 - v2786 = truncate v2785 to 4 bits, max_bit_size: 8 - v2787 = cast v2786 as u4 - inc_rc v0 - v2788 = lt u64 1, v2779 - v2789 = mul v2784, v2788 - enable_side_effects v2789 - v2790 = array_get v0, index Field 1 - v2791 = cast v2790 as u4 - v2792 = and v2790, u8 15 - v2793 = truncate v2792 to 4 bits, max_bit_size: 8 - v2794 = cast v2793 as u4 - v2795 = not v2788 - enable_side_effects v2784 - v2796 = cast v2788 as u4 - v2797 = cast v2795 as u4 - v2798 = mul v2796, v2787 - v2799 = mul v2797, v2787 - v2800 = add v2798, v2799 - v2801 = mul v2796, v2791 - v2802 = mul v2796, v2794 - v2803 = lt u64 2, v2779 - v2804 = mul v2784, v2803 - enable_side_effects v2804 - v2805 = array_get v0, index Field 2 - v2806 = cast v2805 as u4 - v2807 = and v2805, u8 15 - v2808 = truncate v2807 to 4 bits, max_bit_size: 8 - v2809 = cast v2808 as u4 - v2810 = not v2803 - enable_side_effects v2784 - v2811 = cast v2803 as u4 - v2812 = cast v2810 as u4 - v2813 = mul v2811, v2800 - v2814 = mul v2812, v2800 - v2815 = add v2813, v2814 - v2816 = mul v2811, v2801 - v2817 = mul v2812, v2801 - v2818 = add v2816, v2817 - v2819 = mul v2811, v2802 - v2820 = mul v2812, v2802 - v2821 = add v2819, v2820 - v2822 = mul v2811, v2806 - v2823 = mul v2811, v2809 - v2824 = lt u64 3, v2779 - v2825 = mul v2784, v2824 - enable_side_effects v2825 - v2826 = not v2824 - enable_side_effects v2784 - v2827 = cast v2824 as u4 - v2828 = cast v2826 as u4 - v2829 = mul v2827, v2815 - v2830 = mul v2828, v2815 - v2831 = add v2829, v2830 - v2832 = mul v2827, v2818 - v2833 = mul v2828, v2818 - v2834 = add v2832, v2833 - v2835 = mul v2827, v2821 - v2836 = mul v2828, v2821 - v2837 = add v2835, v2836 - v2838 = mul v2827, v2822 - v2839 = mul v2828, v2822 - v2840 = add v2838, v2839 - v2841 = mul v2827, v2823 - v2842 = mul v2828, v2823 - v2843 = add v2841, v2842 - v2844 = lt u64 4, v2779 - v2845 = mul v2784, v2844 - enable_side_effects v2845 - v2846 = not v2844 - enable_side_effects v2784 - v2847 = cast v2844 as u4 - v2848 = cast v2846 as u4 - v2849 = mul v2847, v2831 - v2850 = mul v2848, v2831 - v2851 = add v2849, v2850 - v2852 = mul v2847, v2834 - v2853 = mul v2848, v2834 - v2854 = add v2852, v2853 - v2855 = mul v2847, v2837 - v2856 = mul v2848, v2837 - v2857 = add v2855, v2856 - v2858 = mul v2847, v2840 - v2859 = mul v2848, v2840 - v2860 = add v2858, v2859 - v2861 = mul v2847, v2843 - v2862 = mul v2848, v2843 - v2863 = add v2861, v2862 - v2864 = not v2784 - enable_side_effects v2864 - v2865 = sub v2779, u64 1 - v2866 = cast v2864 as u64 - v2867 = mul v2865, v2866 - range_check v2867 to 64 bits - v2868 = lt u64 0, v2865 - v2869 = mul v2864, v2868 - enable_side_effects v2869 - v2870 = array_get v0, index u64 1 - v2871 = cast v2870 as u4 - v2872 = and v2870, u8 15 - v2873 = truncate v2872 to 4 bits, max_bit_size: 8 - v2874 = cast v2873 as u4 - enable_side_effects v2864 - v2875 = cast v2868 as u4 - v2876 = mul v2875, v2871 - v2877 = mul v2875, v2874 - range_check v2867 to 64 bits - v2878 = lt u64 1, v2865 - v2879 = mul v2864, v2878 - enable_side_effects v2879 - v2880 = array_get v0, index u64 2 - v2881 = cast v2880 as u4 - v2882 = and v2880, u8 15 - v2883 = truncate v2882 to 4 bits, max_bit_size: 8 - v2884 = cast v2883 as u4 - v2885 = not v2878 - enable_side_effects v2864 - v2886 = cast v2878 as u4 - v2887 = cast v2885 as u4 - v2888 = mul v2886, v2876 - v2889 = mul v2887, v2876 - v2890 = add v2888, v2889 - v2891 = mul v2886, v2877 - v2892 = mul v2887, v2877 - v2893 = add v2891, v2892 - v2894 = mul v2886, v2881 - v2895 = mul v2886, v2884 - enable_side_effects u1 1 - v2896 = cast v2784 as u4 - v2897 = cast v2864 as u4 - v2898 = mul v2896, v2851 - v2899 = mul v2897, v2890 - v2900 = add v2898, v2899 - v2901 = mul v2896, v2854 - v2902 = mul v2897, v2893 - v2903 = add v2901, v2902 - v2904 = mul v2896, v2857 - v2905 = mul v2897, v2894 - v2906 = add v2904, v2905 - v2907 = mul v2896, v2860 - v2908 = mul v2897, v2895 - v2909 = add v2907, v2908 - v2910 = mul v2896, v2863 - v2911 = mul Field 2, v1 - v2912 = cast v2784 as Field - v2913 = add v2911, v2912 - v2914 = sub v2913, Field 2 - constrain v2914 == Field 5 - v2915 = eq v2900, u4 15 - v2916 = eq v2903, u4 1 - v2917 = mul v2915, v2916 - v2918 = eq v2906, u4 12 - v2919 = mul v2917, v2918 - v2920 = eq v2909, u4 11 - v2921 = mul v2919, v2920 - v2922 = eq v2910, u4 8 - v2923 = mul v2921, v2922 - constrain v2923 == u1 1 - range_check u8 148 to 8 bits - return -} - diff --git a/test_programs/execution_success/regression/new-acir b/test_programs/execution_success/regression/new-acir deleted file mode 100644 index 9f6cc42b863..00000000000 --- a/test_programs/execution_success/regression/new-acir +++ /dev/null @@ -1,202 +0,0 @@ -Compiled ACIR for main (unoptimized): -current witness index : 100 -public parameters indices : [] -return value indices : [] -BLACKBOX::RANGE [(_1, num_bits: 8)] [ ] -BLACKBOX::RANGE [(_2, num_bits: 8)] [ ] -BLACKBOX::RANGE [(_3, num_bits: 8)] [ ] -BLACKBOX::RANGE [(_4, num_bits: 8)] [ ] -BLACKBOX::RANGE [(_5, num_bits: 8)] [ ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(6))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(7)), Simple(Witness(8))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 255, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 255, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 255, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_7, num_bits: 190)] [ ] -BLACKBOX::RANGE [(_8, num_bits: 64)] [ ] -EXPR [ (1, _6) (-2⁶⁴, _7) (-1, _8) 0 ] -EXPR [ (1, _7) (-1, _9) -1186564023676924939888766319973246049704924238154051448977 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(9))], q_c: 0 })] -outputs: [Simple(Witness(10))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _9, _10) (1, _11) -1 ] -EXPR [ (1, _9, _11) 0 ] -EXPR [ (-1, _8, _11) (2¹⁶×74637766815744, _11) (-1, _12) 0 ] -BLACKBOX::RANGE [(_12, num_bits: 65)] [ ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551621 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(13)), Simple(Witness(14))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_14, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _13) (-1, _14) 18446744073709551621 ] -EXPR [ (-1, _13) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(1))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2 })] -outputs: [Simple(Witness(15)), Simple(Witness(16))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 5, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 5, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 5, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_15, num_bits: 3)] [ ] -EXPR [ (1, _16, _16) (-1, _16) 0 ] -EXPR [ (1, _1) (-2, _15) (-1, _16) 0 ] -EXPR [ (-1, _17) 15 ] -BLACKBOX::AND [(_1, num_bits: 8), (_17, num_bits: 8)] [ _18] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(18))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(19)), Simple(Witness(20))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_19, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_20, num_bits: 4)] [ ] -EXPR [ (1, _18) (-2⁴, _19) (-1, _20) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551617 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(21)), Simple(Witness(22))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _21, _21) (-1, _21) 0 ] -BLACKBOX::RANGE [(_22, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _21) (-1, _22) 18446744073709551617 ] -EXPR [ (-1, _21) (-1, _23) 1 ] -BLACKBOX::AND [(_2, num_bits: 8), (_17, num_bits: 8)] [ _24] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(24))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(25)), Simple(Witness(26))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_25, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_26, num_bits: 4)] [ ] -EXPR [ (1, _24) (-2⁴, _25) (-1, _26) 0 ] -EXPR [ (-1, _23) (-1, _27) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551618 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(28)), Simple(Witness(29))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _28, _28) (-1, _28) 0 ] -BLACKBOX::RANGE [(_29, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _28) (-1, _29) 18446744073709551618 ] -EXPR [ (-1, _28) (-1, _30) 1 ] -BLACKBOX::AND [(_3, num_bits: 8), (_17, num_bits: 8)] [ _31] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(31))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(32)), Simple(Witness(33))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_32, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_33, num_bits: 4)] [ ] -EXPR [ (1, _31) (-2⁴, _32) (-1, _33) 0 ] -EXPR [ (1, _20, _23) (1, _20, _27) (-1, _34) 0 ] -EXPR [ (-1, _30) (-1, _35) 1 ] -EXPR [ (1, _2, _23) (-1, _36) 0 ] -EXPR [ (1, _23, _26) (-1, _37) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551619 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(38)), Simple(Witness(39))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _38, _38) (-1, _38) 0 ] -BLACKBOX::RANGE [(_39, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _38) (-1, _39) 18446744073709551619 ] -EXPR [ (-1, _38) (-1, _40) 1 ] -EXPR [ (1, _30, _34) (1, _34, _35) (-1, _41) 0 ] -EXPR [ (-1, _40) (-1, _42) 1 ] -EXPR [ (1, _30, _36) (1, _35, _36) (-1, _43) 0 ] -EXPR [ (1, _30, _37) (1, _35, _37) (-1, _44) 0 ] -EXPR [ (1, _3, _30) (-1, _45) 0 ] -EXPR [ (1, _30, _33) (-1, _46) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551620 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(47)), Simple(Witness(48))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _47, _47) (-1, _47) 0 ] -BLACKBOX::RANGE [(_48, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _47) (-1, _48) 18446744073709551620 ] -EXPR [ (-1, _47) (-1, _49) 1 ] -EXPR [ (1, _40, _41) (1, _41, _42) (-1, _50) 0 ] -EXPR [ (-1, _49) (-1, _51) 1 ] -EXPR [ (1, _40, _43) (1, _42, _43) (-1, _52) 0 ] -EXPR [ (1, _40, _44) (1, _42, _44) (-1, _53) 0 ] -EXPR [ (1, _40, _45) (1, _42, _45) (-1, _54) 0 ] -EXPR [ (1, _40, _46) (1, _42, _46) (-1, _55) 0 ] -EXPR [ (1, _8) (-1, _56) -1 ] -EXPR [ (-1, _16) (-1, _57) 1 ] -EXPR [ (1, _56, _57) (-1, _58) 0 ] -BLACKBOX::RANGE [(_58, num_bits: 64)] [ ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(56))], q_c: 2⁶⁴ }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(59)), Simple(Witness(60))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _59, _59) (-1, _59) 0 ] -BLACKBOX::RANGE [(_60, num_bits: 64)] [ ] -EXPR [ (-1, _56) (-2⁶⁴, _59) (-1, _60) 2⁶⁴ ] -EXPR [ (-1, _59) (-1, _61) 1 ] -BLACKBOX::AND [(_2, num_bits: 8), (_17, num_bits: 8)] [ _62] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(62))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(63)), Simple(Witness(64))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_63, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_64, num_bits: 4)] [ ] -EXPR [ (1, _62) (-2⁴, _63) (-1, _64) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(56))], q_c: 18446744073709551617 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(65)), Simple(Witness(66))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _65, _65) (-1, _65) 0 ] -BLACKBOX::RANGE [(_66, num_bits: 64)] [ ] -EXPR [ (-1, _56) (-2⁶⁴, _65) (-1, _66) 18446744073709551617 ] -EXPR [ (-1, _65) (-1, _67) 1 ] -BLACKBOX::AND [(_3, num_bits: 8), (_17, num_bits: 8)] [ _68] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(68))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(69)), Simple(Witness(70))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_69, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_70, num_bits: 4)] [ ] -EXPR [ (1, _68) (-2⁴, _69) (-1, _70) 0 ] -EXPR [ (1, _2, _61) (-1, _71) 0 ] -EXPR [ (-1, _67) (-1, _72) 1 ] -EXPR [ (1, _61, _64) (-1, _73) 0 ] -EXPR [ (1, _49, _50) (1, _50, _51) (-1, _74) 0 ] -EXPR [ (1, _67, _71) (1, _71, _72) (-1, _75) 0 ] -EXPR [ (1, _49, _52) (1, _51, _52) (-1, _76) 0 ] -EXPR [ (1, _67, _73) (1, _72, _73) (-1, _77) 0 ] -EXPR [ (1, _49, _53) (1, _51, _53) (-1, _78) 0 ] -EXPR [ (1, _3, _67) (-1, _79) 0 ] -EXPR [ (1, _49, _54) (1, _51, _54) (-1, _80) 0 ] -EXPR [ (1, _67, _70) (-1, _81) 0 ] -EXPR [ (1, _49, _55) (1, _51, _55) (-1, _82) 0 ] -EXPR [ (2, _6) (1, _16) -7 ] -EXPR [ (-1, _16, _74) (-1, _57, _75) (-1, _83) 15 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(83))], q_c: 0 })] -outputs: [Simple(Witness(84))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _83, _84) (1, _85) -1 ] -EXPR [ (1, _83, _85) 0 ] -EXPR [ (-1, _16, _76) (-1, _57, _77) (-1, _86) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(86))], q_c: 0 })] -outputs: [Simple(Witness(87))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _86, _87) (1, _88) -1 ] -EXPR [ (1, _86, _88) 0 ] -EXPR [ (-1, _16, _78) (-1, _57, _79) (-1, _89) 12 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(89))], q_c: 0 })] -outputs: [Simple(Witness(90))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _89, _90) (1, _91) -1 ] -EXPR [ (1, _89, _91) 0 ] -EXPR [ (1, _85, _88) (-1, _92) 0 ] -EXPR [ (-1, _16, _80) (-1, _57, _81) (-1, _93) 11 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(93))], q_c: 0 })] -outputs: [Simple(Witness(94))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _93, _94) (1, _95) -1 ] -EXPR [ (1, _93, _95) 0 ] -EXPR [ (1, _91, _92) (-1, _96) 0 ] -EXPR [ (-1, _16, _82) (-1, _97) 8 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(97))], q_c: 0 })] -outputs: [Simple(Witness(98))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _97, _98) (1, _99) -1 ] -EXPR [ (1, _97, _99) 0 ] -EXPR [ (1, _95, _96) (-1, _100) 0 ] -EXPR [ (1, _99, _100) -1 ] - diff --git a/test_programs/execution_success/regression/old b/test_programs/execution_success/regression/old deleted file mode 100644 index 2bd4842862d..00000000000 --- a/test_programs/execution_success/regression/old +++ /dev/null @@ -1,5180 +0,0 @@ -Initial SSA: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - v3, v4 = call f1(v0, v1) - inc_rc v3 - inc_rc v3 - v6 = eq v4, Field 5 - constrain v4 == Field 5 - v10 = array_get v3, index Field 0 - v11 = array_get v3, index Field 1 - v13 = array_get v3, index Field 2 - v15 = array_get v3, index Field 3 - v17 = array_get v3, index Field 4 - v25 = allocate - store u1 1 at v25 - jmp b1(Field 0) - b1(v26: Field): - v27 = lt v26, Field 5 - jmpif v27 then: b2, else: b3 - b2(): - v28 = array_get [v10, v11, v13, v15, v17], index v26 - v29 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v26 - v30 = eq v28, v29 - v31 = load v25 - v32 = mul v31, v30 - store v32 at v25 - v33 = add v26, Field 1 - jmp b1(v33) - b3(): - v34 = load v25 - constrain v34 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v57, v58 = call f2([u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], Field 20) - inc_rc v57 - v61 = allocate - store u1 1 at v61 - jmp b4(Field 0) - b4(v62: Field): - v64 = lt v62, Field 2⁵ - jmpif v64 then: b5, else: b6 - b5(): - v65 = array_get v57, index v62 - v66 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v62 - v67 = eq v65, v66 - v68 = load v61 - v69 = mul v68, v67 - store v69 at v61 - v70 = add v62, Field 1 - jmp b4(v70) - b6(): - v71 = load v61 - constrain v71 == u1 1 - v73 = eq v58, Field 21 - constrain v58 == Field 21 - v75 = call f3() - v77 = eq v75, u64 1 - constrain v75 == u64 1 - v79 = call f4() - v81 = eq v79, u64 2⁴ - constrain v79 == u64 2⁴ - v84 = call f5(u64 0) - v85 = eq v84, u64 1 - constrain v84 == u64 1 - v88 = call f5(u64 4) - v89 = eq v88, u64 2⁴ - constrain v88 == u64 2⁴ - return -} -acir fn compact_decode f1 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - v11 = truncate v1 to 64 bits, max_bit_size: 254 - v12 = cast v11 as u64 - inc_rc v0 - v13 = lt u64 5, v12 - v14 = not v13 - constrain v13 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v18 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v18 - v20 = array_get v0, index Field 0 - v31 = div v20, Field 2⁴ - v32 = truncate v31 to 4 bits, max_bit_size: 8 - v33 = cast v32 as u4 - v34 = truncate v33 to 1 bits, max_bit_size: 4 - v35 = cast v34 as u1 - jmpif v35 then: b1, else: b2 - b1(): - v36 = load v18 - v37 = array_get v0, index Field 0 - v39 = and v37, u8 15 - v40 = truncate v39 to 4 bits, max_bit_size: 8 - v41 = cast v40 as u4 - v42 = array_set v36, index Field 0, value v41 - store v42 at v18 - inc_rc v0 - jmp b3(Field 1) - b3(v43: Field): - v44 = lt v43, Field 5 - jmpif v44 then: b4, else: b5 - b4(): - v45 = truncate v43 to 64 bits, max_bit_size: 254 - v46 = cast v45 as u64 - v47 = truncate v1 to 64 bits, max_bit_size: 254 - v48 = cast v47 as u64 - v49 = lt v46, v48 - jmpif v49 then: b6, else: b7 - b6(): - v50 = array_get v0, index v43 - v51 = load v18 - v52 = mul Field 2, v43 - v53 = sub v52, Field 1 - v55 = div v50, Field 2⁴ - v56 = truncate v55 to 4 bits, max_bit_size: 8 - v57 = cast v56 as u4 - v58 = array_set v51, index v53, value v57 - v59 = add v53, Field 1 - store v58 at v18 - v60 = load v18 - v61 = mul Field 2, v43 - v62 = and v50, u8 15 - v63 = truncate v62 to 4 bits, max_bit_size: 8 - v64 = cast v63 as u4 - v65 = array_set v60, index v61, value v64 - v66 = add v61, Field 1 - store v65 at v18 - jmp b7() - b7(): - v67 = add v43, Field 1 - jmp b3(v67) - b5(): - jmp b8() - b8(): - v95 = load v18 - v96 = mul Field 2, v1 - v97 = cast v35 as Field - v98 = add v96, v97 - v99 = sub v98, Field 2 - inc_rc v95 - return v95, v99 - b2(): - jmp b9(u64 0) - b9(v68: u64): - v70 = lt v68, u64 2 - jmpif v70 then: b10, else: b11 - b10(): - v71 = truncate v1 to 64 bits, max_bit_size: 254 - v72 = cast v71 as u64 - v74 = sub v72, u64 1 - range_check v74 to 64 bits - v75 = lt v68, v74 - jmpif v75 then: b12, else: b13 - b12(): - v76 = add v68, u64 1 - range_check v76 to 64 bits - v77 = array_get v0, index v76 - v78 = load v18 - v79 = mul u64 2, v68 - range_check v79 to 64 bits - v81 = div v77, Field 2⁴ - v82 = truncate v81 to 4 bits, max_bit_size: 8 - v83 = cast v82 as u4 - v84 = array_set v78, index v79, value v83 - v85 = add v79, Field 1 - store v84 at v18 - v86 = load v18 - v87 = mul u64 2, v68 - range_check v87 to 64 bits - v88 = add v87, u64 1 - range_check v88 to 64 bits - v89 = and v77, u8 15 - v90 = truncate v89 to 4 bits, max_bit_size: 8 - v91 = cast v90 as u4 - v92 = array_set v86, index v88, value v91 - v93 = add v88, Field 1 - store v92 at v18 - jmp b13() - b13(): - v94 = add v68, Field 1 - jmp b9(v94) - b11(): - jmp b8() -} -acir fn enc f2 { - b0(v0: [u8; 32], v1: Field): - inc_rc v0 - v5 = truncate v1 to 8 bits, max_bit_size: 254 - v6 = cast v5 as u8 - v7 = lt u8 2⁵, v6 - v8 = not v7 - constrain v7 == u1 0 - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v13 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v13 - v15 = eq v1, Field 0 - jmpif v15 then: b1, else: b2 - b1(): - v16 = load v13 - inc_rc v16 - jmp b3(v16, v1) - b3(v41: [u8; 32], v42: Field): - return v41, v42 - b2(): - v17 = truncate v1 to 8 bits, max_bit_size: 254 - v18 = cast v17 as u8 - v20 = lt v18, u8 31 - jmpif v20 then: b4, else: b5 - b4(): - v21 = load v13 - v23 = truncate v1 to 8 bits, max_bit_size: 254 - v24 = cast v23 as u8 - v25 = add u8 2⁷, v24 - range_check v25 to 8 bits - v27 = array_set v21, index Field 0, value v25 - store v27 at v13 - inc_rc v0 - jmp b6(Field 1) - b6(v28: Field): - v29 = lt v28, Field 2⁵ - jmpif v29 then: b7, else: b8 - b7(): - v30 = load v13 - v31 = sub v28, Field 1 - v32 = array_get v0, index v31 - v33 = array_set v30, index v28, value v32 - v34 = add v28, Field 1 - store v33 at v13 - v35 = add v28, Field 1 - jmp b6(v35) - b8(): - v36 = load v13 - v37 = add v1, Field 1 - inc_rc v36 - jmp b9(v36, v37) - b9(v39: [u8; 32], v40: Field): - jmp b3(v39, v40) - b5(): - v38 = load v13 - inc_rc v38 - jmp b9(v38, Field 2⁵) -} -acir fn bitshift_literal_0 f3 { - b0(): - v1 = allocate - store u64 0 at v1 - v2 = load v1 - v7 = or v2, u64 1 - store v7 at v1 - v8 = load v1 - return v8 -} -acir fn bitshift_literal_4 f4 { - b0(): - v1 = allocate - store u64 0 at v1 - v2 = load v1 - v9 = or v2, u64 2⁴ - store v9 at v1 - v10 = load v1 - return v10 -} -acir fn bitshift_variable f5 { - b0(v0: u64): - v2 = allocate - store u64 0 at v2 - v3 = load v2 - v7 = lt v0, u64 2⁶ - v9 = cast v7 as u64 - v12, v13 = call to_le_bits(v0, Field 2⁶) - v16 = array_get v13, index Field 63 - v17 = mul Field 2, v16 - v18 = sub Field 1, v16 - v19 = add v17, v18 - v20 = mul v19, v19 - v21 = mul v20, Field 2 - v23 = array_get v13, index Field 62 - v24 = mul v21, v23 - v25 = sub Field 1, v23 - v26 = mul v25, v20 - v27 = add v24, v26 - v28 = mul v27, v27 - v29 = mul v28, Field 2 - v31 = array_get v13, index Field 61 - v32 = mul v29, v31 - v33 = sub Field 1, v31 - v34 = mul v33, v28 - v35 = add v32, v34 - v36 = mul v35, v35 - v37 = mul v36, Field 2 - v39 = array_get v13, index Field 60 - v40 = mul v37, v39 - v41 = sub Field 1, v39 - v42 = mul v41, v36 - v43 = add v40, v42 - v44 = mul v43, v43 - v45 = mul v44, Field 2 - v47 = array_get v13, index Field 59 - v48 = mul v45, v47 - v49 = sub Field 1, v47 - v50 = mul v49, v44 - v51 = add v48, v50 - v52 = mul v51, v51 - v53 = mul v52, Field 2 - v55 = array_get v13, index Field 58 - v56 = mul v53, v55 - v57 = sub Field 1, v55 - v58 = mul v57, v52 - v59 = add v56, v58 - v60 = mul v59, v59 - v61 = mul v60, Field 2 - v63 = array_get v13, index Field 57 - v64 = mul v61, v63 - v65 = sub Field 1, v63 - v66 = mul v65, v60 - v67 = add v64, v66 - v68 = mul v67, v67 - v69 = mul v68, Field 2 - v71 = array_get v13, index Field 56 - v72 = mul v69, v71 - v73 = sub Field 1, v71 - v74 = mul v73, v68 - v75 = add v72, v74 - v76 = mul v75, v75 - v77 = mul v76, Field 2 - v79 = array_get v13, index Field 55 - v80 = mul v77, v79 - v81 = sub Field 1, v79 - v82 = mul v81, v76 - v83 = add v80, v82 - v84 = mul v83, v83 - v85 = mul v84, Field 2 - v87 = array_get v13, index Field 54 - v88 = mul v85, v87 - v89 = sub Field 1, v87 - v90 = mul v89, v84 - v91 = add v88, v90 - v92 = mul v91, v91 - v93 = mul v92, Field 2 - v95 = array_get v13, index Field 53 - v96 = mul v93, v95 - v97 = sub Field 1, v95 - v98 = mul v97, v92 - v99 = add v96, v98 - v100 = mul v99, v99 - v101 = mul v100, Field 2 - v103 = array_get v13, index Field 52 - v104 = mul v101, v103 - v105 = sub Field 1, v103 - v106 = mul v105, v100 - v107 = add v104, v106 - v108 = mul v107, v107 - v109 = mul v108, Field 2 - v111 = array_get v13, index Field 51 - v112 = mul v109, v111 - v113 = sub Field 1, v111 - v114 = mul v113, v108 - v115 = add v112, v114 - v116 = mul v115, v115 - v117 = mul v116, Field 2 - v119 = array_get v13, index Field 50 - v120 = mul v117, v119 - v121 = sub Field 1, v119 - v122 = mul v121, v116 - v123 = add v120, v122 - v124 = mul v123, v123 - v125 = mul v124, Field 2 - v127 = array_get v13, index Field 49 - v128 = mul v125, v127 - v129 = sub Field 1, v127 - v130 = mul v129, v124 - v131 = add v128, v130 - v132 = mul v131, v131 - v133 = mul v132, Field 2 - v135 = array_get v13, index Field 2⁴×3 - v136 = mul v133, v135 - v137 = sub Field 1, v135 - v138 = mul v137, v132 - v139 = add v136, v138 - v140 = mul v139, v139 - v141 = mul v140, Field 2 - v143 = array_get v13, index Field 47 - v144 = mul v141, v143 - v145 = sub Field 1, v143 - v146 = mul v145, v140 - v147 = add v144, v146 - v148 = mul v147, v147 - v149 = mul v148, Field 2 - v151 = array_get v13, index Field 46 - v152 = mul v149, v151 - v153 = sub Field 1, v151 - v154 = mul v153, v148 - v155 = add v152, v154 - v156 = mul v155, v155 - v157 = mul v156, Field 2 - v159 = array_get v13, index Field 45 - v160 = mul v157, v159 - v161 = sub Field 1, v159 - v162 = mul v161, v156 - v163 = add v160, v162 - v164 = mul v163, v163 - v165 = mul v164, Field 2 - v167 = array_get v13, index Field 44 - v168 = mul v165, v167 - v169 = sub Field 1, v167 - v170 = mul v169, v164 - v171 = add v168, v170 - v172 = mul v171, v171 - v173 = mul v172, Field 2 - v175 = array_get v13, index Field 43 - v176 = mul v173, v175 - v177 = sub Field 1, v175 - v178 = mul v177, v172 - v179 = add v176, v178 - v180 = mul v179, v179 - v181 = mul v180, Field 2 - v183 = array_get v13, index Field 42 - v184 = mul v181, v183 - v185 = sub Field 1, v183 - v186 = mul v185, v180 - v187 = add v184, v186 - v188 = mul v187, v187 - v189 = mul v188, Field 2 - v191 = array_get v13, index Field 41 - v192 = mul v189, v191 - v193 = sub Field 1, v191 - v194 = mul v193, v188 - v195 = add v192, v194 - v196 = mul v195, v195 - v197 = mul v196, Field 2 - v199 = array_get v13, index Field 40 - v200 = mul v197, v199 - v201 = sub Field 1, v199 - v202 = mul v201, v196 - v203 = add v200, v202 - v204 = mul v203, v203 - v205 = mul v204, Field 2 - v207 = array_get v13, index Field 39 - v208 = mul v205, v207 - v209 = sub Field 1, v207 - v210 = mul v209, v204 - v211 = add v208, v210 - v212 = mul v211, v211 - v213 = mul v212, Field 2 - v215 = array_get v13, index Field 38 - v216 = mul v213, v215 - v217 = sub Field 1, v215 - v218 = mul v217, v212 - v219 = add v216, v218 - v220 = mul v219, v219 - v221 = mul v220, Field 2 - v223 = array_get v13, index Field 37 - v224 = mul v221, v223 - v225 = sub Field 1, v223 - v226 = mul v225, v220 - v227 = add v224, v226 - v228 = mul v227, v227 - v229 = mul v228, Field 2 - v231 = array_get v13, index Field 36 - v232 = mul v229, v231 - v233 = sub Field 1, v231 - v234 = mul v233, v228 - v235 = add v232, v234 - v236 = mul v235, v235 - v237 = mul v236, Field 2 - v239 = array_get v13, index Field 35 - v240 = mul v237, v239 - v241 = sub Field 1, v239 - v242 = mul v241, v236 - v243 = add v240, v242 - v244 = mul v243, v243 - v245 = mul v244, Field 2 - v247 = array_get v13, index Field 34 - v248 = mul v245, v247 - v249 = sub Field 1, v247 - v250 = mul v249, v244 - v251 = add v248, v250 - v252 = mul v251, v251 - v253 = mul v252, Field 2 - v255 = array_get v13, index Field 33 - v256 = mul v253, v255 - v257 = sub Field 1, v255 - v258 = mul v257, v252 - v259 = add v256, v258 - v260 = mul v259, v259 - v261 = mul v260, Field 2 - v263 = array_get v13, index Field 2⁵ - v264 = mul v261, v263 - v265 = sub Field 1, v263 - v266 = mul v265, v260 - v267 = add v264, v266 - v268 = mul v267, v267 - v269 = mul v268, Field 2 - v271 = array_get v13, index Field 31 - v272 = mul v269, v271 - v273 = sub Field 1, v271 - v274 = mul v273, v268 - v275 = add v272, v274 - v276 = mul v275, v275 - v277 = mul v276, Field 2 - v279 = array_get v13, index Field 30 - v280 = mul v277, v279 - v281 = sub Field 1, v279 - v282 = mul v281, v276 - v283 = add v280, v282 - v284 = mul v283, v283 - v285 = mul v284, Field 2 - v287 = array_get v13, index Field 29 - v288 = mul v285, v287 - v289 = sub Field 1, v287 - v290 = mul v289, v284 - v291 = add v288, v290 - v292 = mul v291, v291 - v293 = mul v292, Field 2 - v295 = array_get v13, index Field 28 - v296 = mul v293, v295 - v297 = sub Field 1, v295 - v298 = mul v297, v292 - v299 = add v296, v298 - v300 = mul v299, v299 - v301 = mul v300, Field 2 - v303 = array_get v13, index Field 27 - v304 = mul v301, v303 - v305 = sub Field 1, v303 - v306 = mul v305, v300 - v307 = add v304, v306 - v308 = mul v307, v307 - v309 = mul v308, Field 2 - v311 = array_get v13, index Field 26 - v312 = mul v309, v311 - v313 = sub Field 1, v311 - v314 = mul v313, v308 - v315 = add v312, v314 - v316 = mul v315, v315 - v317 = mul v316, Field 2 - v319 = array_get v13, index Field 25 - v320 = mul v317, v319 - v321 = sub Field 1, v319 - v322 = mul v321, v316 - v323 = add v320, v322 - v324 = mul v323, v323 - v325 = mul v324, Field 2 - v327 = array_get v13, index Field 24 - v328 = mul v325, v327 - v329 = sub Field 1, v327 - v330 = mul v329, v324 - v331 = add v328, v330 - v332 = mul v331, v331 - v333 = mul v332, Field 2 - v335 = array_get v13, index Field 23 - v336 = mul v333, v335 - v337 = sub Field 1, v335 - v338 = mul v337, v332 - v339 = add v336, v338 - v340 = mul v339, v339 - v341 = mul v340, Field 2 - v343 = array_get v13, index Field 22 - v344 = mul v341, v343 - v345 = sub Field 1, v343 - v346 = mul v345, v340 - v347 = add v344, v346 - v348 = mul v347, v347 - v349 = mul v348, Field 2 - v351 = array_get v13, index Field 21 - v352 = mul v349, v351 - v353 = sub Field 1, v351 - v354 = mul v353, v348 - v355 = add v352, v354 - v356 = mul v355, v355 - v357 = mul v356, Field 2 - v359 = array_get v13, index Field 20 - v360 = mul v357, v359 - v361 = sub Field 1, v359 - v362 = mul v361, v356 - v363 = add v360, v362 - v364 = mul v363, v363 - v365 = mul v364, Field 2 - v367 = array_get v13, index Field 19 - v368 = mul v365, v367 - v369 = sub Field 1, v367 - v370 = mul v369, v364 - v371 = add v368, v370 - v372 = mul v371, v371 - v373 = mul v372, Field 2 - v375 = array_get v13, index Field 18 - v376 = mul v373, v375 - v377 = sub Field 1, v375 - v378 = mul v377, v372 - v379 = add v376, v378 - v380 = mul v379, v379 - v381 = mul v380, Field 2 - v383 = array_get v13, index Field 17 - v384 = mul v381, v383 - v385 = sub Field 1, v383 - v386 = mul v385, v380 - v387 = add v384, v386 - v388 = mul v387, v387 - v389 = mul v388, Field 2 - v391 = array_get v13, index Field 2⁴ - v392 = mul v389, v391 - v393 = sub Field 1, v391 - v394 = mul v393, v388 - v395 = add v392, v394 - v396 = mul v395, v395 - v397 = mul v396, Field 2 - v399 = array_get v13, index Field 15 - v400 = mul v397, v399 - v401 = sub Field 1, v399 - v402 = mul v401, v396 - v403 = add v400, v402 - v404 = mul v403, v403 - v405 = mul v404, Field 2 - v407 = array_get v13, index Field 14 - v408 = mul v405, v407 - v409 = sub Field 1, v407 - v410 = mul v409, v404 - v411 = add v408, v410 - v412 = mul v411, v411 - v413 = mul v412, Field 2 - v415 = array_get v13, index Field 13 - v416 = mul v413, v415 - v417 = sub Field 1, v415 - v418 = mul v417, v412 - v419 = add v416, v418 - v420 = mul v419, v419 - v421 = mul v420, Field 2 - v423 = array_get v13, index Field 12 - v424 = mul v421, v423 - v425 = sub Field 1, v423 - v426 = mul v425, v420 - v427 = add v424, v426 - v428 = mul v427, v427 - v429 = mul v428, Field 2 - v431 = array_get v13, index Field 11 - v432 = mul v429, v431 - v433 = sub Field 1, v431 - v434 = mul v433, v428 - v435 = add v432, v434 - v436 = mul v435, v435 - v437 = mul v436, Field 2 - v439 = array_get v13, index Field 10 - v440 = mul v437, v439 - v441 = sub Field 1, v439 - v442 = mul v441, v436 - v443 = add v440, v442 - v444 = mul v443, v443 - v445 = mul v444, Field 2 - v447 = array_get v13, index Field 9 - v448 = mul v445, v447 - v449 = sub Field 1, v447 - v450 = mul v449, v444 - v451 = add v448, v450 - v452 = mul v451, v451 - v453 = mul v452, Field 2 - v455 = array_get v13, index Field 8 - v456 = mul v453, v455 - v457 = sub Field 1, v455 - v458 = mul v457, v452 - v459 = add v456, v458 - v460 = mul v459, v459 - v461 = mul v460, Field 2 - v463 = array_get v13, index Field 7 - v464 = mul v461, v463 - v465 = sub Field 1, v463 - v466 = mul v465, v460 - v467 = add v464, v466 - v468 = mul v467, v467 - v469 = mul v468, Field 2 - v471 = array_get v13, index Field 6 - v472 = mul v469, v471 - v473 = sub Field 1, v471 - v474 = mul v473, v468 - v475 = add v472, v474 - v476 = mul v475, v475 - v477 = mul v476, Field 2 - v479 = array_get v13, index Field 5 - v480 = mul v477, v479 - v481 = sub Field 1, v479 - v482 = mul v481, v476 - v483 = add v480, v482 - v484 = mul v483, v483 - v485 = mul v484, Field 2 - v487 = array_get v13, index Field 4 - v488 = mul v485, v487 - v489 = sub Field 1, v487 - v490 = mul v489, v484 - v491 = add v488, v490 - v492 = mul v491, v491 - v493 = mul v492, Field 2 - v495 = array_get v13, index Field 3 - v496 = mul v493, v495 - v497 = sub Field 1, v495 - v498 = mul v497, v492 - v499 = add v496, v498 - v500 = mul v499, v499 - v501 = mul v500, Field 2 - v502 = array_get v13, index Field 2 - v503 = mul v501, v502 - v504 = sub Field 1, v502 - v505 = mul v504, v500 - v506 = add v503, v505 - v507 = mul v506, v506 - v508 = mul v507, Field 2 - v509 = array_get v13, index Field 1 - v510 = mul v508, v509 - v511 = sub Field 1, v509 - v512 = mul v511, v507 - v513 = add v510, v512 - v514 = mul v513, v513 - v515 = mul v514, Field 2 - v517 = array_get v13, index Field 0 - v518 = mul v515, v517 - v519 = sub Field 1, v517 - v520 = mul v519, v514 - v521 = add v518, v520 - v522 = truncate v521 to 64 bits, max_bit_size: 254 - v523 = cast v522 as u64 - v524 = mul v9, v523 - v525 = truncate v524 to 64 bits, max_bit_size: 254 - v526 = lt v0, u64 2⁶ - constrain v526 == u1 1 'attempt to bit-shift with overflow' - v527 = or v3, v525 - store v527 at v2 - v528 = load v2 - return v528 -} - -After Defunctionalization: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - v3, v4 = call f1(v0, v1) - inc_rc v3 - inc_rc v3 - v6 = eq v4, Field 5 - constrain v4 == Field 5 - v10 = array_get v3, index Field 0 - v11 = array_get v3, index Field 1 - v13 = array_get v3, index Field 2 - v15 = array_get v3, index Field 3 - v17 = array_get v3, index Field 4 - v25 = allocate - store u1 1 at v25 - jmp b1(Field 0) - b1(v26: Field): - v27 = lt v26, Field 5 - jmpif v27 then: b2, else: b3 - b2(): - v28 = array_get [v10, v11, v13, v15, v17], index v26 - v29 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v26 - v30 = eq v28, v29 - v31 = load v25 - v32 = mul v31, v30 - store v32 at v25 - v33 = add v26, Field 1 - jmp b1(v33) - b3(): - v34 = load v25 - constrain v34 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v57, v58 = call f2([u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], Field 20) - inc_rc v57 - v61 = allocate - store u1 1 at v61 - jmp b4(Field 0) - b4(v62: Field): - v64 = lt v62, Field 2⁵ - jmpif v64 then: b5, else: b6 - b5(): - v65 = array_get v57, index v62 - v66 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v62 - v67 = eq v65, v66 - v68 = load v61 - v69 = mul v68, v67 - store v69 at v61 - v70 = add v62, Field 1 - jmp b4(v70) - b6(): - v71 = load v61 - constrain v71 == u1 1 - v73 = eq v58, Field 21 - constrain v58 == Field 21 - v75 = call f3() - v77 = eq v75, u64 1 - constrain v75 == u64 1 - v79 = call f4() - v81 = eq v79, u64 2⁴ - constrain v79 == u64 2⁴ - v84 = call f5(u64 0) - v85 = eq v84, u64 1 - constrain v84 == u64 1 - v88 = call f5(u64 4) - v89 = eq v88, u64 2⁴ - constrain v88 == u64 2⁴ - return -} -acir fn compact_decode f1 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - v11 = truncate v1 to 64 bits, max_bit_size: 254 - v12 = cast v11 as u64 - inc_rc v0 - v13 = lt u64 5, v12 - v14 = not v13 - constrain v13 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v18 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v18 - v20 = array_get v0, index Field 0 - v31 = div v20, Field 2⁴ - v32 = truncate v31 to 4 bits, max_bit_size: 8 - v33 = cast v32 as u4 - v34 = truncate v33 to 1 bits, max_bit_size: 4 - v35 = cast v34 as u1 - jmpif v35 then: b1, else: b2 - b1(): - v36 = load v18 - v37 = array_get v0, index Field 0 - v39 = and v37, u8 15 - v40 = truncate v39 to 4 bits, max_bit_size: 8 - v41 = cast v40 as u4 - v42 = array_set v36, index Field 0, value v41 - store v42 at v18 - inc_rc v0 - jmp b3(Field 1) - b3(v43: Field): - v44 = lt v43, Field 5 - jmpif v44 then: b4, else: b5 - b4(): - v45 = truncate v43 to 64 bits, max_bit_size: 254 - v46 = cast v45 as u64 - v47 = truncate v1 to 64 bits, max_bit_size: 254 - v48 = cast v47 as u64 - v49 = lt v46, v48 - jmpif v49 then: b6, else: b7 - b6(): - v50 = array_get v0, index v43 - v51 = load v18 - v52 = mul Field 2, v43 - v53 = sub v52, Field 1 - v55 = div v50, Field 2⁴ - v56 = truncate v55 to 4 bits, max_bit_size: 8 - v57 = cast v56 as u4 - v58 = array_set v51, index v53, value v57 - v59 = add v53, Field 1 - store v58 at v18 - v60 = load v18 - v61 = mul Field 2, v43 - v62 = and v50, u8 15 - v63 = truncate v62 to 4 bits, max_bit_size: 8 - v64 = cast v63 as u4 - v65 = array_set v60, index v61, value v64 - v66 = add v61, Field 1 - store v65 at v18 - jmp b7() - b7(): - v67 = add v43, Field 1 - jmp b3(v67) - b5(): - jmp b8() - b8(): - v95 = load v18 - v96 = mul Field 2, v1 - v97 = cast v35 as Field - v98 = add v96, v97 - v99 = sub v98, Field 2 - inc_rc v95 - return v95, v99 - b2(): - jmp b9(u64 0) - b9(v68: u64): - v70 = lt v68, u64 2 - jmpif v70 then: b10, else: b11 - b10(): - v71 = truncate v1 to 64 bits, max_bit_size: 254 - v72 = cast v71 as u64 - v74 = sub v72, u64 1 - range_check v74 to 64 bits - v75 = lt v68, v74 - jmpif v75 then: b12, else: b13 - b12(): - v76 = add v68, u64 1 - range_check v76 to 64 bits - v77 = array_get v0, index v76 - v78 = load v18 - v79 = mul u64 2, v68 - range_check v79 to 64 bits - v81 = div v77, Field 2⁴ - v82 = truncate v81 to 4 bits, max_bit_size: 8 - v83 = cast v82 as u4 - v84 = array_set v78, index v79, value v83 - v85 = add v79, Field 1 - store v84 at v18 - v86 = load v18 - v87 = mul u64 2, v68 - range_check v87 to 64 bits - v88 = add v87, u64 1 - range_check v88 to 64 bits - v89 = and v77, u8 15 - v90 = truncate v89 to 4 bits, max_bit_size: 8 - v91 = cast v90 as u4 - v92 = array_set v86, index v88, value v91 - v93 = add v88, Field 1 - store v92 at v18 - jmp b13() - b13(): - v94 = add v68, Field 1 - jmp b9(v94) - b11(): - jmp b8() -} -acir fn enc f2 { - b0(v0: [u8; 32], v1: Field): - inc_rc v0 - v5 = truncate v1 to 8 bits, max_bit_size: 254 - v6 = cast v5 as u8 - v7 = lt u8 2⁵, v6 - v8 = not v7 - constrain v7 == u1 0 - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v13 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v13 - v15 = eq v1, Field 0 - jmpif v15 then: b1, else: b2 - b1(): - v16 = load v13 - inc_rc v16 - jmp b3(v16, v1) - b3(v41: [u8; 32], v42: Field): - return v41, v42 - b2(): - v17 = truncate v1 to 8 bits, max_bit_size: 254 - v18 = cast v17 as u8 - v20 = lt v18, u8 31 - jmpif v20 then: b4, else: b5 - b4(): - v21 = load v13 - v23 = truncate v1 to 8 bits, max_bit_size: 254 - v24 = cast v23 as u8 - v25 = add u8 2⁷, v24 - range_check v25 to 8 bits - v27 = array_set v21, index Field 0, value v25 - store v27 at v13 - inc_rc v0 - jmp b6(Field 1) - b6(v28: Field): - v29 = lt v28, Field 2⁵ - jmpif v29 then: b7, else: b8 - b7(): - v30 = load v13 - v31 = sub v28, Field 1 - v32 = array_get v0, index v31 - v33 = array_set v30, index v28, value v32 - v34 = add v28, Field 1 - store v33 at v13 - v35 = add v28, Field 1 - jmp b6(v35) - b8(): - v36 = load v13 - v37 = add v1, Field 1 - inc_rc v36 - jmp b9(v36, v37) - b9(v39: [u8; 32], v40: Field): - jmp b3(v39, v40) - b5(): - v38 = load v13 - inc_rc v38 - jmp b9(v38, Field 2⁵) -} -acir fn bitshift_literal_0 f3 { - b0(): - v1 = allocate - store u64 0 at v1 - v2 = load v1 - v7 = or v2, u64 1 - store v7 at v1 - v8 = load v1 - return v8 -} -acir fn bitshift_literal_4 f4 { - b0(): - v1 = allocate - store u64 0 at v1 - v2 = load v1 - v9 = or v2, u64 2⁴ - store v9 at v1 - v10 = load v1 - return v10 -} -acir fn bitshift_variable f5 { - b0(v0: u64): - v2 = allocate - store u64 0 at v2 - v3 = load v2 - v7 = lt v0, u64 2⁶ - v9 = cast v7 as u64 - v12, v13 = call to_le_bits(v0, Field 2⁶) - v16 = array_get v13, index Field 63 - v17 = mul Field 2, v16 - v18 = sub Field 1, v16 - v19 = add v17, v18 - v20 = mul v19, v19 - v21 = mul v20, Field 2 - v23 = array_get v13, index Field 62 - v24 = mul v21, v23 - v25 = sub Field 1, v23 - v26 = mul v25, v20 - v27 = add v24, v26 - v28 = mul v27, v27 - v29 = mul v28, Field 2 - v31 = array_get v13, index Field 61 - v32 = mul v29, v31 - v33 = sub Field 1, v31 - v34 = mul v33, v28 - v35 = add v32, v34 - v36 = mul v35, v35 - v37 = mul v36, Field 2 - v39 = array_get v13, index Field 60 - v40 = mul v37, v39 - v41 = sub Field 1, v39 - v42 = mul v41, v36 - v43 = add v40, v42 - v44 = mul v43, v43 - v45 = mul v44, Field 2 - v47 = array_get v13, index Field 59 - v48 = mul v45, v47 - v49 = sub Field 1, v47 - v50 = mul v49, v44 - v51 = add v48, v50 - v52 = mul v51, v51 - v53 = mul v52, Field 2 - v55 = array_get v13, index Field 58 - v56 = mul v53, v55 - v57 = sub Field 1, v55 - v58 = mul v57, v52 - v59 = add v56, v58 - v60 = mul v59, v59 - v61 = mul v60, Field 2 - v63 = array_get v13, index Field 57 - v64 = mul v61, v63 - v65 = sub Field 1, v63 - v66 = mul v65, v60 - v67 = add v64, v66 - v68 = mul v67, v67 - v69 = mul v68, Field 2 - v71 = array_get v13, index Field 56 - v72 = mul v69, v71 - v73 = sub Field 1, v71 - v74 = mul v73, v68 - v75 = add v72, v74 - v76 = mul v75, v75 - v77 = mul v76, Field 2 - v79 = array_get v13, index Field 55 - v80 = mul v77, v79 - v81 = sub Field 1, v79 - v82 = mul v81, v76 - v83 = add v80, v82 - v84 = mul v83, v83 - v85 = mul v84, Field 2 - v87 = array_get v13, index Field 54 - v88 = mul v85, v87 - v89 = sub Field 1, v87 - v90 = mul v89, v84 - v91 = add v88, v90 - v92 = mul v91, v91 - v93 = mul v92, Field 2 - v95 = array_get v13, index Field 53 - v96 = mul v93, v95 - v97 = sub Field 1, v95 - v98 = mul v97, v92 - v99 = add v96, v98 - v100 = mul v99, v99 - v101 = mul v100, Field 2 - v103 = array_get v13, index Field 52 - v104 = mul v101, v103 - v105 = sub Field 1, v103 - v106 = mul v105, v100 - v107 = add v104, v106 - v108 = mul v107, v107 - v109 = mul v108, Field 2 - v111 = array_get v13, index Field 51 - v112 = mul v109, v111 - v113 = sub Field 1, v111 - v114 = mul v113, v108 - v115 = add v112, v114 - v116 = mul v115, v115 - v117 = mul v116, Field 2 - v119 = array_get v13, index Field 50 - v120 = mul v117, v119 - v121 = sub Field 1, v119 - v122 = mul v121, v116 - v123 = add v120, v122 - v124 = mul v123, v123 - v125 = mul v124, Field 2 - v127 = array_get v13, index Field 49 - v128 = mul v125, v127 - v129 = sub Field 1, v127 - v130 = mul v129, v124 - v131 = add v128, v130 - v132 = mul v131, v131 - v133 = mul v132, Field 2 - v135 = array_get v13, index Field 2⁴×3 - v136 = mul v133, v135 - v137 = sub Field 1, v135 - v138 = mul v137, v132 - v139 = add v136, v138 - v140 = mul v139, v139 - v141 = mul v140, Field 2 - v143 = array_get v13, index Field 47 - v144 = mul v141, v143 - v145 = sub Field 1, v143 - v146 = mul v145, v140 - v147 = add v144, v146 - v148 = mul v147, v147 - v149 = mul v148, Field 2 - v151 = array_get v13, index Field 46 - v152 = mul v149, v151 - v153 = sub Field 1, v151 - v154 = mul v153, v148 - v155 = add v152, v154 - v156 = mul v155, v155 - v157 = mul v156, Field 2 - v159 = array_get v13, index Field 45 - v160 = mul v157, v159 - v161 = sub Field 1, v159 - v162 = mul v161, v156 - v163 = add v160, v162 - v164 = mul v163, v163 - v165 = mul v164, Field 2 - v167 = array_get v13, index Field 44 - v168 = mul v165, v167 - v169 = sub Field 1, v167 - v170 = mul v169, v164 - v171 = add v168, v170 - v172 = mul v171, v171 - v173 = mul v172, Field 2 - v175 = array_get v13, index Field 43 - v176 = mul v173, v175 - v177 = sub Field 1, v175 - v178 = mul v177, v172 - v179 = add v176, v178 - v180 = mul v179, v179 - v181 = mul v180, Field 2 - v183 = array_get v13, index Field 42 - v184 = mul v181, v183 - v185 = sub Field 1, v183 - v186 = mul v185, v180 - v187 = add v184, v186 - v188 = mul v187, v187 - v189 = mul v188, Field 2 - v191 = array_get v13, index Field 41 - v192 = mul v189, v191 - v193 = sub Field 1, v191 - v194 = mul v193, v188 - v195 = add v192, v194 - v196 = mul v195, v195 - v197 = mul v196, Field 2 - v199 = array_get v13, index Field 40 - v200 = mul v197, v199 - v201 = sub Field 1, v199 - v202 = mul v201, v196 - v203 = add v200, v202 - v204 = mul v203, v203 - v205 = mul v204, Field 2 - v207 = array_get v13, index Field 39 - v208 = mul v205, v207 - v209 = sub Field 1, v207 - v210 = mul v209, v204 - v211 = add v208, v210 - v212 = mul v211, v211 - v213 = mul v212, Field 2 - v215 = array_get v13, index Field 38 - v216 = mul v213, v215 - v217 = sub Field 1, v215 - v218 = mul v217, v212 - v219 = add v216, v218 - v220 = mul v219, v219 - v221 = mul v220, Field 2 - v223 = array_get v13, index Field 37 - v224 = mul v221, v223 - v225 = sub Field 1, v223 - v226 = mul v225, v220 - v227 = add v224, v226 - v228 = mul v227, v227 - v229 = mul v228, Field 2 - v231 = array_get v13, index Field 36 - v232 = mul v229, v231 - v233 = sub Field 1, v231 - v234 = mul v233, v228 - v235 = add v232, v234 - v236 = mul v235, v235 - v237 = mul v236, Field 2 - v239 = array_get v13, index Field 35 - v240 = mul v237, v239 - v241 = sub Field 1, v239 - v242 = mul v241, v236 - v243 = add v240, v242 - v244 = mul v243, v243 - v245 = mul v244, Field 2 - v247 = array_get v13, index Field 34 - v248 = mul v245, v247 - v249 = sub Field 1, v247 - v250 = mul v249, v244 - v251 = add v248, v250 - v252 = mul v251, v251 - v253 = mul v252, Field 2 - v255 = array_get v13, index Field 33 - v256 = mul v253, v255 - v257 = sub Field 1, v255 - v258 = mul v257, v252 - v259 = add v256, v258 - v260 = mul v259, v259 - v261 = mul v260, Field 2 - v263 = array_get v13, index Field 2⁵ - v264 = mul v261, v263 - v265 = sub Field 1, v263 - v266 = mul v265, v260 - v267 = add v264, v266 - v268 = mul v267, v267 - v269 = mul v268, Field 2 - v271 = array_get v13, index Field 31 - v272 = mul v269, v271 - v273 = sub Field 1, v271 - v274 = mul v273, v268 - v275 = add v272, v274 - v276 = mul v275, v275 - v277 = mul v276, Field 2 - v279 = array_get v13, index Field 30 - v280 = mul v277, v279 - v281 = sub Field 1, v279 - v282 = mul v281, v276 - v283 = add v280, v282 - v284 = mul v283, v283 - v285 = mul v284, Field 2 - v287 = array_get v13, index Field 29 - v288 = mul v285, v287 - v289 = sub Field 1, v287 - v290 = mul v289, v284 - v291 = add v288, v290 - v292 = mul v291, v291 - v293 = mul v292, Field 2 - v295 = array_get v13, index Field 28 - v296 = mul v293, v295 - v297 = sub Field 1, v295 - v298 = mul v297, v292 - v299 = add v296, v298 - v300 = mul v299, v299 - v301 = mul v300, Field 2 - v303 = array_get v13, index Field 27 - v304 = mul v301, v303 - v305 = sub Field 1, v303 - v306 = mul v305, v300 - v307 = add v304, v306 - v308 = mul v307, v307 - v309 = mul v308, Field 2 - v311 = array_get v13, index Field 26 - v312 = mul v309, v311 - v313 = sub Field 1, v311 - v314 = mul v313, v308 - v315 = add v312, v314 - v316 = mul v315, v315 - v317 = mul v316, Field 2 - v319 = array_get v13, index Field 25 - v320 = mul v317, v319 - v321 = sub Field 1, v319 - v322 = mul v321, v316 - v323 = add v320, v322 - v324 = mul v323, v323 - v325 = mul v324, Field 2 - v327 = array_get v13, index Field 24 - v328 = mul v325, v327 - v329 = sub Field 1, v327 - v330 = mul v329, v324 - v331 = add v328, v330 - v332 = mul v331, v331 - v333 = mul v332, Field 2 - v335 = array_get v13, index Field 23 - v336 = mul v333, v335 - v337 = sub Field 1, v335 - v338 = mul v337, v332 - v339 = add v336, v338 - v340 = mul v339, v339 - v341 = mul v340, Field 2 - v343 = array_get v13, index Field 22 - v344 = mul v341, v343 - v345 = sub Field 1, v343 - v346 = mul v345, v340 - v347 = add v344, v346 - v348 = mul v347, v347 - v349 = mul v348, Field 2 - v351 = array_get v13, index Field 21 - v352 = mul v349, v351 - v353 = sub Field 1, v351 - v354 = mul v353, v348 - v355 = add v352, v354 - v356 = mul v355, v355 - v357 = mul v356, Field 2 - v359 = array_get v13, index Field 20 - v360 = mul v357, v359 - v361 = sub Field 1, v359 - v362 = mul v361, v356 - v363 = add v360, v362 - v364 = mul v363, v363 - v365 = mul v364, Field 2 - v367 = array_get v13, index Field 19 - v368 = mul v365, v367 - v369 = sub Field 1, v367 - v370 = mul v369, v364 - v371 = add v368, v370 - v372 = mul v371, v371 - v373 = mul v372, Field 2 - v375 = array_get v13, index Field 18 - v376 = mul v373, v375 - v377 = sub Field 1, v375 - v378 = mul v377, v372 - v379 = add v376, v378 - v380 = mul v379, v379 - v381 = mul v380, Field 2 - v383 = array_get v13, index Field 17 - v384 = mul v381, v383 - v385 = sub Field 1, v383 - v386 = mul v385, v380 - v387 = add v384, v386 - v388 = mul v387, v387 - v389 = mul v388, Field 2 - v391 = array_get v13, index Field 2⁴ - v392 = mul v389, v391 - v393 = sub Field 1, v391 - v394 = mul v393, v388 - v395 = add v392, v394 - v396 = mul v395, v395 - v397 = mul v396, Field 2 - v399 = array_get v13, index Field 15 - v400 = mul v397, v399 - v401 = sub Field 1, v399 - v402 = mul v401, v396 - v403 = add v400, v402 - v404 = mul v403, v403 - v405 = mul v404, Field 2 - v407 = array_get v13, index Field 14 - v408 = mul v405, v407 - v409 = sub Field 1, v407 - v410 = mul v409, v404 - v411 = add v408, v410 - v412 = mul v411, v411 - v413 = mul v412, Field 2 - v415 = array_get v13, index Field 13 - v416 = mul v413, v415 - v417 = sub Field 1, v415 - v418 = mul v417, v412 - v419 = add v416, v418 - v420 = mul v419, v419 - v421 = mul v420, Field 2 - v423 = array_get v13, index Field 12 - v424 = mul v421, v423 - v425 = sub Field 1, v423 - v426 = mul v425, v420 - v427 = add v424, v426 - v428 = mul v427, v427 - v429 = mul v428, Field 2 - v431 = array_get v13, index Field 11 - v432 = mul v429, v431 - v433 = sub Field 1, v431 - v434 = mul v433, v428 - v435 = add v432, v434 - v436 = mul v435, v435 - v437 = mul v436, Field 2 - v439 = array_get v13, index Field 10 - v440 = mul v437, v439 - v441 = sub Field 1, v439 - v442 = mul v441, v436 - v443 = add v440, v442 - v444 = mul v443, v443 - v445 = mul v444, Field 2 - v447 = array_get v13, index Field 9 - v448 = mul v445, v447 - v449 = sub Field 1, v447 - v450 = mul v449, v444 - v451 = add v448, v450 - v452 = mul v451, v451 - v453 = mul v452, Field 2 - v455 = array_get v13, index Field 8 - v456 = mul v453, v455 - v457 = sub Field 1, v455 - v458 = mul v457, v452 - v459 = add v456, v458 - v460 = mul v459, v459 - v461 = mul v460, Field 2 - v463 = array_get v13, index Field 7 - v464 = mul v461, v463 - v465 = sub Field 1, v463 - v466 = mul v465, v460 - v467 = add v464, v466 - v468 = mul v467, v467 - v469 = mul v468, Field 2 - v471 = array_get v13, index Field 6 - v472 = mul v469, v471 - v473 = sub Field 1, v471 - v474 = mul v473, v468 - v475 = add v472, v474 - v476 = mul v475, v475 - v477 = mul v476, Field 2 - v479 = array_get v13, index Field 5 - v480 = mul v477, v479 - v481 = sub Field 1, v479 - v482 = mul v481, v476 - v483 = add v480, v482 - v484 = mul v483, v483 - v485 = mul v484, Field 2 - v487 = array_get v13, index Field 4 - v488 = mul v485, v487 - v489 = sub Field 1, v487 - v490 = mul v489, v484 - v491 = add v488, v490 - v492 = mul v491, v491 - v493 = mul v492, Field 2 - v495 = array_get v13, index Field 3 - v496 = mul v493, v495 - v497 = sub Field 1, v495 - v498 = mul v497, v492 - v499 = add v496, v498 - v500 = mul v499, v499 - v501 = mul v500, Field 2 - v502 = array_get v13, index Field 2 - v503 = mul v501, v502 - v504 = sub Field 1, v502 - v505 = mul v504, v500 - v506 = add v503, v505 - v507 = mul v506, v506 - v508 = mul v507, Field 2 - v509 = array_get v13, index Field 1 - v510 = mul v508, v509 - v511 = sub Field 1, v509 - v512 = mul v511, v507 - v513 = add v510, v512 - v514 = mul v513, v513 - v515 = mul v514, Field 2 - v517 = array_get v13, index Field 0 - v518 = mul v515, v517 - v519 = sub Field 1, v517 - v520 = mul v519, v514 - v521 = add v518, v520 - v522 = truncate v521 to 64 bits, max_bit_size: 254 - v523 = cast v522 as u64 - v524 = mul v9, v523 - v525 = truncate v524 to 64 bits, max_bit_size: 254 - v526 = lt v0, u64 2⁶ - constrain v526 == u1 1 'attempt to bit-shift with overflow' - v527 = or v3, v525 - store v527 at v2 - v528 = load v2 - return v528 -} - -After Inlining: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v3 = truncate v1 to 64 bits, max_bit_size: 254 - v4 = cast v3 as u64 - inc_rc v0 - v6 = lt u64 5, v4 - v7 = not v6 - constrain v6 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v11 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v11 - v13 = array_get v0, index Field 0 - v15 = div v13, Field 2⁴ - v16 = truncate v15 to 4 bits, max_bit_size: 8 - v17 = cast v16 as u4 - v18 = truncate v17 to 1 bits, max_bit_size: 4 - v19 = cast v18 as u1 - jmpif v19 then: b1, else: b2 - b1(): - v55 = load v11 - v56 = array_get v0, index Field 0 - v57 = and v56, u8 15 - v58 = truncate v57 to 4 bits, max_bit_size: 8 - v59 = cast v58 as u4 - v60 = array_set v55, index Field 0, value v59 - store v60 at v11 - inc_rc v0 - jmp b9(Field 1) - b9(v61: Field): - v63 = lt v61, Field 5 - jmpif v63 then: b10, else: b11 - b10(): - v64 = truncate v61 to 64 bits, max_bit_size: 254 - v65 = cast v64 as u64 - v66 = truncate v1 to 64 bits, max_bit_size: 254 - v67 = cast v66 as u64 - v68 = lt v65, v67 - jmpif v68 then: b12, else: b13 - b12(): - v70 = array_get v0, index v61 - v71 = load v11 - v72 = mul Field 2, v61 - v73 = sub v72, Field 1 - v74 = div v70, Field 2⁴ - v75 = truncate v74 to 4 bits, max_bit_size: 8 - v76 = cast v75 as u4 - v77 = array_set v71, index v73, value v76 - v78 = add v73, Field 1 - store v77 at v11 - v79 = load v11 - v80 = mul Field 2, v61 - v81 = and v70, u8 15 - v82 = truncate v81 to 4 bits, max_bit_size: 8 - v83 = cast v82 as u4 - v84 = array_set v79, index v80, value v83 - v85 = add v80, Field 1 - store v84 at v11 - jmp b13() - b13(): - v69 = add v61, Field 1 - jmp b9(v69) - b11(): - jmp b6() - b6(): - v24 = load v11 - v26 = mul Field 2, v1 - v27 = cast v19 as Field - v28 = add v26, v27 - v29 = sub v28, Field 2 - inc_rc v24 - inc_rc v24 - inc_rc v24 - v86 = eq v29, Field 5 - constrain v29 == Field 5 - v87 = array_get v24, index Field 0 - v88 = array_get v24, index Field 1 - v89 = array_get v24, index Field 2 - v91 = array_get v24, index Field 3 - v93 = array_get v24, index Field 4 - v94 = allocate - store u1 1 at v94 - jmp b14(Field 0) - b14(v96: Field): - v97 = lt v96, Field 5 - jmpif v97 then: b15, else: b16 - b15(): - v242 = array_get [v87, v88, v89, v91, v93], index v96 - v249 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v96 - v250 = eq v242, v249 - v251 = load v94 - v252 = mul v251, v250 - store v252 at v94 - v253 = add v96, Field 1 - jmp b14(v253) - b16(): - v98 = load v94 - constrain v98 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v124 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v124 - jmp b17() - b17(): - jmp b18() - b18(): - v126 = load v124 - range_check u8 148 to 8 bits - v128 = array_set v126, index Field 0, value u8 148 - store v128 at v124 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - jmp b19(Field 1) - b19(v129: Field): - v131 = lt v129, Field 2⁵ - jmpif v131 then: b20, else: b21 - b20(): - v138 = load v124 - v139 = sub v129, Field 1 - v140 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v139 - v141 = array_set v138, index v129, value v140 - v142 = add v129, Field 1 - store v141 at v124 - v143 = add v129, Field 1 - jmp b19(v143) - b21(): - v132 = load v124 - inc_rc v132 - jmp b22(v132, Field 21) - b22(v134: [u8; 32], v135: Field): - jmp b23(v134, v135) - b23(v136: [u8; 32], v137: Field): - inc_rc v136 - v144 = allocate - store u1 1 at v144 - jmp b24(Field 0) - b24(v145: Field): - v146 = lt v145, Field 2⁵ - jmpif v146 then: b25, else: b26 - b25(): - v234 = array_get v136, index v145 - v236 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v145 - v237 = eq v234, v236 - v238 = load v144 - v239 = mul v238, v237 - store v239 at v144 - v240 = add v145, Field 1 - jmp b24(v240) - b26(): - v147 = load v144 - constrain v147 == u1 1 - v148 = eq v137, Field 21 - constrain v137 == Field 21 - v150 = allocate - store u64 0 at v150 - v151 = load v150 - v152 = or v151, u64 1 - store v152 at v150 - v153 = load v150 - v154 = eq v153, u64 1 - constrain v153 == u64 1 - v156 = allocate - store u64 0 at v156 - v157 = load v156 - v159 = or v157, u64 2⁴ - store v159 at v156 - v160 = load v156 - v161 = eq v160, u64 2⁴ - constrain v160 == u64 2⁴ - v163 = allocate - store u64 0 at v163 - v164 = load v163 - v223 = or v164, u64 1 - store v223 at v163 - v224 = load v163 - v225 = eq v224, u64 1 - constrain v224 == u64 1 - v228 = allocate - store u64 0 at v228 - v229 = load v228 - v231 = or v229, u64 2⁴ - store v231 at v228 - v232 = load v228 - v233 = eq v232, u64 2⁴ - constrain v232 == u64 2⁴ - return - b2(): - jmp b3(u64 0) - b3(v20: u64): - v23 = lt v20, u64 2 - jmpif v23 then: b4, else: b5 - b4(): - v30 = truncate v1 to 64 bits, max_bit_size: 254 - v31 = cast v30 as u64 - v33 = sub v31, u64 1 - range_check v33 to 64 bits - v34 = lt v20, v33 - jmpif v34 then: b7, else: b8 - b7(): - v37 = add v20, u64 1 - range_check v37 to 64 bits - v38 = array_get v0, index v37 - v39 = load v11 - v40 = mul u64 2, v20 - range_check v40 to 64 bits - v41 = div v38, Field 2⁴ - v42 = truncate v41 to 4 bits, max_bit_size: 8 - v43 = cast v42 as u4 - v44 = array_set v39, index v40, value v43 - v45 = add v40, Field 1 - store v44 at v11 - v46 = load v11 - v47 = mul u64 2, v20 - range_check v47 to 64 bits - v48 = add v47, u64 1 - range_check v48 to 64 bits - v50 = and v38, u8 15 - v51 = truncate v50 to 4 bits, max_bit_size: 8 - v52 = cast v51 as u4 - v53 = array_set v46, index v48, value v52 - v54 = add v48, Field 1 - store v53 at v11 - jmp b8() - b8(): - v36 = add v20, Field 1 - jmp b3(v36) - b5(): - jmp b6() -} - -After Mem2Reg: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v254 = truncate v1 to 64 bits, max_bit_size: 254 - v255 = cast v254 as u64 - inc_rc v0 - v256 = lt u64 5, v255 - v257 = not v256 - constrain v256 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v259 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 - v261 = array_get v0, index Field 0 - v262 = div v261, Field 2⁴ - v263 = truncate v262 to 4 bits, max_bit_size: 8 - v264 = cast v263 as u4 - v265 = truncate v264 to 1 bits, max_bit_size: 4 - v266 = cast v265 as u1 - jmpif v266 then: b1, else: b2 - b1(): - v291 = array_get v0, index Field 0 - v292 = and v291, u8 15 - v293 = truncate v292 to 4 bits, max_bit_size: 8 - v294 = cast v293 as u4 - store [v294, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 - inc_rc v0 - jmp b9(Field 1) - b9(v61: Field): - v298 = lt v61, Field 5 - jmpif v298 then: b10, else: b11 - b10(): - v364 = truncate v61 to 64 bits, max_bit_size: 254 - v365 = cast v364 as u64 - v366 = truncate v1 to 64 bits, max_bit_size: 254 - v367 = cast v366 as u64 - v368 = lt v365, v367 - jmpif v368 then: b12, else: b13 - b12(): - v369 = array_get v0, index v61 - v370 = load v259 - v371 = mul Field 2, v61 - v372 = sub v371, Field 1 - v373 = div v369, Field 2⁴ - v374 = truncate v373 to 4 bits, max_bit_size: 8 - v375 = cast v374 as u4 - v376 = array_set v370, index v372, value v375 - v377 = add v372, Field 1 - v379 = mul Field 2, v61 - v380 = and v369, u8 15 - v381 = truncate v380 to 4 bits, max_bit_size: 8 - v382 = cast v381 as u4 - v383 = array_set v376, index v379, value v382 - v384 = add v379, Field 1 - store v383 at v259 - jmp b13() - b13(): - v385 = add v61, Field 1 - jmp b9(v385) - b11(): - jmp b6() - b6(): - v299 = load v259 - v300 = mul Field 2, v1 - v301 = cast v266 as Field - v302 = add v300, v301 - v303 = sub v302, Field 2 - inc_rc v299 - inc_rc v299 - inc_rc v299 - v304 = eq v303, Field 5 - constrain v303 == Field 5 - v305 = array_get v299, index Field 0 - v306 = array_get v299, index Field 1 - v307 = array_get v299, index Field 2 - v308 = array_get v299, index Field 3 - v309 = array_get v299, index Field 4 - v310 = allocate - store u1 1 at v310 - jmp b14(Field 0) - b14(v96: Field): - v311 = lt v96, Field 5 - jmpif v311 then: b15, else: b16 - b15(): - v357 = array_get [v305, v306, v307, v308, v309], index v96 - v359 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v96 - v360 = eq v357, v359 - v361 = load v310 - v362 = mul v361, v360 - store v362 at v310 - v363 = add v96, Field 1 - jmp b14(v363) - b16(): - v312 = load v310 - constrain v312 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v317 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 - jmp b17() - b17(): - jmp b18() - b18(): - range_check u8 148 to 8 bits - store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - jmp b19(Field 1) - b19(v129: Field): - v324 = lt v129, Field 2⁵ - jmpif v324 then: b20, else: b21 - b20(): - v349 = load v317 - v350 = sub v129, Field 1 - v352 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v350 - v353 = array_set v349, index v129, value v352 - v354 = add v129, Field 1 - store v353 at v317 - v355 = add v129, Field 1 - jmp b19(v355) - b21(): - v325 = load v317 - inc_rc v325 - jmp b22(v325, Field 21) - b22(v134: [u8; 32], v135: Field): - jmp b23(v134, v135) - b23(v136: [u8; 32], v137: Field): - inc_rc v136 - v326 = allocate - store u1 1 at v326 - jmp b24(Field 0) - b24(v145: Field): - v327 = lt v145, Field 2⁵ - jmpif v327 then: b25, else: b26 - b25(): - v342 = array_get v136, index v145 - v344 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v145 - v345 = eq v342, v344 - v346 = load v326 - v347 = mul v346, v345 - store v347 at v326 - v348 = add v145, Field 1 - jmp b24(v348) - b26(): - v328 = load v326 - constrain v328 == u1 1 - v329 = eq v137, Field 21 - constrain v137 == Field 21 - v330 = allocate - store u64 1 at v330 - v333 = allocate - store u64 2⁴ at v333 - v336 = allocate - store u64 1 at v336 - v339 = allocate - store u64 2⁴ at v339 - return - b2(): - jmp b3(u64 0) - b3(v20: u64): - v267 = lt v20, u64 2 - jmpif v267 then: b4, else: b5 - b4(): - v268 = truncate v1 to 64 bits, max_bit_size: 254 - v269 = cast v268 as u64 - v270 = sub v269, u64 1 - range_check v270 to 64 bits - v271 = lt v20, v270 - jmpif v271 then: b7, else: b8 - b7(): - v272 = add v20, u64 1 - range_check v272 to 64 bits - v273 = array_get v0, index v272 - v274 = load v259 - v275 = mul u64 2, v20 - range_check v275 to 64 bits - v276 = div v273, Field 2⁴ - v277 = truncate v276 to 4 bits, max_bit_size: 8 - v278 = cast v277 as u4 - v279 = array_set v274, index v275, value v278 - v280 = add v275, Field 1 - v282 = mul u64 2, v20 - range_check v282 to 64 bits - v283 = add v282, u64 1 - range_check v283 to 64 bits - v284 = and v273, u8 15 - v285 = truncate v284 to 4 bits, max_bit_size: 8 - v286 = cast v285 as u4 - v287 = array_set v279, index v283, value v286 - v288 = add v283, Field 1 - store v287 at v259 - jmp b8() - b8(): - v289 = add v20, Field 1 - jmp b3(v289) - b5(): - jmp b6() -} - -After Assert Constant: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v254 = truncate v1 to 64 bits, max_bit_size: 254 - v255 = cast v254 as u64 - inc_rc v0 - v256 = lt u64 5, v255 - v257 = not v256 - constrain v256 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v259 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 - v261 = array_get v0, index Field 0 - v262 = div v261, Field 2⁴ - v263 = truncate v262 to 4 bits, max_bit_size: 8 - v264 = cast v263 as u4 - v265 = truncate v264 to 1 bits, max_bit_size: 4 - v266 = cast v265 as u1 - jmpif v266 then: b1, else: b2 - b1(): - v291 = array_get v0, index Field 0 - v292 = and v291, u8 15 - v293 = truncate v292 to 4 bits, max_bit_size: 8 - v294 = cast v293 as u4 - store [v294, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 - inc_rc v0 - jmp b9(Field 1) - b9(v61: Field): - v298 = lt v61, Field 5 - jmpif v298 then: b10, else: b11 - b10(): - v364 = truncate v61 to 64 bits, max_bit_size: 254 - v365 = cast v364 as u64 - v366 = truncate v1 to 64 bits, max_bit_size: 254 - v367 = cast v366 as u64 - v368 = lt v365, v367 - jmpif v368 then: b12, else: b13 - b12(): - v369 = array_get v0, index v61 - v370 = load v259 - v371 = mul Field 2, v61 - v372 = sub v371, Field 1 - v373 = div v369, Field 2⁴ - v374 = truncate v373 to 4 bits, max_bit_size: 8 - v375 = cast v374 as u4 - v376 = array_set v370, index v372, value v375 - v377 = add v372, Field 1 - v379 = mul Field 2, v61 - v380 = and v369, u8 15 - v381 = truncate v380 to 4 bits, max_bit_size: 8 - v382 = cast v381 as u4 - v383 = array_set v376, index v379, value v382 - v384 = add v379, Field 1 - store v383 at v259 - jmp b13() - b13(): - v385 = add v61, Field 1 - jmp b9(v385) - b11(): - jmp b6() - b6(): - v299 = load v259 - v300 = mul Field 2, v1 - v301 = cast v266 as Field - v302 = add v300, v301 - v303 = sub v302, Field 2 - inc_rc v299 - inc_rc v299 - inc_rc v299 - v304 = eq v303, Field 5 - constrain v303 == Field 5 - v305 = array_get v299, index Field 0 - v306 = array_get v299, index Field 1 - v307 = array_get v299, index Field 2 - v308 = array_get v299, index Field 3 - v309 = array_get v299, index Field 4 - v310 = allocate - store u1 1 at v310 - jmp b14(Field 0) - b14(v96: Field): - v311 = lt v96, Field 5 - jmpif v311 then: b15, else: b16 - b15(): - v357 = array_get [v305, v306, v307, v308, v309], index v96 - v359 = array_get [u4 15, u4 1, u4 12, u4 11, u4 8], index v96 - v360 = eq v357, v359 - v361 = load v310 - v362 = mul v361, v360 - store v362 at v310 - v363 = add v96, Field 1 - jmp b14(v363) - b16(): - v312 = load v310 - constrain v312 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v317 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 - jmp b17() - b17(): - jmp b18() - b18(): - range_check u8 148 to 8 bits - store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - jmp b19(Field 1) - b19(v129: Field): - v324 = lt v129, Field 2⁵ - jmpif v324 then: b20, else: b21 - b20(): - v349 = load v317 - v350 = sub v129, Field 1 - v352 = array_get [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v350 - v353 = array_set v349, index v129, value v352 - v354 = add v129, Field 1 - store v353 at v317 - v355 = add v129, Field 1 - jmp b19(v355) - b21(): - v325 = load v317 - inc_rc v325 - jmp b22(v325, Field 21) - b22(v134: [u8; 32], v135: Field): - jmp b23(v134, v135) - b23(v136: [u8; 32], v137: Field): - inc_rc v136 - v326 = allocate - store u1 1 at v326 - jmp b24(Field 0) - b24(v145: Field): - v327 = lt v145, Field 2⁵ - jmpif v327 then: b25, else: b26 - b25(): - v342 = array_get v136, index v145 - v344 = array_get [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0], index v145 - v345 = eq v342, v344 - v346 = load v326 - v347 = mul v346, v345 - store v347 at v326 - v348 = add v145, Field 1 - jmp b24(v348) - b26(): - v328 = load v326 - constrain v328 == u1 1 - v329 = eq v137, Field 21 - constrain v137 == Field 21 - v330 = allocate - store u64 1 at v330 - v333 = allocate - store u64 2⁴ at v333 - v336 = allocate - store u64 1 at v336 - v339 = allocate - store u64 2⁴ at v339 - return - b2(): - jmp b3(u64 0) - b3(v20: u64): - v267 = lt v20, u64 2 - jmpif v267 then: b4, else: b5 - b4(): - v268 = truncate v1 to 64 bits, max_bit_size: 254 - v269 = cast v268 as u64 - v270 = sub v269, u64 1 - range_check v270 to 64 bits - v271 = lt v20, v270 - jmpif v271 then: b7, else: b8 - b7(): - v272 = add v20, u64 1 - range_check v272 to 64 bits - v273 = array_get v0, index v272 - v274 = load v259 - v275 = mul u64 2, v20 - range_check v275 to 64 bits - v276 = div v273, Field 2⁴ - v277 = truncate v276 to 4 bits, max_bit_size: 8 - v278 = cast v277 as u4 - v279 = array_set v274, index v275, value v278 - v280 = add v275, Field 1 - v282 = mul u64 2, v20 - range_check v282 to 64 bits - v283 = add v282, u64 1 - range_check v283 to 64 bits - v284 = and v273, u8 15 - v285 = truncate v284 to 4 bits, max_bit_size: 8 - v286 = cast v285 as u4 - v287 = array_set v279, index v283, value v286 - v288 = add v283, Field 1 - store v287 at v259 - jmp b8() - b8(): - v289 = add v20, Field 1 - jmp b3(v289) - b5(): - jmp b6() -} - -After Unrolling: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v254 = truncate v1 to 64 bits, max_bit_size: 254 - v255 = cast v254 as u64 - inc_rc v0 - v256 = lt u64 5, v255 - v257 = not v256 - constrain v256 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v259 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 - v261 = array_get v0, index Field 0 - v262 = div v261, Field 2⁴ - v263 = truncate v262 to 4 bits, max_bit_size: 8 - v264 = cast v263 as u4 - v265 = truncate v264 to 1 bits, max_bit_size: 4 - v266 = cast v265 as u1 - jmpif v266 then: b1, else: b2 - b1(): - v291 = array_get v0, index Field 0 - v292 = and v291, u8 15 - v293 = truncate v292 to 4 bits, max_bit_size: 8 - v294 = cast v293 as u4 - store [v294, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 - inc_rc v0 - v387 = truncate v1 to 64 bits, max_bit_size: 254 - v388 = cast v387 as u64 - v389 = lt u64 1, v388 - jmpif v389 then: b29, else: b30 - b29(): - v391 = array_get v0, index Field 1 - v392 = load v259 - v393 = div v391, Field 2⁴ - v394 = truncate v393 to 4 bits, max_bit_size: 8 - v395 = cast v394 as u4 - v396 = array_set v392, index Field 1, value v395 - v397 = and v391, u8 15 - v398 = truncate v397 to 4 bits, max_bit_size: 8 - v399 = cast v398 as u4 - v400 = array_set v396, index Field 2, value v399 - store v400 at v259 - jmp b30() - b30(): - v401 = truncate v1 to 64 bits, max_bit_size: 254 - v402 = cast v401 as u64 - v403 = lt u64 2, v402 - jmpif v403 then: b34, else: b35 - b34(): - v405 = array_get v0, index Field 2 - v406 = load v259 - v407 = div v405, Field 2⁴ - v408 = truncate v407 to 4 bits, max_bit_size: 8 - v409 = cast v408 as u4 - v410 = array_set v406, index Field 3, value v409 - v411 = and v405, u8 15 - v412 = truncate v411 to 4 bits, max_bit_size: 8 - v413 = cast v412 as u4 - v414 = array_set v410, index Field 4, value v413 - store v414 at v259 - jmp b35() - b35(): - v416 = truncate v1 to 64 bits, max_bit_size: 254 - v417 = cast v416 as u64 - v418 = lt u64 3, v417 - jmpif v418 then: b39, else: b40 - b39(): - v420 = array_get v0, index Field 3 - v421 = load v259 - v422 = div v420, Field 2⁴ - v423 = truncate v422 to 4 bits, max_bit_size: 8 - v424 = cast v423 as u4 - v425 = array_set v421, index Field 5, value v424 - v426 = and v420, u8 15 - v427 = truncate v426 to 4 bits, max_bit_size: 8 - v428 = cast v427 as u4 - v429 = array_set v425, index Field 6, value v428 - store v429 at v259 - jmp b40() - b40(): - v430 = truncate v1 to 64 bits, max_bit_size: 254 - v431 = cast v430 as u64 - v432 = lt u64 4, v431 - jmpif v432 then: b44, else: b45 - b44(): - v434 = array_get v0, index Field 4 - v435 = load v259 - v436 = div v434, Field 2⁴ - v437 = truncate v436 to 4 bits, max_bit_size: 8 - v438 = cast v437 as u4 - v439 = array_set v435, index Field 7, value v438 - v440 = and v434, u8 15 - v441 = truncate v440 to 4 bits, max_bit_size: 8 - v442 = cast v441 as u4 - v443 = array_set v439, index Field 8, value v442 - store v443 at v259 - jmp b45() - b45(): - jmp b11() - b11(): - jmp b6() - b6(): - v299 = load v259 - v300 = mul Field 2, v1 - v301 = cast v266 as Field - v302 = add v300, v301 - v303 = sub v302, Field 2 - inc_rc v299 - inc_rc v299 - inc_rc v299 - v304 = eq v303, Field 5 - constrain v303 == Field 5 - v305 = array_get v299, index Field 0 - v306 = array_get v299, index Field 1 - v307 = array_get v299, index Field 2 - v308 = array_get v299, index Field 3 - v309 = array_get v299, index Field 4 - v310 = allocate - store u1 1 at v310 - v792 = eq v305, u4 15 - v793 = load v310 - v794 = mul v793, v792 - store v794 at v310 - v798 = eq v306, u4 1 - v799 = load v310 - v800 = mul v799, v798 - store v800 at v310 - v804 = eq v307, u4 12 - v805 = load v310 - v806 = mul v805, v804 - store v806 at v310 - v810 = eq v308, u4 11 - v811 = load v310 - v812 = mul v811, v810 - store v812 at v310 - v816 = eq v309, u4 8 - v817 = load v310 - v818 = mul v817, v816 - store v818 at v310 - jmp b16() - b16(): - v312 = load v310 - constrain v312 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v317 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 - jmp b17() - b17(): - jmp b18() - b18(): - range_check u8 148 to 8 bits - store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v666 = load v317 - v668 = array_set v666, index Field 1, value u8 184 - store v668 at v317 - v670 = load v317 - v672 = array_set v670, index Field 2, value u8 143 - store v672 at v317 - v674 = load v317 - v676 = array_set v674, index Field 3, value u8 97 - store v676 at v317 - v678 = load v317 - v680 = array_set v678, index Field 4, value u8 230 - store v680 at v317 - v682 = load v317 - v684 = array_set v682, index Field 5, value u8 251 - store v684 at v317 - v686 = load v317 - v688 = array_set v686, index Field 6, value u8 218 - store v688 at v317 - v690 = load v317 - v692 = array_set v690, index Field 7, value u8 131 - store v692 at v317 - v694 = load v317 - v696 = array_set v694, index Field 8, value u8 251 - store v696 at v317 - v698 = load v317 - v700 = array_set v698, index Field 9, value u8 255 - store v700 at v317 - v702 = load v317 - v704 = array_set v702, index Field 10, value u8 250 - store v704 at v317 - v706 = load v317 - v708 = array_set v706, index Field 11, value u8 190 - store v708 at v317 - v710 = load v317 - v712 = array_set v710, index Field 12, value u8 54 - store v712 at v317 - v714 = load v317 - v716 = array_set v714, index Field 13, value u8 65 - store v716 at v317 - v718 = load v317 - v720 = array_set v718, index Field 14, value u8 18 - store v720 at v317 - v722 = load v317 - v724 = array_set v722, index Field 15, value u8 19 - store v724 at v317 - v726 = load v317 - v728 = array_set v726, index Field 2⁴, value u8 116 - store v728 at v317 - v730 = load v317 - v732 = array_set v730, index Field 17, value u8 2⁷ - store v732 at v317 - v734 = load v317 - v736 = array_set v734, index Field 18, value u8 57 - store v736 at v317 - v738 = load v317 - v740 = array_set v738, index Field 19, value u8 2⁷ - store v740 at v317 - v742 = load v317 - v744 = array_set v742, index Field 20, value u8 24 - store v744 at v317 - v746 = load v317 - v748 = array_set v746, index Field 21, value u8 0 - store v748 at v317 - v750 = load v317 - v752 = array_set v750, index Field 22, value u8 0 - store v752 at v317 - v754 = load v317 - v756 = array_set v754, index Field 23, value u8 0 - store v756 at v317 - v758 = load v317 - v760 = array_set v758, index Field 24, value u8 0 - store v760 at v317 - v762 = load v317 - v764 = array_set v762, index Field 25, value u8 0 - store v764 at v317 - v766 = load v317 - v768 = array_set v766, index Field 26, value u8 0 - store v768 at v317 - v770 = load v317 - v772 = array_set v770, index Field 27, value u8 0 - store v772 at v317 - v774 = load v317 - v776 = array_set v774, index Field 28, value u8 0 - store v776 at v317 - v778 = load v317 - v780 = array_set v778, index Field 29, value u8 0 - store v780 at v317 - v782 = load v317 - v784 = array_set v782, index Field 30, value u8 0 - store v784 at v317 - v786 = load v317 - v788 = array_set v786, index Field 31, value u8 0 - store v788 at v317 - jmp b21() - b21(): - v325 = load v317 - inc_rc v325 - jmp b22(v325, Field 21) - b22(v134: [u8; 32], v135: Field): - jmp b23(v134, v135) - b23(v136: [u8; 32], v137: Field): - inc_rc v136 - v326 = allocate - store u1 1 at v326 - v474 = array_get v136, index Field 0 - v476 = eq v474, u8 148 - v477 = load v326 - v478 = mul v477, v476 - store v478 at v326 - v480 = array_get v136, index Field 1 - v482 = eq v480, u8 184 - v483 = load v326 - v484 = mul v483, v482 - store v484 at v326 - v486 = array_get v136, index Field 2 - v488 = eq v486, u8 143 - v489 = load v326 - v490 = mul v489, v488 - store v490 at v326 - v492 = array_get v136, index Field 3 - v494 = eq v492, u8 97 - v495 = load v326 - v496 = mul v495, v494 - store v496 at v326 - v498 = array_get v136, index Field 4 - v500 = eq v498, u8 230 - v501 = load v326 - v502 = mul v501, v500 - store v502 at v326 - v504 = array_get v136, index Field 5 - v506 = eq v504, u8 251 - v507 = load v326 - v508 = mul v507, v506 - store v508 at v326 - v510 = array_get v136, index Field 6 - v512 = eq v510, u8 218 - v513 = load v326 - v514 = mul v513, v512 - store v514 at v326 - v516 = array_get v136, index Field 7 - v518 = eq v516, u8 131 - v519 = load v326 - v520 = mul v519, v518 - store v520 at v326 - v522 = array_get v136, index Field 8 - v524 = eq v522, u8 251 - v525 = load v326 - v526 = mul v525, v524 - store v526 at v326 - v528 = array_get v136, index Field 9 - v530 = eq v528, u8 255 - v531 = load v326 - v532 = mul v531, v530 - store v532 at v326 - v534 = array_get v136, index Field 10 - v536 = eq v534, u8 250 - v537 = load v326 - v538 = mul v537, v536 - store v538 at v326 - v540 = array_get v136, index Field 11 - v542 = eq v540, u8 190 - v543 = load v326 - v544 = mul v543, v542 - store v544 at v326 - v546 = array_get v136, index Field 12 - v548 = eq v546, u8 54 - v549 = load v326 - v550 = mul v549, v548 - store v550 at v326 - v552 = array_get v136, index Field 13 - v554 = eq v552, u8 65 - v555 = load v326 - v556 = mul v555, v554 - store v556 at v326 - v558 = array_get v136, index Field 14 - v560 = eq v558, u8 18 - v561 = load v326 - v562 = mul v561, v560 - store v562 at v326 - v564 = array_get v136, index Field 15 - v566 = eq v564, u8 19 - v567 = load v326 - v568 = mul v567, v566 - store v568 at v326 - v570 = array_get v136, index Field 2⁴ - v572 = eq v570, u8 116 - v573 = load v326 - v574 = mul v573, v572 - store v574 at v326 - v576 = array_get v136, index Field 17 - v578 = eq v576, u8 2⁷ - v579 = load v326 - v580 = mul v579, v578 - store v580 at v326 - v582 = array_get v136, index Field 18 - v584 = eq v582, u8 57 - v585 = load v326 - v586 = mul v585, v584 - store v586 at v326 - v588 = array_get v136, index Field 19 - v590 = eq v588, u8 2⁷ - v591 = load v326 - v592 = mul v591, v590 - store v592 at v326 - v594 = array_get v136, index Field 20 - v596 = eq v594, u8 24 - v597 = load v326 - v598 = mul v597, v596 - store v598 at v326 - v600 = array_get v136, index Field 21 - v602 = eq v600, u8 0 - v603 = load v326 - v604 = mul v603, v602 - store v604 at v326 - v606 = array_get v136, index Field 22 - v608 = eq v606, u8 0 - v609 = load v326 - v610 = mul v609, v608 - store v610 at v326 - v612 = array_get v136, index Field 23 - v614 = eq v612, u8 0 - v615 = load v326 - v616 = mul v615, v614 - store v616 at v326 - v618 = array_get v136, index Field 24 - v620 = eq v618, u8 0 - v621 = load v326 - v622 = mul v621, v620 - store v622 at v326 - v624 = array_get v136, index Field 25 - v626 = eq v624, u8 0 - v627 = load v326 - v628 = mul v627, v626 - store v628 at v326 - v630 = array_get v136, index Field 26 - v632 = eq v630, u8 0 - v633 = load v326 - v634 = mul v633, v632 - store v634 at v326 - v636 = array_get v136, index Field 27 - v638 = eq v636, u8 0 - v639 = load v326 - v640 = mul v639, v638 - store v640 at v326 - v642 = array_get v136, index Field 28 - v644 = eq v642, u8 0 - v645 = load v326 - v646 = mul v645, v644 - store v646 at v326 - v648 = array_get v136, index Field 29 - v650 = eq v648, u8 0 - v651 = load v326 - v652 = mul v651, v650 - store v652 at v326 - v654 = array_get v136, index Field 30 - v656 = eq v654, u8 0 - v657 = load v326 - v658 = mul v657, v656 - store v658 at v326 - v660 = array_get v136, index Field 31 - v662 = eq v660, u8 0 - v663 = load v326 - v664 = mul v663, v662 - store v664 at v326 - jmp b26() - b26(): - v328 = load v326 - constrain v328 == u1 1 - v329 = eq v137, Field 21 - constrain v137 == Field 21 - v330 = allocate - store u64 1 at v330 - v333 = allocate - store u64 2⁴ at v333 - v336 = allocate - store u64 1 at v336 - v339 = allocate - store u64 2⁴ at v339 - return - b2(): - v444 = truncate v1 to 64 bits, max_bit_size: 254 - v445 = cast v444 as u64 - v446 = sub v445, u64 1 - range_check v446 to 64 bits - v447 = lt u64 0, v446 - jmpif v447 then: b51, else: b52 - b51(): - v449 = array_get v0, index u64 1 - v450 = load v259 - v451 = div v449, Field 2⁴ - v452 = truncate v451 to 4 bits, max_bit_size: 8 - v453 = cast v452 as u4 - v454 = array_set v450, index u64 0, value v453 - v455 = and v449, u8 15 - v456 = truncate v455 to 4 bits, max_bit_size: 8 - v457 = cast v456 as u4 - v458 = array_set v454, index u64 1, value v457 - store v458 at v259 - jmp b52() - b52(): - v459 = truncate v1 to 64 bits, max_bit_size: 254 - v460 = cast v459 as u64 - v461 = sub v460, u64 1 - range_check v461 to 64 bits - v462 = lt u64 1, v461 - jmpif v462 then: b56, else: b57 - b56(): - v464 = array_get v0, index u64 2 - v465 = load v259 - v466 = div v464, Field 2⁴ - v467 = truncate v466 to 4 bits, max_bit_size: 8 - v468 = cast v467 as u4 - v469 = array_set v465, index u64 2, value v468 - v470 = and v464, u8 15 - v471 = truncate v470 to 4 bits, max_bit_size: 8 - v472 = cast v471 as u4 - v473 = array_set v469, index u64 3, value v472 - store v473 at v259 - jmp b57() - b57(): - jmp b5() - b5(): - jmp b6() -} - -After Simplifying: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v254 = truncate v1 to 64 bits, max_bit_size: 254 - v255 = cast v254 as u64 - inc_rc v0 - v256 = lt u64 5, v255 - v257 = not v256 - constrain v256 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v259 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 - v261 = array_get v0, index Field 0 - v262 = div v261, Field 2⁴ - v263 = truncate v262 to 4 bits, max_bit_size: 8 - v264 = cast v263 as u4 - v265 = truncate v264 to 1 bits, max_bit_size: 4 - v266 = cast v265 as u1 - jmpif v266 then: b1, else: b2 - b1(): - v291 = array_get v0, index Field 0 - v292 = and v291, u8 15 - v293 = truncate v292 to 4 bits, max_bit_size: 8 - v294 = cast v293 as u4 - store [v294, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v259 - inc_rc v0 - v387 = truncate v1 to 64 bits, max_bit_size: 254 - v388 = cast v387 as u64 - v389 = lt u64 1, v388 - jmpif v389 then: b29, else: b30 - b29(): - v391 = array_get v0, index Field 1 - v392 = load v259 - v393 = div v391, Field 2⁴ - v394 = truncate v393 to 4 bits, max_bit_size: 8 - v395 = cast v394 as u4 - v396 = array_set v392, index Field 1, value v395 - v397 = and v391, u8 15 - v398 = truncate v397 to 4 bits, max_bit_size: 8 - v399 = cast v398 as u4 - v400 = array_set v396, index Field 2, value v399 - store v400 at v259 - jmp b30() - b30(): - v401 = truncate v1 to 64 bits, max_bit_size: 254 - v402 = cast v401 as u64 - v403 = lt u64 2, v402 - jmpif v403 then: b34, else: b35 - b34(): - v405 = array_get v0, index Field 2 - v406 = load v259 - v407 = div v405, Field 2⁴ - v408 = truncate v407 to 4 bits, max_bit_size: 8 - v409 = cast v408 as u4 - v410 = array_set v406, index Field 3, value v409 - v411 = and v405, u8 15 - v412 = truncate v411 to 4 bits, max_bit_size: 8 - v413 = cast v412 as u4 - v414 = array_set v410, index Field 4, value v413 - store v414 at v259 - jmp b35() - b35(): - v416 = truncate v1 to 64 bits, max_bit_size: 254 - v417 = cast v416 as u64 - v418 = lt u64 3, v417 - jmpif v418 then: b39, else: b40 - b39(): - v420 = array_get v0, index Field 3 - v421 = load v259 - v422 = div v420, Field 2⁴ - v423 = truncate v422 to 4 bits, max_bit_size: 8 - v424 = cast v423 as u4 - v425 = array_set v421, index Field 5, value v424 - v426 = and v420, u8 15 - v427 = truncate v426 to 4 bits, max_bit_size: 8 - v428 = cast v427 as u4 - v429 = array_set v425, index Field 6, value v428 - store v429 at v259 - jmp b40() - b40(): - v430 = truncate v1 to 64 bits, max_bit_size: 254 - v431 = cast v430 as u64 - v432 = lt u64 4, v431 - jmpif v432 then: b44, else: b45 - b44(): - v434 = array_get v0, index Field 4 - v435 = load v259 - v436 = div v434, Field 2⁴ - v437 = truncate v436 to 4 bits, max_bit_size: 8 - v438 = cast v437 as u4 - v439 = array_set v435, index Field 7, value v438 - v440 = and v434, u8 15 - v441 = truncate v440 to 4 bits, max_bit_size: 8 - v442 = cast v441 as u4 - v443 = array_set v439, index Field 8, value v442 - store v443 at v259 - jmp b45() - b45(): - jmp b6() - b6(): - v299 = load v259 - v300 = mul Field 2, v1 - v301 = cast v266 as Field - v302 = add v300, v301 - v303 = sub v302, Field 2 - inc_rc v299 - inc_rc v299 - inc_rc v299 - v304 = eq v303, Field 5 - constrain v303 == Field 5 - v305 = array_get v299, index Field 0 - v306 = array_get v299, index Field 1 - v307 = array_get v299, index Field 2 - v308 = array_get v299, index Field 3 - v309 = array_get v299, index Field 4 - v310 = allocate - store u1 1 at v310 - v792 = eq v305, u4 15 - v793 = load v310 - v794 = mul v793, v792 - store v794 at v310 - v798 = eq v306, u4 1 - v799 = load v310 - v800 = mul v799, v798 - store v800 at v310 - v804 = eq v307, u4 12 - v805 = load v310 - v806 = mul v805, v804 - store v806 at v310 - v810 = eq v308, u4 11 - v811 = load v310 - v812 = mul v811, v810 - store v812 at v310 - v816 = eq v309, u4 8 - v817 = load v310 - v818 = mul v817, v816 - store v818 at v310 - v312 = load v310 - constrain v312 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v317 = allocate - store [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 - range_check u8 148 to 8 bits - store [u8 148, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v317 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v666 = load v317 - v668 = array_set v666, index Field 1, value u8 184 - store v668 at v317 - v670 = load v317 - v672 = array_set v670, index Field 2, value u8 143 - store v672 at v317 - v674 = load v317 - v676 = array_set v674, index Field 3, value u8 97 - store v676 at v317 - v678 = load v317 - v680 = array_set v678, index Field 4, value u8 230 - store v680 at v317 - v682 = load v317 - v684 = array_set v682, index Field 5, value u8 251 - store v684 at v317 - v686 = load v317 - v688 = array_set v686, index Field 6, value u8 218 - store v688 at v317 - v690 = load v317 - v692 = array_set v690, index Field 7, value u8 131 - store v692 at v317 - v694 = load v317 - v696 = array_set v694, index Field 8, value u8 251 - store v696 at v317 - v698 = load v317 - v700 = array_set v698, index Field 9, value u8 255 - store v700 at v317 - v702 = load v317 - v704 = array_set v702, index Field 10, value u8 250 - store v704 at v317 - v706 = load v317 - v708 = array_set v706, index Field 11, value u8 190 - store v708 at v317 - v710 = load v317 - v712 = array_set v710, index Field 12, value u8 54 - store v712 at v317 - v714 = load v317 - v716 = array_set v714, index Field 13, value u8 65 - store v716 at v317 - v718 = load v317 - v720 = array_set v718, index Field 14, value u8 18 - store v720 at v317 - v722 = load v317 - v724 = array_set v722, index Field 15, value u8 19 - store v724 at v317 - v726 = load v317 - v728 = array_set v726, index Field 2⁴, value u8 116 - store v728 at v317 - v730 = load v317 - v732 = array_set v730, index Field 17, value u8 2⁷ - store v732 at v317 - v734 = load v317 - v736 = array_set v734, index Field 18, value u8 57 - store v736 at v317 - v738 = load v317 - v740 = array_set v738, index Field 19, value u8 2⁷ - store v740 at v317 - v742 = load v317 - v744 = array_set v742, index Field 20, value u8 24 - store v744 at v317 - v746 = load v317 - v748 = array_set v746, index Field 21, value u8 0 - store v748 at v317 - v750 = load v317 - v752 = array_set v750, index Field 22, value u8 0 - store v752 at v317 - v754 = load v317 - v756 = array_set v754, index Field 23, value u8 0 - store v756 at v317 - v758 = load v317 - v760 = array_set v758, index Field 24, value u8 0 - store v760 at v317 - v762 = load v317 - v764 = array_set v762, index Field 25, value u8 0 - store v764 at v317 - v766 = load v317 - v768 = array_set v766, index Field 26, value u8 0 - store v768 at v317 - v770 = load v317 - v772 = array_set v770, index Field 27, value u8 0 - store v772 at v317 - v774 = load v317 - v776 = array_set v774, index Field 28, value u8 0 - store v776 at v317 - v778 = load v317 - v780 = array_set v778, index Field 29, value u8 0 - store v780 at v317 - v782 = load v317 - v784 = array_set v782, index Field 30, value u8 0 - store v784 at v317 - v786 = load v317 - v788 = array_set v786, index Field 31, value u8 0 - store v788 at v317 - v325 = load v317 - inc_rc v325 - inc_rc v325 - v326 = allocate - store u1 1 at v326 - v474 = array_get v325, index Field 0 - v476 = eq v474, u8 148 - v477 = load v326 - v478 = mul v477, v476 - store v478 at v326 - v480 = array_get v325, index Field 1 - v482 = eq v480, u8 184 - v483 = load v326 - v484 = mul v483, v482 - store v484 at v326 - v486 = array_get v325, index Field 2 - v488 = eq v486, u8 143 - v489 = load v326 - v490 = mul v489, v488 - store v490 at v326 - v492 = array_get v325, index Field 3 - v494 = eq v492, u8 97 - v495 = load v326 - v496 = mul v495, v494 - store v496 at v326 - v498 = array_get v325, index Field 4 - v500 = eq v498, u8 230 - v501 = load v326 - v502 = mul v501, v500 - store v502 at v326 - v504 = array_get v325, index Field 5 - v506 = eq v504, u8 251 - v507 = load v326 - v508 = mul v507, v506 - store v508 at v326 - v510 = array_get v325, index Field 6 - v512 = eq v510, u8 218 - v513 = load v326 - v514 = mul v513, v512 - store v514 at v326 - v516 = array_get v325, index Field 7 - v518 = eq v516, u8 131 - v519 = load v326 - v520 = mul v519, v518 - store v520 at v326 - v522 = array_get v325, index Field 8 - v524 = eq v522, u8 251 - v525 = load v326 - v526 = mul v525, v524 - store v526 at v326 - v528 = array_get v325, index Field 9 - v530 = eq v528, u8 255 - v531 = load v326 - v532 = mul v531, v530 - store v532 at v326 - v534 = array_get v325, index Field 10 - v536 = eq v534, u8 250 - v537 = load v326 - v538 = mul v537, v536 - store v538 at v326 - v540 = array_get v325, index Field 11 - v542 = eq v540, u8 190 - v543 = load v326 - v544 = mul v543, v542 - store v544 at v326 - v546 = array_get v325, index Field 12 - v548 = eq v546, u8 54 - v549 = load v326 - v550 = mul v549, v548 - store v550 at v326 - v552 = array_get v325, index Field 13 - v554 = eq v552, u8 65 - v555 = load v326 - v556 = mul v555, v554 - store v556 at v326 - v558 = array_get v325, index Field 14 - v560 = eq v558, u8 18 - v561 = load v326 - v562 = mul v561, v560 - store v562 at v326 - v564 = array_get v325, index Field 15 - v566 = eq v564, u8 19 - v567 = load v326 - v568 = mul v567, v566 - store v568 at v326 - v570 = array_get v325, index Field 2⁴ - v572 = eq v570, u8 116 - v573 = load v326 - v574 = mul v573, v572 - store v574 at v326 - v576 = array_get v325, index Field 17 - v578 = eq v576, u8 2⁷ - v579 = load v326 - v580 = mul v579, v578 - store v580 at v326 - v582 = array_get v325, index Field 18 - v584 = eq v582, u8 57 - v585 = load v326 - v586 = mul v585, v584 - store v586 at v326 - v588 = array_get v325, index Field 19 - v590 = eq v588, u8 2⁷ - v591 = load v326 - v592 = mul v591, v590 - store v592 at v326 - v594 = array_get v325, index Field 20 - v596 = eq v594, u8 24 - v597 = load v326 - v598 = mul v597, v596 - store v598 at v326 - v600 = array_get v325, index Field 21 - v602 = eq v600, u8 0 - v603 = load v326 - v604 = mul v603, v602 - store v604 at v326 - v606 = array_get v325, index Field 22 - v608 = eq v606, u8 0 - v609 = load v326 - v610 = mul v609, v608 - store v610 at v326 - v612 = array_get v325, index Field 23 - v614 = eq v612, u8 0 - v615 = load v326 - v616 = mul v615, v614 - store v616 at v326 - v618 = array_get v325, index Field 24 - v620 = eq v618, u8 0 - v621 = load v326 - v622 = mul v621, v620 - store v622 at v326 - v624 = array_get v325, index Field 25 - v626 = eq v624, u8 0 - v627 = load v326 - v628 = mul v627, v626 - store v628 at v326 - v630 = array_get v325, index Field 26 - v632 = eq v630, u8 0 - v633 = load v326 - v634 = mul v633, v632 - store v634 at v326 - v636 = array_get v325, index Field 27 - v638 = eq v636, u8 0 - v639 = load v326 - v640 = mul v639, v638 - store v640 at v326 - v642 = array_get v325, index Field 28 - v644 = eq v642, u8 0 - v645 = load v326 - v646 = mul v645, v644 - store v646 at v326 - v648 = array_get v325, index Field 29 - v650 = eq v648, u8 0 - v651 = load v326 - v652 = mul v651, v650 - store v652 at v326 - v654 = array_get v325, index Field 30 - v656 = eq v654, u8 0 - v657 = load v326 - v658 = mul v657, v656 - store v658 at v326 - v660 = array_get v325, index Field 31 - v662 = eq v660, u8 0 - v663 = load v326 - v664 = mul v663, v662 - store v664 at v326 - v328 = load v326 - constrain v328 == u1 1 - v329 = eq Field 21, Field 21 - constrain Field 21 == Field 21 - v330 = allocate - store u64 1 at v330 - v333 = allocate - store u64 2⁴ at v333 - v336 = allocate - store u64 1 at v336 - v339 = allocate - store u64 2⁴ at v339 - return - b2(): - v444 = truncate v1 to 64 bits, max_bit_size: 254 - v445 = cast v444 as u64 - v446 = sub v445, u64 1 - range_check v446 to 64 bits - v447 = lt u64 0, v446 - jmpif v447 then: b51, else: b52 - b51(): - v449 = array_get v0, index u64 1 - v450 = load v259 - v451 = div v449, Field 2⁴ - v452 = truncate v451 to 4 bits, max_bit_size: 8 - v453 = cast v452 as u4 - v454 = array_set v450, index u64 0, value v453 - v455 = and v449, u8 15 - v456 = truncate v455 to 4 bits, max_bit_size: 8 - v457 = cast v456 as u4 - v458 = array_set v454, index u64 1, value v457 - store v458 at v259 - jmp b52() - b52(): - v459 = truncate v1 to 64 bits, max_bit_size: 254 - v460 = cast v459 as u64 - v461 = sub v460, u64 1 - range_check v461 to 64 bits - v462 = lt u64 1, v461 - jmpif v462 then: b56, else: b57 - b56(): - v464 = array_get v0, index u64 2 - v465 = load v259 - v466 = div v464, Field 2⁴ - v467 = truncate v466 to 4 bits, max_bit_size: 8 - v468 = cast v467 as u4 - v469 = array_set v465, index u64 2, value v468 - v470 = and v464, u8 15 - v471 = truncate v470 to 4 bits, max_bit_size: 8 - v472 = cast v471 as u4 - v473 = array_set v469, index u64 3, value v472 - store v473 at v259 - jmp b57() - b57(): - jmp b6() -} - -After Mem2Reg: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v820 = truncate v1 to 64 bits, max_bit_size: 254 - v821 = cast v820 as u64 - inc_rc v0 - v822 = lt u64 5, v821 - v823 = not v822 - constrain v822 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v825 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 - v827 = array_get v0, index Field 0 - v828 = div v827, Field 2⁴ - v829 = truncate v828 to 4 bits, max_bit_size: 8 - v830 = cast v829 as u4 - v831 = truncate v830 to 1 bits, max_bit_size: 4 - v832 = cast v831 as u1 - jmpif v832 then: b1, else: b2 - b1(): - v864 = array_get v0, index Field 0 - v865 = and v864, u8 15 - v866 = truncate v865 to 4 bits, max_bit_size: 8 - v867 = cast v866 as u4 - store [v867, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 - inc_rc v0 - v869 = truncate v1 to 64 bits, max_bit_size: 254 - v870 = cast v869 as u64 - v871 = lt u64 1, v870 - jmpif v871 then: b29, else: b30 - b29(): - v872 = array_get v0, index Field 1 - v874 = div v872, Field 2⁴ - v875 = truncate v874 to 4 bits, max_bit_size: 8 - v876 = cast v875 as u4 - v879 = and v872, u8 15 - v880 = truncate v879 to 4 bits, max_bit_size: 8 - v881 = cast v880 as u4 - store [v867, v876, v881, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 - jmp b30() - b30(): - v885 = truncate v1 to 64 bits, max_bit_size: 254 - v886 = cast v885 as u64 - v887 = lt u64 2, v886 - jmpif v887 then: b34, else: b35 - b34(): - v888 = array_get v0, index Field 2 - v889 = load v825 - v890 = div v888, Field 2⁴ - v891 = truncate v890 to 4 bits, max_bit_size: 8 - v892 = cast v891 as u4 - v893 = array_set v889, index Field 3, value v892 - v894 = and v888, u8 15 - v895 = truncate v894 to 4 bits, max_bit_size: 8 - v896 = cast v895 as u4 - v897 = array_set v893, index Field 4, value v896 - store v897 at v825 - jmp b35() - b35(): - v898 = truncate v1 to 64 bits, max_bit_size: 254 - v899 = cast v898 as u64 - v900 = lt u64 3, v899 - jmpif v900 then: b39, else: b40 - b39(): - v901 = array_get v0, index Field 3 - v902 = load v825 - v903 = div v901, Field 2⁴ - v904 = truncate v903 to 4 bits, max_bit_size: 8 - v905 = cast v904 as u4 - v906 = array_set v902, index Field 5, value v905 - v907 = and v901, u8 15 - v908 = truncate v907 to 4 bits, max_bit_size: 8 - v909 = cast v908 as u4 - v910 = array_set v906, index Field 6, value v909 - store v910 at v825 - jmp b40() - b40(): - v911 = truncate v1 to 64 bits, max_bit_size: 254 - v912 = cast v911 as u64 - v913 = lt u64 4, v912 - jmpif v913 then: b44, else: b45 - b44(): - v914 = array_get v0, index Field 4 - v915 = load v825 - v916 = div v914, Field 2⁴ - v917 = truncate v916 to 4 bits, max_bit_size: 8 - v918 = cast v917 as u4 - v919 = array_set v915, index Field 7, value v918 - v920 = and v914, u8 15 - v921 = truncate v920 to 4 bits, max_bit_size: 8 - v922 = cast v921 as u4 - v923 = array_set v919, index Field 8, value v922 - store v923 at v825 - jmp b45() - b45(): - jmp b6() - b6(): - v924 = load v825 - v925 = mul Field 2, v1 - v926 = cast v832 as Field - v927 = add v925, v926 - v928 = sub v927, Field 2 - inc_rc v924 - inc_rc v924 - inc_rc v924 - v929 = eq v928, Field 5 - constrain v928 == Field 5 - v930 = array_get v924, index Field 0 - v931 = array_get v924, index Field 1 - v932 = array_get v924, index Field 2 - v933 = array_get v924, index Field 3 - v934 = array_get v924, index Field 4 - v935 = allocate - v936 = eq v930, u4 15 - v938 = eq v931, u4 1 - v940 = mul v936, v938 - v941 = eq v932, u4 12 - v943 = mul v940, v941 - v944 = eq v933, u4 11 - v946 = mul v943, v944 - v947 = eq v934, u4 8 - v949 = mul v946, v947 - store v949 at v935 - constrain v949 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v955 = allocate - range_check u8 148 to 8 bits - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - store [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v955 - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v1086 = allocate - store u1 1 at v1086 - v1152 = allocate - store u64 1 at v1152 - v1153 = allocate - store u64 2⁴ at v1153 - v1154 = allocate - store u64 1 at v1154 - v1155 = allocate - store u64 2⁴ at v1155 - return - b2(): - v833 = truncate v1 to 64 bits, max_bit_size: 254 - v834 = cast v833 as u64 - v835 = sub v834, u64 1 - range_check v835 to 64 bits - v836 = lt u64 0, v835 - jmpif v836 then: b51, else: b52 - b51(): - v837 = array_get v0, index u64 1 - v839 = div v837, Field 2⁴ - v840 = truncate v839 to 4 bits, max_bit_size: 8 - v841 = cast v840 as u4 - v844 = and v837, u8 15 - v845 = truncate v844 to 4 bits, max_bit_size: 8 - v846 = cast v845 as u4 - store [v841, v846, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 - jmp b52() - b52(): - v850 = truncate v1 to 64 bits, max_bit_size: 254 - v851 = cast v850 as u64 - v852 = sub v851, u64 1 - range_check v852 to 64 bits - v853 = lt u64 1, v852 - jmpif v853 then: b56, else: b57 - b56(): - v854 = array_get v0, index u64 2 - v855 = load v825 - v856 = div v854, Field 2⁴ - v857 = truncate v856 to 4 bits, max_bit_size: 8 - v858 = cast v857 as u4 - v859 = array_set v855, index u64 2, value v858 - v860 = and v854, u8 15 - v861 = truncate v860 to 4 bits, max_bit_size: 8 - v862 = cast v861 as u4 - v863 = array_set v859, index u64 3, value v862 - store v863 at v825 - jmp b57() - b57(): - jmp b6() -} - -After Flattening: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v820 = truncate v1 to 64 bits, max_bit_size: 254 - v821 = cast v820 as u64 - inc_rc v0 - v822 = lt u64 5, v821 - v823 = not v822 - constrain v822 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v825 = allocate - store [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 - v827 = array_get v0, index Field 0 - v828 = div v827, Field 2⁴ - v829 = truncate v828 to 4 bits, max_bit_size: 8 - v830 = cast v829 as u4 - v831 = truncate v830 to 1 bits, max_bit_size: 4 - v832 = cast v831 as u1 - enable_side_effects v832 - v1158 = array_get v0, index Field 0 - v1159 = and v1158, u8 15 - v1160 = truncate v1159 to 4 bits, max_bit_size: 8 - v1161 = cast v1160 as u4 - v1163 = load v825 - store [v1161, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 - inc_rc v0 - v1164 = truncate v1 to 64 bits, max_bit_size: 254 - v1165 = cast v1164 as u64 - v1166 = lt u64 1, v1165 - v1168 = mul v832, v1166 - enable_side_effects v1168 - v1169 = array_get v0, index Field 1 - v1170 = div v1169, Field 2⁴ - v1171 = truncate v1170 to 4 bits, max_bit_size: 8 - v1172 = cast v1171 as u4 - v1173 = and v1169, u8 15 - v1174 = truncate v1173 to 4 bits, max_bit_size: 8 - v1175 = cast v1174 as u4 - v1177 = load v825 - store [v1161, v1172, v1175, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 - v1178 = not v1166 - store v1177 at v825 - enable_side_effects v832 - v1179 = array_get v1177, index Field 0 - v1180 = cast v1166 as u4 - v1181 = cast v1178 as u4 - v1182 = mul v1180, v1161 - v1183 = mul v1181, v1179 - v1184 = add v1182, v1183 - v1185 = array_get v1177, index Field 1 - v1186 = cast v1166 as u4 - v1187 = cast v1178 as u4 - v1188 = mul v1186, v1172 - v1189 = mul v1187, v1185 - v1190 = add v1188, v1189 - v1191 = array_get v1177, index Field 2 - v1192 = cast v1166 as u4 - v1193 = cast v1178 as u4 - v1194 = mul v1192, v1175 - v1195 = mul v1193, v1191 - v1196 = add v1194, v1195 - v1197 = array_get v1177, index Field 3 - v1198 = cast v1166 as u4 - v1199 = cast v1178 as u4 - v1200 = mul v1199, v1197 - v1201 = array_get v1177, index Field 4 - v1202 = cast v1166 as u4 - v1203 = cast v1178 as u4 - v1204 = mul v1203, v1201 - v1205 = array_get v1177, index Field 5 - v1206 = cast v1166 as u4 - v1207 = cast v1178 as u4 - v1208 = mul v1207, v1205 - v1209 = array_get v1177, index Field 6 - v1210 = cast v1166 as u4 - v1211 = cast v1178 as u4 - v1212 = mul v1211, v1209 - v1213 = array_get v1177, index Field 7 - v1214 = cast v1166 as u4 - v1215 = cast v1178 as u4 - v1216 = mul v1215, v1213 - v1217 = array_get v1177, index Field 8 - v1218 = cast v1166 as u4 - v1219 = cast v1178 as u4 - v1220 = mul v1219, v1217 - v1221 = array_get v1177, index Field 9 - v1222 = cast v1166 as u4 - v1223 = cast v1178 as u4 - v1224 = mul v1223, v1221 - v1225 = array_get v1177, index Field 10 - v1226 = cast v1166 as u4 - v1227 = cast v1178 as u4 - v1228 = mul v1227, v1225 - v1229 = array_get v1177, index Field 11 - v1230 = cast v1166 as u4 - v1231 = cast v1178 as u4 - v1232 = mul v1231, v1229 - v1233 = array_get v1177, index Field 12 - v1234 = cast v1166 as u4 - v1235 = cast v1178 as u4 - v1236 = mul v1235, v1233 - v1237 = array_get v1177, index Field 13 - v1238 = cast v1166 as u4 - v1239 = cast v1178 as u4 - v1240 = mul v1239, v1237 - v1241 = array_get v1177, index Field 14 - v1242 = cast v1166 as u4 - v1243 = cast v1178 as u4 - v1244 = mul v1243, v1241 - v1245 = array_get v1177, index Field 15 - v1246 = cast v1166 as u4 - v1247 = cast v1178 as u4 - v1248 = mul v1247, v1245 - store [v1184, v1190, v1196, v1200, v1204, v1208, v1212, v1216, v1220, v1224, v1228, v1232, v1236, v1240, v1244, v1248] at v825 - v1250 = truncate v1 to 64 bits, max_bit_size: 254 - v1251 = cast v1250 as u64 - v1252 = lt u64 2, v1251 - v1253 = mul v832, v1252 - enable_side_effects v1253 - v1254 = array_get v0, index Field 2 - v1255 = load v825 - v1256 = div v1254, Field 2⁴ - v1257 = truncate v1256 to 4 bits, max_bit_size: 8 - v1258 = cast v1257 as u4 - v1259 = array_set v1255, index Field 3, value v1258 - v1260 = and v1254, u8 15 - v1261 = truncate v1260 to 4 bits, max_bit_size: 8 - v1262 = cast v1261 as u4 - v1263 = array_set v1259, index Field 4, value v1262 - v1264 = load v825 - store v1263 at v825 - v1265 = not v1252 - store v1264 at v825 - enable_side_effects v832 - v1266 = array_get v1263, index Field 0 - v1267 = array_get v1264, index Field 0 - v1268 = cast v1252 as u4 - v1269 = cast v1265 as u4 - v1270 = mul v1268, v1266 - v1271 = mul v1269, v1267 - v1272 = add v1270, v1271 - v1273 = array_get v1263, index Field 1 - v1274 = array_get v1264, index Field 1 - v1275 = cast v1252 as u4 - v1276 = cast v1265 as u4 - v1277 = mul v1275, v1273 - v1278 = mul v1276, v1274 - v1279 = add v1277, v1278 - v1280 = array_get v1263, index Field 2 - v1281 = array_get v1264, index Field 2 - v1282 = cast v1252 as u4 - v1283 = cast v1265 as u4 - v1284 = mul v1282, v1280 - v1285 = mul v1283, v1281 - v1286 = add v1284, v1285 - v1287 = array_get v1263, index Field 3 - v1288 = array_get v1264, index Field 3 - v1289 = cast v1252 as u4 - v1290 = cast v1265 as u4 - v1291 = mul v1289, v1287 - v1292 = mul v1290, v1288 - v1293 = add v1291, v1292 - v1294 = array_get v1263, index Field 4 - v1295 = array_get v1264, index Field 4 - v1296 = cast v1252 as u4 - v1297 = cast v1265 as u4 - v1298 = mul v1296, v1294 - v1299 = mul v1297, v1295 - v1300 = add v1298, v1299 - v1301 = array_get v1263, index Field 5 - v1302 = array_get v1264, index Field 5 - v1303 = cast v1252 as u4 - v1304 = cast v1265 as u4 - v1305 = mul v1303, v1301 - v1306 = mul v1304, v1302 - v1307 = add v1305, v1306 - v1308 = array_get v1263, index Field 6 - v1309 = array_get v1264, index Field 6 - v1310 = cast v1252 as u4 - v1311 = cast v1265 as u4 - v1312 = mul v1310, v1308 - v1313 = mul v1311, v1309 - v1314 = add v1312, v1313 - v1315 = array_get v1263, index Field 7 - v1316 = array_get v1264, index Field 7 - v1317 = cast v1252 as u4 - v1318 = cast v1265 as u4 - v1319 = mul v1317, v1315 - v1320 = mul v1318, v1316 - v1321 = add v1319, v1320 - v1322 = array_get v1263, index Field 8 - v1323 = array_get v1264, index Field 8 - v1324 = cast v1252 as u4 - v1325 = cast v1265 as u4 - v1326 = mul v1324, v1322 - v1327 = mul v1325, v1323 - v1328 = add v1326, v1327 - v1329 = array_get v1263, index Field 9 - v1330 = array_get v1264, index Field 9 - v1331 = cast v1252 as u4 - v1332 = cast v1265 as u4 - v1333 = mul v1331, v1329 - v1334 = mul v1332, v1330 - v1335 = add v1333, v1334 - v1336 = array_get v1263, index Field 10 - v1337 = array_get v1264, index Field 10 - v1338 = cast v1252 as u4 - v1339 = cast v1265 as u4 - v1340 = mul v1338, v1336 - v1341 = mul v1339, v1337 - v1342 = add v1340, v1341 - v1343 = array_get v1263, index Field 11 - v1344 = array_get v1264, index Field 11 - v1345 = cast v1252 as u4 - v1346 = cast v1265 as u4 - v1347 = mul v1345, v1343 - v1348 = mul v1346, v1344 - v1349 = add v1347, v1348 - v1350 = array_get v1263, index Field 12 - v1351 = array_get v1264, index Field 12 - v1352 = cast v1252 as u4 - v1353 = cast v1265 as u4 - v1354 = mul v1352, v1350 - v1355 = mul v1353, v1351 - v1356 = add v1354, v1355 - v1357 = array_get v1263, index Field 13 - v1358 = array_get v1264, index Field 13 - v1359 = cast v1252 as u4 - v1360 = cast v1265 as u4 - v1361 = mul v1359, v1357 - v1362 = mul v1360, v1358 - v1363 = add v1361, v1362 - v1364 = array_get v1263, index Field 14 - v1365 = array_get v1264, index Field 14 - v1366 = cast v1252 as u4 - v1367 = cast v1265 as u4 - v1368 = mul v1366, v1364 - v1369 = mul v1367, v1365 - v1370 = add v1368, v1369 - v1371 = array_get v1263, index Field 15 - v1372 = array_get v1264, index Field 15 - v1373 = cast v1252 as u4 - v1374 = cast v1265 as u4 - v1375 = mul v1373, v1371 - v1376 = mul v1374, v1372 - v1377 = add v1375, v1376 - store [v1272, v1279, v1286, v1293, v1300, v1307, v1314, v1321, v1328, v1335, v1342, v1349, v1356, v1363, v1370, v1377] at v825 - v1379 = truncate v1 to 64 bits, max_bit_size: 254 - v1380 = cast v1379 as u64 - v1381 = lt u64 3, v1380 - v1382 = mul v832, v1381 - enable_side_effects v1382 - v1383 = array_get v0, index Field 3 - v1384 = load v825 - v1385 = div v1383, Field 2⁴ - v1386 = truncate v1385 to 4 bits, max_bit_size: 8 - v1387 = cast v1386 as u4 - v1388 = array_set v1384, index Field 5, value v1387 - v1389 = and v1383, u8 15 - v1390 = truncate v1389 to 4 bits, max_bit_size: 8 - v1391 = cast v1390 as u4 - v1392 = array_set v1388, index Field 6, value v1391 - v1393 = load v825 - store v1392 at v825 - v1394 = not v1381 - store v1393 at v825 - enable_side_effects v832 - v1395 = array_get v1392, index Field 0 - v1396 = array_get v1393, index Field 0 - v1397 = cast v1381 as u4 - v1398 = cast v1394 as u4 - v1399 = mul v1397, v1395 - v1400 = mul v1398, v1396 - v1401 = add v1399, v1400 - v1402 = array_get v1392, index Field 1 - v1403 = array_get v1393, index Field 1 - v1404 = cast v1381 as u4 - v1405 = cast v1394 as u4 - v1406 = mul v1404, v1402 - v1407 = mul v1405, v1403 - v1408 = add v1406, v1407 - v1409 = array_get v1392, index Field 2 - v1410 = array_get v1393, index Field 2 - v1411 = cast v1381 as u4 - v1412 = cast v1394 as u4 - v1413 = mul v1411, v1409 - v1414 = mul v1412, v1410 - v1415 = add v1413, v1414 - v1416 = array_get v1392, index Field 3 - v1417 = array_get v1393, index Field 3 - v1418 = cast v1381 as u4 - v1419 = cast v1394 as u4 - v1420 = mul v1418, v1416 - v1421 = mul v1419, v1417 - v1422 = add v1420, v1421 - v1423 = array_get v1392, index Field 4 - v1424 = array_get v1393, index Field 4 - v1425 = cast v1381 as u4 - v1426 = cast v1394 as u4 - v1427 = mul v1425, v1423 - v1428 = mul v1426, v1424 - v1429 = add v1427, v1428 - v1430 = array_get v1392, index Field 5 - v1431 = array_get v1393, index Field 5 - v1432 = cast v1381 as u4 - v1433 = cast v1394 as u4 - v1434 = mul v1432, v1430 - v1435 = mul v1433, v1431 - v1436 = add v1434, v1435 - v1437 = array_get v1392, index Field 6 - v1438 = array_get v1393, index Field 6 - v1439 = cast v1381 as u4 - v1440 = cast v1394 as u4 - v1441 = mul v1439, v1437 - v1442 = mul v1440, v1438 - v1443 = add v1441, v1442 - v1444 = array_get v1392, index Field 7 - v1445 = array_get v1393, index Field 7 - v1446 = cast v1381 as u4 - v1447 = cast v1394 as u4 - v1448 = mul v1446, v1444 - v1449 = mul v1447, v1445 - v1450 = add v1448, v1449 - v1451 = array_get v1392, index Field 8 - v1452 = array_get v1393, index Field 8 - v1453 = cast v1381 as u4 - v1454 = cast v1394 as u4 - v1455 = mul v1453, v1451 - v1456 = mul v1454, v1452 - v1457 = add v1455, v1456 - v1458 = array_get v1392, index Field 9 - v1459 = array_get v1393, index Field 9 - v1460 = cast v1381 as u4 - v1461 = cast v1394 as u4 - v1462 = mul v1460, v1458 - v1463 = mul v1461, v1459 - v1464 = add v1462, v1463 - v1465 = array_get v1392, index Field 10 - v1466 = array_get v1393, index Field 10 - v1467 = cast v1381 as u4 - v1468 = cast v1394 as u4 - v1469 = mul v1467, v1465 - v1470 = mul v1468, v1466 - v1471 = add v1469, v1470 - v1472 = array_get v1392, index Field 11 - v1473 = array_get v1393, index Field 11 - v1474 = cast v1381 as u4 - v1475 = cast v1394 as u4 - v1476 = mul v1474, v1472 - v1477 = mul v1475, v1473 - v1478 = add v1476, v1477 - v1479 = array_get v1392, index Field 12 - v1480 = array_get v1393, index Field 12 - v1481 = cast v1381 as u4 - v1482 = cast v1394 as u4 - v1483 = mul v1481, v1479 - v1484 = mul v1482, v1480 - v1485 = add v1483, v1484 - v1486 = array_get v1392, index Field 13 - v1487 = array_get v1393, index Field 13 - v1488 = cast v1381 as u4 - v1489 = cast v1394 as u4 - v1490 = mul v1488, v1486 - v1491 = mul v1489, v1487 - v1492 = add v1490, v1491 - v1493 = array_get v1392, index Field 14 - v1494 = array_get v1393, index Field 14 - v1495 = cast v1381 as u4 - v1496 = cast v1394 as u4 - v1497 = mul v1495, v1493 - v1498 = mul v1496, v1494 - v1499 = add v1497, v1498 - v1500 = array_get v1392, index Field 15 - v1501 = array_get v1393, index Field 15 - v1502 = cast v1381 as u4 - v1503 = cast v1394 as u4 - v1504 = mul v1502, v1500 - v1505 = mul v1503, v1501 - v1506 = add v1504, v1505 - store [v1401, v1408, v1415, v1422, v1429, v1436, v1443, v1450, v1457, v1464, v1471, v1478, v1485, v1492, v1499, v1506] at v825 - v1508 = truncate v1 to 64 bits, max_bit_size: 254 - v1509 = cast v1508 as u64 - v1510 = lt u64 4, v1509 - v1511 = mul v832, v1510 - enable_side_effects v1511 - v1512 = array_get v0, index Field 4 - v1513 = load v825 - v1514 = div v1512, Field 2⁴ - v1515 = truncate v1514 to 4 bits, max_bit_size: 8 - v1516 = cast v1515 as u4 - v1517 = array_set v1513, index Field 7, value v1516 - v1518 = and v1512, u8 15 - v1519 = truncate v1518 to 4 bits, max_bit_size: 8 - v1520 = cast v1519 as u4 - v1521 = array_set v1517, index Field 8, value v1520 - v1522 = load v825 - store v1521 at v825 - v1523 = not v1510 - store v1522 at v825 - enable_side_effects v832 - v1524 = array_get v1521, index Field 0 - v1525 = array_get v1522, index Field 0 - v1526 = cast v1510 as u4 - v1527 = cast v1523 as u4 - v1528 = mul v1526, v1524 - v1529 = mul v1527, v1525 - v1530 = add v1528, v1529 - v1531 = array_get v1521, index Field 1 - v1532 = array_get v1522, index Field 1 - v1533 = cast v1510 as u4 - v1534 = cast v1523 as u4 - v1535 = mul v1533, v1531 - v1536 = mul v1534, v1532 - v1537 = add v1535, v1536 - v1538 = array_get v1521, index Field 2 - v1539 = array_get v1522, index Field 2 - v1540 = cast v1510 as u4 - v1541 = cast v1523 as u4 - v1542 = mul v1540, v1538 - v1543 = mul v1541, v1539 - v1544 = add v1542, v1543 - v1545 = array_get v1521, index Field 3 - v1546 = array_get v1522, index Field 3 - v1547 = cast v1510 as u4 - v1548 = cast v1523 as u4 - v1549 = mul v1547, v1545 - v1550 = mul v1548, v1546 - v1551 = add v1549, v1550 - v1552 = array_get v1521, index Field 4 - v1553 = array_get v1522, index Field 4 - v1554 = cast v1510 as u4 - v1555 = cast v1523 as u4 - v1556 = mul v1554, v1552 - v1557 = mul v1555, v1553 - v1558 = add v1556, v1557 - v1559 = array_get v1521, index Field 5 - v1560 = array_get v1522, index Field 5 - v1561 = cast v1510 as u4 - v1562 = cast v1523 as u4 - v1563 = mul v1561, v1559 - v1564 = mul v1562, v1560 - v1565 = add v1563, v1564 - v1566 = array_get v1521, index Field 6 - v1567 = array_get v1522, index Field 6 - v1568 = cast v1510 as u4 - v1569 = cast v1523 as u4 - v1570 = mul v1568, v1566 - v1571 = mul v1569, v1567 - v1572 = add v1570, v1571 - v1573 = array_get v1521, index Field 7 - v1574 = array_get v1522, index Field 7 - v1575 = cast v1510 as u4 - v1576 = cast v1523 as u4 - v1577 = mul v1575, v1573 - v1578 = mul v1576, v1574 - v1579 = add v1577, v1578 - v1580 = array_get v1521, index Field 8 - v1581 = array_get v1522, index Field 8 - v1582 = cast v1510 as u4 - v1583 = cast v1523 as u4 - v1584 = mul v1582, v1580 - v1585 = mul v1583, v1581 - v1586 = add v1584, v1585 - v1587 = array_get v1521, index Field 9 - v1588 = array_get v1522, index Field 9 - v1589 = cast v1510 as u4 - v1590 = cast v1523 as u4 - v1591 = mul v1589, v1587 - v1592 = mul v1590, v1588 - v1593 = add v1591, v1592 - v1594 = array_get v1521, index Field 10 - v1595 = array_get v1522, index Field 10 - v1596 = cast v1510 as u4 - v1597 = cast v1523 as u4 - v1598 = mul v1596, v1594 - v1599 = mul v1597, v1595 - v1600 = add v1598, v1599 - v1601 = array_get v1521, index Field 11 - v1602 = array_get v1522, index Field 11 - v1603 = cast v1510 as u4 - v1604 = cast v1523 as u4 - v1605 = mul v1603, v1601 - v1606 = mul v1604, v1602 - v1607 = add v1605, v1606 - v1608 = array_get v1521, index Field 12 - v1609 = array_get v1522, index Field 12 - v1610 = cast v1510 as u4 - v1611 = cast v1523 as u4 - v1612 = mul v1610, v1608 - v1613 = mul v1611, v1609 - v1614 = add v1612, v1613 - v1615 = array_get v1521, index Field 13 - v1616 = array_get v1522, index Field 13 - v1617 = cast v1510 as u4 - v1618 = cast v1523 as u4 - v1619 = mul v1617, v1615 - v1620 = mul v1618, v1616 - v1621 = add v1619, v1620 - v1622 = array_get v1521, index Field 14 - v1623 = array_get v1522, index Field 14 - v1624 = cast v1510 as u4 - v1625 = cast v1523 as u4 - v1626 = mul v1624, v1622 - v1627 = mul v1625, v1623 - v1628 = add v1626, v1627 - v1629 = array_get v1521, index Field 15 - v1630 = array_get v1522, index Field 15 - v1631 = cast v1510 as u4 - v1632 = cast v1523 as u4 - v1633 = mul v1631, v1629 - v1634 = mul v1632, v1630 - v1635 = add v1633, v1634 - store [v1530, v1537, v1544, v1551, v1558, v1565, v1572, v1579, v1586, v1593, v1600, v1607, v1614, v1621, v1628, v1635] at v825 - v1637 = not v832 - store v1163 at v825 - enable_side_effects v1637 - v1638 = truncate v1 to 64 bits, max_bit_size: 254 - v1639 = cast v1638 as u64 - v1640 = sub v1639, u64 1 - v1641 = cast v1637 as u64 - v1642 = mul v1640, v1641 - range_check v1642 to 64 bits - v1643 = lt u64 0, v1640 - v1644 = mul v1637, v1643 - enable_side_effects v1644 - v1645 = array_get v0, index u64 1 - v1646 = div v1645, Field 2⁴ - v1647 = truncate v1646 to 4 bits, max_bit_size: 8 - v1648 = cast v1647 as u4 - v1649 = and v1645, u8 15 - v1650 = truncate v1649 to 4 bits, max_bit_size: 8 - v1651 = cast v1650 as u4 - v1653 = load v825 - store [v1648, v1651, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] at v825 - v1654 = not v1643 - store v1653 at v825 - enable_side_effects v1637 - v1655 = array_get v1653, index Field 0 - v1656 = cast v1643 as u4 - v1657 = cast v1654 as u4 - v1658 = mul v1656, v1648 - v1659 = mul v1657, v1655 - v1660 = add v1658, v1659 - v1661 = array_get v1653, index Field 1 - v1662 = cast v1643 as u4 - v1663 = cast v1654 as u4 - v1664 = mul v1662, v1651 - v1665 = mul v1663, v1661 - v1666 = add v1664, v1665 - v1667 = array_get v1653, index Field 2 - v1668 = cast v1643 as u4 - v1669 = cast v1654 as u4 - v1670 = mul v1669, v1667 - v1671 = array_get v1653, index Field 3 - v1672 = cast v1643 as u4 - v1673 = cast v1654 as u4 - v1674 = mul v1673, v1671 - v1675 = array_get v1653, index Field 4 - v1676 = cast v1643 as u4 - v1677 = cast v1654 as u4 - v1678 = mul v1677, v1675 - v1679 = array_get v1653, index Field 5 - v1680 = cast v1643 as u4 - v1681 = cast v1654 as u4 - v1682 = mul v1681, v1679 - v1683 = array_get v1653, index Field 6 - v1684 = cast v1643 as u4 - v1685 = cast v1654 as u4 - v1686 = mul v1685, v1683 - v1687 = array_get v1653, index Field 7 - v1688 = cast v1643 as u4 - v1689 = cast v1654 as u4 - v1690 = mul v1689, v1687 - v1691 = array_get v1653, index Field 8 - v1692 = cast v1643 as u4 - v1693 = cast v1654 as u4 - v1694 = mul v1693, v1691 - v1695 = array_get v1653, index Field 9 - v1696 = cast v1643 as u4 - v1697 = cast v1654 as u4 - v1698 = mul v1697, v1695 - v1699 = array_get v1653, index Field 10 - v1700 = cast v1643 as u4 - v1701 = cast v1654 as u4 - v1702 = mul v1701, v1699 - v1703 = array_get v1653, index Field 11 - v1704 = cast v1643 as u4 - v1705 = cast v1654 as u4 - v1706 = mul v1705, v1703 - v1707 = array_get v1653, index Field 12 - v1708 = cast v1643 as u4 - v1709 = cast v1654 as u4 - v1710 = mul v1709, v1707 - v1711 = array_get v1653, index Field 13 - v1712 = cast v1643 as u4 - v1713 = cast v1654 as u4 - v1714 = mul v1713, v1711 - v1715 = array_get v1653, index Field 14 - v1716 = cast v1643 as u4 - v1717 = cast v1654 as u4 - v1718 = mul v1717, v1715 - v1719 = array_get v1653, index Field 15 - v1720 = cast v1643 as u4 - v1721 = cast v1654 as u4 - v1722 = mul v1721, v1719 - store [v1660, v1666, v1670, v1674, v1678, v1682, v1686, v1690, v1694, v1698, v1702, v1706, v1710, v1714, v1718, v1722] at v825 - v1724 = truncate v1 to 64 bits, max_bit_size: 254 - v1725 = cast v1724 as u64 - v1726 = sub v1725, u64 1 - v1727 = cast v1637 as u64 - v1728 = mul v1726, v1727 - range_check v1728 to 64 bits - v1729 = lt u64 1, v1726 - v1730 = mul v1637, v1729 - enable_side_effects v1730 - v1731 = array_get v0, index u64 2 - v1732 = load v825 - v1733 = div v1731, Field 2⁴ - v1734 = truncate v1733 to 4 bits, max_bit_size: 8 - v1735 = cast v1734 as u4 - v1736 = array_set v1732, index u64 2, value v1735 - v1737 = and v1731, u8 15 - v1738 = truncate v1737 to 4 bits, max_bit_size: 8 - v1739 = cast v1738 as u4 - v1740 = array_set v1736, index u64 3, value v1739 - v1741 = load v825 - store v1740 at v825 - v1742 = not v1729 - store v1741 at v825 - enable_side_effects v1637 - v1743 = array_get v1740, index Field 0 - v1744 = array_get v1741, index Field 0 - v1745 = cast v1729 as u4 - v1746 = cast v1742 as u4 - v1747 = mul v1745, v1743 - v1748 = mul v1746, v1744 - v1749 = add v1747, v1748 - v1750 = array_get v1740, index Field 1 - v1751 = array_get v1741, index Field 1 - v1752 = cast v1729 as u4 - v1753 = cast v1742 as u4 - v1754 = mul v1752, v1750 - v1755 = mul v1753, v1751 - v1756 = add v1754, v1755 - v1757 = array_get v1740, index Field 2 - v1758 = array_get v1741, index Field 2 - v1759 = cast v1729 as u4 - v1760 = cast v1742 as u4 - v1761 = mul v1759, v1757 - v1762 = mul v1760, v1758 - v1763 = add v1761, v1762 - v1764 = array_get v1740, index Field 3 - v1765 = array_get v1741, index Field 3 - v1766 = cast v1729 as u4 - v1767 = cast v1742 as u4 - v1768 = mul v1766, v1764 - v1769 = mul v1767, v1765 - v1770 = add v1768, v1769 - v1771 = array_get v1740, index Field 4 - v1772 = array_get v1741, index Field 4 - v1773 = cast v1729 as u4 - v1774 = cast v1742 as u4 - v1775 = mul v1773, v1771 - v1776 = mul v1774, v1772 - v1777 = add v1775, v1776 - v1778 = array_get v1740, index Field 5 - v1779 = array_get v1741, index Field 5 - v1780 = cast v1729 as u4 - v1781 = cast v1742 as u4 - v1782 = mul v1780, v1778 - v1783 = mul v1781, v1779 - v1784 = add v1782, v1783 - v1785 = array_get v1740, index Field 6 - v1786 = array_get v1741, index Field 6 - v1787 = cast v1729 as u4 - v1788 = cast v1742 as u4 - v1789 = mul v1787, v1785 - v1790 = mul v1788, v1786 - v1791 = add v1789, v1790 - v1792 = array_get v1740, index Field 7 - v1793 = array_get v1741, index Field 7 - v1794 = cast v1729 as u4 - v1795 = cast v1742 as u4 - v1796 = mul v1794, v1792 - v1797 = mul v1795, v1793 - v1798 = add v1796, v1797 - v1799 = array_get v1740, index Field 8 - v1800 = array_get v1741, index Field 8 - v1801 = cast v1729 as u4 - v1802 = cast v1742 as u4 - v1803 = mul v1801, v1799 - v1804 = mul v1802, v1800 - v1805 = add v1803, v1804 - v1806 = array_get v1740, index Field 9 - v1807 = array_get v1741, index Field 9 - v1808 = cast v1729 as u4 - v1809 = cast v1742 as u4 - v1810 = mul v1808, v1806 - v1811 = mul v1809, v1807 - v1812 = add v1810, v1811 - v1813 = array_get v1740, index Field 10 - v1814 = array_get v1741, index Field 10 - v1815 = cast v1729 as u4 - v1816 = cast v1742 as u4 - v1817 = mul v1815, v1813 - v1818 = mul v1816, v1814 - v1819 = add v1817, v1818 - v1820 = array_get v1740, index Field 11 - v1821 = array_get v1741, index Field 11 - v1822 = cast v1729 as u4 - v1823 = cast v1742 as u4 - v1824 = mul v1822, v1820 - v1825 = mul v1823, v1821 - v1826 = add v1824, v1825 - v1827 = array_get v1740, index Field 12 - v1828 = array_get v1741, index Field 12 - v1829 = cast v1729 as u4 - v1830 = cast v1742 as u4 - v1831 = mul v1829, v1827 - v1832 = mul v1830, v1828 - v1833 = add v1831, v1832 - v1834 = array_get v1740, index Field 13 - v1835 = array_get v1741, index Field 13 - v1836 = cast v1729 as u4 - v1837 = cast v1742 as u4 - v1838 = mul v1836, v1834 - v1839 = mul v1837, v1835 - v1840 = add v1838, v1839 - v1841 = array_get v1740, index Field 14 - v1842 = array_get v1741, index Field 14 - v1843 = cast v1729 as u4 - v1844 = cast v1742 as u4 - v1845 = mul v1843, v1841 - v1846 = mul v1844, v1842 - v1847 = add v1845, v1846 - v1848 = array_get v1740, index Field 15 - v1849 = array_get v1741, index Field 15 - v1850 = cast v1729 as u4 - v1851 = cast v1742 as u4 - v1852 = mul v1850, v1848 - v1853 = mul v1851, v1849 - v1854 = add v1852, v1853 - store [v1749, v1756, v1763, v1770, v1777, v1784, v1791, v1798, v1805, v1812, v1819, v1826, v1833, v1840, v1847, v1854] at v825 - enable_side_effects u1 1 - v1856 = cast v832 as u4 - v1857 = cast v1637 as u4 - v1858 = mul v1856, v1530 - v1859 = mul v1857, v1749 - v1860 = add v1858, v1859 - v1861 = cast v832 as u4 - v1862 = cast v1637 as u4 - v1863 = mul v1861, v1537 - v1864 = mul v1862, v1756 - v1865 = add v1863, v1864 - v1866 = cast v832 as u4 - v1867 = cast v1637 as u4 - v1868 = mul v1866, v1544 - v1869 = mul v1867, v1763 - v1870 = add v1868, v1869 - v1871 = cast v832 as u4 - v1872 = cast v1637 as u4 - v1873 = mul v1871, v1551 - v1874 = mul v1872, v1770 - v1875 = add v1873, v1874 - v1876 = cast v832 as u4 - v1877 = cast v1637 as u4 - v1878 = mul v1876, v1558 - v1879 = mul v1877, v1777 - v1880 = add v1878, v1879 - v1881 = cast v832 as u4 - v1882 = cast v1637 as u4 - v1883 = mul v1881, v1565 - v1884 = mul v1882, v1784 - v1885 = add v1883, v1884 - v1886 = cast v832 as u4 - v1887 = cast v1637 as u4 - v1888 = mul v1886, v1572 - v1889 = mul v1887, v1791 - v1890 = add v1888, v1889 - v1891 = cast v832 as u4 - v1892 = cast v1637 as u4 - v1893 = mul v1891, v1579 - v1894 = mul v1892, v1798 - v1895 = add v1893, v1894 - v1896 = cast v832 as u4 - v1897 = cast v1637 as u4 - v1898 = mul v1896, v1586 - v1899 = mul v1897, v1805 - v1900 = add v1898, v1899 - v1901 = cast v832 as u4 - v1902 = cast v1637 as u4 - v1903 = mul v1901, v1593 - v1904 = mul v1902, v1812 - v1905 = add v1903, v1904 - v1906 = cast v832 as u4 - v1907 = cast v1637 as u4 - v1908 = mul v1906, v1600 - v1909 = mul v1907, v1819 - v1910 = add v1908, v1909 - v1911 = cast v832 as u4 - v1912 = cast v1637 as u4 - v1913 = mul v1911, v1607 - v1914 = mul v1912, v1826 - v1915 = add v1913, v1914 - v1916 = cast v832 as u4 - v1917 = cast v1637 as u4 - v1918 = mul v1916, v1614 - v1919 = mul v1917, v1833 - v1920 = add v1918, v1919 - v1921 = cast v832 as u4 - v1922 = cast v1637 as u4 - v1923 = mul v1921, v1621 - v1924 = mul v1922, v1840 - v1925 = add v1923, v1924 - v1926 = cast v832 as u4 - v1927 = cast v1637 as u4 - v1928 = mul v1926, v1628 - v1929 = mul v1927, v1847 - v1930 = add v1928, v1929 - v1931 = cast v832 as u4 - v1932 = cast v1637 as u4 - v1933 = mul v1931, v1635 - v1934 = mul v1932, v1854 - v1935 = add v1933, v1934 - store [v1860, v1865, v1870, v1875, v1880, v1885, v1890, v1895, v1900, v1905, v1910, v1915, v1920, v1925, v1930, v1935] at v825 - v1937 = load v825 - v1938 = mul Field 2, v1 - v1939 = cast v832 as Field - v1940 = add v1938, v1939 - v1941 = sub v1940, Field 2 - inc_rc v1937 - inc_rc v1937 - inc_rc v1937 - v1942 = eq v1941, Field 5 - constrain v1941 == Field 5 - v1943 = array_get v1937, index Field 0 - v1944 = array_get v1937, index Field 1 - v1945 = array_get v1937, index Field 2 - v1946 = array_get v1937, index Field 3 - v1947 = array_get v1937, index Field 4 - v1948 = allocate - v1949 = eq v1943, u4 15 - v1950 = eq v1944, u4 1 - v1951 = mul v1949, v1950 - v1952 = eq v1945, u4 12 - v1953 = mul v1951, v1952 - v1954 = eq v1946, u4 11 - v1955 = mul v1953, v1954 - v1956 = eq v1947, u4 8 - v1957 = mul v1955, v1956 - store v1957 at v1948 - constrain v1957 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v1962 = allocate - range_check u8 148 to 8 bits - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - store [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] at v1962 - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v1967 = allocate - store u1 1 at v1967 - v1968 = allocate - store u64 1 at v1968 - v1969 = allocate - store u64 2⁴ at v1969 - v1970 = allocate - store u64 1 at v1970 - v1971 = allocate - store u64 2⁴ at v1971 - return -} - -After Mem2Reg: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v1972 = truncate v1 to 64 bits, max_bit_size: 254 - v1973 = cast v1972 as u64 - inc_rc v0 - v1974 = lt u64 5, v1973 - v1975 = not v1974 - constrain v1974 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v1977 = allocate - v1979 = array_get v0, index Field 0 - v1980 = div v1979, Field 2⁴ - v1981 = truncate v1980 to 4 bits, max_bit_size: 8 - v1982 = cast v1981 as u4 - v1983 = truncate v1982 to 1 bits, max_bit_size: 4 - v1984 = cast v1983 as u1 - enable_side_effects v1984 - v1985 = array_get v0, index Field 0 - v1986 = and v1985, u8 15 - v1987 = truncate v1986 to 4 bits, max_bit_size: 8 - v1988 = cast v1987 as u4 - inc_rc v0 - v1991 = truncate v1 to 64 bits, max_bit_size: 254 - v1992 = cast v1991 as u64 - v1993 = lt u64 1, v1992 - v1994 = mul v1984, v1993 - enable_side_effects v1994 - v1995 = array_get v0, index Field 1 - v1996 = div v1995, Field 2⁴ - v1997 = truncate v1996 to 4 bits, max_bit_size: 8 - v1998 = cast v1997 as u4 - v1999 = and v1995, u8 15 - v2000 = truncate v1999 to 4 bits, max_bit_size: 8 - v2001 = cast v2000 as u4 - v2004 = not v1993 - enable_side_effects v1984 - v2007 = cast v1993 as u4 - v2008 = cast v2004 as u4 - v2009 = mul v2007, v1988 - v2010 = mul v2008, v1988 - v2011 = add v2009, v2010 - v2013 = cast v1993 as u4 - v2014 = cast v2004 as u4 - v2015 = mul v2013, v1998 - v2017 = cast v1993 as u4 - v2018 = cast v2004 as u4 - v2019 = mul v2017, v2001 - v2021 = cast v1993 as u4 - v2022 = cast v2004 as u4 - v2024 = cast v1993 as u4 - v2025 = cast v2004 as u4 - v2027 = cast v1993 as u4 - v2028 = cast v2004 as u4 - v2030 = cast v1993 as u4 - v2031 = cast v2004 as u4 - v2033 = cast v1993 as u4 - v2034 = cast v2004 as u4 - v2036 = cast v1993 as u4 - v2037 = cast v2004 as u4 - v2039 = cast v1993 as u4 - v2040 = cast v2004 as u4 - v2042 = cast v1993 as u4 - v2043 = cast v2004 as u4 - v2045 = cast v1993 as u4 - v2046 = cast v2004 as u4 - v2048 = cast v1993 as u4 - v2049 = cast v2004 as u4 - v2051 = cast v1993 as u4 - v2052 = cast v2004 as u4 - v2054 = cast v1993 as u4 - v2055 = cast v2004 as u4 - v2057 = cast v1993 as u4 - v2058 = cast v2004 as u4 - v2060 = truncate v1 to 64 bits, max_bit_size: 254 - v2061 = cast v2060 as u64 - v2062 = lt u64 2, v2061 - v2063 = mul v1984, v2062 - enable_side_effects v2063 - v2064 = array_get v0, index Field 2 - v2066 = div v2064, Field 2⁴ - v2067 = truncate v2066 to 4 bits, max_bit_size: 8 - v2068 = cast v2067 as u4 - v2071 = and v2064, u8 15 - v2072 = truncate v2071 to 4 bits, max_bit_size: 8 - v2073 = cast v2072 as u4 - v2078 = not v2062 - enable_side_effects v1984 - v2082 = cast v2062 as u4 - v2083 = cast v2078 as u4 - v2084 = mul v2082, v2011 - v2085 = mul v2083, v2011 - v2086 = add v2084, v2085 - v2089 = cast v2062 as u4 - v2090 = cast v2078 as u4 - v2091 = mul v2089, v2015 - v2092 = mul v2090, v2015 - v2093 = add v2091, v2092 - v2096 = cast v2062 as u4 - v2097 = cast v2078 as u4 - v2098 = mul v2096, v2019 - v2099 = mul v2097, v2019 - v2100 = add v2098, v2099 - v2103 = cast v2062 as u4 - v2104 = cast v2078 as u4 - v2105 = mul v2103, v2068 - v2108 = cast v2062 as u4 - v2109 = cast v2078 as u4 - v2110 = mul v2108, v2073 - v2113 = cast v2062 as u4 - v2114 = cast v2078 as u4 - v2117 = cast v2062 as u4 - v2118 = cast v2078 as u4 - v2121 = cast v2062 as u4 - v2122 = cast v2078 as u4 - v2125 = cast v2062 as u4 - v2126 = cast v2078 as u4 - v2129 = cast v2062 as u4 - v2130 = cast v2078 as u4 - v2133 = cast v2062 as u4 - v2134 = cast v2078 as u4 - v2137 = cast v2062 as u4 - v2138 = cast v2078 as u4 - v2141 = cast v2062 as u4 - v2142 = cast v2078 as u4 - v2145 = cast v2062 as u4 - v2146 = cast v2078 as u4 - v2149 = cast v2062 as u4 - v2150 = cast v2078 as u4 - v2153 = cast v2062 as u4 - v2154 = cast v2078 as u4 - v2156 = truncate v1 to 64 bits, max_bit_size: 254 - v2157 = cast v2156 as u64 - v2158 = lt u64 3, v2157 - v2159 = mul v1984, v2158 - enable_side_effects v2159 - v2160 = array_get v0, index Field 3 - v2162 = div v2160, Field 2⁴ - v2163 = truncate v2162 to 4 bits, max_bit_size: 8 - v2164 = cast v2163 as u4 - v2167 = and v2160, u8 15 - v2168 = truncate v2167 to 4 bits, max_bit_size: 8 - v2169 = cast v2168 as u4 - v2174 = not v2158 - enable_side_effects v1984 - v2178 = cast v2158 as u4 - v2179 = cast v2174 as u4 - v2180 = mul v2178, v2086 - v2181 = mul v2179, v2086 - v2182 = add v2180, v2181 - v2185 = cast v2158 as u4 - v2186 = cast v2174 as u4 - v2187 = mul v2185, v2093 - v2188 = mul v2186, v2093 - v2189 = add v2187, v2188 - v2192 = cast v2158 as u4 - v2193 = cast v2174 as u4 - v2194 = mul v2192, v2100 - v2195 = mul v2193, v2100 - v2196 = add v2194, v2195 - v2199 = cast v2158 as u4 - v2200 = cast v2174 as u4 - v2201 = mul v2199, v2105 - v2202 = mul v2200, v2105 - v2203 = add v2201, v2202 - v2206 = cast v2158 as u4 - v2207 = cast v2174 as u4 - v2208 = mul v2206, v2110 - v2209 = mul v2207, v2110 - v2210 = add v2208, v2209 - v2213 = cast v2158 as u4 - v2214 = cast v2174 as u4 - v2215 = mul v2213, v2164 - v2218 = cast v2158 as u4 - v2219 = cast v2174 as u4 - v2220 = mul v2218, v2169 - v2223 = cast v2158 as u4 - v2224 = cast v2174 as u4 - v2227 = cast v2158 as u4 - v2228 = cast v2174 as u4 - v2231 = cast v2158 as u4 - v2232 = cast v2174 as u4 - v2235 = cast v2158 as u4 - v2236 = cast v2174 as u4 - v2239 = cast v2158 as u4 - v2240 = cast v2174 as u4 - v2243 = cast v2158 as u4 - v2244 = cast v2174 as u4 - v2247 = cast v2158 as u4 - v2248 = cast v2174 as u4 - v2251 = cast v2158 as u4 - v2252 = cast v2174 as u4 - v2255 = cast v2158 as u4 - v2256 = cast v2174 as u4 - v2258 = truncate v1 to 64 bits, max_bit_size: 254 - v2259 = cast v2258 as u64 - v2260 = lt u64 4, v2259 - v2261 = mul v1984, v2260 - enable_side_effects v2261 - v2262 = array_get v0, index Field 4 - v2264 = div v2262, Field 2⁴ - v2265 = truncate v2264 to 4 bits, max_bit_size: 8 - v2266 = cast v2265 as u4 - v2269 = and v2262, u8 15 - v2270 = truncate v2269 to 4 bits, max_bit_size: 8 - v2271 = cast v2270 as u4 - v2276 = not v2260 - enable_side_effects v1984 - v2280 = cast v2260 as u4 - v2281 = cast v2276 as u4 - v2282 = mul v2280, v2182 - v2283 = mul v2281, v2182 - v2284 = add v2282, v2283 - v2287 = cast v2260 as u4 - v2288 = cast v2276 as u4 - v2289 = mul v2287, v2189 - v2290 = mul v2288, v2189 - v2291 = add v2289, v2290 - v2294 = cast v2260 as u4 - v2295 = cast v2276 as u4 - v2296 = mul v2294, v2196 - v2297 = mul v2295, v2196 - v2298 = add v2296, v2297 - v2301 = cast v2260 as u4 - v2302 = cast v2276 as u4 - v2303 = mul v2301, v2203 - v2304 = mul v2302, v2203 - v2305 = add v2303, v2304 - v2308 = cast v2260 as u4 - v2309 = cast v2276 as u4 - v2310 = mul v2308, v2210 - v2311 = mul v2309, v2210 - v2312 = add v2310, v2311 - v2315 = cast v2260 as u4 - v2316 = cast v2276 as u4 - v2317 = mul v2315, v2215 - v2318 = mul v2316, v2215 - v2319 = add v2317, v2318 - v2322 = cast v2260 as u4 - v2323 = cast v2276 as u4 - v2324 = mul v2322, v2220 - v2325 = mul v2323, v2220 - v2326 = add v2324, v2325 - v2329 = cast v2260 as u4 - v2330 = cast v2276 as u4 - v2331 = mul v2329, v2266 - v2334 = cast v2260 as u4 - v2335 = cast v2276 as u4 - v2336 = mul v2334, v2271 - v2339 = cast v2260 as u4 - v2340 = cast v2276 as u4 - v2343 = cast v2260 as u4 - v2344 = cast v2276 as u4 - v2347 = cast v2260 as u4 - v2348 = cast v2276 as u4 - v2351 = cast v2260 as u4 - v2352 = cast v2276 as u4 - v2355 = cast v2260 as u4 - v2356 = cast v2276 as u4 - v2359 = cast v2260 as u4 - v2360 = cast v2276 as u4 - v2363 = cast v2260 as u4 - v2364 = cast v2276 as u4 - v2366 = not v1984 - enable_side_effects v2366 - v2368 = truncate v1 to 64 bits, max_bit_size: 254 - v2369 = cast v2368 as u64 - v2370 = sub v2369, u64 1 - v2371 = cast v2366 as u64 - v2372 = mul v2370, v2371 - range_check v2372 to 64 bits - v2373 = lt u64 0, v2370 - v2374 = mul v2366, v2373 - enable_side_effects v2374 - v2375 = array_get v0, index u64 1 - v2376 = div v2375, Field 2⁴ - v2377 = truncate v2376 to 4 bits, max_bit_size: 8 - v2378 = cast v2377 as u4 - v2379 = and v2375, u8 15 - v2380 = truncate v2379 to 4 bits, max_bit_size: 8 - v2381 = cast v2380 as u4 - v2384 = not v2373 - enable_side_effects v2366 - v2387 = cast v2373 as u4 - v2388 = cast v2384 as u4 - v2389 = mul v2387, v2378 - v2391 = cast v2373 as u4 - v2392 = cast v2384 as u4 - v2393 = mul v2391, v2381 - v2395 = cast v2373 as u4 - v2396 = cast v2384 as u4 - v2398 = cast v2373 as u4 - v2399 = cast v2384 as u4 - v2401 = cast v2373 as u4 - v2402 = cast v2384 as u4 - v2404 = cast v2373 as u4 - v2405 = cast v2384 as u4 - v2407 = cast v2373 as u4 - v2408 = cast v2384 as u4 - v2410 = cast v2373 as u4 - v2411 = cast v2384 as u4 - v2413 = cast v2373 as u4 - v2414 = cast v2384 as u4 - v2416 = cast v2373 as u4 - v2417 = cast v2384 as u4 - v2419 = cast v2373 as u4 - v2420 = cast v2384 as u4 - v2422 = cast v2373 as u4 - v2423 = cast v2384 as u4 - v2425 = cast v2373 as u4 - v2426 = cast v2384 as u4 - v2428 = cast v2373 as u4 - v2429 = cast v2384 as u4 - v2431 = cast v2373 as u4 - v2432 = cast v2384 as u4 - v2434 = cast v2373 as u4 - v2435 = cast v2384 as u4 - v2437 = truncate v1 to 64 bits, max_bit_size: 254 - v2438 = cast v2437 as u64 - v2439 = sub v2438, u64 1 - v2440 = cast v2366 as u64 - v2441 = mul v2439, v2440 - range_check v2441 to 64 bits - v2442 = lt u64 1, v2439 - v2443 = mul v2366, v2442 - enable_side_effects v2443 - v2444 = array_get v0, index u64 2 - v2446 = div v2444, Field 2⁴ - v2447 = truncate v2446 to 4 bits, max_bit_size: 8 - v2448 = cast v2447 as u4 - v2451 = and v2444, u8 15 - v2452 = truncate v2451 to 4 bits, max_bit_size: 8 - v2453 = cast v2452 as u4 - v2458 = not v2442 - enable_side_effects v2366 - v2462 = cast v2442 as u4 - v2463 = cast v2458 as u4 - v2464 = mul v2462, v2389 - v2465 = mul v2463, v2389 - v2466 = add v2464, v2465 - v2469 = cast v2442 as u4 - v2470 = cast v2458 as u4 - v2471 = mul v2469, v2393 - v2472 = mul v2470, v2393 - v2473 = add v2471, v2472 - v2476 = cast v2442 as u4 - v2477 = cast v2458 as u4 - v2478 = mul v2476, v2448 - v2481 = cast v2442 as u4 - v2482 = cast v2458 as u4 - v2483 = mul v2481, v2453 - v2486 = cast v2442 as u4 - v2487 = cast v2458 as u4 - v2490 = cast v2442 as u4 - v2491 = cast v2458 as u4 - v2494 = cast v2442 as u4 - v2495 = cast v2458 as u4 - v2498 = cast v2442 as u4 - v2499 = cast v2458 as u4 - v2502 = cast v2442 as u4 - v2503 = cast v2458 as u4 - v2506 = cast v2442 as u4 - v2507 = cast v2458 as u4 - v2510 = cast v2442 as u4 - v2511 = cast v2458 as u4 - v2514 = cast v2442 as u4 - v2515 = cast v2458 as u4 - v2518 = cast v2442 as u4 - v2519 = cast v2458 as u4 - v2522 = cast v2442 as u4 - v2523 = cast v2458 as u4 - v2526 = cast v2442 as u4 - v2527 = cast v2458 as u4 - v2530 = cast v2442 as u4 - v2531 = cast v2458 as u4 - enable_side_effects u1 1 - v2533 = cast v1984 as u4 - v2534 = cast v2366 as u4 - v2535 = mul v2533, v2284 - v2536 = mul v2534, v2466 - v2537 = add v2535, v2536 - v2538 = cast v1984 as u4 - v2539 = cast v2366 as u4 - v2540 = mul v2538, v2291 - v2541 = mul v2539, v2473 - v2542 = add v2540, v2541 - v2543 = cast v1984 as u4 - v2544 = cast v2366 as u4 - v2545 = mul v2543, v2298 - v2546 = mul v2544, v2478 - v2547 = add v2545, v2546 - v2548 = cast v1984 as u4 - v2549 = cast v2366 as u4 - v2550 = mul v2548, v2305 - v2551 = mul v2549, v2483 - v2552 = add v2550, v2551 - v2553 = cast v1984 as u4 - v2554 = cast v2366 as u4 - v2555 = mul v2553, v2312 - v2556 = cast v1984 as u4 - v2557 = cast v2366 as u4 - v2558 = mul v2556, v2319 - v2559 = cast v1984 as u4 - v2560 = cast v2366 as u4 - v2561 = mul v2559, v2326 - v2562 = cast v1984 as u4 - v2563 = cast v2366 as u4 - v2564 = mul v2562, v2331 - v2565 = cast v1984 as u4 - v2566 = cast v2366 as u4 - v2567 = mul v2565, v2336 - v2568 = cast v1984 as u4 - v2569 = cast v2366 as u4 - v2570 = cast v1984 as u4 - v2571 = cast v2366 as u4 - v2572 = cast v1984 as u4 - v2573 = cast v2366 as u4 - v2574 = cast v1984 as u4 - v2575 = cast v2366 as u4 - v2576 = cast v1984 as u4 - v2577 = cast v2366 as u4 - v2578 = cast v1984 as u4 - v2579 = cast v2366 as u4 - v2580 = cast v1984 as u4 - v2581 = cast v2366 as u4 - v2584 = mul Field 2, v1 - v2585 = cast v1984 as Field - v2586 = add v2584, v2585 - v2587 = sub v2586, Field 2 - inc_rc [v2537, v2542, v2547, v2552, v2555, v2558, v2561, v2564, v2567, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - inc_rc [v2537, v2542, v2547, v2552, v2555, v2558, v2561, v2564, v2567, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - inc_rc [v2537, v2542, v2547, v2552, v2555, v2558, v2561, v2564, v2567, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v2591 = eq v2587, Field 5 - constrain v2587 == Field 5 - v2597 = allocate - v2598 = eq v2537, u4 15 - v2599 = eq v2542, u4 1 - v2600 = mul v2598, v2599 - v2601 = eq v2547, u4 12 - v2602 = mul v2600, v2601 - v2603 = eq v2552, u4 11 - v2604 = mul v2602, v2603 - v2605 = eq v2555, u4 8 - v2606 = mul v2604, v2605 - constrain v2606 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v2611 = allocate - range_check u8 148 to 8 bits - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v2616 = allocate - v2617 = allocate - v2618 = allocate - v2619 = allocate - v2620 = allocate - return -} - -After Constant Folding: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v2621 = truncate v1 to 64 bits, max_bit_size: 254 - v2622 = cast v2621 as u64 - inc_rc v0 - v2623 = lt u64 5, v2622 - v2624 = not v2623 - constrain v2623 == u1 0 - inc_rc [u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v2625 = allocate - v2626 = array_get v0, index Field 0 - v2627 = div v2626, Field 2⁴ - v2628 = truncate v2627 to 4 bits, max_bit_size: 8 - v2629 = cast v2628 as u4 - v2630 = truncate v2629 to 1 bits, max_bit_size: 4 - v2631 = cast v2630 as u1 - enable_side_effects v2631 - v2632 = and v2626, u8 15 - v2633 = truncate v2632 to 4 bits, max_bit_size: 8 - v2634 = cast v2633 as u4 - inc_rc v0 - v2635 = lt u64 1, v2622 - v2636 = mul v2631, v2635 - enable_side_effects v2636 - v2637 = array_get v0, index Field 1 - v2638 = div v2637, Field 2⁴ - v2639 = truncate v2638 to 4 bits, max_bit_size: 8 - v2640 = cast v2639 as u4 - v2641 = and v2637, u8 15 - v2642 = truncate v2641 to 4 bits, max_bit_size: 8 - v2643 = cast v2642 as u4 - v2644 = not v2635 - enable_side_effects v2631 - v2645 = cast v2635 as u4 - v2646 = cast v2644 as u4 - v2647 = mul v2645, v2634 - v2648 = mul v2646, v2634 - v2649 = add v2647, v2648 - v2650 = mul v2645, v2640 - v2651 = mul v2645, v2643 - v2652 = lt u64 2, v2622 - v2653 = mul v2631, v2652 - enable_side_effects v2653 - v2654 = array_get v0, index Field 2 - v2655 = div v2654, Field 2⁴ - v2656 = truncate v2655 to 4 bits, max_bit_size: 8 - v2657 = cast v2656 as u4 - v2658 = and v2654, u8 15 - v2659 = truncate v2658 to 4 bits, max_bit_size: 8 - v2660 = cast v2659 as u4 - v2661 = not v2652 - enable_side_effects v2631 - v2662 = cast v2652 as u4 - v2663 = cast v2661 as u4 - v2664 = mul v2662, v2649 - v2665 = mul v2663, v2649 - v2666 = add v2664, v2665 - v2667 = mul v2662, v2650 - v2668 = mul v2663, v2650 - v2669 = add v2667, v2668 - v2670 = mul v2662, v2651 - v2671 = mul v2663, v2651 - v2672 = add v2670, v2671 - v2673 = mul v2662, v2657 - v2674 = mul v2662, v2660 - v2675 = lt u64 3, v2622 - v2676 = mul v2631, v2675 - enable_side_effects v2676 - v2677 = array_get v0, index Field 3 - v2678 = div v2677, Field 2⁴ - v2679 = truncate v2678 to 4 bits, max_bit_size: 8 - v2680 = cast v2679 as u4 - v2681 = and v2677, u8 15 - v2682 = truncate v2681 to 4 bits, max_bit_size: 8 - v2683 = cast v2682 as u4 - v2684 = not v2675 - enable_side_effects v2631 - v2685 = cast v2675 as u4 - v2686 = cast v2684 as u4 - v2687 = mul v2685, v2666 - v2688 = mul v2686, v2666 - v2689 = add v2687, v2688 - v2690 = mul v2685, v2669 - v2691 = mul v2686, v2669 - v2692 = add v2690, v2691 - v2693 = mul v2685, v2672 - v2694 = mul v2686, v2672 - v2695 = add v2693, v2694 - v2696 = mul v2685, v2673 - v2697 = mul v2686, v2673 - v2698 = add v2696, v2697 - v2699 = mul v2685, v2674 - v2700 = mul v2686, v2674 - v2701 = add v2699, v2700 - v2702 = mul v2685, v2680 - v2703 = mul v2685, v2683 - v2704 = lt u64 4, v2622 - v2705 = mul v2631, v2704 - enable_side_effects v2705 - v2706 = array_get v0, index Field 4 - v2707 = div v2706, Field 2⁴ - v2708 = truncate v2707 to 4 bits, max_bit_size: 8 - v2709 = cast v2708 as u4 - v2710 = and v2706, u8 15 - v2711 = truncate v2710 to 4 bits, max_bit_size: 8 - v2712 = cast v2711 as u4 - v2713 = not v2704 - enable_side_effects v2631 - v2714 = cast v2704 as u4 - v2715 = cast v2713 as u4 - v2716 = mul v2714, v2689 - v2717 = mul v2715, v2689 - v2718 = add v2716, v2717 - v2719 = mul v2714, v2692 - v2720 = mul v2715, v2692 - v2721 = add v2719, v2720 - v2722 = mul v2714, v2695 - v2723 = mul v2715, v2695 - v2724 = add v2722, v2723 - v2725 = mul v2714, v2698 - v2726 = mul v2715, v2698 - v2727 = add v2725, v2726 - v2728 = mul v2714, v2701 - v2729 = mul v2715, v2701 - v2730 = add v2728, v2729 - v2731 = mul v2714, v2702 - v2732 = mul v2715, v2702 - v2733 = add v2731, v2732 - v2734 = mul v2714, v2703 - v2735 = mul v2715, v2703 - v2736 = add v2734, v2735 - v2737 = mul v2714, v2709 - v2738 = mul v2714, v2712 - v2739 = not v2631 - enable_side_effects v2739 - v2740 = sub v2622, u64 1 - v2741 = cast v2739 as u64 - v2742 = mul v2740, v2741 - range_check v2742 to 64 bits - v2743 = lt u64 0, v2740 - v2744 = mul v2739, v2743 - enable_side_effects v2744 - v2745 = array_get v0, index u64 1 - v2746 = div v2745, Field 2⁴ - v2747 = truncate v2746 to 4 bits, max_bit_size: 8 - v2748 = cast v2747 as u4 - v2749 = and v2745, u8 15 - v2750 = truncate v2749 to 4 bits, max_bit_size: 8 - v2751 = cast v2750 as u4 - v2752 = not v2743 - enable_side_effects v2739 - v2753 = cast v2743 as u4 - v2754 = cast v2752 as u4 - v2755 = mul v2753, v2748 - v2756 = mul v2753, v2751 - range_check v2742 to 64 bits - v2757 = lt u64 1, v2740 - v2758 = mul v2739, v2757 - enable_side_effects v2758 - v2759 = array_get v0, index u64 2 - v2760 = div v2759, Field 2⁴ - v2761 = truncate v2760 to 4 bits, max_bit_size: 8 - v2762 = cast v2761 as u4 - v2763 = and v2759, u8 15 - v2764 = truncate v2763 to 4 bits, max_bit_size: 8 - v2765 = cast v2764 as u4 - v2766 = not v2757 - enable_side_effects v2739 - v2767 = cast v2757 as u4 - v2768 = cast v2766 as u4 - v2769 = mul v2767, v2755 - v2770 = mul v2768, v2755 - v2771 = add v2769, v2770 - v2772 = mul v2767, v2756 - v2773 = mul v2768, v2756 - v2774 = add v2772, v2773 - v2775 = mul v2767, v2762 - v2776 = mul v2767, v2765 - enable_side_effects u1 1 - v2777 = cast v2631 as u4 - v2778 = cast v2739 as u4 - v2779 = mul v2777, v2718 - v2780 = mul v2778, v2771 - v2781 = add v2779, v2780 - v2782 = mul v2777, v2721 - v2783 = mul v2778, v2774 - v2784 = add v2782, v2783 - v2785 = mul v2777, v2724 - v2786 = mul v2778, v2775 - v2787 = add v2785, v2786 - v2788 = mul v2777, v2727 - v2789 = mul v2778, v2776 - v2790 = add v2788, v2789 - v2791 = mul v2777, v2730 - v2792 = mul v2777, v2733 - v2793 = mul v2777, v2736 - v2794 = mul v2777, v2737 - v2795 = mul v2777, v2738 - v2796 = mul Field 2, v1 - v2797 = cast v2631 as Field - v2798 = add v2796, v2797 - v2799 = sub v2798, Field 2 - inc_rc [v2781, v2784, v2787, v2790, v2791, v2792, v2793, v2794, v2795, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - inc_rc [v2781, v2784, v2787, v2790, v2791, v2792, v2793, v2794, v2795, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - inc_rc [v2781, v2784, v2787, v2790, v2791, v2792, v2793, v2794, v2795, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0, u4 0] - v2800 = eq v2799, Field 5 - constrain v2799 == Field 5 - v2801 = allocate - v2802 = eq v2781, u4 15 - v2803 = eq v2784, u4 1 - v2804 = mul v2802, v2803 - v2805 = eq v2787, u4 12 - v2806 = mul v2804, v2805 - v2807 = eq v2790, u4 11 - v2808 = mul v2806, v2807 - v2809 = eq v2791, u4 8 - v2810 = mul v2808, v2809 - constrain v2810 == u1 1 - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v2811 = allocate - range_check u8 148 to 8 bits - inc_rc [u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - inc_rc [u8 148, u8 184, u8 143, u8 97, u8 230, u8 251, u8 218, u8 131, u8 251, u8 255, u8 250, u8 190, u8 54, u8 65, u8 18, u8 19, u8 116, u8 2⁷, u8 57, u8 2⁷, u8 24, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0, u8 0] - v2812 = allocate - v2813 = allocate - v2814 = allocate - v2815 = allocate - v2816 = allocate - return -} - -After Dead Instruction Elimination: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v2621 = truncate v1 to 64 bits, max_bit_size: 254 - v2622 = cast v2621 as u64 - inc_rc v0 - v2623 = lt u64 5, v2622 - constrain v2623 == u1 0 - v2626 = array_get v0, index Field 0 - v2627 = div v2626, Field 2⁴ - v2628 = truncate v2627 to 4 bits, max_bit_size: 8 - v2629 = cast v2628 as u4 - v2630 = truncate v2629 to 1 bits, max_bit_size: 4 - v2631 = cast v2630 as u1 - enable_side_effects v2631 - v2632 = and v2626, u8 15 - v2633 = truncate v2632 to 4 bits, max_bit_size: 8 - v2634 = cast v2633 as u4 - inc_rc v0 - v2635 = lt u64 1, v2622 - v2636 = mul v2631, v2635 - enable_side_effects v2636 - v2637 = array_get v0, index Field 1 - v2638 = div v2637, Field 2⁴ - v2639 = truncate v2638 to 4 bits, max_bit_size: 8 - v2640 = cast v2639 as u4 - v2641 = and v2637, u8 15 - v2642 = truncate v2641 to 4 bits, max_bit_size: 8 - v2643 = cast v2642 as u4 - v2644 = not v2635 - enable_side_effects v2631 - v2645 = cast v2635 as u4 - v2646 = cast v2644 as u4 - v2647 = mul v2645, v2634 - v2648 = mul v2646, v2634 - v2649 = add v2647, v2648 - v2650 = mul v2645, v2640 - v2651 = mul v2645, v2643 - v2652 = lt u64 2, v2622 - v2653 = mul v2631, v2652 - enable_side_effects v2653 - v2654 = array_get v0, index Field 2 - v2655 = div v2654, Field 2⁴ - v2656 = truncate v2655 to 4 bits, max_bit_size: 8 - v2657 = cast v2656 as u4 - v2658 = and v2654, u8 15 - v2659 = truncate v2658 to 4 bits, max_bit_size: 8 - v2660 = cast v2659 as u4 - v2661 = not v2652 - enable_side_effects v2631 - v2662 = cast v2652 as u4 - v2663 = cast v2661 as u4 - v2664 = mul v2662, v2649 - v2665 = mul v2663, v2649 - v2666 = add v2664, v2665 - v2667 = mul v2662, v2650 - v2668 = mul v2663, v2650 - v2669 = add v2667, v2668 - v2670 = mul v2662, v2651 - v2671 = mul v2663, v2651 - v2672 = add v2670, v2671 - v2673 = mul v2662, v2657 - v2674 = mul v2662, v2660 - v2675 = lt u64 3, v2622 - v2676 = mul v2631, v2675 - enable_side_effects v2676 - v2684 = not v2675 - enable_side_effects v2631 - v2685 = cast v2675 as u4 - v2686 = cast v2684 as u4 - v2687 = mul v2685, v2666 - v2688 = mul v2686, v2666 - v2689 = add v2687, v2688 - v2690 = mul v2685, v2669 - v2691 = mul v2686, v2669 - v2692 = add v2690, v2691 - v2693 = mul v2685, v2672 - v2694 = mul v2686, v2672 - v2695 = add v2693, v2694 - v2696 = mul v2685, v2673 - v2697 = mul v2686, v2673 - v2698 = add v2696, v2697 - v2699 = mul v2685, v2674 - v2700 = mul v2686, v2674 - v2701 = add v2699, v2700 - v2704 = lt u64 4, v2622 - v2705 = mul v2631, v2704 - enable_side_effects v2705 - v2713 = not v2704 - enable_side_effects v2631 - v2714 = cast v2704 as u4 - v2715 = cast v2713 as u4 - v2716 = mul v2714, v2689 - v2717 = mul v2715, v2689 - v2718 = add v2716, v2717 - v2719 = mul v2714, v2692 - v2720 = mul v2715, v2692 - v2721 = add v2719, v2720 - v2722 = mul v2714, v2695 - v2723 = mul v2715, v2695 - v2724 = add v2722, v2723 - v2725 = mul v2714, v2698 - v2726 = mul v2715, v2698 - v2727 = add v2725, v2726 - v2728 = mul v2714, v2701 - v2729 = mul v2715, v2701 - v2730 = add v2728, v2729 - v2739 = not v2631 - enable_side_effects v2739 - v2740 = sub v2622, u64 1 - v2741 = cast v2739 as u64 - v2742 = mul v2740, v2741 - range_check v2742 to 64 bits - v2743 = lt u64 0, v2740 - v2744 = mul v2739, v2743 - enable_side_effects v2744 - v2745 = array_get v0, index u64 1 - v2746 = div v2745, Field 2⁴ - v2747 = truncate v2746 to 4 bits, max_bit_size: 8 - v2748 = cast v2747 as u4 - v2749 = and v2745, u8 15 - v2750 = truncate v2749 to 4 bits, max_bit_size: 8 - v2751 = cast v2750 as u4 - enable_side_effects v2739 - v2753 = cast v2743 as u4 - v2755 = mul v2753, v2748 - v2756 = mul v2753, v2751 - range_check v2742 to 64 bits - v2757 = lt u64 1, v2740 - v2758 = mul v2739, v2757 - enable_side_effects v2758 - v2759 = array_get v0, index u64 2 - v2760 = div v2759, Field 2⁴ - v2761 = truncate v2760 to 4 bits, max_bit_size: 8 - v2762 = cast v2761 as u4 - v2763 = and v2759, u8 15 - v2764 = truncate v2763 to 4 bits, max_bit_size: 8 - v2765 = cast v2764 as u4 - v2766 = not v2757 - enable_side_effects v2739 - v2767 = cast v2757 as u4 - v2768 = cast v2766 as u4 - v2769 = mul v2767, v2755 - v2770 = mul v2768, v2755 - v2771 = add v2769, v2770 - v2772 = mul v2767, v2756 - v2773 = mul v2768, v2756 - v2774 = add v2772, v2773 - v2775 = mul v2767, v2762 - v2776 = mul v2767, v2765 - enable_side_effects u1 1 - v2777 = cast v2631 as u4 - v2778 = cast v2739 as u4 - v2779 = mul v2777, v2718 - v2780 = mul v2778, v2771 - v2781 = add v2779, v2780 - v2782 = mul v2777, v2721 - v2783 = mul v2778, v2774 - v2784 = add v2782, v2783 - v2785 = mul v2777, v2724 - v2786 = mul v2778, v2775 - v2787 = add v2785, v2786 - v2788 = mul v2777, v2727 - v2789 = mul v2778, v2776 - v2790 = add v2788, v2789 - v2791 = mul v2777, v2730 - v2796 = mul Field 2, v1 - v2797 = cast v2631 as Field - v2798 = add v2796, v2797 - v2799 = sub v2798, Field 2 - constrain v2799 == Field 5 - v2802 = eq v2781, u4 15 - v2803 = eq v2784, u4 1 - v2804 = mul v2802, v2803 - v2805 = eq v2787, u4 12 - v2806 = mul v2804, v2805 - v2807 = eq v2790, u4 11 - v2808 = mul v2806, v2807 - v2809 = eq v2791, u4 8 - v2810 = mul v2808, v2809 - constrain v2810 == u1 1 - range_check u8 148 to 8 bits - return -} - -After Fill Internal Slice Dummy Data: -acir fn main f0 { - b0(v0: [u8; 5], v1: Field): - inc_rc v0 - inc_rc v0 - v2817 = truncate v1 to 64 bits, max_bit_size: 254 - v2818 = cast v2817 as u64 - inc_rc v0 - v2819 = lt u64 5, v2818 - constrain v2819 == u1 0 - v2820 = array_get v0, index Field 0 - v2821 = div v2820, Field 2⁴ - v2822 = truncate v2821 to 4 bits, max_bit_size: 8 - v2823 = cast v2822 as u4 - v2824 = truncate v2823 to 1 bits, max_bit_size: 4 - v2825 = cast v2824 as u1 - enable_side_effects v2825 - v2826 = and v2820, u8 15 - v2827 = truncate v2826 to 4 bits, max_bit_size: 8 - v2828 = cast v2827 as u4 - inc_rc v0 - v2829 = lt u64 1, v2818 - v2830 = mul v2825, v2829 - enable_side_effects v2830 - v2831 = array_get v0, index Field 1 - v2832 = div v2831, Field 2⁴ - v2833 = truncate v2832 to 4 bits, max_bit_size: 8 - v2834 = cast v2833 as u4 - v2835 = and v2831, u8 15 - v2836 = truncate v2835 to 4 bits, max_bit_size: 8 - v2837 = cast v2836 as u4 - v2838 = not v2829 - enable_side_effects v2825 - v2839 = cast v2829 as u4 - v2840 = cast v2838 as u4 - v2841 = mul v2839, v2828 - v2842 = mul v2840, v2828 - v2843 = add v2841, v2842 - v2844 = mul v2839, v2834 - v2845 = mul v2839, v2837 - v2846 = lt u64 2, v2818 - v2847 = mul v2825, v2846 - enable_side_effects v2847 - v2848 = array_get v0, index Field 2 - v2849 = div v2848, Field 2⁴ - v2850 = truncate v2849 to 4 bits, max_bit_size: 8 - v2851 = cast v2850 as u4 - v2852 = and v2848, u8 15 - v2853 = truncate v2852 to 4 bits, max_bit_size: 8 - v2854 = cast v2853 as u4 - v2855 = not v2846 - enable_side_effects v2825 - v2856 = cast v2846 as u4 - v2857 = cast v2855 as u4 - v2858 = mul v2856, v2843 - v2859 = mul v2857, v2843 - v2860 = add v2858, v2859 - v2861 = mul v2856, v2844 - v2862 = mul v2857, v2844 - v2863 = add v2861, v2862 - v2864 = mul v2856, v2845 - v2865 = mul v2857, v2845 - v2866 = add v2864, v2865 - v2867 = mul v2856, v2851 - v2868 = mul v2856, v2854 - v2869 = lt u64 3, v2818 - v2870 = mul v2825, v2869 - enable_side_effects v2870 - v2871 = not v2869 - enable_side_effects v2825 - v2872 = cast v2869 as u4 - v2873 = cast v2871 as u4 - v2874 = mul v2872, v2860 - v2875 = mul v2873, v2860 - v2876 = add v2874, v2875 - v2877 = mul v2872, v2863 - v2878 = mul v2873, v2863 - v2879 = add v2877, v2878 - v2880 = mul v2872, v2866 - v2881 = mul v2873, v2866 - v2882 = add v2880, v2881 - v2883 = mul v2872, v2867 - v2884 = mul v2873, v2867 - v2885 = add v2883, v2884 - v2886 = mul v2872, v2868 - v2887 = mul v2873, v2868 - v2888 = add v2886, v2887 - v2889 = lt u64 4, v2818 - v2890 = mul v2825, v2889 - enable_side_effects v2890 - v2891 = not v2889 - enable_side_effects v2825 - v2892 = cast v2889 as u4 - v2893 = cast v2891 as u4 - v2894 = mul v2892, v2876 - v2895 = mul v2893, v2876 - v2896 = add v2894, v2895 - v2897 = mul v2892, v2879 - v2898 = mul v2893, v2879 - v2899 = add v2897, v2898 - v2900 = mul v2892, v2882 - v2901 = mul v2893, v2882 - v2902 = add v2900, v2901 - v2903 = mul v2892, v2885 - v2904 = mul v2893, v2885 - v2905 = add v2903, v2904 - v2906 = mul v2892, v2888 - v2907 = mul v2893, v2888 - v2908 = add v2906, v2907 - v2909 = not v2825 - enable_side_effects v2909 - v2910 = sub v2818, u64 1 - v2911 = cast v2909 as u64 - v2912 = mul v2910, v2911 - range_check v2912 to 64 bits - v2913 = lt u64 0, v2910 - v2914 = mul v2909, v2913 - enable_side_effects v2914 - v2915 = array_get v0, index u64 1 - v2916 = div v2915, Field 2⁴ - v2917 = truncate v2916 to 4 bits, max_bit_size: 8 - v2918 = cast v2917 as u4 - v2919 = and v2915, u8 15 - v2920 = truncate v2919 to 4 bits, max_bit_size: 8 - v2921 = cast v2920 as u4 - enable_side_effects v2909 - v2922 = cast v2913 as u4 - v2923 = mul v2922, v2918 - v2924 = mul v2922, v2921 - range_check v2912 to 64 bits - v2925 = lt u64 1, v2910 - v2926 = mul v2909, v2925 - enable_side_effects v2926 - v2927 = array_get v0, index u64 2 - v2928 = div v2927, Field 2⁴ - v2929 = truncate v2928 to 4 bits, max_bit_size: 8 - v2930 = cast v2929 as u4 - v2931 = and v2927, u8 15 - v2932 = truncate v2931 to 4 bits, max_bit_size: 8 - v2933 = cast v2932 as u4 - v2934 = not v2925 - enable_side_effects v2909 - v2935 = cast v2925 as u4 - v2936 = cast v2934 as u4 - v2937 = mul v2935, v2923 - v2938 = mul v2936, v2923 - v2939 = add v2937, v2938 - v2940 = mul v2935, v2924 - v2941 = mul v2936, v2924 - v2942 = add v2940, v2941 - v2943 = mul v2935, v2930 - v2944 = mul v2935, v2933 - enable_side_effects u1 1 - v2945 = cast v2825 as u4 - v2946 = cast v2909 as u4 - v2947 = mul v2945, v2896 - v2948 = mul v2946, v2939 - v2949 = add v2947, v2948 - v2950 = mul v2945, v2899 - v2951 = mul v2946, v2942 - v2952 = add v2950, v2951 - v2953 = mul v2945, v2902 - v2954 = mul v2946, v2943 - v2955 = add v2953, v2954 - v2956 = mul v2945, v2905 - v2957 = mul v2946, v2944 - v2958 = add v2956, v2957 - v2959 = mul v2945, v2908 - v2960 = mul Field 2, v1 - v2961 = cast v2825 as Field - v2962 = add v2960, v2961 - v2963 = sub v2962, Field 2 - constrain v2963 == Field 5 - v2964 = eq v2949, u4 15 - v2965 = eq v2952, u4 1 - v2966 = mul v2964, v2965 - v2967 = eq v2955, u4 12 - v2968 = mul v2966, v2967 - v2969 = eq v2958, u4 11 - v2970 = mul v2968, v2969 - v2971 = eq v2959, u4 8 - v2972 = mul v2970, v2971 - constrain v2972 == u1 1 - range_check u8 148 to 8 bits - return -} - diff --git a/test_programs/execution_success/regression/old-acir b/test_programs/execution_success/regression/old-acir deleted file mode 100644 index 44e1ded5777..00000000000 --- a/test_programs/execution_success/regression/old-acir +++ /dev/null @@ -1,288 +0,0 @@ -Compiled ACIR for main (unoptimized): -current witness index : 132 -public parameters indices : [] -return value indices : [] -BLACKBOX::RANGE [(_1, num_bits: 8)] [ ] -BLACKBOX::RANGE [(_2, num_bits: 8)] [ ] -BLACKBOX::RANGE [(_3, num_bits: 8)] [ ] -BLACKBOX::RANGE [(_4, num_bits: 8)] [ ] -BLACKBOX::RANGE [(_5, num_bits: 8)] [ ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(6))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(7)), Simple(Witness(8))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 255, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 255, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 255, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_7, num_bits: 190)] [ ] -BLACKBOX::RANGE [(_8, num_bits: 64)] [ ] -EXPR [ (1, _6) (-2⁶⁴, _7) (-1, _8) 0 ] -EXPR [ (1, _7) (-1, _9) -1186564023676924939888766319973246049704924238154051448977 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(9))], q_c: 0 })] -outputs: [Simple(Witness(10))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _9, _10) (1, _11) -1 ] -EXPR [ (1, _9, _11) 0 ] -EXPR [ (-1, _8, _11) (2¹⁶×74637766815744, _11) (-1, _12) 0 ] -BLACKBOX::RANGE [(_12, num_bits: 65)] [ ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551621 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(13)), Simple(Witness(14))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_14, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _13) (-1, _14) 18446744073709551621 ] -EXPR [ (-1, _13) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(1))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(15)), Simple(Witness(16))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_15, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_16, num_bits: 4)] [ ] -EXPR [ (1, _1) (-2⁴, _15) (-1, _16) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(15))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(17)), Simple(Witness(18))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_17, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_18, num_bits: 4)] [ ] -EXPR [ (1, _15) (-2⁴, _17) (-1, _18) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(18))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2 })] -outputs: [Simple(Witness(19)), Simple(Witness(20))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 5, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 5, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 5, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_19, num_bits: 3)] [ ] -EXPR [ (1, _20, _20) (-1, _20) 0 ] -EXPR [ (1, _18) (-2, _19) (-1, _20) 0 ] -EXPR [ (-1, _21) 15 ] -BLACKBOX::AND [(_1, num_bits: 8), (_21, num_bits: 8)] [ _22] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(22))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(23)), Simple(Witness(24))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_23, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_24, num_bits: 4)] [ ] -EXPR [ (1, _22) (-2⁴, _23) (-1, _24) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551617 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(25)), Simple(Witness(26))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _25, _25) (-1, _25) 0 ] -BLACKBOX::RANGE [(_26, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _25) (-1, _26) 18446744073709551617 ] -EXPR [ (-1, _25) (-1, _27) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(2))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(28)), Simple(Witness(29))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_28, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_29, num_bits: 5)] [ ] -EXPR [ (1, _20, _27) (1, _29) (-1, _30) 15 ] -BLACKBOX::RANGE [(_30, num_bits: 5)] [ ] -EXPR [ (2⁴, _28) (1, _29) (-1, _31) 0 ] -EXPR [ (1, _20, _27) (-1, _32) 0 ] -EXPR [ (1, _2, _32) (-1, _31, _32) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(28))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(33)), Simple(Witness(34))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_33, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_34, num_bits: 4)] [ ] -EXPR [ (1, _28) (-2⁴, _33) (-1, _34) 0 ] -BLACKBOX::AND [(_2, num_bits: 8), (_21, num_bits: 8)] [ _35] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(35))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(36)), Simple(Witness(37))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_36, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_37, num_bits: 4)] [ ] -EXPR [ (1, _35) (-2⁴, _36) (-1, _37) 0 ] -EXPR [ (-1, _27) (-1, _38) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551618 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(39)), Simple(Witness(40))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _39, _39) (-1, _39) 0 ] -BLACKBOX::RANGE [(_40, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _39) (-1, _40) 18446744073709551618 ] -EXPR [ (-1, _39) (-1, _41) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(3))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(42)), Simple(Witness(43))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_42, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_43, num_bits: 5)] [ ] -EXPR [ (1, _20, _41) (1, _43) (-1, _44) 15 ] -BLACKBOX::RANGE [(_44, num_bits: 5)] [ ] -EXPR [ (2⁴, _42) (1, _43) (-1, _45) 0 ] -EXPR [ (1, _20, _41) (-1, _46) 0 ] -EXPR [ (1, _3, _46) (-1, _45, _46) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(42))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(47)), Simple(Witness(48))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_47, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_48, num_bits: 4)] [ ] -EXPR [ (1, _42) (-2⁴, _47) (-1, _48) 0 ] -BLACKBOX::AND [(_3, num_bits: 8), (_21, num_bits: 8)] [ _49] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(49))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(50)), Simple(Witness(51))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_50, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_51, num_bits: 4)] [ ] -EXPR [ (1, _49) (-2⁴, _50) (-1, _51) 0 ] -EXPR [ (1, _24, _27) (1, _24, _38) (-1, _52) 0 ] -EXPR [ (-1, _41) (-1, _53) 1 ] -EXPR [ (1, _27, _34) (-1, _54) 0 ] -EXPR [ (1, _27, _37) (-1, _55) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551619 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(56)), Simple(Witness(57))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _56, _56) (-1, _56) 0 ] -BLACKBOX::RANGE [(_57, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _56) (-1, _57) 18446744073709551619 ] -EXPR [ (-1, _56) (-1, _58) 1 ] -EXPR [ (1, _41, _52) (1, _52, _53) (-1, _59) 0 ] -EXPR [ (-1, _58) (-1, _60) 1 ] -EXPR [ (1, _41, _54) (1, _53, _54) (-1, _61) 0 ] -EXPR [ (1, _41, _55) (1, _53, _55) (-1, _62) 0 ] -EXPR [ (1, _41, _48) (-1, _63) 0 ] -EXPR [ (1, _41, _51) (-1, _64) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(8))], q_c: 18446744073709551620 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(65)), Simple(Witness(66))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _65, _65) (-1, _65) 0 ] -BLACKBOX::RANGE [(_66, num_bits: 64)] [ ] -EXPR [ (-1, _8) (-2⁶⁴, _65) (-1, _66) 18446744073709551620 ] -EXPR [ (-1, _65) (-1, _67) 1 ] -EXPR [ (1, _58, _59) (1, _59, _60) (-1, _68) 0 ] -EXPR [ (-1, _67) (-1, _69) 1 ] -EXPR [ (1, _58, _61) (1, _60, _61) (-1, _70) 0 ] -EXPR [ (1, _58, _62) (1, _60, _62) (-1, _71) 0 ] -EXPR [ (1, _58, _63) (1, _60, _63) (-1, _72) 0 ] -EXPR [ (1, _58, _64) (1, _60, _64) (-1, _73) 0 ] -EXPR [ (1, _8) (-1, _74) -1 ] -EXPR [ (-1, _20) (-1, _75) 1 ] -EXPR [ (1, _74, _75) (-1, _76) 0 ] -BLACKBOX::RANGE [(_76, num_bits: 64)] [ ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(74))], q_c: 2⁶⁴ }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(77)), Simple(Witness(78))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _77, _77) (-1, _77) 0 ] -BLACKBOX::RANGE [(_78, num_bits: 64)] [ ] -EXPR [ (-1, _74) (-2⁶⁴, _77) (-1, _78) 2⁶⁴ ] -EXPR [ (-1, _77) (-1, _79) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(2))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(80)), Simple(Witness(81))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_80, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_81, num_bits: 5)] [ ] -EXPR [ (1, _75, _79) (1, _81) (-1, _82) 15 ] -BLACKBOX::RANGE [(_82, num_bits: 5)] [ ] -EXPR [ (2⁴, _80) (1, _81) (-1, _83) 0 ] -EXPR [ (1, _75, _79) (-1, _84) 0 ] -EXPR [ (1, _2, _84) (-1, _83, _84) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(80))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(85)), Simple(Witness(86))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_85, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_86, num_bits: 4)] [ ] -EXPR [ (1, _80) (-2⁴, _85) (-1, _86) 0 ] -BLACKBOX::AND [(_2, num_bits: 8), (_21, num_bits: 8)] [ _87] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(87))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(88)), Simple(Witness(89))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_88, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_89, num_bits: 4)] [ ] -EXPR [ (1, _87) (-2⁴, _88) (-1, _89) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(-1, Witness(74))], q_c: 18446744073709551617 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁶⁴ })] -outputs: [Simple(Witness(90)), Simple(Witness(91))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 66, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 66, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -EXPR [ (1, _90, _90) (-1, _90) 0 ] -BLACKBOX::RANGE [(_91, num_bits: 64)] [ ] -EXPR [ (-1, _74) (-2⁶⁴, _90) (-1, _91) 18446744073709551617 ] -EXPR [ (-1, _90) (-1, _92) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(3))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(93)), Simple(Witness(94))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_93, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_94, num_bits: 5)] [ ] -EXPR [ (1, _75, _92) (1, _94) (-1, _95) 15 ] -BLACKBOX::RANGE [(_95, num_bits: 5)] [ ] -EXPR [ (2⁴, _93) (1, _94) (-1, _96) 0 ] -EXPR [ (1, _75, _92) (-1, _97) 0 ] -EXPR [ (1, _3, _97) (-1, _96, _97) 0 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(93))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(98)), Simple(Witness(99))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_98, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_99, num_bits: 4)] [ ] -EXPR [ (1, _93) (-2⁴, _98) (-1, _99) 0 ] -BLACKBOX::AND [(_3, num_bits: 8), (_21, num_bits: 8)] [ _100] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(100))], q_c: 0 }), Single(Expression { mul_terms: [], linear_combinations: [], q_c: 2⁴ })] -outputs: [Simple(Witness(101)), Simple(Witness(102))] -[BinaryIntOp { destination: RegisterIndex(2), op: UnsignedDiv, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Mul, bit_size: 9, lhs: RegisterIndex(2), rhs: RegisterIndex(1) }, BinaryIntOp { destination: RegisterIndex(1), op: Sub, bit_size: 9, lhs: RegisterIndex(0), rhs: RegisterIndex(1) }, Mov { destination: RegisterIndex(0), source: RegisterIndex(2) }, Stop] - -BLACKBOX::RANGE [(_101, num_bits: 4)] [ ] -BLACKBOX::RANGE [(_102, num_bits: 4)] [ ] -EXPR [ (1, _100) (-2⁴, _101) (-1, _102) 0 ] -EXPR [ (1, _79, _86) (-1, _103) 0 ] -EXPR [ (-1, _92) (-1, _104) 1 ] -EXPR [ (1, _79, _89) (-1, _105) 0 ] -EXPR [ (1, _67, _68) (1, _68, _69) (-1, _106) 0 ] -EXPR [ (1, _92, _103) (1, _103, _104) (-1, _107) 0 ] -EXPR [ (1, _67, _70) (1, _69, _70) (-1, _108) 0 ] -EXPR [ (1, _92, _105) (1, _104, _105) (-1, _109) 0 ] -EXPR [ (1, _67, _71) (1, _69, _71) (-1, _110) 0 ] -EXPR [ (1, _92, _99) (-1, _111) 0 ] -EXPR [ (1, _67, _72) (1, _69, _72) (-1, _112) 0 ] -EXPR [ (1, _92, _102) (-1, _113) 0 ] -EXPR [ (1, _67, _73) (1, _69, _73) (-1, _114) 0 ] -EXPR [ (2, _6) (1, _20) -7 ] -EXPR [ (-1, _20, _106) (-1, _75, _107) (-1, _115) 15 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(115))], q_c: 0 })] -outputs: [Simple(Witness(116))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _115, _116) (1, _117) -1 ] -EXPR [ (1, _115, _117) 0 ] -EXPR [ (-1, _20, _108) (-1, _75, _109) (-1, _118) 1 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(118))], q_c: 0 })] -outputs: [Simple(Witness(119))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _118, _119) (1, _120) -1 ] -EXPR [ (1, _118, _120) 0 ] -EXPR [ (-1, _20, _110) (-1, _75, _111) (-1, _121) 12 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(121))], q_c: 0 })] -outputs: [Simple(Witness(122))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _121, _122) (1, _123) -1 ] -EXPR [ (1, _121, _123) 0 ] -EXPR [ (1, _117, _120) (-1, _124) 0 ] -EXPR [ (-1, _20, _112) (-1, _75, _113) (-1, _125) 11 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(125))], q_c: 0 })] -outputs: [Simple(Witness(126))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _125, _126) (1, _127) -1 ] -EXPR [ (1, _125, _127) 0 ] -EXPR [ (1, _123, _124) (-1, _128) 0 ] -EXPR [ (-1, _20, _114) (-1, _129) 8 ] -BRILLIG: inputs: [Single(Expression { mul_terms: [], linear_combinations: [(1, Witness(129))], q_c: 0 })] -outputs: [Simple(Witness(130))] -[JumpIfNot { condition: RegisterIndex(0), location: 3 }, Const { destination: RegisterIndex(1), value: Value { inner: 1 } }, BinaryFieldOp { destination: RegisterIndex(0), op: Div, lhs: RegisterIndex(1), rhs: RegisterIndex(0) }, Stop] - -EXPR [ (1, _129, _130) (1, _131) -1 ] -EXPR [ (1, _129, _131) 0 ] -EXPR [ (1, _127, _128) (-1, _132) 0 ] -EXPR [ (1, _131, _132) -1 ] -