From 78b3432be5602dce8b8107f798b302c16670f6b3 Mon Sep 17 00:00:00 2001 From: Levi Zim Date: Mon, 6 Nov 2023 23:19:55 +0800 Subject: [PATCH] deps: V8: cherry-pick 13192d6e10fa MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Original commit message: [riscv][tagged-ptr] Convert more Objects to Tagged<> Port commit 064b9a7903b793734b6c03a86ee53a2dc85f0f80 Bug: v8:12710 Change-Id: If076ca5cd9e9d175c20fc3611e03d39c0260404d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4837830 Reviewed-by: Ji Qiu Commit-Queue: Ji Qiu Auto-Submit: Yahan Lu Cr-Commit-Position: refs/heads/main@{#89780} Refs: https://github.com/v8/v8/commit/13192d6e10fa726858056e49fc9bca6201401171 PR-URL: https://github.com/nodejs/node/pull/50552 Reviewed-By: Richard Lau Reviewed-By: Michaël Zasso Reviewed-By: Debadree Chatterjee Reviewed-By: Jiawen Geng --- common.gypi | 2 +- deps/v8/src/builtins/riscv/builtins-riscv.cc | 2 +- deps/v8/src/codegen/riscv/assembler-riscv-inl.h | 15 ++++++++------- deps/v8/src/codegen/riscv/assembler-riscv.h | 2 +- deps/v8/src/execution/riscv/simulator-riscv.cc | 8 ++++---- .../regexp/riscv/regexp-macro-assembler-riscv.cc | 2 +- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/common.gypi b/common.gypi index d5328f39b28837..c51dbca5e74c5b 100644 --- a/common.gypi +++ b/common.gypi @@ -36,7 +36,7 @@ # Reset this number to 0 on major V8 upgrades. # Increment by one for each non-official patch applied to deps/v8. - 'v8_embedder_string': '-node.14', + 'v8_embedder_string': '-node.15', ##### V8 defaults for Node.js ##### diff --git a/deps/v8/src/builtins/riscv/builtins-riscv.cc b/deps/v8/src/builtins/riscv/builtins-riscv.cc index 326001fdd18add..638001f90549cc 100644 --- a/deps/v8/src/builtins/riscv/builtins-riscv.cc +++ b/deps/v8/src/builtins/riscv/builtins-riscv.cc @@ -1673,7 +1673,7 @@ static void Generate_InterpreterEnterBytecode(MacroAssembler* masm) { // Set the return address to the correct point in the interpreter entry // trampoline. Label builtin_trampoline, trampoline_loaded; - Smi interpreter_entry_return_pc_offset( + Tagged interpreter_entry_return_pc_offset( masm->isolate()->heap()->interpreter_entry_return_pc_offset()); DCHECK_NE(interpreter_entry_return_pc_offset, Smi::zero()); diff --git a/deps/v8/src/codegen/riscv/assembler-riscv-inl.h b/deps/v8/src/codegen/riscv/assembler-riscv-inl.h index 773dc560da1e64..8abf4b3239ff6d 100644 --- a/deps/v8/src/codegen/riscv/assembler-riscv-inl.h +++ b/deps/v8/src/codegen/riscv/assembler-riscv-inl.h @@ -128,9 +128,9 @@ Handle Assembler::compressed_embedded_object_handle_at( } void Assembler::deserialization_set_special_target_at( - Address instruction_payload, Code code, Address target) { + Address instruction_payload, Tagged code, Address target) { set_target_address_at(instruction_payload, - !code.is_null() ? code.constant_pool() : kNullAddress, + !code.is_null() ? code->constant_pool() : kNullAddress, target); } @@ -159,12 +159,13 @@ void Assembler::deserialization_set_target_internal_reference_at( } } -HeapObject RelocInfo::target_object(PtrComprCageBase cage_base) { +Tagged RelocInfo::target_object(PtrComprCageBase cage_base) { DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_)); if (IsCompressedEmbeddedObject(rmode_)) { - return HeapObject::cast(Object(V8HeapCompressionScheme::DecompressTagged( - cage_base, - Assembler::target_compressed_address_at(pc_, constant_pool_)))); + return HeapObject::cast( + Tagged(V8HeapCompressionScheme::DecompressTagged( + cage_base, + Assembler::target_compressed_address_at(pc_, constant_pool_)))); } else { return HeapObject::cast( Object(Assembler::target_address_at(pc_, constant_pool_))); @@ -186,7 +187,7 @@ Handle RelocInfo::target_object_handle(Assembler* origin) { } } -void RelocInfo::set_target_object(HeapObject target, +void RelocInfo::set_target_object(Tagged target, ICacheFlushMode icache_flush_mode) { DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_)); if (IsCompressedEmbeddedObject(rmode_)) { diff --git a/deps/v8/src/codegen/riscv/assembler-riscv.h b/deps/v8/src/codegen/riscv/assembler-riscv.h index 65c317ad018126..ced4dd8aee8591 100644 --- a/deps/v8/src/codegen/riscv/assembler-riscv.h +++ b/deps/v8/src/codegen/riscv/assembler-riscv.h @@ -288,7 +288,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase, // This is for calls and branches within generated code. The serializer // has already deserialized the lui/ori instructions etc. inline static void deserialization_set_special_target_at(Address location, - Code code, + Tagged code, Address target); // Get the size of the special target encoded at 'instruction_payload'. diff --git a/deps/v8/src/execution/riscv/simulator-riscv.cc b/deps/v8/src/execution/riscv/simulator-riscv.cc index 1baf9eb6c66457..5b5411cb3e237c 100644 --- a/deps/v8/src/execution/riscv/simulator-riscv.cc +++ b/deps/v8/src/execution/riscv/simulator-riscv.cc @@ -1889,7 +1889,7 @@ void RiscvDebugger::Debug() { sreg_t value; StdoutStream os; if (GetValue(arg1, &value)) { - Object obj(value); + Tagged obj(value); os << arg1 << ": \n"; #ifdef DEBUG Print(obj, os); @@ -1938,7 +1938,7 @@ void RiscvDebugger::Debug() { PrintF(" 0x%012" PRIxPTR " : 0x%016" REGIx_FORMAT " %14" REGId_FORMAT " ", reinterpret_cast(cur), *cur, *cur); - Object obj(*cur); + Tagged obj(*cur); Heap* current_heap = sim_->isolate_->heap(); if (IsSmi(obj) || IsValidHeapObject(current_heap, HeapObject::cast(obj))) { @@ -4815,7 +4815,7 @@ bool Simulator::DecodeRvvVS() { Builtin Simulator::LookUp(Address pc) { for (Builtin builtin = Builtins::kFirst; builtin <= Builtins::kLast; ++builtin) { - if (builtins_.code(builtin).contains(isolate_, pc)) return builtin; + if (builtins_.code(builtin)->contains(isolate_, pc)) return builtin; } return Builtin::kNoBuiltinId; } @@ -4832,7 +4832,7 @@ void Simulator::DecodeRVIType() { if (builtin != Builtin::kNoBuiltinId) { auto code = builtins_.code(builtin); if ((rs1_reg() != ra || imm12() != 0)) { - if ((Address)get_pc() == code.instruction_start()) { + if ((Address)get_pc() == code->instruction_start()) { sreg_t arg0 = get_register(a0); sreg_t arg1 = get_register(a1); sreg_t arg2 = get_register(a2); diff --git a/deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc b/deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc index 3b57e613eefc15..f60f03e5eee6d0 100644 --- a/deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc +++ b/deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc @@ -1216,7 +1216,7 @@ static T* frame_entry_address(Address re_frame, int frame_offset) { int64_t RegExpMacroAssemblerRISCV::CheckStackGuardState(Address* return_address, Address raw_code, Address re_frame) { - InstructionStream re_code = InstructionStream::cast(Object(raw_code)); + Tagged re_code = InstructionStream::cast(Object(raw_code)); return NativeRegExpMacroAssembler::CheckStackGuardState( frame_entry(re_frame, kIsolateOffset), static_cast(frame_entry(re_frame, kStartIndexOffset)),