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| 1 | +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
| 2 | +<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
| 3 | + |
| 4 | + <!-- --> |
| 5 | + |
| 6 | + <!-- For tool use only. Do not edit. --> |
| 7 | + |
| 8 | + <!-- --> |
| 9 | + |
| 10 | + <!-- ProjectNavigator created generated project file. --> |
| 11 | + |
| 12 | + <!-- For use in tracking generated file and other information --> |
| 13 | + |
| 14 | + <!-- allowing preservation of process status. --> |
| 15 | + |
| 16 | + <!-- --> |
| 17 | + |
| 18 | + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> |
| 19 | + |
| 20 | + <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version> |
| 21 | + |
| 22 | + <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="GAMEBOY_TOP.xise"/> |
| 23 | + |
| 24 | + <files xmlns="http://www.xilinx.com/XMLSchema"> |
| 25 | + <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/> |
| 26 | + <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
| 27 | + <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/> |
| 28 | + <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
| 29 | + <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/> |
| 30 | + <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> |
| 31 | + <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> |
| 32 | + <file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/> |
| 33 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="lcd_top.bgn" xil_pn:subbranch="FPGAConfiguration"/> |
| 34 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="lcd_top.bit" xil_pn:subbranch="FPGAConfiguration"/> |
| 35 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="lcd_top.bld"/> |
| 36 | + <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="lcd_top.cmd_log"/> |
| 37 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="lcd_top.drc" xil_pn:subbranch="FPGAConfiguration"/> |
| 38 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="lcd_top.lso"/> |
| 39 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="lcd_top.ncd" xil_pn:subbranch="Par"/> |
| 40 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="lcd_top.ngc"/> |
| 41 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="lcd_top.ngd"/> |
| 42 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="lcd_top.ngr"/> |
| 43 | + <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="lcd_top.pad"/> |
| 44 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="lcd_top.par" xil_pn:subbranch="Par"/> |
| 45 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="lcd_top.pcf" xil_pn:subbranch="Map"/> |
| 46 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_top.prj"/> |
| 47 | + <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="lcd_top.ptwx"/> |
| 48 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_top.stx"/> |
| 49 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="lcd_top.syr"/> |
| 50 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="lcd_top.twr" xil_pn:subbranch="Par"/> |
| 51 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="lcd_top.twx" xil_pn:subbranch="Par"/> |
| 52 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="lcd_top.unroutes" xil_pn:subbranch="Par"/> |
| 53 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="lcd_top.ut" xil_pn:subbranch="FPGAConfiguration"/> |
| 54 | + <file xil_pn:fileType="FILE_XPI" xil_pn:name="lcd_top.xpi"/> |
| 55 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="lcd_top.xst"/> |
| 56 | + <file xil_pn:fileType="FILE_HTML" xil_pn:name="lcd_top_envsettings.html"/> |
| 57 | + <file xil_pn:fileType="FILE_NCD" xil_pn:name="lcd_top_guide.ncd" xil_pn:origination="imported"/> |
| 58 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="lcd_top_map.map" xil_pn:subbranch="Map"/> |
| 59 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="lcd_top_map.mrp" xil_pn:subbranch="Map"/> |
| 60 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="lcd_top_map.ncd" xil_pn:subbranch="Map"/> |
| 61 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="lcd_top_map.ngm" xil_pn:subbranch="Map"/> |
| 62 | + <file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_top_map.xrpt"/> |
| 63 | + <file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_top_ngdbuild.xrpt"/> |
| 64 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="lcd_top_pad.csv" xil_pn:subbranch="Par"/> |
| 65 | + <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="lcd_top_pad.txt" xil_pn:subbranch="Par"/> |
| 66 | + <file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_top_par.xrpt"/> |
| 67 | + <file xil_pn:fileType="FILE_HTML" xil_pn:name="lcd_top_summary.html"/> |
| 68 | + <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="lcd_top_summary.xml"/> |
| 69 | + <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="lcd_top_usage.xml"/> |
| 70 | + <file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_top_xst.xrpt"/> |
| 71 | + <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/> |
| 72 | + <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> |
| 73 | + <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> |
| 74 | + <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> |
| 75 | + <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> |
| 76 | + </files> |
| 77 | + |
| 78 | + <transforms xmlns="http://www.xilinx.com/XMLSchema"> |
| 79 | + <transform xil_pn:end_ts="1384970333" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1384970333"> |
| 80 | + <status xil_pn:value="SuccessfullyRun"/> |
| 81 | + </transform> |
| 82 | + <transform xil_pn:end_ts="1384970333" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="788783067979857354" xil_pn:start_ts="1384970333"> |
| 83 | + <status xil_pn:value="SuccessfullyRun"/> |
| 84 | + <status xil_pn:value="ReadyToRun"/> |
| 85 | + </transform> |
| 86 | + <transform xil_pn:end_ts="1384973059" xil_pn:in_ck="5744992072747982963" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8851858514933316079" xil_pn:start_ts="1384973059"> |
| 87 | + <status xil_pn:value="SuccessfullyRun"/> |
| 88 | + <status xil_pn:value="ReadyToRun"/> |
| 89 | + <outfile xil_pn:name="ipcore_dir/blockram8192.ngc"/> |
| 90 | + <outfile xil_pn:name="ipcore_dir/blockram8192.v"/> |
| 91 | + </transform> |
| 92 | + <transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy"> |
| 93 | + <status xil_pn:value="SuccessfullyRun"/> |
| 94 | + <status xil_pn:value="ReadyToRun"/> |
| 95 | + </transform> |
| 96 | + <transform xil_pn:end_ts="1384970333" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9059256021112377124" xil_pn:start_ts="1384970333"> |
| 97 | + <status xil_pn:value="SuccessfullyRun"/> |
| 98 | + <status xil_pn:value="ReadyToRun"/> |
| 99 | + </transform> |
| 100 | + <transform xil_pn:end_ts="1384970333" xil_pn:in_ck="-8454138244336260053" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-8458126479482839362" xil_pn:start_ts="1384970333"> |
| 101 | + <status xil_pn:value="SuccessfullyRun"/> |
| 102 | + <status xil_pn:value="ReadyToRun"/> |
| 103 | + </transform> |
| 104 | + <transform xil_pn:end_ts="1384970333" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6908640399856491749" xil_pn:start_ts="1384970333"> |
| 105 | + <status xil_pn:value="SuccessfullyRun"/> |
| 106 | + <status xil_pn:value="ReadyToRun"/> |
| 107 | + </transform> |
| 108 | + <transform xil_pn:end_ts="1384973903" xil_pn:in_ck="-3296564387604906944" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="5963379695169079831" xil_pn:start_ts="1384973804"> |
| 109 | + <status xil_pn:value="SuccessfullyRun"/> |
| 110 | + <status xil_pn:value="WarningsGenerated"/> |
| 111 | + <status xil_pn:value="ReadyToRun"/> |
| 112 | + <status xil_pn:value="OutOfDateForOutputs"/> |
| 113 | + <status xil_pn:value="OutputChanged"/> |
| 114 | + <outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
| 115 | + <outfile xil_pn:name="lcd_top.lso"/> |
| 116 | + <outfile xil_pn:name="lcd_top.ngc"/> |
| 117 | + <outfile xil_pn:name="lcd_top.ngr"/> |
| 118 | + <outfile xil_pn:name="lcd_top.prj"/> |
| 119 | + <outfile xil_pn:name="lcd_top.stx"/> |
| 120 | + <outfile xil_pn:name="lcd_top.syr"/> |
| 121 | + <outfile xil_pn:name="lcd_top.xst"/> |
| 122 | + <outfile xil_pn:name="lcd_top_xst.xrpt"/> |
| 123 | + <outfile xil_pn:name="webtalk_pn.xml"/> |
| 124 | + <outfile xil_pn:name="xst"/> |
| 125 | + </transform> |
| 126 | + <transform xil_pn:end_ts="1384973917" xil_pn:in_ck="4416554822933299080" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981273420214151" xil_pn:start_ts="1384973917"> |
| 127 | + <status xil_pn:value="SuccessfullyRun"/> |
| 128 | + <status xil_pn:value="ReadyToRun"/> |
| 129 | + </transform> |
| 130 | + <transform xil_pn:end_ts="1384973923" xil_pn:in_ck="-1934397648636733049" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1384973917"> |
| 131 | + <status xil_pn:value="SuccessfullyRun"/> |
| 132 | + <status xil_pn:value="WarningsGenerated"/> |
| 133 | + <status xil_pn:value="ReadyToRun"/> |
| 134 | + <outfile xil_pn:name="_ngo"/> |
| 135 | + <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
| 136 | + <outfile xil_pn:name="lcd_top.bld"/> |
| 137 | + <outfile xil_pn:name="lcd_top.ngd"/> |
| 138 | + <outfile xil_pn:name="lcd_top_ngdbuild.xrpt"/> |
| 139 | + </transform> |
| 140 | + <transform xil_pn:end_ts="1384973963" xil_pn:in_ck="4243404421696925268" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="6733564432430981316" xil_pn:start_ts="1384973923"> |
| 141 | + <status xil_pn:value="SuccessfullyRun"/> |
| 142 | + <status xil_pn:value="ReadyToRun"/> |
| 143 | + <outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
| 144 | + <outfile xil_pn:name="lcd_top.pcf"/> |
| 145 | + <outfile xil_pn:name="lcd_top_map.map"/> |
| 146 | + <outfile xil_pn:name="lcd_top_map.mrp"/> |
| 147 | + <outfile xil_pn:name="lcd_top_map.ncd"/> |
| 148 | + <outfile xil_pn:name="lcd_top_map.ngm"/> |
| 149 | + <outfile xil_pn:name="lcd_top_map.xrpt"/> |
| 150 | + <outfile xil_pn:name="lcd_top_summary.xml"/> |
| 151 | + <outfile xil_pn:name="lcd_top_usage.xml"/> |
| 152 | + </transform> |
| 153 | + <transform xil_pn:end_ts="1384974005" xil_pn:in_ck="-3155098934414866579" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4097515898943074650" xil_pn:start_ts="1384973963"> |
| 154 | + <status xil_pn:value="SuccessfullyRun"/> |
| 155 | + <status xil_pn:value="WarningsGenerated"/> |
| 156 | + <status xil_pn:value="ReadyToRun"/> |
| 157 | + <outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
| 158 | + <outfile xil_pn:name="lcd_top.ncd"/> |
| 159 | + <outfile xil_pn:name="lcd_top.pad"/> |
| 160 | + <outfile xil_pn:name="lcd_top.par"/> |
| 161 | + <outfile xil_pn:name="lcd_top.ptwx"/> |
| 162 | + <outfile xil_pn:name="lcd_top.unroutes"/> |
| 163 | + <outfile xil_pn:name="lcd_top.xpi"/> |
| 164 | + <outfile xil_pn:name="lcd_top_pad.csv"/> |
| 165 | + <outfile xil_pn:name="lcd_top_pad.txt"/> |
| 166 | + <outfile xil_pn:name="lcd_top_par.xrpt"/> |
| 167 | + </transform> |
| 168 | + <transform xil_pn:end_ts="1384974035" xil_pn:in_ck="170150111267173192" xil_pn:name="TRANEXT_bitFile_virtex5" xil_pn:prop_ck="-4008143788065839743" xil_pn:start_ts="1384974005"> |
| 169 | + <status xil_pn:value="SuccessfullyRun"/> |
| 170 | + <status xil_pn:value="ReadyToRun"/> |
| 171 | + <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
| 172 | + <outfile xil_pn:name="lcd_top.bgn"/> |
| 173 | + <outfile xil_pn:name="lcd_top.bit"/> |
| 174 | + <outfile xil_pn:name="lcd_top.drc"/> |
| 175 | + <outfile xil_pn:name="lcd_top.ut"/> |
| 176 | + <outfile xil_pn:name="usage_statistics_webtalk.html"/> |
| 177 | + <outfile xil_pn:name="webtalk.log"/> |
| 178 | + <outfile xil_pn:name="webtalk_pn.xml"/> |
| 179 | + </transform> |
| 180 | + <transform xil_pn:end_ts="1384974005" xil_pn:in_ck="4243404421696925136" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1384973996"> |
| 181 | + <status xil_pn:value="SuccessfullyRun"/> |
| 182 | + <status xil_pn:value="ReadyToRun"/> |
| 183 | + <outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
| 184 | + <outfile xil_pn:name="lcd_top.twr"/> |
| 185 | + <outfile xil_pn:name="lcd_top.twx"/> |
| 186 | + </transform> |
| 187 | + </transforms> |
| 188 | + |
| 189 | +</generated_project> |
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