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root
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added link cable module
1 parent 1e093a4 commit 53d91e4

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134 files changed

+6008
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lines changed

Diff for: ‎GAMEBOY_TOP/GAMEBOY_TOP.gise

+9-23
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@
9090
<status xil_pn:value="SuccessfullyRun"/>
9191
<status xil_pn:value="ReadyToRun"/>
9292
</transform>
93-
<transform xil_pn:end_ts="1386129407" xil_pn:in_ck="-1195210778552110790" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8851858514933316079" xil_pn:start_ts="1386129407">
93+
<transform xil_pn:end_ts="1386176383" xil_pn:in_ck="-1195210778552110790" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8851858514933316079" xil_pn:start_ts="1386176383">
9494
<status xil_pn:value="SuccessfullyRun"/>
9595
<status xil_pn:value="ReadyToRun"/>
9696
<outfile xil_pn:name="../GPU/ipcore_dir/OAM.ngc"/>
@@ -120,13 +120,11 @@
120120
<status xil_pn:value="SuccessfullyRun"/>
121121
<status xil_pn:value="ReadyToRun"/>
122122
</transform>
123-
<transform xil_pn:end_ts="1386138633" xil_pn:in_ck="-5564990055820481360" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-8520347394040804913" xil_pn:start_ts="1386138486">
123+
<transform xil_pn:end_ts="1386320981" xil_pn:in_ck="6611238507098692611" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-8520347394040804913" xil_pn:start_ts="1386320824">
124124
<status xil_pn:value="SuccessfullyRun"/>
125125
<status xil_pn:value="WarningsGenerated"/>
126126
<status xil_pn:value="ReadyToRun"/>
127-
<status xil_pn:value="OutOfDateForInputs"/>
128127
<status xil_pn:value="OutOfDateForOutputs"/>
129-
<status xil_pn:value="InputChanged"/>
130128
<status xil_pn:value="OutputChanged"/>
131129
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
132130
<outfile xil_pn:name="lcd_top.lso"/>
@@ -144,23 +142,19 @@
144142
<status xil_pn:value="SuccessfullyRun"/>
145143
<status xil_pn:value="ReadyToRun"/>
146144
</transform>
147-
<transform xil_pn:end_ts="1386138644" xil_pn:in_ck="-9062899737394110733" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1386138633">
145+
<transform xil_pn:end_ts="1386320992" xil_pn:in_ck="-9062899737394110733" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1386320981">
148146
<status xil_pn:value="SuccessfullyRun"/>
149147
<status xil_pn:value="WarningsGenerated"/>
150148
<status xil_pn:value="ReadyToRun"/>
151-
<status xil_pn:value="OutOfDateForPredecessor"/>
152149
<outfile xil_pn:name="_ngo"/>
153150
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
154151
<outfile xil_pn:name="lcd_top.bld"/>
155152
<outfile xil_pn:name="lcd_top.ngd"/>
156153
<outfile xil_pn:name="lcd_top_ngdbuild.xrpt"/>
157154
</transform>
158-
<transform xil_pn:end_ts="1386138696" xil_pn:in_ck="4243404421696925268" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="6733564432430981316" xil_pn:start_ts="1386138644">
155+
<transform xil_pn:end_ts="1386321044" xil_pn:in_ck="4243404421696925268" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="6733564432430981316" xil_pn:start_ts="1386320992">
159156
<status xil_pn:value="SuccessfullyRun"/>
160157
<status xil_pn:value="ReadyToRun"/>
161-
<status xil_pn:value="OutOfDateForPredecessor"/>
162-
<status xil_pn:value="OutOfDateForOutputs"/>
163-
<status xil_pn:value="OutputChanged"/>
164158
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
165159
<outfile xil_pn:name="lcd_top.pcf"/>
166160
<outfile xil_pn:name="lcd_top_map.map"/>
@@ -171,11 +165,10 @@
171165
<outfile xil_pn:name="lcd_top_summary.xml"/>
172166
<outfile xil_pn:name="lcd_top_usage.xml"/>
173167
</transform>
174-
<transform xil_pn:end_ts="1386138747" xil_pn:in_ck="-3155098934414866579" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4097515898943074650" xil_pn:start_ts="1386138696">
168+
<transform xil_pn:end_ts="1386321097" xil_pn:in_ck="-3155098934414866579" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4097515898943074650" xil_pn:start_ts="1386321044">
175169
<status xil_pn:value="SuccessfullyRun"/>
176170
<status xil_pn:value="WarningsGenerated"/>
177171
<status xil_pn:value="ReadyToRun"/>
178-
<status xil_pn:value="OutOfDateForPredecessor"/>
179172
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
180173
<outfile xil_pn:name="lcd_top.ncd"/>
181174
<outfile xil_pn:name="lcd_top.pad"/>
@@ -187,11 +180,10 @@
187180
<outfile xil_pn:name="lcd_top_pad.txt"/>
188181
<outfile xil_pn:name="lcd_top_par.xrpt"/>
189182
</transform>
190-
<transform xil_pn:end_ts="1386138815" xil_pn:in_ck="170150111267173192" xil_pn:name="TRANEXT_bitFile_virtex5" xil_pn:prop_ck="1555517831305455702" xil_pn:start_ts="1386138747">
183+
<transform xil_pn:end_ts="1386321171" xil_pn:in_ck="170150111267173192" xil_pn:name="TRANEXT_bitFile_virtex5" xil_pn:prop_ck="1555517831305455702" xil_pn:start_ts="1386321097">
191184
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192185
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193186
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194-
<status xil_pn:value="OutOfDateForPredecessor"/>
195187
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
196188
<outfile xil_pn:name="lcd_top.bgn"/>
197189
<outfile xil_pn:name="lcd_top.bit"/>
@@ -205,28 +197,22 @@
205197
<status xil_pn:value="SuccessfullyRun"/>
206198
<status xil_pn:value="ReadyToRun"/>
207199
<status xil_pn:value="OutOfDateForInputs"/>
208-
<status xil_pn:value="OutOfDateForPredecessor"/>
209200
<status xil_pn:value="OutOfDateForOutputs"/>
210201
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211202
<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="InputRemoved"/>
213204
<status xil_pn:value="OutputChanged"/>
214205
<status xil_pn:value="OutputRemoved"/>
215206
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216-
<transform xil_pn:end_ts="1386026466" xil_pn:in_ck="170150111267160338" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1386026466">
217-
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207+
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208+
<status xil_pn:value="SuccessfullyRun"/>
218209
<status xil_pn:value="ReadyToRun"/>
219210
<status xil_pn:value="OutOfDateForInputs"/>
220-
<status xil_pn:value="OutOfDateForPredecessor"/>
221-
<status xil_pn:value="OutOfDateForced"/>
222-
<status xil_pn:value="InputAdded"/>
223211
<status xil_pn:value="InputChanged"/>
224-
<status xil_pn:value="InputRemoved"/>
225212
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226-
<transform xil_pn:end_ts="1386138747" xil_pn:in_ck="4243404421696925136" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1386138737">
213+
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227214
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228215
<status xil_pn:value="ReadyToRun"/>
229-
<status xil_pn:value="OutOfDateForPredecessor"/>
230216
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
231217
<outfile xil_pn:name="lcd_top.twr"/>
232218
<outfile xil_pn:name="lcd_top.twx"/>

Diff for: ‎GAMEBOY_TOP/GAMEBOY_TOP.xise

+38-34
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,11 @@
2929
</file>
3030
<file xil_pn:name="../GPU/ipcore_dir/OAM.xco" xil_pn:type="FILE_COREGEN">
3131
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
32-
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
32+
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
3333
</file>
3434
<file xil_pn:name="../GPU/ipcore_dir/VRAM.xco" xil_pn:type="FILE_COREGEN">
3535
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
36-
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
36+
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
3737
</file>
3838
<file xil_pn:name="../cpu/cpusynth/lcd_top_pad.txt" xil_pn:type="FILE_USERDOC"/>
3939
<file xil_pn:name="../cpu/src/cpu_auto_testbench_breakpoints.v" xil_pn:type="FILE_VERILOG">
@@ -74,62 +74,62 @@
7474
</file>
7575
<file xil_pn:name="ipcore_dir/blockram8192.xco" xil_pn:type="FILE_COREGEN">
7676
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
77-
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
77+
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7878
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7979
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8080
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81-
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
81+
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8282
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8383
<file xil_pn:name="../cpu/src/breakpoints.v" xil_pn:type="FILE_VERILOG">
8484
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
85-
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85+
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8686
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8787
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8888
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89-
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89+
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9090
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9191
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9292
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93-
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93+
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9494
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9595
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9696
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97-
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97+
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9898
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9999
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100100
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101-
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101+
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102102
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103103
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104104
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105-
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105+
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106106
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107107
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108108
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109-
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109+
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110110
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111111
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112112
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113-
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113+
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114114
</file>
115115
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116116
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
117-
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
117+
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118118
</file>
119119
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120120
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121-
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121+
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122122
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123123
<file xil_pn:name="../cpu/cpusynth/lcd_control.v" xil_pn:type="FILE_VERILOG">
124124
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
125-
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
125+
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
126126
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127127
<file xil_pn:name="../cpu/cpusynth/lcd_top.ucf" xil_pn:type="FILE_UCF">
128128
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
129129
</file>
130130
<file xil_pn:name="../cpu/cpusynth/lcd_top.v" xil_pn:type="FILE_VERILOG">
131131
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
132-
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
132+
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133133
</file>
134134
<file xil_pn:name="../my_clock_divider.v" xil_pn:type="FILE_VERILOG">
135135
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
@@ -160,7 +160,7 @@
160160
</file>
161161
<file xil_pn:name="../fpgaboy_files/clk31p5_dcm.v" xil_pn:type="FILE_VERILOG">
162162
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163-
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163+
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164164
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165165
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
@@ -172,46 +172,46 @@
172172
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173173
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174174
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175-
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175+
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176176
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177177
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178178
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179-
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179+
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180180
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181181
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182182
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183183
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184184
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185185
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186186
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187-
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187+
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188188
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189189
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190190
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191-
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191+
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192192
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193193
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194194
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195-
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195+
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196196
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197197
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201201
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202-
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202+
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203203
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204204
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205205
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206+
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207207
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208208
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209209
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210210
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211211
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212212
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213213
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214-
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214+
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215215
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216216
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217217
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@@ -223,48 +223,52 @@
223223
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224224
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225225
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227227
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228228
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229229
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230+
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231231
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232232
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233233
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235235
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236236
<file xil_pn:name="../fpgaboy_files/video_module.v" xil_pn:type="FILE_VERILOG">
237237
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
238-
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
238+
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
239239
</file>
240240
<file xil_pn:name="../fpgaboy_files/video_ram.v" xil_pn:type="FILE_VERILOG">
241241
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
242242
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
243243
</file>
244244
<file xil_pn:name="../fpgaboy_files/x2_dcm.v" xil_pn:type="FILE_VERILOG">
245245
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
246-
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
246+
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
247247
</file>
248248
<file xil_pn:name="../cpu/cpusynth/mux.v" xil_pn:type="FILE_VERILOG">
249249
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
250-
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
250+
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
251251
</file>
252252
<file xil_pn:name="../cartridge_interface.v" xil_pn:type="FILE_VERILOG">
253253
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
254-
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
254+
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
255255
</file>
256256
<file xil_pn:name="ipcore_dir/chipscope_icon.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="138"/>
258-
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
258+
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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</file>
260260
<file xil_pn:name="ipcore_dir/chipscope_ila.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
262-
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
262+
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
263263
</file>
264264
<file xil_pn:name="../NES_controller.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
267267
</file>
268+
<file xil_pn:name="../link_cable.v" xil_pn:type="FILE_VERILOG">
269+
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
270+
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
271+
</file>
268272
<file xil_pn:name="../GPU/ipcore_dir/OAM.xise" xil_pn:type="FILE_COREGENISE">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
270274
</file>

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