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jdcarlosjdcarlos
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added chipscope, fixed rst instruction
1 parent d4fccd0 commit 4ddfdc2

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65 files changed

+12084
-829
lines changed

Diff for: ‎GAMEBOY_TOP/GAMEBOY_TOP.gise

+36-45
Original file line numberDiff line numberDiff line change
@@ -22,20 +22,19 @@
2222
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="GAMEBOY_TOP.xise"/>
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2424
<files xmlns="http://www.xilinx.com/XMLSchema">
25-
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../GPU/ipcore_dir/OAM.ngc" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../GPU/ipcore_dir/OAM.sym" xil_pn:origination="imported"/>
27-
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="../GPU/ipcore_dir/OAM.v" xil_pn:origination="imported"/>
28-
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../GPU/ipcore_dir/VRAM.ngc" xil_pn:origination="imported"/>
2926
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../GPU/ipcore_dir/VRAM.sym" xil_pn:origination="imported"/>
30-
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="../GPU/ipcore_dir/VRAM.v" xil_pn:origination="imported"/>
3127
<file xil_pn:fileType="FILE_LOG" xil_pn:name="../GPU/ipcore_dir/coregen.log"/>
28+
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
29+
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
37+
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="ipcore_dir/chipscope_ila_readme.txt"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="lcd_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="lcd_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
@@ -83,49 +82,56 @@
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
86-
<transform xil_pn:end_ts="1384970333" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1384970333">
85+
<transform xil_pn:end_ts="1385146303" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1385146303">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
90-
<transform xil_pn:end_ts="1384970333" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="788783067979857354" xil_pn:start_ts="1384970333">
89+
<transform xil_pn:end_ts="1385146303" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="788783067979857354" xil_pn:start_ts="1385146303">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
94-
<transform xil_pn:end_ts="1385087974" xil_pn:in_ck="5744992072747982963" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8851858514933316079" xil_pn:start_ts="1385087974">
93+
<transform xil_pn:end_ts="1385169336" xil_pn:in_ck="-1195210778552110790" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8851858514933316079" xil_pn:start_ts="1385169335">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
96+
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97+
<status xil_pn:value="OutOfDateForOutputs"/>
98+
<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="../GPU/ipcore_dir/OAM.ngc"/>
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<outfile xil_pn:name="../GPU/ipcore_dir/OAM.v"/>
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<outfile xil_pn:name="../GPU/ipcore_dir/VRAM.ngc"/>
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<outfile xil_pn:name="../GPU/ipcore_dir/VRAM.v"/>
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<outfile xil_pn:name="ipcore_dir/blockram8192.ngc"/>
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<outfile xil_pn:name="ipcore_dir/blockram8192.v"/>
106+
<outfile xil_pn:name="ipcore_dir/chipscope_icon.ngc"/>
107+
<outfile xil_pn:name="ipcore_dir/chipscope_icon.v"/>
108+
<outfile xil_pn:name="ipcore_dir/chipscope_ila.ngc"/>
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<outfile xil_pn:name="ipcore_dir/chipscope_ila.v"/>
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</transform>
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<transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1384970333" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9059256021112377124" xil_pn:start_ts="1384970333">
115+
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
112-
<transform xil_pn:end_ts="1384970333" xil_pn:in_ck="-8454138244336260053" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-8458126479482839362" xil_pn:start_ts="1384970333">
119+
<transform xil_pn:end_ts="1385146304" xil_pn:in_ck="1345748343033360544" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-8458126479482839362" xil_pn:start_ts="1385146304">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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</transform>
116-
<transform xil_pn:end_ts="1384970333" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6908640399856491749" xil_pn:start_ts="1384970333">
124+
<transform xil_pn:end_ts="1385146304" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6908640399856491749" xil_pn:start_ts="1385146304">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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</transform>
120-
<<<<<<< HEAD
121-
<transform xil_pn:end_ts="1385091930" xil_pn:in_ck="-8039839614482936423" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-8520347394040804913" xil_pn:start_ts="1385091821">
122-
=======
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<transform xil_pn:end_ts="1385088501" xil_pn:in_ck="-8039839614482936423" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-8520347394040804913" xil_pn:start_ts="1385088393">
124-
>>>>>>> eb8b20b5bd28ca2f4ada8e247f72a57705564de0
129+
<transform xil_pn:end_ts="1385179461" xil_pn:in_ck="-7678780738846064328" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-8520347394040804913" xil_pn:start_ts="1385179322">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
@@ -141,30 +147,25 @@
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<outfile xil_pn:name="webtalk_pn.xml"/>
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<outfile xil_pn:name="xst"/>
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</transform>
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<transform xil_pn:end_ts="1384983671" xil_pn:in_ck="4416554822933299080" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981273420214151" xil_pn:start_ts="1384983671">
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<transform xil_pn:end_ts="1385146414" xil_pn:in_ck="4416554822933299080" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981273420214151" xil_pn:start_ts="1385146414">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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</transform>
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<<<<<<< HEAD
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<transform xil_pn:end_ts="1385091939" xil_pn:in_ck="4166032577501441264" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1385091930">
150-
=======
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<transform xil_pn:end_ts="1385088508" xil_pn:in_ck="4166032577501441264" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1385088501">
152-
>>>>>>> eb8b20b5bd28ca2f4ada8e247f72a57705564de0
155+
<transform xil_pn:end_ts="1385179473" xil_pn:in_ck="-9062899737394110733" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1385179461">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="InputChanged"/>
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<outfile xil_pn:name="_ngo"/>
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<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<outfile xil_pn:name="lcd_top.bld"/>
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<outfile xil_pn:name="lcd_top.ngd"/>
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<outfile xil_pn:name="lcd_top_ngdbuild.xrpt"/>
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</transform>
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<<<<<<< HEAD
164-
<transform xil_pn:end_ts="1385091986" xil_pn:in_ck="4243404421696925268" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="6733564432430981316" xil_pn:start_ts="1385091939">
165-
=======
166-
<transform xil_pn:end_ts="1385088552" xil_pn:in_ck="4243404421696925268" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="6733564432430981316" xil_pn:start_ts="1385088508">
167-
>>>>>>> eb8b20b5bd28ca2f4ada8e247f72a57705564de0
168+
<transform xil_pn:end_ts="1385179527" xil_pn:in_ck="4243404421696925268" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="6733564432430981316" xil_pn:start_ts="1385179473">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
@@ -181,11 +182,7 @@
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<outfile xil_pn:name="lcd_top_summary.xml"/>
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<outfile xil_pn:name="lcd_top_usage.xml"/>
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</transform>
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<<<<<<< HEAD
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<transform xil_pn:end_ts="1385092039" xil_pn:in_ck="-3155098934414866579" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4097515898943074650" xil_pn:start_ts="1385091986">
186-
=======
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<transform xil_pn:end_ts="1385088598" xil_pn:in_ck="-3155098934414866579" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4097515898943074650" xil_pn:start_ts="1385088552">
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>>>>>>> eb8b20b5bd28ca2f4ada8e247f72a57705564de0
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<transform xil_pn:end_ts="1385179584" xil_pn:in_ck="-3155098934414866579" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4097515898943074650" xil_pn:start_ts="1385179527">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
@@ -201,12 +198,9 @@
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<outfile xil_pn:name="lcd_top_pad.txt"/>
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<outfile xil_pn:name="lcd_top_par.xrpt"/>
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</transform>
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<<<<<<< HEAD
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<transform xil_pn:end_ts="1385092078" xil_pn:in_ck="170150111267173192" xil_pn:name="TRANEXT_bitFile_virtex5" xil_pn:prop_ck="1555517831305455702" xil_pn:start_ts="1385092039">
206-
=======
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<transform xil_pn:end_ts="1385088629" xil_pn:in_ck="170150111267173192" xil_pn:name="TRANEXT_bitFile_virtex5" xil_pn:prop_ck="1555517831305455702" xil_pn:start_ts="1385088598">
208-
>>>>>>> eb8b20b5bd28ca2f4ada8e247f72a57705564de0
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<transform xil_pn:end_ts="1385179652" xil_pn:in_ck="170150111267173192" xil_pn:name="TRANEXT_bitFile_virtex5" xil_pn:prop_ck="1555517831305455702" xil_pn:start_ts="1385179584">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -218,26 +212,23 @@
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<outfile xil_pn:name="webtalk.log"/>
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<outfile xil_pn:name="webtalk_pn.xml"/>
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</transform>
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<transform xil_pn:end_ts="1384979879" xil_pn:in_ck="170150111267160338" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="7814804799388247210" xil_pn:start_ts="1384979877">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<<<<<<< HEAD
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="_impact.cmd"/>
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<outfile xil_pn:name="_impact.log"/>
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</transform>
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<transform xil_pn:end_ts="1385092039" xil_pn:in_ck="4243404421696925136" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1385092027">
233-
=======
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<transform xil_pn:end_ts="1385179777" xil_pn:in_ck="170150111267160338" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1385179776">
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<status xil_pn:value="OutOfDateForPredecessor"/>
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240-
>>>>>>> eb8b20b5bd28ca2f4ada8e247f72a57705564de0
231+
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<status xil_pn:value="ReadyToRun"/>
243234
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