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jdcarlosjdcarlos
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got past the bootstrap (sort of)
1 parent b9277b2 commit 2fde46f

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+3385
-2849
lines changed

Diff for: ‎GAMEBOY_TOP/GAMEBOY_TOP.gise

+25-14
Original file line numberDiff line numberDiff line change
@@ -106,40 +106,48 @@
106106
<status xil_pn:value="SuccessfullyRun"/>
107107
<status xil_pn:value="ReadyToRun"/>
108108
</transform>
109-
<transform xil_pn:end_ts="1384978413" xil_pn:in_ck="5552731434052028797" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-8520347394040804913" xil_pn:start_ts="1384978406">
110-
<status xil_pn:value="FailedRun"/>
109+
<transform xil_pn:end_ts="1384987449" xil_pn:in_ck="-8039839614482936423" xil_pn:name="TRANEXT_xstsynthesize_virtex5" xil_pn:prop_ck="-8520347394040804913" xil_pn:start_ts="1384987346">
110+
<status xil_pn:value="SuccessfullyRun"/>
111+
<status xil_pn:value="WarningsGenerated"/>
111112
<status xil_pn:value="ReadyToRun"/>
113+
<status xil_pn:value="OutOfDateForInputs"/>
114+
<status xil_pn:value="OutOfDateForOutputs"/>
115+
<status xil_pn:value="InputChanged"/>
116+
<status xil_pn:value="OutputChanged"/>
112117
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
113118
<outfile xil_pn:name="lcd_top.lso"/>
114119
<outfile xil_pn:name="lcd_top.ngc"/>
115120
<outfile xil_pn:name="lcd_top.ngr"/>
116121
<outfile xil_pn:name="lcd_top.prj"/>
122+
<outfile xil_pn:name="lcd_top.stx"/>
117123
<outfile xil_pn:name="lcd_top.syr"/>
118124
<outfile xil_pn:name="lcd_top.xst"/>
119125
<outfile xil_pn:name="lcd_top_xst.xrpt"/>
120126
<outfile xil_pn:name="webtalk_pn.xml"/>
121127
<outfile xil_pn:name="xst"/>
122128
</transform>
123-
<transform xil_pn:end_ts="1384973917" xil_pn:in_ck="4416554822933299080" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981273420214151" xil_pn:start_ts="1384973917">
129+
<transform xil_pn:end_ts="1384983671" xil_pn:in_ck="4416554822933299080" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981273420214151" xil_pn:start_ts="1384983671">
124130
<status xil_pn:value="SuccessfullyRun"/>
125131
<status xil_pn:value="ReadyToRun"/>
126132
</transform>
127-
<transform xil_pn:end_ts="1384973923" xil_pn:in_ck="-1934397648636733049" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1384973917">
133+
<transform xil_pn:end_ts="1384987458" xil_pn:in_ck="4166032577501441264" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2027775693196902650" xil_pn:start_ts="1384987449">
128134
<status xil_pn:value="SuccessfullyRun"/>
129135
<status xil_pn:value="WarningsGenerated"/>
130136
<status xil_pn:value="ReadyToRun"/>
131-
<status xil_pn:value="OutOfDateForInputs"/>
137+
<status xil_pn:value="OutOfDateForPredecessor"/>
132138
<outfile xil_pn:name="_ngo"/>
133139
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
134140
<outfile xil_pn:name="lcd_top.bld"/>
135141
<outfile xil_pn:name="lcd_top.ngd"/>
136142
<outfile xil_pn:name="lcd_top_ngdbuild.xrpt"/>
137143
</transform>
138-
<transform xil_pn:end_ts="1384973963" xil_pn:in_ck="4243404421696925268" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="6733564432430981316" xil_pn:start_ts="1384973923">
144+
<transform xil_pn:end_ts="1384987502" xil_pn:in_ck="4243404421696925268" xil_pn:name="TRANEXT_map_virtex5" xil_pn:prop_ck="6733564432430981316" xil_pn:start_ts="1384987458">
139145
<status xil_pn:value="SuccessfullyRun"/>
146+
<status xil_pn:value="WarningsGenerated"/>
140147
<status xil_pn:value="ReadyToRun"/>
141-
<status xil_pn:value="OutOfDateForInputs"/>
142148
<status xil_pn:value="OutOfDateForPredecessor"/>
149+
<status xil_pn:value="OutOfDateForOutputs"/>
150+
<status xil_pn:value="OutputChanged"/>
143151
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
144152
<outfile xil_pn:name="lcd_top.pcf"/>
145153
<outfile xil_pn:name="lcd_top_map.map"/>
@@ -150,11 +158,10 @@
150158
<outfile xil_pn:name="lcd_top_summary.xml"/>
151159
<outfile xil_pn:name="lcd_top_usage.xml"/>
152160
</transform>
153-
<transform xil_pn:end_ts="1384974005" xil_pn:in_ck="-3155098934414866579" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4097515898943074650" xil_pn:start_ts="1384973963">
161+
<transform xil_pn:end_ts="1384987553" xil_pn:in_ck="-3155098934414866579" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4097515898943074650" xil_pn:start_ts="1384987502">
154162
<status xil_pn:value="SuccessfullyRun"/>
155163
<status xil_pn:value="WarningsGenerated"/>
156164
<status xil_pn:value="ReadyToRun"/>
157-
<status xil_pn:value="OutOfDateForInputs"/>
158165
<status xil_pn:value="OutOfDateForPredecessor"/>
159166
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
160167
<outfile xil_pn:name="lcd_top.ncd"/>
@@ -167,13 +174,10 @@
167174
<outfile xil_pn:name="lcd_top_pad.txt"/>
168175
<outfile xil_pn:name="lcd_top_par.xrpt"/>
169176
</transform>
170-
<transform xil_pn:end_ts="1384974035" xil_pn:in_ck="170150111267173192" xil_pn:name="TRANEXT_bitFile_virtex5" xil_pn:prop_ck="-4008143788065839743" xil_pn:start_ts="1384974005">
177+
<transform xil_pn:end_ts="1384987594" xil_pn:in_ck="170150111267173192" xil_pn:name="TRANEXT_bitFile_virtex5" xil_pn:prop_ck="1555517831305455702" xil_pn:start_ts="1384987553">
171178
<status xil_pn:value="SuccessfullyRun"/>
172179
<status xil_pn:value="ReadyToRun"/>
173-
<status xil_pn:value="OutOfDateForProperties"/>
174180
<status xil_pn:value="OutOfDateForPredecessor"/>
175-
<status xil_pn:value="OutOfDateForOutputs"/>
176-
<status xil_pn:value="OutputChanged"/>
177181
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
178182
<outfile xil_pn:name="lcd_top.bgn"/>
179183
<outfile xil_pn:name="lcd_top.bit"/>
@@ -183,7 +187,14 @@
183187
<outfile xil_pn:name="webtalk.log"/>
184188
<outfile xil_pn:name="webtalk_pn.xml"/>
185189
</transform>
186-
<transform xil_pn:end_ts="1384974005" xil_pn:in_ck="4243404421696925136" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1384973996">
190+
<transform xil_pn:end_ts="1384979879" xil_pn:in_ck="170150111267160338" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="7814804799388247210" xil_pn:start_ts="1384979877">
191+
<status xil_pn:value="SuccessfullyRun"/>
192+
<status xil_pn:value="ReadyToRun"/>
193+
<status xil_pn:value="OutOfDateForInputs"/>
194+
<status xil_pn:value="OutOfDateForPredecessor"/>
195+
<status xil_pn:value="InputChanged"/>
196+
</transform>
197+
<transform xil_pn:end_ts="1384987553" xil_pn:in_ck="4243404421696925136" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1384987541">
187198
<status xil_pn:value="SuccessfullyRun"/>
188199
<status xil_pn:value="ReadyToRun"/>
189200
<status xil_pn:value="OutOfDateForPredecessor"/>

Diff for: ‎GAMEBOY_TOP/GAMEBOY_TOP.xise

+50-31
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,11 @@
2929
</file>
3030
<file xil_pn:name="../GPU/ipcore_dir/OAM.xco" xil_pn:type="FILE_COREGEN">
3131
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
32-
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
32+
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
3333
</file>
3434
<file xil_pn:name="../GPU/ipcore_dir/VRAM.xco" xil_pn:type="FILE_COREGEN">
3535
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
36-
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
36+
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
3737
</file>
3838
<file xil_pn:name="../cpu/cpusynth/lcd_top_pad.txt" xil_pn:type="FILE_USERDOC"/>
3939
<file xil_pn:name="../cpu/src/cpu_auto_testbench_breakpoints.v" xil_pn:type="FILE_VERILOG">
@@ -74,62 +74,62 @@
7474
</file>
7575
<file xil_pn:name="ipcore_dir/blockram8192.xco" xil_pn:type="FILE_COREGEN">
7676
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
77-
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
77+
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
7878
</file>
7979
<file xil_pn:name="../cpu/src/alu.v" xil_pn:type="FILE_VERILOG">
8080
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
81-
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
81+
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
8282
</file>
8383
<file xil_pn:name="../cpu/src/breakpoints.v" xil_pn:type="FILE_VERILOG">
8484
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
85-
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
85+
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
8686
</file>
8787
<file xil_pn:name="../cpu/src/cpu.v" xil_pn:type="FILE_VERILOG">
8888
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
89-
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
89+
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
9090
</file>
9191
<file xil_pn:name="../cpu/src/decode.v" xil_pn:type="FILE_VERILOG">
9292
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
93-
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
93+
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
9494
</file>
9595
<file xil_pn:name="../cpu/src/dma.v" xil_pn:type="FILE_VERILOG">
9696
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
97-
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
97+
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
9898
</file>
9999
<file xil_pn:name="../cpu/src/mem_synth.v" xil_pn:type="FILE_VERILOG">
100100
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
101-
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
101+
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
102102
</file>
103103
<file xil_pn:name="../cpu/src/regfile.v" xil_pn:type="FILE_VERILOG">
104104
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="108"/>
105-
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
105+
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
106106
</file>
107107
<file xil_pn:name="../cpu/src/timers.v" xil_pn:type="FILE_VERILOG">
108108
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="109"/>
109-
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
109+
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
110110
</file>
111111
<file xil_pn:name="../cpu/cpusynth/button.v" xil_pn:type="FILE_VERILOG">
112112
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
113-
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
113+
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
114114
</file>
115115
<file xil_pn:name="../cpu/cpusynth/display_hex.v" xil_pn:type="FILE_VERILOG">
116116
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="111"/>
117-
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
117+
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
118118
</file>
119119
<file xil_pn:name="../cpu/cpusynth/display_signal.v" xil_pn:type="FILE_VERILOG">
120120
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
121-
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
121+
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
122122
</file>
123123
<file xil_pn:name="../cpu/cpusynth/lcd_control.v" xil_pn:type="FILE_VERILOG">
124124
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="113"/>
125-
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
125+
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
126126
</file>
127127
<file xil_pn:name="../cpu/cpusynth/lcd_top.ucf" xil_pn:type="FILE_UCF">
128128
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
129129
</file>
130130
<file xil_pn:name="../cpu/cpusynth/lcd_top.v" xil_pn:type="FILE_VERILOG">
131131
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
132-
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
132+
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
133133
</file>
134134
<file xil_pn:name="../my_clock_divider.v" xil_pn:type="FILE_VERILOG">
135135
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="116"/>
@@ -160,7 +160,7 @@
160160
</file>
161161
<file xil_pn:name="../fpgaboy_files/clk31p5_dcm.v" xil_pn:type="FILE_VERILOG">
162162
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
163-
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
163+
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
164164
</file>
165165
<file xil_pn:name="../fpgaboy_files/clk33_dcm.v" xil_pn:type="FILE_VERILOG">
166166
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
@@ -172,46 +172,46 @@
172172
</file>
173173
<file xil_pn:name="../fpgaboy_files/ddr2_idelay_ctrl_mod.v" xil_pn:type="FILE_VERILOG">
174174
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
175-
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
175+
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
176176
</file>
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<file xil_pn:name="../fpgaboy_files/ddr2_idelay_ctrl.v" xil_pn:type="FILE_VERILOG">
178178
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="127"/>
179-
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
179+
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
180180
</file>
181181
<file xil_pn:name="../fpgaboy_files/div4_dcm.v" xil_pn:type="FILE_VERILOG">
182182
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
183183
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="../fpgaboy_files/divider.v" xil_pn:type="FILE_VERILOG">
186186
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="129"/>
187-
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
187+
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
188188
</file>
189189
<file xil_pn:name="../fpgaboy_files/dvi_module.v" xil_pn:type="FILE_VERILOG">
190190
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/>
191-
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
191+
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192192
</file>
193193
<file xil_pn:name="../fpgaboy_files/frame_buffer.v" xil_pn:type="FILE_VERILOG">
194194
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="131"/>
195-
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
195+
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
196196
</file>
197197
<file xil_pn:name="../fpgaboy_files/gpu_top.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="../fpgaboy_files/gpu_top.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="133"/>
202-
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
202+
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203203
</file>
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<file xil_pn:name="../fpgaboy_files/iic_init.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
206-
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206+
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207207
</file>
208208
<file xil_pn:name="../fpgaboy_files/mult_dcm.v" xil_pn:type="FILE_VERILOG">
209209
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="135"/>
210210
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
211211
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212212
<file xil_pn:name="../fpgaboy_files/scanline_ram.v" xil_pn:type="FILE_VERILOG">
213213
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
214-
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
214+
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
215215
</file>
216216
<file xil_pn:name="../fpgaboy_files/scanline.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="137"/>
@@ -223,31 +223,49 @@
223223
</file>
224224
<file xil_pn:name="../fpgaboy_files/sync_gen.v" xil_pn:type="FILE_VERILOG">
225225
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="139"/>
226-
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226+
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227227
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228228
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229229
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230-
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230+
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231231
</file>
232232
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233233
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234-
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234+
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235235
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236236
<file xil_pn:name="../fpgaboy_files/video_module.v" xil_pn:type="FILE_VERILOG">
237237
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238-
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238+
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239239
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240240
<file xil_pn:name="../fpgaboy_files/video_ram.v" xil_pn:type="FILE_VERILOG">
241241
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242242
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243243
</file>
244244
<file xil_pn:name="../fpgaboy_files/x2_dcm.v" xil_pn:type="FILE_VERILOG">
245245
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
246-
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
246+
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
247247
</file>
248248
<file xil_pn:name="../cpu/cpusynth/mux.v" xil_pn:type="FILE_VERILOG">
249249
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
250-
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
250+
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
251+
</file>
252+
<file xil_pn:name="../GPU/ipcore_dir/OAM.ngc" xil_pn:type="FILE_NGC">
253+
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
254+
</file>
255+
<file xil_pn:name="../GPU/ipcore_dir/OAM.v" xil_pn:type="FILE_VERILOG">
256+
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
257+
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
258+
</file>
259+
<file xil_pn:name="../GPU/ipcore_dir/VRAM.ngc" xil_pn:type="FILE_NGC">
260+
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
261+
</file>
262+
<file xil_pn:name="../GPU/ipcore_dir/VRAM.v" xil_pn:type="FILE_VERILOG">
263+
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
264+
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
265+
</file>
266+
<file xil_pn:name="../cartridge_interface.v" xil_pn:type="FILE_VERILOG">
267+
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
268+
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
251269
</file>
252270
<file xil_pn:name="../GPU/ipcore_dir/OAM.xise" xil_pn:type="FILE_COREGENISE">
253271
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -597,6 +615,7 @@
597615
<!-- project is analyzed based on files automatically identified as -->
598616
<!-- include files. -->
599617
<file xil_pn:name="../cpu/src/cpu.vh" xil_pn:type="FILE_VERILOG"/>
618+
<file xil_pn:name="../cpu/cpusynth/cpu.vh" xil_pn:type="FILE_VERILOG"/>
600619
</autoManagedFiles>
601620

602621
</project>

Diff for: ‎GAMEBOY_TOP/_ngo/netlist.lst

+4-4
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
/Gameboy/Gameboy_git/GAMEBOY_TOP/lcd_top.ngc 1384973902
2-
ipcore_dir/blockram8192.ngc 1384973001
3-
../GPU/ipcore_dir/OAM.ngc 1384808859
4-
../GPU/ipcore_dir/VRAM.ngc 1384808859
1+
C:\Users\Joseph\Documents\GitHub\Gameboy\GAMEBOY_TOP\lcd_top.ngc 1384987447
2+
ipcore_dir/blockram8192.ngc 1384974803
3+
../GPU/ipcore_dir/OAM.ngc 1384965960
4+
../GPU/ipcore_dir/VRAM.ngc 1384965960
55
OK

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