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swankmania_HDL.map.rpt
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swankmania_HDL.map.rpt
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Analysis & Synthesis report for swankmania_HDL
Mon Nov 26 17:49:10 2007
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis RAM Summary
8. Registers Removed During Synthesis
9. General Register Statistics
10. Inverted Register Statistics
11. Gate-level Retiming
12. Multiplexer Restructuring Statistics (No Restructuring Performed)
13. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component
14. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated
15. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_e2c:wrptr_g1p
16. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_d2c:wrptr_gp
17. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|altsyncram_amu:fifo_ram
18. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|altsyncram_amu:fifo_ram|altsyncram_6p81:altsyncram3
19. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_7ub:rdaclr
20. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_1r7:rs_dgwp
21. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_1r7:rs_dgwp|dffpipe_c09:dffpipe3
22. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp
23. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp
24. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_gv7:ws_dgrp
25. Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_gv7:ws_dgrp|dffpipe_d09:dffpipe5
26. Source assignments for FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component|altsyncram_00b1:auto_generated
27. Parameter Settings for User Entity Instance: PLL_Sys:PLL_Sys0|altpll:altpll_component
28. Parameter Settings for User Entity Instance: ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component
29. Parameter Settings for User Entity Instance: ComCtrl:ComCtrl0|CmdDecoder:CmdDecoder0|lpm_decode:lpm_decode_component
30. Parameter Settings for User Entity Instance: FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component
31. Parameter Settings for User Entity Instance: Line:Line0
32. dcfifo Parameter Settings by Entity Instance
33. Analysis & Synthesis Messages
34. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Nov 26 17:49:10 2007 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name ; swankmania_HDL ;
; Top-level Entity Name ; swankmania_HDL ;
; Family ; Cyclone II ;
; Total logic elements ; 982 ;
; Total combinational functions ; 982 ;
; Dedicated logic registers ; 288 ;
; Total registers ; 288 ;
; Total pins ; 196 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 355,840 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
+------------------------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; swankmania_HDL ; swankmania_HDL ;
; Family name ; Cyclone II ; Stratix II ;
; Use smart compilation ; On ; Off ;
; Restructure Multiplexers ; Off ; Auto ;
; Verilog Show LMF Mapping Messages ; Off ; ;
; Verilog Version ; SystemVerilog_2005 ; Verilog_2001 ;
; State Machine Processing ; One-Hot ; Auto ;
; Remove Redundant Logic Cells ; On ; Off ;
; Optimization Technique -- Cyclone II/Cyclone III ; Speed ; Balanced ;
; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
; Perform gate-level register retiming ; On ; Off ;
; PowerPlay Power Optimization ; Off ; Normal compilation ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
; Source/Flip.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Source/Flip.v ;
; Lib/CmdDecoder.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Lib/CmdDecoder.v ;
; Lib/ComFIFO.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Lib/ComFIFO.v ;
; Lib/FrameA.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Lib/FrameA.v ;
; Lib/PLL_Sys.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Lib/PLL_Sys.v ;
; Source/Debounce.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Source/Debounce.v ;
; Source/ACX705AKM_Ctrl.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Source/ACX705AKM_Ctrl.v ;
; Source/ComCtrl.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Source/ComCtrl.v ;
; Source/FrameCtrl.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Source/FrameCtrl.v ;
; Source/Global.h ; yes ; User File ; C:/user/swankmania/swankmania_HDL/Source/Global.h ;
; Source/Line.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Source/Line.v ;
; Source/SSHLEDMDCtrl.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Source/SSHLEDMDCtrl.v ;
; Source/swankmania_HDL.v ; yes ; User Verilog HDL File ; C:/user/swankmania/swankmania_HDL/Source/swankmania_HDL.v ;
; altpll.tdf ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altpll.tdf ;
; aglobal72.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/aglobal72.inc ;
; stratix_pll.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; dcfifo.tdf ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/dcfifo.tdf ;
; lpm_counter.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_counter.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altdpram.inc ;
; a_graycounter.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/a_graycounter.inc ;
; a_fefifo.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/a_fefifo.inc ;
; a_gray2bin.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/a_gray2bin.inc ;
; dffpipe.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/dffpipe.inc ;
; alt_sync_fifo.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/alt_sync_fifo.inc ;
; lpm_compare.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_compare.inc ;
; altsyncram_fifo.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altsyncram_fifo.inc ;
; db/dcfifo_k1j1.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/dcfifo_k1j1.tdf ;
; db/a_gray2bin_ldb.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/a_gray2bin_ldb.tdf ;
; db/a_graycounter_p96.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/a_graycounter_p96.tdf ;
; db/a_graycounter_e2c.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/a_graycounter_e2c.tdf ;
; db/a_graycounter_d2c.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/a_graycounter_d2c.tdf ;
; db/altsyncram_amu.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/altsyncram_amu.tdf ;
; db/altsyncram_6p81.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/altsyncram_6p81.tdf ;
; db/dffpipe_7ub.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/dffpipe_7ub.tdf ;
; db/alt_synch_pipe_1r7.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/alt_synch_pipe_1r7.tdf ;
; db/dffpipe_c09.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/dffpipe_c09.tdf ;
; db/dffpipe_a09.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/dffpipe_a09.tdf ;
; db/alt_synch_pipe_gv7.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/alt_synch_pipe_gv7.tdf ;
; db/dffpipe_d09.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/dffpipe_d09.tdf ;
; db/mux_1u7.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/mux_1u7.tdf ;
; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf ;
; declut.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/declut.inc ;
; altshift.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altshift.inc ;
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_constant.inc ;
; db/decode_c8f.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/decode_c8f.tdf ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/lpm_decode.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altram.inc ;
; altqpram.inc ; yes ; Megafunction ; c:/altera/72/quartus/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_00b1.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/altsyncram_00b1.tdf ;
; db/decode_jpa.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/decode_jpa.tdf ;
; db/mux_4kb.tdf ; yes ; Auto-Generated Megafunction ; C:/user/swankmania/swankmania_HDL/db/mux_4kb.tdf ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+------------------------------------------------+
; Estimated Total logic elements ; 982 ;
; ; ;
; Total combinational functions ; 982 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 286 ;
; -- 3 input functions ; 447 ;
; -- <=2 input functions ; 249 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 613 ;
; -- arithmetic mode ; 369 ;
; ; ;
; Total registers ; 288 ;
; -- Dedicated logic registers ; 288 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 196 ;
; Total memory bits ; 355840 ;
; Total PLLs ; 1 ;
; Maximum fan-out node ; PLL_Sys:PLL_Sys0|altpll:altpll_component|_clk0 ;
; Maximum fan-out ; 304 ;
; Total fan-out ; 5477 ;
; Average fan-out ; 3.50 ;
+---------------------------------------------+------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |swankmania_HDL ; 982 (4) ; 288 (0) ; 355840 ; 0 ; 0 ; 0 ; 196 ; 0 ; |swankmania_HDL ; work ;
; |ACX705AKM_Ctrl:ACX705AKM_Ctrl0| ; 93 (92) ; 45 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ACX705AKM_Ctrl:ACX705AKM_Ctrl0 ; work ;
; |Debounce:Debounce0| ; 1 (1) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ACX705AKM_Ctrl:ACX705AKM_Ctrl0|Debounce:Debounce0 ; work ;
; |ComCtrl:ComCtrl0| ; 162 (56) ; 146 (57) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0 ; work ;
; |CmdDecoder:CmdDecoder0| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|CmdDecoder:CmdDecoder0 ; work ;
; |lpm_decode:lpm_decode_component| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|CmdDecoder:CmdDecoder0|lpm_decode:lpm_decode_component ; work ;
; |decode_c8f:auto_generated| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|CmdDecoder:CmdDecoder0|lpm_decode:lpm_decode_component|decode_c8f:auto_generated ; work ;
; |ComFIFO:ComFIFO0| ; 105 (0) ; 89 (0) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0 ; work ;
; |dcfifo:dcfifo_component| ; 105 (0) ; 89 (0) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component ; work ;
; |dcfifo_k1j1:auto_generated| ; 105 (16) ; 89 (22) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated ; work ;
; |a_gray2bin_ldb:wrptr_g_gray2bin| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_gray2bin_ldb:wrptr_g_gray2bin ; work ;
; |a_gray2bin_ldb:ws_dgrp_gray2bin| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_gray2bin_ldb:ws_dgrp_gray2bin ; work ;
; |a_graycounter_d2c:wrptr_gp| ; 12 (12) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_d2c:wrptr_gp ; work ;
; |a_graycounter_e2c:wrptr_g1p| ; 14 (14) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_e2c:wrptr_g1p ; work ;
; |a_graycounter_p96:rdptr_g1p| ; 12 (12) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_p96:rdptr_g1p ; work ;
; |alt_synch_pipe_gv7:ws_dgrp| ; 0 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_gv7:ws_dgrp ; work ;
; |dffpipe_d09:dffpipe5| ; 0 (0) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_gv7:ws_dgrp|dffpipe_d09:dffpipe5 ; work ;
; |altsyncram_amu:fifo_ram| ; 0 (0) ; 0 (0) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|altsyncram_amu:fifo_ram ; work ;
; |altsyncram_6p81:altsyncram3| ; 0 (0) ; 0 (0) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|altsyncram_amu:fifo_ram|altsyncram_6p81:altsyncram3 ; work ;
; |dffpipe_a09:ws_brp| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp ; work ;
; |dffpipe_a09:ws_bwp| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp ; work ;
; |mux_1u7:rdemp_eq_comp_lsb_mux| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|mux_1u7:rdemp_eq_comp_lsb_mux ; work ;
; |mux_1u7:rdemp_eq_comp_msb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|mux_1u7:rdemp_eq_comp_msb_mux ; work ;
; |mux_1u7:wrfull_eq_comp_lsb_mux| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|mux_1u7:wrfull_eq_comp_lsb_mux ; work ;
; |mux_1u7:wrfull_eq_comp_msb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|mux_1u7:wrfull_eq_comp_msb_mux ; work ;
; |Flip:Flip0| ; 23 (23) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|Flip:Flip0 ; work ;
; |FrameCtrl:FrameCtrl0| ; 179 (111) ; 9 (1) ; 345600 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|FrameCtrl:FrameCtrl0 ; work ;
; |FrameA:FrameA0| ; 68 (0) ; 8 (0) ; 345600 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|FrameCtrl:FrameCtrl0|FrameA:FrameA0 ; work ;
; |altsyncram:altsyncram_component| ; 68 (0) ; 8 (0) ; 345600 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component ; work ;
; |altsyncram_00b1:auto_generated| ; 68 (0) ; 8 (8) ; 345600 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component|altsyncram_00b1:auto_generated ; work ;
; |decode_jpa:decode3| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component|altsyncram_00b1:auto_generated|decode_jpa:decode3 ; work ;
; |mux_4kb:mux2| ; 54 (54) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component|altsyncram_00b1:auto_generated|mux_4kb:mux2 ; work ;
; |Line:Line0| ; 487 (487) ; 71 (71) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|Line:Line0 ; work ;
; |PLL_Sys:PLL_Sys0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|PLL_Sys:PLL_Sys0 ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|PLL_Sys:PLL_Sys0|altpll:altpll_component ; work ;
; |SSHLEDMDCtrl:gSSHLEDMDCtrl[0].Digit| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|SSHLEDMDCtrl:gSSHLEDMDCtrl[0].Digit ; work ;
; |SSHLEDMDCtrl:gSSHLEDMDCtrl[1].Digit| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|SSHLEDMDCtrl:gSSHLEDMDCtrl[1].Digit ; work ;
; |SSHLEDMDCtrl:gSSHLEDMDCtrl[2].Digit| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|SSHLEDMDCtrl:gSSHLEDMDCtrl[2].Digit ; work ;
; |SSHLEDMDCtrl:gSSHLEDMDCtrl[4].Digit| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|SSHLEDMDCtrl:gSSHLEDMDCtrl[4].Digit ; work ;
; |SSHLEDMDCtrl:gSSHLEDMDCtrl[5].Digit| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|SSHLEDMDCtrl:gSSHLEDMDCtrl[5].Digit ; work ;
; |SSHLEDMDCtrl:gSSHLEDMDCtrl[6].Digit| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |swankmania_HDL|SSHLEDMDCtrl:gSSHLEDMDCtrl[6].Digit ; work ;
+--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+----------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+----------------+
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|altsyncram_amu:fifo_ram|altsyncram_6p81:altsyncram3|ALTSYNCRAM ; AUTO ; True Dual Port ; 1024 ; 10 ; 1024 ; 10 ; 10240 ; None ;
; FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component|altsyncram_00b1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 38400 ; 9 ; -- ; -- ; 345600 ; ../startup.hex ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+--------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+--------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; Line:Line0|_LastStep[8] ; Stuck at GND due to stuck port data_in ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_7ub:rdaclr|dffe5a[0] ; Stuck at VCC due to stuck port data_in ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[10] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[10] ; Lost fanout ;
; Line:Line0|_Y[8] ; Lost fanout ;
; Flip:Flip0|_Done ; Merged with Flip:Flip0|_WrEn ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[5] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[5] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[4] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[4] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[3] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[3] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[2] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[2] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[1] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[1] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[0] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[0] ; Lost fanout ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|delayed_wrptr_g[0..4] ; Lost fanout ;
; Total Number of Removed Registers = 23 ; ;
+--------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 288 ;
; Number of registers using Synchronous Clear ; 24 ;
; Number of registers using Synchronous Load ; 68 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 124 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics ;
+-------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+-------------------------------------------------------------------------------------------------------------------------------+---------+
; FrameCtrl:FrameCtrl0|_Face0 ; 79 ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_e2c:wrptr_g1p|counter_ffa0 ; 3 ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|rdemp_eq_comp_lsb_aeb ; 3 ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|rdemp_eq_comp_msb_aeb ; 3 ;
; Line:Line0|_Done ; 38 ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_e2c:wrptr_g1p|parity_ff ; 1 ;
; ComCtrl:ComCtrl0|_Y ; 4 ;
; ACX705AKM_Ctrl:ACX705AKM_Ctrl0|_Vsync ; 2 ;
; ACX705AKM_Ctrl:ACX705AKM_Ctrl0|_Hsync ; 1 ;
; Total number of inverted registers = 9 ; ;
+-------------------------------------------------------------------------------------------------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Gate-level Retiming ;
+----------------------------------------------------------------------------------------------------------------------+-------------------------------------+-----------------+
; Register Name ; Clock Name ; Created/Deleted ;
+----------------------------------------------------------------------------------------------------------------------+-------------------------------------+-----------------+
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[5] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[5] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[4] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[4] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[3] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[3] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[2] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[2] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[1] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[1] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[0] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[0] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|delayed_wrptr_g[4] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|delayed_wrptr_g[3] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|delayed_wrptr_g[2] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|delayed_wrptr_g[1] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|delayed_wrptr_g[0] ; ioGPIO0[19]~4 ; Deleted ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[0]~61 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[0]~62 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[0]~63 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[0]~64 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[0]~65 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp|dffe7a[0]~66 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[0]~61 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[0]~62 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[0]~63 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[0]~64 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[0]~65 ; ioGPIO0[19]~4 ; Created ;
; ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp|dffe7a[0]~66 ; ioGPIO0[19]~4 ; Created ;
; ACX705AKM_Ctrl:ACX705AKM_Ctrl0|_DotCnt[1]~193 ; ACX705AKM_Ctrl:ACX705AKM_Ctrl0|_MCK ; Created ;
+----------------------------------------------------------------------------------------------------------------------+-------------------------------------+-----------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+
; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |swankmania_HDL|Line:Line0|_dy[0] ;
; 4:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |swankmania_HDL|ComCtrl:ComCtrl0|_VertexBuf[0][6] ;
; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |swankmania_HDL|ComCtrl:ComCtrl0|_VertexBuf[2][0] ;
; 4:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |swankmania_HDL|ComCtrl:ComCtrl0|_VertexBuf[1][0] ;
; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |swankmania_HDL|ComCtrl:ComCtrl0|_Cnt[5] ;
; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |swankmania_HDL|Line:Line0|_AddrX[3] ;
; 4:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |swankmania_HDL|Line:Line0|_dx[2] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |swankmania_HDL|Line:Line0|_Y[5] ;
; 7:1 ; 9 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |swankmania_HDL|Line:Line0|_Err[4] ;
; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |swankmania_HDL|Line:Line0|_AddrY~18 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+
+----------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component ;
+---------------------------------+-------+------+---------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+---------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+---------------------------------+
+-------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated ;
+---------------------------------+-------+-----------------+-------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+-----------------+-------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; POWER_UP_LEVEL ; LOW ; - ; p0addr ;
; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ;
; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ;
; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe5|dffe6a ;
; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe3|dffe4a ;
+---------------------------------+-------+-----------------+-------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_e2c:wrptr_g1p ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; POWER_UP_LEVEL ; HIGH ; - ; counter_ffa0 ;
; POWER_UP_LEVEL ; HIGH ; - ; parity_ff ;
+---------------------------+-------+------+----------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|a_graycounter_d2c:wrptr_gp ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|altsyncram_amu:fifo_ram ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; OFF ; - ; - ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|altsyncram_amu:fifo_ram|altsyncram_6p81:altsyncram3 ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; OFF ; - ; - ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_7ub:rdaclr ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; c106 ; - ; - ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_1r7:rs_dgwp ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF ; - ; - ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_1r7:rs_dgwp|dffpipe_c09:dffpipe3 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_brp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|dffpipe_a09:ws_bwp ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+-------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_gv7:ws_dgrp ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------+
; X_ON_VIOLATION_OPTION ; OFF ; - ; - ;
+-----------------------+-------+------+-------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component|dcfifo_k1j1:auto_generated|alt_synch_pipe_gv7:ws_dgrp|dffpipe_d09:dffpipe5 ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component|altsyncram_00b1:auto_generated ;
+---------------------------------+-------+------+--------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+--------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; D101 ; - ; - ;
; OPTIMIZE_POWER_DURING_SYNTHESIS ; OFF ; - ; - ;
+---------------------------------+-------+------+--------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: PLL_Sys:PLL_Sys0|altpll:altpll_component ;
+-------------------------------+-------------------+-----------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------------+-------------------+-----------------------------------+
; OPERATION_MODE ; NORMAL ; Untyped ;
; PLL_TYPE ; AUTO ; Untyped ;
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
; SCAN_CHAIN ; LONG ; Untyped ;
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ;
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
; LOCK_HIGH ; 1 ; Untyped ;
; LOCK_LOW ; 1 ; Untyped ;
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
; SKIP_VCO ; OFF ; Untyped ;
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
; BANDWIDTH ; 0 ; Untyped ;
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
; SPREAD_FREQUENCY ; 0 ; Untyped ;
; DOWN_SPREAD ; 0 ; Untyped ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
; CLK1_MULTIPLY_BY ; 2 ; Signed Integer ;
; CLK0_MULTIPLY_BY ; 8 ; Signed Integer ;
; CLK9_DIVIDE_BY ; 0 ; Untyped ;
; CLK8_DIVIDE_BY ; 0 ; Untyped ;
; CLK7_DIVIDE_BY ; 0 ; Untyped ;
; CLK6_DIVIDE_BY ; 0 ; Untyped ;
; CLK5_DIVIDE_BY ; 1 ; Untyped ;
; CLK4_DIVIDE_BY ; 1 ; Untyped ;
; CLK3_DIVIDE_BY ; 1 ; Untyped ;
; CLK2_DIVIDE_BY ; 1 ; Untyped ;
; CLK1_DIVIDE_BY ; 1 ; Signed Integer ;
; CLK0_DIVIDE_BY ; 25 ; Signed Integer ;
; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_TIME_DELAY ; 0 ; Untyped ;
; CLK4_TIME_DELAY ; 0 ; Untyped ;
; CLK3_TIME_DELAY ; 0 ; Untyped ;
; CLK2_TIME_DELAY ; 0 ; Untyped ;
; CLK1_TIME_DELAY ; 0 ; Untyped ;
; CLK0_TIME_DELAY ; 0 ; Untyped ;
; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
; VCO_MULTIPLY_BY ; 0 ; Untyped ;
; VCO_DIVIDE_BY ; 0 ; Untyped ;
; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
; VCO_MIN ; 0 ; Untyped ;
; VCO_MAX ; 0 ; Untyped ;
; VCO_CENTER ; 0 ; Untyped ;
; PFD_MIN ; 0 ; Untyped ;
; PFD_MAX ; 0 ; Untyped ;
; M_INITIAL ; 0 ; Untyped ;
; M ; 0 ; Untyped ;
; N ; 1 ; Untyped ;
; M2 ; 1 ; Untyped ;
; N2 ; 1 ; Untyped ;
; SS ; 1 ; Untyped ;
; C0_HIGH ; 0 ; Untyped ;
; C1_HIGH ; 0 ; Untyped ;
; C2_HIGH ; 0 ; Untyped ;
; C3_HIGH ; 0 ; Untyped ;
; C4_HIGH ; 0 ; Untyped ;
; C5_HIGH ; 0 ; Untyped ;
; C6_HIGH ; 0 ; Untyped ;
; C7_HIGH ; 0 ; Untyped ;
; C8_HIGH ; 0 ; Untyped ;
; C9_HIGH ; 0 ; Untyped ;
; C0_LOW ; 0 ; Untyped ;
; C1_LOW ; 0 ; Untyped ;
; C2_LOW ; 0 ; Untyped ;
; C3_LOW ; 0 ; Untyped ;
; C4_LOW ; 0 ; Untyped ;
; C5_LOW ; 0 ; Untyped ;
; C6_LOW ; 0 ; Untyped ;
; C7_LOW ; 0 ; Untyped ;
; C8_LOW ; 0 ; Untyped ;
; C9_LOW ; 0 ; Untyped ;
; C0_INITIAL ; 0 ; Untyped ;
; C1_INITIAL ; 0 ; Untyped ;
; C2_INITIAL ; 0 ; Untyped ;
; C3_INITIAL ; 0 ; Untyped ;
; C4_INITIAL ; 0 ; Untyped ;
; C5_INITIAL ; 0 ; Untyped ;
; C6_INITIAL ; 0 ; Untyped ;
; C7_INITIAL ; 0 ; Untyped ;
; C8_INITIAL ; 0 ; Untyped ;
; C9_INITIAL ; 0 ; Untyped ;
; C0_MODE ; BYPASS ; Untyped ;
; C1_MODE ; BYPASS ; Untyped ;
; C2_MODE ; BYPASS ; Untyped ;
; C3_MODE ; BYPASS ; Untyped ;
; C4_MODE ; BYPASS ; Untyped ;
; C5_MODE ; BYPASS ; Untyped ;
; C6_MODE ; BYPASS ; Untyped ;
; C7_MODE ; BYPASS ; Untyped ;
; C8_MODE ; BYPASS ; Untyped ;
; C9_MODE ; BYPASS ; Untyped ;
; C0_PH ; 0 ; Untyped ;
; C1_PH ; 0 ; Untyped ;
; C2_PH ; 0 ; Untyped ;
; C3_PH ; 0 ; Untyped ;
; C4_PH ; 0 ; Untyped ;
; C5_PH ; 0 ; Untyped ;
; C6_PH ; 0 ; Untyped ;
; C7_PH ; 0 ; Untyped ;
; C8_PH ; 0 ; Untyped ;
; C9_PH ; 0 ; Untyped ;
; L0_HIGH ; 1 ; Untyped ;
; L1_HIGH ; 1 ; Untyped ;
; G0_HIGH ; 1 ; Untyped ;
; G1_HIGH ; 1 ; Untyped ;
; G2_HIGH ; 1 ; Untyped ;
; G3_HIGH ; 1 ; Untyped ;
; E0_HIGH ; 1 ; Untyped ;
; E1_HIGH ; 1 ; Untyped ;
; E2_HIGH ; 1 ; Untyped ;
; E3_HIGH ; 1 ; Untyped ;
; L0_LOW ; 1 ; Untyped ;
; L1_LOW ; 1 ; Untyped ;
; G0_LOW ; 1 ; Untyped ;
; G1_LOW ; 1 ; Untyped ;
; G2_LOW ; 1 ; Untyped ;
; G3_LOW ; 1 ; Untyped ;
; E0_LOW ; 1 ; Untyped ;
; E1_LOW ; 1 ; Untyped ;
; E2_LOW ; 1 ; Untyped ;
; E3_LOW ; 1 ; Untyped ;
; L0_INITIAL ; 1 ; Untyped ;
; L1_INITIAL ; 1 ; Untyped ;
; G0_INITIAL ; 1 ; Untyped ;
; G1_INITIAL ; 1 ; Untyped ;
; G2_INITIAL ; 1 ; Untyped ;
; G3_INITIAL ; 1 ; Untyped ;
; E0_INITIAL ; 1 ; Untyped ;
; E1_INITIAL ; 1 ; Untyped ;
; E2_INITIAL ; 1 ; Untyped ;
; E3_INITIAL ; 1 ; Untyped ;
; L0_MODE ; BYPASS ; Untyped ;
; L1_MODE ; BYPASS ; Untyped ;
; G0_MODE ; BYPASS ; Untyped ;
; G1_MODE ; BYPASS ; Untyped ;
; G2_MODE ; BYPASS ; Untyped ;
; G3_MODE ; BYPASS ; Untyped ;
; E0_MODE ; BYPASS ; Untyped ;
; E1_MODE ; BYPASS ; Untyped ;
; E2_MODE ; BYPASS ; Untyped ;
; E3_MODE ; BYPASS ; Untyped ;
; L0_PH ; 0 ; Untyped ;
; L1_PH ; 0 ; Untyped ;
; G0_PH ; 0 ; Untyped ;
; G1_PH ; 0 ; Untyped ;
; G2_PH ; 0 ; Untyped ;
; G3_PH ; 0 ; Untyped ;
; E0_PH ; 0 ; Untyped ;
; E1_PH ; 0 ; Untyped ;
; E2_PH ; 0 ; Untyped ;
; E3_PH ; 0 ; Untyped ;
; M_PH ; 0 ; Untyped ;
; C1_USE_CASC_IN ; OFF ; Untyped ;
; C2_USE_CASC_IN ; OFF ; Untyped ;
; C3_USE_CASC_IN ; OFF ; Untyped ;
; C4_USE_CASC_IN ; OFF ; Untyped ;
; C5_USE_CASC_IN ; OFF ; Untyped ;
; C6_USE_CASC_IN ; OFF ; Untyped ;
; C7_USE_CASC_IN ; OFF ; Untyped ;
; C8_USE_CASC_IN ; OFF ; Untyped ;
; C9_USE_CASC_IN ; OFF ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; CLK6_COUNTER ; E0 ; Untyped ;
; CLK7_COUNTER ; E1 ; Untyped ;
; CLK8_COUNTER ; E2 ; Untyped ;
; CLK9_COUNTER ; E3 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone II ; Untyped ;
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK0 ; PORT_USED ; Untyped ;
; PORT_CLK1 ; PORT_USED ; Untyped ;
; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_CLK6 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK7 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK8 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK9 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; C6_TEST_SOURCE ; 5 ; Untyped ;
; C7_TEST_SOURCE ; 5 ; Untyped ;
; C8_TEST_SOURCE ; 5 ; Untyped ;
; C9_TEST_SOURCE ; 5 ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
; WIDTH_CLOCK ; 6 ; Untyped ;
; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ComCtrl:ComCtrl0|ComFIFO:ComFIFO0|dcfifo:dcfifo_component ;
+-------------------------+-------------+----------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------+-------------+----------------------------------------------------------------+
; WIDTH_BYTEENA ; 1 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 10 ; Signed Integer ;
; LPM_NUMWORDS ; 1024 ; Signed Integer ;
; LPM_WIDTHU ; 10 ; Signed Integer ;
; LPM_SHOWAHEAD ; ON ; Untyped ;
; UNDERFLOW_CHECKING ; ON ; Untyped ;
; OVERFLOW_CHECKING ; ON ; Untyped ;
; USE_EAB ; ON ; Untyped ;
; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ;
; DELAY_RDUSEDW ; 1 ; Untyped ;
; DELAY_WRUSEDW ; 1 ; Untyped ;
; RDSYNC_DELAYPIPE ; 3 ; Signed Integer ;
; WRSYNC_DELAYPIPE ; 3 ; Signed Integer ;
; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ;
; MAXIMIZE_SPEED ; 7 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; ADD_USEDW_MSB_BIT ; OFF ; Untyped ;
; WRITE_ACLR_SYNCH ; OFF ; Untyped ;
; CBXI_PARAMETER ; dcfifo_k1j1 ; Untyped ;
+-------------------------+-------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ComCtrl:ComCtrl0|CmdDecoder:CmdDecoder0|lpm_decode:lpm_decode_component ;
+------------------------+------------+--------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+------------+--------------------------------------------------------------------------------+
; LPM_WIDTH ; 4 ; Signed Integer ;
; LPM_DECODES ; 16 ; Signed Integer ;
; LPM_PIPELINE ; 0 ; Untyped ;
; CASCADE_CHAIN ; MANUAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; decode_c8f ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: FrameCtrl:FrameCtrl0|FrameA:FrameA0|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+------------------------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
; WIDTH_A ; 9 ; Signed Integer ;
; WIDTHAD_A ; 16 ; Signed Integer ;
; NUMWORDS_A ; 38400 ; Signed Integer ;