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prev_cmp_swankmania_HDL.qmsg
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prev_cmp_swankmania_HDL.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 27 18:30:20 2007 " "Info: Processing started: Thu Sep 27 18:30:20 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off swankmania_HDL -c swankmania_HDL " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off swankmania_HDL -c swankmania_HDL" { } { } 0 0 "Command: %1!s!" 1 0 "" 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "wef " "Warning: Ignored assignments for entity \"wef\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -entity wef -section_id Top " "Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "HDL_Source/Library/M4K_38400.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file HDL_Source/Library/M4K_38400.v" { { "Info" "ISGN_ENTITY_NAME" "1 M4K_38400 " "Info: Found entity 1: M4K_38400" { } { { "HDL_Source/Library/M4K_38400.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/Library/M4K_38400.v" 39 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "HDL_Source/Library/PLL_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file HDL_Source/Library/PLL_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL_16 " "Info: Found entity 1: PLL_16" { } { { "HDL_Source/Library/PLL_16.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/Library/PLL_16.v" 39 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 1 0 "" 0}
{ "Warning" "WVRFX_VERI_COMPLICATED_EVENT_EXPR" "swankmania_HDL.v(176) " "Warning (10261): Verilog HDL Event Control warning at swankmania_HDL.v(176): Event Control contains a complex event expression" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 176 0 0 } } } 0 10261 "Verilog HDL Event Control warning at %1!s!: Event Control contains a complex event expression" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "FrameBuffer_Adr swankmania_HDL.v(102) " "Warning (10236): Verilog HDL Implicit Net warning at swankmania_HDL.v(102): created implicit net for \"FrameBuffer_Adr\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 102 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "HDL_Source/swankmania_HDL.v 3 3 " "Info: Found 3 design units, including 3 entities, in source file HDL_Source/swankmania_HDL.v" { { "Info" "ISGN_ENTITY_NAME" "1 swankmania_HDL " "Info: Found entity 1: swankmania_HDL" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 9 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 ACX705AKM_Ctrl " "Info: Found entity 2: ACX705AKM_Ctrl" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 209 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 FrequencyDivider50 " "Info: Found entity 3: FrequencyDivider50" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 233 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 1 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "swankmania_HDL " "Info: Elaborating entity \"swankmania_HDL\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 1 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "_LineCount swankmania_HDL.v(107) " "Warning (10036): Verilog HDL or VHDL warning at swankmania_HDL.v(107): object \"_LineCount\" assigned a value but never read" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 107 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "FrameBuffer_Adr swankmania_HDL.v(102) " "Warning (10036): Verilog HDL or VHDL warning at swankmania_HDL.v(102): object \"FrameBuffer_Adr\" assigned a value but never read" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 102 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 1 swankmania_HDL.v(102) " "Warning (10230): Verilog HDL assignment warning at swankmania_HDL.v(102): truncated value with size 16 to match size of target (1)" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL_16 PLL_16:PLL_16_0 " "Info: Elaborating entity \"PLL_16\" for hierarchy \"PLL_16:PLL_16_0\"" { } { { "HDL_Source/swankmania_HDL.v" "PLL_16_0" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 76 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/71sp1/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" { } { { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 462 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 1 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL_16:PLL_16_0\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL_16:PLL_16_0\|altpll:altpll_component\"" { } { { "HDL_Source/Library/PLL_16.v" "altpll_component" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/Library/PLL_16.v" 88 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 1 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "PLL_16:PLL_16_0\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"PLL_16:PLL_16_0\|altpll:altpll_component\"" { } { { "HDL_Source/Library/PLL_16.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/Library/PLL_16.v" 88 0 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 1 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[12\] " "Warning: The bidir \"GPIO_1\[12\]\" has no source; inserted an always disabled tri-state buffer." { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "Warning: The bidir \"GPIO_1\[14\]\" has no source; inserted an always disabled tri-state buffer." { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "Warning: The bidir \"GPIO_1\[16\]\" has no source; inserted an always disabled tri-state buffer." { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "Warning: The bidir \"GPIO_1\[18\]\" has no source; inserted an always disabled tri-state buffer." { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "The bidir \"%1!s!\" has no source; inserted an always disabled tri-state buffer." 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[0\]~21 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[0\]~21 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[1\]~20 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[1\]~20 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[2\]~19 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[2\]~19 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[2\]~19 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[2\]~19 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[3\]~18 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[3\]~18 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[4\]~17 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[4\]~17 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[4\]~17 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[4\]~17 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[5\]~16 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[5\]~16 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[6\]~15 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[6\]~15 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[6\]~15 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[6\]~15 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[7\]~14 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[7\]~14 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[8\]~13 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[8\]~13 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[8\]~13 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[8\]~13 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[9\]~12 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[9\]~12 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[10\]~11 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[10\]~11 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[11\]~10 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[11\]~10 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[13\]~9 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[13\]~9 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[15\]~8 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[15\]~8 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[17\]~7 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[17\]~7 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[19\]~6 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[19\]~6 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 110 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[20\]~5 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[20\]~5 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[21\]~4 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[21\]~4 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 109 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[22\]~3 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[22\]~3 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[23\]~2 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[23\]~2 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[24\]~1 " "Warning: Replaced VCC or GND feeding tri-state bus GPIO_1\[24\]~1 with an always-enabled tri-state buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Replaced VCC or GND feeding tri-state bus %1!s! with an always-enabled tri-state buffer" 0 0 "" 0}
{ "Warning" "WOPT_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[25\]~0 " "Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIO_1\[25\]~0 that it feeds" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } } 0 0 "Inserted an always-enabled tri-state buffer between logic and the tri-state bus %1!s! that it feeds" 0 0 "" 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[1\]~43 " "Warning: Node \"GPIO_1\[1\]~43\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[3\]~46 " "Warning: Node \"GPIO_1\[3\]~46\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[5\]~49 " "Warning: Node \"GPIO_1\[5\]~49\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[7\]~52 " "Warning: Node \"GPIO_1\[7\]~52\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[9\]~55 " "Warning: Node \"GPIO_1\[9\]~55\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[11\]~57 " "Warning: Node \"GPIO_1\[11\]~57\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[13\]~58 " "Warning: Node \"GPIO_1\[13\]~58\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[15\]~59 " "Warning: Node \"GPIO_1\[15\]~59\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[17\]~60 " "Warning: Node \"GPIO_1\[17\]~60\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[19\]~61 " "Warning: Node \"GPIO_1\[19\]~61\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[21\]~63 " "Warning: Node \"GPIO_1\[21\]~63\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[23\]~65 " "Warning: Node \"GPIO_1\[23\]~65\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "GPIO_1\[25\]~67 " "Warning: Node \"GPIO_1\[25\]~67\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} } { } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0}
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "wef " "Warning: Ignored assignments for entity \"wef\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -entity wef -section_id Top " "Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to \| -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity wef -section_id Top " "Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity wef -section_id Top is ignored" { } { } 0 0 "Assignment of entity %1!s! is ignored" 0 0 "" 0} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/user/swankmania/swankmania_HDL/swankmania_HDL.map.smsg " "Info: Generated suppressed messages file C:/user/swankmania/swankmania_HDL/swankmania_HDL.map.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 1 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "10 " "Warning: Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_27 " "Warning: No output dependent on input pin \"CLOCK_27\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 11 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning: No output dependent on input pin \"SW\[9\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[10\] " "Warning: No output dependent on input pin \"SW\[10\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[11\] " "Warning: No output dependent on input pin \"SW\[11\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[12\] " "Warning: No output dependent on input pin \"SW\[12\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[13\] " "Warning: No output dependent on input pin \"SW\[13\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[14\] " "Warning: No output dependent on input pin \"SW\[14\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[15\] " "Warning: No output dependent on input pin \"SW\[15\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[16\] " "Warning: No output dependent on input pin \"SW\[16\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[17\] " "Warning: No output dependent on input pin \"SW\[17\]\"" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "102 " "Info: Implemented 102 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Info: Implemented 20 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "0 " "Info: Implemented 0 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "26 " "Info: Implemented 26 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "55 " "Info: Implemented 55 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" { } { } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 1 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 75 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 75 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 27 18:30:22 2007 " "Info: Processing ended: Thu Sep 27 18:30:22 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 1 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 27 18:30:23 2007 " "Info: Processing started: Thu Sep 27 18:30:23 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL" { } { } 0 0 "Command: %1!s!" 1 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "swankmania_HDL EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"swankmania_HDL\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 1 0 "" 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "PLL_16:PLL_16_0\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"PLL_16:PLL_16_0\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 8 25 0 0 " "Info: Implementing clock multiplication of 8, clock division of 25, and phase shift of 0 degrees (0 ps) for PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 port" { } { { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0} } { { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 1 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 1 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 1 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 1 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "126 Top " "Info: Previous placement does not exist for 126 of 126 atoms in partition Top" { } { } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0} } { } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" { } { } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} } { { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 504 3 0 } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "_MCK " "Info: Automatically promoted node _MCK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[25\] " "Info: Destination node GPIO_1\[25\]" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "_MCK~2 " "Info: Destination node _MCK~2" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { _MCK~2 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { _MCK~2 } "NODE_NAME" } } } 0 0 "Destination node %1!s!" 0 0 "" 0} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0} } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { _MCK } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { _MCK } "NODE_NAME" } } } 0 0 "Automatically promoted node %1!s! %2!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0} } { } 0 0 "Finished register packing: elapsed time is %1!s!" 1 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Warning: Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Warning: Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Warning: Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Warning: Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Warning: Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Warning: Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Warning: Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Warning: Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Warning: Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Warning: Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Warning: Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Warning: Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Warning: Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Warning: Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Warning: Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Warning: Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Warning: Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Warning: Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_0 " "Warning: Node \"DRAM_BA_0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_1 " "Warning: Node \"DRAM_BA_1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Warning: Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Warning: Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Warning: Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Warning: Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Warning: Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Warning: Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Warning: Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Warning: Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Warning: Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Warning: Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Warning: Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Warning: Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Warning: Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Warning: Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Warning: Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Warning: Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Warning: Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Warning: Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Warning: Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Warning: Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_LDQM " "Warning: Node \"DRAM_LDQM\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Warning: Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_UDQM " "Warning: Node \"DRAM_UDQM\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Warning: Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CLK " "Warning: Node \"ENET_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CMD " "Warning: Node \"ENET_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CMD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_CS_N " "Warning: Node \"ENET_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[0\] " "Warning: Node \"ENET_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[10\] " "Warning: Node \"ENET_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[11\] " "Warning: Node \"ENET_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[12\] " "Warning: Node \"ENET_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[13\] " "Warning: Node \"ENET_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[14\] " "Warning: Node \"ENET_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[15\] " "Warning: Node \"ENET_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[1\] " "Warning: Node \"ENET_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[2\] " "Warning: Node \"ENET_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[3\] " "Warning: Node \"ENET_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[4\] " "Warning: Node \"ENET_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[5\] " "Warning: Node \"ENET_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[6\] " "Warning: Node \"ENET_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[7\] " "Warning: Node \"ENET_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[8\] " "Warning: Node \"ENET_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_DATA\[9\] " "Warning: Node \"ENET_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_INT " "Warning: Node \"ENET_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_INT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RD_N " "Warning: Node \"ENET_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_RD_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_RST_N " "Warning: Node \"ENET_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET_WR_N " "Warning: Node \"ENET_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "ENET_WR_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EXT_CLOCK " "Warning: Node \"EXT_CLOCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "EXT_CLOCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Warning: Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Warning: Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Warning: Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Warning: Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Warning: Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Warning: Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Warning: Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Warning: Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Warning: Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Warning: Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Warning: Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Warning: Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Warning: Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Warning: Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Warning: Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Warning: Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Warning: Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Warning: Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Warning: Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Warning: Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Warning: Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Warning: Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Warning: Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Warning: Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Warning: Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Warning: Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Warning: Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Warning: Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Warning: Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Warning: Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Warning: Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Warning: Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Warning: Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Warning: Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Warning: Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Warning: Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Warning: Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Warning: Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Warning: Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Warning: Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Warning: Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Warning: Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Warning: Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Warning: Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Warning: Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Warning: Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Warning: Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Warning: Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Warning: Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Warning: Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Warning: Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Warning: Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Warning: Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Warning: Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Warning: Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Warning: Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Warning: Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Warning: Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Warning: Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Warning: Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Warning: Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[34\] " "Warning: Node \"GPIO_0\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[35\] " "Warning: Node \"GPIO_0\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Warning: Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Warning: Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Warning: Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Warning: Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Warning: Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Warning: Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Warning: Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Warning: Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Warning: Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Warning: Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Warning: Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Warning: Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Warning: Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Warning: Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Warning: Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[34\] " "Warning: Node \"GPIO_1\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[35\] " "Warning: Node \"GPIO_1\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Warning: Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Warning: Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Warning: Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Warning: Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Warning: Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Warning: Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Warning: Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Warning: Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Warning: Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Warning: Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Warning: Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Warning: Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Warning: Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Warning: Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Warning: Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Warning: Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Warning: Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Warning: Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Warning: Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Warning: Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Warning: Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Warning: Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Warning: Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Warning: Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Warning: Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Warning: Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Warning: Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Warning: Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Warning: Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Warning: Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Warning: Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Warning: Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Warning: Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Warning: Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Warning: Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Warning: Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Warning: Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Warning: Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Warning: Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Warning: Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Warning: Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Warning: Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Warning: Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Warning: Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Warning: Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Warning: Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Warning: Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Warning: Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Warning: Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Warning: Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Warning: Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Warning: Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Warning: Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Warning: Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Warning: Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Warning: Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Warning: Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Warning: Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Warning: Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_TXD " "Warning: Node \"IRDA_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "IRDA_TXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Warning: Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Warning: Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Warning: Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Warning: Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Warning: Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Warning: Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Warning: Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Warning: Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Warning: Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Warning: Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Warning: Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Warning: Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Warning: Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Warning: Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Warning: Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Warning: Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Warning: Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Warning: Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Warning: Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Warning: Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Warning: Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Warning: Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Warning: Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Warning: Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Warning: Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Warning: Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Warning: Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Warning: Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Warning: Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Warning: Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Warning: Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Warning: Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Warning: Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Warning: Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Warning: Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Warning: Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Warning: Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Warning: Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Warning: Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Warning: Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Warning: Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Warning: Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Warning: Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Warning: Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Warning: Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Warning: Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Warning: Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK0_N " "Warning: Node \"OTG_DACK0_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DACK0_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK1_N " "Warning: Node \"OTG_DACK1_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DACK1_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Warning: Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Warning: Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Warning: Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Warning: Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Warning: Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Warning: Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Warning: Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Warning: Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Warning: Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Warning: Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Warning: Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Warning: Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Warning: Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Warning: Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Warning: Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Warning: Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ0 " "Warning: Node \"OTG_DREQ0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DREQ0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ1 " "Warning: Node \"OTG_DREQ1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_DREQ1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Warning: Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT0 " "Warning: Node \"OTG_INT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_INT0" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT1 " "Warning: Node \"OTG_INT1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_INT1" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Warning: Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Warning: Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Warning: Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Warning: Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Warning: Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Warning: Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Warning: Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Warning: Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT " "Warning: Node \"SD_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_DAT" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT3 " "Warning: Node \"SD_DAT3\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Warning: Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Warning: Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Warning: Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Warning: Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Warning: Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Warning: Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Warning: Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Warning: Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Warning: Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Warning: Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Warning: Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Warning: Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Warning: Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Warning: Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Warning: Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Warning: Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Warning: Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Warning: Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Warning: Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Warning: Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Warning: Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Warning: Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Warning: Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Warning: Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Warning: Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Warning: Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Warning: Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Warning: Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Warning: Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Warning: Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Warning: Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Warning: Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Warning: Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Warning: Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Warning: Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Warning: Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Warning: Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Warning: Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Warning: Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCK " "Warning: Node \"TCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TCK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TCS " "Warning: Node \"TCS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TCS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDI " "Warning: Node \"TDI\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDI" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TDO " "Warning: Node \"TDO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TDO" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Warning: Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Warning: Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Warning: Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Warning: Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Warning: Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Warning: Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Warning: Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Warning: Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Warning: Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET " "Warning: Node \"TD_RESET\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_RESET" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Warning: Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Warning: Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Warning: Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK " "Warning: Node \"VGA_BLANK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_BLANK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Warning: Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Warning: Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Warning: Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Warning: Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Warning: Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Warning: Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Warning: Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Warning: Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[8\] " "Warning: Node \"VGA_B\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[9\] " "Warning: Node \"VGA_B\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_B\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Warning: Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Warning: Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Warning: Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Warning: Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Warning: Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Warning: Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Warning: Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Warning: Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Warning: Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[8\] " "Warning: Node \"VGA_G\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[9\] " "Warning: Node \"VGA_G\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_G\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Warning: Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Warning: Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Warning: Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Warning: Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Warning: Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Warning: Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Warning: Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Warning: Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Warning: Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[8\] " "Warning: Node \"VGA_R\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[8\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[9\] " "Warning: Node \"VGA_R\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_R\[9\]" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC " "Warning: Node \"VGA_SYNC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_SYNC" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Warning: Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} } { } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 1 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 1 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 1 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.616 ns register register " "Info: Estimated most critical path is register to register delay of 2.616 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns _DotCount\[0\] 1 REG LAB_X62_Y20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X62_Y20; Fanout = 4; REG Node = '_DotCount\[0\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { _DotCount[0] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.414 ns) 1.060 ns Add1~109 2 COMB LAB_X61_Y20 2 " "Info: 2: + IC(0.646 ns) + CELL(0.414 ns) = 1.060 ns; Loc. = LAB_X61_Y20; Fanout = 2; COMB Node = 'Add1~109'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.060 ns" { _DotCount[0] Add1~109 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.131 ns Add1~111 3 COMB LAB_X61_Y20 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.131 ns; Loc. = LAB_X61_Y20; Fanout = 2; COMB Node = 'Add1~111'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~109 Add1~111 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.202 ns Add1~113 4 COMB LAB_X61_Y20 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.202 ns; Loc. = LAB_X61_Y20; Fanout = 2; COMB Node = 'Add1~113'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~111 Add1~113 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.273 ns Add1~115 5 COMB LAB_X61_Y20 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.273 ns; Loc. = LAB_X61_Y20; Fanout = 2; COMB Node = 'Add1~115'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~113 Add1~115 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.344 ns Add1~117 6 COMB LAB_X61_Y20 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.344 ns; Loc. = LAB_X61_Y20; Fanout = 2; COMB Node = 'Add1~117'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~115 Add1~117 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.415 ns Add1~119 7 COMB LAB_X61_Y20 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.415 ns; Loc. = LAB_X61_Y20; Fanout = 2; COMB Node = 'Add1~119'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~117 Add1~119 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.486 ns Add1~121 8 COMB LAB_X61_Y20 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.486 ns; Loc. = LAB_X61_Y20; Fanout = 2; COMB Node = 'Add1~121'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~119 Add1~121 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.557 ns Add1~123 9 COMB LAB_X61_Y20 1 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.557 ns; Loc. = LAB_X61_Y20; Fanout = 1; COMB Node = 'Add1~123'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { Add1~121 Add1~123 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.967 ns Add1~124 10 COMB LAB_X61_Y20 1 " "Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 1.967 ns; Loc. = LAB_X61_Y20; Fanout = 1; COMB Node = 'Add1~124'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add1~123 Add1~124 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 161 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 2.532 ns _DotCount~308 11 COMB LAB_X61_Y20 1 " "Info: 11: + IC(0.127 ns) + CELL(0.438 ns) = 2.532 ns; Loc. = LAB_X61_Y20; Fanout = 1; COMB Node = '_DotCount~308'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { Add1~124 _DotCount~308 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 106 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.616 ns _DotCount\[8\] 12 REG LAB_X61_Y20 3 " "Info: 12: + IC(0.000 ns) + CELL(0.084 ns) = 2.616 ns; Loc. = LAB_X61_Y20; Fanout = 3; REG Node = '_DotCount\[8\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { _DotCount~308 _DotCount[8] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.843 ns ( 70.45 % ) " "Info: Total cell delay = 1.843 ns ( 70.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 29.55 % ) " "Info: Total interconnect delay = 0.773 ns ( 29.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.616 ns" { _DotCount[0] Add1~109 Add1~111 Add1~113 Add1~115 Add1~117 Add1~119 Add1~121 Add1~123 Add1~124 _DotCount~308 _DotCount[8] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 1 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 1 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X55_Y12 X65_Y23 " "Info: The peak interconnect region extends from location X55_Y12 to location X65_Y23" { } { } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 1 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 1 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 1 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "26 " "Warning: Found 26 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 1 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "26 " "Warning: Following 26 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently enabled " "Info: Pin GPIO_1\[0\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently enabled " "Info: Pin GPIO_1\[1\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently enabled " "Info: Pin GPIO_1\[2\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently enabled " "Info: Pin GPIO_1\[3\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently enabled " "Info: Pin GPIO_1\[4\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently enabled " "Info: Pin GPIO_1\[5\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently enabled " "Info: Pin GPIO_1\[6\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently enabled " "Info: Pin GPIO_1\[7\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently enabled " "Info: Pin GPIO_1\[8\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently enabled " "Info: Pin GPIO_1\[9\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently enabled " "Info: Pin GPIO_1\[10\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently enabled " "Info: Pin GPIO_1\[11\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently enabled " "Info: Pin GPIO_1\[13\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently enabled " "Info: Pin GPIO_1\[15\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently enabled " "Info: Pin GPIO_1\[17\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently enabled " "Info: Pin GPIO_1\[19\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently enabled " "Info: Pin GPIO_1\[20\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently enabled " "Info: Pin GPIO_1\[21\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently enabled " "Info: Pin GPIO_1\[22\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently enabled " "Info: Pin GPIO_1\[23\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently enabled " "Info: Pin GPIO_1\[24\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently enabled " "Info: Pin GPIO_1\[25\] has a permanently enabled output enable" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! output enable" 0 0 "" 0} } { } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "14 " "Warning: Following 14 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[12\] VCC " "Info: Pin GPIO_1\[12\] has VCC driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[14\] VCC " "Info: Pin GPIO_1\[14\] has VCC driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[16\] VCC " "Info: Pin GPIO_1\[16\] has VCC driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[18\] VCC " "Info: Pin GPIO_1\[18\] has VCC driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[0\] GND " "Info: Pin GPIO_1\[0\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[2\] GND " "Info: Pin GPIO_1\[2\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[4\] GND " "Info: Pin GPIO_1\[4\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[6\] GND " "Info: Pin GPIO_1\[6\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[8\] GND " "Info: Pin GPIO_1\[8\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[10\] GND " "Info: Pin GPIO_1\[10\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[20\] GND " "Info: Pin GPIO_1\[20\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[22\] GND " "Info: Pin GPIO_1\[22\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[23\] VCC " "Info: Pin GPIO_1\[23\] has VCC driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[24\] GND " "Info: Pin GPIO_1\[24\] has GND driving its datain port" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 384 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 384 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "232 " "Info: Allocated 232 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 27 18:30:33 2007 " "Info: Processing ended: Thu Sep 27 18:30:33 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 1 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 27 18:30:34 2007 " "Info: Processing started: Thu Sep 27 18:30:34 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL" { } { } 0 0 "Command: %1!s!" 1 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 1 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 1 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "186 " "Info: Allocated 186 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 27 18:30:47 2007 " "Info: Processing ended: Thu Sep 27 18:30:47 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 1 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 27 18:30:48 2007 " "Info: Processing started: Thu Sep 27 18:30:48 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off swankmania_HDL -c swankmania_HDL --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 1 0 "" 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "_MCK8 " "Info: Detected ripple clock \"_MCK8\" as buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "_MCK8" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "_MCK " "Info: Detected ripple clock \"_MCK\" as buffer" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "_MCK" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 1 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 register _DotCount\[3\] register _HSYNCCount\[10\] 59.559 ns " "Info: Slack time is 59.559 ns for clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" between source register \"_DotCount\[3\]\" and destination register \"_HSYNCCount\[10\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "340.02 MHz 2.941 ns " "Info: Fmax is 340.02 MHz (period= 2.941 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "62.286 ns + Largest register register " "Info: + Largest register to register requirement is 62.286 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "62.500 ns + " "Info: + Setup relationship between source and destination is 62.500 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 60.142 ns " "Info: + Latch edge is 60.142 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 62.500 ns -2.358 ns 50 " "Info: Clock period of Destination clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" is 62.500 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 62.500 ns -2.358 ns 50 " "Info: Clock period of Source clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" is 62.500 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 destination 6.177 ns + Shortest register " "Info: + Shortest clock path from clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" to destination register is 6.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 1 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 1; COMB Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.787 ns) 2.900 ns _MCK8 3 REG LCFF_X1_Y18_N13 2 " "Info: 3: + IC(1.022 ns) + CELL(0.787 ns) = 2.900 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = '_MCK8'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.282 ns) + CELL(0.787 ns) 3.969 ns _MCK 4 REG LCFF_X1_Y18_N19 3 " "Info: 4: + IC(0.282 ns) + CELL(0.787 ns) = 3.969 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 3; REG Node = '_MCK'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { _MCK8 _MCK } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.635 ns) + CELL(0.000 ns) 4.604 ns _MCK~clkctrl 5 COMB CLKCTRL_G1 22 " "Info: 5: + IC(0.635 ns) + CELL(0.000 ns) = 4.604 ns; Loc. = CLKCTRL_G1; Fanout = 22; COMB Node = '_MCK~clkctrl'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.635 ns" { _MCK _MCK~clkctrl } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 6.177 ns _HSYNCCount\[10\] 6 REG LCFF_X63_Y20_N23 2 " "Info: 6: + IC(1.036 ns) + CELL(0.537 ns) = 6.177 ns; Loc. = LCFF_X63_Y20_N23; Fanout = 2; REG Node = '_HSYNCCount\[10\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { _MCK~clkctrl _HSYNCCount[10] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.111 ns ( 34.18 % ) " "Info: Total cell delay = 2.111 ns ( 34.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.066 ns ( 65.82 % ) " "Info: Total interconnect delay = 4.066 ns ( 65.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[10] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 source 6.177 ns - Longest register " "Info: - Longest clock path from clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" to source register is 6.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 1 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 1; COMB Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.787 ns) 2.900 ns _MCK8 3 REG LCFF_X1_Y18_N13 2 " "Info: 3: + IC(1.022 ns) + CELL(0.787 ns) = 2.900 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = '_MCK8'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.282 ns) + CELL(0.787 ns) 3.969 ns _MCK 4 REG LCFF_X1_Y18_N19 3 " "Info: 4: + IC(0.282 ns) + CELL(0.787 ns) = 3.969 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 3; REG Node = '_MCK'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { _MCK8 _MCK } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.635 ns) + CELL(0.000 ns) 4.604 ns _MCK~clkctrl 5 COMB CLKCTRL_G1 22 " "Info: 5: + IC(0.635 ns) + CELL(0.000 ns) = 4.604 ns; Loc. = CLKCTRL_G1; Fanout = 22; COMB Node = '_MCK~clkctrl'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.635 ns" { _MCK _MCK~clkctrl } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 6.177 ns _DotCount\[3\] 6 REG LCFF_X61_Y20_N3 4 " "Info: 6: + IC(1.036 ns) + CELL(0.537 ns) = 6.177 ns; Loc. = LCFF_X61_Y20_N3; Fanout = 4; REG Node = '_DotCount\[3\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { _MCK~clkctrl _DotCount[3] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.111 ns ( 34.18 % ) " "Info: Total cell delay = 2.111 ns ( 34.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.066 ns ( 65.82 % ) " "Info: Total interconnect delay = 4.066 ns ( 65.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _DotCount[3] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _DotCount[3] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[10] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _DotCount[3] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _DotCount[3] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[10] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _DotCount[3] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _DotCount[3] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.727 ns - Longest register register " "Info: - Longest register to register delay is 2.727 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns _DotCount\[3\] 1 REG LCFF_X61_Y20_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y20_N3; Fanout = 4; REG Node = '_DotCount\[3\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { _DotCount[3] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.393 ns) 0.722 ns Equal0~131 2 COMB LCCOMB_X61_Y20_N6 2 " "Info: 2: + IC(0.329 ns) + CELL(0.393 ns) = 0.722 ns; Loc. = LCCOMB_X61_Y20_N6; Fanout = 2; COMB Node = 'Equal0~131'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.722 ns" { _DotCount[3] Equal0~131 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 147 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.275 ns) 1.433 ns Equal0~132 3 COMB LCCOMB_X61_Y20_N4 16 " "Info: 3: + IC(0.436 ns) + CELL(0.275 ns) = 1.433 ns; Loc. = LCCOMB_X61_Y20_N4; Fanout = 16; COMB Node = 'Equal0~132'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.711 ns" { Equal0~131 Equal0~132 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 147 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.660 ns) 2.727 ns _HSYNCCount\[10\] 4 REG LCFF_X63_Y20_N23 2 " "Info: 4: + IC(0.634 ns) + CELL(0.660 ns) = 2.727 ns; Loc. = LCFF_X63_Y20_N23; Fanout = 2; REG Node = '_HSYNCCount\[10\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.294 ns" { Equal0~132 _HSYNCCount[10] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns ( 48.70 % ) " "Info: Total cell delay = 1.328 ns ( 48.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.399 ns ( 51.30 % ) " "Info: Total interconnect delay = 1.399 ns ( 51.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.727 ns" { _DotCount[3] Equal0~131 Equal0~132 _HSYNCCount[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.727 ns" { _DotCount[3] Equal0~131 Equal0~132 _HSYNCCount[10] } { 0.000ns 0.329ns 0.436ns 0.634ns } { 0.000ns 0.393ns 0.275ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[10] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _DotCount[3] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _DotCount[3] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.727 ns" { _DotCount[3] Equal0~131 Equal0~132 _HSYNCCount[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.727 ns" { _DotCount[3] Equal0~131 Equal0~132 _HSYNCCount[10] } { 0.000ns 0.329ns 0.436ns 0.634ns } { 0.000ns 0.393ns 0.275ns 0.660ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 1 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLOCK_50 " "Info: No valid register-to-register data paths exist for clock \"CLOCK_50\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 1 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 register _MCK8 register _MCK8 391 ps " "Info: Minimum slack time is 391 ps for clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" between source register \"_MCK8\" and destination register \"_MCK8\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns _MCK8 1 REG LCFF_X1_Y18_N13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = '_MCK8'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { _MCK8 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns _MCK8~2 2 COMB LCCOMB_X1_Y18_N12 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X1_Y18_N12; Fanout = 1; COMB Node = '_MCK8~2'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.323 ns" { _MCK8 _MCK8~2 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns _MCK8 3 REG LCFF_X1_Y18_N13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = '_MCK8'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { _MCK8~2 _MCK8 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { _MCK8 _MCK8~2 _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "0.407 ns" { _MCK8 _MCK8~2 _MCK8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.358 ns " "Info: + Latch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 62.500 ns -2.358 ns 50 " "Info: Clock period of Destination clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" is 62.500 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 62.500 ns -2.358 ns 50 " "Info: Clock period of Source clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" is 62.500 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 destination 2.650 ns + Longest register " "Info: + Longest clock path from clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" to destination register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 1 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 1; COMB Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns _MCK8 3 REG LCFF_X1_Y18_N13 2 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = '_MCK8'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 source 2.650 ns - Shortest register " "Info: - Shortest clock path from clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" to source register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 1 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 1; COMB Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns _MCK8 3 REG LCFF_X1_Y18_N13 2 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = '_MCK8'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { _MCK8 _MCK8~2 _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "0.407 ns" { _MCK8 _MCK8~2 _MCK8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 1 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 GPIO_1\[17\] _HSYNCCount\[4\] 10.095 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"GPIO_1\[17\]\" through register \"_HSYNCCount\[4\]\" is 10.095 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLOCK_50 PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 -2.358 ns + " "Info: + Offset between input clock \"CLOCK_50\" and output clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" is -2.358 ns" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 12 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 source 6.177 ns + Longest register " "Info: + Longest clock path from clock \"PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0\" to source register is 6.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 1 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 1; COMB Node = 'PLL_16:PLL_16_0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/71sp1/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.787 ns) 2.900 ns _MCK8 3 REG LCFF_X1_Y18_N13 2 " "Info: 3: + IC(1.022 ns) + CELL(0.787 ns) = 2.900 ns; Loc. = LCFF_X1_Y18_N13; Fanout = 2; REG Node = '_MCK8'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 80 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.282 ns) + CELL(0.787 ns) 3.969 ns _MCK 4 REG LCFF_X1_Y18_N19 3 " "Info: 4: + IC(0.282 ns) + CELL(0.787 ns) = 3.969 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 3; REG Node = '_MCK'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { _MCK8 _MCK } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.635 ns) + CELL(0.000 ns) 4.604 ns _MCK~clkctrl 5 COMB CLKCTRL_G1 22 " "Info: 5: + IC(0.635 ns) + CELL(0.000 ns) = 4.604 ns; Loc. = CLKCTRL_G1; Fanout = 22; COMB Node = '_MCK~clkctrl'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.635 ns" { _MCK _MCK~clkctrl } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.537 ns) 6.177 ns _HSYNCCount\[4\] 6 REG LCFF_X63_Y20_N11 4 " "Info: 6: + IC(1.036 ns) + CELL(0.537 ns) = 6.177 ns; Loc. = LCFF_X63_Y20_N11; Fanout = 4; REG Node = '_HSYNCCount\[4\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { _MCK~clkctrl _HSYNCCount[4] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.111 ns ( 34.18 % ) " "Info: Total cell delay = 2.111 ns ( 34.18 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.066 ns ( 65.82 % ) " "Info: Total interconnect delay = 4.066 ns ( 65.82 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[4] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[4] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.026 ns + Longest register pin " "Info: + Longest register to pin delay is 6.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns _HSYNCCount\[4\] 1 REG LCFF_X63_Y20_N11 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y20_N11; Fanout = 4; REG Node = '_HSYNCCount\[4\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { _HSYNCCount[4] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 144 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.376 ns) 0.903 ns Equal1~110 2 COMB LCCOMB_X62_Y20_N24 2 " "Info: 2: + IC(0.527 ns) + CELL(0.376 ns) = 0.903 ns; Loc. = LCCOMB_X62_Y20_N24; Fanout = 2; COMB Node = 'Equal1~110'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.903 ns" { _HSYNCCount[4] Equal1~110 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(0.438 ns) 1.615 ns LessThan4~210 3 COMB LCCOMB_X62_Y20_N28 9 " "Info: 3: + IC(0.274 ns) + CELL(0.438 ns) = 1.615 ns; Loc. = LCCOMB_X62_Y20_N28; Fanout = 9; COMB Node = 'LessThan4~210'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.712 ns" { Equal1~110 LessThan4~210 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 193 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.150 ns) 2.445 ns RGB\[0\]~287 4 COMB LCCOMB_X64_Y20_N16 1 " "Info: 4: + IC(0.680 ns) + CELL(0.150 ns) = 2.445 ns; Loc. = LCCOMB_X64_Y20_N16; Fanout = 1; COMB Node = 'RGB\[0\]~287'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { LessThan4~210 RGB[0]~287 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(2.632 ns) 6.026 ns GPIO_1\[17\] 5 PIN PIN_T24 0 " "Info: 5: + IC(0.949 ns) + CELL(2.632 ns) = 6.026 ns; Loc. = PIN_T24; Fanout = 0; PIN Node = 'GPIO_1\[17\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.581 ns" { RGB[0]~287 GPIO_1[17] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.596 ns ( 59.67 % ) " "Info: Total cell delay = 3.596 ns ( 59.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.430 ns ( 40.33 % ) " "Info: Total interconnect delay = 2.430 ns ( 40.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.026 ns" { _HSYNCCount[4] Equal1~110 LessThan4~210 RGB[0]~287 GPIO_1[17] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.026 ns" { _HSYNCCount[4] Equal1~110 LessThan4~210 RGB[0]~287 GPIO_1[17] } { 0.000ns 0.527ns 0.274ns 0.680ns 0.949ns } { 0.000ns 0.376ns 0.438ns 0.150ns 2.632ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[4] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.177 ns" { PLL_16:PLL_16_0|altpll:altpll_component|_clk0 PLL_16:PLL_16_0|altpll:altpll_component|_clk0~clkctrl _MCK8 _MCK _MCK~clkctrl _HSYNCCount[4] } { 0.000ns 1.091ns 1.022ns 0.282ns 0.635ns 1.036ns } { 0.000ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "6.026 ns" { _HSYNCCount[4] Equal1~110 LessThan4~210 RGB[0]~287 GPIO_1[17] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "6.026 ns" { _HSYNCCount[4] Equal1~110 LessThan4~210 RGB[0]~287 GPIO_1[17] } { 0.000ns 0.527ns 0.274ns 0.680ns 0.949ns } { 0.000ns 0.376ns 0.438ns 0.150ns 2.632ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 1 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[5\] GPIO_1\[7\] 7.303 ns Longest " "Info: Longest tpd from source pin \"SW\[5\]\" to destination pin \"GPIO_1\[7\]\" is 7.303 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns SW\[5\] 1 PIN PIN_AD13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AD13; Fanout = 1; PIN Node = 'SW\[5\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.328 ns) + CELL(0.438 ns) 3.755 ns RGB\[5\]~282 2 COMB LCCOMB_X62_Y20_N12 1 " "Info: 2: + IC(2.328 ns) + CELL(0.438 ns) = 3.755 ns; Loc. = LCCOMB_X62_Y20_N12; Fanout = 1; COMB Node = 'RGB\[5\]~282'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "2.766 ns" { SW[5] RGB[5]~282 } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.936 ns) + CELL(2.612 ns) 7.303 ns GPIO_1\[7\] 3 PIN PIN_M21 0 " "Info: 3: + IC(0.936 ns) + CELL(2.612 ns) = 7.303 ns; Loc. = PIN_M21; Fanout = 0; PIN Node = 'GPIO_1\[7\]'" { } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "3.548 ns" { RGB[5]~282 GPIO_1[7] } "NODE_NAME" } } { "HDL_Source/swankmania_HDL.v" "" { Text "C:/user/swankmania/swankmania_HDL/HDL_Source/swankmania_HDL.v" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.039 ns ( 55.31 % ) " "Info: Total cell delay = 4.039 ns ( 55.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.264 ns ( 44.69 % ) " "Info: Total interconnect delay = 3.264 ns ( 44.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "7.303 ns" { SW[5] RGB[5]~282 GPIO_1[7] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71sp1/quartus/bin/Technology_Viewer.qrui" "7.303 ns" { SW[5] SW[5]~combout RGB[5]~282 GPIO_1[7] } { 0.000ns 0.000ns 2.328ns 0.936ns } { 0.000ns 0.989ns 0.438ns 2.612ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 1 0 "" 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 1 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 27 18:30:49 2007 " "Info: Processing ended: Thu Sep 27 18:30:49 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 1 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 461 s " "Info: Quartus II Full Compilation was successful. 0 errors, 461 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 1 0 "" 0}