-
Notifications
You must be signed in to change notification settings - Fork 1
yapm ISA
Parallel machine is based on VLIW architecture. Some key aspects:
- Memory is direct addressed. Available address space is 0 .. 2^16
- Register space is 256 wide
- 4 asymmetric execution units:
- Units 0 and 1: operations with memory(ld/st) and control operations(call)
- Units 2 and 3: basic arithmetic(add, sub, etc.)
- Each operation costs 1 cycle, no memory latency.
- All data has tags. Tags are used to determine data types(int/float/address) and allowed of operations on them.
Machine executes 1 macrooperation per cycle. Each macrooperation consists of 4 operations - 1 operation per execution unit. So all execution is statically planned by compiler. If some execution unit on some cycle has no command to execute than macrooperation should have "NOP" operation in corresponding slot.
TBD
To simplify joint development of binary translator and interpretor assembler has following syntax:
- Operations inside macrooperations are separated by semicolon. At the end of each macrooperation should be caret return. EOL is delimiter of macrooperations.
- Integer constants size is 1 byte(short int), floating point - 2 bytes(half-precision float), address constant - 2 bytes(unsigned word).
LDC 2, r0; NOP; NOP; NOP; ST r0, 0; NOP; NOP; NOP;
Instructions in this group are executed on units 0 and 1.
LDC - load constant to register
ldc <const>, <dest_reg>
LD - load value from memory to register
ld <addr>, <dest_reg>
ST - store value from register to memory
st <src_reg>, <addr>
LDA - load value from memory at dynamic address to register
lda <base_reg>, <index_reg>, <dest_reg>
STA - store value from register to memory by dynamic address
sta <base_reg>, <index_reg>, <src_reg>
Instructions in this group are executed on units 0 and 1.
CALL - make call of hard-coded function
call <index>
Instructions in this group are executed on units 2 and 3.
ADD , SUB , MUL , DIV , REM , CHSGN