From a7b7b9f9e41ec8361602d06f34b140cedeafa7da Mon Sep 17 00:00:00 2001 From: Christophe Gerbier Date: Sun, 31 Dec 2017 14:01:44 +0100 Subject: [PATCH 1/4] PWM first draft Initial commit Signed-off-by: Christophe Gerbier --- CMake/Modules/FindWindows.Devices.Pwm.cmake | 9 +-- .../ChibiOS/MBN_QUAIL/nanoCLR/mcuconf.h | 12 ++-- .../ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h | 14 ++-- .../win_dev_pwm_native.cpp | 68 +++++++++++++++--- .../Windows.Devices.Pwm/win_dev_pwm_native.h | 71 +++++++++++++++---- ...m_native_Windows_Devices_PWM_PwmDevice.cpp | 37 ---------- 6 files changed, 136 insertions(+), 75 deletions(-) delete mode 100644 targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_PWM_PwmDevice.cpp diff --git a/CMake/Modules/FindWindows.Devices.Pwm.cmake b/CMake/Modules/FindWindows.Devices.Pwm.cmake index 9512bef60b..3cd5c550e8 100644 --- a/CMake/Modules/FindWindows.Devices.Pwm.cmake +++ b/CMake/Modules/FindWindows.Devices.Pwm.cmake @@ -4,7 +4,7 @@ # # native code directory -set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Devices.Pwm") +set(BASE_PATH_FOR_THIS_MODULE "targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm") # set include directories @@ -12,7 +12,7 @@ list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Core list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Include") list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/HAL/Include") list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/PAL/Include") -list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS "${BASE_PATH_FOR_THIS_MODULE}") +list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/${BASE_PATH_FOR_THIS_MODULE}") # source files @@ -20,14 +20,15 @@ set(Windows.Devices.Pwm_SRCS win_dev_pwm_native.cpp win_dev_pwm_native.h - win_dev_pwm_native_Windows_Devices_PWM_PwmDevice.cpp + win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp + win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp ) foreach(SRC_FILE ${Windows.Devices.Pwm_SRCS}) set(Windows.Devices.Pwm_SRC_FILE SRC_FILE-NOTFOUND) find_file(Windows.Devices.Pwm_SRC_FILE ${SRC_FILE} PATHS - "${BASE_PATH_FOR_THIS_MODULE}" + ${PROJECT_SOURCE_DIR}/${BASE_PATH_FOR_THIS_MODULE} CMAKE_FIND_ROOT_PATH_BOTH ) diff --git a/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf.h index 13fecdf670..03424eaa99 100644 --- a/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf.h @@ -115,7 +115,7 @@ * GPT driver system settings. */ #define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM2 TRUE #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE @@ -207,14 +207,14 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_ADVANCED TRUE #define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM3 TRUE #define STM32_PWM_USE_TIM4 TRUE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h index 4bd5d04b13..fe74e7e432 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h @@ -207,14 +207,14 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.cpp index 547e9d762b..1ca24220b9 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.cpp @@ -1,8 +1,60 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - - -#include "win_dev_pwm_native.h" - +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_pwm_native.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFrequency___R8, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MinFrequency___R8, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCount___I4, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetDesiredFrequency___U4__U4, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetActiveDutyCyclePercentage___VOID__U4, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetPolarity___VOID__U1, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStart___VOID, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStop___VOID, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::DisposeNative___VOID, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Pwm = +{ + "Windows.Devices.Pwm", + 0xA5DBEB86, + method_lookup +}; diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.h b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.h index 81611ed0f3..3d2f0e968d 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.h +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.h @@ -1,13 +1,58 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - - -#ifndef _WIN_DEV_PWM_NATIVE_H_ -#define _WIN_DEV_PWM_NATIVE_H_ - -#include -#include -#include -#include \ No newline at end of file +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_PWM_NATIVE_H_ +#define _WIN_DEV_PWM_NATIVE_H_ + +#include +#include +#include +#include + +struct Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController +{ + static const int FIELD___deviceId = 1; + static const int FIELD___actualFrequency = 2; + static const int FIELD___pwmTimer = 3; + + NANOCLR_NATIVE_DECLARE(get_MaxFrequency___R8); + NANOCLR_NATIVE_DECLARE(get_MinFrequency___R8); + NANOCLR_NATIVE_DECLARE(get_PinCount___I4); + NANOCLR_NATIVE_DECLARE(NativeSetDesiredFrequency___U4__U4); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin +{ + static const int FIELD___syncLock = 1; + static const int FIELD___pwmController = 2; + static const int FIELD___polarity = 3; + static const int FIELD___dutyCyclePercentage = 4; + static const int FIELD___dutyCycle = 5; + static const int FIELD___pinNumber = 6; + static const int FIELD___pwmTimer = 7; + static const int FIELD___isStarted = 8; + static const int FIELD___disposedValue = 9; + + NANOCLR_NATIVE_DECLARE(NativeSetActiveDutyCyclePercentage___VOID__U4); + NANOCLR_NATIVE_DECLARE(NativeSetPolarity___VOID__U1); + NANOCLR_NATIVE_DECLARE(NativeStart___VOID); + NANOCLR_NATIVE_DECLARE(NativeStop___VOID); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + + //--// + + static int GetChannel (int pin, int timerId); + static int GetAlternateFunction (int timerId); + static PWMDriver * GetDriver(int timerId); + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Pwm; + +#endif //_WIN_DEV_PWM_NATIVE_H_ diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_PWM_PwmDevice.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_PWM_PwmDevice.cpp deleted file mode 100644 index 09460fe00c..0000000000 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_PWM_PwmDevice.cpp +++ /dev/null @@ -1,37 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - - -#include -#include -#include -#include -#include - -#include "win_dev_pwm_native.h" - -/////////////////////////////////////////////////////////////////////////////////////// -// !!! KEEP IN SYNC WITH Windows.Devices.I2c.I2cSharingMode (in managed code) !!! // -/////////////////////////////////////////////////////////////////////////////////////// -enum PwmPulsePolarity - { - ActiveHigh, - ActiveLow - }; - - - - -HRESULT Library_win_dev_pwm_native_Windows_Devices_PWM_PwmDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) -{ - NANOCLR_HEADER(); - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_win_dev_pwm_native_Windows_Devices_PWM_PwmDevice::DisposeNative___VOID( CLR_RT_StackFrame& stack ) -{ - NANOCLR_HEADER(); - NANOCLR_NOCLEANUP(); -} \ No newline at end of file From c5d8b7355ac1f53e7fdccca1fa256b6667fba47a Mon Sep 17 00:00:00 2001 From: Christophe Gerbier Date: Sun, 31 Dec 2017 14:03:54 +0100 Subject: [PATCH 2/4] Add missing files Mising files --- ...tive_Windows_Devices_Pwm_PwmController.cpp | 151 +++++++ ..._pwm_native_Windows_Devices_Pwm_PwmPin.cpp | 422 ++++++++++++++++++ 2 files changed, 573 insertions(+) create mode 100644 targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp create mode 100644 targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp new file mode 100644 index 0000000000..7c4ac5ba57 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp @@ -0,0 +1,151 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include "win_dev_pwm_native.h" + +PWMConfig _pwmConfig; + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int timerId = (int)(pThis[ FIELD___deviceId ].NumericByRef().u4); + double maxFrequency = 0.0; + +#if defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF) + if (timerId == 1 || timerId >= 8) maxFrequency = (double)STM32_PCLK2_MAX; // TIM1, TIM8 and TIM9 on APB2 + else maxFrequency = (double)STM32_PCLK1_MAX; // other timers on APB1 +#elif defined(STM32F0xx_MCUCONF) + maxFrequency = (double)STM32_PCLK1_MAX; // Only APB1 on this MCU +#endif + stack.SetResult_R8(maxFrequency); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MinFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // FIXME : how can this value be determined ? + stack.SetResult_R8(1.0); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int pinCount = 0; +#if defined(STM32F4xx_MCUCONF) + pinCount = 42; +#elif defined(STM32F7xx_MCUCONF) + //FIXME: arbitrary value, here. Where do I find the information ? + pinCount = 42; +#elif defined(STM32F0xx_MCUCONF) + pinCount = 24; +#endif + stack.SetResult_I4(pinCount); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetDesiredFrequency___U4__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int timerId = (int)(pThis[ FIELD___deviceId ].NumericByRef().u4); + unsigned int desiredFrequency = (unsigned int)stack.Arg1().NumericByRef().u4; + + // Gets the PWM driver associated with the requested timer + PWMDriver * _drv; + _drv = Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::GetDriver(timerId); + + // Sets the period to something able to be precise enough with low and high frequencies + // and that allows the clock frequency parameter to fit in an unsigned int + int period = 1000; + if (desiredFrequency >= 1000) period = 100; + else if (desiredFrequency >= 1000000) period = 10; + + // Build the PWM config structure + PWMConfig pwmConfig = + { + desiredFrequency*period, // PWM clock frequency + period, // PWM period + NULL, // No callback + // Enable all channels + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_LOW, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} + }, + 0, + 0 + }; + + // Starts the pwm driver + pwmStop(_drv); + osDelay(5); + pwmStart(_drv, &pwmConfig); + + stack.SetResult_R8((double)desiredFrequency); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "TIM1,TIM3,TIM4,TIM5,TIM8,TIM9," + terminator and init with the terminator + char deviceSelectorString[ 30 + 1] = { 0 }; + + #if STM32_PWM_USE_TIM1 + strcat(deviceSelectorString, "TIM1,"); + #endif + #if STM32_PWM_USE_TIM2 + strcat(deviceSelectorString, "TIM2,"); + #endif + #if STM32_PWM_USE_TIM3 + strcat(deviceSelectorString, "TIM3,"); + #endif +#ifndef STM32F0xx_MCUCONF + #if STM32_PWM_USE_TIM4 + strcat(deviceSelectorString, "TIM4,"); + #endif + #if STM32_PWM_USE_TIM5 + strcat(deviceSelectorString, "TIM5,"); + #endif + #if STM32_PWM_USE_TIM8 + strcat(deviceSelectorString, "TIM8,"); + #endif + #if STM32_PWM_USE_TIM9 + strcat(deviceSelectorString, "TIM9,"); + #endif +#endif + // replace the last comma with a terminator + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP(); +} diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp new file mode 100644 index 0000000000..2e5d41a840 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp @@ -0,0 +1,422 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include "win_dev_pwm_native.h" +#include + + +int Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::GetChannel (int pin, int timerId) +{ + int channel = 0; +#if defined(STM32F427xx) || defined(STM32F429xx) + switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8 + case 4*16+9 : // PE9 + channel = 0; + break; + case 9 : // PA9 + case 4*16+11 : // PE11 + channel = 1; + break; + case 10 : // PA10 + case 4*16+13 : // PE13 + channel = 2; + break; + case 11 : // PA11 + case 4*16+14 : // PE14 + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1 * 16 + 3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1 * 16 + 10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1 * 16 + 11 : + channel = 3; + break; + } + break; + + case 3 : + switch (pin) + { + case 0 : + case 5 : + case 15 : + channel = 0; + break; + case 1 : + case 1*16+3 : + channel = 1; + break; + case 2 : + case 1*16+10 : + channel = 2; + break; + case 3 : + case 1*16+11 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1 * 16 + 6 : // PB6, PD12 + case 3 * 16 + 12 : + channel = 0; + break; + case 1 * 16 + 7 : // PB7, PD13 + case 3 * 16 + 13 : + channel = 1; + break; + case 1 * 16 + 8 : // PB8, PD14 + case 3 * 16 + 14 : + channel = 2; + break; + case 1 * 16 + 9 : // PB9, PD15 + case 3 * 16 + 15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0, PH10 + case 7 * 16 + 10 : + channel = 0; + break; + case 1 : // PA1, PH11 + case 7 * 16 + 11 : + channel = 1; + break; + case 2 : // PA2, PH12 + case 7 * 16 + 12 : + channel = 2; + break; + case 3 : // PA3, PI0 + case 8 * 16 + 0 : + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2 * 16 + 6 : // PC6, PI5 + case 7 * 16 + 5 : + channel = 0; + break; + case 2 * 16 + 7 : // PC7, PI6 + case 7 * 16 + 6 : + channel = 1; + break; + case 2 * 16 + 8 : // PC8, PI7 + case 7 * 16 + 7 : + channel = 2; + break; + case 2 * 16 + 9 : // PC9 + channel = 3; + break; + } + break; + + case 9 : + switch (pin) + { + case 2 * 16 + 6 : // PC6, PI5 + case 7 * 16 + 5 : + channel = 0; + break; + case 2 * 16 + 7 : // PC7, PI6 + case 7 * 16 + 6 : + channel = 1; + break; + case 2 * 16 + 8 : // PC8, PI7 + case 7 * 16 + 7 : + channel = 2; + break; + case 2 * 16 + 9 : // PC9 + channel = 3; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#elif defined(STM32F411xx) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8 + channel = 0; + break; + case 9 : // PA9 + channel = 1; + break; + case 10 : // PA10 + channel = 2; + break; + case 11 : // PA11 + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1 * 16 + 3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1 * 16 + 10 : + channel = 2; + break; + case 3 : // PA3 + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4 + case 1 * 16 + 4 : + channel = 0; + break; + case 7 : // PA7, PB5 + case 1 * 16 + 5 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0 + channel = 2; + break; + case 1 * 16 + 1 : // PB1 + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1 * 16 + 6 : // PB6 + channel = 0; + break; + case 1 * 16 + 7 : // PB7 + channel = 1; + break; + case 1 * 16 + 8 : // PB8 + channel = 2; + break; + case 1 * 16 + 9 : // PB9 + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0 + channel = 0; + break; + case 1 : // PA1 + channel = 1; + break; + case 2 : // PA2 + channel = 2; + break; + case 3 : // PA3 + channel = 3; + break; + } + break; + + case 9 : + switch (pin) + { + case 2 : // PA2 + channel = 0; + break; + case 3 : // PA3 + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif + return channel; +} + +int Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::GetAlternateFunction (int timerId) +{ + if (timerId >= 8) return 3; + if (timerId >= 3) return 2; + return 1; +} + +PWMDriver * Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::GetDriver(int timerId) +{ + PWMDriver * _drv; + + switch (timerId) + { +#if STM32_PWM_USE_TIM1 + case 1 : _drv = &PWMD1; + break; +#endif +#if STM32_PWM_USE_TIM2 + case 2 : _drv = &PWMD2; + break; +#endif +#if STM32_PWM_USE_TIM3 + case 3 : _drv = &PWMD3; + break; +#endif +#if STM32_PWM_USE_TIM4 + case 4 : _drv = &PWMD4; + break; +#endif +#if STM32_PWM_USE_TIM5 + case 5 : _drv = &PWMD5; + break; +#endif +#if STM32_PWM_USE_TIM8 + case 8 : _drv = &PWMD8; + break; +#endif +#if STM32_PWM_USE_TIM9 + case 9 : _drv = &PWMD9; + break; +#endif + } + + return _drv; +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetActiveDutyCyclePercentage___VOID__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + PWMDriver * _drv; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + unsigned int dutyCycle = (unsigned int)stack.Arg1().NumericByRef().u4; + + // Gets the PWM driver associated with the requested timer + _drv = GetDriver(timerId); + + // Enables the channel associated with the selected pin on that timer + pwmEnableChannel(_drv, GetChannel(pinNumber, timerId),PWM_PERCENTAGE_TO_WIDTH(_drv, dutyCycle)); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetPolarity___VOID__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStart___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + PWMDriver * _drv; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + unsigned int dutyCycle = (int)(pThis[ FIELD___dutyCycle ].NumericByRef().u4); + + // Gets the PWM driver associated with the requested timer + _drv = GetDriver(timerId); + + // Sets the pin to the correct pwm alternate functin and enables the associated channel + palSetPadMode(GPIO_PORT(pinNumber), pinNumber % 16, PAL_MODE_ALTERNATE(GetAlternateFunction(timerId))); + pwmEnableChannel(_drv, GetChannel(pinNumber, timerId),PWM_PERCENTAGE_TO_WIDTH(_drv, dutyCycle)); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStop___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // Stops pwm output on the channel associated with the selected pin + pwmDisableChannel(GetDriver(timerId), GetChannel(pinNumber, timerId)); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} From 20801a9385c8884a1ebd3c90b736d68e3427dba3 Mon Sep 17 00:00:00 2001 From: Christophe Gerbier Date: Sun, 31 Dec 2017 14:15:16 +0100 Subject: [PATCH 3/4] Update win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp Forgot to remove the PWM_OUTPUT_ACTIVE_LOW test... --- .../win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp index 7c4ac5ba57..a58a653234 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp @@ -92,7 +92,7 @@ HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetD // Enable all channels { {PWM_OUTPUT_ACTIVE_HIGH, NULL}, - {PWM_OUTPUT_ACTIVE_LOW, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, {PWM_OUTPUT_ACTIVE_HIGH, NULL}, {PWM_OUTPUT_ACTIVE_HIGH, NULL} }, From f7bfdf78a1a1bddb823c905f3587b67ef08310e2 Mon Sep 17 00:00:00 2001 From: Christophe Gerbier Date: Sun, 31 Dec 2017 18:40:37 +0100 Subject: [PATCH 4/4] Add new MCU for PWM Added support for F746xx, F769xx and F091xxC. Signed-off-by: Christophe Gerbier --- .../ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h | 14 +- .../ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h | 6 +- .../ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h | 14 +- ...tive_Windows_Devices_Pwm_PwmController.cpp | 2 +- ..._pwm_native_Windows_Devices_Pwm_PwmPin.cpp | 378 +++++++++++++++++- 5 files changed, 395 insertions(+), 19 deletions(-) diff --git a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h index f15910f965..1eb52832a4 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h @@ -227,14 +227,14 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 diff --git a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h index 06cfa0d130..eeb497eed2 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h @@ -128,10 +128,10 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM3 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 3 #define STM32_PWM_TIM2_IRQ_PRIORITY 3 #define STM32_PWM_TIM3_IRQ_PRIORITY 3 diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h index bb4cdabd29..9657a62132 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h @@ -229,14 +229,14 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp index a58a653234..8866ba8b96 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp @@ -27,7 +27,7 @@ HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFre if (timerId == 1 || timerId >= 8) maxFrequency = (double)STM32_PCLK2_MAX; // TIM1, TIM8 and TIM9 on APB2 else maxFrequency = (double)STM32_PCLK1_MAX; // other timers on APB1 #elif defined(STM32F0xx_MCUCONF) - maxFrequency = (double)STM32_PCLK1_MAX; // Only APB1 on this MCU + maxFrequency = (double)STM32_PCLK_MAX; // Only APB1 on this MCU #endif stack.SetResult_R8(maxFrequency); } diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp index 2e5d41a840..bf92af09c3 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp @@ -174,7 +174,8 @@ int Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::GetChannel (int pin, channel = 0xFF; break; } -#elif defined(STM32F411xx) +#endif +#if defined(STM32F411xx) switch (timerId) { case 1 : @@ -287,6 +288,381 @@ switch (timerId) channel = 0xFF; break; } +#endif +#if defined(STM32F746xx) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8, PE9 + case 4*16+9 : + channel = 0; + break; + case 9 : // PA9, PE11 + case 4*16+11 : + channel = 1; + break; + case 10 : // PA10, PE13 + case 4*16+13 : + channel = 2; + break; + case 11 : // PA11, PE14 + case 4*16+14 : + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1*16+6 : // PB6, PD12 + case 3*16+12 : + channel = 0; + break; + case 1*16+7 : // PB7, PD13 + case 3*16+13 : + channel = 1; + break; + case 1*16+8 : // PB8, PD14 + case 3*16+14 : + channel = 2; + break; + case 1*16+9 : // PB9, PD15 + case 3*16+15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0 + channel = 0; + break; + case 1 : // PA1 + channel = 1; + break; + case 2 : // PA2 + channel = 2; + break; + case 3 : // PA3 + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2*16+6 : // PC6 + channel = 0; + break; + case 2*16+7 : // PC7 + channel = 1; + break; + case 2*16+8 : // PC8 + channel = 2; + break; + case 2*16+9 : // PC9 + channel = 3; + break; + } + break; + + + case 9 : + switch (pin) + { + case 2 : // PA2, PE5 + case 4*16+5 : + channel = 0; + break; + case 3 : // PA3, PE6 + case 4*16+6 : + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F769xx) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8, PE9 + case 4*16+9 : + channel = 0; + break; + case 9 : // PA9, PE11 + case 4*16+11 : + channel = 1; + break; + case 10 : // PA10, PE13 + case 4*16+13 : + channel = 2; + break; + case 11 : // PA11, PE14 + case 4*16+14 : + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1*16+6 : // PB6, PD12 + case 3*16+12 : + channel = 0; + break; + case 1*16+7 : // PB7, PD13 + case 3*16+13 : + channel = 1; + break; + case 1*16+8 : // PB8, PD14 + case 3*16+14 : + channel = 2; + break; + case 1*16+9 : // PB9, PD15 + case 3*16+15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0, PH10 + case 7*16+10 : + channel = 0; + break; + case 1 : // PA1, PH11 + case 7*16+11 : + channel = 1; + break; + case 2 : // PA2, PH12 + case 7*16+12 : + channel = 2; + break; + case 3 : // PA3, PI0 + case 8*16+0 : + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2*16+6 : // PC6, PI5 + case 8*16+5 : + channel = 0; + break; + case 2*16+7 : // PC7, PI6 + case 8*16+6 : + channel = 1; + break; + case 2*16+8 : // PC8, PI7 + case 8*16+7 : + channel = 2; + break; + case 2*16+9 : // PC9, PI2 + case 8*16+2 : + channel = 3; + break; + } + break; + + + case 9 : + switch (pin) + { + case 2 : // PA2, PE5 + case 4*16+5 : + channel = 0; + break; + case 3 : // PA3, PE6 + case 4*16+6 : + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F091xC) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8 + channel = 0; + break; + case 9 : // PA9 + channel = 1; + break; + case 10 : // PA10 + channel = 2; + break; + case 11 : // PA11 + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + default : + channel = 0xFF; + break; + } #endif return channel; }