From 0cbfaa8ecaea433de9792c8143ce28e9bc43fe4b Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 20 Jun 2021 20:08:00 +0100 Subject: [PATCH 01/15] Update chconf.h files --- .../NETDUINO3_WIFI/nanoBooter/chconf.h | 158 ++++++++++++------ .../ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h | 156 +++++++++++------ .../ORGPAL_PALTHREE/nanoBooter/chconf.h | 156 +++++++++++------ .../ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h | 156 +++++++++++------ .../ST_NUCLEO64_F091RC/nanoBooter/chconf.h | 156 +++++++++++------ .../ST_NUCLEO64_F091RC/nanoCLR/chconf.h | 70 +++++++- .../nanoBooter/chconf.h | 70 +++++++- .../ST_STM32F429I_DISCOVERY/nanoCLR/chconf.h | 70 +++++++- .../nanoBooter/chconf.h | 70 +++++++- .../ST_STM32F769I_DISCOVERY/nanoCLR/chconf.h | 70 +++++++- 10 files changed, 851 insertions(+), 281 deletions(-) diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h index 176709dd8f..232dd00ae4 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -127,7 +147,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_OPTIMIZE_SPEED) -#define CH_CFG_OPTIMIZE_SPEED FALSE +#define CH_CFG_OPTIMIZE_SPEED TRUE #endif /** @} */ @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -620,23 +651,40 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -644,45 +692,47 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) \ - { \ - /* Add threads finalization code here.*/ \ - } +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ - { \ - /* Context switch code here.*/ \ - } +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() \ - { \ - /* IRQ prologue code here.*/ \ - } +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() \ - { \ - /* IRQ epilogue code here.*/ \ - } +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /** * @brief Idle thread enter hook. @@ -690,10 +740,9 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() \ - { \ - /* Idle-enter code here.*/ \ - } +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} /** * @brief Idle thread leave hook. @@ -701,49 +750,52 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() \ - { \ - /* Idle-leave code here.*/ \ - } +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() \ - { \ - /* Idle loop code here.*/ \ - } +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() \ - { \ - /* System tick event code here.*/ \ - } +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ - { \ - /* System halt code here.*/ \ - } +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) \ - { \ - /* Trace code here.*/ \ - } +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} /** @} */ diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h index f9cb68581c..c52486ac50 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -620,23 +651,40 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -644,45 +692,47 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) \ - { \ - /* Add threads finalization code here.*/ \ - } +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ - { \ - /* Context switch code here.*/ \ - } +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() \ - { \ - /* IRQ prologue code here.*/ \ - } +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() \ - { \ - /* IRQ epilogue code here.*/ \ - } +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /** * @brief Idle thread enter hook. @@ -690,10 +740,9 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() \ - { \ - /* Idle-enter code here.*/ \ - } +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} /** * @brief Idle thread leave hook. @@ -701,49 +750,52 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() \ - { \ - /* Idle-leave code here.*/ \ - } +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() \ - { \ - /* Idle loop code here.*/ \ - } +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() \ - { \ - /* System tick event code here.*/ \ - } +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ - { \ - /* System halt code here.*/ \ - } +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) \ - { \ - /* Trace code here.*/ \ - } +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} /** @} */ diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/chconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/chconf.h index 0afc022706..232dd00ae4 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/chconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -620,23 +651,40 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -644,45 +692,47 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) \ - { \ - /* Add threads finalization code here.*/ \ - } +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ - { \ - /* Context switch code here.*/ \ - } +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() \ - { \ - /* IRQ prologue code here.*/ \ - } +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() \ - { \ - /* IRQ epilogue code here.*/ \ - } +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /** * @brief Idle thread enter hook. @@ -690,10 +740,9 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() \ - { \ - /* Idle-enter code here.*/ \ - } +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} /** * @brief Idle thread leave hook. @@ -701,49 +750,52 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() \ - { \ - /* Idle-leave code here.*/ \ - } +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() \ - { \ - /* Idle loop code here.*/ \ - } +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() \ - { \ - /* System tick event code here.*/ \ - } +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ - { \ - /* System halt code here.*/ \ - } +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) \ - { \ - /* Trace code here.*/ \ - } +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} /** @} */ diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h index f9cb68581c..c52486ac50 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -620,23 +651,40 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -644,45 +692,47 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) \ - { \ - /* Add threads finalization code here.*/ \ - } +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ - { \ - /* Context switch code here.*/ \ - } +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() \ - { \ - /* IRQ prologue code here.*/ \ - } +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() \ - { \ - /* IRQ epilogue code here.*/ \ - } +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /** * @brief Idle thread enter hook. @@ -690,10 +740,9 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() \ - { \ - /* Idle-enter code here.*/ \ - } +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} /** * @brief Idle thread leave hook. @@ -701,49 +750,52 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() \ - { \ - /* Idle-leave code here.*/ \ - } +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() \ - { \ - /* Idle loop code here.*/ \ - } +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() \ - { \ - /* System tick event code here.*/ \ - } +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ - { \ - /* System halt code here.*/ \ - } +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) \ - { \ - /* Trace code here.*/ \ - } +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} /** @} */ diff --git a/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/chconf.h b/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/chconf.h index b510efa624..f7d416dbc7 100644 --- a/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/chconf.h +++ b/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -620,23 +651,40 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -644,45 +692,47 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) \ - { \ - /* Add threads initialization code here.*/ \ - } +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) \ - { \ - /* Add threads finalization code here.*/ \ - } +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ - { \ - /* Context switch code here.*/ \ - } +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() \ - { \ - /* IRQ prologue code here.*/ \ - } +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() \ - { \ - /* IRQ epilogue code here.*/ \ - } +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} /** * @brief Idle thread enter hook. @@ -690,10 +740,9 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() \ - { \ - /* Idle-enter code here.*/ \ - } +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} /** * @brief Idle thread leave hook. @@ -701,49 +750,52 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() \ - { \ - /* Idle-leave code here.*/ \ - } +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() \ - { \ - /* Idle loop code here.*/ \ - } +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() \ - { \ - /* System tick event code here.*/ \ - } +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ - { \ - /* System halt code here.*/ \ - } +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) \ - { \ - /* Trace code here.*/ \ - } +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} /** @} */ diff --git a/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/chconf.h b/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/chconf.h index af7b7438f4..d1e23c9050 100644 --- a/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/chconf.h +++ b/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -621,7 +652,7 @@ * @details User fields added to the end of the @p ch_system_t structure. */ #define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ + /* Add system custom fields here.*/ /** * @brief System initialization hook. @@ -629,7 +660,23 @@ * just before interrupts are enabled globally. */ #define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ } /** @@ -645,6 +692,8 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ @@ -653,6 +702,8 @@ /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ @@ -661,6 +712,9 @@ /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ /* Context switch code here.*/ \ @@ -735,6 +789,14 @@ /* Trace code here.*/ \ } +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + /** @} */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/chconf.h b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/chconf.h index d1e3bd1907..8b7e15a07a 100644 --- a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/chconf.h +++ b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -621,7 +652,7 @@ * @details User fields added to the end of the @p ch_system_t structure. */ #define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ + /* Add system custom fields here.*/ /** * @brief System initialization hook. @@ -629,7 +660,23 @@ * just before interrupts are enabled globally. */ #define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ } /** @@ -645,6 +692,8 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ @@ -653,6 +702,8 @@ /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ @@ -661,6 +712,9 @@ /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ /* Context switch code here.*/ \ @@ -735,6 +789,14 @@ /* Trace code here.*/ \ } +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + /** @} */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/chconf.h b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/chconf.h index af7b7438f4..d1e23c9050 100644 --- a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/chconf.h +++ b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -621,7 +652,7 @@ * @details User fields added to the end of the @p ch_system_t structure. */ #define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ + /* Add system custom fields here.*/ /** * @brief System initialization hook. @@ -629,7 +660,23 @@ * just before interrupts are enabled globally. */ #define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ } /** @@ -645,6 +692,8 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ @@ -653,6 +702,8 @@ /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ @@ -661,6 +712,9 @@ /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ /* Context switch code here.*/ \ @@ -735,6 +789,14 @@ /* Trace code here.*/ \ } +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + /** @} */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/chconf.h b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/chconf.h index a1fcd00529..67e6f1156d 100644 --- a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/chconf.h +++ b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -621,7 +652,7 @@ * @details User fields added to the end of the @p ch_system_t structure. */ #define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ + /* Add system custom fields here.*/ /** * @brief System initialization hook. @@ -629,7 +660,23 @@ * just before interrupts are enabled globally. */ #define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ } /** @@ -645,6 +692,8 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ @@ -653,6 +702,8 @@ /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ @@ -661,6 +712,9 @@ /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ /* Context switch code here.*/ \ @@ -735,6 +789,14 @@ /* Trace code here.*/ \ } +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + /** @} */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/chconf.h b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/chconf.h index e5c868b7f8..cc4d2a81a6 100644 --- a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/chconf.h +++ b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/chconf.h @@ -19,7 +19,27 @@ #define CHCONF_H #define _CHIBIOS_RT_CONF_ -#define _CHIBIOS_RT_CONF_VER_6_1_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ /*===========================================================================*/ /** @@ -30,7 +50,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 @@ -150,6 +170,17 @@ #define CH_CFG_USE_TM FALSE #endif +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP FALSE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. @@ -621,7 +652,7 @@ * @details User fields added to the end of the @p ch_system_t structure. */ #define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ + /* Add system custom fields here.*/ /** * @brief System initialization hook. @@ -629,7 +660,23 @@ * just before interrupts are enabled globally. */ #define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add threads initialization code here.*/ \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ } /** @@ -645,6 +692,8 @@ * * @note It is invoked from within @p _thread_init() and implicitly from all * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ @@ -653,6 +702,8 @@ /** * @brief Threads finalization hook. * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure */ #define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ @@ -661,6 +712,9 @@ /** * @brief Context switch hook. * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out */ #define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ /* Context switch code here.*/ \ @@ -735,6 +789,14 @@ /* Trace code here.*/ \ } +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + /** @} */ /*===========================================================================*/ From 2019a5daaccae750013b05f12e8006d7409d7354 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 20 Jun 2021 20:13:12 +0100 Subject: [PATCH 02/15] Update chibios git branch. (requires mirror update) --- .devcontainer/scripts/git-pull-repos.sh | 2 +- .devcontainer/sources/Dockerfile.All | 2 +- .devcontainer/sources/Dockerfile.ChibiOS | 2 +- targets/ChibiOS/CMakeLists.txt | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.devcontainer/scripts/git-pull-repos.sh b/.devcontainer/scripts/git-pull-repos.sh index 59db28adda..5188ba253d 100644 --- a/.devcontainer/scripts/git-pull-repos.sh +++ b/.devcontainer/scripts/git-pull-repos.sh @@ -10,7 +10,7 @@ git pull origin nf-build cd /sources/AzureRTOS git pull cd /sources/ChibiOs -git pull origin stable_20.3.x +git pull origin stable_21.6.x cd /sources/ChibiOs-Contrib git pull origin nanoframework cd /sources/mbedtls diff --git a/.devcontainer/sources/Dockerfile.All b/.devcontainer/sources/Dockerfile.All index 98eaddc3f6..0a89e0be8a 100644 --- a/.devcontainer/sources/Dockerfile.All +++ b/.devcontainer/sources/Dockerfile.All @@ -78,7 +78,7 @@ RUN git clone --branch nf-build https://github.com/nanoframework/STM32CubeL4.git && git clone --branch nf-build https://github.com/nanoframework/STM32CubeF4.git --depth 1 ./sources/STM32CubeF4 \ && git clone --branch nf-build https://github.com/nanoframework/STM32CubeH7.git --depth 1 ./sources/STM32CubeH7 \ && git clone --recursive https://github.com/azure-rtos/threadx.git --depth 1 ./sources/AzureRTOS \ - && git clone --branch stable_20.3.x https://github.com/nanoframework/chibios.git --depth 1 ./sources/ChibiOs \ + && git clone --branch stable_21.6.x https://github.com/nanoframework/chibios.git --depth 1 ./sources/ChibiOs \ && git clone --branch nanoframework https://github.com/nanoframework/ChibiOS-Contrib.git --depth 1 ./sources/ChibiOs-Contrib # Clone mbedtls and fatfs RUN git clone --branch mbedtls-2.26.0 https://github.com/ARMmbed/mbedtls.git --depth 1 ./sources/mbedtls \ diff --git a/.devcontainer/sources/Dockerfile.ChibiOS b/.devcontainer/sources/Dockerfile.ChibiOS index 7d32745d0a..991eff4b2e 100644 --- a/.devcontainer/sources/Dockerfile.ChibiOS +++ b/.devcontainer/sources/Dockerfile.ChibiOS @@ -46,7 +46,7 @@ RUN git clone --branch nf-build https://github.com/nanoframework/STM32CubeL4.git && git clone --branch nf-build https://github.com/nanoframework/STM32CubeF7.git --depth 1 ./sources/STM32CubeF7 \ && git clone --branch nf-build https://github.com/nanoframework/STM32CubeF4.git --depth 1 ./sources/STM32CubeF4 \ && git clone --branch nf-build https://github.com/nanoframework/STM32CubeH7.git --depth 1 ./sources/STM32CubeH7 \ - && git clone --branch stable_20.3.x https://github.com/nanoframework/chibios.git --depth 1 ./sources/ChibiOs \ + && git clone --branch stable_21.6.x https://github.com/nanoframework/chibios.git --depth 1 ./sources/ChibiOs \ && git clone --branch nanoframework https://github.com/nanoframework/ChibiOS-Contrib.git --depth 1 ./sources/ChibiOs-Contrib # Clone mbedtls and fatfs RUN git clone --branch mbedtls-2.26.0 https://github.com/ARMmbed/mbedtls.git --depth 1 ./sources/mbedtls \ diff --git a/targets/ChibiOS/CMakeLists.txt b/targets/ChibiOS/CMakeLists.txt index 7ac869adcc..f17ecb13e0 100644 --- a/targets/ChibiOS/CMakeLists.txt +++ b/targets/ChibiOS/CMakeLists.txt @@ -72,7 +72,7 @@ endif() if(RTOS_VERSION_EMPTY) # no ChibiOS version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(RTOS_VERSION "stable_20.3.x") + set(RTOS_VERSION "stable_21.6.x") endif() if(NO_RTOS_SOURCE_FOLDER) From a6457144ba7153814c5d82adf1bd3f41da4e2580 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 20 Jun 2021 20:34:57 +0100 Subject: [PATCH 03/15] Update F7 series mcuconf.h --- .../ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h | 13 +++++++++++++ targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h | 14 +++++++++++++- .../ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h | 13 +++++++++++++ .../ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h | 15 ++++++++++++++- 4 files changed, 53 insertions(+), 2 deletions(-) diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h index 222656a3e4..ce62b8eddc 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h @@ -304,6 +304,18 @@ #define STM32_SERIAL_USE_UART7 FALSE #define STM32_SERIAL_USE_UART8 FALSE +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE + /* * SPI driver system settings. */ @@ -410,6 +422,7 @@ */ #define STM32_WSPI_USE_QUADSPI1 FALSE #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 2 // header for nanoFramework overlay drivers #include "mcuconf_nf.h" diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h index 6eaa3e1582..5add6edd29 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h @@ -304,6 +304,18 @@ #define STM32_SERIAL_USE_UART7 FALSE #define STM32_SERIAL_USE_UART8 FALSE +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE + /* * SPI driver system settings. */ @@ -410,7 +422,7 @@ */ #define STM32_WSPI_USE_QUADSPI1 FALSE #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 2 // NOT IN LATEST VERSION, KEEPING JUST INCASE +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 2 // header for nanoFramework overlay drivers #include "mcuconf_nf.h" diff --git a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h index 93228ac697..fb3770006f 100644 --- a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h @@ -308,6 +308,18 @@ #define STM32_SERIAL_USE_UART7 FALSE #define STM32_SERIAL_USE_UART8 FALSE +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE + /* * SPI driver system settings. */ @@ -414,5 +426,6 @@ */ #define STM32_WSPI_USE_QUADSPI1 FALSE #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 2 #endif /* MCUCONF_H */ diff --git a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h index 50c5203499..12b65367ba 100644 --- a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h @@ -308,6 +308,18 @@ #define STM32_SERIAL_USE_UART7 FALSE #define STM32_SERIAL_USE_UART8 FALSE +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE + /* * SPI driver system settings. */ @@ -414,7 +426,8 @@ */ #define STM32_WSPI_USE_QUADSPI1 FALSE #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 2 // NOT IN LATEST VERSION, KEEPING JUST INCASE +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 2 + // header for nanoFramework overlay drivers #include "mcuconf_nf.h" From 0d2ed914413c639d9988de420b6058c4525d962a Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 20 Jun 2021 20:44:34 +0100 Subject: [PATCH 04/15] Update halconf.h files. --- .../NETDUINO3_WIFI/nanoBooter/halconf.h | 20 ++++++++++ .../ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h | 20 ++++++++++ .../ORGPAL_PALTHREE/nanoBooter/halconf.h | 40 +++++++++++++++++++ .../ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h | 20 ++++++++++ .../ST_NUCLEO64_F091RC/nanoBooter/halconf.h | 20 ++++++++++ .../ST_NUCLEO64_F091RC/nanoCLR/halconf.h | 20 ++++++++++ .../nanoBooter/halconf.h | 20 ++++++++++ .../ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h | 20 ++++++++++ .../nanoBooter/halconf.h | 20 ++++++++++ .../ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h | 20 ++++++++++ 10 files changed, 220 insertions(+) diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h index 63b4ffd496..3202c3c52a 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h @@ -405,6 +405,26 @@ #define SERIAL_BUFFERS_SIZE 16 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h index 31de933726..cfd29fc0e3 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h @@ -416,6 +416,26 @@ #define SERIAL_BUFFERS_SIZE 16 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/halconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/halconf.h index dae1869f7d..93132a85e1 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/halconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/halconf.h @@ -405,6 +405,46 @@ #define SERIAL_BUFFERS_SIZE 64 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h index 954222e17b..676e4345b4 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h @@ -417,6 +417,26 @@ #define SERIAL_BUFFERS_SIZE 16 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf.h b/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf.h index 49d618dcd6..8f0ff525a3 100644 --- a/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf.h +++ b/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf.h @@ -405,6 +405,26 @@ #define SERIAL_BUFFERS_SIZE 64 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h b/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h index 15dda09b4d..df71b06e45 100644 --- a/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h +++ b/targets/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h @@ -417,6 +417,26 @@ #define SERIAL_BUFFERS_SIZE 64 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf.h b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf.h index 8b4ca18126..07c510bffa 100644 --- a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf.h +++ b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf.h @@ -405,6 +405,26 @@ #define SERIAL_BUFFERS_SIZE 16 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h index 31743b78b9..ce2ed04e34 100644 --- a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h +++ b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h @@ -417,6 +417,26 @@ #define SERIAL_BUFFERS_SIZE 16 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf.h b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf.h index f6b86fb8c5..b38a2ebd68 100644 --- a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf.h +++ b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf.h @@ -405,6 +405,26 @@ #define SERIAL_BUFFERS_SIZE 64 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ diff --git a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h index ede05e987d..90c7601a0a 100644 --- a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h +++ b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h @@ -426,6 +426,26 @@ #define SERIAL_BUFFERS_SIZE 64 #endif +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + /*===========================================================================*/ /* SERIAL_USB driver related setting. */ /*===========================================================================*/ From 9ed26b295ef6dfe334d4d51fd3f12c85cf876eb0 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sun, 20 Jun 2021 21:01:57 +0100 Subject: [PATCH 05/15] Update chibios sources for SYSTICKv1 being split out from TIMv1. --- CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake | 2 ++ CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake | 2 ++ CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake | 2 ++ CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake | 2 ++ CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake | 2 ++ CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake | 2 ++ 6 files changed, 12 insertions(+) diff --git a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake index 2f752f14ff..b16fa0806a 100644 --- a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake @@ -74,6 +74,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1 @@ -105,6 +106,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GP list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1) diff --git a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake index dbb781d693..ae618b5bd3 100644 --- a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake @@ -85,6 +85,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDIOv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 @@ -121,6 +122,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RN list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDIOv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) diff --git a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake index b25d9940b9..c3075494c8 100644 --- a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake @@ -86,6 +86,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 @@ -122,6 +123,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RN list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) diff --git a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake index a6f19ddeb2..4c4496f794 100644 --- a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake @@ -86,6 +86,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv3 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 @@ -123,6 +124,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RN list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) diff --git a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake index 95e03bd764..cb8d80cd03 100644 --- a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake @@ -75,6 +75,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1 @@ -105,6 +106,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GP list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1) diff --git a/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake index 4105c43613..8b2ea7569c 100644 --- a/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake @@ -85,6 +85,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 @@ -121,6 +122,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RN list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) From c600bcd8f00dae2d734f27aa68da50615057faf3 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Jun 2021 14:59:20 +0100 Subject: [PATCH 06/15] Fix location change of RT chcore files. --- CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake | 9 +++++---- CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake | 9 +++++---- CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake | 9 +++++---- CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake | 9 +++++---- CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake | 9 +++++---- CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake | 9 +++++---- 6 files changed, 30 insertions(+), 24 deletions(-) diff --git a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake index b16fa0806a..4ecb1feddd 100644 --- a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake @@ -49,8 +49,7 @@ set(CHIBIOS_PORT_SRCS # RT chcore.c - chcore_v6m.c - chcoreasm_v6m.S + chcoreasm.S ) foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) @@ -59,9 +58,9 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) find_file(CHIBIOS_F0_SRC_FILE ${SRC_FILE} PATHS - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M/compilers/GCC ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx + ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F0xx @@ -92,6 +91,8 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F0xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) diff --git a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake index ae618b5bd3..97f442a142 100644 --- a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake @@ -53,8 +53,7 @@ set(CHIBIOS_PORT_SRCS # RT chcore.c - chcore_v7m.c - chcoreasm_v7m.S + chcoreasm.S ) foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) @@ -64,9 +63,9 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) find_file(CHIBIOS_F4_SRC_FILE ${SRC_FILE} PATHS - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F4xx @@ -102,6 +101,8 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F4xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) diff --git a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake index c3075494c8..77f2138b74 100644 --- a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake @@ -53,8 +53,7 @@ set(CHIBIOS_PORT_SRCS # RT chcore.c - chcore_v7m.c - chcoreasm_v7m.S + chcoreasm.S ) foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) @@ -64,9 +63,9 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) find_file(CHIBIOS_F7_SRC_FILE ${SRC_FILE} PATHS - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F7xx @@ -103,6 +102,8 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F7xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) diff --git a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake index 4c4496f794..b51c4ab195 100644 --- a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake @@ -53,8 +53,7 @@ set(CHIBIOS_PORT_SRCS # RT chcore.c - chcore_v7m.c - chcoreasm_v7m.S + chcoreasm.S ) foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) @@ -64,9 +63,9 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) find_file(CHIBIOS_H7_SRC_FILE ${SRC_FILE} PATHS - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32H7xx @@ -103,6 +102,8 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32H7xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) diff --git a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake index cb8d80cd03..9be11f5c82 100644 --- a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake @@ -49,8 +49,7 @@ set(CHIBIOS_PORT_SRCS # RT chcore.c - chcore_v6m.c - chcoreasm_v6m.S + chcoreasm.S ) foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) @@ -60,9 +59,9 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) find_file(CHIBIOS_L0_SRC_FILE ${SRC_FILE} PATHS - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M/compilers/GCC ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx + ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32L0xx @@ -92,6 +91,8 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32L0xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) diff --git a/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake index 8b2ea7569c..e982e24bd0 100644 --- a/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake @@ -53,8 +53,7 @@ set(CHIBIOS_PORT_SRCS # RT chcore.c - chcore_v7m.c - chcoreasm_v7m.S + chcoreasm.S ) foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) @@ -64,9 +63,9 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) find_file(CHIBIOS_L4_SRC_FILE ${SRC_FILE} PATHS - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F4xx @@ -102,6 +101,8 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32L4xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) From 85f4df1d816892022e537a926734a7b16a6d0e61 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Jun 2021 15:15:56 +0100 Subject: [PATCH 07/15] Add required USART include. --- CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake | 1 + CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake | 1 + CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake | 1 + CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake | 1 + CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake | 1 + CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake | 1 + 6 files changed, 6 insertions(+) diff --git a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake index 4ecb1feddd..27cdfa0156 100644 --- a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake @@ -109,6 +109,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RT list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) diff --git a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake index 97f442a142..ff66b532a2 100644 --- a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake @@ -125,6 +125,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SD list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) diff --git a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake index 77f2138b74..8d3d17459a 100644 --- a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake @@ -126,6 +126,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SD list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) diff --git a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake index b51c4ab195..2990094b08 100644 --- a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake @@ -127,6 +127,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SD list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv3) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) diff --git a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake index 9be11f5c82..6b25738bd9 100644 --- a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake @@ -109,6 +109,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RT list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) diff --git a/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake index e982e24bd0..bb8322e96e 100644 --- a/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake @@ -125,6 +125,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SD list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) From f82d7c14b57454e6bcfedfe4deb67327cc3f9ce7 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Jun 2021 17:27:26 +0100 Subject: [PATCH 08/15] Add missing RT files. --- CMake/Modules/FindChibiOS.cmake | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/CMake/Modules/FindChibiOS.cmake b/CMake/Modules/FindChibiOS.cmake index 0d59d84681..0d8370ae8f 100644 --- a/CMake/Modules/FindChibiOS.cmake +++ b/CMake/Modules/FindChibiOS.cmake @@ -48,8 +48,8 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/osal/rt-nil) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/oslib/include) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/rt/include) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/${TARGET_SERIES}) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/abstractions/cmsis_os) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/CMSIS/include) @@ -112,10 +112,12 @@ set(CHIBIOS_SRCS # RT chsys.c + chrfcu.c chdebug.c chtrace.c chvt.c chschd.c + chinstances.c chthreads.c chtm.c chstats.c @@ -132,6 +134,8 @@ set(CHIBIOS_SRCS chmemheaps.c chmempools.c chpipes.c + chobjcaches.c + chdelegates.c chfactory.c # required to use malloc and other newlib stuff From f4f9909743514ea942b2b809ca5bc6a8a5f2ac4b Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Jun 2021 19:01:55 +0100 Subject: [PATCH 09/15] Fixes for timer callbacks. --- targets/ChibiOS/_common/Target_Windows_Storage.c | 3 ++- targets/ChibiOS/_nanoCLR/Windows.Devices.Gpio/cpu_gpio.cpp | 3 ++- targets/ChibiOS/_nanoCLR/targetPAL_Events.cpp | 3 ++- targets/ChibiOS/_nanoCLR/targetPAL_Time.cpp | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/targets/ChibiOS/_common/Target_Windows_Storage.c b/targets/ChibiOS/_common/Target_Windows_Storage.c index 0c3e0857fe..5b1b9e0e9c 100644 --- a/targets/ChibiOS/_common/Target_Windows_Storage.c +++ b/targets/ChibiOS/_common/Target_Windows_Storage.c @@ -37,8 +37,9 @@ static virtual_timer_t sdCardDebounceTimer; static bool sdCardPresent; // Insertion monitor timer callback function. -static void SdCardInsertionMonitorCallback(void *p) +static void SdCardInsertionMonitorCallback(virtual_timer_t *vtp, void *p) { + (void)vtp; BaseBlockDevice *bbdp = p; bool currentStatus; diff --git a/targets/ChibiOS/_nanoCLR/Windows.Devices.Gpio/cpu_gpio.cpp b/targets/ChibiOS/_nanoCLR/Windows.Devices.Gpio/cpu_gpio.cpp index 6878f57917..b7489a9e96 100644 --- a/targets/ChibiOS/_nanoCLR/Windows.Devices.Gpio/cpu_gpio.cpp +++ b/targets/ChibiOS/_nanoCLR/Windows.Devices.Gpio/cpu_gpio.cpp @@ -43,8 +43,9 @@ bool IsValidGpioPin(GPIO_PIN pinNumber) return (pinNumber <= GPIO_MAX_PIN); } -static void DebounceTimerCallback(void *arg) +static void DebounceTimerCallback(virtual_timer_t *vtp, void *arg) { + (void)vtp; gpio_input_state *pState = (gpio_input_state *)arg; // get current pin state diff --git a/targets/ChibiOS/_nanoCLR/targetPAL_Events.cpp b/targets/ChibiOS/_nanoCLR/targetPAL_Events.cpp index dc633a1504..0b2861dc3f 100644 --- a/targets/ChibiOS/_nanoCLR/targetPAL_Events.cpp +++ b/targets/ChibiOS/_nanoCLR/targetPAL_Events.cpp @@ -21,8 +21,9 @@ bool Events_Uninitialize_Platform() return true; } -static void local_Events_SetBoolTimer_Callback(void *arg) +static void local_Events_SetBoolTimer_Callback(virtual_timer_t *vtp, void *arg) { + (void)vtp; NATIVE_PROFILE_PAL_EVENTS(); bool *timerCompleteFlag = (bool *)arg; diff --git a/targets/ChibiOS/_nanoCLR/targetPAL_Time.cpp b/targets/ChibiOS/_nanoCLR/targetPAL_Time.cpp index 8ac76fee1b..aafa3ac1e7 100644 --- a/targets/ChibiOS/_nanoCLR/targetPAL_Time.cpp +++ b/targets/ChibiOS/_nanoCLR/targetPAL_Time.cpp @@ -13,8 +13,9 @@ static virtual_timer_t nextEventTimer; void* nextEventCallbackDummyArg = NULL; -static void NextEventTimer_Callback( void* arg ) +static void NextEventTimer_Callback(virtual_timer_t *vtp, void* arg ) { + (void)vtp; (void)arg; // this call also schedules the next one, if there is one From 06bf0c72e9deb6361385c09fd9184c0c578836b5 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Jun 2021 19:22:13 +0100 Subject: [PATCH 10/15] Use master branch for chibiOS whilst waiting for a mirror. !!! TODO: revert to set(RTOS_VERSION "stable_21.6.x") when mirror available !!! (dev containers continue to target the correct, but non existing branch. --- targets/ChibiOS/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/ChibiOS/CMakeLists.txt b/targets/ChibiOS/CMakeLists.txt index f17ecb13e0..b9eadffc5c 100644 --- a/targets/ChibiOS/CMakeLists.txt +++ b/targets/ChibiOS/CMakeLists.txt @@ -72,7 +72,7 @@ endif() if(RTOS_VERSION_EMPTY) # no ChibiOS version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(RTOS_VERSION "stable_21.6.x") + set(RTOS_VERSION "master") # !!! TODO: revert to set(RTOS_VERSION "stable_21.6.x") when mirror available !!! endif() if(NO_RTOS_SOURCE_FOLDER) From 87925a6912d9edea40b9bd111176411ae930f5a8 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Jun 2021 19:35:41 +0100 Subject: [PATCH 11/15] Add MCU Defines for netduino and F429I_DISCO --- targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h | 1 + targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h | 1 + targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h | 1 + targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h | 2 +- 4 files changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h index c5548028dc..7ed42208a3 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h @@ -22,6 +22,7 @@ */ #define STM32F4xx_MCUCONF +#define STM32F427_MCUCONF /* * HAL driver system settings. diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h index 76d1d005a8..c1efc04d74 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h @@ -22,6 +22,7 @@ */ #define STM32F4xx_MCUCONF +#define STM32F427_MCUCONF /* * HAL driver system settings. diff --git a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h index ad0344da2b..e84b65c48c 100644 --- a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h @@ -22,6 +22,7 @@ */ #define STM32F4xx_MCUCONF +#define STM32F429_MCUCONF /* * HAL driver system settings. diff --git a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h index 79c06ff042..51d4d3e1de 100644 --- a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h @@ -22,7 +22,7 @@ */ #define STM32F4xx_MCUCONF -//#define STM32F429_MCUCONF +#define STM32F429_MCUCONF /* * HAL driver system settings. From 4262e534112f785ff82f8d660afb1356aa8d2be6 Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Mon, 21 Jun 2021 19:51:10 +0100 Subject: [PATCH 12/15] Add required mcuconf irq changes for F4 boards. --- .../NETDUINO3_WIFI/nanoBooter/mcuconf.h | 24 +++++++++ .../ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h | 52 ++++++++++++++----- .../nanoBooter/mcuconf.h | 24 +++++++++ .../ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h | 24 +++++++++ 4 files changed, 110 insertions(+), 14 deletions(-) diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h index 7ed42208a3..54790f8478 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h @@ -73,6 +73,30 @@ #define STM32_IRQ_EXTI21_PRIORITY 15 #define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 + /* * ADC driver system settings. */ diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h index c1efc04d74..da33b02383 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h @@ -61,20 +61,44 @@ /* * IRQ system settings. */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 /* * ADC driver system settings. diff --git a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h index e84b65c48c..b61391f1c5 100644 --- a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h @@ -73,6 +73,30 @@ #define STM32_IRQ_EXTI21_PRIORITY 15 #define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 + /* * ADC driver system settings. */ diff --git a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h index 51d4d3e1de..287551e691 100644 --- a/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h @@ -73,6 +73,30 @@ #define STM32_IRQ_EXTI21_PRIORITY 15 #define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 + /* * ADC driver system settings. */ From 56b227c67919033a7253f86466eaf2032d15fb04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 12 Jul 2021 17:15:32 +0100 Subject: [PATCH 13/15] Revert b31ed79a5cf00524909644814c3286fa36600b91 - Switch repo to our mirror. --- targets/ChibiOS/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/ChibiOS/CMakeLists.txt b/targets/ChibiOS/CMakeLists.txt index b9eadffc5c..52fea4509d 100644 --- a/targets/ChibiOS/CMakeLists.txt +++ b/targets/ChibiOS/CMakeLists.txt @@ -72,7 +72,7 @@ endif() if(RTOS_VERSION_EMPTY) # no ChibiOS version actualy specified, must be empty which is fine, we'll default to a known good version # WHEN CHANGING THIS MAKE SURE TO UPDATE THE DEV CONTAINERS - set(RTOS_VERSION "master") # !!! TODO: revert to set(RTOS_VERSION "stable_21.6.x") when mirror available !!! + set(RTOS_VERSION "stable_21.6.x") endif() if(NO_RTOS_SOURCE_FOLDER) @@ -81,7 +81,7 @@ if(NO_RTOS_SOURCE_FOLDER) FetchContent_Declare( chibios - GIT_REPOSITORY https://github.com/nanoframework/chibios + GIT_REPOSITORY https://github.com/nanoframework/ChibiOS_mirror GIT_TAG ${RTOS_VERSION} ) From 0d46720355e708951caf52490372d5732007fbfa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 12 Jul 2021 17:12:24 +0100 Subject: [PATCH 14/15] Extract ChibiOS HAL to separate CMake modules - Update series sources and chibios module to accordingly. --- CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake | 71 ------- CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake | 87 -------- CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake | 87 -------- CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake | 89 -------- CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake | 73 ------- CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake | 87 -------- CMake/Modules/FindChibiOS.cmake | 3 + CMake/Modules/FindChibiOS_F0_HAL.cmake | 170 ++++++++++++++++ CMake/Modules/FindChibiOS_F4_HAL.cmake | 188 +++++++++++++++++ CMake/Modules/FindChibiOS_F7_HAL.cmake | 188 +++++++++++++++++ CMake/Modules/FindChibiOS_H7_HAL.cmake | 191 ++++++++++++++++++ CMake/Modules/FindChibiOS_L0_HAL.cmake | 173 ++++++++++++++++ CMake/Modules/FindChibiOS_L4_HAL.cmake | 191 ++++++++++++++++++ CMake/binutils.ChibiOS.cmake | 13 ++ targets/ChibiOS/CMakeLists.txt | 3 + 15 files changed, 1120 insertions(+), 494 deletions(-) create mode 100644 CMake/Modules/FindChibiOS_F0_HAL.cmake create mode 100644 CMake/Modules/FindChibiOS_F4_HAL.cmake create mode 100644 CMake/Modules/FindChibiOS_F7_HAL.cmake create mode 100644 CMake/Modules/FindChibiOS_H7_HAL.cmake create mode 100644 CMake/Modules/FindChibiOS_L0_HAL.cmake create mode 100644 CMake/Modules/FindChibiOS_L4_HAL.cmake diff --git a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake index 27cdfa0156..66648bbb6b 100644 --- a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake @@ -14,38 +14,6 @@ FetchContent_GetProperties(chibios) ################################################################################ set(CHIBIOS_PORT_SRCS - # startup code - crt1.c - vectors.S - crt0_v6m.S - - nvic.c - stm32_isr.c - hal_lld.c - - hal_adc_lld.c - hal_can_lld.c - hal_dac_lld.c - stm32_dma.c - stm32_exti.c - hal_pal_lld.c - hal_i2c_lld.c - hal_rtc_lld.c - - hal_i2s_lld.c - hal_spi_lld.c - - hal_st_lld.c - hal_gpt_lld.c - hal_icu_lld.c - hal_pwm_lld.c - - hal_serial_lld.c - hal_uart_lld.c - - hal_usb_lld.c - - hal_wdg_lld.c # RT chcore.c @@ -59,25 +27,9 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) PATHS ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F0xx - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 CMAKE_FIND_ROOT_PATH_BOTH ) @@ -90,30 +42,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F0xx) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32F0xx) - -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) - #################################################################################### # WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below diff --git a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake index ff66b532a2..2ff3abc7b2 100644 --- a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake @@ -14,42 +14,6 @@ FetchContent_GetProperties(chibios) ################################################################################################ set(CHIBIOS_PORT_SRCS - # startup code - crt1.c - vectors.S - crt0_v7m.S - - nvic.c - stm32_isr.c - hal_lld.c - - hal_adc_lld.c - hal_can_lld.c - hal_crypto_lld.c - hal_dac_lld.c - stm32_dma.c - stm32_exti.c - hal_pal_lld.c - hal_i2c_lld.c - hal_mac_lld.c - hal_usb_lld.c - hal_wspi_lld.c - hal_trng_lld.c - hal_rtc_lld.c - hal_sdc_lld.c - - hal_i2s_lld.c - hal_spi_lld.c - - hal_st_lld.c - hal_gpt_lld.c - hal_icu_lld.c - hal_pwm_lld.c - - hal_serial_lld.c - hal_uart_lld.c - - hal_wdg_lld.c # RT chcore.c @@ -64,30 +28,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) PATHS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M - ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx - - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F4xx - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDIOv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 CMAKE_FIND_ROOT_PATH_BOTH ) @@ -100,35 +41,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F4xx) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32F4xx) - -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDIOv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) - #################################################################################### # WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below diff --git a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake index 8d3d17459a..c7809e49ba 100644 --- a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake @@ -14,42 +14,6 @@ FetchContent_GetProperties(chibios) ################################################################################################ set(CHIBIOS_PORT_SRCS - # startup code - crt1.c - vectors.S - crt0_v7m.S - - nvic.c - stm32_isr.c - hal_lld.c - - hal_adc_lld.c - hal_can_lld.c - hal_crypto_lld.c - hal_dac_lld.c - stm32_dma.c - stm32_exti.c - hal_pal_lld.c - hal_i2c_lld.c - hal_mac_lld.c - hal_usb_lld.c - hal_wspi_lld.c - hal_trng_lld.c - hal_rtc_lld.c - hal_sdc_lld.c - - hal_i2s_lld.c - hal_spi_lld.c - - hal_st_lld.c - hal_gpt_lld.c - hal_icu_lld.c - hal_pwm_lld.c - - hal_serial_lld.c - hal_uart_lld.c - - hal_wdg_lld.c # RT chcore.c @@ -64,31 +28,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) PATHS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M - ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx - - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F7xx - - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 CMAKE_FIND_ROOT_PATH_BOTH ) @@ -101,34 +41,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F7xx) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32F7xx) - -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) #################################################################################### diff --git a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake index 2990094b08..c3c49dd424 100644 --- a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake @@ -14,42 +14,6 @@ FetchContent_GetProperties(chibios) ################################################################################################ set(CHIBIOS_PORT_SRCS - # startup code - crt1.c - vectors.S - crt0_v7m.S - - nvic.c - stm32_isr.c - hal_lld.c - - hal_adc_lld.c - hal_can_lld.c - hal_crypto_lld.c - hal_dac_lld.c - stm32_dma.c - stm32_exti.c - hal_pal_lld.c - hal_i2c_lld.c - #hal_mac_lld.c - hal_usb_lld.c - hal_wspi_lld.c - hal_trng_lld.c - hal_rtc_lld.c - hal_sdc_lld.c - - #hal_i2s_lld.c - hal_spi_lld.c - - hal_st_lld.c - hal_gpt_lld.c - hal_icu_lld.c - hal_pwm_lld.c - - hal_serial_lld.c - hal_uart_lld.c - - hal_wdg_lld.c # RT chcore.c @@ -64,31 +28,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) PATHS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M - ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx - - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32H7xx - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv4 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/BDMAv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/FDCANv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv3 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MDMAv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv3 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 CMAKE_FIND_ROOT_PATH_BOTH ) @@ -101,36 +41,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32H7xx) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32H7xx) - -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv4) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/BDMAv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/FDCANv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv3) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MDMAv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv3) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) - #################################################################################### # WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below diff --git a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake index 6b25738bd9..f0047f4626 100644 --- a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake @@ -14,38 +14,6 @@ FetchContent_GetProperties(chibios) ################################################################################ set(CHIBIOS_PORT_SRCS - # startup code - crt1.c - vectors.S - crt0_v6m.S - - nvic.c - stm32_isr.c - hal_lld.c - - hal_adc_lld.c - hal_can_lld.c - hal_dac_lld.c - stm32_dma.c - stm32_exti.c - hal_pal_lld.c - hal_i2c_lld.c - hal_rtc_lld.c - - hal_i2s_lld.c - hal_spi_lld.c - - hal_st_lld.c - hal_gpt_lld.c - hal_icu_lld.c - hal_pwm_lld.c - - hal_serial_lld.c - hal_uart_lld.c - - hal_usb_lld.c - - hal_wdg_lld.c # RT chcore.c @@ -60,25 +28,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) PATHS ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M - ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx - - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32L0xx - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 CMAKE_FIND_ROOT_PATH_BOTH ) @@ -90,30 +40,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) list(APPEND CHIBIOS_SOURCES ${CHIBIOS_L0_SRC_FILE}) endforeach() -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32L0xx) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32L0xx) - -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) - #################################################################################### # WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below diff --git a/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake index bb8322e96e..1624d7f1ed 100644 --- a/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L4xx_sources.cmake @@ -14,42 +14,6 @@ FetchContent_GetProperties(chibios) ################################################################################################ set(CHIBIOS_PORT_SRCS - # startup code - crt1.c - vectors.S - crt0_v7m.S - - nvic.c - stm32_isr.c - hal_lld.c - - hal_adc_lld.c - hal_can_lld.c - hal_crypto_lld.c - hal_dac_lld.c - stm32_dma.c - stm32_exti.c - hal_pal_lld.c - hal_i2c_lld.c - #hal_mac_lld.c - hal_usb_lld.c - hal_wspi_lld.c - hal_trng_lld.c - hal_rtc_lld.c - hal_sdc_lld.c - - hal_i2s_lld.c - hal_spi_lld.c - - hal_st_lld.c - hal_gpt_lld.c - hal_icu_lld.c - hal_pwm_lld.c - - hal_serial_lld.c - hal_uart_lld.c - - hal_wdg_lld.c # RT chcore.c @@ -64,30 +28,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) PATHS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC - ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M - ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx - - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F4xx - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv3 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv3 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 - #${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 - ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 CMAKE_FIND_ROOT_PATH_BOTH ) @@ -100,35 +41,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) endforeach() -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32L4xx) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32L4xx) - -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv3) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv3) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) -#list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) -list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) - #################################################################################### # WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below diff --git a/CMake/Modules/FindChibiOS.cmake b/CMake/Modules/FindChibiOS.cmake index 0d8370ae8f..518b84832d 100644 --- a/CMake/Modules/FindChibiOS.cmake +++ b/CMake/Modules/FindChibiOS.cmake @@ -31,6 +31,9 @@ else() set(TARGET_VENDOR "STM" CACHE INTERNAL "target vendor is STM") endif() +# store the package name for later use +set(TARGET_STM32_SERIES STM32${TARGET_SERIES_SHORT} CACHE INTERNAL "name for STM32 Cube package") + # including here the CMake files for the source files specific to the target series include(CHIBIOS_${TARGET_SERIES}_sources) # and here the GCC options tuned for the target series diff --git a/CMake/Modules/FindChibiOS_F0_HAL.cmake b/CMake/Modules/FindChibiOS_F0_HAL.cmake new file mode 100644 index 0000000000..a1b6cb382a --- /dev/null +++ b/CMake/Modules/FindChibiOS_F0_HAL.cmake @@ -0,0 +1,170 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(FetchContent) +FetchContent_GetProperties(chibios) + +# set include directories for ChibiOS HAL +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/boards/${TARGET_BOARD}) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F0xx) + +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F0xx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32F0xx) + + +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) + + +# OSHAL sources need to be added for ChibiOS RT-NIL or Azure RTOS depending on build +# adjust search path here +if(RTOS_CHIBIOS_CHECK) + set(OSHAL_PATH ${chibios_SOURCE_DIR}/os/hal/osal/rt-nil) +elseif(RTOS_AZURERTOS_CHECK) + set(OSHAL_PATH targets/AzureRTOS/ChibiOS/HAL) +else() + message(FATAL_ERROR "RTOS not configured to use ChibiOS HAL") +endif() + +# set include path for OSHAL header +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${OSHAL_PATH}) + + +# source files for ChibiOS HAL +set(CHIBIOS_HAL_SRCS + + # startup code + crt1.c + vectors.S + crt0_v6m.S + + nvic.c + stm32_isr.c + + # HAL-OSAL files + hal.c + hal_st.c + + hal_buffers.c + hal_queues.c + hal_mmcsd.c + + hal_adc.c + hal_can.c + hal_crypto.c + hal_dac.c + hal_gpt.c + hal_i2c.c + hal_i2s.c + hal_icu.c + hal_mac.c + hal_mmc_spi.c + hal_pal.c + hal_pwm.c + hal_rtc.c + hal_sdc.c + hal_serial.c + hal_serial_usb.c + hal_sio.c + hal_spi.c + hal_trng.c + hal_uart.c + hal_usb.c + hal_wdg.c + hal_wspi.c + + # LLD HAL files + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_rtc_lld.c + hal_spi_lld.c + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + hal_serial_lld.c + hal_uart_lld.c + hal_usb_lld.c + hal_wdg_lld.c + + # OSAL + osal.c +) + +foreach(SRC_FILE ${CHIBIOS_HAL_SRCS}) + + set(CHIBIOS_HAL_SRC_FILE SRC_FILE -NOTFOUND) + + find_file(CHIBIOS_HAL_SRC_FILE ${SRC_FILE} + PATHS + + ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC + + ${chibios_SOURCE_DIR}/os/hal/src + ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F0xx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F0xx + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 + + ${OSHAL_PATH} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${CHIBIOS_HAL_SRC_FILE}") + endif() + + list(APPEND CHIBIOS_HAL_SOURCES ${CHIBIOS_HAL_SRC_FILE}) + +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(ChibiOS DEFAULT_MSG CHIBIOS_HAL_INCLUDE_DIRS CHIBIOS_HAL_SOURCES) diff --git a/CMake/Modules/FindChibiOS_F4_HAL.cmake b/CMake/Modules/FindChibiOS_F4_HAL.cmake new file mode 100644 index 0000000000..b4c35a89d9 --- /dev/null +++ b/CMake/Modules/FindChibiOS_F4_HAL.cmake @@ -0,0 +1,188 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(FetchContent) +FetchContent_GetProperties(chibios) + +# set include directories for ChibiOS HAL +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/boards/${TARGET_BOARD}) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F4xx) + +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F4xx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32F4xx) + +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDIOv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) + +# OSHAL sources need to be added for ChibiOS RT-NIL or Azure RTOS depending on build +# adjust search path here +if(RTOS_CHIBIOS_CHECK) + set(OSHAL_PATH ${chibios_SOURCE_DIR}/os/hal/osal/rt-nil) +elseif(RTOS_AZURERTOS_CHECK) + set(OSHAL_PATH targets/AzureRTOS/ChibiOS/HAL) +else() + message(FATAL_ERROR "RTOS not configured to use ChibiOS HAL") +endif() + +# set include path for OSHAL header +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${OSHAL_PATH}) + + +# source files for ChibiOS HAL +set(CHIBIOS_HAL_SRCS + + # startup code + crt1.c + vectors.S + crt0_v7m.S + + nvic.c + stm32_isr.c + + # HAL-OSAL files + hal.c + hal_st.c + + hal_buffers.c + hal_queues.c + hal_mmcsd.c + + hal_adc.c + hal_can.c + hal_crypto.c + hal_dac.c + hal_gpt.c + hal_i2c.c + hal_i2s.c + hal_icu.c + hal_mac.c + hal_mmc_spi.c + hal_pal.c + hal_pwm.c + hal_rtc.c + hal_sdc.c + hal_serial.c + hal_serial_usb.c + hal_sio.c + hal_spi.c + hal_trng.c + hal_uart.c + hal_usb.c + hal_wdg.c + hal_wspi.c + + # LLD HAL files + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_crypto_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_mac_lld.c + hal_usb_lld.c + hal_wspi_lld.c + hal_trng_lld.c + hal_rtc_lld.c + hal_sdc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_wdg_lld.c + + # OSAL + osal.c +) + +foreach(SRC_FILE ${CHIBIOS_HAL_SRCS}) + + set(CHIBIOS_HAL_SRC_FILE SRC_FILE -NOTFOUND) + + find_file(CHIBIOS_HAL_SRC_FILE ${SRC_FILE} + PATHS + + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC + + ${chibios_SOURCE_DIR}/os/hal/src + ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F4xx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F4xx + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDIOv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 + + ${OSHAL_PATH} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${CHIBIOS_HAL_SRC_FILE}") + endif() + + list(APPEND CHIBIOS_HAL_SOURCES ${CHIBIOS_HAL_SRC_FILE}) + +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(ChibiOS DEFAULT_MSG CHIBIOS_HAL_INCLUDE_DIRS CHIBIOS_HAL_SOURCES) diff --git a/CMake/Modules/FindChibiOS_F7_HAL.cmake b/CMake/Modules/FindChibiOS_F7_HAL.cmake new file mode 100644 index 0000000000..9dbfe6e0e4 --- /dev/null +++ b/CMake/Modules/FindChibiOS_F7_HAL.cmake @@ -0,0 +1,188 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(FetchContent) +FetchContent_GetProperties(chibios) + +# set include directories for ChibiOS HAL +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/boards/${TARGET_BOARD}) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F7xx) + +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32F7xx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32F7xx) + +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) + + +# OSHAL sources need to be added for ChibiOS RT-NIL or Azure RTOS depending on build +# adjust search path here +if(RTOS_CHIBIOS_CHECK) + set(OSHAL_PATH ${chibios_SOURCE_DIR}/os/hal/osal/rt-nil) +elseif(RTOS_AZURERTOS_CHECK) + set(OSHAL_PATH targets/AzureRTOS/ChibiOS/HAL) +else() + message(FATAL_ERROR "RTOS not configured to use ChibiOS HAL") +endif() + +# set include path for OSHAL header +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${OSHAL_PATH}) + + +# source files for ChibiOS HAL +set(CHIBIOS_HAL_SRCS + + # startup code + crt1.c + vectors.S + crt0_v7m.S + + nvic.c + stm32_isr.c + + # HAL-OSAL files + hal.c + hal_st.c + + hal_buffers.c + hal_queues.c + hal_mmcsd.c + + hal_adc.c + hal_can.c + hal_crypto.c + hal_dac.c + hal_gpt.c + hal_i2c.c + hal_i2s.c + hal_icu.c + hal_mac.c + hal_mmc_spi.c + hal_pal.c + hal_pwm.c + hal_rtc.c + hal_sdc.c + hal_serial.c + hal_serial_usb.c + hal_sio.c + hal_spi.c + hal_trng.c + hal_uart.c + hal_usb.c + hal_wdg.c + hal_wspi.c + + # LLD HAL files + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_crypto_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_mac_lld.c + hal_usb_lld.c + hal_wspi_lld.c + hal_trng_lld.c + hal_rtc_lld.c + hal_sdc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_wdg_lld.c + + # OSAL + osal.c +) + +foreach(SRC_FILE ${CHIBIOS_HAL_SRCS}) + + set(CHIBIOS_HAL_SRC_FILE SRC_FILE -NOTFOUND) + + find_file(CHIBIOS_HAL_SRC_FILE ${SRC_FILE} + PATHS + + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC + + ${chibios_SOURCE_DIR}/os/hal/src + ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32F7xx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 + + ${OSHAL_PATH} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${CHIBIOS_HAL_SRC_FILE}") + endif() + + list(APPEND CHIBIOS_HAL_SOURCES ${CHIBIOS_HAL_SRC_FILE}) + +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(ChibiOS DEFAULT_MSG CHIBIOS_HAL_INCLUDE_DIRS CHIBIOS_HAL_SOURCES) diff --git a/CMake/Modules/FindChibiOS_H7_HAL.cmake b/CMake/Modules/FindChibiOS_H7_HAL.cmake new file mode 100644 index 0000000000..e4faa448d6 --- /dev/null +++ b/CMake/Modules/FindChibiOS_H7_HAL.cmake @@ -0,0 +1,191 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(FetchContent) +FetchContent_GetProperties(chibios) + +# set include directories for ChibiOS HAL +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/boards/${TARGET_BOARD}) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32H7xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32H7xx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32H7xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv4) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/BDMAv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/FDCANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MDMAv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) + + +# OSHAL sources need to be added for ChibiOS RT-NIL or Azure RTOS depending on build +# adjust search path here +if(RTOS_CHIBIOS_CHECK) + set(OSHAL_PATH ${chibios_SOURCE_DIR}/os/hal/osal/rt-nil) +elseif(RTOS_AZURERTOS_CHECK) + set(OSHAL_PATH targets/AzureRTOS/ChibiOS/HAL) +else() + message(FATAL_ERROR "RTOS not configured to use ChibiOS HAL") +endif() + +# set include path for OSHAL header +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${OSHAL_PATH}) + + +# source files for ChibiOS HAL +set(CHIBIOS_HAL_SRCS + + # startup code + crt1.c + vectors.S + crt0_v7m.S + + nvic.c + stm32_isr.c + + # HAL-OSAL files + hal.c + hal_st.c + + hal_buffers.c + hal_queues.c + hal_mmcsd.c + + hal_adc.c + hal_can.c + hal_crypto.c + hal_dac.c + hal_gpt.c + hal_i2c.c + hal_i2s.c + hal_icu.c + hal_mac.c + hal_mmc_spi.c + hal_pal.c + hal_pwm.c + hal_rtc.c + hal_sdc.c + hal_serial.c + hal_serial_usb.c + hal_sio.c + hal_spi.c + hal_trng.c + hal_uart.c + hal_usb.c + hal_wdg.c + hal_wspi.c + + # LLD HAL files + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_crypto_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + #hal_mac_lld.c + hal_usb_lld.c + hal_wspi_lld.c + hal_trng_lld.c + hal_rtc_lld.c + hal_sdc_lld.c + + #hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_wdg_lld.c + + # OSAL + osal.c +) + +foreach(SRC_FILE ${CHIBIOS_HAL_SRCS}) + + set(CHIBIOS_HAL_SRC_FILE SRC_FILE -NOTFOUND) + + find_file(CHIBIOS_HAL_SRC_FILE ${SRC_FILE} + PATHS + + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC + + ${chibios_SOURCE_DIR}/os/hal/src + ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32H7xx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32H7xx + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv4 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/BDMAv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/FDCANv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv3 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MDMAv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv3 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 + + ${OSHAL_PATH} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${CHIBIOS_HAL_SRC_FILE}") + endif() + + list(APPEND CHIBIOS_HAL_SOURCES ${CHIBIOS_HAL_SRC_FILE}) + +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(ChibiOS DEFAULT_MSG CHIBIOS_HAL_INCLUDE_DIRS CHIBIOS_HAL_SOURCES) diff --git a/CMake/Modules/FindChibiOS_L0_HAL.cmake b/CMake/Modules/FindChibiOS_L0_HAL.cmake new file mode 100644 index 0000000000..b9d0f69e44 --- /dev/null +++ b/CMake/Modules/FindChibiOS_L0_HAL.cmake @@ -0,0 +1,173 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(FetchContent) +FetchContent_GetProperties(chibios) + +# set include directories for ChibiOS HAL +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/boards/${TARGET_BOARD}) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32L0xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32L0xx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32L0xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) + + +# OSHAL sources need to be added for ChibiOS RT-NIL or Azure RTOS depending on build +# adjust search path here +if(RTOS_CHIBIOS_CHECK) + set(OSHAL_PATH ${chibios_SOURCE_DIR}/os/hal/osal/rt-nil) +elseif(RTOS_AZURERTOS_CHECK) + set(OSHAL_PATH targets/AzureRTOS/ChibiOS/HAL) +else() + message(FATAL_ERROR "RTOS not configured to use ChibiOS HAL") +endif() + +# set include path for OSHAL header +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${OSHAL_PATH}) + + +# source files for ChibiOS HAL +set(CHIBIOS_HAL_SRCS + + # startup code + crt1.c + vectors.S + crt0_v6m.S + + nvic.c + stm32_isr.c + + # HAL-OSAL files + hal.c + hal_st.c + + hal_buffers.c + hal_queues.c + hal_mmcsd.c + + hal_adc.c + hal_can.c + hal_crypto.c + hal_dac.c + hal_gpt.c + hal_i2c.c + hal_i2s.c + hal_icu.c + hal_mac.c + hal_mmc_spi.c + hal_pal.c + hal_pwm.c + hal_rtc.c + hal_sdc.c + hal_serial.c + hal_serial_usb.c + hal_sio.c + hal_spi.c + hal_trng.c + hal_uart.c + hal_usb.c + hal_wdg.c + hal_wspi.c + + # LLD HAL files + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_usb_lld.c + hal_rtc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_wdg_lld.c + + # OSAL + osal.c +) + +foreach(SRC_FILE ${CHIBIOS_HAL_SRCS}) + + set(CHIBIOS_HAL_SRC_FILE SRC_FILE -NOTFOUND) + + find_file(CHIBIOS_HAL_SRC_FILE ${SRC_FILE} + PATHS + + ${chibios_SOURCE_DIR}/os/common/ports/ARMv6-M/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC + + ${chibios_SOURCE_DIR}/os/hal/src + ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32L0xx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32L0xx + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USBv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 + + ${OSHAL_PATH} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${CHIBIOS_HAL_SRC_FILE}") + endif() + + list(APPEND CHIBIOS_HAL_SOURCES ${CHIBIOS_HAL_SRC_FILE}) + +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(ChibiOS DEFAULT_MSG CHIBIOS_HAL_INCLUDE_DIRS CHIBIOS_HAL_SOURCES) diff --git a/CMake/Modules/FindChibiOS_L4_HAL.cmake b/CMake/Modules/FindChibiOS_L4_HAL.cmake new file mode 100644 index 0000000000..972250f063 --- /dev/null +++ b/CMake/Modules/FindChibiOS_L4_HAL.cmake @@ -0,0 +1,191 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(FetchContent) +FetchContent_GetProperties(chibios) + +# set include directories for ChibiOS HAL +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/include) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/boards/${TARGET_BOARD}) +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32L4xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARM-common) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/devices/STM32L4xx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/common/ext/ST/STM32L4xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2) +#list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USART) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1) + + +# OSHAL sources need to be added for ChibiOS RT-NIL or Azure RTOS depending on build +# adjust search path here +if(RTOS_CHIBIOS_CHECK) + set(OSHAL_PATH ${chibios_SOURCE_DIR}/os/hal/osal/rt-nil) +elseif(RTOS_AZURERTOS_CHECK) + set(OSHAL_PATH targets/AzureRTOS/ChibiOS/HAL) +else() + message(FATAL_ERROR "RTOS not configured to use ChibiOS HAL") +endif() + +# set include path for OSHAL header +list(APPEND CHIBIOS_HAL_INCLUDE_DIRS ${OSHAL_PATH}) + + +# source files for ChibiOS HAL +set(CHIBIOS_HAL_SRCS + + # startup code + crt1.c + vectors.S + crt0_v7m.S + + nvic.c + stm32_isr.c + + # HAL-OSAL files + hal.c + hal_st.c + + hal_buffers.c + hal_queues.c + hal_mmcsd.c + + hal_adc.c + hal_can.c + hal_crypto.c + hal_dac.c + hal_gpt.c + hal_i2c.c + hal_i2s.c + hal_icu.c + hal_mac.c + hal_mmc_spi.c + hal_pal.c + hal_pwm.c + hal_rtc.c + hal_sdc.c + hal_serial.c + hal_serial_usb.c + hal_sio.c + hal_spi.c + hal_trng.c + hal_uart.c + hal_usb.c + hal_wdg.c + hal_wspi.c + + # LLD HAL files + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_crypto_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + #hal_mac_lld.c + hal_usb_lld.c + hal_wspi_lld.c + hal_trng_lld.c + hal_rtc_lld.c + hal_sdc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_wdg_lld.c + + + # OSAL + osal.c +) + +foreach(SRC_FILE ${CHIBIOS_HAL_SRCS}) + + set(CHIBIOS_HAL_SRC_FILE SRC_FILE -NOTFOUND) + + find_file(CHIBIOS_HAL_SRC_FILE ${SRC_FILE} + PATHS + + ${chibios_SOURCE_DIR}/os/common/ports/ARMv7-M/compilers/GCC + ${chibios_SOURCE_DIR}/os/common/startup/ARMCMx/compilers/GCC + + ${chibios_SOURCE_DIR}/os/hal/src + ${chibios_SOURCE_DIR}/os/hal/ports/common/ARMCMx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32L4xx + + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/STM32L4xx + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/ADCv3 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CANv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/CRYPv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/DMAv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/EXTIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/GPIOv3 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/I2Cv2 + #${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/MACv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/OTGv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/QUADSPIv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RNGv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/RTCv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SDMMCv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SPIv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/SYSTICKv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/TIMv1 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/USARTv2 + ${chibios_SOURCE_DIR}/os/hal/ports/STM32/LLD/xWDGv1 + + + ${OSHAL_PATH} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + + if (BUILD_VERBOSE) + message("${SRC_FILE} >> ${CHIBIOS_HAL_SRC_FILE}") + endif() + + list(APPEND CHIBIOS_HAL_SOURCES ${CHIBIOS_HAL_SRC_FILE}) + +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(ChibiOS DEFAULT_MSG CHIBIOS_HAL_INCLUDE_DIRS CHIBIOS_HAL_SOURCES) diff --git a/CMake/binutils.ChibiOS.cmake b/CMake/binutils.ChibiOS.cmake index 4ea20983f0..17c75273eb 100644 --- a/CMake/binutils.ChibiOS.cmake +++ b/CMake/binutils.ChibiOS.cmake @@ -84,11 +84,22 @@ function(NF_SET_COMPILER_DEFINITIONS TARGET) endfunction() +function(NF_SET_STM32_TARGET_SERIES) + # process target series, which is in the format "STM32F4xx" + string(REPLACE "STM32" "" TARGET_SERIES_SHORT_1 "${TARGET_SERIES}") + string(REPLACE "xx" "" TARGET_SERIES_SHORT "${TARGET_SERIES_SHORT_1}") + + # store the series short name for later use + set(TARGET_SERIES_SHORT ${TARGET_SERIES_SHORT} CACHE INTERNAL "STM32 target series short name") + +endfunction() + # Add packages that are common to ChibiOS platform builds # To be called from target CMakeList.txt macro(NF_ADD_PLATFORM_PACKAGES) find_package(ChibiOS REQUIRED) + find_package(ChibiOS_${TARGET_SERIES_SHORT}_HAL REQUIRED) find_package(ChibiOSnfOverlay REQUIRED) # ChibiOS contrib repo @@ -130,6 +141,7 @@ macro(NF_ADD_PLATFORM_INCLUDE_DIRECTORIES TARGET) target_include_directories(${TARGET}.elf PUBLIC ${CHIBIOS_INCLUDE_DIRS} + ${CHIBIOS_HAL_INCLUDE_DIRS} ${ChibiOSnfOverlay_INCLUDE_DIRS} ${CHIBIOS_CONTRIB_INCLUDE_DIRS} ${${TARGET_STM32_CUBE_PACKAGE}_CubePackage_INCLUDE_DIRS} @@ -180,6 +192,7 @@ macro(NF_ADD_PLATFORM_SOURCES TARGET) ${${TARGET_STM32_CUBE_PACKAGE}_CubePackage_SOURCES} ${CHIBIOS_SOURCES} + ${CHIBIOS_HAL_SOURCES} ${ChibiOSnfOverlay_SOURCES} ) diff --git a/targets/ChibiOS/CMakeLists.txt b/targets/ChibiOS/CMakeLists.txt index 52fea4509d..e229e64e44 100644 --- a/targets/ChibiOS/CMakeLists.txt +++ b/targets/ChibiOS/CMakeLists.txt @@ -9,6 +9,9 @@ include(binutils.ChibiOS) include(STM32_CubePackage) include(NF_Utils) +# Set target series +NF_SET_STM32_TARGET_SERIES() + # Define PLATFORM base path set(BASE_PATH_FOR_PLATFORM ${CMAKE_CURRENT_SOURCE_DIR} PARENT_SCOPE) From 5aacaa6d105935053b500ab4cf441e385b8270e9 Mon Sep 17 00:00:00 2001 From: nfbot Date: Tue, 13 Jul 2021 19:57:21 +0100 Subject: [PATCH 15/15] Code style fixes (#1983) Automated fixes for code style. --- .../NETDUINO3_WIFI/nanoBooter/chconf.h | 109 ++-- .../NETDUINO3_WIFI/nanoBooter/halconf.h | 4 +- .../NETDUINO3_WIFI/nanoBooter/mcuconf.h | 484 +++++++++--------- .../ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h | 109 ++-- .../ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h | 4 +- .../ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h | 44 +- .../ORGPAL_PALTHREE/nanoBooter/chconf.h | 109 ++-- .../ORGPAL_PALTHREE/nanoBooter/halconf.h | 8 +- .../ORGPAL_PALTHREE/nanoBooter/mcuconf.h | 20 +- .../ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h | 109 ++-- .../ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h | 4 +- .../ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h | 16 +- 12 files changed, 532 insertions(+), 488 deletions(-) diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h index 232dd00ae4..7d04091405 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h @@ -36,7 +36,7 @@ * direct interactions are handled by the OS. */ #if !defined(CH_CFG_SMP_MODE) -#define CH_CFG_SMP_MODE FALSE +#define CH_CFG_SMP_MODE FALSE #endif /** @} */ @@ -651,40 +651,39 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add system custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add system initialization code here.*/ \ -} +#define CH_CFG_SYSTEM_INIT_HOOK() \ + { \ + /* Add system initialization code here.*/ \ + } /** * @brief OS instance structure extension. * @details User fields added to the end of the @p os_instance_t structure. */ -#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ - /* Add OS instance custom fields here.*/ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS /* Add OS instance custom fields here.*/ /** * @brief OS instance initialization hook. * * @param[in] oip pointer to the @p os_instance_t structure */ -#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ - /* Add OS instance initialization code here.*/ \ -} +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) \ + { \ + /* Add OS instance initialization code here.*/ \ + } /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -695,9 +694,10 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} +#define CH_CFG_THREAD_INIT_HOOK(tp) \ + { \ + /* Add threads initialization code here.*/ \ + } /** * @brief Threads finalization hook. @@ -705,9 +705,10 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} +#define CH_CFG_THREAD_EXIT_HOOK(tp) \ + { \ + /* Add threads finalization code here.*/ \ + } /** * @brief Context switch hook. @@ -716,23 +717,26 @@ * @param[in] ntp thread being switched in * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ + { \ + /* Context switch code here.*/ \ + } /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} +#define CH_CFG_IRQ_PROLOGUE_HOOK() \ + { \ + /* IRQ prologue code here.*/ \ + } /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} +#define CH_CFG_IRQ_EPILOGUE_HOOK() \ + { \ + /* IRQ epilogue code here.*/ \ + } /** * @brief Idle thread enter hook. @@ -740,9 +744,10 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} +#define CH_CFG_IDLE_ENTER_HOOK() \ + { \ + /* Idle-enter code here.*/ \ + } /** * @brief Idle thread leave hook. @@ -750,52 +755,58 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} +#define CH_CFG_IDLE_LEAVE_HOOK() \ + { \ + /* Idle-leave code here.*/ \ + } /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} +#define CH_CFG_IDLE_LOOP_HOOK() \ + { \ + /* Idle loop code here.*/ \ + } /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} +#define CH_CFG_SYSTEM_TICK_HOOK() \ + { \ + /* System tick event code here.*/ \ + } /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} +#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ + { \ + /* System halt code here.*/ \ + } /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} +#define CH_CFG_TRACE_HOOK(tep) \ + { \ + /* Trace code here.*/ \ + } /** * @brief Runtime Faults Collection Unit hook. * @details This hook is invoked each time new faults are collected and stored. */ -#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ - /* Faults handling code here.*/ \ -} +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) \ + { \ + /* Faults handling code here.*/ \ + } /** @} */ diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h index 3202c3c52a..2aa384cd33 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h @@ -415,14 +415,14 @@ * default configuration. */ #if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SIO_DEFAULT_BITRATE 38400 +#define SIO_DEFAULT_BITRATE 38400 #endif /** * @brief Support for thread synchronization API. */ #if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) -#define SIO_USE_SYNCHRONIZATION TRUE +#define SIO_USE_SYNCHRONIZATION TRUE #endif /*===========================================================================*/ diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h index 54790f8478..fb2da4df8b 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h @@ -27,51 +27,51 @@ /* * HAL driver system settings. */ -#define STM32_NO_INIT FALSE -#define STM32_HSI_ENABLED TRUE -#define STM32_LSI_ENABLED TRUE -#define STM32_HSE_ENABLED TRUE -#define STM32_LSE_ENABLED FALSE -#define STM32_CLOCK48_REQUIRED TRUE -#define STM32_SW STM32_SW_PLL -#define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 25 -#define STM32_PLLN_VALUE 336 -#define STM32_PLLP_VALUE 2 -#define STM32_PLLQ_VALUE 7 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 -#define STM32_RTCSEL STM32_RTCSEL_LSI -#define STM32_RTCPRE_VALUE 8 -#define STM32_MCO1SEL STM32_MCO1SEL_HSI -#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 -#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK -#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 -#define STM32_I2SSRC STM32_I2SSRC_PLLI2S -#define STM32_PLLI2SN_VALUE 192 -#define STM32_PLLI2SR_VALUE 2 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE /* * IRQ system settings. */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 #define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 #define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 @@ -88,271 +88,271 @@ #define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 #define STM32_IRQ_TIM8_CC_PRIORITY 7 -#define STM32_IRQ_USART1_PRIORITY 12 -#define STM32_IRQ_USART2_PRIORITY 12 -#define STM32_IRQ_USART3_PRIORITY 12 -#define STM32_IRQ_UART4_PRIORITY 12 -#define STM32_IRQ_UART5_PRIORITY 12 -#define STM32_IRQ_USART6_PRIORITY 12 -#define STM32_IRQ_UART7_PRIORITY 12 -#define STM32_IRQ_UART8_PRIORITY 12 +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 /* * ADC driver system settings. */ -#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 -#define STM32_ADC_USE_ADC1 FALSE -#define STM32_ADC_USE_ADC2 FALSE -#define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) -#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#define STM32_ADC_ADC2_DMA_PRIORITY 2 -#define STM32_ADC_ADC3_DMA_PRIORITY 2 -#define STM32_ADC_IRQ_PRIORITY 6 -#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 -#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. */ -#define STM32_CAN_USE_CAN1 FALSE -#define STM32_CAN_USE_CAN2 FALSE -#define STM32_CAN_CAN1_IRQ_PRIORITY 11 -#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 /* * DAC driver system settings. */ -#define STM32_DAC_DUAL_MODE FALSE -#define STM32_DAC_USE_DAC1_CH1 FALSE -#define STM32_DAC_USE_DAC1_CH2 FALSE -#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 -#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) /* * GPT driver system settings. */ -#define STM32_GPT_USE_TIM1 FALSE -#define STM32_GPT_USE_TIM2 FALSE -#define STM32_GPT_USE_TIM3 FALSE -#define STM32_GPT_USE_TIM4 FALSE -#define STM32_GPT_USE_TIM5 FALSE -#define STM32_GPT_USE_TIM6 FALSE -#define STM32_GPT_USE_TIM7 FALSE -#define STM32_GPT_USE_TIM8 FALSE -#define STM32_GPT_USE_TIM9 FALSE -#define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_USE_TIM12 FALSE -#define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 /* * I2C driver system settings. */ -#define STM32_I2C_USE_I2C1 FALSE -#define STM32_I2C_USE_I2C2 FALSE -#define STM32_I2C_USE_I2C3 FALSE -#define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2C_I2C1_IRQ_PRIORITY 5 -#define STM32_I2C_I2C2_IRQ_PRIORITY 5 -#define STM32_I2C_I2C3_IRQ_PRIORITY 5 -#define STM32_I2C_I2C1_DMA_PRIORITY 3 -#define STM32_I2C_I2C2_DMA_PRIORITY 3 -#define STM32_I2C_I2C3_DMA_PRIORITY 3 -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* * I2S driver system settings. */ -#define STM32_I2S_USE_SPI2 FALSE -#define STM32_I2S_USE_SPI3 FALSE -#define STM32_I2S_SPI2_IRQ_PRIORITY 10 -#define STM32_I2S_SPI3_IRQ_PRIORITY 10 -#define STM32_I2S_SPI2_DMA_PRIORITY 1 -#define STM32_I2S_SPI3_DMA_PRIORITY 1 -#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") /* * ICU driver system settings. */ -#define STM32_ICU_USE_TIM1 FALSE -#define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE -#define STM32_ICU_USE_TIM5 FALSE -#define STM32_ICU_USE_TIM8 FALSE -#define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 /* * MAC driver system settings. */ -#define STM32_MAC_TRANSMIT_BUFFERS 2 -#define STM32_MAC_RECEIVE_BUFFERS 4 -#define STM32_MAC_BUFFERS_SIZE 1522 -#define STM32_MAC_PHY_TIMEOUT 100 -#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE -#define STM32_MAC_ETH1_IRQ_PRIORITY 13 -#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE -#define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 /* * SDC driver system settings. */ -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#define STM32_SDC_WRITE_TIMEOUT_MS 250 -#define STM32_SDC_READ_TIMEOUT_MS 25 -#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE -#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) /* * SERIAL driver system settings. */ -#define STM32_SERIAL_USE_USART1 FALSE -#define STM32_SERIAL_USE_USART2 TRUE -#define STM32_SERIAL_USE_USART3 FALSE -#define STM32_SERIAL_USE_UART4 FALSE -#define STM32_SERIAL_USE_UART5 FALSE -#define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE -#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) -#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) -#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* * ST driver system settings. */ -#define STM32_ST_IRQ_PRIORITY 8 -#define STM32_ST_USE_TIMER 2 +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 /* * UART driver system settings. */ -#define STM32_UART_USE_USART1 FALSE -#define STM32_UART_USE_USART2 FALSE -#define STM32_UART_USE_USART3 FALSE -#define STM32_UART_USE_UART4 FALSE -#define STM32_UART_USE_UART5 FALSE -#define STM32_UART_USE_USART6 FALSE -#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) -#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) -#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) -#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) -#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 -#define STM32_UART_USART1_DMA_PRIORITY 0 -#define STM32_UART_USART2_DMA_PRIORITY 0 -#define STM32_UART_USART3_DMA_PRIORITY 0 -#define STM32_UART_UART4_DMA_PRIORITY 0 -#define STM32_UART_UART5_DMA_PRIORITY 0 -#define STM32_UART_USART6_DMA_PRIORITY 0 -#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") /* * USB driver system settings. */ -#define STM32_USB_USE_OTG1 TRUE -#define STM32_USB_USE_OTG2 FALSE -#define STM32_USB_OTG1_IRQ_PRIORITY 14 -#define STM32_USB_OTG2_IRQ_PRIORITY 14 -#define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 /* * WDG driver system settings. */ -#define STM32_WDG_USE_IWDG FALSE +#define STM32_WDG_USE_IWDG FALSE // header for nanoFramework overlay drivers #include "mcuconf_nf.h" diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h index c52486ac50..0f0f0988cf 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h @@ -36,7 +36,7 @@ * direct interactions are handled by the OS. */ #if !defined(CH_CFG_SMP_MODE) -#define CH_CFG_SMP_MODE FALSE +#define CH_CFG_SMP_MODE FALSE #endif /** @} */ @@ -651,40 +651,39 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add system custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add system initialization code here.*/ \ -} +#define CH_CFG_SYSTEM_INIT_HOOK() \ + { \ + /* Add system initialization code here.*/ \ + } /** * @brief OS instance structure extension. * @details User fields added to the end of the @p os_instance_t structure. */ -#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ - /* Add OS instance custom fields here.*/ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS /* Add OS instance custom fields here.*/ /** * @brief OS instance initialization hook. * * @param[in] oip pointer to the @p os_instance_t structure */ -#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ - /* Add OS instance initialization code here.*/ \ -} +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) \ + { \ + /* Add OS instance initialization code here.*/ \ + } /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -695,9 +694,10 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} +#define CH_CFG_THREAD_INIT_HOOK(tp) \ + { \ + /* Add threads initialization code here.*/ \ + } /** * @brief Threads finalization hook. @@ -705,9 +705,10 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} +#define CH_CFG_THREAD_EXIT_HOOK(tp) \ + { \ + /* Add threads finalization code here.*/ \ + } /** * @brief Context switch hook. @@ -716,23 +717,26 @@ * @param[in] ntp thread being switched in * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ + { \ + /* Context switch code here.*/ \ + } /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} +#define CH_CFG_IRQ_PROLOGUE_HOOK() \ + { \ + /* IRQ prologue code here.*/ \ + } /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} +#define CH_CFG_IRQ_EPILOGUE_HOOK() \ + { \ + /* IRQ epilogue code here.*/ \ + } /** * @brief Idle thread enter hook. @@ -740,9 +744,10 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} +#define CH_CFG_IDLE_ENTER_HOOK() \ + { \ + /* Idle-enter code here.*/ \ + } /** * @brief Idle thread leave hook. @@ -750,52 +755,58 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} +#define CH_CFG_IDLE_LEAVE_HOOK() \ + { \ + /* Idle-leave code here.*/ \ + } /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} +#define CH_CFG_IDLE_LOOP_HOOK() \ + { \ + /* Idle loop code here.*/ \ + } /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} +#define CH_CFG_SYSTEM_TICK_HOOK() \ + { \ + /* System tick event code here.*/ \ + } /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} +#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ + { \ + /* System halt code here.*/ \ + } /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} +#define CH_CFG_TRACE_HOOK(tep) \ + { \ + /* Trace code here.*/ \ + } /** * @brief Runtime Faults Collection Unit hook. * @details This hook is invoked each time new faults are collected and stored. */ -#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ - /* Faults handling code here.*/ \ -} +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) \ + { \ + /* Faults handling code here.*/ \ + } /** @} */ diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h index cfd29fc0e3..b52ca80fc6 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h @@ -426,14 +426,14 @@ * default configuration. */ #if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SIO_DEFAULT_BITRATE 38400 +#define SIO_DEFAULT_BITRATE 38400 #endif /** * @brief Support for thread synchronization API. */ #if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) -#define SIO_USE_SYNCHRONIZATION TRUE +#define SIO_USE_SYNCHRONIZATION TRUE #endif /*===========================================================================*/ diff --git a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h index da33b02383..cde08c526a 100644 --- a/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h @@ -61,20 +61,20 @@ /* * IRQ system settings. */ -#define STM32_IRQ_EXTI0_PRIORITY 6 -#define STM32_IRQ_EXTI1_PRIORITY 6 -#define STM32_IRQ_EXTI2_PRIORITY 6 -#define STM32_IRQ_EXTI3_PRIORITY 6 -#define STM32_IRQ_EXTI4_PRIORITY 6 -#define STM32_IRQ_EXTI5_9_PRIORITY 6 -#define STM32_IRQ_EXTI10_15_PRIORITY 6 -#define STM32_IRQ_EXTI16_PRIORITY 6 -#define STM32_IRQ_EXTI17_PRIORITY 15 -#define STM32_IRQ_EXTI18_PRIORITY 6 -#define STM32_IRQ_EXTI19_PRIORITY 6 -#define STM32_IRQ_EXTI20_PRIORITY 6 -#define STM32_IRQ_EXTI21_PRIORITY 15 -#define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 #define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 #define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 @@ -91,14 +91,14 @@ #define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 #define STM32_IRQ_TIM8_CC_PRIORITY 7 -#define STM32_IRQ_USART1_PRIORITY 12 -#define STM32_IRQ_USART2_PRIORITY 12 -#define STM32_IRQ_USART3_PRIORITY 12 -#define STM32_IRQ_UART4_PRIORITY 12 -#define STM32_IRQ_UART5_PRIORITY 12 -#define STM32_IRQ_USART6_PRIORITY 12 -#define STM32_IRQ_UART7_PRIORITY 12 -#define STM32_IRQ_UART8_PRIORITY 12 +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 /* * ADC driver system settings. diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/chconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/chconf.h index 232dd00ae4..7d04091405 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/chconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/chconf.h @@ -36,7 +36,7 @@ * direct interactions are handled by the OS. */ #if !defined(CH_CFG_SMP_MODE) -#define CH_CFG_SMP_MODE FALSE +#define CH_CFG_SMP_MODE FALSE #endif /** @} */ @@ -651,40 +651,39 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add system custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add system initialization code here.*/ \ -} +#define CH_CFG_SYSTEM_INIT_HOOK() \ + { \ + /* Add system initialization code here.*/ \ + } /** * @brief OS instance structure extension. * @details User fields added to the end of the @p os_instance_t structure. */ -#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ - /* Add OS instance custom fields here.*/ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS /* Add OS instance custom fields here.*/ /** * @brief OS instance initialization hook. * * @param[in] oip pointer to the @p os_instance_t structure */ -#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ - /* Add OS instance initialization code here.*/ \ -} +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) \ + { \ + /* Add OS instance initialization code here.*/ \ + } /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -695,9 +694,10 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} +#define CH_CFG_THREAD_INIT_HOOK(tp) \ + { \ + /* Add threads initialization code here.*/ \ + } /** * @brief Threads finalization hook. @@ -705,9 +705,10 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} +#define CH_CFG_THREAD_EXIT_HOOK(tp) \ + { \ + /* Add threads finalization code here.*/ \ + } /** * @brief Context switch hook. @@ -716,23 +717,26 @@ * @param[in] ntp thread being switched in * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ + { \ + /* Context switch code here.*/ \ + } /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} +#define CH_CFG_IRQ_PROLOGUE_HOOK() \ + { \ + /* IRQ prologue code here.*/ \ + } /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} +#define CH_CFG_IRQ_EPILOGUE_HOOK() \ + { \ + /* IRQ epilogue code here.*/ \ + } /** * @brief Idle thread enter hook. @@ -740,9 +744,10 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} +#define CH_CFG_IDLE_ENTER_HOOK() \ + { \ + /* Idle-enter code here.*/ \ + } /** * @brief Idle thread leave hook. @@ -750,52 +755,58 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} +#define CH_CFG_IDLE_LEAVE_HOOK() \ + { \ + /* Idle-leave code here.*/ \ + } /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} +#define CH_CFG_IDLE_LOOP_HOOK() \ + { \ + /* Idle loop code here.*/ \ + } /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} +#define CH_CFG_SYSTEM_TICK_HOOK() \ + { \ + /* System tick event code here.*/ \ + } /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} +#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ + { \ + /* System halt code here.*/ \ + } /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} +#define CH_CFG_TRACE_HOOK(tep) \ + { \ + /* Trace code here.*/ \ + } /** * @brief Runtime Faults Collection Unit hook. * @details This hook is invoked each time new faults are collected and stored. */ -#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ - /* Faults handling code here.*/ \ -} +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) \ + { \ + /* Faults handling code here.*/ \ + } /** @} */ diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/halconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/halconf.h index 93132a85e1..7ca5642d80 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/halconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/halconf.h @@ -415,14 +415,14 @@ * default configuration. */ #if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SIO_DEFAULT_BITRATE 38400 +#define SIO_DEFAULT_BITRATE 38400 #endif /** * @brief Support for thread synchronization API. */ #if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) -#define SIO_USE_SYNCHRONIZATION TRUE +#define SIO_USE_SYNCHRONIZATION TRUE #endif /*===========================================================================*/ @@ -435,14 +435,14 @@ * default configuration. */ #if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SIO_DEFAULT_BITRATE 38400 +#define SIO_DEFAULT_BITRATE 38400 #endif /** * @brief Support for thread synchronization API. */ #if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) -#define SIO_USE_SYNCHRONIZATION TRUE +#define SIO_USE_SYNCHRONIZATION TRUE #endif /*===========================================================================*/ diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h index ce62b8eddc..9ed3334f02 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h @@ -307,14 +307,14 @@ /* * SIO driver system settings. */ -#define STM32_SIO_USE_USART1 FALSE -#define STM32_SIO_USE_USART2 FALSE -#define STM32_SIO_USE_USART3 FALSE -#define STM32_SIO_USE_UART4 FALSE -#define STM32_SIO_USE_UART5 FALSE -#define STM32_SIO_USE_USART6 FALSE -#define STM32_SIO_USE_UART7 FALSE -#define STM32_SIO_USE_UART8 FALSE +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE /* * SPI driver system settings. @@ -420,8 +420,8 @@ /* * WSPI driver system settings. */ -#define STM32_WSPI_USE_QUADSPI1 FALSE -#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 2 // header for nanoFramework overlay drivers diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h index c52486ac50..0f0f0988cf 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/chconf.h @@ -36,7 +36,7 @@ * direct interactions are handled by the OS. */ #if !defined(CH_CFG_SMP_MODE) -#define CH_CFG_SMP_MODE FALSE +#define CH_CFG_SMP_MODE FALSE #endif /** @} */ @@ -651,40 +651,39 @@ * @brief System structure extension. * @details User fields added to the end of the @p ch_system_t structure. */ -#define CH_CFG_SYSTEM_EXTRA_FIELDS \ - /* Add system custom fields here.*/ +#define CH_CFG_SYSTEM_EXTRA_FIELDS /* Add system custom fields here.*/ /** * @brief System initialization hook. * @details User initialization code added to the @p chSysInit() function * just before interrupts are enabled globally. */ -#define CH_CFG_SYSTEM_INIT_HOOK() { \ - /* Add system initialization code here.*/ \ -} +#define CH_CFG_SYSTEM_INIT_HOOK() \ + { \ + /* Add system initialization code here.*/ \ + } /** * @brief OS instance structure extension. * @details User fields added to the end of the @p os_instance_t structure. */ -#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ - /* Add OS instance custom fields here.*/ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS /* Add OS instance custom fields here.*/ /** * @brief OS instance initialization hook. * * @param[in] oip pointer to the @p os_instance_t structure */ -#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ - /* Add OS instance initialization code here.*/ \ -} +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) \ + { \ + /* Add OS instance initialization code here.*/ \ + } /** * @brief Threads descriptor structure extension. * @details User fields added to the end of the @p thread_t structure. */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ +#define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/ /** * @brief Threads initialization hook. @@ -695,9 +694,10 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} +#define CH_CFG_THREAD_INIT_HOOK(tp) \ + { \ + /* Add threads initialization code here.*/ \ + } /** * @brief Threads finalization hook. @@ -705,9 +705,10 @@ * * @param[in] tp pointer to the @p thread_t structure */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} +#define CH_CFG_THREAD_EXIT_HOOK(tp) \ + { \ + /* Add threads finalization code here.*/ \ + } /** * @brief Context switch hook. @@ -716,23 +717,26 @@ * @param[in] ntp thread being switched in * @param[in] otp thread being switched out */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \ + { \ + /* Context switch code here.*/ \ + } /** * @brief ISR enter hook. */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} +#define CH_CFG_IRQ_PROLOGUE_HOOK() \ + { \ + /* IRQ prologue code here.*/ \ + } /** * @brief ISR exit hook. */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} +#define CH_CFG_IRQ_EPILOGUE_HOOK() \ + { \ + /* IRQ epilogue code here.*/ \ + } /** * @brief Idle thread enter hook. @@ -740,9 +744,10 @@ * should be invoked from here. * @note This macro can be used to activate a power saving mode. */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} +#define CH_CFG_IDLE_ENTER_HOOK() \ + { \ + /* Idle-enter code here.*/ \ + } /** * @brief Idle thread leave hook. @@ -750,52 +755,58 @@ * should be invoked from here. * @note This macro can be used to deactivate a power saving mode. */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-leave code here.*/ \ -} +#define CH_CFG_IDLE_LEAVE_HOOK() \ + { \ + /* Idle-leave code here.*/ \ + } /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} +#define CH_CFG_IDLE_LOOP_HOOK() \ + { \ + /* Idle loop code here.*/ \ + } /** * @brief System tick event hook. * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} +#define CH_CFG_SYSTEM_TICK_HOOK() \ + { \ + /* System tick event code here.*/ \ + } /** * @brief System halt hook. * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} +#define CH_CFG_SYSTEM_HALT_HOOK(reason) \ + { \ + /* System halt code here.*/ \ + } /** * @brief Trace hook. * @details This hook is invoked each time a new record is written in the * trace buffer. */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} +#define CH_CFG_TRACE_HOOK(tep) \ + { \ + /* Trace code here.*/ \ + } /** * @brief Runtime Faults Collection Unit hook. * @details This hook is invoked each time new faults are collected and stored. */ -#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ - /* Faults handling code here.*/ \ -} +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) \ + { \ + /* Faults handling code here.*/ \ + } /** @} */ diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h index 676e4345b4..ccc3d647cb 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/halconf.h @@ -427,14 +427,14 @@ * default configuration. */ #if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SIO_DEFAULT_BITRATE 38400 +#define SIO_DEFAULT_BITRATE 38400 #endif /** * @brief Support for thread synchronization API. */ #if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) -#define SIO_USE_SYNCHRONIZATION TRUE +#define SIO_USE_SYNCHRONIZATION TRUE #endif /*===========================================================================*/ diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h index 5add6edd29..126a26cae4 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h @@ -307,14 +307,14 @@ /* * SIO driver system settings. */ -#define STM32_SIO_USE_USART1 FALSE -#define STM32_SIO_USE_USART2 FALSE -#define STM32_SIO_USE_USART3 FALSE -#define STM32_SIO_USE_UART4 FALSE -#define STM32_SIO_USE_UART5 FALSE -#define STM32_SIO_USE_USART6 FALSE -#define STM32_SIO_USE_UART7 FALSE -#define STM32_SIO_USE_UART8 FALSE +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE /* * SPI driver system settings.