From 7ca447f0ccc3df964e95892d0ec16a44521f27f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 29 Jan 2018 14:07:30 +0000 Subject: [PATCH 01/90] Initial work on adding support for CC3200 Launchpad MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- CMake/Modules/FindCC3200_SDK.cmake | 171 ++++++++++++++ CMake/Modules/TIRTOS_CC3200_GCC_options.cmake | 56 +++++ CMake/toolchain.TIRTOS.GCC.cmake | 168 +++++++++++++ CMakeLists.txt | 31 ++- cmake-variants.TEMPLATE.json | 7 +- targets/TI-RTOS/CC3200/CMakeLists.txt | 154 ++++++++++++ targets/TI-RTOS/CC3200/nanoCLR/CMakeLists.txt | 12 + targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld | 94 ++++++++ targets/TI-RTOS/CC3200/nanoCLR/main.c | 222 ++++++++++++++++++ targets/TI-RTOS/CC3200/nanoCLR/pinmux.c | 80 +++++++ targets/TI-RTOS/CC3200/nanoCLR/pinmux.h | 49 ++++ .../TI-RTOS/CC3200/nanoCLR/target_board.h.in | 19 ++ targets/TI-RTOS/CC3200/target_common.c | 31 +++ targets/TI-RTOS/CC3200/target_common.h.in | 33 +++ targets/TI-RTOS/common/include/target_types.h | 101 ++++++++ 15 files changed, 1225 insertions(+), 3 deletions(-) create mode 100644 CMake/Modules/FindCC3200_SDK.cmake create mode 100644 CMake/Modules/TIRTOS_CC3200_GCC_options.cmake create mode 100644 CMake/toolchain.TIRTOS.GCC.cmake create mode 100644 targets/TI-RTOS/CC3200/CMakeLists.txt create mode 100644 targets/TI-RTOS/CC3200/nanoCLR/CMakeLists.txt create mode 100644 targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld create mode 100644 targets/TI-RTOS/CC3200/nanoCLR/main.c create mode 100644 targets/TI-RTOS/CC3200/nanoCLR/pinmux.c create mode 100644 targets/TI-RTOS/CC3200/nanoCLR/pinmux.h create mode 100644 targets/TI-RTOS/CC3200/nanoCLR/target_board.h.in create mode 100644 targets/TI-RTOS/CC3200/target_common.c create mode 100644 targets/TI-RTOS/CC3200/target_common.h.in create mode 100644 targets/TI-RTOS/common/include/target_types.h diff --git a/CMake/Modules/FindCC3200_SDK.cmake b/CMake/Modules/FindCC3200_SDK.cmake new file mode 100644 index 0000000000..ebd4b2e088 --- /dev/null +++ b/CMake/Modules/FindCC3200_SDK.cmake @@ -0,0 +1,171 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# and here the GCC options tuned for the target series +include(TIRTOS_CC3200_GCC_options) + +# set include directories for CC3200 SDK +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/example/common) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/inc) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/driverlib) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/driver) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/driver/hal) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/framework/pm) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/framework/timer) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/soc) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/oslib) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink/include) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/include) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/flc) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/ota) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/provisioninglib) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/TI-RTOS/common/include) + +# XDC tools includes +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_XDCTOOLS_INSTALLATION_DIR}/packages) +list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_XDCTOOLS_INSTALLATION_DIR}/packages/xdc) +# list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/xdc) +# list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/ti/targets) + +# source files for CC3200 SDK +set(CC3200_SDK_SRCS + + # examples common + button_if.c + gpio_if.c + i2c_if.c + i2s_if.c + network_common.c + network_if.c + startup_gcc.c + timer_if.c + uart_if.c + udma_if.c + utils_if.c + wdt_if.c + + # drivers + # adc.c + # aes.c + # camera.c + # cpu.c + # crc.c + # des.c + # flash.c + # gpio.c + # i2c.c + # i2s.c + # interrupt.c + # pin.c + # prcm.c + # sdhost.c + # shamd5.c + # spi.c + # systick.c + # timer.c + # uart.c + # udma.c + # utils.c + # wdt.c + + # middleware/driver/hal + # dma_hal.c + # gpio_hal.c + # hw_timer32.c + # hw_timer32.c + # rtc_hal.c + # spi_hal.c + # uart_hal.c + # util64.c + + # middleware/driver + # spi_drv.c + # uart_drv.c + + # middleware/framework/pm + # cc_pm.c + + # middleware/framework/timer + # cc_timer.c + + # middleware/soc + # cc_io_park.c + # cc_pm_ops.c + + # netapps + + # oslib + # osi_tirtos.c + + # simplelink + # cc_pal_pm.c + # cc_pal.c + # device.c + # flowcont.c + # fs.c + # netapp.c + # netcfg.c + # nonos.c + # socket.c + # spawn.c + # wlan.c + + # simplelink_extlib + # flc.c + # CdnClient.c + # LogClient.c + # OtaApp.c + # OtaClient.c + # OtaHttp.c + # cfg_confirm.c + # events_handler.c + # networkListHndl.c + # provisioning_logic.c + +) + +foreach(SRC_FILE ${CC3200_SDK_SRCS}) + set(CC3200_SDK_FILE SRC_FILE -NOTFOUND) + find_file(CC3200_SDK_FILE ${SRC_FILE} + PATHS + + # examples common + ${TI_CC3200_SDK_PATH}/example/common + + # drivers + ${TI_CC3200_SDK_PATH}/driverlib + + # middleware + ${TI_CC3200_SDK_PATH}/middleware/driver + ${TI_CC3200_SDK_PATH}/middleware/driver/hal + ${TI_CC3200_SDK_PATH}/middleware/framework/pm + ${TI_CC3200_SDK_PATH}/middleware/framework/timer + ${TI_CC3200_SDK_PATH}/middleware/soc + + # netapps + + # oslib + ${TI_CC3200_SDK_PATH}/oslib + + # simplelink + ${TI_CC3200_SDK_PATH}/simplelink + ${TI_CC3200_SDK_PATH}/simplelink/source + + # simplelink_extlib + ${TI_CC3200_SDK_PATH}/simplelink_extlib/flc + ${TI_CC3200_SDK_PATH}/simplelink_extlib/ota + ${TI_CC3200_SDK_PATH}/simplelink_extlib/provisioninglib + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${CC3200_SDK_FILE}") # debug helper + list(APPEND CC3200_SDK_SOURCES ${CC3200_SDK_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(CC3200_SDK DEFAULT_MSG CC3200_SDK_INCLUDE_DIRS CC3200_SDK_SOURCES) diff --git a/CMake/Modules/TIRTOS_CC3200_GCC_options.cmake b/CMake/Modules/TIRTOS_CC3200_GCC_options.cmake new file mode 100644 index 0000000000..996d62f1ea --- /dev/null +++ b/CMake/Modules/TIRTOS_CC3200_GCC_options.cmake @@ -0,0 +1,56 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# FPU preference for using hardware FP unit or soft library +if(USE_FPU_IS_TRUE) + set(FLOAT_ABI_OPTION "-mfloat-abi=hard") +elseif() + set(FLOAT_ABI_OPTION "-mfloat-abi=soft") +endif() + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options bellow +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +# -mfpu=fpv5-sp-d16 +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -march=armv7e-m -mfpu=fpv4-sp-d16 -mabi=aapcs -nostartfiles -Wl,-T,${TIRTOS_BIOS_INSTALLATION_DIR}/ti/platforms/simplelink/include_gnu/cc3200.lds -lgcc -lc -lm -lrdimon " CACHE INTERNAL "executable linker flags") + + +function(NF_SET_COMPILER_OPTIONS TARGET) + + # include any extra options comming from any extra args? + target_compile_options(${TARGET} PUBLIC ${ARGN} -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -march=armv7e-m -mfpu=fpv4-sp-d16 -gstrict-dwarf -mabi=aapcs -nostdlib -Wall -w -static -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -mstructure-size-boundary=8 -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) + +endfunction() + + +function(NF_SET_LINKER_OPTIONS TARGET PRINTF_FLOAT_SUPPORT) + + # request to include support for float printf form newlib nano + if(PRINTF_FLOAT_SUPPORT) + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs -u _printf_float") + else() + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") + endif() + + # set extra linker flags + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fno-strict-aliasing ") + endif() + + # set optimization flags + nf_set_optimization_options(${TARGET}) + + # set link map + nf_set_link_map(${TARGET}) + +endfunction() diff --git a/CMake/toolchain.TIRTOS.GCC.cmake b/CMake/toolchain.TIRTOS.GCC.cmake new file mode 100644 index 0000000000..da2017ee47 --- /dev/null +++ b/CMake/toolchain.TIRTOS.GCC.cmake @@ -0,0 +1,168 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +INCLUDE(CMakeForceCompiler) +# if( DEFINED CMAKE_CROSSCOMPILING ) +# # subsequent toolchain loading is not really needed +# return() +# endif() + + +################################################### +# set C and C++ flags for compiler detection tests +################################################### +# IMPORTANT: these flags need to be removed after +# the compiler detection otherwise they'll get +# added to all compiler build calls and +# will colide with the use of nano.specs +################################################### +set(CMAKE_C_FLAGS_INIT "-specs=nosys.specs") +set(CMAKE_CXX_FLAGS_INIT "-specs=nosys.specs") +################################################### + + +# set toolchain directories +set(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_PREFIX}/bin) +set(TOOLCHAIN_INC_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/include) +set(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/lib) + +# the name of the operating system for which CMake is to build +set(CMAKE_SYSTEM_NAME Generic) + +# name of the CPU CMake is building for +set(CMAKE_SYSTEM_PROCESSOR arm) + +# macro to setup compilers +macro(SET_COMPILER_VAR var name) + find_program(CMAKE_${var} arm-none-eabi-${name} HINTS ${TOOLCHAIN_BIN_DIR} DOC "${name} tool") +endmacro() + +# setup C compiler +if(NOT CMAKE_C_COMPILER) + SET_COMPILER_VAR(C_COMPILER gcc) +endif() + +# setup C++ compiler +if(NOT CMAKE_CXX_COMPILER) + SET_COMPILER_VAR(CXX_COMPILER g++) +endif() + +# setup Assembler compiler +SET_COMPILER_VAR(ASM-ATT_COMPILER as) + +# other toolchain configurations +set(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objcopy CACHE INTERNAL "objcopy tool") +set(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objdump CACHE INTERNAL "objdump tool") +set(CMAKE_SIZE ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-size CACHE INTERNAL "size tool") +set(CMAKE_DEBUGER ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-gdb CACHE INTERNAL "debuger") + +# root paths to search on the filesystem for cross-compiling +set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_PREFIX}/arm-none-eabi ${EXTRA_FIND_PATH}) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +# set required C and C++ standard for ALL targets +set(CMAKE_C_STANDARD 11 CACHE INTERNAL "C standard for all targets") +set(CMAKE_CXX_STANDARD 11 CACHE INTERNAL "C++ standard for all targets") + +# set all C and C++ extensions to be OFF on ALL targets +# this forces the use of -std=c11 and -std=c++11 instead of -std=gnu11 and -std=gnu++11 +set(CMAKE_C_EXTENSIONS OFF CACHE INTERNAL "C compiler extensions OFF") +set(CMAKE_CXX_EXTENSIONS OFF CACHE INTERNAL "C++ compiler extensions OFF") + + +function(NF_ADD_HEX_BIN_DUMP_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + + # add targets for HEX, BIN and S19 formats with no output so they will always be built + add_custom_target(${TARGET}.hex DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Oihex ${FILENAME} ${FILENAME}.hex) + add_custom_target(${TARGET}.s19 DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Osrec ${FILENAME} ${FILENAME}.s19) + add_custom_target(${TARGET}.bin DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Obinary ${FILENAME} ${FILENAME}.bin) + add_custom_target(${TARGET}.dump DEPENDS ${TARGET} COMMAND ${CMAKE_OBJDUMP} -d -EL -S ${FILENAME} ${FILENAME}.dump) +endfunction() + + +function(NF_PRINT_SIZE_OF_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} ${FILENAME}) +endfunction() + + +function(NF_SET_OPTIMIZATION_OPTIONS TARGET) + + target_compile_options(${TARGET} PRIVATE + $<$:-Og -femit-class-debug-always -g3 -ggdb> + $<$:-O3 -flto -fno-strict-aliasing> + $<$:-Os -flto -fno-strict-aliasing> + $<$:-Os -femit-class-debug-always -g3 -ggdb> + ) + +endfunction() + + +function(NF_SET_LINK_MAP TARGET) + + # need to remove the .elf suffix from target name + string(FIND ${TARGET} "." TARGET_EXTENSION_DOT_INDEX) + string(SUBSTRING ${TARGET} 0 ${TARGET_EXTENSION_DOT_INDEX} TARGET_SHORT) + + # add linker flags to generate map file + set_property(TARGET ${TARGET_SHORT}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=${PROJECT_SOURCE_DIR}/build/${TARGET_SHORT}.map,--library-path=${PROJECT_SOURCE_DIR}/targets/TI-RTOS/CC3200/nanoCLR") + +endfunction() + + +function(NF_SET_COMPILER_DEFINITIONS TARGET) + + # definition for platform (always ARM here) + target_compile_definitions(${TARGET} PUBLIC "-DPLATFORM_ARM ") + + # definition for platform + target_compile_definitions(${TARGET} PUBLIC "-Dgcc -DPART_CC3200 -DUSE_TIRTOS -DCCWARE -DSL_FULL -DSL_PLATFORM_MULTI_THREADED -DTARGET_IS_CC3200 -Dxdc_target_types__=target_types.h") + + # set compiler definitions related with the build type + if(CMAKE_BUILD_TYPE STREQUAL "Debug" OR CMAKE_BUILD_TYPE STREQUAL "RelWithDebInfo") + # build types that include debug have the define 'NANOCLR_ENABLE_SOURCELEVELDEBUGGING' + target_compile_definitions(${TARGET} PUBLIC "-DNANOCLR_ENABLE_SOURCELEVELDEBUGGING ") + endif() + + # set compiler definition for RTM build option + if(NF_BUILD_RTM) + target_compile_definitions(${TARGET} PUBLIC BUILD_RTM) + endif() + + # set compiler definition for platform emulated floating point according to FPU + # no FPU requires FP emulation from the platform + target_compile_definitions(${TARGET} PUBLIC $<$>:-DPLATFORM_EMULATED_FLOATINGPOINT>) + + # set compiler definition for CORTEX according to FPU + target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=$<$:TRUE>$<$>:FALSE>) + + # set compiler definition for using Application Domains feature + if(NF_FEATURE_USE_APPDOMAINS) + target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_USE_APPDOMAINS) + endif() + + # set definition for Wire Protocol trace mask + target_compile_definitions(${TARGET} PUBLIC -DTRACE_MASK=${WP_TRACE_MASK}) + +endfunction() + + +function(NF_SET_LINKER_FILE TARGET LINKER_FILE_NAME) + + # set linker file name + set_target_properties(${TARGET} PROPERTIES LINK_FLAGS "-T${LINKER_FILE_NAME}") + +endfunction() diff --git a/CMakeLists.txt b/CMakeLists.txt index 5c924e0378..6469a4ebfd 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,7 +53,7 @@ endif() # list of supported RTOSes # when adding a new RTOS add the corresponding string bellow AND... # ... also on the compare block bellow -set(RTOS_SUPPORTED "CHIBIOS" "FREERTOS_ESP32" CACHE INTERNAL "supported RTOS options") +set(RTOS_SUPPORTED "CHIBIOS" "FREERTOS_ESP32" "TIRTOS" CACHE INTERNAL "supported RTOS options") list(FIND RTOS_SUPPORTED ${RTOS} RTOS_INDEX) if(RTOS_INDEX EQUAL -1) @@ -63,18 +63,27 @@ else() endif() string(COMPARE EQUAL "CHIBIOS" "${RTOS}" RTOS_CHIBIOS_CHECK) -string(COMPARE EQUAL "FREERTOS_ESP32" "${RTOS}" RTOS_FREERTOS_ESP32_CHECK) +string(COMPARE EQUAL "FREERTOS_ESP32" "${RTOS}" RTOS_FREERTOS_CHECK) +string(COMPARE EQUAL "TIRTOS" "${RTOS}" RTOS_TIRTOS_CHECK) ########################################################################## if(RTOS_FREERTOS_ESP32_CHECK) set(RTOS_FREERTOS_ESP32_CHECK TRUE) set(RTOS_CHIBIOS_CHECK FALSE) + set(RTOS_TIRTOS_CHECK FALSE) endif() if(RTOS_CHIBIOS_CHECK) set(RTOS_CHIBIOS_CHECK TRUE) set(RTOS_FREERTOS_ESP32_CHECK FALSE) + set(RTOS_TIRTOS_CHECK FALSE) +endif() + +if(RTOS_TIRTOS_CHECK) + set(RTOS_CHIBIOS_CHECK FALSE) + set(RTOS_FREERTOS_ESP32_CHECK FALSE) + set(RTOS_TIRTOS_CHECK TRUE) endif() ####################### @@ -143,6 +152,11 @@ elseif(RTOS_FREERTOS_ESP32_CHECK) # # set toolchain file # set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.${CHIP_VENDOR_STM32}.${TOOLCHAIN}.cmake) + +elseif(RTOS_TIRTOS_CHECK) + message(STATUS "\nSetting Toolchain file for TI-RTOS \n") + set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.TIRTOS.${TOOLCHAIN}.cmake) + endif() ######################################### @@ -1101,4 +1115,17 @@ elseif(RTOS_FREERTOS_ESP32_CHECK) endif() +####################### +# TI-RTOS +elseif(RTOS_TIRTOS_CHECK) + + if("${TARGET_SERIES}" STREQUAL "TICC3200") + message("Platform TICC3200") + + # Define base path for the class libraries + set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/TI-RTOS/CC3200/nanoCLR") + + add_subdirectory(targets/TI-RTOS/CC3200) + endif() + endif() diff --git a/cmake-variants.TEMPLATE.json b/cmake-variants.TEMPLATE.json index 6690fbc7e2..0979011a61 100644 --- a/cmake-variants.TEMPLATE.json +++ b/cmake-variants.TEMPLATE.json @@ -34,13 +34,18 @@ "BUILD_VERSION" : "0.9.99.999", "TOOLCHAIN_PREFIX" : "", "TOOL_HEX2DFU_PREFIX" : "", + "TI_CC3200_SDK_PATH" : "", + "TI_XDCTOOLS_INSTALLATION_DIR" : "", + "TIRTOS_BIOS_INSTALLATION_DIR" : "", + "TIRTOS_UIA_INSTALLATION_DIR" : "", + "TARGET_SERIES" : "", "ESP32_IDF_PATH" : "/esp-idf", "ESP32_LIBS_PATH" : "/libs", "TARGET_SERIES" : "", "USE_RNG" : "", "DP_FLOATINGPOINT" : "", "SUPPORT_ANY_BASE_CONVERSION" : "", - "RTOS" : "", + "RTOS" : "", "CHIBIOS_SOURCE" : "", "CHIBIOS_CONTRIB_REQUIRED" : "OFF-default-ON-to-include_ChibiOS-Contrib-repository-in-the-build", "CHIBIOS_CONTRIB_SOURCE" : "", diff --git a/targets/TI-RTOS/CC3200/CMakeLists.txt b/targets/TI-RTOS/CC3200/CMakeLists.txt new file mode 100644 index 0000000000..a2231eb182 --- /dev/null +++ b/targets/TI-RTOS/CC3200/CMakeLists.txt @@ -0,0 +1,154 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +# configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" +# "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +# set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(CC3200_SDK REQUIRED) +find_package(BuildUtils REQUIRED) +# find_package(CHIBIOS REQUIRED) +# find_package(ChibiOSnfOverlay REQUIRED) +# find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +# find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# # nF feature: debugger +# if(NF_FEATURE_DEBUGGER) +# find_package(NF_Debugger REQUIRED) +# find_package(NF_Diagnostics REQUIRED) +# endif() + +# # nF feature: networking +# if(USE_NETWORKING_OPTION) +# find_package(CHIBIOS_LWIP REQUIRED) +# endif() + +# # nF feature: filesystem +# if(USE_FILESYSTEM_OPTION) +# find_package(CHIBIOS_FATFS REQUIRED) +# endif() + +####################################### + + +# add_subdirectory("common") +# add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +# ####################### +# # nanoBooter executable + +# add_executable( +# # executables for project, project sources +# ${NANOBOOTER_PROJECT_NAME}.elf + +# "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + +# ${COMMON_PROJECT_SOURCES} +# ${NANOBOOTER_PROJECT_SOURCES} + +# ${TARGET_CMSIS_COMMON_SOURCES} +# ${TARGET_CMSIS_NANOBOOTER_SOURCES} + +# ${TARGET_CHIBIOS_COMMON_SOURCES} +# ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + +# ${CHIBIOS_SOURCES} +# ${ChibiOSnfOverlay_SOURCES} + +# ${WireProtocol_SOURCES} +# ) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + # "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + # ${TARGET_CMSIS_COMMON_SOURCES} + # ${TARGET_CMSIS_NANOCLR_SOURCES} + + # ${TARGET_CHIBIOS_COMMON_SOURCES} + # ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CC3200_SDK_SOURCES} + # ${ChibiOSnfOverlay_SOURCES} + + # sources for nanoFramework libraries + # "${NF_CoreCLR_SOURCES}" + # "${NF_Debugger_SOURCES}" + # "${NF_Diagnostics_SOURCES}" + + # sources for nanoFramework APIs + # "${TARGET_NANO_APIS_SOURCES}" +) + + +# include common directories +include_directories( + "${CMAKE_CURRENT_BINARY_DIR}" + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + # ${PROJECT_SOURCE_DIR}/src/CLR/Core + # ${PROJECT_SOURCE_DIR}/src/CLR/Include + # ${PROJECT_SOURCE_DIR}/src/HAL/Include + # ${PROJECT_SOURCE_DIR}/src/PAL/Include + + # ${WireProtocol_INCLUDE_DIRS} + ${CC3200_SDK_INCLUDE_DIRS} + # ${ChibiOSnfOverlay_INCLUDE_DIRS} + + # ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + # ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# set compiler options +# nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +# nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker file +# nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F76xx_booter.ld) +nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/cc3200_CLR.ld) + +# set linker options +# using FPU requires enabling printf with FP support for newlib nano, but just for nanoCLR target, don't need to overload nanoBooter with that +# nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf FALSE) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf FALSE) + +# add libraries +target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/driverlib/gcc/exe/libdriver.a) +target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/simplelink/gcc/exe/libsimplelink.a) +target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/oslib/gcc/exe/libtirtos.a) + +# generate output files +# nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/targets/TI-RTOS/CC3200/nanoCLR/CMakeLists.txt b/targets/TI-RTOS/CC3200/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..3bd60b1509 --- /dev/null +++ b/targets/TI-RTOS/CC3200/nanoCLR/CMakeLists.txt @@ -0,0 +1,12 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/pinmux.c") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld b/targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld new file mode 100644 index 0000000000..580c8a01e6 --- /dev/null +++ b/targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld @@ -0,0 +1,94 @@ +/***************************************************************************** +* blinky.ld +* +* GCC Linker script for blinky application. +* +* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + + +HEAP_SIZE = 0x00010000; + +MEMORY +{ + /* SRAM size of 240KB for cc3200 ES 1.33 device onward */ + SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 0x3C000 +} + +SECTIONS +{ + .text : + { + _text = .; + KEEP(*(.intvecs)) + *(.text*) + *(.rodata*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + _etext = .; + } > SRAM + + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > SRAM + + __init_data = .; + + .data : AT(__init_data) + { + _data = .; + *(.data*) + . = ALIGN (8); + _edata = .; + } > SRAM + + .bss : + { + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + } > SRAM + + .heap : + { + _heap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + + } +} + diff --git a/targets/TI-RTOS/CC3200/nanoCLR/main.c b/targets/TI-RTOS/CC3200/nanoCLR/main.c new file mode 100644 index 0000000000..e9431873ca --- /dev/null +++ b/targets/TI-RTOS/CC3200/nanoCLR/main.c @@ -0,0 +1,222 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// Application Name - Blinky +// Application Overview - The objective of this application is to showcase the +// GPIO control using Driverlib api calls. The LEDs +// connected to the GPIOs on the LP are used to indicate +// the GPIO output. The GPIOs are driven high-low +// periodically in order to turn on-off the LEDs. +// Application Details - +// http://processors.wiki.ti.com/index.php/CC32xx_Blinky_Application +// or +// docs\examples\CC32xx_Blinky_Application.pdf +// +//***************************************************************************** + +//**************************************************************************** +// +//! \addtogroup blinky +//! @{ +// +//**************************************************************************** + +// Standard includes +#include + +// Driverlib includes +#include "hw_types.h" +#include "hw_ints.h" +#include "hw_memmap.h" +#include "hw_common_reg.h" +#include "interrupt.h" +#include "hw_apps_rcm.h" +#include "prcm.h" +#include "rom.h" +#include "rom_map.h" +#include "prcm.h" +#include "gpio.h" +#include "utils.h" + +// Common interface includes +#include "gpio_if.h" + +#include "pinmux.h" + +#define APPLICATION_VERSION "1.1.1" + +//***************************************************************************** +// GLOBAL VARIABLES -- Start +//***************************************************************************** +#if defined(ccs) +extern void (* const g_pfnVectors[])(void); +#endif +#if defined(ewarm) +extern uVectorEntry __vector_table; +#endif +//***************************************************************************** +// GLOBAL VARIABLES -- End +//***************************************************************************** + + +//***************************************************************************** +// LOCAL FUNCTION PROTOTYPES +//***************************************************************************** +void LEDBlinkyRoutine(); +static void BoardInit(void); + +//***************************************************************************** +// LOCAL FUNCTION DEFINITIONS +//***************************************************************************** + +//***************************************************************************** +// +//! Configures the pins as GPIOs and peroidically toggles the lines +//! +//! \param None +//! +//! This function +//! 1. Configures 3 lines connected to LEDs as GPIO +//! 2. Sets up the GPIO pins as output +//! 3. Periodically toggles each LED one by one by toggling the GPIO line +//! +//! \return None +// +//***************************************************************************** +void LEDBlinkyRoutine() +{ + // + // Toggle the lines initially to turn off the LEDs. + // The values driven are as required by the LEDs on the LP. + // + GPIO_IF_LedOff(MCU_ALL_LED_IND); + while(1) + { + // + // Alternately toggle hi-low each of the GPIOs + // to switch the corresponding LED on/off. + // + MAP_UtilsDelay(8000000); + GPIO_IF_LedOn(MCU_RED_LED_GPIO); + MAP_UtilsDelay(8000000); + GPIO_IF_LedOff(MCU_RED_LED_GPIO); + MAP_UtilsDelay(8000000); + GPIO_IF_LedOn(MCU_ORANGE_LED_GPIO); + MAP_UtilsDelay(8000000); + GPIO_IF_LedOff(MCU_ORANGE_LED_GPIO); + MAP_UtilsDelay(8000000); + GPIO_IF_LedOn(MCU_GREEN_LED_GPIO); + MAP_UtilsDelay(8000000); + GPIO_IF_LedOff(MCU_GREEN_LED_GPIO); + } + +} +//***************************************************************************** +// +//! Board Initialization & Configuration +//! +//! \param None +//! +//! \return None +// +//***************************************************************************** +static void +BoardInit(void) +{ +/* In case of TI-RTOS vector table is initialize by OS itself */ +#ifndef USE_TIRTOS + // + // Set vector table base + // +#if defined(ccs) + MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]); +#endif +#if defined(ewarm) + MAP_IntVTableBaseSet((unsigned long)&__vector_table); +#endif +#endif + + // + // Enable Processor + // + MAP_IntMasterEnable(); + MAP_IntEnable(FAULT_SYSTICK); + + PRCMCC3200MCUInit(); +} +//**************************************************************************** +// +//! Main function +//! +//! \param none +//! +//! This function +//! 1. Invokes the LEDBlinkyTask +//! +//! \return None. +// +//**************************************************************************** +int +main() +{ + // + // Initialize Board configurations + // + BoardInit(); + + // + // Power on the corresponding GPIO port B for 9,10,11. + // Set up the GPIO lines to mode 0 (GPIO) + // + PinMuxConfig(); + GPIO_IF_LedConfigure(LED1|LED2|LED3); + + GPIO_IF_LedOff(MCU_ALL_LED_IND); + + // + // Start the LEDBlinkyRoutine + // + LEDBlinkyRoutine(); + return 0; +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/TI-RTOS/CC3200/nanoCLR/pinmux.c b/targets/TI-RTOS/CC3200/nanoCLR/pinmux.c new file mode 100644 index 0000000000..0372791e85 --- /dev/null +++ b/targets/TI-RTOS/CC3200/nanoCLR/pinmux.c @@ -0,0 +1,80 @@ +//***************************************************************************** +// pinmux.c +// +// configure the device pins for different peripheral signals +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +// This file was automatically generated on 7/21/2014 at 3:06:20 PM +// by TI PinMux version 3.0.334 +// +//***************************************************************************** + +#include "pinmux.h" +#include "hw_types.h" +#include "hw_memmap.h" +#include "hw_gpio.h" +#include "pin.h" +#include "rom.h" +#include "rom_map.h" +#include "gpio.h" +#include "prcm.h" + +//***************************************************************************** +void +PinMuxConfig(void) +{ + // + // Enable Peripheral Clocks + // + MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK); + + // + // Configure PIN_64 for GPIOOutput + // + MAP_PinTypeGPIO(PIN_64, PIN_MODE_0, false); + MAP_GPIODirModeSet(GPIOA1_BASE, 0x2, GPIO_DIR_MODE_OUT); + + // + // Configure PIN_01 for GPIOOutput + // + MAP_PinTypeGPIO(PIN_01, PIN_MODE_0, false); + MAP_GPIODirModeSet(GPIOA1_BASE, 0x4, GPIO_DIR_MODE_OUT); + + // + // Configure PIN_02 for GPIOOutput + // + MAP_PinTypeGPIO(PIN_02, PIN_MODE_0, false); + MAP_GPIODirModeSet(GPIOA1_BASE, 0x8, GPIO_DIR_MODE_OUT); +} diff --git a/targets/TI-RTOS/CC3200/nanoCLR/pinmux.h b/targets/TI-RTOS/CC3200/nanoCLR/pinmux.h new file mode 100644 index 0000000000..8d560a61ae --- /dev/null +++ b/targets/TI-RTOS/CC3200/nanoCLR/pinmux.h @@ -0,0 +1,49 @@ +//***************************************************************************** +// pinmux.h +// +// function prototype for pinmuxconfig +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +// This file was automatically generated on 7/21/2014 at 3:06:20 PM +// by TI PinMux version 3.0.334 +// +//***************************************************************************** + +#ifndef __PINMUX_H__ +#define __PINMUX_H__ + +extern void PinMuxConfig(void); + +#endif // __PINMUX_H__ diff --git a/targets/TI-RTOS/CC3200/nanoCLR/target_board.h.in b/targets/TI-RTOS/CC3200/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..48da76acbc --- /dev/null +++ b/targets/TI-RTOS/CC3200/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/targets/TI-RTOS/CC3200/target_common.c b/targets/TI-RTOS/CC3200/target_common.c new file mode 100644 index 0000000000..bf152a89ed --- /dev/null +++ b/targets/TI-RTOS/CC3200/target_common.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + //--// + + { // unsigned int DebuggerPorts[MAX_DEBUGGERS]; + 0//ConvertCOM_DebugHandle(0), + }, + + { + 0//ConvertCOM_DebugHandle(0), + }, + + 0,//ConvertCOM_DebugHandle(0), + 115200, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; diff --git a/targets/TI-RTOS/CC3200/target_common.h.in b/targets/TI-RTOS/CC3200/target_common.h.in new file mode 100644 index 0000000000..4309fa60bd --- /dev/null +++ b/targets/TI-RTOS/CC3200/target_common.h.in @@ -0,0 +1,33 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00020000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + + +#endif /* _TARGET_COMMON_H_ */ diff --git a/targets/TI-RTOS/common/include/target_types.h b/targets/TI-RTOS/common/include/target_types.h new file mode 100644 index 0000000000..1a305a1cc4 --- /dev/null +++ b/targets/TI-RTOS/common/include/target_types.h @@ -0,0 +1,101 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _TIRTOS_TYPES_H_ +#define _TIRTOS_TYPES_H_ + +#include + +/* + * ======== [U]Int ======== + */ +typedef int_least8_t xdc_Int8; +typedef uint_least8_t xdc_UInt8; +typedef int_least16_t xdc_Int16; +typedef uint_least16_t xdc_UInt16; +typedef int_least32_t xdc_Int32; +typedef uint_least32_t xdc_UInt32; + +#ifdef xdc__INT64__ + typedef int_least64_t xdc_Int64; + typedef uint_least64_t xdc_UInt64; +#endif + +#ifdef xdc__INT40__ + typedef int_least40_t xdc_Int40; + typedef uint_least40_t xdc_UInt40; + + /* the following unqualified names are here because 40-bit types are not + * supported by xdc/std.h + */ + #ifndef xdc__nolocalnames + typedef xdc_Int40 Int40; + typedef xdc_UInt40 UInt40; + #endif +#endif + +/* + * ======== Bits ======== + */ +#ifdef xdc__BITS8__ + typedef uint8_t xdc_Bits8; +#endif +#ifdef xdc__BITS16__ + typedef uint16_t xdc_Bits16; +#endif +#ifdef xdc__BITS32__ + typedef uint32_t xdc_Bits32; +#endif +#ifdef xdc__BITS64__ + typedef uint64_t xdc_Bits64; +#endif + +/* + * ======== [UI]Arg ======== + */ +typedef intptr_t xdc_IArg; +typedef uintptr_t xdc_UArg; + +/* + * ======== restrict ======== + */ +#define xdc__RESTRICT__ + + +/* + * ======== ti_targets_mkPragma ======== + */ +#define ti_targets_mkPragma(x) _Pragma(#x) + +/* + * ======== xdc__META ======== + */ +#define xdc__META(n,s) \ + ti_targets_mkPragma(DATA_SECTION(n, "xdc.meta")) \ + const char (n)[] = {s} + +/* + * ======== __ti__ ======== + * These symbols are used by RTSC tools to indicate presence/absence of + * assorted #pragma options in TI compiler. + */ +#define __ti__ +#define __ti__align +#define __ti__sect + +#if (xdc_target__sizeof_IArg > xdc_target__sizeof_Ptr) \ + || (xdc_target__sizeof_IArg > xdc_target__sizeof_Fxn) + +#define xdc__ARGTOPTR +#define xdc__ARGTOFXN +static inline xdc_Ptr xdc_iargToPtr(xdc_IArg a) { return ((xdc_Ptr)(int)a); } +static inline xdc_Ptr xdc_uargToPtr(xdc_UArg a) { return ((xdc_Ptr)(int)a); } +static inline xdc_Fxn xdc_iargToFxn(xdc_IArg a) { return ((xdc_Fxn)(int)a); } +static inline xdc_Fxn xdc_uargToFxn(xdc_UArg a) { return ((xdc_Fxn)(int)a); } + +#endif + +#endif // _TIRTOS_TYPES_H_ From 9594a67da2725d0bf63a0b49359d94b554195354 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 30 Jan 2018 19:44:53 +0000 Subject: [PATCH 02/90] Correct launch.json template for CC3200 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .vscode/launch.TEMPLATE.json | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/.vscode/launch.TEMPLATE.json b/.vscode/launch.TEMPLATE.json index 633c3b0cdf..a01ed96d0f 100644 --- a/.vscode/launch.TEMPLATE.json +++ b/.vscode/launch.TEMPLATE.json @@ -65,12 +65,39 @@ "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", "filterStderr": true, "externalConsole": true, - "cwd": "${cwd}", + "cwd": "${cwd}" // Enable the following to debug GDB //"logging": { // "engineLogging": true, // "traceResponse": true //}, + }, + + { + "MIMode": "gdb", + "name": "CC3200 Launchpad nanoCLR TEMPLATE", + "type": "cppdbg", + "request": "launch", + + "setupCommands": [ + {"text": "target remote | e:/openocd-0.10.0/bin/openocd.exe -c \"gdb_port pipe; log_output openocd.log\" -f "}, + {"text": "file /nanoCLR.elf>"}, + {"text": "load"}, + {"text": "set $sp = g_pfnVectors[0]"}, + {"text": "set $pc = g_pfnVectors[1]"}, + {"text": "break main"}, + {"text": "continue", "ignoreFailures": true } + ], + + "miDebuggerPath": "", + "targetArchitecture": "ARM", + "program": "${workspaceRoot}/build/nanoCLR.elf", + + "launchCompleteCommand": "None", + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}" } ] } From 3153c87902c8057e6eb52c726c3ea7479ae0d59f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 9 Feb 2018 10:19:40 +0000 Subject: [PATCH 03/90] Work on removing TI-RTOS and add support for CC3200 with ChibiOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- ...ake => CHIBIOS_TICC3200_GCC_options.cmake} | 4 +- CMake/Modules/CHIBIOS_TICC3200_sources.cmake | 298 ++ CMake/Modules/FindCC3200_SDK.cmake | 171 - CMake/Modules/FindCHIBIOS.cmake | 23 +- CMake/toolchain.TIRTOS.GCC.cmake | 168 - CMakeLists.txt | 17 - .../TI_CC3200_LAUNCHPAD}/CMakeLists.txt | 110 +- .../ChibiOS/TI_CC3200_LAUNCHPAD/board.c | 23 + .../ChibiOS/TI_CC3200_LAUNCHPAD/board.h | 32 + .../TI_CC3200_LAUNCHPAD/common/CMakeLists.txt | 11 + .../common/Device_BlockStorage.c | 95 + .../TI_CC3200_LAUNCHPAD/heap_useNewlib.c | 156 + .../nanoBooter/CMakeLists.txt | 4 + .../nanoCLR/CMakeLists.txt | 5 +- .../TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld | 164 + .../TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h | 516 +++ .../TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h | 384 ++ .../TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h | 20 + .../TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c | 112 + .../TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c | 964 +++++ .../TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h | 76 + .../TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h | 9 + .../TI_CC3200_LAUNCHPAD}/nanoCLR/pinmux.c | 11 + .../TI_CC3200_LAUNCHPAD}/nanoCLR/pinmux.h | 0 .../nanoCLR/target_board.h.in | 0 .../ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c | 791 ++++ .../TI_CC3200_LAUNCHPAD}/target_common.c | 2 +- .../TI_CC3200_LAUNCHPAD}/target_common.h.in | 0 .../os/common/ext/CCWare/inc/asmdefs.h | 229 ++ .../os/common/ext/CCWare/inc/hw_adc.h | 888 +++++ .../os/common/ext/CCWare/inc/hw_aes.h | 802 ++++ .../os/common/ext/CCWare/inc/hw_apps_config.h | 747 ++++ .../os/common/ext/CCWare/inc/hw_apps_rcm.h | 1506 +++++++ .../os/common/ext/CCWare/inc/hw_camera.h | 519 +++ .../os/common/ext/CCWare/inc/hw_common_reg.h | 1117 ++++++ .../os/common/ext/CCWare/inc/hw_des.h | 339 ++ .../os/common/ext/CCWare/inc/hw_dthe.h | 392 ++ .../os/common/ext/CCWare/inc/hw_flash_ctrl.h | 1862 +++++++++ .../os/common/ext/CCWare/inc/hw_gpio.h | 1349 +++++++ .../os/common/ext/CCWare/inc/hw_gprcm.h | 3322 ++++++++++++++++ .../os/common/ext/CCWare/inc/hw_hib1p2.h | 1750 +++++++++ .../os/common/ext/CCWare/inc/hw_hib3p3.h | 1138 ++++++ .../os/common/ext/CCWare/inc/hw_i2c.h | 503 +++ .../os/common/ext/CCWare/inc/hw_ints.h | 117 + .../os/common/ext/CCWare/inc/hw_mcasp.h | 1706 ++++++++ .../os/common/ext/CCWare/inc/hw_mcspi.h | 1745 +++++++++ .../os/common/ext/CCWare/inc/hw_memmap.h | 84 + .../os/common/ext/CCWare/inc/hw_mmchs.h | 1919 +++++++++ .../os/common/ext/CCWare/inc/hw_nvic.h | 1710 ++++++++ .../os/common/ext/CCWare/inc/hw_ocp_shared.h | 3445 +++++++++++++++++ .../os/common/ext/CCWare/inc/hw_shamd5.h | 1242 ++++++ .../common/ext/CCWare/inc/hw_stack_die_ctrl.h | 764 ++++ .../os/common/ext/CCWare/inc/hw_timer.h | 778 ++++ .../os/common/ext/CCWare/inc/hw_types.h | 76 + .../os/common/ext/CCWare/inc/hw_uart.h | 417 ++ .../os/common/ext/CCWare/inc/hw_udma.h | 336 ++ .../os/common/ext/CCWare/inc/hw_wdt.h | 131 + .../os/common/ext/CMSIS/TI/TICC3200/cc3200.h | 118 + .../ARMCMx/devices/TICC3200/cmparams.h | 119 + .../os/hal/ports/TI/LLD/GPIO/hal_pal_lld.c | 432 +++ .../os/hal/ports/TI/LLD/GPIO/hal_pal_lld.h | 806 ++++ .../os/hal/ports/TI/LLD/GPTM/hal_st_lld.c | 244 ++ .../os/hal/ports/TI/LLD/GPTM/hal_st_lld.h | 199 + .../os/hal/ports/TI/LLD/RTC/hal_rtc_lld.h | 188 + .../os/hal/ports/TI/LLD/UART/hal_serial_lld.h | 437 +++ .../os/hal/ports/TI/TICC3200/hal_lld.c | 131 + .../os/hal/ports/TI/TICC3200/hal_lld.h | 234 ++ .../os/hal/ports/TI/TICC3200/ticc3200_isr.h | 40 + .../hal/ports/TI/TICC3200/ticc3200_registry.h | 31 + targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld | 94 - targets/TI-RTOS/CC3200/nanoCLR/main.c | 222 -- 71 files changed, 37677 insertions(+), 717 deletions(-) rename CMake/Modules/{TIRTOS_CC3200_GCC_options.cmake => CHIBIOS_TICC3200_GCC_options.cmake} (69%) create mode 100644 CMake/Modules/CHIBIOS_TICC3200_sources.cmake delete mode 100644 CMake/Modules/FindCC3200_SDK.cmake delete mode 100644 CMake/toolchain.TIRTOS.GCC.cmake rename targets/{TI-RTOS/CC3200 => CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD}/CMakeLists.txt (51%) create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.c create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.h create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/CMakeLists.txt create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/Device_BlockStorage.c create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/heap_useNewlib.c create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoBooter/CMakeLists.txt rename targets/{TI-RTOS/CC3200 => CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD}/nanoCLR/CMakeLists.txt (70%) create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h rename targets/{TI-RTOS/CC3200 => CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD}/nanoCLR/pinmux.c (91%) rename targets/{TI-RTOS/CC3200 => CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD}/nanoCLR/pinmux.h (100%) rename targets/{TI-RTOS/CC3200 => CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD}/nanoCLR/target_board.h.in (100%) create mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c rename targets/{TI-RTOS/CC3200 => CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD}/target_common.c (97%) rename targets/{TI-RTOS/CC3200 => CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD}/target_common.h.in (100%) create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/asmdefs.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_adc.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_aes.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_config.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_rcm.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_camera.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_common_reg.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_des.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_dthe.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_flash_ctrl.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gpio.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gprcm.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib1p2.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib3p3.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_i2c.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ints.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcasp.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcspi.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_memmap.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mmchs.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_nvic.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ocp_shared.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_shamd5.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_stack_die_ctrl.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_timer.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_types.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_uart.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_udma.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_wdt.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200/cc3200.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200/cmparams.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.c create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.c create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC/hal_rtc_lld.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART/hal_serial_lld.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.c create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_isr.h create mode 100644 targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_registry.h delete mode 100644 targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld delete mode 100644 targets/TI-RTOS/CC3200/nanoCLR/main.c diff --git a/CMake/Modules/TIRTOS_CC3200_GCC_options.cmake b/CMake/Modules/CHIBIOS_TICC3200_GCC_options.cmake similarity index 69% rename from CMake/Modules/TIRTOS_CC3200_GCC_options.cmake rename to CMake/Modules/CHIBIOS_TICC3200_GCC_options.cmake index 996d62f1ea..6f9b84569c 100644 --- a/CMake/Modules/TIRTOS_CC3200_GCC_options.cmake +++ b/CMake/Modules/CHIBIOS_TICC3200_GCC_options.cmake @@ -19,13 +19,13 @@ set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTER # need to specify linker flags here # -mfpu=fpv5-sp-d16 -set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -march=armv7e-m -mfpu=fpv4-sp-d16 -mabi=aapcs -nostartfiles -Wl,-T,${TIRTOS_BIOS_INSTALLATION_DIR}/ti/platforms/simplelink/include_gnu/cc3200.lds -lgcc -lc -lm -lrdimon " CACHE INTERNAL "executable linker flags") +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=soft -mabi=aapcs -nostartfiles -lgcc -lc -lm -lrdimon " CACHE INTERNAL "executable linker flags") function(NF_SET_COMPILER_OPTIONS TARGET) # include any extra options comming from any extra args? - target_compile_options(${TARGET} PUBLIC ${ARGN} -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -march=armv7e-m -mfpu=fpv4-sp-d16 -gstrict-dwarf -mabi=aapcs -nostdlib -Wall -w -static -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -mstructure-size-boundary=8 -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) + target_compile_options(${TARGET} PUBLIC ${ARGN} -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=soft -mabi=aapcs -gstrict-dwarf -nostdlib -Wall -w -static -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -mstructure-size-boundary=8 -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) endfunction() diff --git a/CMake/Modules/CHIBIOS_TICC3200_sources.cmake b/CMake/Modules/CHIBIOS_TICC3200_sources.cmake new file mode 100644 index 0000000000..e4b9c22bde --- /dev/null +++ b/CMake/Modules/CHIBIOS_TICC3200_sources.cmake @@ -0,0 +1,298 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# List of the ChibiOS generic CC3200 startup and CMSIS files. + +# set include directories for CC3200 SDK +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/example/common) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/inc) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/driverlib) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/driver) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/driver/hal) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/framework/pm) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/framework/timer) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/soc) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/oslib) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink/include) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/include) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/flc) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/ota) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/provisioninglib) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source/include) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source/portable/GCC/ARM_CM4) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/TI-RTOS/common/include) + +# XDC tools includes +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_XDCTOOLS_INSTALLATION_DIR}/packages) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_XDCTOOLS_INSTALLATION_DIR}/packages/xdc) +# # list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/xdc) +# # list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/ti/targets) + +# ChibiOS includes +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/license) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/include) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/boards/${CHIBIOS_BOARD}) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/osal/rt) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/oslib/include) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/abstractions/cmsis_os) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/rt/include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/abstractions/cmsis_os) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200) + + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/CMSIS/include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC) + + +# source files for CC3200 SDK +set(CHIBIOS_PORT_SRCS + + # startup code + crt1.c + vectors.c + crt0_v7m.S + + nvic.c + hal_lld.c + + # + hal_st_lld.c + hal_pal_lld.c + + # examples common + # button_if.c + # gpio_if.c + # i2c_if.c + # i2s_if.c + # network_common.c + # network_if.c + #######startup_gcc.c + # timer_if.c + # uart_if.c + # udma_if.c + # utils_if.c + # wdt_if.c + + # drivers + # adc.c + # aes.c + # camera.c + # cpu.c + # crc.c + # des.c + # flash.c + # gpio.c + # i2c.c + # i2s.c + # interrupt.c + # pin.c + # prcm.c + # sdhost.c + # shamd5.c + # spi.c + # systick.c + # timer.c + # uart.c + # udma.c + # utils.c + # wdt.c + + # middleware/driver/hal + # dma_hal.c + # gpio_hal.c + # hw_timer32.c + # hw_timer32.c + # rtc_hal.c + # spi_hal.c + # uart_hal.c + # util64.c + + # middleware/driver + # spi_drv.c + # uart_drv.c + + # middleware/framework/pm + # cc_pm.c + + # middleware/framework/timer + # cc_timer.c + + # middleware/soc + # cc_io_park.c + # cc_pm_ops.c + + # netapps + + # oslib + # osi_tirtos.c + # osi_freertos.c + # port.c + # heap_2.c + + # FreeRTOS + # croutine.c + # event_groups.c + # list.c + # queue.c + # tasks.c + # timers.c + + # simplelink + # cc_pal_pm.c + # cc_pal.c + # device.c + # flowcont.c + # fs.c + # netapp.c + # netcfg.c + # nonos.c + # socket.c + # spawn.c + # wlan.c + + # simplelink_extlib + # flc.c + # CdnClient.c + # LogClient.c + # OtaApp.c + # OtaClient.c + # OtaHttp.c + # cfg_confirm.c + # events_handler.c + # networkListHndl.c + # provisioning_logic.c + + + # # ChibiOS + + # # OSAL RT + # osal.c + + # # RT + # chsys.c + # chdebug.c + # chvt.c + # chschd.c + # chthreads.c + # chtm.c + # chstats.c + # chdynamic.c + # chregistry.c + # chsem.c + # chmtx.c + # chcond.c + # chevents.c + # chmsg.c + + # chheap.c + # chmboxes.c + # chmemcore.c + # chmempools.c + + # # required to use malloc and other newlib stuff + # syscalls.c + + # # CMSIS + # cmsis_os.c + + # # board file(s) + # # board.c + + # # RT + # chcore.c + # chcore_v7m.c + # chcoreasm_v7m.S + + # startup code + # crt1.c + # vectors.c + # crt0_v7m.S + + # nvic.c + # hal_lld.c + # hal_ext_lld_isr.c + +) + +foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) + set(CC3200_SCR_FILE SRC_FILE -NOTFOUND) + find_file(CC3200_SCR_FILE ${SRC_FILE} + PATHS + + # examples common + # ${TI_CC3200_SDK_PATH}/example/common + + # drivers + # ${TI_CC3200_SDK_PATH}/driverlib + + # middleware + # ${TI_CC3200_SDK_PATH}/middleware/driver + # ${TI_CC3200_SDK_PATH}/middleware/driver/hal + # ${TI_CC3200_SDK_PATH}/middleware/framework/pm + # ${TI_CC3200_SDK_PATH}/middleware/framework/timer + # ${TI_CC3200_SDK_PATH}/middleware/soc + + # netapps + + # oslib + # ${TI_CC3200_SDK_PATH}/oslib + # ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source + # ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source/portable/GCC/ARM_CM4 + # ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source/portable/MemMang + + # simplelink + # ${TI_CC3200_SDK_PATH}/simplelink + # ${TI_CC3200_SDK_PATH}/simplelink/source + + # simplelink_extlib + # ${TI_CC3200_SDK_PATH}/simplelink_extlib/flc + # ${TI_CC3200_SDK_PATH}/simplelink_extlib/ota + # ${TI_CC3200_SDK_PATH}/simplelink_extlib/provisioninglib + + # ChibiOS + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/src + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/osal/rt + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/rt/src + # # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/oslib/src + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/abstractions/cmsis_os + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/various + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx + + ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200 + ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM + ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO + ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${CC3200_SCR_FILE}") # debug helper + list(APPEND CHIBIOS_SOURCES ${CC3200_SCR_FILE}) +endforeach() diff --git a/CMake/Modules/FindCC3200_SDK.cmake b/CMake/Modules/FindCC3200_SDK.cmake deleted file mode 100644 index ebd4b2e088..0000000000 --- a/CMake/Modules/FindCC3200_SDK.cmake +++ /dev/null @@ -1,171 +0,0 @@ -# -# Copyright (c) 2017 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# - -# and here the GCC options tuned for the target series -include(TIRTOS_CC3200_GCC_options) - -# set include directories for CC3200 SDK -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/example/common) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/inc) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/driverlib) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/driver) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/driver/hal) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/framework/pm) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/framework/timer) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/soc) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/oslib) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink/include) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/include) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/flc) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/ota) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/provisioninglib) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/TI-RTOS/common/include) - -# XDC tools includes -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_XDCTOOLS_INSTALLATION_DIR}/packages) -list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_XDCTOOLS_INSTALLATION_DIR}/packages/xdc) -# list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/xdc) -# list(APPEND CC3200_SDK_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/ti/targets) - -# source files for CC3200 SDK -set(CC3200_SDK_SRCS - - # examples common - button_if.c - gpio_if.c - i2c_if.c - i2s_if.c - network_common.c - network_if.c - startup_gcc.c - timer_if.c - uart_if.c - udma_if.c - utils_if.c - wdt_if.c - - # drivers - # adc.c - # aes.c - # camera.c - # cpu.c - # crc.c - # des.c - # flash.c - # gpio.c - # i2c.c - # i2s.c - # interrupt.c - # pin.c - # prcm.c - # sdhost.c - # shamd5.c - # spi.c - # systick.c - # timer.c - # uart.c - # udma.c - # utils.c - # wdt.c - - # middleware/driver/hal - # dma_hal.c - # gpio_hal.c - # hw_timer32.c - # hw_timer32.c - # rtc_hal.c - # spi_hal.c - # uart_hal.c - # util64.c - - # middleware/driver - # spi_drv.c - # uart_drv.c - - # middleware/framework/pm - # cc_pm.c - - # middleware/framework/timer - # cc_timer.c - - # middleware/soc - # cc_io_park.c - # cc_pm_ops.c - - # netapps - - # oslib - # osi_tirtos.c - - # simplelink - # cc_pal_pm.c - # cc_pal.c - # device.c - # flowcont.c - # fs.c - # netapp.c - # netcfg.c - # nonos.c - # socket.c - # spawn.c - # wlan.c - - # simplelink_extlib - # flc.c - # CdnClient.c - # LogClient.c - # OtaApp.c - # OtaClient.c - # OtaHttp.c - # cfg_confirm.c - # events_handler.c - # networkListHndl.c - # provisioning_logic.c - -) - -foreach(SRC_FILE ${CC3200_SDK_SRCS}) - set(CC3200_SDK_FILE SRC_FILE -NOTFOUND) - find_file(CC3200_SDK_FILE ${SRC_FILE} - PATHS - - # examples common - ${TI_CC3200_SDK_PATH}/example/common - - # drivers - ${TI_CC3200_SDK_PATH}/driverlib - - # middleware - ${TI_CC3200_SDK_PATH}/middleware/driver - ${TI_CC3200_SDK_PATH}/middleware/driver/hal - ${TI_CC3200_SDK_PATH}/middleware/framework/pm - ${TI_CC3200_SDK_PATH}/middleware/framework/timer - ${TI_CC3200_SDK_PATH}/middleware/soc - - # netapps - - # oslib - ${TI_CC3200_SDK_PATH}/oslib - - # simplelink - ${TI_CC3200_SDK_PATH}/simplelink - ${TI_CC3200_SDK_PATH}/simplelink/source - - # simplelink_extlib - ${TI_CC3200_SDK_PATH}/simplelink_extlib/flc - ${TI_CC3200_SDK_PATH}/simplelink_extlib/ota - ${TI_CC3200_SDK_PATH}/simplelink_extlib/provisioninglib - - CMAKE_FIND_ROOT_PATH_BOTH - ) - # message("${SRC_FILE} >> ${CC3200_SDK_FILE}") # debug helper - list(APPEND CC3200_SDK_SOURCES ${CC3200_SDK_FILE}) -endforeach() - -include(FindPackageHandleStandardArgs) - -FIND_PACKAGE_HANDLE_STANDARD_ARGS(CC3200_SDK DEFAULT_MSG CC3200_SDK_INCLUDE_DIRS CC3200_SDK_SOURCES) diff --git a/CMake/Modules/FindCHIBIOS.cmake b/CMake/Modules/FindCHIBIOS.cmake index a68dfb9a72..dc8664019e 100644 --- a/CMake/Modules/FindCHIBIOS.cmake +++ b/CMake/Modules/FindCHIBIOS.cmake @@ -9,10 +9,23 @@ # check if the series name is supported -set(CHIBIOS_SUPPORTED_SERIES "STM32L0xx" "STM32F0xx" "STM32F4xx" "STM32F7xx" "STM32H7xx" CACHE INTERNAL "supported series names for ChibiOS") -list(FIND CHIBIOS_SUPPORTED_SERIES ${TARGET_SERIES} TARGET_SERIES_NAME_INDEX) +set(CHIBIOS_STM_SUPPORTED_SERIES "STM32F0xx" "STM32F4xx" "STM32F7xx" "STM32H7xx" "TICC3200" CACHE INTERNAL "supported STM series names for ChibiOS") +set(CHIBIOS_TI_SUPPORTED_SERIES "TICC3200" CACHE INTERNAL "supported TI series names for ChibiOS") + +list(FIND CHIBIOS_STM_SUPPORTED_SERIES ${TARGET_SERIES} TARGET_SERIES_NAME_INDEX) if(TARGET_SERIES_NAME_INDEX EQUAL -1) - message(FATAL_ERROR "\n\nSorry but ${TARGET_SERIES} is not supported at this time...\nYou can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") + # series is NOT supported by STM + # try TI + list(FIND CHIBIOS_TI_SUPPORTED_SERIES ${TARGET_SERIES} TARGET_SERIES_NAME_INDEX) + if(TARGET_SERIES_NAME_INDEX EQUAL -1) + message(FATAL_ERROR "\n\nSorry but ${TARGET_SERIES} is not supported at this time...\nYou can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") + else() + # series is supported by TI + set(TARGET_VENDOR "TI" CACHE INTERNAL "target vendor is TI") + endif() +else() + # series is supported by STM + set(TARGET_VENDOR "STM" CACHE INTERNAL "target vendor is STM") endif() # including here the CMake files for the source files specific to the target series @@ -50,6 +63,10 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/ # append include directory for boards in the nanoFramework ChibiOS 'overlay' provideded by the community list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets-community/CMSIS-OS/ChibiOS/nf-overlay/os/hal/boards/${CHIBIOS_BOARD}) +# +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/${TARGET_SERIES}) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/${TARGET_SERIES}) + # source files and GCC options according to target vendor and series diff --git a/CMake/toolchain.TIRTOS.GCC.cmake b/CMake/toolchain.TIRTOS.GCC.cmake deleted file mode 100644 index da2017ee47..0000000000 --- a/CMake/toolchain.TIRTOS.GCC.cmake +++ /dev/null @@ -1,168 +0,0 @@ -# -# Copyright (c) 2017 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# - -INCLUDE(CMakeForceCompiler) -# if( DEFINED CMAKE_CROSSCOMPILING ) -# # subsequent toolchain loading is not really needed -# return() -# endif() - - -################################################### -# set C and C++ flags for compiler detection tests -################################################### -# IMPORTANT: these flags need to be removed after -# the compiler detection otherwise they'll get -# added to all compiler build calls and -# will colide with the use of nano.specs -################################################### -set(CMAKE_C_FLAGS_INIT "-specs=nosys.specs") -set(CMAKE_CXX_FLAGS_INIT "-specs=nosys.specs") -################################################### - - -# set toolchain directories -set(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_PREFIX}/bin) -set(TOOLCHAIN_INC_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/include) -set(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/lib) - -# the name of the operating system for which CMake is to build -set(CMAKE_SYSTEM_NAME Generic) - -# name of the CPU CMake is building for -set(CMAKE_SYSTEM_PROCESSOR arm) - -# macro to setup compilers -macro(SET_COMPILER_VAR var name) - find_program(CMAKE_${var} arm-none-eabi-${name} HINTS ${TOOLCHAIN_BIN_DIR} DOC "${name} tool") -endmacro() - -# setup C compiler -if(NOT CMAKE_C_COMPILER) - SET_COMPILER_VAR(C_COMPILER gcc) -endif() - -# setup C++ compiler -if(NOT CMAKE_CXX_COMPILER) - SET_COMPILER_VAR(CXX_COMPILER g++) -endif() - -# setup Assembler compiler -SET_COMPILER_VAR(ASM-ATT_COMPILER as) - -# other toolchain configurations -set(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objcopy CACHE INTERNAL "objcopy tool") -set(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objdump CACHE INTERNAL "objdump tool") -set(CMAKE_SIZE ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-size CACHE INTERNAL "size tool") -set(CMAKE_DEBUGER ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-gdb CACHE INTERNAL "debuger") - -# root paths to search on the filesystem for cross-compiling -set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_PREFIX}/arm-none-eabi ${EXTRA_FIND_PATH}) -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -# set required C and C++ standard for ALL targets -set(CMAKE_C_STANDARD 11 CACHE INTERNAL "C standard for all targets") -set(CMAKE_CXX_STANDARD 11 CACHE INTERNAL "C++ standard for all targets") - -# set all C and C++ extensions to be OFF on ALL targets -# this forces the use of -std=c11 and -std=c++11 instead of -std=gnu11 and -std=gnu++11 -set(CMAKE_C_EXTENSIONS OFF CACHE INTERNAL "C compiler extensions OFF") -set(CMAKE_CXX_EXTENSIONS OFF CACHE INTERNAL "C++ compiler extensions OFF") - - -function(NF_ADD_HEX_BIN_DUMP_TARGETS TARGET) - if(EXECUTABLE_OUTPUT_PATH) - set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") - else() - set(FILENAME "${TARGET}") - endif() - - # add targets for HEX, BIN and S19 formats with no output so they will always be built - add_custom_target(${TARGET}.hex DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Oihex ${FILENAME} ${FILENAME}.hex) - add_custom_target(${TARGET}.s19 DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Osrec ${FILENAME} ${FILENAME}.s19) - add_custom_target(${TARGET}.bin DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Obinary ${FILENAME} ${FILENAME}.bin) - add_custom_target(${TARGET}.dump DEPENDS ${TARGET} COMMAND ${CMAKE_OBJDUMP} -d -EL -S ${FILENAME} ${FILENAME}.dump) -endfunction() - - -function(NF_PRINT_SIZE_OF_TARGETS TARGET) - if(EXECUTABLE_OUTPUT_PATH) - set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") - else() - set(FILENAME "${TARGET}") - endif() - add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} ${FILENAME}) -endfunction() - - -function(NF_SET_OPTIMIZATION_OPTIONS TARGET) - - target_compile_options(${TARGET} PRIVATE - $<$:-Og -femit-class-debug-always -g3 -ggdb> - $<$:-O3 -flto -fno-strict-aliasing> - $<$:-Os -flto -fno-strict-aliasing> - $<$:-Os -femit-class-debug-always -g3 -ggdb> - ) - -endfunction() - - -function(NF_SET_LINK_MAP TARGET) - - # need to remove the .elf suffix from target name - string(FIND ${TARGET} "." TARGET_EXTENSION_DOT_INDEX) - string(SUBSTRING ${TARGET} 0 ${TARGET_EXTENSION_DOT_INDEX} TARGET_SHORT) - - # add linker flags to generate map file - set_property(TARGET ${TARGET_SHORT}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=${PROJECT_SOURCE_DIR}/build/${TARGET_SHORT}.map,--library-path=${PROJECT_SOURCE_DIR}/targets/TI-RTOS/CC3200/nanoCLR") - -endfunction() - - -function(NF_SET_COMPILER_DEFINITIONS TARGET) - - # definition for platform (always ARM here) - target_compile_definitions(${TARGET} PUBLIC "-DPLATFORM_ARM ") - - # definition for platform - target_compile_definitions(${TARGET} PUBLIC "-Dgcc -DPART_CC3200 -DUSE_TIRTOS -DCCWARE -DSL_FULL -DSL_PLATFORM_MULTI_THREADED -DTARGET_IS_CC3200 -Dxdc_target_types__=target_types.h") - - # set compiler definitions related with the build type - if(CMAKE_BUILD_TYPE STREQUAL "Debug" OR CMAKE_BUILD_TYPE STREQUAL "RelWithDebInfo") - # build types that include debug have the define 'NANOCLR_ENABLE_SOURCELEVELDEBUGGING' - target_compile_definitions(${TARGET} PUBLIC "-DNANOCLR_ENABLE_SOURCELEVELDEBUGGING ") - endif() - - # set compiler definition for RTM build option - if(NF_BUILD_RTM) - target_compile_definitions(${TARGET} PUBLIC BUILD_RTM) - endif() - - # set compiler definition for platform emulated floating point according to FPU - # no FPU requires FP emulation from the platform - target_compile_definitions(${TARGET} PUBLIC $<$>:-DPLATFORM_EMULATED_FLOATINGPOINT>) - - # set compiler definition for CORTEX according to FPU - target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=$<$:TRUE>$<$>:FALSE>) - - # set compiler definition for using Application Domains feature - if(NF_FEATURE_USE_APPDOMAINS) - target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_USE_APPDOMAINS) - endif() - - # set definition for Wire Protocol trace mask - target_compile_definitions(${TARGET} PUBLIC -DTRACE_MASK=${WP_TRACE_MASK}) - -endfunction() - - -function(NF_SET_LINKER_FILE TARGET LINKER_FILE_NAME) - - # set linker file name - set_target_properties(${TARGET} PROPERTIES LINK_FLAGS "-T${LINKER_FILE_NAME}") - -endfunction() diff --git a/CMakeLists.txt b/CMakeLists.txt index 6469a4ebfd..d1395aad37 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -153,10 +153,6 @@ elseif(RTOS_FREERTOS_ESP32_CHECK) # # set toolchain file # set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.${CHIP_VENDOR_STM32}.${TOOLCHAIN}.cmake) -elseif(RTOS_TIRTOS_CHECK) - message(STATUS "\nSetting Toolchain file for TI-RTOS \n") - set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.TIRTOS.${TOOLCHAIN}.cmake) - endif() ######################################### @@ -1115,17 +1111,4 @@ elseif(RTOS_FREERTOS_ESP32_CHECK) endif() -####################### -# TI-RTOS -elseif(RTOS_TIRTOS_CHECK) - - if("${TARGET_SERIES}" STREQUAL "TICC3200") - message("Platform TICC3200") - - # Define base path for the class libraries - set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/TI-RTOS/CC3200/nanoCLR") - - add_subdirectory(targets/TI-RTOS/CC3200) - endif() - endif() diff --git a/targets/TI-RTOS/CC3200/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/CMakeLists.txt similarity index 51% rename from targets/TI-RTOS/CC3200/CMakeLists.txt rename to targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/CMakeLists.txt index a2231eb182..f38c6b908e 100644 --- a/targets/TI-RTOS/CC3200/CMakeLists.txt +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/CMakeLists.txt @@ -7,8 +7,6 @@ cmake_minimum_required(VERSION 3.0) ENABLE_LANGUAGE(ASM) # add header files with common OS definitions and board definitions specific for each image -# configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" -# "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" @@ -17,25 +15,24 @@ configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" # set(NANOBOOTER_PROJECT_NAME "nanoBooter") set(NANOCLR_PROJECT_NAME "nanoCLR") -find_package(CC3200_SDK REQUIRED) find_package(BuildUtils REQUIRED) -# find_package(CHIBIOS REQUIRED) -# find_package(ChibiOSnfOverlay REQUIRED) -# find_package(WireProtocol REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) # packages for nanoFramework libraries ####################################### # mandatory -# find_package(NF_CoreCLR REQUIRED) +find_package(NF_CoreCLR REQUIRED) ####################################### # optional -# # nF feature: debugger -# if(NF_FEATURE_DEBUGGER) -# find_package(NF_Debugger REQUIRED) -# find_package(NF_Diagnostics REQUIRED) -# endif() +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() # # nF feature: networking # if(USE_NETWORKING_OPTION) @@ -47,10 +44,18 @@ find_package(BuildUtils REQUIRED) # find_package(CHIBIOS_FATFS REQUIRED) # endif() -####################################### +#################################################### +# sources for target specifc stuff related with APIs +list(APPEND API_RELATED_TARGET_SOURCES "") + +# Windows.Devices.SerialCommunication +if(API_Windows.Devices.SerialCommunication) + list(APPEND API_RELATED_TARGET_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/target_windows_devices_serialcommunication_config.cpp") +endif() +####################################### -# add_subdirectory("common") +add_subdirectory("common") # add_subdirectory("nanoBooter") add_subdirectory("nanoCLR") @@ -85,46 +90,70 @@ add_executable( # executables for project, project sources ${NANOCLR_PROJECT_NAME}.elf - # "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + # "heap_useNewlib.c" + # "osi_chibios.c" ${COMMON_PROJECT_SOURCES} ${NANOCLR_PROJECT_SOURCES} - # ${TARGET_CMSIS_COMMON_SOURCES} - # ${TARGET_CMSIS_NANOCLR_SOURCES} + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} - # ${TARGET_CHIBIOS_COMMON_SOURCES} - # ${TARGET_CHIBIOS_NANOCLR_SOURCES} + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} - ${CC3200_SDK_SOURCES} - # ${ChibiOSnfOverlay_SOURCES} + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} # sources for nanoFramework libraries - # "${NF_CoreCLR_SOURCES}" - # "${NF_Debugger_SOURCES}" - # "${NF_Diagnostics_SOURCES}" + "${NF_CoreCLR_SOURCES}" + "${NF_Debugger_SOURCES}" + "${NF_Diagnostics_SOURCES}" # sources for nanoFramework APIs - # "${TARGET_NANO_APIS_SOURCES}" + "${TARGET_NANO_APIS_SOURCES}" ) +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) # include common directories include_directories( "${CMAKE_CURRENT_BINARY_DIR}" ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/common - # ${PROJECT_SOURCE_DIR}/src/CLR/Core - # ${PROJECT_SOURCE_DIR}/src/CLR/Include - # ${PROJECT_SOURCE_DIR}/src/HAL/Include - # ${PROJECT_SOURCE_DIR}/src/PAL/Include + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include - # ${WireProtocol_INCLUDE_DIRS} - ${CC3200_SDK_INCLUDE_DIRS} - # ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} - # ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} - # ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + "${NF_CoreCLR_INCLUDE_DIRS}" + "${NF_Debugger_INCLUDE_DIRS}" + "${NF_Diagnostics_INCLUDE_DIRS}" + + # includes for nanoFramework APIs + "${TARGET_NANO_APIS_INCLUDES}" + + # includes for ChibiOS LwIP + # "${CHIBIOS_LWIP_INCLUDE_DIRS}" ) # set compiler options @@ -144,10 +173,17 @@ nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoC # nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf FALSE) nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf FALSE) +# add other linker flags +################################################### +# the size of the CLR managed heap is defined here +################################################### +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x1800") + # add libraries -target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/driverlib/gcc/exe/libdriver.a) -target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/simplelink/gcc/exe/libsimplelink.a) -target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/oslib/gcc/exe/libtirtos.a) +# target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/simplelink/gcc/exe/libsimplelink.a) +# target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/driverlib/gcc/exe/libdriver.a) +# target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/oslib/gcc/exe/libtirtos.a) +# target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/oslib/gcc/exe/freertos.a) # generate output files # nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.c new file mode 100644 index 0000000000..f5b2ba5f9f --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.c @@ -0,0 +1,23 @@ + + +#include "hal.h" + + +/** + * @brief Early initialization code. + * @details This initialization is performed just after reset before BSS and + * DATA segments initialization. + */ +void __early_init(void) +{ + ticc3200_clock_init(); +} + +/** + * @brief Late initialization code. + * @note This initialization is performed after BSS and DATA segments + * initialization and before invoking the main() function. + */ +void boardInit(void) +{ +} diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.h new file mode 100644 index 0000000000..31a52231e0 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.h @@ -0,0 +1,32 @@ + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for Texas Instruments CC3200 Launchpad Board + */ + +/* + * Board identifier. + */ +#define BOARD_TI_CC3200_LAUNCHPAD +#define BOARD_NAME "Texas Instruments CC3200 Launchpad" + +/* + * MCU type and revision as defined in the TI header. + */ +#define PART_CC3200 +#define TARGET_IS_CC3200 + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif // BOARD_H \ No newline at end of file diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/CMakeLists.txt new file mode 100644 index 0000000000..ad042a37bc --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +# list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/Device_BlockStorage.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/Device_BlockStorage.c new file mode 100644 index 0000000000..c1b87a35c1 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/Device_BlockStorage.c @@ -0,0 +1,95 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +const BlockRange BlockRange1[] = // 32KB blocks +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 08008000 nanoCLR +}; + +const BlockRange BlockRange2[] = //128KB block +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR +}; + +const BlockRange BlockRange3[] = // 256KB blocks +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + + +const DeviceBlockInfo Device_BlockInfo = +{ + { + false, // BOOL Removable; + true, // BOOL SupportsXIP; + false, // BOOL WriteProtected; + false // BOOL SupportsCopyBack + }, + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + &Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/heap_useNewlib.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/heap_useNewlib.c new file mode 100644 index 0000000000..6ad783a69b --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/heap_useNewlib.c @@ -0,0 +1,156 @@ +/** + * \file heap_useNewlib.c + * \brief Wrappers required to use newlib malloc-family within FreeRTOS. + * + * \par Overview + * Route FreeRTOS memory management functions to newlib's malloc family. + * Thus newlib and FreeRTOS share memory-management routines and memory pool, + * and all newlib's internal memory-management requirements are supported. + * + * \author Dave Nadler + * \date 2-July-2017 + * + * \see http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * \see https://sourceware.org/newlib/libc.html#Reentrancy + * \see https://sourceware.org/newlib/libc.html#malloc + * \see https://sourceware.org/newlib/libc.html#index-_005f_005fenv_005flock + * \see https://sourceware.org/newlib/libc.html#index-_005f_005fmalloc_005flock + * \see https://sourceforge.net/p/freertos/feature-requests/72/ + * \see http://www.billgatliff.com/newlib.html + * \see http://wiki.osdev.org/Porting_Newlib + * \see http://www.embecosm.com/appnotes/ean9/ean9-howto-newlib-1.0.html + * + * + * \copyright + * (c) Dave Nadler 2017, All Rights Reserved. + * Web: http://www.nadler.com + * email: drn@nadler.com + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * - Use or redistributions of source code must retain the above copyright notice, + * this list of conditions, ALL ORIGINAL COMMENTS, and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include // maps to newlib... +#include // mallinfo... +#include // ENOMEM + +#include "newlib.h" +#if (__NEWLIB__ != 2) || (__NEWLIB_MINOR__ != 5) + #warning "This wrapper was verified for newlib version 2.5.0; please ensure newlib's external requirements for malloc-family are unchanged!" +#endif + +#include "FreeRTOS.h" // defines public interface we're implementing here +#if !defined(configUSE_NEWLIB_REENTRANT) || (configUSE_NEWLIB_REENTRANT!=1) + #warning "#define configUSE_NEWLIB_REENTRANT 1 // Required for thread-safety of newlib sprintf, strtok, etc..." + // If you're *really* sure you don't need FreeRTOS's newlib reentrancy support, remove this warning... +#endif +#include "task.h" + +// ================================================================================================ +// External routines required by newlib's malloc (sbrk/_sbrk, __malloc_lock/unlock) +// ================================================================================================ + +#ifndef NDEBUG + static int totalBytesProvidedBySBRK = 0; +#endif +extern char __HeapBase, __HeapLimit, HEAP_SIZE; // make sure to define these symbols in linker command file +static int heapBytesRemaining = (int)&HEAP_SIZE; // that's (&__HeapLimit)-(&__HeapBase) + +//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file). +char * sbrk(int incr) { + static char *currentHeapEnd = &__HeapBase; + vTaskSuspendAll(); // Note: safe to use before FreeRTOS scheduler started + char *previousHeapEnd = currentHeapEnd; + if (currentHeapEnd + incr > &__HeapLimit) { + #if( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + #elif 0 + // If you want to alert debugger or halt... + while(1) { __asm("bkpt #0"); }; // Stop in GUI as if at a breakpoint (if debugging, otherwise loop forever) + #else + // If you prefer to believe your application will gracefully trap out-of-memory... + _impure_ptr->_errno = ENOMEM; // newlib's thread-specific errno + xTaskResumeAll(); + #endif + return (char *)-1; // the malloc-family routine that called sbrk will return 0 + } + currentHeapEnd += incr; + heapBytesRemaining -= incr; + #ifndef NDEBUG + totalBytesProvidedBySBRK += incr; + #endif + xTaskResumeAll(); + return (char *) previousHeapEnd; +} +//! Synonym for sbrk. +char * _sbrk(int incr) { return sbrk(incr); }; + +void __malloc_lock() { vTaskSuspendAll(); }; +void __malloc_unlock() { (void)xTaskResumeAll(); }; + +// newlib also requires implementing locks for the application's environment memory space, +// accessed by newlib's setenv() and getenv() functions. +// As these are trivial functions, momentarily suspend task switching (rather than semaphore). +// ToDo: Move __env_lock/unlock to a separate newlib helper file. +void __env_lock() { vTaskSuspendAll(); }; +void __env_unlock() { (void)xTaskResumeAll(); }; + +/// /brief Wrap malloc/malloc_r to help debug who requests memory and why. +/// Add to the linker command line: -Xlinker --wrap=malloc -Xlinker --wrap=_malloc_r +// Note: These functions are normally unused and stripped by linker. +void *__wrap_malloc(size_t nbytes) { + extern void * __real_malloc(size_t nbytes); + void *p = __real_malloc(nbytes); // Solely for debug breakpoint... + return p; +}; +void *__wrap__malloc_r(void *reent, size_t nbytes) { + extern void * __real__malloc_r(size_t nbytes); + void *p = __real__malloc_r(nbytes); // Solely for debug breakpoint... + return p; +}; + + +// ================================================================================================ +// Implement FreeRTOS's memory API using newlib-provided malloc family. +// ================================================================================================ + +void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION { + + void *p = malloc(xSize); + return p; +} +void vPortFree( void *pv ) PRIVILEGED_FUNCTION { + free(pv); +}; + +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION { + struct mallinfo mi = mallinfo(); + return mi.fordblks + heapBytesRemaining; +} + +// GetMinimumEverFree is not available in newlib's malloc implementation. +// So, no implementation provided: size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +//! No implementation needed, but stub provided in case application already calls vPortInitialiseBlocks +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION {}; diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoBooter/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoBooter/CMakeLists.txt new file mode 100644 index 0000000000..7535bcf31a --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoBooter/CMakeLists.txt @@ -0,0 +1,4 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# diff --git a/targets/TI-RTOS/CC3200/nanoCLR/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/CMakeLists.txt similarity index 70% rename from targets/TI-RTOS/CC3200/nanoCLR/CMakeLists.txt rename to targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/CMakeLists.txt index 3bd60b1509..246391d098 100644 --- a/targets/TI-RTOS/CC3200/nanoCLR/CMakeLists.txt +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/CMakeLists.txt @@ -4,9 +4,10 @@ # # append nanoCLR source files -list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main_blink.c") +# list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") # list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") -list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/pinmux.c") +# list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/pinmux.c") # make var global set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld new file mode 100644 index 0000000000..dd708baed7 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld @@ -0,0 +1,164 @@ +/***************************************************************************** +* blinky.ld +* +* GCC Linker script for blinky application. +* +* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * CC3200 generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08008000, len = 2M - 32k - 1792k /* flash size less the space reserved for nanoBooter and application deployment*/ + flash_itcm : org = 0x00208000, len = 2M - 32k - 1792k + deployment : org = 0x08040000, len = 1792k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h new file mode 100644 index 0000000000..49157f296d --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h @@ -0,0 +1,516 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 0 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +/////////////////////////////////////////////////////////////////////////////// +// address of vector table for nanoCLR +//#define CORTEX_VTOR_INIT 0x08008000U +/////////////////////////////////////////////////////////////////////////////// + +#endif /* CHCONF_H */ + +/** @} */ + diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h new file mode 100644 index 0000000000..056f370803 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h @@ -0,0 +1,384 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +// FIXME #include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +// #define HAL_USE_EXT FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 115200 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ + diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h new file mode 100644 index 0000000000..1371a05162 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h @@ -0,0 +1,20 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// Enables the ChibiOS community overlay. +#if !defined(HAL_USE_COMMUNITY) +#define HAL_USE_COMMUNITY TRUE +#endif + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +//#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c new file mode 100644 index 0000000000..801a272181 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c @@ -0,0 +1,112 @@ + +#include +#include +#include + + +// // Simplelink includes +// #include "simplelink.h" + +// // Driverlib includes +// #include "hw_types.h" +// #include "hw_ints.h" +// #include "hw_memmap.h" +// #include "hw_common_reg.h" +// #include "interrupt.h" +// #include "hw_apps_rcm.h" +// #include "prcm.h" +// #include "rom.h" +// #include "rom_map.h" +// #include "prcm.h" +// #include "gpio.h" +// #include "utils.h" + +// //Free_rtos/ti-rtos includes +// #include "osi.h" + +// // Common interface includes +// #include "gpio_if.h" +// #include "common.h" +// #include "pinmux.h" + + +void BlinkerThread(void const * argument) +{ + (void)argument; + + // palSetLineMode(1, PAL_MODE_OUTPUT_PUSHPULL); + + + // loop until thread receives a request to terminate + while (!chThdShouldTerminateX()) { + + // palSetPad(GPIOD, GPIOD_LED3); + // osDelay(500); + // palClearPad(GPIOD, GPIOD_LED3); + // osDelay(500); + + } + // nothing to deinitialize or cleanup, so it's safe to return +} +osThreadDef(BlinkerThread, osPriorityNormal, 128, "BlinkerThread"); + +// Application entry point. +int main(void) { + + osThreadId blinkerThreadId; + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + +// // init SWO as soon as possible to make it available to output ASAP +// #if (SWO_OUTPUT == TRUE) +// SwoInit(); +// #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + +// // the following IF is not mandatory, it's just providing a way for a user to 'force' +// // the board to remain in nanoBooter and not launching nanoCLR + +// // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter +// // the user button in this board has a pull-up resistor so the check has to be inverted +// if (palReadPad(GPIOA, GPIOA_BUTTON)) +// { +// // check for valid CLR image +// if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) +// { +// // there seems to be a valid CLR image +// // launch nanoCLR +// LaunchCLR((uint32_t)&__nanoImage_end__); +// } +// } + +// // Initializes a serial-over-USB CDC driver. +// sduObjectInit(&SDU1); +// sduStart(&SDU1, &serusbcfg); + +// // Activates the USB driver and then the USB bus pull-up on D+. +// // Note, a delay is inserted in order to not have to disconnect the cable after a reset. +// usbDisconnectBus(serusbcfg.usbp); +// chThdSleepMilliseconds(1500); +// usbStart(serusbcfg.usbp, &usbcfg); +// usbConnectBus(serusbcfg.usbp); + + // Creates the blinker thread, it does not start immediately. + blinkerThreadId = osThreadCreate(osThread(BlinkerThread), NULL); + +// // create the receiver thread +// receiverThreadId = osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // Normal main() thread + while (true) { + osDelay(500); + } +} diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c new file mode 100644 index 0000000000..05cc17cab9 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c @@ -0,0 +1,964 @@ + +// Standard includes +#include +#include + +#include "ch.h" +#include "hal.h" + +// Simplelink includes +#include "simplelink.h" + +//Driverlib includes +#include "hw_types.h" +#include "hw_ints.h" +#include "rom.h" +#include "rom_map.h" +#include "interrupt.h" +#include "prcm.h" +#include "utils.h" + +//Free_rtos/ti-rtos includes +#include "osi.h" + +//Common interface includes +#include "gpio_if.h" +#ifndef NOTERM +#include "uart_if.h" +#endif +#include "common.h" +#include "pinmux.h" + + +#define APPLICATION_NAME "WLAN STATION" +#define APPLICATION_VERSION "1.1.1" + +#define HOST_NAME "www.ti.com" + +// +// Values for below macros shall be modified for setting the 'Ping' properties +// +#define PING_INTERVAL 1000 /* In msecs */ +#define PING_TIMEOUT 3000 /* In msecs */ +#define PING_PKT_SIZE 20 /* In bytes */ +#define NO_OF_ATTEMPTS 3 + +#define OSI_STACK_SIZE 2048 + +// Application specific status/error codes +typedef enum{ + // Choosing -0x7D0 to avoid overlap w/ host-driver's error codes + LAN_CONNECTION_FAILED = -0x7D0, + INTERNET_CONNECTION_FAILED = LAN_CONNECTION_FAILED - 1, + DEVICE_NOT_IN_STATION_MODE = INTERNET_CONNECTION_FAILED - 1, + + STATUS_CODE_MAX = -0xBB8 +}e_AppStatusCodes; + + +//***************************************************************************** +// GLOBAL VARIABLES -- Start +//***************************************************************************** +unsigned long g_ulStatus = 0;//SimpleLink Status +unsigned long g_ulPingPacketsRecv = 0; //Number of Ping Packets received +unsigned long g_ulGatewayIP = 0; //Network Gateway IP address +unsigned char g_ucConnectionSSID[SSID_LEN_MAX+1]; //Connection SSID +unsigned char g_ucConnectionBSSID[BSSID_LEN_MAX]; //Connection BSSID + +#if defined(gcc) +extern void (* const g_pfnVectors[])(void); +#endif +#if defined(ewarm) +extern uVectorEntry __vector_table; +#endif +//***************************************************************************** +// GLOBAL VARIABLES -- End +//***************************************************************************** + + + +//**************************************************************************** +// LOCAL FUNCTION PROTOTYPES +//**************************************************************************** +static long WlanConnect(); +void WlanStationMode( void *pvParameters ); +static long CheckLanConnection(); +static long CheckInternetConnection(); +static void InitializeAppVariables(); +static long ConfigureSimpleLinkToDefaultState(); + + +#ifdef USE_FREERTOS +//***************************************************************************** +// FreeRTOS User Hook Functions enabled in FreeRTOSConfig.h +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Application defined hook (or callback) function - assert +//! +//! \param[in] pcFile - Pointer to the File Name +//! \param[in] ulLine - Line Number +//! +//! \return none +//! +//***************************************************************************** +void +vAssertCalled( const char *pcFile, unsigned long ulLine ) +{ + //Handle Assert here + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Application defined idle task hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void +vApplicationIdleHook( void) +{ + //Handle Idle Hook for Profiling, Power Management etc +} + +//***************************************************************************** +// +//! \brief Application defined malloc failed hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void vApplicationMallocFailedHook() +{ + //Handle Memory Allocation Errors + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Application defined stack overflow hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void vApplicationStackOverflowHook( OsiTaskHandle *pxTask, + signed char *pcTaskName) +{ + //Handle FreeRTOS Stack Overflow + while(1) + { + } +} +#endif //USE_FREERTOS + + +//***************************************************************************** +// SimpleLink Asynchronous Event Handlers -- Start +//***************************************************************************** + + +//***************************************************************************** +// +//! \brief The Function Handles WLAN Events +//! +//! \param[in] pWlanEvent - Pointer to WLAN Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) +{ + switch(pWlanEvent->Event) + { + case SL_WLAN_CONNECT_EVENT: + { + SET_STATUS_BIT(g_ulStatus, STATUS_BIT_CONNECTION); + + // + // Information about the connected AP (like name, MAC etc) will be + // available in 'slWlanConnectAsyncResponse_t'-Applications + // can use it if required + // + // slWlanConnectAsyncResponse_t *pEventData = NULL; + // pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected; + // + + // Copy new connection SSID and BSSID to global parameters + memcpy(g_ucConnectionSSID,pWlanEvent->EventData. + STAandP2PModeWlanConnected.ssid_name, + pWlanEvent->EventData.STAandP2PModeWlanConnected.ssid_len); + memcpy(g_ucConnectionBSSID, + pWlanEvent->EventData.STAandP2PModeWlanConnected.bssid, + SL_BSSID_LENGTH); + + UART_PRINT("[WLAN EVENT] STA Connected to the AP: %s ," + "BSSID: %x:%x:%x:%x:%x:%x\n\r", + g_ucConnectionSSID,g_ucConnectionBSSID[0], + g_ucConnectionBSSID[1],g_ucConnectionBSSID[2], + g_ucConnectionBSSID[3],g_ucConnectionBSSID[4], + g_ucConnectionBSSID[5]); + } + break; + + case SL_WLAN_DISCONNECT_EVENT: + { + slWlanConnectAsyncResponse_t* pEventData = NULL; + + CLR_STATUS_BIT(g_ulStatus, STATUS_BIT_CONNECTION); + CLR_STATUS_BIT(g_ulStatus, STATUS_BIT_IP_AQUIRED); + + pEventData = &pWlanEvent->EventData.STAandP2PModeDisconnected; + + // If the user has initiated 'Disconnect' request, + //'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED_DISCONNECTION + if(SL_WLAN_DISCONNECT_USER_INITIATED_DISCONNECTION == pEventData->reason_code) + { + UART_PRINT("[WLAN EVENT]Device disconnected from the AP: %s," + "BSSID: %x:%x:%x:%x:%x:%x on application's request \n\r", + g_ucConnectionSSID,g_ucConnectionBSSID[0], + g_ucConnectionBSSID[1],g_ucConnectionBSSID[2], + g_ucConnectionBSSID[3],g_ucConnectionBSSID[4], + g_ucConnectionBSSID[5]); + } + else + { + UART_PRINT("[WLAN ERROR]Device disconnected from the AP AP: %s," + "BSSID: %x:%x:%x:%x:%x:%x on an ERROR..!! \n\r", + g_ucConnectionSSID,g_ucConnectionBSSID[0], + g_ucConnectionBSSID[1],g_ucConnectionBSSID[2], + g_ucConnectionBSSID[3],g_ucConnectionBSSID[4], + g_ucConnectionBSSID[5]); + } + memset(g_ucConnectionSSID,0,sizeof(g_ucConnectionSSID)); + memset(g_ucConnectionBSSID,0,sizeof(g_ucConnectionBSSID)); + } + break; + + default: + { + UART_PRINT("[WLAN EVENT] Unexpected event [0x%x]\n\r", + pWlanEvent->Event); + } + break; + } +} + +//***************************************************************************** +// +//! \brief This function handles network events such as IP acquisition, IP +//! leased, IP released etc. +//! +//! \param[in] pNetAppEvent - Pointer to NetApp Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) +{ + switch(pNetAppEvent->Event) + { + case SL_NETAPP_IPV4_IPACQUIRED_EVENT: + { + SlIpV4AcquiredAsync_t *pEventData = NULL; + + SET_STATUS_BIT(g_ulStatus, STATUS_BIT_IP_AQUIRED); + + //Ip Acquired Event Data + pEventData = &pNetAppEvent->EventData.ipAcquiredV4; + + //Gateway IP address + g_ulGatewayIP = pEventData->gateway; + + UART_PRINT("[NETAPP EVENT] IP Acquired: IP=%d.%d.%d.%d , " + "Gateway=%d.%d.%d.%d\n\r", + SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.ip,3), + SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.ip,2), + SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.ip,1), + SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.ip,0), + SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.gateway,3), + SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.gateway,2), + SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.gateway,1), + SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.gateway,0)); + } + break; + + default: + { + UART_PRINT("[NETAPP EVENT] Unexpected event [0x%x] \n\r", + pNetAppEvent->Event); + } + break; + } +} + + +//***************************************************************************** +// +//! \brief This function handles HTTP server events +//! +//! \param[in] pServerEvent - Contains the relevant event information +//! \param[in] pServerResponse - Should be filled by the user with the +//! relevant response information +//! +//! \return None +//! +//**************************************************************************** +void SimpleLinkHttpServerCallback(SlHttpServerEvent_t *pHttpEvent, + SlHttpServerResponse_t *pHttpResponse) +{ + // Unused in this application +} + +//***************************************************************************** +// +//! \brief This function handles General Events +//! +//! \param[in] pDevEvent - Pointer to General Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent) +{ + // + // Most of the general errors are not FATAL are are to be handled + // appropriately by the application + // + UART_PRINT("[GENERAL EVENT] - ID=[%d] Sender=[%d]\n\n", + pDevEvent->EventData.deviceEvent.status, + pDevEvent->EventData.deviceEvent.sender); +} + + +//***************************************************************************** +// +//! This function handles socket events indication +//! +//! \param[in] pSock - Pointer to Socket Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) +{ + // + // This application doesn't work w/ socket - Events are not expected + // + switch( pSock->Event ) + { + case SL_SOCKET_TX_FAILED_EVENT: + switch( pSock->socketAsyncEvent.SockTxFailData.status) + { + case SL_ECLOSE: + UART_PRINT("[SOCK ERROR] - close socket (%d) operation " + "failed to transmit all queued packets\n\n", + pSock->socketAsyncEvent.SockTxFailData.sd); + break; + default: + UART_PRINT("[SOCK ERROR] - TX FAILED : socket %d , reason " + "(%d) \n\n", + pSock->socketAsyncEvent.SockTxFailData.sd, pSock->socketAsyncEvent.SockTxFailData.status); + break; + } + break; + + default: + UART_PRINT("[SOCK EVENT] - Unexpected Event [%x0x]\n\n",pSock->Event); + break; + } + +} + + +//***************************************************************************** +// +//! \brief This function handles ping report events +//! +//! \param[in] pPingReport - Ping report statistics +//! +//! \return None +//! +//***************************************************************************** +static void SimpleLinkPingReport(SlPingReport_t *pPingReport) +{ + SET_STATUS_BIT(g_ulStatus, STATUS_BIT_PING_DONE); + g_ulPingPacketsRecv = pPingReport->PacketsReceived; +} + +//***************************************************************************** +// SimpleLink Asynchronous Event Handlers -- End +//***************************************************************************** + + + +//***************************************************************************** +// +//! \brief This function initializes the application variables +//! +//! \param None +//! +//! \return None +//! +//***************************************************************************** +static void InitializeAppVariables() +{ + g_ulStatus = 0; + g_ulPingPacketsRecv = 0; + g_ulGatewayIP = 0; + memset(g_ucConnectionSSID,0,sizeof(g_ucConnectionSSID)); + memset(g_ucConnectionBSSID,0,sizeof(g_ucConnectionBSSID)); +} + + +//***************************************************************************** +//! \brief This function puts the device in its default state. It: +//! - Set the mode to STATION +//! - Configures connection policy to Auto and AutoSmartConfig +//! - Deletes all the stored profiles +//! - Enables DHCP +//! - Disables Scan policy +//! - Sets Tx power to maximum +//! - Sets power policy to normal +//! - Unregister mDNS services +//! - Remove all filters +//! +//! \param none +//! \return On success, zero is returned. On error, negative is returned +//***************************************************************************** + +static long ConfigureSimpleLinkToDefaultState() +{ + SlVersionFull ver = {0}; + _WlanRxFilterOperationCommandBuff_t RxFilterIdMask = {0}; + + unsigned char ucVal = 1; + unsigned char ucConfigOpt = 0; + unsigned char ucConfigLen = 0; + unsigned char ucPower = 0; + + long lRetVal = -1; + long lMode = -1; + + lMode = sl_Start(0, 0, 0); + ASSERT_ON_ERROR(lMode); + + // If the device is not in station-mode, try configuring it in station-mode + if (ROLE_STA != lMode) + { + if (ROLE_AP == lMode) + { + // If the device is in AP mode, we need to wait for this event + // before doing anything + while(!IS_IP_ACQUIRED(g_ulStatus)) + { +#ifndef SL_PLATFORM_MULTI_THREADED + _SlNonOsMainLoopTask(); +#endif + } + } + + // Switch to STA role and restart + lRetVal = sl_WlanSetMode(ROLE_STA); + ASSERT_ON_ERROR(lRetVal); + + lRetVal = sl_Stop(0xFF); + ASSERT_ON_ERROR(lRetVal); + + lRetVal = sl_Start(0, 0, 0); + ASSERT_ON_ERROR(lRetVal); + + // Check if the device is in station again + if (ROLE_STA != lRetVal) + { + // We don't want to proceed if the device is not coming up in STA-mode + ASSERT_ON_ERROR(DEVICE_NOT_IN_STATION_MODE); + } + } + + // Get the device's version-information + ucConfigOpt = SL_DEVICE_GENERAL_VERSION; + ucConfigLen = sizeof(ver); + lRetVal = sl_DevGet(SL_DEVICE_GENERAL_CONFIGURATION, &ucConfigOpt, + &ucConfigLen, (unsigned char *)(&ver)); + ASSERT_ON_ERROR(lRetVal); + + UART_PRINT("Host Driver Version: %s\n\r",SL_DRIVER_VERSION); + UART_PRINT("Build Version %d.%d.%d.%d.31.%d.%d.%d.%d.%d.%d.%d.%d\n\r", + ver.NwpVersion[0],ver.NwpVersion[1],ver.NwpVersion[2],ver.NwpVersion[3], + ver.ChipFwAndPhyVersion.FwVersion[0],ver.ChipFwAndPhyVersion.FwVersion[1], + ver.ChipFwAndPhyVersion.FwVersion[2],ver.ChipFwAndPhyVersion.FwVersion[3], + ver.ChipFwAndPhyVersion.PhyVersion[0],ver.ChipFwAndPhyVersion.PhyVersion[1], + ver.ChipFwAndPhyVersion.PhyVersion[2],ver.ChipFwAndPhyVersion.PhyVersion[3]); + + // Set connection policy to Auto + SmartConfig + // (Device's default connection policy) + lRetVal = sl_WlanPolicySet(SL_POLICY_CONNECTION, + SL_CONNECTION_POLICY(1, 0, 0, 0, 1), NULL, 0); + ASSERT_ON_ERROR(lRetVal); + + // Remove all profiles + lRetVal = sl_WlanProfileDel(0xFF); + ASSERT_ON_ERROR(lRetVal); + + + + // + // Device in station-mode. Disconnect previous connection if any + // The function returns 0 if 'Disconnected done', negative number if already + // disconnected Wait for 'disconnection' event if 0 is returned, Ignore + // other return-codes + // + lRetVal = sl_WlanDisconnect(); + if(0 == lRetVal) + { + // Wait + while(IS_CONNECTED(g_ulStatus)) + { +#ifndef SL_PLATFORM_MULTI_THREADED + _SlNonOsMainLoopTask(); +#endif + } + } + + // Enable DHCP client + lRetVal = sl_NetCfgSet(SL_IPV4_STA_P2P_CL_DHCP_ENABLE,1,1,&ucVal); + ASSERT_ON_ERROR(lRetVal); + + // Disable scan + ucConfigOpt = SL_SCAN_POLICY(0); + lRetVal = sl_WlanPolicySet(SL_POLICY_SCAN , ucConfigOpt, NULL, 0); + ASSERT_ON_ERROR(lRetVal); + + // Set Tx power level for station mode + // Number between 0-15, as dB offset from max power - 0 will set max power + ucPower = 0; + lRetVal = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, + WLAN_GENERAL_PARAM_OPT_STA_TX_POWER, 1, (unsigned char *)&ucPower); + ASSERT_ON_ERROR(lRetVal); + + // Set PM policy to normal + lRetVal = sl_WlanPolicySet(SL_POLICY_PM , SL_NORMAL_POLICY, NULL, 0); + ASSERT_ON_ERROR(lRetVal); + + // Unregister mDNS services + lRetVal = sl_NetAppMDNSUnRegisterService(0, 0); + ASSERT_ON_ERROR(lRetVal); + + // Remove all 64 filters (8*8) + memset(RxFilterIdMask.FilterIdMask, 0xFF, 8); + lRetVal = sl_WlanRxFilterSet(SL_REMOVE_RX_FILTER, (_u8 *)&RxFilterIdMask, + sizeof(_WlanRxFilterOperationCommandBuff_t)); + ASSERT_ON_ERROR(lRetVal); + + lRetVal = sl_Stop(SL_STOP_TIMEOUT); + ASSERT_ON_ERROR(lRetVal); + + InitializeAppVariables(); + + return lRetVal; // Success +} + +//***************************************************************************** +//! \brief This function checks the LAN connection by pinging the AP's gateway +//! +//! \param None +//! +//! \return 0 on success, negative error-code on error +//! +//***************************************************************************** +static long CheckLanConnection() +{ + SlPingStartCommand_t pingParams = {0}; + SlPingReport_t pingReport = {0}; + + long lRetVal = -1; + + CLR_STATUS_BIT(g_ulStatus, STATUS_BIT_PING_DONE); + g_ulPingPacketsRecv = 0; + + // Set the ping parameters + pingParams.PingIntervalTime = PING_INTERVAL; + pingParams.PingSize = PING_PKT_SIZE; + pingParams.PingRequestTimeout = PING_TIMEOUT; + pingParams.TotalNumberOfAttempts = NO_OF_ATTEMPTS; + pingParams.Flags = 0; + pingParams.Ip = g_ulGatewayIP; + + // Check for LAN connection + lRetVal = sl_NetAppPingStart((SlPingStartCommand_t*)&pingParams, SL_AF_INET, + (SlPingReport_t*)&pingReport, SimpleLinkPingReport); + ASSERT_ON_ERROR(lRetVal); + + // Wait for NetApp Event + while(!IS_PING_DONE(g_ulStatus)) + { +#ifndef SL_PLATFORM_MULTI_THREADED + _SlNonOsMainLoopTask(); +#endif + } + + if(0 == g_ulPingPacketsRecv) + { + //Problem with LAN connection + ASSERT_ON_ERROR(LAN_CONNECTION_FAILED); + } + + // LAN connection is successful + return SUCCESS; +} + + +//***************************************************************************** +//! \brief This function checks the internet connection by pinging +//! the external-host (HOST_NAME) +//! +//! \param None +//! +//! \return 0 on success, negative error-code on error +//! +//***************************************************************************** +static long CheckInternetConnection() +{ + SlPingStartCommand_t pingParams = {0}; + SlPingReport_t pingReport = {0}; + + unsigned long ulIpAddr = 0; + long lRetVal = -1; + + CLR_STATUS_BIT(g_ulStatus, STATUS_BIT_PING_DONE); + g_ulPingPacketsRecv = 0; + + // Set the ping parameters + pingParams.PingIntervalTime = PING_INTERVAL; + pingParams.PingSize = PING_PKT_SIZE; + pingParams.PingRequestTimeout = PING_TIMEOUT; + pingParams.TotalNumberOfAttempts = NO_OF_ATTEMPTS; + pingParams.Flags = 0; + pingParams.Ip = g_ulGatewayIP; + + // Get external host IP address + lRetVal = sl_NetAppDnsGetHostByName((signed char*)HOST_NAME, sizeof(HOST_NAME), + &ulIpAddr, SL_AF_INET); + ASSERT_ON_ERROR(lRetVal); + + // Replace the ping address to match HOST_NAME's IP address + pingParams.Ip = ulIpAddr; + + // Try to ping HOST_NAME + lRetVal = sl_NetAppPingStart((SlPingStartCommand_t*)&pingParams, SL_AF_INET, + (SlPingReport_t*)&pingReport, SimpleLinkPingReport); + ASSERT_ON_ERROR(lRetVal); + + // Wait + while(!IS_PING_DONE(g_ulStatus)) + { + // Wait for Ping Event +#ifndef SL_PLATFORM_MULTI_THREADED + _SlNonOsMainLoopTask(); +#endif + } + + if (0 == g_ulPingPacketsRecv) + { + // Problem with internet connection + ASSERT_ON_ERROR(INTERNET_CONNECTION_FAILED); + } + + // Internet connection is successful + return SUCCESS; +} + + +//**************************************************************************** +// +//! \brief Connecting to a WLAN Accesspoint +//! +//! This function connects to the required AP (SSID_NAME) with Security +//! parameters specified in te form of macros at the top of this file +//! +//! \param None +//! +//! \return None +//! +//! \warning If the WLAN connection fails or we don't aquire an IP +//! address, It will be stuck in this function forever. +// +//**************************************************************************** +static long WlanConnect() +{ + SlSecParams_t secParams = {0}; + long lRetVal = 0; + + secParams.Key = (signed char*)SECURITY_KEY; + secParams.KeyLen = strlen(SECURITY_KEY); + secParams.Type = SECURITY_TYPE; + + lRetVal = sl_WlanConnect((signed char*)SSID_NAME, strlen(SSID_NAME), 0, &secParams, 0); + ASSERT_ON_ERROR(lRetVal); + + // Wait for WLAN Event + while((!IS_CONNECTED(g_ulStatus)) || (!IS_IP_ACQUIRED(g_ulStatus))) + { + // Toggle LEDs to Indicate Connection Progress + GPIO_IF_LedOff(MCU_IP_ALLOC_IND); + MAP_UtilsDelay(800000); + GPIO_IF_LedOn(MCU_IP_ALLOC_IND); + MAP_UtilsDelay(800000); + } + + return SUCCESS; + +} + +//**************************************************************************** +// +//! \brief Start simplelink, connect to the ap and run the ping test +//! +//! This function starts the simplelink, connect to the ap and start the ping +//! test on the default gateway for the ap +//! +//! \param[in] pvParameters - Pointer to the list of parameters that +//! can bepassed to the task while creating it +//! +//! \return None +// +//**************************************************************************** +void WlanStationMode( void *pvParameters ) +{ + + long lRetVal = -1; + InitializeAppVariables(); + + // + // Following function configure the device to default state by cleaning + // the persistent settings stored in NVMEM (viz. connection profiles & + // policies, power policy etc) + // + // Applications may choose to skip this step if the developer is sure + // that the device is in its default state at start of applicaton + // + // Note that all profiles and persistent settings that were done on the + // device will be lost + // + lRetVal = ConfigureSimpleLinkToDefaultState(); + if(lRetVal < 0) + { + if (DEVICE_NOT_IN_STATION_MODE == lRetVal) + { + UART_PRINT("Failed to configure the device in its default state\n\r"); + } + + LOOP_FOREVER(); + } + + UART_PRINT("Device is configured in default state \n\r"); + + // + // Assumption is that the device is configured in station mode already + // and it is in its default state + // + lRetVal = sl_Start(0, 0, 0); + if (lRetVal < 0 || ROLE_STA != lRetVal) + { + UART_PRINT("Failed to start the device \n\r"); + LOOP_FOREVER(); + } + + UART_PRINT("Device started as STATION \n\r"); + + // + //Connecting to WLAN AP + // + lRetVal = WlanConnect(); + if(lRetVal < 0) + { + UART_PRINT("Failed to establish connection w/ an AP \n\r"); + LOOP_FOREVER(); + } + + UART_PRINT("Connection established w/ AP and IP is aquired \n\r"); + UART_PRINT("Pinging...! \n\r"); + + // + // Checking the Lan connection by pinging to AP gateway + // + lRetVal = CheckLanConnection(); + if(lRetVal < 0) + { + UART_PRINT("Device couldn't ping the gateway \n\r"); + LOOP_FOREVER(); + } + + // Turn on GREEN LED when device gets PING response from AP + GPIO_IF_LedOn(MCU_EXECUTE_SUCCESS_IND); + + // + // Checking the internet connection by pinging to external host + // + lRetVal = CheckInternetConnection(); + if(lRetVal < 0) + { + UART_PRINT("Device couldn't ping the external host \n\r"); + LOOP_FOREVER(); + } + + // Turn on ORAGE LED when device gets PING response from AP + GPIO_IF_LedOn(MCU_ORANGE_LED_GPIO); + + UART_PRINT("Device pinged both the gateway and the external host \n\r"); + + UART_PRINT("WLAN STATION example executed successfully \n\r"); + + // + // power off the network processor + // + lRetVal = sl_Stop(SL_STOP_TIMEOUT); + + LOOP_FOREVER(); + +} +//***************************************************************************** +// +//! Application startup display on UART +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +static void +DisplayBanner(char * AppName) +{ + + UART_PRINT("\n\n\n\r"); + UART_PRINT("\t\t *************************************************\n\r"); + UART_PRINT("\t\t CC3200 %s Application \n\r", AppName); + UART_PRINT("\t\t *************************************************\n\r"); + UART_PRINT("\n\n\n\r"); +} +//***************************************************************************** +// +//! \brief Board Initialization & Configuration +//! +//! \param None +//! +//! \return None +// +//***************************************************************************** +static void +BoardInit(void) +{ +// In case of TI-RTOS vector table is initialize by OS itself +#ifndef USE_TIRTOS + // + // Set vector table base + // +#if defined(ccs) || defined(gcc) + MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]); +#endif +#if defined(ewarm) + MAP_IntVTableBaseSet((unsigned long)&__vector_table); +#endif +#endif //USE_TIRTOS + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // + // Enable Processor + // + MAP_IntMasterEnable(); + MAP_IntEnable(FAULT_SYSTICK); + + PRCMCC3200MCUInit(); +} + + +//***************************************************************************** +// MAIN FUNCTION +//***************************************************************************** +void main() +{ + long lRetVal = -1; + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // + // Board Initialization + // + BoardInit(); + + // + // configure the GPIO pins for LEDs,UART + // + PinMuxConfig(); + + // + // Configure the UART + // +#ifndef NOTERM + InitTerm(); +#endif //NOTERM + + // + // Display Application Banner + // + DisplayBanner(APPLICATION_NAME); + + // + // Configure all 3 LEDs + // + GPIO_IF_LedConfigure(LED1|LED2|LED3); + + // switch off all LEDs + GPIO_IF_LedOff(MCU_ALL_LED_IND); + + // + // Start the SimpleLink Host + // + lRetVal = VStartSimpleLinkSpawnTask(SPAWN_TASK_PRIORITY); + if(lRetVal < 0) + { + ERR_PRINT(lRetVal); + LOOP_FOREVER(); + } + + // + // Start the WlanStationMode task + // + lRetVal = osi_TaskCreate( WlanStationMode, \ + (const signed char*)"Wlan Station Task", \ + OSI_STACK_SIZE, NULL, 1, NULL ); + if(lRetVal < 0) + { + ERR_PRINT(lRetVal); + LOOP_FOREVER(); + } + + // + // Start the task scheduler + // + osi_start(); + } + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h new file mode 100644 index 0000000000..9acef485fe --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h @@ -0,0 +1,76 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * CC3200 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 7...0 Lowest...Highest. + */ + +#define TICC3200_MCUCONF + + +/* + * HAL driver system settings. + */ +#define TICC3200_OSCSRC SYSCTL_RCC2_OSCSRC2_MO +#define TICC3200_MOSC_ENABLE TRUE +#define TICC3200_DIV400_VALUE 1 +#define TICC3200_SYSDIV_VALUE 2 +#define TICC3200_USESYSDIV_ENABLE FALSE +#define TICC3200_SYSDIV2LSB_ENABLE FALSE +#define TICC3200_BYPASS_VALUE 0 +#define TICC3200_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ + SYSCTL_RCC_PWMDIV_8) + +/* + * GPIO driver system settings. + */ +#define TICC3200_GPIO_GPIOA_USE_AHB TRUE +#define TICC3200_GPIO_GPIOB_USE_AHB TRUE +#define TICC3200_GPIO_GPIOC_USE_AHB TRUE +#define TICC3200_GPIO_GPIOD_USE_AHB TRUE +#define TICC3200_GPIO_GPIOE_USE_AHB TRUE +#define TICC3200_GPIO_GPIOF_USE_AHB TRUE + +/* + * GPT driver system settings. + */ +#define TICC3200_GPT_USE_GPT0 FALSE +#define TICC3200_GPT_USE_GPT1 FALSE +#define TICC3200_GPT_USE_GPT2 FALSE +#define TICC3200_GPT_USE_GPT3 FALSE + +#define TICC3200_GPT_GPT0A_IRQ_PRIORITY 7 +#define TICC3200_GPT_GPT1A_IRQ_PRIORITY 7 +#define TICC3200_GPT_GPT2A_IRQ_PRIORITY 7 +#define TICC3200_GPT_GPT3A_IRQ_PRIORITY 7 +/* + * SERIAL driver system settings. + */ +#define TICC3200_SERIAL_USE_UART0 TRUE +#define TICC3200_SERIAL_USE_UART1 FALSE +#define TICC3200_SERIAL_UART0_PRIORITY 5 +#define TICC3200_SERIAL_UART1_PRIORITY 5 + +/* + * ST driver system settings. + */ +#define TICC3200_ST_IRQ_PRIORITY 2 +#define TICC3200_ST_TIMER_NUMBER 0 +#define TICC3200_ST_TIMER_LETTER A + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h new file mode 100644 index 0000000000..37dc82fd91 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/targets/TI-RTOS/CC3200/nanoCLR/pinmux.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.c similarity index 91% rename from targets/TI-RTOS/CC3200/nanoCLR/pinmux.c rename to targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.c index 0372791e85..8d42df1685 100644 --- a/targets/TI-RTOS/CC3200/nanoCLR/pinmux.c +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.c @@ -59,6 +59,17 @@ PinMuxConfig(void) // Enable Peripheral Clocks // MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK); + MAP_PRCMPeripheralClkEnable(PRCM_UARTA0, PRCM_RUN_MODE_CLK); + + // + // Configure PIN_55 for UART0 UART0_TX + // + MAP_PinTypeUART(PIN_55, PIN_MODE_3); + + // + // Configure PIN_57 for UART0 UART0_RX + // + MAP_PinTypeUART(PIN_57, PIN_MODE_3); // // Configure PIN_64 for GPIOOutput diff --git a/targets/TI-RTOS/CC3200/nanoCLR/pinmux.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.h similarity index 100% rename from targets/TI-RTOS/CC3200/nanoCLR/pinmux.h rename to targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.h diff --git a/targets/TI-RTOS/CC3200/nanoCLR/target_board.h.in b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/target_board.h.in similarity index 100% rename from targets/TI-RTOS/CC3200/nanoCLR/target_board.h.in rename to targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/target_board.h.in diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c new file mode 100644 index 0000000000..e366395cf7 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c @@ -0,0 +1,791 @@ +//***************************************************************************** +// osi_chibios.c +// +// Interface APIs for ChibiOS function calls +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + + +#include +#include +#include +#include +#include +#include + +#include "rom.h" +#include "rom_map.h" +#include "hw_types.h" +#include "interrupt.h" + +//Local function definition +static void vSimpleLinkSpawnTask( void *pvParameters ); + +// Queue Handler +// Queue size +#define slQUEUE_SIZE 3 + +osMessageQDef(simpleLink_mailbox, slQUEUE_SIZE, tSimpleLinkSpawnMsg); +osMessageQId(simpleLink_mailbox_id); + +osThreadId SimpleLinkSpawnTaskHndl; + + +/*! + \brief This function registers an interrupt in NVIC table + + The sync object is used for synchronization between different thread or ISR and + a thread. + + \param iIntrNum - Interrupt number to register + \param pEntry - Pointer to the interrupt handler + \param ucPriority - priority of the interrupt + + \return upon successful creation the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_InterruptRegister(int iIntrNum,P_OSI_INTR_ENTRY pEntry,unsigned char ucPriority) +{ + MAP_IntRegister(iIntrNum,(void(*)(void))pEntry); + MAP_IntPrioritySet(iIntrNum, ucPriority); + MAP_IntEnable(iIntrNum); + return OSI_OK; +} + +/*! + \brief This function De registers an interrupt in NVIC table + + + \param iIntrNum - Interrupt number to De register + + \return none + \note + \warning +*/ + +void osi_InterruptDeRegister(int iIntrNum) +{ + MAP_IntDisable(iIntrNum); + MAP_IntUnregister(iIntrNum); +} + +/*! + \brief This function creates a sync object + + The sync object is used for synchronization between different thread or ISR and + a thread. + + \param pSyncObj - pointer to the sync object control block + + \return upon successful creation the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_SyncObjCreate(OsiSyncObj_t* pSyncObj) +{ + if(pSyncObj == NULL) + { + return OSI_INVALID_PARAMS; + } + + osSemaphoreId semaphore_id = osSemaphoreCreate(NULL, 1); + if (semaphore_id == NULL) + { + *pSyncObj = NULL; + return OSI_FAILURE; + } + + *pSyncObj = (OsiSyncObj_t)semaphore_id; + + return OSI_OK; +} + +/*! + \brief This function deletes a sync object + + \param pSyncObj - pointer to the sync object control block + + \return upon successful deletion the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_SyncObjDelete(OsiSyncObj_t* pSyncObj) +{ + if(pSyncObj == NULL) + { + return OSI_INVALID_PARAMS; + } + + osSemaphoreDelete((osSemaphoreId*) pSyncObj); + + return OSI_OK; +} + +/*! + \brief This function generates a sync signal for the object. + + All suspended threads waiting on this sync object are resumed + + \param pSyncObj - pointer to the sync object control block + + \return upon successful signaling the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note the function could be called from ISR context + \warning +*/ +OsiReturnVal_e osi_SyncObjSignal(OsiSyncObj_t* pSyncObj) +{ + if(pSyncObj == NULL) + { + return OSI_INVALID_PARAMS; + } + + osSemaphoreRelease((osSemaphoreId)*pSyncObj); + + return OSI_OK; +} +/*! + \brief This function generates a sync signal for the object + from ISR context. + + All suspended threads waiting on this sync object are resumed + + \param pSyncObj - pointer to the sync object control block + + \return upon successful signalling the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note the function is called from ISR context + \warning +*/ +OsiReturnVal_e osi_SyncObjSignalFromISR(OsiSyncObj_t* pSyncObj) +{ + if(pSyncObj == NULL) + { + return OSI_INVALID_PARAMS; + } + + osSemaphoreRelease((osSemaphoreId)*pSyncObj); + + return OSI_OK; +} + +/*! + \brief This function waits for a sync signal of the specific sync object + + \param pSyncObj - pointer to the sync object control block + \param Timeout - numeric value specifies the maximum number of mSec to + stay suspended while waiting for the sync signal + Currently, the simple link driver uses only two values: + - OSI_WAIT_FOREVER + - OSI_NO_WAIT + + \return upon successful reception of the signal within the timeout window return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_SyncObjWait(OsiSyncObj_t* pSyncObj , OsiTime_t Timeout) +{ + if(pSyncObj == NULL) + { + return OSI_INVALID_PARAMS; + } + + if(osSemaphoreWait((osSemaphoreId)*pSyncObj, (uint32_t) Timeout) != osOK) + { + return OSI_OPERATION_FAILED; + } + + return OSI_OK; +} + +/*! + \brief This function clears a sync object + + \param pSyncObj - pointer to the sync object control block + + \return upon successful clearing the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_SyncObjClear(OsiSyncObj_t* pSyncObj) +{ + if(pSyncObj == NULL) + { + return OSI_INVALID_PARAMS; + } + + if (OSI_OK == osi_SyncObjWait(pSyncObj,0) ) + { + return OSI_OK; + } + else + { + return OSI_OPERATION_FAILED; + } +} + +/*! + \brief This function creates a locking object. + + The locking object is used for protecting a shared resources between different + threads. + + \param pLockObj - pointer to the locking object control block + + \return upon successful creation the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_LockObjCreate(OsiLockObj_t* pLockObj) +{ + if(pLockObj == NULL) + { + return OSI_INVALID_PARAMS; + } + + + osSemaphoreId semaphore_id = osSemaphoreCreate(NULL, 1); + if (semaphore_id == NULL) + { + *pLockObj = NULL; + return OSI_FAILURE; + } + + *pLockObj = (OsiLockObj_t)semaphore_id; + + return OSI_OK; +} + +/*! + \brief This function creates a Task. + + Creates a new Task and add it to the last of tasks that are ready to run + + \param pEntry - pointer to the Task Function + \param pcName - Task Name String + \param usStackDepth - Stack Size in bytes + \param pvParameters - pointer to structure to be passed to the Task Function + \param uxPriority - Task Priority + + \return upon successful creation the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_TaskCreate(P_OSI_TASK_ENTRY pEntry,const signed char * const pcName, + unsigned short usStackDepth, void *pvParameters, + unsigned long uxPriority,OsiTaskHandle* pTaskHandle) +{ + + osThreadDef_t threadDefinition; + threadDefinition.stacksize = usStackDepth; + threadDefinition.tpriority = uxPriority; + threadDefinition.name = pcName; + + osThreadId id = osThreadCreate(&threadDefinition, pvParameters); + + if(id != NULL) + { + *pTaskHandle = (OsiTaskHandle)id; + } + + if(id == NULL) + { + return OSI_FAILURE; + } + + return OSI_OK; +} + +/*! + \brief This function Deletes a Task. + + Deletes a Task and remove it from list of running task + + \param pTaskHandle - Task Handle + + \note + \warning +*/ +void osi_TaskDelete(OsiTaskHandle* pTaskHandle) +{ + osThreadTerminate((osThreadId)pTaskHandle); +} + +/*! + \brief This function deletes a locking object. + + \param pLockObj - pointer to the locking object control block + + \return upon successful deletion the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_LockObjDelete(OsiLockObj_t* pLockObj) +{ + osSemaphoreDelete((osSemaphoreId)*pLockObj ); + + return OSI_OK; +} + +/*! + \brief This function locks a locking object. + + All other threads that call this function before this thread calls + the osi_LockObjUnlock would be suspended + + \param pLockObj - pointer to the locking object control block + \param Timeout - numeric value specifies the maximum number of mSec to + stay suspended while waiting for the locking object + Currently, the simple link driver uses only two values: + - OSI_WAIT_FOREVER + - OSI_NO_WAIT + + + \return upon successful reception of the locking object the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_LockObjLock(OsiLockObj_t* pLockObj , OsiTime_t Timeout) +{ + if(pLockObj == NULL) + { + return OSI_INVALID_PARAMS; + } + + //Take Semaphore + if(osSemaphoreWait((osSemaphoreId)*pLockObj, (uint32_t) Timeout) != osOK) + { + return OSI_OPERATION_FAILED; + } + + return OSI_OK; +} + +/*! + \brief This function unlock a locking object. + + \param pLockObj - pointer to the locking object control block + + \return upon successful unlocking the function should return 0 + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ +OsiReturnVal_e osi_LockObjUnlock(OsiLockObj_t* pLockObj) +{ + + if(NULL == pLockObj) + { + return OSI_INVALID_PARAMS; + } + + //Release Semaphore + if(osSemaphoreRelease((osSemaphoreId)*pLockObj) == osOK) + { + return OSI_OK; + } + else + { + return OSI_OPERATION_FAILED; + } +} + +/*! + \brief This function call the pEntry callback from a different context + + \param pEntry - pointer to the entry callback function + + \param pValue - pointer to any type of memory structure that would be + passed to pEntry callback from the execution thread. + + \param flags - execution flags - reserved for future usage + + \return upon successful registration of the spawn the function should return 0 + (the function is not blocked till the end of the execution of the function + and could be returned before the execution is actually completed) + Otherwise, a negative value indicating the error code shall be returned + \note + \warning +*/ + +OsiReturnVal_e osi_Spawn(P_OSI_SPAWN_ENTRY pEntry , void* pValue , unsigned long flags) +{ + tSimpleLinkSpawnMsg Msg; + Msg.pEntry = pEntry; + Msg.pValue = pValue; + + if(osMessagePut(simpleLink_mailbox_id, &Msg, osWaitForever) == osOK) + { + return OSI_OK; + } + + return OSI_OPERATION_FAILED; +} + +/*! + \brief This is the simplelink spawn task to call SL callback from a different context + + \param pvParameters - pointer to the task parameter + + \return void + \note + \warning +*/ +void vSimpleLinkSpawnTask(void *pvParameters) +{ + tSimpleLinkSpawnMsg* Msg; + osEvent event; + + for(;;) + { + event = osMessageGet(simpleLink_mailbox_id, osWaitForever); + if(event.status == osEventMessage) + { + Msg = (tSimpleLinkSpawnMsg*)event.value.p; + Msg->pEntry(Msg->pValue); + } + } +} + +/*! + \brief This is the API to create SL spawn task and create the SL queue + + \param uxPriority - task priority + + \return void + \note + \warning +*/ +OsiReturnVal_e VStartSimpleLinkSpawnTask(unsigned long uxPriority) +{ + simpleLink_mailbox_id = osMessageCreate(osMessageQ(simpleLink_mailbox), NULL); + + osThreadDef(vSimpleLinkSpawnTask, uxPriority, 2048, "SimpleLinkTask"); + + SimpleLinkSpawnTaskHndl = osThreadCreate(osThread(vSimpleLinkSpawnTask), NULL); + if (SimpleLinkSpawnTaskHndl == NULL) + { + return OSI_OPERATION_FAILED; + } + + return OSI_OK; +} + +/*! + \brief This is the API to delete SL spawn task and delete the SL queue + + \param none + + \return void + \note + \warning +*/ +void VDeleteSimpleLinkSpawnTask( void ) +{ + osThreadTerminate(SimpleLinkSpawnTaskHndl); +} + +/*! + \brief This function to call the memory allocation function of the RTOS + + \param pMem - pointer to the memory which needs to be freed + + \return - void * + \note + \warning +*/ + +void * mem_Malloc(unsigned long Size) +{ + return ( void * )chHeapAlloc(NULL, Size); +} + +/*! + \brief This function to call the memory de-allocation function of the RTOS + + \param pMem - pointer to the memory which needs to be freed + + \return - void + \note + \warning +*/ +void mem_Free(void *pMem) +{ + chHeapFree(pMem); +} + +/*! + \brief This function call the memset function + \param pBuf - pointer to the memory to be fill + \param Val - Value to be fill + \param Size - Size of the memory which needs to be fill + + \return - void + \note + \warning +*/ + +void mem_set(void *pBuf, int Val, size_t Size) +{ + memset(pBuf, Val, Size); +} + +/*! + \brief This function call the memset function + \param pDst - pointer to the destination + \param pSrc - pointer to the source + \param Size - Size of the memory which needs to be copy + + \return - void + \note + \warning +*/ +void mem_copy(void *pDst, void *pSrc, size_t Size) +{ + memcpy(pDst, pSrc, Size); +} + + +/*! + \brief This function use to entering into critical section + \param void + \return - void + \note + \warning +*/ + +unsigned long osi_EnterCritical(void) +{ + chSysLock(); + return 0; +} + +/*! + \brief This function use to exit critical section + \param void + \return - void + \note + \warning +*/ + +void osi_ExitCritical(unsigned long ulKey) +{ + chSysUnlock(); +} + +/*! + \brief This function is used to create the MsgQ + + \param pMsgQ - pointer to the message queue + \param pMsgQName - msg queue name + \param MsgSize - size of message on the queue + \param MaxMsgs - max. number of msgs that the queue can hold + + \return - OsiReturnVal_e + \note + \warning +*/ +OsiReturnVal_e osi_MsgQCreate(OsiMsgQ_t* pMsgQ , + char* pMsgQName, + unsigned long MsgSize, + unsigned long MaxMsgs) +{ + + if(NULL == pMsgQ) + { + return OSI_INVALID_PARAMS; + } + + *pMsgQ = (OsiMsgQ_t)osMessageCreate((osMessageQDef_t*)pMsgQ, NULL); + + if (*pMsgQ == NULL) + { + return OSI_OPERATION_FAILED; + } + + return OSI_OK; +} +/*! + \brief This function is used to delete the MsgQ + + \param pMsgQ - pointer to the message queue + + \return - OsiReturnVal_e + \note + \warning +*/ +OsiReturnVal_e osi_MsgQDelete(OsiMsgQ_t* pMsgQ) +{ + return OSI_OK; +} +/*! + \brief This function is used to write data to the MsgQ + + \param pMsgQ - pointer to the message queue + \param pMsg - pointer to the Msg strut to read into + \param Timeout - timeout to wait for the Msg to be available + + \return - OsiReturnVal_e + \note + \warning +*/ + +OsiReturnVal_e osi_MsgQWrite(OsiMsgQ_t* pMsgQ, void* pMsg , OsiTime_t Timeout) +{ + + if(NULL == pMsgQ) + { + return OSI_INVALID_PARAMS; + } + + if(osMessagePut((osMessageQDef_t*)pMsgQ, pMsg, osWaitForever) == osOK) + { + return OSI_OK; + } + + return OSI_OPERATION_FAILED; +} +/*! + \brief This function is used to read data from the MsgQ + + \param pMsgQ - pointer to the message queue + \param pMsg - pointer to the Msg strut to read into + \param Timeout - timeout to wait for the Msg to be available + + \return - OsiReturnVal_e + \note + \warning +*/ + +OsiReturnVal_e osi_MsgQRead(OsiMsgQ_t* pMsgQ, void* pMsg , OsiTime_t Timeout) +{ + osEvent event; + + + if(NULL == pMsgQ) + { + return OSI_INVALID_PARAMS; + } + + event = osMessageGet((osMessageQDef_t*)pMsgQ, Timeout); + if(event.status == osEventMessage) + { + pMsg = event.value.p; + + return OSI_OK; + } + + return OSI_OPERATION_FAILED; +} + +/*! + \brief This function used to suspend the task for the specified number of milli secs + \param MilliSecs - Time in millisecs to suspend the task + \return - void + \note + \warning +*/ +void osi_Sleep(unsigned int MilliSecs) +{ + osDelay(MilliSecs); +} + +/*! + \brief This function used to disable the tasks + \param - void + \return - Key with the suspended tasks + \note + \warning +*/ +unsigned long osi_TaskDisable(void) +{ + return OSI_OK; +} + +/*! + \brief This function used to start the scheduler + \param void + \return - void + \note + \warning +*/ +void osi_start() +{ + osKernelStart(); +} + +/*! + \brief This function used to resume all the tasks + \param key - returned from suspend tasks + \return - void + \note + \warning +*/ +void osi_TaskEnable(unsigned long key) +{ + +} + +/*! + \brief This function used to save the OS context before sleep + \param void + \return - void + \note + \warning +*/ +void osi_ContextSave() +{ + +} +/*! + \brief This function used to restore the OS context after sleep + \param void + \return - void + \note + \warning +*/ +void osi_ContextRestore() +{ + +} diff --git a/targets/TI-RTOS/CC3200/target_common.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.c similarity index 97% rename from targets/TI-RTOS/CC3200/target_common.c rename to targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.c index bf152a89ed..f3374923e4 100644 --- a/targets/TI-RTOS/CC3200/target_common.c +++ b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.c @@ -3,7 +3,7 @@ // Portions Copyright (c) Microsoft Corporation. All rights reserved. // See LICENSE file in the project root for full license information. // - +#include #include #include "target_board.h" #include "target_common.h" diff --git a/targets/TI-RTOS/CC3200/target_common.h.in b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.h.in similarity index 100% rename from targets/TI-RTOS/CC3200/target_common.h.in rename to targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.h.in diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/asmdefs.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/asmdefs.h new file mode 100644 index 0000000000..c2a6f97342 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/asmdefs.h @@ -0,0 +1,229 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for code_red. +// +//***************************************************************************** +#ifdef codered + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // codered + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(gcc) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // rvmdk + +//***************************************************************************** +// +// The defines required for Sourcery G++. +// +//***************************************************************************** +#if defined(sourcerygxx) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // sourcerygxx + +#endif // __ASMDEF_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_adc.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_adc.h new file mode 100644 index 0000000000..525ce905c6 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_adc.h @@ -0,0 +1,888 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ADC_CTRL 0x00000000 // ADC control register. +#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting +#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting +#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting +#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting +#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting +#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting +#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting +#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting +#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable + // register +#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable + // register +#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable + // register +#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable + // register +#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable + // register +#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable + // register +#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable + // register +#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable + // register +#define ADC_O_adc_ch0_irq_status \ + 0x00000044 // Channel 0 interrupt status + // register + +#define ADC_O_adc_ch1_irq_status \ + 0x00000048 // Channel 1 interrupt status + // register + +#define ADC_O_adc_ch2_irq_status \ + 0x0000004C + +#define ADC_O_adc_ch3_irq_status \ + 0x00000050 // Channel 3 interrupt status + // register + +#define ADC_O_adc_ch4_irq_status \ + 0x00000054 // Channel 4 interrupt status + // register + +#define ADC_O_adc_ch5_irq_status \ + 0x00000058 + +#define ADC_O_adc_ch6_irq_status \ + 0x0000005C // Channel 6 interrupt status + // register + +#define ADC_O_adc_ch7_irq_status \ + 0x00000060 // Channel 7 interrupt status + // register + +#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register +#define ADC_O_adc_timer_configuration \ + 0x00000068 // ADC timer configuration register + +#define ADC_O_adc_timer_current_count \ + 0x00000070 // ADC timer current count register + +#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register +#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register +#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register +#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register +#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register +#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register +#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register +#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register +#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register +#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status + // register +#define ADC_O_adc_ch2_fifo_lvl 0x0000009C +#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status + // register +#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status + // register +#define ADC_O_adc_ch5_fifo_lvl 0x000000A8 +#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status + // register +#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status + // register + +#define ADC_O_ADC_CH_ENABLE 0x000000B8 + +//****************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ADC_CTRL register. +// +//****************************************************************************** +#define ADC_ADC_CTRL_adc_cap_scale \ + 0x00000020 // ADC CAP SCALE. + +#define ADC_ADC_CTRL_adc_buf_bypass \ + 0x00000010 // ADC ANA CIO buffer bypass. + // Signal is modelled in ANA TOP. + // When '1': ADC buffer is bypassed. + +#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1: + // ADC buffer is enabled. +#define ADC_ADC_CTRL_adc_core_en \ + 0x00000004 // ANA ADC core en. This signal act + // as glbal enable to ADC CIO. When + // 1: ADC core is enabled. + +#define ADC_ADC_CTRL_adc_soft_reset \ + 0x00000002 // ADC soft reset. When '1' : reset + // ADC internal logic. + +#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC + // module is enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_gain register. +// +//****************************************************************************** +#define ADC_adc_ch0_gain_adc_channel0_gain_M \ + 0x00000003 // gain setting for ADC channel 0. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch0_gain_adc_channel0_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_gain register. +// +//****************************************************************************** +#define ADC_adc_ch1_gain_adc_channel1_gain_M \ + 0x00000003 // gain setting for ADC channel 1. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch1_gain_adc_channel1_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_gain register. +// +//****************************************************************************** +#define ADC_adc_ch2_gain_adc_channel2_gain_M \ + 0x00000003 // gain setting for ADC channel 2. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch2_gain_adc_channel2_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_gain register. +// +//****************************************************************************** +#define ADC_adc_ch3_gain_adc_channel3_gain_M \ + 0x00000003 // gain setting for ADC channel 3. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch3_gain_adc_channel3_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_gain register. +// +//****************************************************************************** +#define ADC_adc_ch4_gain_adc_channel4_gain_M \ + 0x00000003 // gain setting for ADC channel 4 + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch4_gain_adc_channel4_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_gain register. +// +//****************************************************************************** +#define ADC_adc_ch5_gain_adc_channel5_gain_M \ + 0x00000003 // gain setting for ADC channel 5. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch5_gain_adc_channel5_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_gain register. +// +//****************************************************************************** +#define ADC_adc_ch6_gain_adc_channel6_gain_M \ + 0x00000003 // gain setting for ADC channel 6 + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch6_gain_adc_channel6_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_gain register. +// +//****************************************************************************** +#define ADC_adc_ch7_gain_adc_channel7_gain_M \ + 0x00000003 // gain setting for ADC channel 7. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch7_gain_adc_channel7_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_dma_mode_en register. +// +//****************************************************************************** +#define ADC_adc_dma_mode_en_DMA_MODEenable_M \ + 0x000000FF // this register enable DMA mode. + // when '1' respective ADC channel + // is enabled for DMA. When '0' only + // interrupt mode is enabled. Bit 0: + // channel 0 DMA mode enable. Bit 1: + // channel 1 DMA mode enable. Bit 2: + // channel 2 DMA mode enable. Bit 3: + // channel 3 DMA mode enable. bit 4: + // channel 4 DMA mode enable. bit 5: + // channel 5 DMA mode enable. bit 6: + // channel 6 DMA mode enable. bit 7: + // channel 7 DMA mode enable. + +#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_timer_configuration register. +// +//****************************************************************************** +#define ADC_adc_timer_configuration_timeren \ + 0x02000000 // when '1' timer is enabled. + +#define ADC_adc_timer_configuration_timerreset \ + 0x01000000 // when '1' reset timer. + +#define ADC_adc_timer_configuration_timercount_M \ + 0x00FFFFFF // Timer count configuration. 17 + // bit counter is supported. Other + // MSB's are redundent. + +#define ADC_adc_timer_configuration_timercount_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_timer_current_count register. +// +//****************************************************************************** +#define ADC_adc_timer_current_count_timercurrentcount_M \ + 0x0001FFFF // Timer count configuration + +#define ADC_adc_timer_current_count_timercurrentcount_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel0FIFODATA register. +// +//****************************************************************************** +#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel1FIFODATA register. +// +//****************************************************************************** +#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel2FIFODATA register. +// +//****************************************************************************** +#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel3FIFODATA register. +// +//****************************************************************************** +#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel4FIFODATA register. +// +//****************************************************************************** +#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel5FIFODATA register. +// +//****************************************************************************** +#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel6FIFODATA register. +// +//****************************************************************************** +#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel7FIFODATA register. +// +//****************************************************************************** +#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0 + + + +#endif // __HW_ADC_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_aes.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_aes.h new file mode 100644 index 0000000000..3ab0398b35 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_aes.h @@ -0,0 +1,802 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_AES_H__ +#define __HW_AES_H__ + +//***************************************************************************** +// +// The following are defines for the AES_P register offsets. +// +//***************************************************************************** +#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third + // key +#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit + // key) / CBC-MAC third key (MSW) +#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC + // third key (LSW) +#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit + // key) / CBC-MAC third key +#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key / + // Hash Key input +#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit + // key) + CCM/CBC-MAC second key + // (MSW) / Hash Key input (MSW) +#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key + // (LSW) / Hash Key input (LSW) +#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key / + // Hash Key input +#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key) +#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key) +#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key) +#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key) +#define AES_O_KEY1_2 0x00000030 // Key +#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key) +#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key) +#define AES_O_KEY1_1 0x0000003C // Key +#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input + // (LSW) +#define AES_O_IV_IN_1 0x00000044 // Initialization vector input +#define AES_O_IV_IN_2 0x00000048 // Initialization vector input +#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input + // (MSW) +#define AES_O_CTRL 0x00000050 // register determines the mode of + // operation of the AES Engine +#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers + // (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. +#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers + // (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. +#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The + // authentication length register + // store the authentication data + // length in bytes for combined + // modes only (GCM or CCM) Supported + // AAD-lengths for CCM are from 0 to + // (2^16 - 2^8) bytes. For GCM any + // value up to (2^32 - 1) bytes can + // be used. Once processing with + // this context is started@@ this + // length decrements to zero. A + // write to this register triggers + // the engine to start using this + // context for GCM and CCM. For XTS + // this register is optionally used + // to load ‘j’. Loading of ‘j’ is + // only required if ‘j’ != 0. ‘j’ is + // a 28-bit value and must be + // written to bits [31-4] of this + // register. ‘j’ represents the + // sequential number of the 128-bit + // block inside the data unit. For + // the first block in a unit@@ this + // value is zero. It is not required + // to provide a ‘j’ for each new + // data block within a unit. Note + // that it is possible to start with + // a ‘j’ unequal to zero; refer to + // Table 4 for more details. For a + // Host read operation@@ these + // registers return all-zeroes. +#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write + // plaintext/ciphertext (MSW) +#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write + // plaintext/ciphertext +#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write + // plaintext/ciphertext +#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write + // plaintext/ciphertext (LSW) +#define AES_O_TAG_OUT_0 0x00000070 +#define AES_O_TAG_OUT_1 0x00000074 +#define AES_O_TAG_OUT_2 0x00000078 +#define AES_O_TAG_OUT_3 0x0000007C +#define AES_O_REVISION 0x00000080 // Register AES_REVISION +#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This + // register configures the DMA + // signals and controls the IDLE and + // reset logic +#define AES_O_SYSSTATUS 0x00000088 +#define AES_O_IRQSTATUS 0x0000008C // This register indicates the + // interrupt status. If one of the + // interrupt bits is set the + // interrupt output will be asserted +#define AES_O_IRQENABLE 0x00000090 // This register contains an enable + // bit for each unique interrupt + // generated by the module. It + // matches the layout of + // AES_IRQSTATUS register. An + // interrupt is enabled when the bit + // in this register is set to ‘1’. + // An interrupt that is enabled is + // propagated to the SINTREQUEST_x + // output. All interrupts need to be + // enabled explicitly by writing + // this register. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_6 register. +// +//****************************************************************************** +#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_6_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_7 register. +// +//****************************************************************************** +#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_7_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_4 register. +// +//****************************************************************************** +#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_4_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_5 register. +// +//****************************************************************************** +#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_5_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_2 register. +// +//****************************************************************************** +#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_3 register. +// +//****************************************************************************** +#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_3_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_0 register. +// +//****************************************************************************** +#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_1 register. +// +//****************************************************************************** +#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_6 register. +// +//****************************************************************************** +#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_6_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_7 register. +// +//****************************************************************************** +#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_7_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_4 register. +// +//****************************************************************************** +#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_4_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_5 register. +// +//****************************************************************************** +#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_5_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_2 register. +// +//****************************************************************************** +#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_3 register. +// +//****************************************************************************** +#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_3_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_0 register. +// +//****************************************************************************** +#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_1 register. +// +//****************************************************************************** +#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_0 register. +// +//****************************************************************************** +#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_0_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_1 register. +// +//****************************************************************************** +#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_2 register. +// +//****************************************************************************** +#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_3 register. +// +//****************************************************************************** +#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_CTRL register. +// +//****************************************************************************** +#define AES_CTRL_CONTEXT_READY \ + 0x80000000 // If ‘1’@@ this read-only status + // bit indicates that the context + // data registers can be overwritten + // and the host is permitted to + // write the next context. + +#define AES_CTRL_SVCTXTRDY \ + 0x40000000 // If ‘1’@@ this read-only status + // bit indicates that an AES + // authentication TAG and/or IV + // block(s) is/are available for the + // host to retrieve. This bit is + // only asserted if the + // ‘save_context’ bit is set to ‘1’. + // The bit is mutual exclusive with + // the ‘context_ready’ bit. + +#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate + // that an authentication TAG or + // result IV needs to be stored as a + // result context. If this bit is + // set@@ context output DMA and/or + // interrupt will be asserted if the + // operation is finished and related + // signals are enabled. +#define AES_CTRL_CCM_M 0x01C00000 // Defines “M” that indicated the + // length of the authentication + // field for CCM operations; the + // authentication field length + // equals two times (the value of + // CCM-M plus one). Note that the + // AES Engine always returns a + // 128-bit authentication field@@ of + // which the M least significant + // bytes are valid. All values are + // supported. +#define AES_CTRL_CCM_S 22 +#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L” that indicated the + // width of the length field for CCM + // operations; the length field in + // bytes equals the value of CMM-L + // plus one. Supported values for L + // are (programmed value): 2 (1)@@ 4 + // (3) and 8 (7). +#define AES_CTRL_CCM_L_S 19 +#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a + // combined mode@@ using AES for + // both authentication and + // encryption. No additional mode + // selection is required. 0 Other + // mode selected 1 ccm mode selected +#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is + // a combined mode@@ using the + // Galois field multiplier GF(2^128) + // for authentication and AES-CTR + // mode for encryption@@ the bits + // specify the GCM mode. 0x0 No + // operation 0x1 GHASH with H loaded + // and Y0-encrypted forced to zero + // 0x2 GHASH with H loaded and + // Y0-encrypted calculated + // internally 0x3 Autonomous GHASH + // (both H and Y0-encrypted + // calculated internally) +#define AES_CTRL_GCM_S 16 +#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the + // Direction bit must be set to ‘1’ + // for this mode. 0 Other mode + // selected 1 cbcmac mode selected +#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the + // AES key size must be set to + // 128-bit for this mode. 0 Other + // mode selected 1 f9 selected +#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the + // AES key size must be set to + // 128-bit for this mode. 0 Other + // mode selected 1 f8 selected +#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected; + // the bits specify the XTS mode.01 + // = Previous/intermediate tweak + // value and ‘j’ loaded (value is + // loaded via IV@@ j is loaded via + // the AAD length register) 0x0 No + // operation 0x1 + // Previous/intermediate tweak value + // and ‘j’ loaded (value is loaded + // via IV@@ j is loaded via the AAD + // length register) 0x2 Key2@@ i and + // j loaded (i is loaded via IV@@ j + // is loaded via the AAD length + // register) 0x3 Key2 and i loaded@@ + // j=0 (i is loaded via IV) +#define AES_CTRL_XTS_S 11 +#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback + // mode (CFB128) is selected. 0 + // other mode selected 1 cfb + // selected +#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM) + // is selected@@ this is a counter + // mode with a 16-bit wide counter. + // 0 Other mode selected. 1 ICM mode + // selected +#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for + // AES-CTR mode 0x0 Counter is 32 + // bits 0x1 Counter is 64 bits 0x2 + // Counter is 128 bits 0x3 Counter + // is 192 bits +#define AES_CTRL_CTR_WIDTH_S 7 +#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for + // GCM and CCM@@ when + // encryption/decryption is + // required. 0 Other mode selected 1 + // Counter mode +#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc + // mode +#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is + // 128 bits. 0x2 Key is 192 bits 0x3 + // Key is 256 +#define AES_CTRL_KEY_SIZE_S 3 +#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt + // operation is performed. If set to + // ‘0’ a decrypt operation is + // performed. Read 0 decryption is + // selected Read 1 Encryption is + // selected +#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status + // bit indicates that the 16-byte + // input buffer is empty@@ and the + // host is permitted to write the + // next block of data. +#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status + // bit indicates that an AES output + // block is available for the host + // to retrieve. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_C_LENGTH_0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_C_LENGTH_1 register. +// +//****************************************************************************** +#define AES_C_LENGTH_1_LENGTH_M \ + 0x1FFFFFFF // Data length (MSW) length + // registers (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. + +#define AES_C_LENGTH_1_LENGTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_AUTH_LENGTH register. +// +//****************************************************************************** +#define AES_AUTH_LENGTH_AUTH_M \ + 0xFFFFFFFF // data + +#define AES_AUTH_LENGTH_AUTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_0 register. +// +//****************************************************************************** +#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_0_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_1 register. +// +//****************************************************************************** +#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_2 register. +// +//****************************************************************************** +#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_3 register. +// +//****************************************************************************** +#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register. +// +//****************************************************************************** +#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_0_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register. +// +//****************************************************************************** +#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_1_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register. +// +//****************************************************************************** +#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_2_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register. +// +//****************************************************************************** +#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW) +#define AES_TAG_OUT_3_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_REVISION register. +// +//****************************************************************************** +#define AES_REVISION_SCHEME_M 0xC0000000 +#define AES_REVISION_SCHEME_S 30 +#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define AES_REVISION_FUNC_S 16 +#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by + // IP design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define AES_REVISION_R_RTL_S 11 +#define AES_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X)@@ maintained + // by IP specification owner. X + // changes ONLY when: (1) There is a + // major feature addition. An + // example would be adding Master + // Mode to Utopia Level2. The Func + // field (or Class/Type in old PID + // format) will remain the same. X + // does NOT change due to: (1) Bug + // fixes (2) Change in feature + // parameters. + +#define AES_REVISION_X_MAJOR_S 8 +#define AES_REVISION_CUSTOM_M 0x000000C0 +#define AES_REVISION_CUSTOM_S 6 +#define AES_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y)@@ maintained + // by IP specification owner. Y + // changes ONLY when: (1) Features + // are scaled (up or down). + // Flexibility exists in that this + // feature scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R@@ S@@ X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless@@ the spec tracks + // the IP bugs. An RTL release (say + // for silicon PG1.1) that occurs + // due to bug fix should document + // the corresponding spec number + // (X.Y.S) in its release notes. + +#define AES_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSCONFIG register. +// +//****************************************************************************** +#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \ + 0x00000200 // If set to '1' the two context + // out requests + // (dma_req_context_out_en@@ Bit [8] + // above@@ and context_out interrupt + // enable@@ Bit [3] of AES_IRQENABLE + // register) are mapped on the + // corresponding data output request + // bit. In this case@@ the original + // ‘context out’ bit values are + // ignored. + +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ + 0x00000100 // If set to ‘1’@@ the DMA context + // output request is enabled (for + // context data out@@ e.g. TAG for + // authentication modes). 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // If set to ‘1’@@ the DMA context + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // If set to ‘1’@@ the DMA output + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // If set to ‘1’@@ the DMA input + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSSTATUS register. +// +//****************************************************************************** +#define AES_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQSTATUS register. +// +//****************************************************************************** +#define AES_IRQSTATUS_CONTEXT_OUT \ + 0x00000008 // This bit indicates + // authentication tag (and IV) + // interrupt(s) is/are active and + // triggers the interrupt output. + +#define AES_IRQSTATUS_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define AES_IRQSTATUS_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQENABLE register. +// +//****************************************************************************** +#define AES_IRQENABLE_CONTEXT_OUT \ + 0x00000008 // This bit indicates + // authentication tag (and IV) + // interrupt(s) is/are active and + // triggers the interrupt output. + +#define AES_IRQENABLE_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define AES_IRQENABLE_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + + + + +#endif // __HW_AES_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_config.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_config.h new file mode 100644 index 0000000000..b8789b9802 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_config.h @@ -0,0 +1,747 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + + +#ifndef __HW_APPS_CONFIG_H__ +#define __HW_APPS_CONFIG_H__ + +//***************************************************************************** +// +// The following are defines for the APPS_CONFIG register offsets. +// +//***************************************************************************** +#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \ + 0x00000000 // Patch trap address Register + // array + +#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \ + 0x00000078 + +#define APPS_CONFIG_O_FAULT_STATUS_REG \ + 0x0000007C + +#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \ + 0x00000080 + +#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \ + 0x00000084 + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK \ + 0x0000008C + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \ + 0x00000090 + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \ + 0x00000094 + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \ + 0x00000098 + +#define APPS_CONFIG_O_DMA_DONE_INT_ACK \ + 0x0000009C + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \ + 0x000000A0 + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \ + 0x000000A4 + +#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \ + 0x000000A8 + +#define APPS_CONFIG_O_RESERVD_REG_0 \ + 0x000000AC + +#define APPS_CONFIG_O_GPT_TRIG_SEL \ + 0x000000B0 + +#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \ + 0x000000B4 + +#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \ + 0x000000B8 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \ + 0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus + // fault is generated for the + // address + // PATCH_TRAP_ADDR_REG[n][31:0] from + // Idcode bus. The exception routine + // should take care to jump to the + // location where the patch + // correspond to this address is + // kept. + +#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_PATCH_TRAP_EN_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \ + 0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus + // fault is generated for the + // address PATCH_TRAP_ADD[n][31:0] + // from Idcode bus. The exception + // routine should take care to jump + // to the location where the patch + // correspond to this address is + // kept. + +#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_FAULT_STATUS_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \ + 0x0000003E // This field shows because of + // which patch trap address the + // bus_fault is generated. If the + // PATCH_ERR bit is set, then it + // means the bus fault is generated + // because of + // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX] + +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1 +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \ + 0x00000001 // This bit is set when there is a + // bus fault because of patched + // address access to the Apps boot + // rom. Write 0 to clear this + // register. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \ + 0x00000001 // This bit is set when there is a + // an error in memss write access. + // And the address causing this + // error is captured in + // MEMSS_ERR_ADDR_REG. To capture + // the next error address one have + // to clear this bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \ + 0x0000F000 // 1= disable corresponding + // interrupt;0 = interrupt enabled + // bit 14: ADC channel 7 interrupt + // enable/disable bit 13: ADC + // channel 5 interrupt + // enable/disable bit 12: ADC + // channel 3 interrupt + // enable/disable bit 11: ADC + // channel 1 interrupt + // enable/disable + +#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \ + 0x00000800 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \ + 0x00000400 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \ + 0x00000200 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \ + 0x00000100 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \ + 0x00000080 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \ + 0x00000040 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \ + 0x00000020 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \ + 0x00000010 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \ + 0x00000008 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \ + 0x00000004 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \ + 0x00000002 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \ + 0x00000001 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \ + 0x0000F000 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect bit 14: ADC channel 7 DMA + // Done IRQ bit 13: ADC channel 5 + // DMA Done IRQ bit 12: ADC channel + // 3 DMA Done IRQ bit 11: ADC + // channel 1 DMA Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \ + 0x00000800 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \ + 0x00000400 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \ + 0x00000200 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \ + 0x00000100 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000080 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000040 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000020 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000010 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000008 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000004 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \ + 0x00000002 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \ + 0x00000001 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \ + 0x0000F000 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect bit 14: ADC channel 7 DMA + // Done IRQ mask bit 13: ADC channel + // 5 DMA Done IRQ mask bit 12: ADC + // channel 3 DMA Done IRQ mask bit + // 11: ADC channel 1 DMA Done IRQ + // mask + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000800 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000400 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \ + 0x00000200 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \ + 0x00000100 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000080 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000040 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000020 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000010 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000008 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000004 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000002 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000001 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 or 0 to clear all + // DMA_DONE interrupt; + +#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_ACK register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \ + 0x0000F000 // write 1 to clear corresponding + // interrupt; 0 = no effect; bit 14: + // ADC channel 7 DMA Done IRQ bit + // 13: ADC channel 5 DMA Done IRQ + // bit 12: ADC channel 3 DMA Done + // IRQ bit 11: ADC channel 1 DMA + // Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12 +#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \ + 0x00000800 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \ + 0x00000400 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \ + 0x00000200 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \ + 0x00000100 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \ + 0x00000080 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \ + 0x00000040 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \ + 0x00000020 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \ + 0x00000010 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \ + 0x00000008 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \ + 0x00000004 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \ + 0x00000002 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \ + 0x00000001 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \ + 0x0000F000 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask bit 14: ADC + // channel 7 DMA Done IRQ bit 13: + // ADC channel 5 DMA Done IRQ bit + // 12: ADC channel 3 DMA Done IRQ + // bit 11: ADC channel 1 DMA Done + // IRQ + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12 +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000800 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000400 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \ + 0x00000200 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \ + 0x00000100 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000080 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000040 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000020 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000010 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000008 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000004 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000002 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000001 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \ + 0x0000F000 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive bit 14: ADC channel 7 + // DMA Done IRQ bit 13: ADC channel + // 5 DMA Done IRQ bit 12: ADC + // channel 3 DMA Done IRQ bit 11: + // ADC channel 1 DMA Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12 +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \ + 0x00000800 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \ + 0x00000400 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \ + 0x00000200 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \ + 0x00000100 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000080 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000040 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000020 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000010 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000008 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000004 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \ + 0x00000002 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \ + 0x00000001 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \ + 0x00000001 // Write 1 to clear the LSB of + // FAULT_STATUS_REG + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_RESERVD_REG_0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_GPT_TRIG_SEL register. +// +//****************************************************************************** +#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \ + 0x000000FF // This bit is implemented for GPT + // trigger mode select. GPT IP + // support 2 modes: RTC mode and + // external trigger. When this bit + // is set to logic '1': enable + // external trigger mode for APPS + // GPT CP0 and CP1 pin. bit 0: when + // set '1' enable external GPT + // trigger 0 on GPIO0 CP0 pin else + // RTC mode is selected. bit 1: when + // set '1' enable external GPT + // trigger 1 on GPIO0 CP1 pin else + // RTC mode is selected. bit 2: when + // set '1' enable external GPT + // trigger 2 on GPIO1 CP0 pin else + // RTC mode is selected. bit 3: when + // set '1' enable external GPT + // trigger 3 on GPIO1 CP1 pin else + // RTC mode is selected. bit 4: when + // set '1' enable external GPT + // trigger 4 on GPIO2 CP0 pin else + // RTC mode is selected. bit 5: when + // set '1' enable external GPT + // trigger 5 on GPIO2 CP1 pin else + // RTC mode is selected. bit 6: when + // set '1' enable external GPT + // trigger 6 on GPIO3 CP0 pin else + // RTC mode is selected. bit 7: when + // set '1' enable external GPT + // trigger 7 on GPIO3 CP1 pin else + // RTC mode is selected. + +#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \ + 0x00000007 // Capture data from d2d_spare pads + +#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \ + 0x00000007 // Send data to d2d_spare pads - + // eventually this will get + // registered in top die + +#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0 + + + +#endif // __HW_APPS_CONFIG_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_rcm.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_rcm.h new file mode 100644 index 0000000000..edb52d26be --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_rcm.h @@ -0,0 +1,1506 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_APPS_RCM_H__ +#define __HW_APPS_RCM_H__ + +//***************************************************************************** +// +// The following are defines for the APPS_RCM register offsets. +// +//***************************************************************************** +#define APPS_RCM_O_CAMERA_CLK_GEN \ + 0x00000000 + +#define APPS_RCM_O_CAMERA_CLK_GATING \ + 0x00000004 + +#define APPS_RCM_O_CAMERA_SOFT_RESET \ + 0x00000008 + +#define APPS_RCM_O_MCASP_CLK_GATING \ + 0x00000014 + +#define APPS_RCM_O_MCASP_SOFT_RESET \ + 0x00000018 + +#define APPS_RCM_O_MMCHS_CLK_GEN \ + 0x00000020 + +#define APPS_RCM_O_MMCHS_CLK_GATING \ + 0x00000024 + +#define APPS_RCM_O_MMCHS_SOFT_RESET \ + 0x00000028 + +#define APPS_RCM_O_MCSPI_A1_CLK_GEN \ + 0x0000002C + +#define APPS_RCM_O_MCSPI_A1_CLK_GATING \ + 0x00000030 + +#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \ + 0x00000034 + +#define APPS_RCM_O_MCSPI_A2_CLK_GEN \ + 0x00000038 + +#define APPS_RCM_O_MCSPI_A2_CLK_GATING \ + 0x00000040 + +#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \ + 0x00000044 + +#define APPS_RCM_O_UDMA_A_CLK_GATING \ + 0x00000048 + +#define APPS_RCM_O_UDMA_A_SOFT_RESET \ + 0x0000004C + +#define APPS_RCM_O_GPIO_A_CLK_GATING \ + 0x00000050 + +#define APPS_RCM_O_GPIO_A_SOFT_RESET \ + 0x00000054 + +#define APPS_RCM_O_GPIO_B_CLK_GATING \ + 0x00000058 + +#define APPS_RCM_O_GPIO_B_SOFT_RESET \ + 0x0000005C + +#define APPS_RCM_O_GPIO_C_CLK_GATING \ + 0x00000060 + +#define APPS_RCM_O_GPIO_C_SOFT_RESET \ + 0x00000064 + +#define APPS_RCM_O_GPIO_D_CLK_GATING \ + 0x00000068 + +#define APPS_RCM_O_GPIO_D_SOFT_RESET \ + 0x0000006C + +#define APPS_RCM_O_GPIO_E_CLK_GATING \ + 0x00000070 + +#define APPS_RCM_O_GPIO_E_SOFT_RESET \ + 0x00000074 + +#define APPS_RCM_O_WDOG_A_CLK_GATING \ + 0x00000078 + +#define APPS_RCM_O_WDOG_A_SOFT_RESET \ + 0x0000007C + +#define APPS_RCM_O_UART_A0_CLK_GATING \ + 0x00000080 + +#define APPS_RCM_O_UART_A0_SOFT_RESET \ + 0x00000084 + +#define APPS_RCM_O_UART_A1_CLK_GATING \ + 0x00000088 + +#define APPS_RCM_O_UART_A1_SOFT_RESET \ + 0x0000008C + +#define APPS_RCM_O_GPT_A0_CLK_GATING \ + 0x00000090 + +#define APPS_RCM_O_GPT_A0_SOFT_RESET \ + 0x00000094 + +#define APPS_RCM_O_GPT_A1_CLK_GATING \ + 0x00000098 + +#define APPS_RCM_O_GPT_A1_SOFT_RESET \ + 0x0000009C + +#define APPS_RCM_O_GPT_A2_CLK_GATING \ + 0x000000A0 + +#define APPS_RCM_O_GPT_A2_SOFT_RESET \ + 0x000000A4 + +#define APPS_RCM_O_GPT_A3_CLK_GATING \ + 0x000000A8 + +#define APPS_RCM_O_GPT_A3_SOFT_RESET \ + 0x000000AC + +#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \ + 0x000000B0 + +#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \ + 0x000000B4 + +#define APPS_RCM_O_CRYPTO_CLK_GATING \ + 0x000000B8 + +#define APPS_RCM_O_CRYPTO_SOFT_RESET \ + 0x000000BC + +#define APPS_RCM_O_MCSPI_S0_CLK_GATING \ + 0x000000C8 + +#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \ + 0x000000CC + +#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \ + 0x000000D0 + +#define APPS_RCM_O_I2C_CLK_GATING \ + 0x000000D8 + +#define APPS_RCM_O_I2C_SOFT_RESET \ + 0x000000DC + +#define APPS_RCM_O_APPS_LPDS_REQ \ + 0x000000E4 + +#define APPS_RCM_O_APPS_TURBO_REQ \ + 0x000000EC + +#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \ + 0x00000108 + +#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \ + 0x0000010C + +#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \ + 0x00000110 + +#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \ + 0x00000114 + +#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \ + 0x00000118 + +#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \ + 0x00000120 + +#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \ + 0x00000124 + + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of Camera func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \ + 0x000000F8 + +#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3 +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of Camera func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable camera clk during + // deep-sleep mode + +#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable camera clk during + // sleep mode ; 0- Disable camera + // clk during sleep mode + +#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable camera clk during run + // mode ; 0- Disable camera clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \ + 0x00000002 // 1 - Camera clocks/resets are + // enabled ; 0 - Camera + // clocks/resets are disabled + +#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for Camera-core + // ; 0 - De-assert reset for + // Camera-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCASP clk during + // deep-sleep mode + +#define APPS_RCM_MCASP_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCASP clk during sleep + // mode ; 0- Disable MCASP clk + // during sleep mode + +#define APPS_RCM_MCASP_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCASP clk during run + // mode ; 0- Disable MCASP clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \ + 0x00000002 // 1 - MCASP Clocks/resets are + // enabled ; 0 - MCASP Clocks/resets + // are disabled + +#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for MCASP-core + // ; 0 - De-assert reset for + // MCASP-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MMCHS func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \ + 0x000000F8 + +#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3 +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MMCHS func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MMCHS clk during + // deep-sleep mode + +#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MMCHS clk during sleep + // mode ; 0- Disable MMCHS clk + // during sleep mode + +#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MMCHS clk during run + // mode ; 0- Disable MMCHS clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \ + 0x00000002 // 1 - MMCHS Clocks/resets are + // enabled ; 0 - MMCHS Clocks/resets + // are disabled + +#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for MMCHS-core + // ; 0 - De-assert reset for + // MMCHS-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud clk + // for MCSPI_A1 ; 1 - PLL divclk is + // used as baud clk for MCSPI_A1. + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11 +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A1 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3 +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A1 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCSPI_A1 clk during + // deep-sleep mode + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCSPI_A1 clk during + // sleep mode ; 0- Disable MCSPI_A1 + // clk during sleep mode + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCSPI_A1 clk during + // run mode ; 0- Disable MCSPI_A1 + // clk during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are + // enabled ; 0 - MCSPI_A1 + // Clocks/Resets are disabled + +#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for + // MCSPI_A1-core ; 0 - De-assert + // reset for MCSPI_A1-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud-clk + // for MCSPI_A2 ; 1 - PLL divclk is + // used as baud-clk for MCSPI_A2 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11 +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A2 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3 +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A2 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCSPI_A2 clk during + // deep-sleep mode + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCSPI_A2 clk during + // sleep mode ; 0- Disable MCSPI_A2 + // clk during sleep mode + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCSPI_A2 clk during + // run mode ; 0- Disable MCSPI_A2 + // clk during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are + // enabled ; 0 - MCSPI_A2 + // Clocks/Resets are disabled + +#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for + // MCSPI_A2-core ; 0 - De-assert + // reset for MCSPI_A2-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UDMA_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UDMA_A clk during + // deep-sleep mode 0 - Disable + // UDMA_A clk during deep-sleep mode + // ; + +#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UDMA_A clk during + // sleep mode 0 - Disable UDMA_A clk + // during sleep mode ; + +#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UDMA_A clk during run + // mode 0 - Disable UDMA_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UDMA_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \ + 0x00000002 // 1 - UDMA_A Clocks/Resets are + // enabled ; 0 - UDMA_A + // Clocks/Resets are disabled + +#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for DMA_A ; 0 - + // De-assert reset for DMA_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_A clk during + // deep-sleep mode 0 - Disable + // GPIO_A clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_A clk during + // sleep mode 0 - Disable GPIO_A clk + // during sleep mode ; + +#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_A clk during run + // mode 0 - Disable GPIO_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_A Clocks/Resets are + // enabled ; 0 - GPIO_A + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_A ; 0 + // - De-assert reset for GPIO_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_B_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_B clk during + // deep-sleep mode 0 - Disable + // GPIO_B clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_B clk during + // sleep mode 0 - Disable GPIO_B clk + // during sleep mode ; + +#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_B clk during run + // mode 0 - Disable GPIO_B clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_B_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_B Clocks/Resets are + // enabled ; 0 - GPIO_B + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_B ; 0 + // - De-assert reset for GPIO_B + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_C_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_C clk during + // deep-sleep mode 0 - Disable + // GPIO_C clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_C clk during + // sleep mode 0 - Disable GPIO_C clk + // during sleep mode ; + +#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_C clk during run + // mode 0 - Disable GPIO_C clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_C_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_C Clocks/Resets are + // enabled ; 0 - GPIO_C + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_C ; 0 + // - De-assert reset for GPIO_C + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_D_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_D clk during + // deep-sleep mode 0 - Disable + // GPIO_D clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_D clk during + // sleep mode 0 - Disable GPIO_D clk + // during sleep mode ; + +#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_D clk during run + // mode 0 - Disable GPIO_D clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_D_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_D Clocks/Resets are + // enabled ; 0 - GPIO_D + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_D ; 0 + // - De-assert reset for GPIO_D + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_E_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_E clk during + // deep-sleep mode 0 - Disable + // GPIO_E clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_E clk during + // sleep mode 0 - Disable GPIO_E clk + // during sleep mode ; + +#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_E clk during run + // mode 0 - Disable GPIO_E clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_E_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_E Clocks/Resets are + // enabled ; 0 - GPIO_E + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_E ; 0 + // - De-assert reset for GPIO_E + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_WDOG_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \ + 0x03000000 // "00" - Sysclk ; "01" - REF_CLK + // (38.4 MHz) ; "10/11" - Slow_clk + +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable WDOG_A clk during + // deep-sleep mode 0 - Disable + // WDOG_A clk during deep-sleep mode + // ; + +#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable WDOG_A clk during + // sleep mode 0 - Disable WDOG_A clk + // during sleep mode ; + +#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable WDOG_A clk during run + // mode 0 - Disable WDOG_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_WDOG_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \ + 0x00000002 // 1 - WDOG_A Clocks/Resets are + // enabled ; 0 - WDOG_A + // Clocks/Resets are disabled + +#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for WDOG_A ; 0 + // - De-assert reset for WDOG_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UART_A0 clk during + // deep-sleep mode 0 - Disable + // UART_A0 clk during deep-sleep + // mode ; + +#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9 +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UART_A0 clk during + // sleep mode 0 - Disable UART_A0 + // clk during sleep mode ; + +#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1 +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UART_A0 clk during + // run mode 0 - Disable UART_A0 clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \ + 0x00000002 // 1 - UART_A0 Clocks/Resets are + // enabled ; 0 - UART_A0 + // Clocks/Resets are disabled + +#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for UART_A0 ; 0 + // - De-assert reset for UART_A0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UART_A1 clk during + // deep-sleep mode 0 - Disable + // UART_A1 clk during deep-sleep + // mode ; + +#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9 +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UART_A1 clk during + // sleep mode 0 - Disable UART_A1 + // clk during sleep mode ; + +#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1 +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UART_A1 clk during + // run mode 0 - Disable UART_A1 clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \ + 0x00000002 // 1 - UART_A1 Clocks/Resets are + // enabled ; 0 - UART_A1 + // Clocks/Resets are disabled + +#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // UART_A1 ; 0 - De-assert the soft + // reset for UART_A1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A0 clock + // during deep-sleep ; 0 - Disable + // the GPT_A0 clock during + // deep-sleep + +#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A0 clock + // during sleep ; 0 - Disable the + // GPT_A0 clock during sleep + +#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A0 clock + // during run ; 0 - Disable the + // GPT_A0 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A0 clocks/resets are + // enabled ; 0 - GPT_A0 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A0 ; 0 - De-assert the soft + // reset for GPT_A0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A1 clock + // during deep-sleep ; 0 - Disable + // the GPT_A1 clock during + // deep-sleep + +#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A1 clock + // during sleep ; 0 - Disable the + // GPT_A1 clock during sleep + +#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A1 clock + // during run ; 0 - Disable the + // GPT_A1 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A1 clocks/resets are + // enabled ; 0 - GPT_A1 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A1 ; 0 - De-assert the soft + // reset for GPT_A1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A2_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A2 clock + // during deep-sleep ; 0 - Disable + // the GPT_A2 clock during + // deep-sleep + +#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A2 clock + // during sleep ; 0 - Disable the + // GPT_A2 clock during sleep + +#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A2 clock + // during run ; 0 - Disable the + // GPT_A2 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A2_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A2 clocks/resets are + // enabled ; 0 - GPT_A2 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A2 ; 0 - De-assert the soft + // reset for GPT_A2 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A3_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A3 clock + // during deep-sleep ; 0 - Disable + // the GPT_A3 clock during + // deep-sleep + +#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A3 clock + // during sleep ; 0 - Disable the + // GPT_A3 clock during sleep + +#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A3 clock + // during run ; 0 - Disable the + // GPT_A3 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A3_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A3 Clocks/resets are + // enabled ; 0 - GPT_A3 + // Clocks/resets are disabled + +#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A3 ; 0 - De-assert the soft + // reset for GPT_A3 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \ + 0x03FF0000 + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16 +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \ + 0x0000FFFF + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \ + 0x00010000 // 1 - Assert the reset for MCASP + // Frac-clk div; 0 - Donot assert + // the reset for MCASP frac clk-div + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \ + 0x000003FF + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CRYPTO_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable the Crypto clock + // during deep-sleep + +#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9 +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the Crypto clock + // during sleep ; 0 - Disable the + // Crypto clock during sleep + +#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1 +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the Crypto clock + // during run ; 0 - Disable the + // Crypto clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CRYPTO_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \ + 0x00000002 // 1 - Crypto clocks/resets are + // enabled ; 0 - Crypto + // clocks/resets are disabled + +#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // Crypto ; 0 - De-assert the soft + // reset for Crypto + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable the MCSPI_S0 clock + // during deep-sleep + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9 +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the MCSPI_S0 clock + // during sleep ; 0 - Disable the + // MCSPI_S0 clock during sleep + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1 +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the MCSPI_S0 clock + // during run ; 0 - Disable the + // MCSPI_S0 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are + // enabled ; 0 - MCSPI_S0 + // Clocks/resets are disabled + +#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // MCSPI_S0 ; 0 - De-assert the soft + // reset for MCSPI_S0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud-clk + // for MCSPI_S0 ; 1 - PLL divclk is + // used as buad-clk for MCSPI_S0 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_S0 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_S0 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_I2C_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the I2C Clock during + // deep-sleep 0 - Disable the I2C + // clock during deep-sleep + +#define APPS_RCM_I2C_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_I2C_CLK_GATING_NU1_S 9 +#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the I2C clock during + // sleep ; 0 - Disable the I2C clock + // during sleep + +#define APPS_RCM_I2C_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_I2C_CLK_GATING_NU2_S 1 +#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the I2C clock during + // run ; 0 - Disable the I2C clock + // during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_I2C_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \ + 0x00000002 // 1 - I2C Clocks/Resets are + // enabled ; 0 - I2C clocks/resets + // are disabled + +#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // Shared-I2C ; 0 - De-assert the + // soft reset for Shared-I2C + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_LPDS_REQ register. +// +//****************************************************************************** +#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \ + 0x00000001 // 1 - Request for LPDS + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_TURBO_REQ register. +// +//****************************************************************************** +#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \ + 0x00000001 // 1 - Request for TURBO + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \ + 0x00000002 // 1 - Enable the NWP to wake APPS + // from deep-sleep ; 0 - Disable NWP + // to wake APPS from deep-sleep + +#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \ + 0x00000001 // 1 - Enable deep-sleep wake timer + // in APPS RCM for deep-sleep; 0 - + // Disable deep-sleep wake timer in + // APPS RCM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \ + 0xFFFF0000 // Configuration (in slow_clks) + // which says when to request for + // OPP during deep-sleep exit + +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16 +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \ + 0x0000FFFF // Configuration (in slow_clks) + // which says when to request for + // WAKE during deep-sleep exit + +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register. +// +//****************************************************************************** +#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \ + 0x00000002 // 1- Enable the sleep wakeup due + // to NWP request. 0- Disable the + // sleep wakeup due to NWP request + +#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \ + 0x00000001 // 1- Enable the sleep wakeup due + // to sleep-timer; 0-Disable the + // sleep wakeup due to sleep-timer + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \ + 0xFFFFFFFF // Configuration (number of + // sysclks-80MHz) for the Sleep + // wakeup timer + +#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register. +// +//****************************************************************************** +#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \ + 0x00000001 // When 1 => APPS generated a wake + // request to NWP (When NWP is in + // any of its low-power modes : + // SLP/DSLP/LPDS) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register. +// +//****************************************************************************** +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \ + 0x00000008 // 1 - Indicates that deep-sleep + // timer expiry had caused the + // wakeup from deep-sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \ + 0x00000004 // 1 - Indicates that sleep timer + // expiry had caused the wakeup from + // sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \ + 0x00000002 // 1 - Indicates that NWP had + // caused the wakeup from deep-sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \ + 0x00000001 // 1 - Indicates that NWP had + // caused the wakeup from Sleep + + + + +#endif // __HW_APPS_RCM_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_camera.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_camera.h new file mode 100644 index 0000000000..4461a28467 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_camera.h @@ -0,0 +1,519 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_CAMERA_H__ +#define __HW_CAMERA_H__ + +//***************************************************************************** +// +// The following are defines for the CAMERA register offsets. +// +//***************************************************************************** +#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP + // revision code ( Parallel Mode) +#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the + // various parameters of the OCP + // interface (CCP and Parallel Mode) +#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status + // information about the module + // excluding the interrupt status + // information (CCP and Parallel + // Mode) +#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups + // all the status of the module + // internal events that can generate + // an interrupt (CCP & Parallel + // Mode) +#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register + // allows to enable/disable the + // module internal sources of + // interrupt on an event-by-event + // basis (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the + // various parameters of the Camera + // Core block (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA + // interface of the Camera Core + // block (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value + // of the clock divisor used to + // generate the external clock + // (Parallel Mode) +#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to + // the FIFO and read from the FIFO + // (CCP & Parallel Mode) +#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status + // of some important variables of + // the camera core module (CCP & + // Parallel Mode) +#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values + // of the generic parameters of the + // module + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_REVISION register. +// +//****************************************************************************** +#define CAMERA_CC_REVISION_REV_M \ + 0x000000FF // IP revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 + +#define CAMERA_CC_REVISION_REV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_SYSCONFIG register. +// +//****************************************************************************** +#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \ + 0x00000018 // Slave interface power management + // req/ack control """00"" + // Force-idle. An idle request is + // acknoledged unconditionally" + // """01"" No-idle. An idle request + // is never acknowledged" """10"" + // reserved (Smart-idle not + // implemented)" + +#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3 +#define CAMERA_CC_SYSCONFIG_SOFT_RESET \ + 0x00000002 // Software reset. Set this bit to + // 1 to trigger a module reset. The + // bit is automatically reset by the + // hardware. During reset it always + // returns 0. 0 Normal mode 1 The + // module is reset + +#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \ + 0x00000001 // Internal OCP clock gating + // strategy 0 OCP clock is + // free-running 1 Automatic OCP + // clock gating strategy is applied + // based on the OCP interface + // activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_SYSSTATUS register. +// +//****************************************************************************** +#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \ + 0x00000001 // Internal Reset Monitoring 0 + // Internal module reset is on-going + // 1 Reset completed + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_IRQSTATUS register. +// +//****************************************************************************** +#define CAMERA_CC_IRQSTATUS_FS_IRQ \ + 0x00080000 // Frame Start has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_LE_IRQ \ + 0x00040000 // Line End has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_LS_IRQ \ + 0x00020000 // Line Start has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FE_IRQ \ + 0x00010000 // Frame End has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \ + 0x00000800 // FSP code error 0 Event false "1 + // Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \ + 0x00000400 // Frame Height Error 0 Event false + // "1 Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \ + 0x00000200 // False Synchronization Code 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \ + 0x00000100 // Shifted Synchronization Code 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \ + 0x00000010 // FIFO is not empty 0 Event false + // "1 Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \ + 0x00000008 // FIFO is full 0 Event false "1 + // Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \ + 0x00000004 // FIFO threshold has been reached + // 0 Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \ + 0x00000002 // FIFO overflow has occurred 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \ + 0x00000001 // FIFO underflow has occurred 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_IRQENABLE register. +// +//****************************************************************************** +#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \ + 0x00080000 // Frame Start Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \ + 0x00040000 // Line End Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \ + 0x00020000 // Line Start Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \ + 0x00010000 // Frame End Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \ + 0x00000800 // FSP code Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \ + 0x00000400 // Frame Height Error Interrupt + // Enable 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \ + 0x00000200 // False Synchronization Code + // Interrupt Enable 0 Event is + // masked 1 Event generates an + // interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \ + 0x00000100 // False Synchronization Code + // Interrupt Enable 0 Event is + // masked 1 Event generates an + // interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \ + 0x00000010 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \ + 0x00000008 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \ + 0x00000004 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \ + 0x00000002 // FIFO Overflow Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \ + 0x00000001 // FIFO Underflow Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +//****************************************************************************** +// +// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \ + 0x00080000 // Synchronize all camera sensor + // inputs This must be set during + // the configuration phase before + // CC_EN set to '1'. This can be + // used in very high frequency to + // avoid dependancy to the IO + // timings. 0 No synchro (most of + // applications) 1 Synchro enabled + // (should never be required) + +#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite + // states machines of the camera + // core module - by writing a 1 to + // this bit. must be applied when + // CC_EN = 0 Reads returns 0 +#define CAMERA_CC_CTRL_CC_FRAME_TRIG \ + 0x00020000 // Set the modality in which CC_EN + // works when a disabling of the + // sensor camera core is wanted "If + // CC_FRAME_TRIG = 1 by writing + // ""0"" to CC_EN" the module is + // disabled at the end of the frame + // "If CC_FRAME_TRIG = 0 by writing + // ""0"" to CC_EN" the module is + // disabled immediately + +#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of + // the camera core module "By + // writing ""1"" to this field the + // module is enabled." "By writing + // ""0"" to this field the module is + // disabled at" the end of the frame + // if CC_FRAM_TRIG =1 and is + // disabled immediately if + // CC_FRAM_TRIG = 0 +#define CAMERA_CC_CTRL_NOBT_SYNCHRO \ + 0x00002000 // Enables to start at the + // beginning of the frame or not in + // NoBT 0 Acquisition starts when + // Vertical synchro is high 1 + // Acquisition starts when Vertical + // synchro goes from low to high + // (beginning of the frame) - + // Recommended. + +#define CAMERA_CC_CTRL_BT_CORRECT \ + 0x00001000 // Enables the correction within + // the sync codes in BT mode 0 + // correction is not enabled 1 + // correction is enabled + +#define CAMERA_CC_CTRL_PAR_ORDERCAM \ + 0x00000800 // Enables swap between image-data + // in parallel mode 0 swap is not + // enabled 1 swap is enabled + +#define CAMERA_CC_CTRL_PAR_CLK_POL \ + 0x00000400 // Inverts the clock coming from + // the sensor in parallel mode 0 + // clock not inverted - data sampled + // on rising edge 1 clock inverted - + // data sampled on falling edge + +#define CAMERA_CC_CTRL_NOBT_HS_POL \ + 0x00000200 // Sets the polarity of the + // synchronization signals in NOBT + // parallel mode 0 CAM_P_HS is + // active high 1 CAM_P_HS is active + // low + +#define CAMERA_CC_CTRL_NOBT_VS_POL \ + 0x00000100 // Sets the polarity of the + // synchronization signals in NOBT + // parallel mode 0 CAM_P_VS is + // active high 1 CAM_P_VS is active + // low + +#define CAMERA_CC_CTRL_PAR_MODE_M \ + 0x0000000E // Sets the Protocol Mode of the + // Camera Core module in parallel + // mode (when CCP_MODE = 0) """000"" + // Parallel NOBT 8-bit" """001"" + // Parallel NOBT 10-bit" """010"" + // Parallel NOBT 12-bit" """011"" + // reserved" """100"" Parallet BT + // 8-bit" """101"" Parallel BT + // 10-bit" """110"" reserved" + // """111"" FIFO test mode. Refer to + // Table 12 - FIFO Write and Read + // access" + +#define CAMERA_CC_CTRL_PAR_MODE_S 1 +#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode + // 0 CCP mode disabled 1 CCP mode + // enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_CTRL_DMA register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_DMA_DMA_EN \ + 0x00000100 // Sets the number of dma request + // lines 0 DMA interface disabled + // The DMA request line stays + // inactive 1 DMA interface enabled + // The DMA request line is + // operational + +#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \ + 0x0000007F // Sets the threshold of the FIFO + // the assertion of the dmarequest + // line takes place when the + // threshold is reached. + // """0000000"" threshold set to 1" + // """0000001"" threshold set to 2" + // … """1111111"" threshold set to + // 128" + +#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_CTRL_XCLK register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \ + 0x0000001F // Sets the clock divisor value for + // CAM_XCLK generation. based on + // CAM_MCK (value of CAM_MCLK is + // 96MHz) """00000"" CAM_XCLK Stable + // Low Level" Divider not enabled + // """00001"" CAM_XCLK Stable High + // Level" Divider not enabled from 2 + // to 30 CAM_XCLK = CAM_MCLK / + // XCLK_DIV """11111"" Bypass - + // CAM_XCLK = CAM_MCLK" + +#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_FIFO_DATA register. +// +//****************************************************************************** +#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \ + 0xFFFFFFFF // Writes the 32-bit word into the + // FIFO Reads the 32-bit word from + // the FIFO + +#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the CAMERA_O_CC_TEST register. +// +//****************************************************************************** +#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \ + 0xFF000000 // FIFO READ Pointer This field + // shows the value of the FIFO read + // pointer Expected value ranges + // from 0 to 127 + +#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24 +#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \ + 0x00FF0000 // FIFO WRITE pointer This field + // shows the value of the FIFO write + // pointer Expected value ranges + // from 0 to 127 + +#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16 +#define CAMERA_CC_TEST_FIFO_LEVEL_M \ + 0x0000FF00 // FIFO level (how many 32-bit + // words the FIFO contains) This + // field shows the value of the FIFO + // level and can assume values from + // 0 to 128 + +#define CAMERA_CC_TEST_FIFO_LEVEL_S 8 +#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \ + 0x000000FF // FIFO level peak This field shows + // the max value of the FIFO level + // and can assume values from 0 to + // 128 + +#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_GEN_PAR register. +// +//****************************************************************************** +#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \ + 0x00000007 // Camera Core FIFO DEPTH generic + // parameter + +#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0 + + + +#endif // __HW_CAMERA_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_common_reg.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_common_reg.h new file mode 100644 index 0000000000..417544ad48 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_common_reg.h @@ -0,0 +1,1117 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_COMMON_REG_H__ +#define __HW_COMMON_REG_H__ + +//***************************************************************************** +// +// The following are defines for the COMMON_REG register offsets. +// +//***************************************************************************** +#define COMMON_REG_O_I2C_Properties_Register \ + 0x00000000 + +#define COMMON_REG_O_SPI_Properties_Register \ + 0x00000004 + +#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \ + 0x0000000C + +#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \ + 0x00000010 + +#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \ + 0x00000014 + +#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \ + 0x00000018 + +#define COMMON_REG_O_Flash_ctrl_reg \ + 0x0000001C + +#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \ + 0x00000024 + +#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \ + 0x00000028 + +#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \ + 0x0000002C + +#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \ + 0x00000030 + +#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \ + 0x00000034 + +#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \ + 0x00000038 + +#define COMMON_REG_O_GPIO_properties_register \ + 0x0000003C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \ + 0x00000040 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \ + 0x00000044 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \ + 0x00000048 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \ + 0x0000004C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \ + 0x00000050 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \ + 0x00000054 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \ + 0x00000058 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \ + 0x0000005C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \ + 0x00000060 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \ + 0x00000064 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \ + 0x00000068 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \ + 0x0000006C + +#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \ + 0x00000070 + +#define COMMON_REG_O_NW_SEMAPPHORE_PEND \ + 0x00000074 + +#define COMMON_REG_O_SEMAPHORE_STATUS \ + 0x00000078 + +#define COMMON_REG_O_IDMEM_TIM_Update \ + 0x0000007C + +#define COMMON_REG_O_FPGA_ROM_WR_EN \ + 0x00000080 + +#define COMMON_REG_O_NW_INT_MASK \ + 0x00000084 + +#define COMMON_REG_O_NW_INT_MASK_SET \ + 0x00000088 + +#define COMMON_REG_O_NW_INT_MASK_CLR \ + 0x0000008C + +#define COMMON_REG_O_NW_INT_STS_CLR \ + 0x00000090 + +#define COMMON_REG_O_NW_INT_ACK 0x00000094 +#define COMMON_REG_O_NW_INT_TRIG \ + 0x00000098 + +#define COMMON_REG_O_NW_INT_STS_MASKED \ + 0x0000009C + +#define COMMON_REG_O_NW_INT_STS_RAW \ + 0x000000A0 + +#define COMMON_REG_O_APPS_INT_MASK \ + 0x000000A4 + +#define COMMON_REG_O_APPS_INT_MASK_SET \ + 0x000000A8 + +#define COMMON_REG_O_APPS_INT_MASK_CLR \ + 0x000000AC + +#define COMMON_REG_O_APPS_INT_STS_CLR \ + 0x000000B0 + +#define COMMON_REG_O_APPS_INT_ACK \ + 0x000000B4 + +#define COMMON_REG_O_APPS_INT_TRIG \ + 0x000000B8 + +#define COMMON_REG_O_APPS_INT_STS_MASKED \ + 0x000000BC + +#define COMMON_REG_O_APPS_INT_STS_RAW \ + 0x000000C0 + +#define COMMON_REG_O_IDMEM_TIM_Updated \ + 0x000000C4 + +#define COMMON_REG_O_APPS_GPIO_TRIG_EN \ + 0x000000C8 + +#define COMMON_REG_O_EMU_DEBUG_REG \ + 0x000000CC + +#define COMMON_REG_O_SEMAPHORE_STATUS2 \ + 0x000000D0 + +#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \ + 0x000000D4 + +#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \ + 0x000000D8 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_I2C_Properties_Register register. +// +//****************************************************************************** +#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SPI_Properties_Register register. +// +//****************************************************************************** +#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register. +// +//****************************************************************************** +#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \ + 0x0000000F // Interrupt enable APPS bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_sh_resource_Interrupt_status register. +// +//****************************************************************************** +#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \ + 0x0000000F // Interrupt enable APPS bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register. +// +//****************************************************************************** +#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \ + 0x0000000F // Interrupt enable NWP bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NWP_sh_resource_Interrupt_status register. +// +//****************************************************************************** +#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \ + 0x0000000F // Interrupt enable NWP bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Flash_ctrl_reg register. +// +//****************************************************************************** +#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M0_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \ + 0x0003FFFF // Master 0 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M1_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \ + 0x0003FFFF // Master 1 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M2_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \ + 0x0003FFFF // Master 2 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M3_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \ + 0x0003FFFF // Master 3 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M4_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \ + 0x0003FFFF // Master 4 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M5_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \ + 0x0003FFFF // Master 5 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_GPIO_properties_register register. +// +//****************************************************************************** +#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \ + 0x000003FF // Shared GPIO configuration + // register. Bit [1:0] to configure + // GPIO0 Bit [3:2] to configure + // GPIO1 Bit [5:4] to configure + // GPIO2 Bit [7:6] to configure + // GPIO3 Bit [9:8] to configure + // GPIO4 each GPIO can be + // individully selected. When “00” + // GPIO is free resource. When “01” + // GPIO is APPS resource. When “10” + // GPIO is NWP resource. Writing 11 + // doesnt have any affect, i.e. If + // one write only relevant gpio + // semaphore and other bits are 1s, + // it'll not disturb the other + // semaphore bits. For example : Say + // If NW wants to take control of + // gpio-1, one should write + // 10'b11_1111_1011 and if one wants + // to release it write + // 10'b11_1111_0011. + +#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE1 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE2 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE3 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE4 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE5 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE6 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE7 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE8 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE9 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE10 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE11 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE12 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \ + 0xFFFFFFFF // APPS NW semaphore register - not + // reflected in status. + +#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_SEMAPPHORE_PEND register. +// +//****************************************************************************** +#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \ + 0xFFFFFFFF // APPS SEMAPOHORE STATUS + +#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_SEMAPPHORE_PEND register. +// +//****************************************************************************** +#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \ + 0xFFFFFFFF // NW SEMAPHORE STATUS + +#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_STATUS register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \ + 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore + // status of flash_control 7:6 + // :semaphore status of + // gpio_properties 5:4 + // :semaphore status of + // spi_propertie 1:0 :semaphore + // status of i2c_propertie + +#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_IDMEM_TIM_Update register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_FPGA_ROM_WR_EN register. +// +//****************************************************************************** +#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \ + 0x00000001 // when '1' enables Write into + // IDMEM CORE ROM, APPS ROM, NWP ROM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \ + 0xFFFFFFFF // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK_SET register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \ + 0xFFFFFFFF // write 1 to set corresponding bit + // in NW_INT_MASK;0 = no effect + +#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK_CLR register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // bit in NW_INT_MASK;0 = no effect + +#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_CLR register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt; 0 = no effect; + // interrupt is not lost if coincide + // with write operation + +#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_ACK register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt;0 = no effect + +#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_TRIG register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \ + 0xFFFFFFFF // Writing a 1 to a bit in this + // register causes the the Host CPU + // if enabled (not masked). This + // register is self-clearing. + // Writing 0 has no effect + +#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_MASKED register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by NW_INT mask + +#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_RAW register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \ + 0xFFFFFFFF // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK_SET register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \ + 0xFFFFFFFF // write 1 to set corresponding bit + // in APPS_INT_MASK;0 = no effect + +#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK_CLR register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // bit in APPS_INT_MASK;0 = no + // effect + +#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_CLR register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt; 0 = no effect; + // interrupt is not lost if coincide + // with write operation + +#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_ACK register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt;0 = no effect + +#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_TRIG register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \ + 0xFFFFFFFF // Writing a 1 to a bit in this + // register causes the the Host CPU + // if enabled (not masked). This + // register is self-clearing. + // Writing 0 has no effect + +#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_MASKED register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by APPS_INT mask + +#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_RAW register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_IDMEM_TIM_Updated register. +// +//****************************************************************************** +#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \ + 0x00000001 // toggle in this signal + // indicatesIDMEM_TIM_UPDATE + // register mentioned above is + // updated. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_GPIO_TRIG_EN register. +// +//****************************************************************************** +#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \ + 0x0000001F // APPS GPIO Trigger EN control. + // Bit 0: when '1' enable GPIO 0 + // trigger. This bit enables trigger + // for all GPIO 0 pins (GPIO 0 to + // GPIO7). Bit 1: when '1' enable + // GPIO 1 trigger. This bit enables + // trigger for all GPIO 1 pins ( + // GPIO8 to GPIO15). Bit 2: when '1' + // enable GPIO 2 trigger. This bit + // enables trigger for all GPIO 2 + // pins (GPIO16 to GPIO23). Bit 3: + // when '1' enable GPIO 3 trigger. + // This bit enables trigger for all + // GPIO 3 pins (GPIO24 to GPIO31). + // Bit 4: when '1' enable GPIO 4 + // trigger. This bit enables trigger + // for all GPIO 4 pins.(GPIO32 to + // GPIO39) + +#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_EMU_DEBUG_REG register. +// +//****************************************************************************** +#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \ + 0xFFFFFFFF // 0 th bit used for stalling APPS + // DMA and 1st bit is used for + // stalling NWP DMA for debug + // purpose. Other bits are unused. + +#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_STATUS2 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \ + 0x00FFFFFF // SEMAPHORE STATUS 23:22 + // :semaphore status of + // apps_nw_semaphore11 21:20 + // :semaphore status of + // apps_nw_semaphore11 19:18 + // :semaphore status of + // apps_nw_semaphore10 17:16 + // :semaphore status of + // apps_nw_semaphore9 15:14 + // :semaphore status of + // apps_nw_semaphore8 13:12 + // :semaphore status of + // apps_nw_semaphore7 11:10 + // :semaphore status of + // apps_nw_semaphore6 9:8 :semaphore + // status of apps_nw_semaphore5 7:6 + // :semaphore status of + // apps_nw_semaphore4 5:4 :semaphore + // status of apps_nw_semaphore3 3:2 + // :semaphore status of + // apps_nw_semaphore2 1:0 :semaphore + // status of apps_nw_semaphore1 + +#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \ + 0x0003FFFF // 1:0 : prvious owner of + // i2c_properties_reg[1:0] 3:2 : + // prvious owner of + // spi_properties_reg[1:0] 5:4 : + // prvious owner of + // gpio_properties_reg[1:0] 9:8 : + // prvious owner of + // gpio_properties_reg[3:2] 11:10 : + // prvious owner of + // gpio_properties_reg[5:4] 13:12 : + // prvious owner of + // gpio_properties_reg[7:6] 15:14 : + // prvious owner of + // gpio_properties_reg[9:8] 17:16 : + // prvious owner of + // flash_control_reg[1:0] + +#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \ + 0x00FFFFFF // 1:0 : previous owner of + // apps_nw_semaphore1_reg[1:0] 3:2 : + // previous owner of + // apps_nw_semaphore2_reg[1:0] 5:4 : + // previous owner of + // apps_nw_semaphore3_reg[1:0] 7:6 : + // previous owner of + // apps_nw_semaphore4_reg[1:0] 9:8 : + // previous owner of + // apps_nw_semaphore5_reg[1:0] 11:10 + // : previous owner of + // apps_nw_semaphore6_reg[1:0] 13:12 + // : previous owner of + // apps_nw_semaphore7_reg[1:0] 15:14 + // : previous owner of + // apps_nw_semaphore8_reg[1:0] 17:16 + // : previous owner of + // apps_nw_semaphore9_reg[1:0] 19:18 + // : previous owner of + // apps_nw_semaphore10_reg[1:0] + // 21:20 : previous owner of + // apps_nw_semaphore11_reg[1:0] + // 23:22 : previous owner of + // apps_nw_semaphore12_reg[1:0] + +#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0 + + + +#endif // __HW_COMMON_REG_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_des.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_des.h new file mode 100644 index 0000000000..c3aed65627 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_des.h @@ -0,0 +1,339 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_DES_H__ +#define __HW_DES_H__ + +//***************************************************************************** +// +// The following are defines for the DES_P register offsets. +// +//***************************************************************************** +#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key +#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key +#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key +#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key +#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit + // key/192-bit key +#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit + // key/192-bit key +#define DES_O_IV_L 0x00000018 // Initialization vector LSW +#define DES_O_IV_H 0x0000001C // Initialization vector MSW +#define DES_O_CTRL 0x00000020 +#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data + // length in bytes for all modes. + // Once processing is started with + // this context this length + // decrements to zero. Data lengths + // up to (2^32 – 1) bytes are + // allowed. A write to this register + // triggers the engine to start + // using this context. For a Host + // read operation these registers + // return all-zeroes. +#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write + // encrypted/decrypted data. +#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write + // encrypted/decrypted data. +#define DES_O_REVISION 0x00000030 +#define DES_O_SYSCONFIG 0x00000034 +#define DES_O_SYSSTATUS 0x00000038 +#define DES_O_IRQSTATUS 0x0000003C // This register indicates the + // interrupt status. If one of the + // interrupt bits is set the + // interrupt output will be asserted +#define DES_O_IRQENABLE 0x00000040 // This register contains an enable + // bit for each unique interrupt + // generated by the module. It + // matches the layout of + // DES_IRQSTATUS register. An + // interrupt is enabled when the bit + // in this register is set to 1 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_L register. +// +//****************************************************************************** +#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3 +#define DES_KEY3_L_KEY3_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_H register. +// +//****************************************************************************** +#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3 +#define DES_KEY3_H_KEY3_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_L register. +// +//****************************************************************************** +#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2 +#define DES_KEY2_L_KEY2_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_H register. +// +//****************************************************************************** +#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2 +#define DES_KEY2_H_KEY2_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_L register. +// +//****************************************************************************** +#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1 +#define DES_KEY1_L_KEY1_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_H register. +// +//****************************************************************************** +#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1 +#define DES_KEY1_H_KEY1_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_L register. +// +//****************************************************************************** +#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC + // CFB modes +#define DES_IV_L_IV_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_H register. +// +//****************************************************************************** +#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC + // CFB modes +#define DES_IV_H_IV_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_CTRL register. +// +//****************************************************************************** +#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit + // indicates that the context data + // registers can be overwritten and + // the host is permitted to write + // the next context. +#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0 + // ecb mode 0x1 cbc mode 0x2 cfb + // mode 0x3 reserved +#define DES_CTRL_MODE_S 4 +#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES + // encryption/decryption. 0 des mode + // 1 tdes mode +#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0 + // decryption is selected 1 + // Encryption is selected +#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to + // encrypt/decrypt data +#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data + // decrypted/encrypted ready +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_LENGTH register. +// +//****************************************************************************** +#define DES_LENGTH_LENGTH_M 0xFFFFFFFF +#define DES_LENGTH_LENGTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_L register. +// +//****************************************************************************** +#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption +#define DES_DATA_L_DATA_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_H register. +// +//****************************************************************************** +#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption +#define DES_DATA_H_DATA_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_REVISION register. +// +//****************************************************************************** +#define DES_REVISION_SCHEME_M 0xC0000000 +#define DES_REVISION_SCHEME_S 30 +#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define DES_REVISION_FUNC_S 16 +#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define DES_REVISION_R_RTL_S 11 +#define DES_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. + +#define DES_REVISION_X_MAJOR_S 8 +#define DES_REVISION_CUSTOM_M 0x000000C0 +#define DES_REVISION_CUSTOM_S 6 +#define DES_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. + +#define DES_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSCONFIG register. +// +//****************************************************************************** +#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // If set to ‘1’ the DMA context + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // If set to ‘1’ the DMA output + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // If set to ‘1’ the DMA input + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSSTATUS register. +// +//****************************************************************************** +#define DES_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQSTATUS register. +// +//****************************************************************************** +#define DES_IRQSTATUS_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define DES_IRQSTATUS_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQENABLE register. +// +//****************************************************************************** +#define DES_IRQENABLE_M_DATA_OUT \ + 0x00000004 // If this bit is set to ‘1’ the + // secure data output interrupt is + // enabled. + +#define DES_IRQENABLE_M_DATA_IN \ + 0x00000002 // If this bit is set to ‘1’ the + // secure data input interrupt is + // enabled. + +#define DES_IRQENABLE_M_CONTEX_IN \ + 0x00000001 // If this bit is set to ‘1’ the + // secure context interrupt is + // enabled. + + + + +#endif // __HW_DES_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_dthe.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_dthe.h new file mode 100644 index 0000000000..1d302f426b --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_dthe.h @@ -0,0 +1,392 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +//***************************************************************************** + +#ifndef __HW_DTHE_H__ +#define __HW_DTHE_H__ + +//***************************************************************************** +// +// The following are defines for the DTHE register offsets. +// +//***************************************************************************** +#define DTHE_O_SHA_IM 0x00000810 +#define DTHE_O_SHA_RIS 0x00000814 +#define DTHE_O_SHA_MIS 0x00000818 +#define DTHE_O_SHA_IC 0x0000081C +#define DTHE_O_AES_IM 0x00000820 +#define DTHE_O_AES_RIS 0x00000824 +#define DTHE_O_AES_MIS 0x00000828 +#define DTHE_O_AES_IC 0x0000082C +#define DTHE_O_DES_IM 0x00000830 +#define DTHE_O_DES_RIS 0x00000834 +#define DTHE_O_DES_MIS 0x00000838 +#define DTHE_O_DES_IC 0x0000083C +#define DTHE_O_EIP_CGCFG 0x00000A00 +#define DTHE_O_EIP_CGREQ 0x00000A04 +#define DTHE_O_CRC_CTRL 0x00000C00 +#define DTHE_O_CRC_SEED 0x00000C10 +#define DTHE_O_CRC_DIN 0x00000C14 +#define DTHE_O_CRC_RSLT_PP 0x00000C18 +#define DTHE_O_RAND_KEY0 0x00000F00 +#define DTHE_O_RAND_KEY1 0x00000F04 +#define DTHE_O_RAND_KEY2 0x00000F08 +#define DTHE_O_RAND_KEY3 0x00000F0C + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IMST register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is + // raised when DMA complets the + // output context movement from + // internal register +#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IRIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done +#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IMIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done +#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_ICIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done” + // flag +#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done” flag +#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done” flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IMST register. +// +//****************************************************************************** +#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is + // raised when DMA finishes writing + // last word of the process result +#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is + // raised when DMA complets the + // output context movement from + // internal register +#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IRIS register. +// +//****************************************************************************** +#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done +#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IMIS register. +// +//****************************************************************************** +#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done +#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_ICIS register. +// +//****************************************************************************** +#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement + // done” flag +#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done” + // flag +#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done” flag +#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done” flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IMST register. +// +//****************************************************************************** +#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is + // raised when DMA finishes writing + // last word of the process result +#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IRIS register. +// +//****************************************************************************** +#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IMIS register. +// +//****************************************************************************** +#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_ICIS register. +// +//****************************************************************************** +#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement + // done” flag +#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done” + // flag +#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done” flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_EIP_CGCFG register. +// +//****************************************************************************** +#define DTHE_EIP_CGCFG_EIP29_CFG \ + 0x00000010 // Clock gating protocol setting + // for EIP29T. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP75_CFG \ + 0x00000008 // Clock gating protocol setting + // for EIP75T. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP16_CFG \ + 0x00000004 // Clock gating protocol setting + // for DES. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP36_CFG \ + 0x00000002 // Clock gating protocol setting + // for AES. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP57_CFG \ + 0x00000001 // Clock gating protocol setting + // for SHAMD5. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_EIP_CGREQ register. +// +//****************************************************************************** +#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5” write “1” to lower + // bits [4:0] will set the bit. + // Write “0” will be ignored When + // “0x2” write “1” to lower bit + // [4:0] will clear the bit. Write + // “0” will be ignored for other key + // value, regular read write + // operation +#define DTHE_EIP_CGREQ_Key_S 28 +#define DTHE_EIP_CGREQ_EIP29_REQ \ + 0x00000010 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP75_REQ \ + 0x00000008 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP16_REQ \ + 0x00000004 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP36_REQ \ + 0x00000002 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP57_REQ \ + 0x00000001 // 0 – request clock gating 1 – + // request to un-gate the clock. + +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register. +// +//****************************************************************************** +#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED + // register context as starting + // value 10 – all “zero” 11 – all + // “one” This is self clearing. With + // first write to data register this + // value clears to zero and remain + // zero for rest of the operation + // unless written again +#define DTHE_CRC_CTRL_INIT_S 13 +#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8 + // bit +#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result + // before storing to CRC_RSLT_PP0 +#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result + // byte before storing to + // CRC_RSLT_PP0. applicable for all + // bytes in word +#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For + // all bytes in word +#define DTHE_CRC_CTRL_ENDIAN_M \ + 0x00000030 // Endian control [0] – swap byte + // in half-word [1] – swap half word + +#define DTHE_CRC_CTRL_ENDIAN_S 4 +#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 – + // polynomial 0x8005 0001 – + // polynomial 0x1021 0010 – + // polynomial 0x4C11DB7 0011 – + // polynomial 0x1EDC6F41 1000 – TCP + // checksum TYPE in DTHE_S_CRC_CTRL + // & DTHE_S_CRC_CTRL should be + // exclusive +#define DTHE_CRC_CTRL_TYPE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_SEED register. +// +//****************************************************************************** +#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and + // checksum operation. Please see + // CTRL register for more detail. + // This resister also holds the + // latest result of CRC or checksum + // operation +#define DTHE_CRC_SEED_SEED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_DIN register. +// +//****************************************************************************** +#define DTHE_CRC_DIN_DATA_IN_M \ + 0xFFFFFFFF // Input data for CRC or checksum + // operation + +#define DTHE_CRC_DIN_DATA_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_CRC_RSLT_PP register. +// +//****************************************************************************** +#define DTHE_CRC_RSLT_PP_RSLT_PP_M \ + 0xFFFFFFFF // Input data for CRC or checksum + // operation + +#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY0 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [31:0] +#define DTHE_RAND_KEY0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY1 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [63:32] +#define DTHE_RAND_KEY1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY2 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [95:34] +#define DTHE_RAND_KEY2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY3 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [127:96] +#define DTHE_RAND_KEY3_KEY_S 0 + + + +#endif // __HW_DTHE_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_flash_ctrl.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_flash_ctrl.h new file mode 100644 index 0000000000..b57044aa13 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_flash_ctrl.h @@ -0,0 +1,1862 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_FLASH_CTRL_H__ +#define __HW_FLASH_CTRL_H__ + +//***************************************************************************** +// +// The following are defines for the FLASH_CTRL register offsets. +// +//***************************************************************************** +#define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA) + // offset 0x000 During a write + // operation this register contains + // a 4-byte-aligned address and + // specifies where the data is + // written. During erase operations + // this register contains a 1 + // KB-aligned CPU byte address and + // specifies which block is erased. + // Note that the alignment + // requirements must be met by + // software or the results of the + // operation are unpredictable. +#define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset + // 0x004 This register contains the + // data to be written during the + // programming cycle or read during + // the read cycle. Note that the + // contents of this register are + // undefined for a read access of an + // execute-only block. This register + // is not used during erase cycles. +#define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC) + // offset 0x008 When this register + // is written the Flash memory + // controller initiates the + // appropriate access cycle for the + // location specified by the Flash + // Memory Address (FMA) register . + // If the access is a write access + // the data contained in the Flash + // Memory Data (FMD) register is + // written to the specified address. + // This register must be the final + // register written and initiates + // the memory operation. The four + // control bits in the lower byte of + // this register are used to + // initiate memory operations. +#define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt + // Status (FCRIS) offset 0x00C This + // register indicates that the Flash + // memory controller has an + // interrupt condition. An interrupt + // is sent to the interrupt + // controller only if the + // corresponding FCIM register bit + // is set. +#define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask + // (FCIM) offset 0x010 This register + // controls whether the Flash memory + // controller generates interrupts + // to the controller. +#define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked + // Interrupt Status and Clear + // (FCMISC) offset 0x014 This + // register provides two functions. + // First it reports the cause of an + // interrupt by indicating which + // interrupt source or sources are + // signalling the interrupt. Second + // it serves as the method to clear + // the interrupt reporting. +#define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2) + // offset 0x020 When this register + // is written the Flash memory + // controller initiates the + // appropriate access cycle for the + // location specified by the Flash + // Memory Address (FMA) register . + // If the access is a write access + // the data contained in the Flash + // Write Buffer (FWB) registers is + // written. This register must be + // the final register written as it + // initiates the memory operation. +#define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid + // (FWBVAL) offset 0x030 This + // register provides a bitwise + // status of which FWBn registers + // have been written by the + // processor since the last write of + // the Flash memory write buffer. + // The entries with a 1 are written + // on the next write of the Flash + // memory write buffer. This + // register is cleared after the + // write operation by hardware. A + // protection violation on the write + // operation also clears this + // status. Software can program the + // same 32 words to various Flash + // memory locations by setting the + // FWB[n] bits after they are + // cleared by the write operation. + // The next write operation then + // uses the same data as the + // previous one. In addition if a + // FWBn register change should not + // be written to Flash memory + // software can clear the + // corresponding FWB[n] bit to + // preserve the existing data when + // the next write operation occurs. +#define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0 + // This register indicates the size + // of the on-chip Flash memory. + // Important: This register should + // be used to determine the size of + // the Flash memory that is + // implemented on this + // microcontroller. However to + // support legacy software the DC0 + // register is available. A read of + // the DC0 register correctly + // identifies legacy memory sizes. + // Software must use the FSIZE + // register for memory sizes that + // are not listed in the DC0 + // register description. +#define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4 + // This register indicates the size + // of the on-chip SRAM. Important: + // This register should be used to + // determine the size of the SRAM + // that is implemented on this + // microcontroller. However to + // support legacy software the DC0 + // register is available. A read of + // the DC0 register correctly + // identifies legacy memory sizes. + // Software must use the SSIZE + // register for memory sizes that + // are not listed in the DC0 + // register description. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMA register. +// +//****************************************************************************** +#define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in + // Flash memory where operation is + // performed except for nonvolatile + // registers +#define FLASH_CTRL_FMA_OFFSET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMD register. +// +//****************************************************************************** +#define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write + // operation. +#define FLASH_CTRL_FMD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMC register. +// +//****************************************************************************** +#define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This + // field contains a write key which + // is used to minimize the incidence + // of accidental Flash memory + // writes. The value 0xA442 must be + // written into this field for a + // Flash memory write to occur. + // Writes to the FMC register + // without this WRKEY value are + // ignored. A read of this field + // returns the value 0. +#define FLASH_CTRL_FMC_WRKEY_S 16 +#define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit + // is used to commit writes to + // Flash-memory-resident registers + // and to monitor the progress of + // that process. Value Description 1 + // Set this bit to commit (write) + // the register value to a + // Flash-memory-resident register. + // When read a 1 indicates that the + // previous commit access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous commit access is + // complete. +#define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit + // is used to mass erase the Flash + // main memory and to monitor the + // progress of that process. Value + // Description 1 Set this bit to + // erase the Flash main memory. When + // read a 1 indicates that the + // previous mass erase access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous mass erase access is + // complete. +#define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory + // This bit is used to erase a page + // of Flash memory and to monitor + // the progress of that process. + // Value Description 1 Set this bit + // to erase the Flash memory page + // specified by the contents of the + // FMA register. When read a 1 + // indicates that the previous page + // erase access is not complete. 0 A + // write of 0 has no effect on the + // state of this bit. When read a 0 + // indicates that the previous page + // erase access is complete. +#define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + // This bit is used to write a word + // into Flash memory and to monitor + // the progress of that process. + // Value Description 1 Set this bit + // to write the data stored in the + // FMD register into the Flash + // memory location specified by the + // contents of the FMA register. + // When read a 1 indicates that the + // write update access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous write update access is + // complete. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FCRIS register. +// +//****************************************************************************** +#define FLASH_CTRL_FCRIS_PROGRIS \ + 0x00002000 // Program Verify Error Raw + // Interrupt Status Value + // Description 1 An interrupt is + // pending because the verify of a + // PROGRAM operation failed. 0 An + // interrupt has not occurred. This + // bit is cleared by writing a 1 to + // the PROGMISC bit in the FCMISC + // register. + +#define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because the + // verify of an ERASE operation + // failed. 0 An interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the ERMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_INVDRIS \ + 0x00000400 // Invalid Data Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because a + // bit that was previously + // programmed as a 0 is now being + // requested to be programmed as a + // 1. 0 An interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the INVMISC bit in + // the FCMISC register. + +#define FLASH_CTRL_FCRIS_VOLTRIS \ + 0x00000200 // Pump Voltage Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because the + // regulated voltage of the pump + // went out of spec during the Flash + // operation and the operation was + // terminated. 0 An interrupt has + // not occurred. This bit is cleared + // by writing a 1 to the VOLTMISC + // bit in the FCMISC register. + +#define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This + // bit provides status EEPROM + // operation. Value Description 1 An + // EEPROM interrupt has occurred. 0 + // An EEPROM interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the EMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status + // This bit provides status on + // programming cycles which are + // write or erase actions generated + // through the FMC or FMC2 register + // bits (see page 537 and page 549). + // Value Description 1 The + // programming or erase cycle has + // completed. 0 The programming or + // erase cycle has not completed. + // This status is sent to the + // interrupt controller when the + // PMASK bit in the FCIM register is + // set. This bit is cleared by + // writing a 1 to the PMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + // Value Description 1 A program or + // erase action was attempted on a + // block of Flash memory that + // contradicts the protection policy + // for that block as set in the + // FMPPEn registers. 0 No access has + // tried to improperly program or + // erase the Flash memory. This + // status is sent to the interrupt + // controller when the AMASK bit in + // the FCIM register is set. This + // bit is cleared by writing a 1 to + // the AMISC bit in the FCMISC + // register. +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register. +// +//****************************************************************************** +#define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the ILLARIS bit + // is set. 0 The ILLARIS interrupt + // is suppressed and not sent to the + // interrupt controller. +#define FLASH_CTRL_FCIM_PROGMASK \ + 0x00002000 // PROGVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the PROGRIS bit is set. 0 + // The PROGRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the PRERIS bit is set. 0 The + // PRERIS interrupt is suppressed + // and not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ERRIS bit is set. 0 The + // ERRIS interrupt is suppressed and + // not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_INVDMASK \ + 0x00000400 // Invalid Data Interrupt Mask + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the INVDRIS bit + // is set. 0 The INVDRIS interrupt + // is suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_VOLTMASK \ + 0x00000200 // VOLT Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the VOLTRIS bit is set. 0 + // The VOLTRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_LOCKMASK \ + 0x00000100 // LOCK Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the LOCKRIS bit is set. 0 + // The LOCKRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ERIS bit is set. 0 The + // ERIS interrupt is suppressed and + // not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This + // bit controls the reporting of the + // programming raw interrupt status + // to the interrupt controller. + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the PRIS bit is + // set. 0 The PRIS interrupt is + // suppressed and not sent to the + // interrupt controller. +#define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit + // controls the reporting of the + // access raw interrupt status to + // the interrupt controller. Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ARIS bit is set. 0 The + // ARIS interrupt is suppressed and + // not sent to the interrupt + // controller. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FCMISC register. +// +//****************************************************************************** +#define FLASH_CTRL_FCMISC_ILLMISC \ + 0x00004000 // Illegal Address Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled. Writing a + // 1 to this bit clears ILLAMISC and + // also the ILLARIS bit in the FCRIS + // register (see page 540). 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_PROGMISC \ + 0x00002000 // PROGVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // PROGMISC and also the PROGRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_PREMISC \ + 0x00001000 // PREVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // PREMISC and also the PRERIS bit + // in the FCRIS register . 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_ERMISC \ + 0x00000800 // ERVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // ERMISC and also the ERRIS bit in + // the FCRIS register 0 When read a + // 0 indicates that an interrupt has + // not occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_INVDMISC \ + 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled. Writing a + // 1 to this bit clears INVDMISC and + // also the INVDRIS bit in the FCRIS + // register (see page 540). 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_VOLTMISC \ + 0x00000200 // VOLT Masked Interrupt Status and + // Clear Value Description 1 When + // read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // VOLTMISC and also the VOLTRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_LOCKMISC \ + 0x00000100 // LOCK Masked Interrupt Status and + // Clear Value Description 1 When + // read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // LOCKMISC and also the LOCKRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // EMISC and also the ERIS bit in + // the FCRIS register 0 When read a + // 0 indicates that an interrupt has + // not occurred. A write of 0 has no + // effect on the state of this bit. +#define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled because a + // programming cycle completed. + // Writing a 1 to this bit clears + // PMISC and also the PRIS bit in + // the FCRIS register 0 When read a + // 0 indicates that a programming + // cycle complete interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. +#define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled + // because a program or erase action + // was attempted on a block of Flash + // memory that contradicts the + // protection policy for that block + // as set in the FMPPEn registers. + // Writing a 1 to this bit clears + // AMISC and also the ARIS bit in + // the FCRIS register 0 When read a + // 0 indicates that no improper + // accesses have occurred. A write + // of 0 has no effect on the state + // of this bit. +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register. +// +//****************************************************************************** +#define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This + // field contains a write key which + // is used to minimize the incidence + // of accidental Flash memory + // writes. The value 0xA442 must be + // written into this field for a + // write to occur. Writes to the + // FMC2 register without this WRKEY + // value are ignored. A read of this + // field returns the value 0. +#define FLASH_CTRL_FMC2_WRKEY_S 16 +#define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This + // bit is used to start a buffered + // write to Flash memory. Value + // Description 1 Set this bit to + // write the data stored in the FWBn + // registers to the location + // specified by the contents of the + // FMA register. When read a 1 + // indicates that the previous + // buffered Flash memory write + // access is not complete. 0 A write + // of 0 has no effect on the state + // of this bit. When read a 0 + // indicates that the previous + // buffered Flash memory write + // access is complete. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWBVAL register. +// +//****************************************************************************** +#define FLASH_CTRL_FWBVAL_FWBN_M \ + 0xFFFFFFFF // Flash Memory Write Buffer Value + // Description 1 The corresponding + // FWBn register has been updated + // since the last buffer write + // operation and is ready to be + // written to Flash memory. 0 The + // corresponding FWBn register has + // no new data to be written. Bit 0 + // corresponds to FWB0 offset 0x100 + // and bit 31 corresponds to FWB31 + // offset 0x13C. + +#define FLASH_CTRL_FWBVAL_FWBN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB4_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB5_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB6_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB7_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB8_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB9_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB10 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB10_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB11 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB11_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB12 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB12_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB13 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB13_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB14 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB14_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB15 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB15_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB16 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB16_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB17 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB17_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB18 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB18_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB19 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB19_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB20 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB20_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB21 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB21_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB22 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB22_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB23 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB23_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB24 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB24_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB25 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB25_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB26 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB26_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB27 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB27_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB28 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB28_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB29 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB29_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB30 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB30_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB31 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB31_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB32 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB32_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FSIZE register. +// +//****************************************************************************** +#define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of + // the on-chip Flash memory. Value + // Description 0x0003 8 KB of Flash + // 0x0007 16 KB of Flash 0x000F 32 + // KB of Flash 0x001F 64 KB of Flash + // 0x002F 96 KB of Flash 0x003F 128 + // KB of Flash 0x005F 192 KB of + // Flash 0x007F 256 KB of Flash +#define FLASH_CTRL_FSIZE_SIZE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_SSIZE register. +// +//****************************************************************************** +#define FLASH_CTRL_SSIZE_SRAM_SIZE_M \ + 0x0000FFFF // SRAM Size Indicates the size of + // the on-chip SRAM. Value + // Description 0x0007 2 KB of SRAM + // 0x000F 4 KB of SRAM 0x0017 6 KB + // of SRAM 0x001F 8 KB of SRAM + // 0x002F 12 KB of SRAM 0x003F 16 KB + // of SRAM 0x004F 20 KB of SRAM + // 0x005F 24 KB of SRAM 0x007F 32 KB + // of SRAM + +#define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0 +#define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key +#define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1 +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read + // Enable 0 +#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read + // Enable 1 +#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read + // Enable 2 +#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read + // Enable 3 +#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read + // Enable 4 +#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read + // Enable 5 +#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read + // Enable 6 +#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read + // Enable 7 +#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read + // Enable 8 +#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read + // Enable 9 +#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read + // Enable 10 +#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read + // Enable 11 +#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read + // Enable 12 +#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read + // Enable 13 +#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read + // Enable 14 +#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read + // Enable 15 + +#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program + // Enable 0 +#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program + // Enable 1 +#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program + // Enable 2 +#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program + // Enable 3 +#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program + // Enable 4 +#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program + // Enable 5 +#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program + // Enable 6 +#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program + // Enable 7 +#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program + // Enable 8 +#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program + // Enable 9 +#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program + // Enable 10 +#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program + // Enable 11 +#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program + // Enable 12 +#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program + // Enable 13 +#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program + // Enable 14 +#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program + // Enable 15 + +#define FLASH_USECRL 0x400FE140 // USec Reload +#define FLASH_CTRL_ERASE_SIZE 0x00000400 + + +#endif // __HW_FLASH_CTRL_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gpio.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gpio.h new file mode 100644 index 0000000000..2bd6e0f3ae --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gpio.h @@ -0,0 +1,1349 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets. +// +//***************************************************************************** +#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000 + // 7000 0x4002 4000 GPIO Data + // (GPIODATA)@@ offset 0x000 The + // GPIODATA register is the data + // register. In software control + // mode@@ values written in the + // GPIODATA register are transferred + // onto the GPIO port pins if the + // respective pins have been + // configured as outputs through the + // GPIO Direction (GPIODIR) register + // (see page 653). In order to write + // to GPIODATA@@ the corresponding + // bits in the mask@@ resulting from + // the address bus bits [9:2]@@ must + // be set. Otherwise@@ the bit + // values remain unchanged by the + // write. Similarly@@ the values + // read from this register are + // determined for each bit by the + // mask bit derived from the address + // used to access the data + // register@@ bits [9:2]. Bits that + // are set in the address mask cause + // the corresponding bits in + // GPIODATA to be read@@ and bits + // that are clear in the address + // mask cause the corresponding bits + // in GPIODATA to be read as 0@@ + // regardless of their value. A read + // from GPIODATA returns the last + // bit value written if the + // respective pins are configured as + // outputs@@ or it returns the value + // on the corresponding input pin + // when these are configured as + // inputs. All bits are cleared by a + // reset. +#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000 + // 7400 0x4002 4400 GPIO Direction + // (GPIODIR)@@ offset 0x400 The + // GPIODIR register is the data + // direction register. Setting a bit + // in the GPIODIR register + // configures the corresponding pin + // to be an output@@ while clearing + // a bit configures the + // corresponding pin to be an input. + // All bits are cleared by a reset@@ + // meaning all GPIO pins are inputs + // by default. +#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000 + // 7404 0x4002 4404 GPIO Interrupt + // Sense (GPIOIS)@@ offset 0x404 The + // GPIOIS register is the interrupt + // sense register. Setting a bit in + // the GPIOIS register configures + // the corresponding pin to detect + // levels@@ while clearing a bit + // configures the corresponding pin + // to detect edges. All bits are + // cleared by a reset. +#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000 + // 7408 0x4002 4408 GPIO Interrupt + // Both Edges (GPIOIBE)@@ offset + // 0x408 The GPIOIBE register allows + // both edges to cause interrupts. + // When the corresponding bit in the + // GPIO Interrupt Sense (GPIOIS) + // register is set to detect edges@@ + // setting a bit in the GPIOIBE + // register configures the + // corresponding pin to detect both + // rising and falling edges@@ + // regardless of the corresponding + // bit in the GPIO Interrupt Event + // (GPIOIEV) register . Clearing a + // bit configures the pin to be + // controlled by the GPIOIEV + // register. All bits are cleared by + // a reset. +#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000 + // 740C 0x4002 440C GPIO Interrupt + // Event (GPIOIEV)@@ offset 0x40C + // The GPIOIEV register is the + // interrupt event register. Setting + // a bit in the GPIOIEV register + // configures the corresponding pin + // to detect rising edges or high + // levels@@ depending on the + // corresponding bit value in the + // GPIO Interrupt Sense (GPIOIS) + // register . Clearing a bit + // configures the pin to detect + // falling edges or low levels@@ + // depending on the corresponding + // bit value in the GPIOIS register. + // All bits are cleared by a reset. +#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000 + // 7410 0x4002 4410 GPIO Interrupt + // Mask (GPIOIM)@@ offset 0x410 The + // GPIOIM register is the interrupt + // mask register. Setting a bit in + // the GPIOIM register allows + // interrupts that are generated by + // the corresponding pin to be sent + // to the interrupt controller on + // the combined interrupt signal. + // Clearing a bit prevents an + // interrupt on the corresponding + // pin from being sent to the + // interrupt controller. All bits + // are cleared by a reset. +#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000 + // 7414 0x4002 4414 GPIO Raw + // Interrupt Status (GPIORIS)@@ + // offset 0x414 The GPIORIS register + // is the raw interrupt status + // register. A bit in this register + // is set when an interrupt + // condition occurs on the + // corresponding GPIO pin. If the + // corresponding bit in the GPIO + // Interrupt Mask (GPIOIM) register + // is set@@ the interrupt is sent to + // the interrupt controller. Bits + // read as zero indicate that + // corresponding input pins have not + // initiated an interrupt. A bit in + // this register can be cleared by + // writing a 1 to the corresponding + // bit in the GPIO Interrupt Clear + // (GPIOICR) register. +#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000 + // 7418 0x4002 4418 GPIO Masked + // Interrupt Status (GPIOMIS)@@ + // offset 0x418 The GPIOMIS register + // is the masked interrupt status + // register. If a bit is set in this + // register@@ the corresponding + // interrupt has triggered an + // interrupt to the interrupt + // controller. If a bit is clear@@ + // either no interrupt has been + // generated@@ or the interrupt is + // masked. If no port pin@@ other + // than the one that is being used + // as an ADC trigger@@ is being used + // to generate interrupts@@ the + // appropriate Interrupt Set Enable + // (ENn) register can disable the + // interrupts for the port@@ and the + // ADC interrupt can be used to read + // back the converted data. + // Otherwise@@ the port interrupt + // handler must ignore and clear + // interrupts on the port pin and + // wait for the ADC interrupt@@ or + // the ADC interrupt must be + // disabled in the EN0 register and + // the port interrupt handler must + // poll the ADC registers until the + // conversion is completed. If no + // port pin@@ other than the one + // that is being used as an ADC + // trigger@@ is being used to + // generate interrupts@@ the + // appropriate Interrupt Set Enable + // (ENn) register can disable the + // interrupts for the port@@ and the + // ADC interrupt can be used to read + // back the converted data. + // Otherwise@@ the port interrupt + // handler must ignore and clear + // interrupts on the port pin and + // wait for the ADC interrupt@@ or + // the ADC interrupt must be + // disabled in the EN0 register and + // the port interrupt handler must + // poll the ADC registers until the + // conversion is completed. Note + // that if the Port B GPIOADCCTL + // register is cleared@@ PB4 can + // still be used as an external + // trigger for the ADC. This is a + // legacy mode which allows code + // written for previous Stellaris + // devices to operate on this + // microcontroller. GPIOMIS is the + // state of the interrupt after + // masking. +#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000 + // 741C 0x4002 441C GPIO Interrupt + // Clear (GPIOICR)@@ offset 0x41C + // The GPIOICR register is the + // interrupt clear register. Writing + // a 1 to a bit in this register + // clears the corresponding + // interrupt bit in the GPIORIS and + // GPIOMIS registers. Writing a 0 + // has no effect. +#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000 + // 7420 0x4002 4420 GPIO Alternate + // Function Select (GPIOAFSEL)@@ + // offset 0x420 The GPIOAFSEL + // register is the mode control + // select register. If a bit is + // clear@@ the pin is used as a GPIO + // and is controlled by the GPIO + // registers. Setting a bit in this + // register configures the + // corresponding GPIO line to be + // controlled by an associated + // peripheral. Several possible + // peripheral functions are + // multiplexed on each GPIO. The + // GPIO Port Control (GPIOPCTL) + // register is used to select one of + // the possible functions. +#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000 + // 7500 0x4002 4500 GPIO 2-mA Drive + // Select (GPIODR2R)@@ offset 0x500 + // The GPIODR2R register is the 2-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV2 bit for a GPIO + // signal@@ the corresponding DRV4 + // bit in the GPIODR4R register and + // DRV8 bit in the GPIODR8R register + // are automatically cleared by + // hardware. By default@@ all GPIO + // pins have 2-mA drive. +#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000 + // 7504 0x4002 4504 GPIO 4-mA Drive + // Select (GPIODR4R)@@ offset 0x504 + // The GPIODR4R register is the 4-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV4 bit for a GPIO + // signal@@ the corresponding DRV2 + // bit in the GPIODR2R register and + // DRV8 bit in the GPIODR8R register + // are automatically cleared by + // hardware. +#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000 + // 7508 0x4002 4508 GPIO 8-mA Drive + // Select (GPIODR8R)@@ offset 0x508 + // The GPIODR8R register is the 8-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV8 bit for a GPIO + // signal@@ the corresponding DRV2 + // bit in the GPIODR2R register and + // DRV4 bit in the GPIODR4R register + // are automatically cleared by + // hardware. The 8-mA setting is + // also used for high-current + // operation. Note: There is no + // configuration difference between + // 8-mA and high-current operation. + // The additional current capacity + // results from a shift in the + // VOH/VOL levels. +#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000 + // 750C 0x4002 450C GPIO Open Drain + // Select (GPIOODR)@@ offset 0x50C + // The GPIOODR register is the open + // drain control register. Setting a + // bit in this register enables the + // open-drain configuration of the + // corresponding GPIO pad. When + // open-drain mode is enabled@@ the + // corresponding bit should also be + // set in the GPIO Digital Input + // Enable (GPIODEN) register . + // Corresponding bits in the drive + // strength and slew rate control + // registers (GPIODR2R@@ GPIODR4R@@ + // GPIODR8R@@ and GPIOSLR) can be + // set to achieve the desired rise + // and fall times. The GPIO acts as + // an open-drain input if the + // corresponding bit in the GPIODIR + // register is cleared. If open + // drain is selected while the GPIO + // is configured as an input@@ the + // GPIO will remain an input and the + // open-drain selection has no + // effect until the GPIO is changed + // to an output. When using the I2C + // module@@ in addition to + // configuring the pin to open + // drain@@ the GPIO Alternate + // Function Select (GPIOAFSEL) + // register bits for the I2C clock + // and data pins should be set +#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000 + // 7510 0x4002 4510 GPIO Pull-Up + // Select (GPIOPUR)@@ offset 0x510 + // The GPIOPUR register is the + // pull-up control register. When a + // bit is set@@ a weak pull-up + // resistor on the corresponding + // GPIO signal is enabled. Setting a + // bit in GPIOPUR automatically + // clears the corresponding bit in + // the GPIO Pull-Down Select + // (GPIOPDR) register . Write access + // to this register is protected + // with the GPIOCR register. Bits in + // GPIOCR that are cleared prevent + // writes to the equivalent bit in + // this register. +#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000 + // 7514 0x4002 4514 GPIO Pull-Down + // Select (GPIOPDR)@@ offset 0x514 + // The GPIOPDR register is the + // pull-down control register. When + // a bit is set@@ a weak pull-down + // resistor on the corresponding + // GPIO signal is enabled. Setting a + // bit in GPIOPDR automatically + // clears the corresponding bit in + // the GPIO Pull-Up Select (GPIOPUR) + // register +#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000 + // 7518 0x4002 4518 The GPIOSLR + // register is the slew rate control + // register. Slew rate control is + // only available when using the + // 8-mA drive strength option via + // the GPIO 8-mA Drive Select + // (GPIODR8R) register +#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000 + // 751C 0x4002 451C GPIO Digital + // Enable (GPIODEN)@@ offset 0x51C + // Note: Pins configured as digital + // inputs are Schmitt-triggered. The + // GPIODEN register is the digital + // enable register. By default@@ all + // GPIO signals except those listed + // below are configured out of reset + // to be undriven (tristate). Their + // digital function is disabled; + // they do not drive a logic value + // on the pin and they do not allow + // the pin voltage into the GPIO + // receiver. To use the pin as a + // digital input or output (either + // GPIO or alternate function)@@ the + // corresponding GPIODEN bit must be + // set. +#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000 + // 7520 0x4002 4520 GPIO Lock + // (GPIOLOCK)@@ offset 0x520 The + // GPIOLOCK register enables write + // access to the GPIOCR register . + // Writing 0x4C4F.434B to the + // GPIOLOCK register unlocks the + // GPIOCR register. Writing any + // other value to the GPIOLOCK + // register re-enables the locked + // state. Reading the GPIOLOCK + // register returns the lock status + // rather than the 32-bit value that + // was previously written. + // Therefore@@ when write accesses + // are disabled@@ or locked@@ + // reading the GPIOLOCK register + // returns 0x0000.0001. When write + // accesses are enabled@@ or + // unlocked@@ reading the GPIOLOCK + // register returns 0x0000.0000. +#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000 + // 7524 0x4002 4524 GPIO Commit + // (GPIOCR)@@ offset 0x524 The + // GPIOCR register is the commit + // register. The value of the GPIOCR + // register determines which bits of + // the GPIOAFSEL@@ GPIOPUR@@ + // GPIOPDR@@ and GPIODEN registers + // are committed when a write to + // these registers is performed. If + // a bit in the GPIOCR register is + // cleared@@ the data being written + // to the corresponding bit in the + // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ + // or GPIODEN registers cannot be + // committed and retains its + // previous value. If a bit in the + // GPIOCR register is set@@ the data + // being written to the + // corresponding bit of the + // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ + // or GPIODEN registers is committed + // to the register and reflects the + // new value. The contents of the + // GPIOCR register can only be + // modified if the status in the + // GPIOLOCK register is unlocked. + // Writes to the GPIOCR register are + // ignored if the status in the + // GPIOLOCK register is locked. +#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000 + // 7528 0x4002 4528 The GPIOAMSEL + // register controls isolation + // circuits to the analog side of a + // unified I/O pad. Because the + // GPIOs may be driven by a 5-V + // source and affect analog + // operation@@ analog circuitry + // requires isolation from the pins + // when they are not used in their + // analog function. Each bit of this + // register controls the isolation + // circuitry for the corresponding + // GPIO signal. +#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) 0x4000 552C + // 0x4000 652C 0x4000 752C 0x4002 + // 452C GPIO Port Control + // (GPIOPCTL)@@ offset 0x52C The + // GPIOPCTL register is used in + // conjunction with the GPIOAFSEL + // register and selects the specific + // peripheral signal for each GPIO + // pin when using the alternate + // function mode. Most bits in the + // GPIOAFSEL register are cleared on + // reset@@ therefore most GPIO pins + // are configured as GPIOs by + // default. When a bit is set in the + // GPIOAFSEL register@@ the + // corresponding GPIO signal is + // controlled by an associated + // peripheral. The GPIOPCTL register + // selects one out of a set of + // peripheral functions for each + // GPIO@@ providing additional + // flexibility in signal definition. +#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in + // cc3xx. ADC trigger via GPIO is + // not supported. 0x4000 5530 0x4000 + // 6530 0x4000 7530 0x4002 4530 GPIO + // ADC Control (GPIOADCCTL)@@ offset + // 0x530 This register is used to + // configure a GPIO pin as a source + // for the ADC trigger. Note that if + // the Port B GPIOADCCTL register is + // cleared@@ PB4 can still be used + // as an external trigger for the + // ADC. This is a legacy mode which + // allows code written for previous + // Stellaris devices to operate on + // this microcontroller. +#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000 + // 7534 0x4002 4534 GPIO DMA Control + // (GPIODMACTL)@@ offset 0x534 This + // register is used to configure a + // GPIO pin as a source for the ?DMA + // trigger. +#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000 + // 7538 0x4002 4538 GPIO Select + // Interrupt (GPIOSI)@@ offset 0x538 + // This register is used to enable + // individual interrupts for each + // pin. Note: This register is only + // available on Port P and Port Q. +#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000 + // 7FD0 0x4002 4FD0 GPIO Peripheral + // Identification 4 + // (GPIOPeriphID4)@@ offset 0xFD0 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000 + // 7FD4 0x4002 4FD4 GPIO Peripheral + // Identification 5 + // (GPIOPeriphID5)@@ offset 0xFD4 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000 + // 7FD8 0x4002 4FD8 GPIO Peripheral + // Identification 6 + // (GPIOPeriphID6)@@ offset 0xFD8 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000 + // 7FDC 0x4002 4FDC GPIO Peripheral + // Identification 7 + // (GPIOPeriphID7)@@ offset 0xFDC + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000 + // 7FE0 0x4002 4FE0 GPIO Peripheral + // Identification 0 + // (GPIOPeriphID0)@@ offset 0xFE0 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000 + // 7FE4 0x4002 4FE4 GPIO Peripheral + // Identification 1 + // (GPIOPeriphID1)@@ offset 0xFE4 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000 + // 7FE8 0x4002 4FE8 GPIO Peripheral + // Identification 2 + // (GPIOPeriphID2)@@ offset 0xFE8 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000 + // 7FEC 0x4002 4FEC GPIO Peripheral + // Identification 3 + // (GPIOPeriphID3)@@ offset 0xFEC + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000 + // 7FF0 0x4002 4FF0 GPIO PrimeCell + // Identification 0 (GPIOPCellID0)@@ + // offset 0xFF0 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000 + // 7FF4 0x4002 4FF4 GPIO PrimeCell + // Identification 1 (GPIOPCellID1)@@ + // offset 0xFF4 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000 + // 7FF8 0x4002 4FF8 GPIO PrimeCell + // Identification 2 (GPIOPCellID2)@@ + // offset 0xFF8 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000 + // 7FFC 0x4002 4FFC GPIO PrimeCell + // Identification 3 (GPIOPCellID3)@@ + // offset 0xFFC The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system.0xb1 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register. +// +//****************************************************************************** +#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is + // virtually mapped to 256 locations + // in the address space. To + // facilitate the reading and + // writing of data to these + // registers by independent + // drivers@@ the data read from and + // written to the registers are + // masked by the eight address lines + // [9:2]. Reads from this register + // return its current state. Writes + // to this register only affect bits + // that are not masked by ADDR[9:2] + // and are configured as outputs. +#define GPIO_GPIO_DATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register. +// +//****************************************************************************** +#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value + // Description 0 Corresponding pin + // is an input. 1 Corresponding pins + // is an output. +#define GPIO_GPIO_DIR_DIR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IS register. +// +//****************************************************************************** +#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value + // Description 0 The edge on the + // corresponding pin is detected + // (edge-sensitive). 1 The level on + // the corresponding pin is detected + // (level-sensitive). +#define GPIO_GPIO_IS_IS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register. +// +//****************************************************************************** +#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value + // Description 0 Interrupt + // generation is controlled by the + // GPIO Interrupt Event (GPIOIEV) + // register. 1 Both edges on the + // corresponding pin trigger an + // interrupt. +#define GPIO_GPIO_IBE_IBE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register. +// +//****************************************************************************** +#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value + // Description 1 A falling edge or a + // Low level on the corresponding + // pin triggers an interrupt. 0 A + // rising edge or a High level on + // the corresponding pin triggers an + // interrupt. +#define GPIO_GPIO_IEV_IEV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IM register. +// +//****************************************************************************** +#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value + // Description 0 The interrupt from + // the corresponding pin is masked. + // 1 The interrupt from the + // corresponding pin is sent to the + // interrupt controller. +#define GPIO_GPIO_IM_IME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register. +// +//****************************************************************************** +#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value + // Description 1 An interrupt + // condition has occurred on the + // corresponding pin. 0 interrupt + // condition has not occurred on the + // corresponding pin. A bit is + // cleared by writing a 1 to the + // corresponding bit in the GPIOICR + // register. +#define GPIO_GPIO_RIS_RIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register. +// +//****************************************************************************** +#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status + // Value Description 1 An interrupt + // condition on the corresponding + // pin has triggered an interrupt to + // the interrupt controller. 0 An + // interrupt condition on the + // corresponding pin is masked or + // has not occurred. A bit is + // cleared by writing a 1 to the + // corresponding bit in the GPIOICR + // register. +#define GPIO_GPIO_MIS_MIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register. +// +//****************************************************************************** +#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value + // Description 1 The corresponding + // interrupt is cleared. 0 The + // corresponding interrupt is + // unaffected. +#define GPIO_GPIO_ICR_IC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 2-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 2-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR4R + // or GPIODR8R register. 0 Setting a + // bit in either the GPIODR4 + // register or the GPIODR8 register + // clears the corresponding 2-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR2R_DRV2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 4-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 4-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR2R + // or GPIODR8R register. 0 Setting a + // bit in either the GPIODR2 + // register or the GPIODR8 register + // clears the corresponding 4-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR4R_DRV4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 8-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 8-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR2R + // or GPIODR4R register. 0 Setting a + // bit in either the GPIODR2 + // register or the GPIODR4 register + // clears the corresponding 8-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR8R_DRV8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register. +// +//****************************************************************************** +#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // Open Drain Enable Value + // Description 1 The corresponding + // pin is configured as open drain. + // 0 The corresponding pin is not + // configured as open drain. +#define GPIO_GPIO_ODR_ODE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register. +// +//****************************************************************************** +#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Pad Weak + // Pull-Up Enable Value Description + // 1 The corresponding pin has a + // weak pull-up resistor. 0 The + // corresponding pin is not + // affected. Setting a bit in the + // GPIOPDR register clears the + // corresponding bit in the GPIOPUR + // register. The change is effective + // on the second clock cycle after + // the write if accessing GPIO via + // the APB memory aperture. If using + // AHB access@@ the change is + // effective on the next clock + // cycle. +#define GPIO_GPIO_PUR_PUE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register. +// +//****************************************************************************** +#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Pad Weak + // Pull-Down Enable Value + // Description 1 The corresponding + // pin has a weak pull-down + // resistor. 0 The corresponding pin + // is not affected. Setting a bit in + // the GPIOPUR register clears the + // corresponding bit in the GPIOPDR + // register. The change is effective + // on the second clock cycle after + // the write if accessing GPIO via + // the APB memory aperture. If using + // AHB access@@ the change is + // effective on the next clock + // cycle. +#define GPIO_GPIO_PDR_PDE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register. +// +//****************************************************************************** +#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Slew Rate + // Limit Enable (8-mA drive only) + // Value Description 1 Slew rate + // control is enabled for the + // corresponding pin. 0 Slew rate + // control is disabled for the + // corresponding pin. +#define GPIO_GPIO_SLR_SRL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register. +// +//****************************************************************************** +#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Digital Enable + // Value Description 0 The digital + // functions for the corresponding + // pin are disabled. 1 The digital + // functions for the corresponding + // pin are enabled. +#define GPIO_GPIO_DEN_DEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register. +// +//****************************************************************************** +#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in + // cc3xx. GPIO Lock A write of the + // value 0x4C4F.434B unlocks the + // GPIO Commit (GPIOCR) register for + // write access.A write of any other + // value or a write to the GPIOCR + // register reapplies the lock@@ + // preventing any register updates. + // A read of this register returns + // the following values: Value + // Description 0x1 The GPIOCR + // register is locked and may not be + // modified. 0x0 The GPIOCR register + // is unlocked and may be modified. +#define GPIO_GPIO_LOCK_LOCK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_CR register. +// +//****************************************************************************** +#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) GPIO Commit + // Value Description The + // corresponding GPIOAFSEL@@ + // GPIOPUR@@ GPIOPDR@@ or GPIODEN + // bits can be written. 1 The + // corresponding GPIOAFSEL@@ + // GPIOPUR@@ GPIOPDR@@ or GPIODEN + // bits cannot be written. 0 Note: + // The default register type for the + // GPIOCR register is RO for all + // GPIO pins with the exception of + // the NMI pin and the four JTAG/SWD + // pins (PD7@@ PF0@@ and PC[3:0]). + // These six pins are the only GPIOs + // that are protected by the GPIOCR + // register. Because of this@@ the + // register type for GPIO Port D7@@ + // GPIO Port F0@@ and GPIO Port + // C[3:0] is R/W. The default reset + // value for the GPIOCR register is + // 0x0000.00FF for all GPIO pins@@ + // with the exception of the NMI pin + // and the four JTAG/SWD pins (PD7@@ + // PF0@@ and PC[3:0]). To ensure + // that the JTAG port is not + // accidentally programmed as GPIO + // pins@@ the PC[3:0] pins default + // to non-committable. Similarly@@ + // to ensure that the NMI pin is not + // accidentally programmed as a GPIO + // pin@@ the PD7 and PF0 pins + // default to non-committable. + // Because of this@@ the default + // reset value of GPIOCR for GPIO + // Port C is 0x0000.00F0@@ for GPIO + // Port D is 0x0000.007F@@ and for + // GPIO Port F is 0x0000.00FE. +#define GPIO_GPIO_CR_CR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register. +// +//****************************************************************************** +#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \ + 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) GPIO Analog + // Mode Select Value Description 1 + // The analog function of the pin is + // enabled@@ the isolation is + // disabled@@ and the pin is capable + // of analog functions. 0 The analog + // function of the pin is disabled@@ + // the isolation is enabled@@ and + // the pin is capable of digital + // functions as specified by the + // other GPIO configuration + // registers. Note: This register + // and bits are only valid for GPIO + // signals that share analog + // function through a unified I/O + // pad. The reset state of this + // register is 0 for all signals. + +#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register. +// +//****************************************************************************** +#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 7 This field controls the + // configuration for GPIO pin 7. +#define GPIO_GPIO_PCTL_PMC7_S 28 +#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 6 This field controls the + // configuration for GPIO pin 6. +#define GPIO_GPIO_PCTL_PMC6_S 24 +#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 5 This field controls the + // configuration for GPIO pin 5. +#define GPIO_GPIO_PCTL_PMC5_S 20 +#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 4 This field controls the + // configuration for GPIO pin 4. +#define GPIO_GPIO_PCTL_PMC4_S 16 +#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 43 This field controls + // the configuration for GPIO pin 3. +#define GPIO_GPIO_PCTL_PMC3_S 12 +#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 1 This field controls the + // configuration for GPIO pin 1. +#define GPIO_GPIO_PCTL_PMC1_S 8 +#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 2 This field controls the + // configuration for GPIO pin 2. +#define GPIO_GPIO_PCTL_PMC2_S 4 +#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 0 This field controls the + // configuration for GPIO pin 0. +#define GPIO_GPIO_PCTL_PMC0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_ADCCTL register. +// +//****************************************************************************** +#define GPIO_GPIO_ADCCTL_ADCEN_M \ + 0x000000FF // This register is not used in + // cc3xx. ADC trigger via GPIO is + // not supported. ADC Trigger Enable + // Value Description 1 The + // corresponding pin is used to + // trigger the ADC. 0 The + // corresponding pin is not used to + // trigger the ADC. + +#define GPIO_GPIO_ADCCTL_ADCEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_DMACTL register. +// +//****************************************************************************** +#define GPIO_GPIO_DMACTL_DMAEN_M \ + 0x000000FF // This register is not used in the + // cc3xx. Alternate register to + // support this feature is coded in + // the APPS_NWP_CMN space. refer + // register as offset 0x400F70D8 + // ?DMA Trigger Enable Value + // Description 1 The corresponding + // pin is used to trigger the ?DMA. + // 0 The corresponding pin is not + // used to trigger the ?DMA. + +#define GPIO_GPIO_DMACTL_DMAEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_SI register. +// +//****************************************************************************** +#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value + // Description 1 Each pin has its + // own interrupt vector. 0 All port + // pin interrupts are OR'ed together + // to produce a summary interrupt. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID4 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID4_PID4_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [7:0] + +#define GPIO_GPIO_PERIPHID4_PID4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID5 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID5_PID5_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [15:8] + +#define GPIO_GPIO_PERIPHID5_PID5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID6 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID6_PID6_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [23:16] + +#define GPIO_GPIO_PERIPHID6_PID6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID7 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID7_PID7_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [31:24] + +#define GPIO_GPIO_PERIPHID7_PID7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID0 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID0_PID0_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [7:0] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID0_PID0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID1 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID1_PID1_M \ + 0x000000FF // GPIO Peripheral ID Register + // [15:8] Can be used by software to + // identify the presence of this + // peripheral. + +#define GPIO_GPIO_PERIPHID1_PID1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID2 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID2_PID2_M \ + 0x000000FF // This register is not used in + // CC3XX.v GPIO Peripheral ID + // Register [23:16] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID2_PID2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID3 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID3_PID3_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [31:24] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID3_PID3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID0 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID0_CID0_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [7:0] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID0_CID0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID1 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID1_CID1_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [15:8] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID1_CID1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID2 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID2_CID2_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [23:16] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID2_CID2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID3 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID3_CID3_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [31:24] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID3_CID3_S 0 + + + +#endif // __HW_GPIO_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gprcm.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gprcm.h new file mode 100644 index 0000000000..43628f4aba --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gprcm.h @@ -0,0 +1,3322 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_GPRCM_H__ +#define __HW_GPRCM_H__ + +//***************************************************************************** +// +// The following are defines for the GPRCM register offsets. +// +//***************************************************************************** +#define GPRCM_O_APPS_SOFT_RESET 0x00000000 +#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \ + 0x00000004 + +#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \ + 0x00000008 + +#define GPRCM_O_APPS_RESET_CAUSE \ + 0x0000000C + +#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \ + 0x00000010 + +#define GPRCM_O_APPS_SRAM_DSLP_CFG \ + 0x00000018 + +#define GPRCM_O_APPS_SRAM_LPDS_CFG \ + 0x0000001C + +#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \ + 0x00000020 + +#define GPRCM_O_TOP_DIE_ENABLE 0x00000100 +#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \ + 0x00000104 + +#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \ + 0x00000108 + +#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C +#define GPRCM_O_APPS_GPIO_WAKE_CONF \ + 0x00000110 + +#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \ + 0x00000114 + +#define GPRCM_O_MEM_HCLK_DIV_CFG \ + 0x00000118 + +#define GPRCM_O_MEM_SYSCLK_DIV_CFG \ + 0x0000011C + +#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \ + 0x00000120 + +#define GPRCM_O_NWP_SOFT_RESET 0x00000400 +#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \ + 0x00000404 + +#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \ + 0x00000408 + +#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C +#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \ + 0x00000410 + +#define GPRCM_O_NWP_SRAM_DSLP_CFG \ + 0x00000418 + +#define GPRCM_O_NWP_SRAM_LPDS_CFG \ + 0x0000041C + +#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \ + 0x00000420 + +#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \ + 0x00000424 + +#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \ + 0x00000428 + +#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \ + 0x0000042C + +#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \ + 0x00000430 + +#define GPRCM_O_NWP_GPIO_WAKE_CONF \ + 0x00000434 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \ + 0x00000438 + +#define GPRCM_O_GPRCM_DIEID_READ_REG5 \ + 0x00000448 + +#define GPRCM_O_GPRCM_DIEID_READ_REG6 \ + 0x0000044C + +#define GPRCM_O_REF_FSM_CFG0 0x00000800 +#define GPRCM_O_REF_FSM_CFG1 0x00000804 +#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \ + 0x00000808 + +#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \ + 0x0000080C + +#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \ + 0x00000810 + +#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \ + 0x00000814 + +#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \ + 0x00000818 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \ + 0x0000081C + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \ + 0x00000820 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \ + 0x00000824 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \ + 0x00000828 + +#define GPRCM_O_SPARE_RW0 0x0000082C +#define GPRCM_O_SPARE_RW1 0x00000830 +#define GPRCM_O_APLLMCS_MCU_OVERRIDES \ + 0x00000834 + +#define GPRCM_O_SYSCLK_SWITCH_STATUS \ + 0x00000838 + +#define GPRCM_O_REF_LDO_CONTROLS \ + 0x0000083C + +#define GPRCM_O_REF_RTRIM_CONTROL \ + 0x00000840 + +#define GPRCM_O_REF_SLICER_CONTROLS0 \ + 0x00000844 + +#define GPRCM_O_REF_SLICER_CONTROLS1 \ + 0x00000848 + +#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \ + 0x0000084C + +#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \ + 0x00000850 + +#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \ + 0x00000854 + +#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \ + 0x00000858 + +#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \ + 0x0000085C + +#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \ + 0x00000860 + +#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \ + 0x00000864 + +#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868 +#define GPRCM_O_MEMSS_PWR_PS 0x0000086C +#define GPRCM_O_REF_FSM_DEBUG 0x00000870 +#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \ + 0x00000874 + +#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \ + 0x00000878 + +#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \ + 0x0000087C + +#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \ + 0x00000880 + +#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \ + 0x00000884 + +#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \ + 0x00000888 + +#define GPRCM_O_MEM_REF_FSM_CFG2 \ + 0x0000088C + +#define GPRCM_O_TESTCTRL_POWER_CTRL \ + 0x00000C10 + +#define GPRCM_O_SSDIO_POWER_CTRL \ + 0x00000C14 + +#define GPRCM_O_MCSPI_N1_POWER_CTRL \ + 0x00000C18 + +#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C +#define GPRCM_O_WL_SDIO_POWER_CTRL \ + 0x00000C20 + +#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \ + 0x00000C24 + +#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \ + 0x00000C28 + +#define GPRCM_O_APPS_SECURE_INIT_DONE \ + 0x00000C30 + +#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \ + 0x00000C34 + +#define GPRCM_O_EN_APPS_REBOOT 0x00000C38 +#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \ + 0x00000C3C + +#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \ + 0x00000C40 + +#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \ + 0x00000C44 + +#define GPRCM_O_NWP_PWR_STATE 0x00000C48 +#define GPRCM_O_APPS_PWR_STATE 0x00000C4C +#define GPRCM_O_MCU_PWR_STATE 0x00000C50 +#define GPRCM_O_WTOP_PM_PS 0x00000C54 +#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \ + 0x00000C58 + +#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \ + 0x00000C5C + +#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \ + 0x00000C60 + +#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \ + 0x00000C64 + +#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \ + 0x00000C68 + +#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \ + 0x00000C6C + +#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \ + 0x00000C70 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \ + 0x00000C78 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \ + 0x00000C7C + +#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \ + 0x00000C80 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \ + 0x00000C84 + +#define GPRCM_O_WTOP_MEM_RET_CFG \ + 0x00000C88 + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \ + 0x00000C8C + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \ + 0x00000C90 + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \ + 0x00000C94 + +#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \ + 0x00000C98 + +#define GPRCM_O_DCDC_CLK_GEN_CONFIG \ + 0x00000C9C + +#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \ + 0x00000CA0 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \ + 0x00000CA4 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \ + 0x00000CA8 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \ + 0x00000CAC + +#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \ + 0x00000CB0 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \ + 0x00000CB4 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \ + 0x00000CB8 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \ + 0x00000CBC + +#define GPRCM_O_GPRCM_DIEID_READ_REG0 \ + 0x00000CC0 + +#define GPRCM_O_GPRCM_DIEID_READ_REG1 \ + 0x00000CC4 + +#define GPRCM_O_GPRCM_DIEID_READ_REG2 \ + 0x00000CC8 + +#define GPRCM_O_GPRCM_DIEID_READ_REG3 \ + 0x00000CCC + +#define GPRCM_O_GPRCM_DIEID_READ_REG4 \ + 0x00000CD0 + +#define GPRCM_O_APPS_SS_OVERRIDES \ + 0x00000CD4 + +#define GPRCM_O_NWP_SS_OVERRIDES \ + 0x00000CD8 + +#define GPRCM_O_SHARED_SS_OVERRIDES \ + 0x00000CDC + +#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \ + 0x00000CE0 + +#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \ + 0x00000CE4 + +#define GPRCM_O_MCU_PSCON_OVERRIDES \ + 0x00000CE8 + +#define GPRCM_O_WTOP_PSCON_OVERRIDES \ + 0x00000CEC + +#define GPRCM_O_WELP_PSCON_OVERRIDES \ + 0x00000CF0 + +#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \ + 0x00000CF4 + +#define GPRCM_O_MCSPI_PSCON_OVERRIDES \ + 0x00000CF8 + +#define GPRCM_O_SSDIO_PSCON_OVERRIDES \ + 0x00000CFC + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \ + 0x00000002 // Soft-reset1 for APPS : Cortex + // sysrstn is asserted and in + // addition to that the associated + // APPS Peripherals are also reset. + // This is an auto-clear bit. + +#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \ + 0x00000001 // Soft-reset0 for APPS : Only + // sys-resetn for Cortex will be + // asserted. This is an auto-clear + // bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKEUP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \ + 0x000000FF // Mask for LPDS Wakeup interrupt : + // [7] - Host IRQ from NWP [6] - + // NWP_LPDS_Wake_irq (TRUE_LPDS) [5] + // - NWP Wake-request to APPS [4] - + // GPIO [3:1] - Reserved [0] - LPDS + // Wakeup-timer + +#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKEUP_SRC register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \ + 0x000000FF // Indicates the cause for wakeup + // from LPDS : [7] - Host IRQ from + // NWP [6] - NWP_LPDS_Wake_irq + // (TRUE_LPDS) [5] - NWP + // Wake-request to APPS [4] - GPIO + // [3:1] - Reserved [0] - LPDS + // Wakeup-timer + +#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_RESET_CAUSE register. +// +//****************************************************************************** +#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \ + 0x000000FF // Indicates the reset cause for + // APPS : "0000" - Wake from HIB/OFF + // mode; "0001" - Wake from LPDS ; + // "0010" - Reserved ; "0011" - + // Soft-reset0 (Only APPS + // Cortex-sysrstn is asserted); + // "0100" - Soft-reset1 (APPS + // Cortex-sysrstn and APPS + // peripherals are reset); "0101" - + // WDOG0 (APPS Cortex-sysrstn and + // APPS peripherals are reset); + // "0110" - MCU Soft-reset (APPS + + // NWP Cortex-sysrstn + Peripherals + // are reset); "0111" - Secure Init + // done (Indication that reset has + // happened after DevInit); "1000" - + // Dev Mode Patch Init done (During + // development mode, patch + // downloading and Cortex + // re-vectoring is completed) + +#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \ + 0xFFFFFFFF // OPP Request Configuration + // (Number of slow-clk cycles) for + // LPDS Wake-timer : This + // configuration implies the RTC + // time-stamp, which must be few + // slow-clks prior to + // APPS_LPDS_WAKETIME_WAKE_CFG, such + // that by the time actual wakeup is + // given, OPP is already switched to + // ACTIVE (RUN). + +#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SRAM_DSLP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \ + 0x000FFFFF // Configuration of APPS Memories + // during Deep-sleep : 0 - SRAMs are + // OFF ; 1 - SRAMs are Retained. + // APPS SRAM Cluster information : + // [0] - 1st column in MEMSS + // (Applicable only when owned by + // APPS); [1] - 2nd column in MEMSS + // (Applicable only when owned by + // APPS); [2] - 3rd column in MEMSS + // (Applicable only when owned by + // APPS) ; [3] - 4th column in MEMSS + // (Applicable only when owned by + // APPS) ; [16] - MCU-PD - Apps + // cluster 0 (TBD); [19:18] - + // Reserved. + +#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SRAM_LPDS_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \ + 0x000FFFFF // Configuration of APPS Memories + // during LPDS : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. APPS SRAM + // Cluster information : [0] - 1st + // column in MEMSS (Applicable only + // when owned by APPS); [1] - 2nd + // column in MEMSS (Applicable only + // when owned by APPS); [2] - 3rd + // column in MEMSS (Applicable only + // when owned by APPS) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by APPS) ; [16] - + // MCU-PD - Apps cluster 0 (TBD); + // [19:18] - Reserved. + +#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \ + 0xFFFFFFFF // Configuration (in no of + // slow_clks) which says when the + // actual wakeup request for + // removing the PD-reset be given. + +#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_ENABLE register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \ + 0x00001000 + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \ + 0x00000F00 + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8 +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \ + 0x00000002 // 1 - Top-die is enabled ; + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \ + 0x00000001 // 1 - Enable the top-die ; 0 - + // Disable the top-die + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \ + 0xF0000000 // Configuration (in slow_clks) for + // number of clks between + // Flash-3p3-rstn to D2D POR Resetn. + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28 +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \ + 0x00FF0000 // Configuration (in slow_clks) for + // number of clks between Top-die + // Switch-Enable and Top-die Flash + // 3p3 Reset removal + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16 +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \ + 0x000000FF // Configuration (in slow_clks) for + // number of clks between D2D POR + // Reset removal and bottom die FMC + // reset removal + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_GLOBAL_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \ + 0x00000001 // 1 - Assert the global reset for + // MCU (APPS + NWP) ; Asserts both + // Cortex sysrstn and its + // peripherals 0 - Deassert the + // global reset for MCU (APPS + NWP) + // ; Asserts both Cortex sysrstn and + // its peripherals Note : Reset for + // shared peripherals is not + // affected here. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_ADC_CLK_CONFIG register. +// +//****************************************************************************** +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \ + 0x000007C0 // Configuration (in number of 38.4 + // MHz clks) for the OFF-Time in + // generation of ADC_CLK + +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6 +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \ + 0x0000003E // Configuration (in number of 38.4 + // MHz clks) for the ON-Time in + // generation of ADC_CLK + +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1 +#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \ + 0x00000001 // 1 - Enable the ADC_CLK ; 0 - + // Disable the ADC_CLK + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \ + 0x00000003 // "00" - Wake on Level0 on + // selected GPIO pin (GPIO is + // selected inside the HIB3p3 + // module); "01" - Wakeup on + // fall-edge of GPIO pin. + +#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register. +// +//****************************************************************************** +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \ + 0xFFFFFFFE + +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1 +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \ + 0x00000001 // 1 - Override the secure-mode + // done for booting up NWP (Wakeup + // NWP on its event independent of + // CM4 state) ; 0 - Donot override + // the secure-mode done for NWP boot + // (NWP must be enabled by CM4 only) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_HCLK_DIV_CFG register. +// +//****************************************************************************** +#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \ + 0x00000007 // Division configuration for + // HCLKDIVOUT : "000" - Divide by 1 + // ; "001" - Divide by 2 ; "010" - + // Divide by 3 ; "011" - Divide by 4 + // ; "100" - Divide by 5 ; "101" - + // Divide by 6 ; "110" - Divide by 7 + // ; "111" - Divide by 8 + +#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SYSCLK_DIV_CFG register. +// +//****************************************************************************** +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \ + 0x00000038 + +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3 +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \ + 0x00000007 + +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_LOCK_TIME_CONF register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \ + 0x0000FF00 + +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8 +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \ + 0x000000FF + +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \ + 0x00000002 // Soft-reset1 for NWP - Cortex + // sysrstn and NWP associated + // peripherals are - This is an + // auto-clr bit. + +#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \ + 0x00000001 // Soft-reset0 for NWP - Only + // Cortex-sysrstn is asserted - This + // is an auto-clear bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKEUP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \ + 0x000000FF // Mask for LPDS Wakeup interrupt : + // 7 - WLAN Host Interrupt ; 6 - + // WLAN to NWP Wake request ; 5 - + // APPS to NWP Wake request; 4 - + // GPIO Wakeup ; 3 - Autonomous UART + // Wakeup ; 2 - SSDIO Wakeup ; 1 - + // Autonomous SPI Wakeup ; 0 - LPDS + // Wakeup-timer + +#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKEUP_SRC register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \ + 0x000000FF // Indicates the cause for NWP + // LPDS-Wakeup : 7 - WLAN Host + // Interrupt ; 6 - WLAN to NWP Wake + // request ; 5 - APPS to NWP Wake + // request; 4 - GPIO Wakeup ; 3 - + // Autonomous UART Wakeup ; 2 - + // SSDIO Wakeup ; 1 - Autonomous SPI + // Wakeup ; 0 - LPDS Wakeup-timer + +#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_RESET_CAUSE register. +// +//****************************************************************************** +#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \ + 0x000000FF // Indicates the reset cause for + // NWP : "0000" - Wake from HIB/OFF + // mode; "0001" - Wake from LPDS ; + // "0010" - Reserved ; "0011" - + // Soft-reset0 (Only NWP + // Cortex-sysrstn is asserted); + // "0100" - Soft-reset1 (NWP + // Cortex-sysrstn and NWP + // peripherals are reset); "0101" - + // WDOG0 (NWP Cortex-sysrstn and NWP + // peripherals are reset); "0110" - + // MCU Soft-reset (APPS + NWP + // Cortex-sysrstn + Peripherals are + // reset); "0111" - SSDIO Function2 + // reset (Only Cortex-sysrstn is + // asserted) ; "1000" - Reset due to + // WDOG of APPS (NWP Cortex-sysrstn + // and NWP peripherals are reset); + +#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \ + 0xFFFFFFFF // OPP Request Configuration + // (Number of slow-clk cycles) for + // LPDS Wake-timer + +#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SRAM_DSLP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \ + 0x000FFFFF // Configuration of NWP Memories + // during DSLP : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. NWP SRAM + // Cluster information : [2] - 3rd + // column in MEMSS (Applicable only + // when owned by NWP) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by NWP) ; [4] - 5th + // column in MEMSS (Applicable only + // when owned by NWP) ; [5] - 6th + // column in MEMSS (Applicable only + // when owned by NWP) ; [6] - 7th + // column in MEMSS (Applicable only + // when owned by NWP) ; [7] - 8th + // column in MEMSS (Applicable only + // when owned by NWP) ; [8] - 9th + // column in MEMSS (Applicable only + // when owned by NWP) ; [9] - 10th + // column in MEMSS (Applicable only + // when owned by NWP) ; [10] - 11th + // column in MEMSS (Applicable only + // when owned by NWP) ; [11] - 12th + // column in MEMSS (Applicable only + // when owned by NWP) ; [12] - 13th + // column in MEMSS (Applicable only + // when owned by NWP) ; [13] - 14th + // column in MEMSS (Applicable only + // when owned by NWP) ; [14] - 15th + // column in MEMSS (Applicable only + // when owned by NWP) ; [19:18] - + // Reserved. + +#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SRAM_LPDS_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \ + 0x000FFFFF // Configuration of NWP Memories + // during LPDS : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. NWP SRAM + // Cluster information : [2] - 3rd + // column in MEMSS (Applicable only + // when owned by NWP) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by NWP) ; [4] - 5th + // column in MEMSS (Applicable only + // when owned by NWP) ; [5] - 6th + // column in MEMSS (Applicable only + // when owned by NWP) ; [6] - 7th + // column in MEMSS (Applicable only + // when owned by NWP) ; [7] - 8th + // column in MEMSS (Applicable only + // when owned by NWP) ; [8] - 9th + // column in MEMSS (Applicable only + // when owned by NWP) ; [9] - 10th + // column in MEMSS (Applicable only + // when owned by NWP) ; [10] - 11th + // column in MEMSS (Applicable only + // when owned by NWP) ; [11] - 12th + // column in MEMSS (Applicable only + // when owned by NWP) ; [12] - 13th + // column in MEMSS (Applicable only + // when owned by NWP) ; [13] - 14th + // column in MEMSS (Applicable only + // when owned by NWP) ; [14] - 15th + // column in MEMSS (Applicable only + // when owned by NWP) ; [19:18] - + // Reserved. + +#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \ + 0xFFFFFFFF // Wake time configuration (no of + // slow clks) for NWP wake from + // LPDS. + +#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register. +// +//****************************************************************************** +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \ + 0xFFFE0000 + +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17 +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \ + 0x00010000 // 0 - APPS is selected as host for + // Autonms SPI ; 1 - External host + // is selected as host for Autonms + // SPI + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register. +// +//****************************************************************************** +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \ + 0x00010000 + +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \ + 0x00000002 // When 1 => IDLE-mode is + // acknowledged by the SPI-IP. (This + // is for MCSPI_N1) + +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \ + 0x00000001 // When 1 => Request for IDLE-mode + // for autonomous SPI. (This is for + // MCSPI_N1) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register. +// +//****************************************************************************** +#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \ + 0x00000001 // 1 - Request for waking up NWP + // from any of its low-power modes + // (SLP/DSLP/LPDS) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register. +// +//****************************************************************************** +#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \ + 0x00000001 // 1 - Request for wakinp up WLAN + // from its ELP Mode (This gets + // triggered to ELP-logic of WLAN) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \ + 0x00000003 // "00" - Wakeup on level0 of the + // selected GPIO (GPIO gets selected + // inside HIB3P3-module); "01" - + // Wakeup on fall-edge of selected + // GPIO. + +#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG12 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \ + 0x0000FFFF // This corrsponds to ROW_32 + // [31:16] of the FUSEFARM. SPARE + +#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG5 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \ + 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM + // : [5:0] - ADC OFFSET ; [13:6] - + // TEMP_SENSE ; [14:14] - DFT_GSG ; + // [15:15] - FMC_DISABLE ; [31:16] - + // WLAN_MAC ID + +#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG6 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \ + 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM + // : [31:0] : WLAN MAC ID + +#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_CFG0 register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \ + 0x00FF0000 // ANA-BGAP Settling time (In + // number of slow_clks) + +#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16 +#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \ + 0x0000FF00 // Slicer LDO settling time (In + // number of slow clks) + +#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8 +#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \ + 0x000000FF // Dig-buffer settling time (In + // number of slow clks) + +#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_CFG1 register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \ + 0xFF000000 // XTAL settling time (In number of + // slow clks) + +#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24 +#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \ + 0x00FF0000 // LV Slicer settling time + +#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16 +#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \ + 0x0000FF00 // HV Slicer Pull-down settling + // time + +#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8 +#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \ + 0x000000FF // HV Slicer settling time + +#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \ + 0x00007F00 // Configuration for WLAN APLLMCS - + // N[6:0], if the XTAL frequency is + // 40 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8 +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \ + 0x000000FF // Configuration for WLAN APLLMCS - + // M[7:0], if the XTAL frequency is + // 40 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \ + 0x00000010 // Configuration for WLAN APLLMCS - + // if the XTAL frequency if 40 MHz + // (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \ + 0x00000008 // Configuration for WLAN APLLMCS - + // Sel96, if the XTAL frequency is + // 40 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \ + 0x00000007 // Configuration for WLAN APLLMCS - + // Selinpfreq, if the XTAL frequency + // is 40 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \ + 0x00007F00 // Configuration for WLAN APLLMCS - + // N[6:0], if the XTAL frequency is + // 26 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8 +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \ + 0x000000FF // Configuration for WLAN APLLMCS - + // M[7:0], if the XTAL frequency is + // 26 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \ + 0x00000010 // Configuration for WLAN APLLMCS - + // if the XTAL frequency if 26 MHz + // (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \ + 0x00000008 // Configuration for WLAN APLLMCS - + // Sel96, if the XTAL frequency is + // 26 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \ + 0x00000007 // Configuration for WLAN APLLMCS - + // Selinpfreq, if the XTAL frequency + // is 26 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \ + 0x00080000 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \ + 0x00070000 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16 +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \ + 0x00000700 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8 +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \ + 0x00000020 // Override control for + // WLAN_APLLMCS_M[8]. When set to1, + // M[8] will be selected by bit [3]. + // (Else controlled from WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \ + 0x00000010 // Override for WLAN_APLLMCS_M[8]. + // Applicable only when bit [4] is + // set to 1. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \ + 0x00000004 // Override control for + // WLAN_APLLMCS_N[8:7]. When set + // to1, N[8:7] will be selected by + // bits [2:1]. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \ + 0x00000003 // Override value for + // WLAN_APLLMCS_N[8:7] bits. + // Applicable only when bit [1] is + // set to 1. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \ + 0x38000000 + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \ + 0x07000000 + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \ + 0x007F0000 // Configuration for MCU-APLLMCS : + // N during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \ + 0x0000FF00 // Configuration for MCU-APLLMCS : + // M during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // M[8] during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \ + 0x00000003 // Configuration for MCU-APLLMCS : + // N[8:7] during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // HISPEED during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \ + 0x00000008 // Configuration for MCU-APLLMCS : + // SEL96 during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \ + 0x00000007 // Configuration for MCU-APLLMCS : + // SELINPFREQ during RUN mode. + // Selected if the XTAL frequency is + // 38.4 MHz (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \ + 0x007F0000 // Configuration for MCU-APLLMCS : + // N during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \ + 0x0000FF00 // Configuration for MCU-APLLMCS : + // M during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // M[8] during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \ + 0x00000003 // Configuration for MCU-APLLMCS : + // N[8:7] during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // HISPEED during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \ + 0x00000008 // Configuration for MCU-APLLMCS : + // SEL96 during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \ + 0x00000007 // Configuration for MCU-APLLMCS : + // SELINPFREQ during RUN mode. + // Selected if the XTAL frequency is + // 26 MHz (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \ + 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 - + // APLLMCS_MCU is not locked + +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \ + 0x00000200 // Override for APLLMCS_MCU Enable. + // Applicable if bit [8] is set + +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \ + 0x00000100 // 1 - Enable for APLLMCS_MCU comes + // from bit [9]. 0 - Enable for + // APLLMCS_MCU comes from FSM. + +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \ + 0x00000006 // Override for sysclk src + // (applicable only if bit [0] is + // set to 1. "00"- SLOW_CLK "01"- + // XTAL_CLK "10"- PLL_CLK + +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1 +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \ + 0x00000001 // 1 - Sysclk src is selected from + // bits [2:1] of this register. 0 - + // Sysclk src is selected from FSM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SYSCLK_SWITCH_STATUS register. +// +//****************************************************************************** +#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \ + 0x00000001 // 1 - Sysclk switching is + // complete. 0 - Sysclk switching is + // in progress. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_LDO_CONTROLS register. +// +//****************************************************************************** +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \ + 0x00010000 // 1 - Enable for REF_LDO comes + // from bit [0] of this register ; 0 + // - Enable for REF_LDO comes from + // the FSM. Note : Final REF_LDO_EN + // reaches on the port + // TOP_PM_REG2[0] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \ + 0x0000C000 // Spare bits for REF_CTRL_FSM. + // Reaches directly on port + // TOP_PM_REG2[15:14] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14 +#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \ + 0x00003800 // REF TLOAD Enable. Reaches + // directly on port + // TOP_PM_REG2[13:11] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11 +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \ + 0x00000700 // REF_LDO Test-mux control. + // Reaches directly on port + // TOP_PM_REG2[10:8] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8 +#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \ + 0x000000C0 // REF BW Control. Reaches directly + // on port TOP_PM_REG2[7:6] of + // gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6 +#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \ + 0x0000003C // REF VTRIM Control. Reaches + // directly on port TOP_PM_REG2[5:2] + // of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2 +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \ + 0x00000002 // REF LDO Bypass Enable. Reaches + // directly on port TOP_PM_REG2[1] + // of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \ + 0x00000001 // Override for REF_LDO Enable. + // Applicable only if bit [16] of + // this register is set. Note : + // Final REF_LDO_EN reaches on the + // port TOP_PM_REG2[0] of gprcm. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_RTRIM_CONTROL register. +// +//****************************************************************************** +#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \ + 0x18000000 // This is [5:4] bits of + // TOP_PM_REG0 + +#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27 +#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \ + 0x07FF0000 // This is [15:5] bits of + // TOP_CLKM_REG0 + +#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16 +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \ + 0x00000100 // 1 - CLKM_RTRIM comes for + // bits[4:0] of this register. 0 - + // CLKM_RTRIM comes from Efuse + // (after efuse_done = 1). + +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \ + 0x0000001F // CLKM_TRIM Override. Applicable + // when efuse_done = 0 or bit[8] is + // set to 1. + +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_SLICER_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \ + 0x00200000 // 1 - EN_DIG_BUF_TOP comes from + // bit [14] of this register. 0 - + // EN_DIG_BUF_TOP comes from the + // FSM. Note : Final EN_DIG_BUF_WLAN + // reaches on TOP_CLKM_REG1_IN[14] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \ + 0x00100000 // 1 - EN_DIG_BUF_TOP comes from + // bit [15] of this register. 0 - + // EN_DIG_BUF_TOP comes from the + // FSM. Note : Final EN_DIG_BUF_TOP + // reaches on TOP_CLKM_REG1_IN[15] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \ + 0x00080000 // 1 - EN_XTAL comes from bit [3] + // of this register. 0 - EN_XTAL + // comes from FSM. Note : Final + // XTAL_EN reaches on + // TOP_CLKM_REG1_IN[3] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \ + 0x00040000 // 1 - Enable HV Slicer comes from + // bit [2] of this register. 0 - + // Enable HV Slicer comes from FSM. + // Note : Final HV_SLICER_EN reaches + // on port TOP_CLKM_REG1_IN[1] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \ + 0x00020000 // 1 - Enable LV Slicer comes from + // bit[1] of this register. 0 - + // Enable LV Slicer comes from FSM. + // Note : final LV_SLICER_EN reaches + // on port TOP_CLKM_REG1_IN[2] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \ + 0x00010000 // 1 - Enable HV Pull-down comes + // from bit[0] of this register. 0 - + // Enable HV Pull-down comes from + // FSM. Note : Final HV_PULL_DOWN + // reaches on port + // TOP_CLKM_REG1_IN[0] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \ + 0x00008000 // Override for EN_DIG_BUF_TOP. + // Applicable if bit[20] is set to + // 1. Note : Final EN_DIG_BUF_TOP + // reaches on TOP_CLKM_REG1_IN[15] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \ + 0x00004000 // Override for EN_DIG_BUF_WLAN. + // Applicable if bit[19] is set to + // 1. Note : Final EN_DIG_BUF_WLAN + // reaches on TOP_CLKM_REG1_IN[14] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \ + 0x00002000 // CLKOUT Flip Enable. Reaches on + // bit[13] of TOP_CLKM_REG1_IN[13] + // port of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \ + 0x00001000 // Enable divide2 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[12] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \ + 0x00000800 // Enable divide3 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[11] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \ + 0x00000400 // Enable divide4 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[10] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \ + 0x000003C0 // CM Test-mux select. Reaches on + // TOP_CLMM_REG1_IN[9:6] port of + // gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6 +#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \ + 0x00000030 // Slicer spare0 control. Reaches + // on TOP_CLKM_REG1_IN[5:4] port of + // gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4 +#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \ + 0x00000008 // Enable XTAL override. Reaches on + // TOP_CLKM_REG1_IN[3] port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \ + 0x00000004 // Enable HV Slicer override. + // Reaches on TOP_CLKM_REG1_IN[1] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \ + 0x00000002 // Enable LV Slicer override. + // Reaches on TOP_CLKM_REG1_IN[2] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \ + 0x00000001 // Enable HV Pull-down override. + // Reaches on TOP_CLKM_REG1_IN[0] + // port of gprcm + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_SLICER_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \ + 0x0000FC00 // Slicer spare1. Reaches on port + // TOP_CLKM_REG2_IN[15:10] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10 +#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \ + 0x000003F0 // XOSC Trim. Reaches on port + // TOP_CLKM_REG2_IN[9:4] of gprcm + +#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4 +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \ + 0x00000008 // Slicer ITRIM Toggle. Reaches on + // port TOP_CLKM_REG2_IN[3] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \ + 0x00000007 // LV Slicer trim. Reaches on port + // TOP_CLKM_REG2_IN[2:0] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \ + 0xFF800000 + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \ + 0x00400000 // 1 - REF_MAG_TRIM comes from + // bit[4:0] of register + // REF_ANA_BGAP_CONTROLS1 [Addr : + // 0x0850]; 0 - REF_MAG_TRIM comes + // from efuse (After efc_done = 1). + // Note : Final REF_MAG_TRIM reaches + // on port TOP_PM_REG1[4:0] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \ + 0x00200000 // 1 - REF_V2I_TRIM comes from + // bit[9:6] of this register ; 0 - + // REF_V2I_TRIM comes from efuse + // (After efc_done = 1). Note : + // Final REF_V2I_TRIM reaches on + // port TOP_PM_REG0[9:6] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \ + 0x00100000 // 1 - REF_TEMP_TRIM comes from + // bit[15:10] of this register ; 0 - + // REF_TEMP_TRIM comes from efuse + // (After efc_done = 1). Note : + // Final REF_TEMP_TRIM reaches on + // port TOP_PM_REG0[15:10] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \ + 0x00080000 // 1 - REF_STARTUP_EN comes from + // bit [3] of this register ; 0 - + // REF_STARTUP_EN comes from FSM. + // Note : Final REF_STARTUP_EN + // reaches on port TOP_PM_REG0[3] of + // gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \ + 0x00040000 // 1 - REF_V2I_EN comes from bit + // [2] of this register ; 0 - + // REF_V2I_EN comes from FSM. Note : + // Final REF_V2I_EN reaches on port + // TOP_PM_REG0[2] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \ + 0x00020000 // 1 - REF_FC_EN comes from bit [1] + // of this register ; 0 - REF_FC_EN + // comes from FSM. Note : Final + // REF_FC_EN reaches on port + // TOP_PM_REG0[1] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \ + 0x00010000 // 1 - REF_BGAP_EN comes from bit + // [0] of this register ; 0 - + // REF_BGAP_EN comes from FSM. Note + // : Final REF_BGAP_EN reaches on + // port TOP_PM_REG0[0] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \ + 0x0000FC00 // REF_TEMP_TRIM override. + // Applicable when bit [20] of this + // register set to 1. (or efc_done = + // 0) Note : Final REF_TEMP_TRIM + // reaches on port + // TOP_PM_REG0[15:10] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \ + 0x000003C0 // REF_V2I_TRIM Override. + // Applicable when bit [21] of this + // register set to 1 . (of efc_done + // = 0) Note : Final REF_V2I_TRIM + // reaches on port TOP_PM_REG0[9:6] + // of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \ + 0x00000030 + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \ + 0x00000008 // REF_STARTUP_EN override. + // Applicable when bit [19] of this + // register is set to 1. Note : + // Final REF_STARTUP_EN reaches on + // port TOP_PM_REG0[3] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \ + 0x00000004 // REF_V2I_EN override. Applicable + // when bit [21] of this register is + // set to 1. Note : Final REF_V2I_EN + // reaches on port TOP_PM_REG0[2] of + // gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \ + 0x00000002 // REF_FC_EN override. Applicable + // when bit [17] of this register is + // set to 1. Note : Final REF_FC_EN + // reaches on port TOP_PM_REG0[1] of + // gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \ + 0x00000001 // REF_BGAP_EN override. Applicable + // when bit [16] of this register + // set to 1. Note : Final + // REF_BGAP_EN reaches on port + // TOP_PM_REG0[0] of gprcm. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \ + 0xFFFF0000 + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \ + 0x0000C000 // REF_BGAP_SPARE. Reaches on port + // TOP_PM_REG1[15:14] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \ + 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on + // port TOP_PM_REG1[13:9] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \ + 0x000001E0 // REF_FILT_TRIM. Reaches on port + // TOP_PM_REG1[8:5] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \ + 0x0000001F // REF_MAG_TRIM Override. + // Applicable when bit[22] of + // REF_ANA_BGAP_CONTROLS0 [0x084C] + // set to 1 (of efc_done = 0). Note + // : Final REF_MAG_TRIM reaches on + // port TOP_PM_REG1[4:0] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \ + 0xFFFF0000 + +#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16 +#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \ + 0x0000FFFF // Spare control. Reaches on + // TOP_PM_REG3 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \ + 0xFFFF0000 // Spare control. Reaches on + // TOP_CLKM_REG3 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16 +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \ + 0x0000FFFF // Spare control. Reaches on + // TOP_CLKM_REG4 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \ + 0xFFFF0000 + +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16 +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \ + 0x0000FFFF + +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6 +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \ + 0x00000020 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \ + 0x00000010 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \ + 0x00000008 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \ + 0x00000004 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \ + 0x00000002 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_PLL_REF_LOCK_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3 +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \ + 0x00000004 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \ + 0x00000002 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PSCON_DEBUG register. +// +//****************************************************************************** +#define GPRCM_MCU_PSCON_DEBUG_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6 +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \ + 0x00000038 // MCU_PSCON_RTC_ON = "0000"; + // MCU_PSCON_RTC_OFF = "0001"; + // MCU_PSCON_RTC_RET = "0010"; + // MCU_PSCON_RTC_OFF_TO_ON = "0011"; + // MCU_PSCON_RTC_RET_TO_ON = "0100"; + // MCU_PSCON_RTC_ON_TO_RET = "0101"; + // MCU_PSCON_RTC_ON_TO_OFF = "0110"; + // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP + // = "0111"; + // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP + // = "1000"; + +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3 +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \ + 0x00000007 + +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PWR_PS register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PWR_PS_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_MEMSS_PWR_PS_reserved_S 3 +#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \ + 0x00000007 // MEMSS_PM_SLEEP = "000"; + // MEMSS_PM_WAIT_OPP = "010"; + // MEMSS_PM_ACTIVE = "011"; + // MEMSS_PM_SLEEP_TO_ACTIVE = "100"; + // MEMSS_PM_ACTIVE_TO_SLEEP = "101"; + +#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_DEBUG register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_DEBUG_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_REF_FSM_DEBUG_reserved_S 6 +#define GPRCM_REF_FSM_DEBUG_fref_mode_M \ + 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11 + // - XTAL Mode + +#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4 +#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \ + 0x0000000F // constant FREF_CLK_OFF = "00000"; + // constant FREF_EN_BGAP = "00001"; + // constant FREF_EN_LDO = "00010"; + // constant FREF_EN_SLI_HV = + // "00011"; constant + // FREF_EN_SLI_HV_PD = "00100"; + // constant FREF_EN_DIG_BUF = + // "00101"; constant FREF_EN_OSC = + // "00110"; constant FREF_EN_SLI_LV + // = "00111"; constant + // FREF_EN_CLK_REQ = "01000"; + // constant FREF_CLK_VALID = + // "01001"; constant FREF_MODE_DET0 + // = "01010"; constant + // FREF_MODE_DET1 = "01011"; + // constant FREF_MODE_DET2 = + // "10010"; constant FREF_MODE_DET3 + // = "10011"; constant FREF_VALID = + // "01100"; constant FREF_VALID0 = + // "01101"; constant FREF_VALID1 = + // "01110"; constant FREF_VALID2 = + // "01111"; constant + // FREF_WAIT_EXT_TCXO0 = "10000"; + // constant FREF_WAIT_EXT_TCXO1 = + // "10001"; + +#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register. +// +//****************************************************************************** +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \ + 0xFFFFFFE0 + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5 +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \ + 0x00000010 // 1 - Override the sytem-opp + // request to ANATOP using bit0 of + // this register + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \ + 0x0000000F // "0001" - RUN ; "0010" - DSLP ; + // "0100" - LPDS ; Others - NA + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register. +// +//****************************************************************************** +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \ + 0xFFFFFFFE + +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1 +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \ + 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS) + // entry even if Test-Pd is kept ON + // ; 0 - Donot enable sleep-opp + // (DSLP/LPDS) entry with Test-Pd + // ON. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3 +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \ + 0x00000004 // NA + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \ + 0x00000002 // NA + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \ + 0x00000001 // NA + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \ + 0x00000004 // 1 - Override the MCU-PD power + // modes using bits [1] & [0] ; + +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \ + 0x00000002 // 1 - Request for power-down of + // MCU-PD ; + +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \ + 0x00000001 // 1 - Request for retention mode + // of MCU-PD. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \ + 0x00000002 // 1- Override the MCSPI + // (Autonomous SPI) memory state + // using bit [0] + +#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \ + 0x00000001 // 1 - Request for power-down of + // Autonomous SPI 8k memory ; 0 - + // Donot request power-down of + // Autonomous SPI 8k Memory + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \ + 0x00000100 + +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \ + 0x00000002 + +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_REF_FSM_CFG2 register. +// +//****************************************************************************** +#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \ + 0x00380000 // Number of RTC clocks for keeping + // the FC_EN asserted high + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19 +#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \ + 0x00070000 // Number of RTC clocks for keeping + // the STARTUP_EN asserted high + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16 +#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \ + 0x0000FFFF // Number of RTC clocks for waiting + // for clock to settle. + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TESTCTRL_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1 +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \ + 0x00000001 // 0 - Disable the TestCtrl-pd ; 1 + // - Enable the TestCtrl-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \ + 0x00000006 // 1 - SSDIO-PD is ON ; 0 - + // SSDIO-PD is OFF + +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1 +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \ + 0x00000001 // 0 - Disable the SSDIO-pd ; 1 - + // Enable the SSDIO-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_N1_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \ + 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 - + // MCSPI_N1-PD if OFF + +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1 +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \ + 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1 + // - Enable the MCSPI_N1-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \ + 0x00001C00 + +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10 +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \ + 0x00000200 + +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \ + 0x00000100 + +#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1 +#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \ + 0x00000001 // 0 - Disable the WELP-pd ; 1 - + // Enable the WELP-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1 +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \ + 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 - + // Enable the WL_SDIO-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register. +// +//****************************************************************************** +#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \ + 0x00FFFFFF // SRAM (WTOP+DRP) state during + // Active-mode : 1 - SRAMs are ON ; + // 0 - SRAMs are OFF. Cluster + // information : [0] - 1st column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) [1] - 2nd column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [2] - 3rd column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [3] - 4th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [4] - + // 5th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [5] - 6th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [6] - 7th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [7] - 8th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [8] - 9th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [9] - + // 10th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [10] - 11th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [11] - 12th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [12] - 13th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [13] - 14th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [14] - + // 15th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [15] - 16th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [23:16] - Internal to + // WTOP Cluster + +#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register. +// +//****************************************************************************** +#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \ + 0x00FFFFFF // SRAM (WTOP+DRP) state during + // Sleep-mode : 1 - SRAMs are RET ; + // 0 - SRAMs are OFF. Cluster + // information : [0] - 1st column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) [1] - 2nd column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [2] - 3rd column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [3] - 4th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [4] - + // 5th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [5] - 6th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [6] - 7th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [7] - 8th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [8] - 9th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [9] - + // 10th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [10] - 11th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [11] - 12th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [12] - 13th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [13] - 14th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [14] - + // 15th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [15] - 16th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [23:16] - Internal to + // WTOP Cluster + +#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SECURE_INIT_DONE register. +// +//****************************************************************************** +#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \ + 0x00000002 // 1-Secure mode init is done ; + // 0-Secure mode init is not done + +#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \ + 0x00000001 // Must be programmed 1 in order to + // say that secure-mode device init + // is done + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_DEV_MODE_INIT_DONE register. +// +//****************************************************************************** +#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \ + 0x00000001 // 1 - Patch download and other + // initializations are done (before + // removing APPS resetn) for + // development mode (#3) . 0 - + // Development mode (#3) init is not + // done yet + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_EN_APPS_REBOOT register. +// +//****************************************************************************** +#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \ + 0x00000001 // 1 - When 1, disable the reboot + // of APPS after DevInit is + // completed. In this case, APPS + // will permanantly help in reset. 0 + // - When 0, enable the reboot of + // APPS after DevInit is completed. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_APPS_PERIPH_PRESENT register. +// +//****************************************************************************** +#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \ + 0x00010000 // 1 - Enable ; 0 - Disable + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \ + 0x00008000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \ + 0x00004000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \ + 0x00002000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \ + 0x00001000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \ + 0x00000800 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \ + 0x00000400 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \ + 0x00000200 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \ + 0x00000100 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \ + 0x00000080 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \ + 0x00000040 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \ + 0x00000020 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \ + 0x00000010 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \ + 0x00000008 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \ + 0x00000004 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \ + 0x00000002 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_NWP_PERIPH_PRESENT register. +// +//****************************************************************************** +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \ + 0x00000200 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \ + 0x00000100 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \ + 0x00000080 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \ + 0x00000040 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \ + 0x00000020 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \ + 0x00000010 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \ + 0x00000008 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \ + 0x00000004 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \ + 0x00000002 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register. +// +//****************************************************************************** + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \ + 0x00000040 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \ + 0x00000020 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \ + 0x00000010 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \ + 0x00000008 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \ + 0x00000004 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \ + 0x00000002 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \ + 0x00000F00 // "0000"- PORZ :- NWP is yet to be + // enabled by APPS during powerup + // (from HIB/OFF) ; "0011"- ACTIVE + // :- NWP is enabled, clocks and + // resets to NWP-SubSystem are + // enabled ; "0010"- LPDS :- NWP is + // in LPDS-mode ; Clocks and reset + // to NWP-SubSystem are gated ; + // "0101"- WAIT_FOR_OPP :- NWP is in + // transition from LPDS to ACTIVE, + // where it is waiting for OPP to be + // stable ; "1000"- + // WAKE_TIMER_OPP_REQ :- NWP is in + // transition from LPDS, where the + // wakeup cause is LPDS_Wake timer + // OTHERS : NA + +#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8 +#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \ + 0x00000007 // "000" - NWP_RUN : NWP is in RUN + // state (default) - Applicable only + // when NWP_PWR_STATE_PS = ACTIVE ; + // "001" - NWP_SLP : NWP is in SLEEP + // state (default) - Applicable only + // when NWP_PWR_STATE_PS = ACTIVE ; + // "010" - NWP_DSLP : NWP is in + // Deep-Sleep state (default) - + // Applicable only when + // NWP_PWR_STATE_PS = ACTIVE ; "011" + // - WAIT_FOR_ACTIVE : NWP is in + // transition from Deep-sleep to + // Run, where it is waiting for OPP + // to be stable ; "100" - + // WAIT_FOR_DSLP_TIMER_WAKE_REQ : + // NWP is in transition from + // Deep-sleep to Run, where the + // wakeup cause is deep-sleep + // wake-timer + +#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \ + 0x00000F00 // "0000"- PORZ :- APPS is waiting + // for PLL_clock during powerup + // (from HIB/OFF) ; "0011"- ACTIVE + // :- APPS is enabled, clocks and + // resets to APPS-SubSystem are + // enabled ; APPS might be either in + // Secure or Un-secure mode during + // this state. "1001" - + // SECURE_MODE_LPDS :- While in + // ACTIVE (Secure-mode), APPS had to + // program the DevInit_done bit at + // the end, after which it enters + // into this state, where the reset + // to APPS will be asserted. From + // this state APPS might either + // re-boot itself or enter into LPDS + // depending upon whether the device + // is 3200 or 3100. "0010"- LPDS :- + // APPS is in LPDS-mode ; Clocks and + // reset to APPS-SubSystem are gated + // ; "0101"- WAIT_FOR_OPP :- APPS is + // in transition from LPDS to + // ACTIVE, where it is waiting for + // OPP to be stable ; "1000" - + // WAKE_TIMER_OPP_REQ : APPS is in + // transition from LPDS, where the + // wakeup cause is LPDS_Wake timer ; + // "1010" - WAIT_FOR_PATCH_INIT : + // APPS enters into this state + // during development-mode #3 (SOP = + // 3), where it is waiting for patch + // download to complete and 0x4 hack + // is programmed. OTHERS : NA + +#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8 +#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \ + 0x00000007 // "000" - APPS_RUN : APPS is in + // RUN state (default) - Applicable + // only when APPS_PWR_STATE_PS = + // ACTIVE ; "001" - APPS_SLP : APPS + // is in SLEEP state (default) - + // Applicable only when + // APPS_PWR_STATE_PS = ACTIVE ; + // "010" - APPS_DSLP : APPS is in + // Deep-Sleep state (default) - + // Applicable only when + // APPS_PWR_STATE_PS = ACTIVE ; + // "011" - WAIT_FOR_ACTIVE : APPS is + // in transition from Deep-sleep to + // Run, where it is waiting for OPP + // to be stable ; "100" - + // WAIT_FOR_DSLP_TIMER_WAKE_REQ : + // APPS is in transition from + // Deep-sleep to Run, where the + // wakeup cause is deep-sleep + // wake-timer + +#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \ + 0x0000001F // TBD + +#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PM_PS register. +// +//****************************************************************************** +#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \ + 0x00000007 // "011" - WTOP_PM_ACTIVE (Default) + // :- WTOP_Pd is in ACTIVE mode; + // "100" - WTOP_PM_ACTIVE_TO_SLEEP + // :- WTOP_Pd is in transition from + // ACTIVE to SLEEP ; "000" - + // WTOP_PM_SLEEP : WTOP-Pd is in + // Sleep-state ; "100" - + // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd + // is in transition from SLEEP to + // ACTIVE ; "000" - + // WTOP_PM_WAIT_FOR_OPP : Wait for + // OPP to be stable ; + +#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WTOP PD + // Resetz. When set to 1, + // WTOP_Resetz will be controlled by + // bit [0] + +#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WTOP PD Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WELP PD + // Resetz. When set to 1, + // WELP_Resetz will be controlled by + // bit [0] + +#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WELP PD Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WL_SDIO + // Resetz. When set to 1, + // WL_SDIO_Resetz will be controlled + // by bit [0] + +#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WL_SDIO Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for SSDIO + // Resetz. When set to 1, + // SSDIO_Resetz will be controlled + // by bit [0] + +#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for SSDIO Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for MCSPI_N1 + // Resetz. When set to 1, + // MCSPI_N1_Resetz will be + // controlled by bit [0] + +#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for MCSPI_N1 Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for TESTCTRL-PD + // Resetz. When set to 1, + // TESTCTRL_Resetz will be + // controlled by bit [0] + +#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for TESTCTRL Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for MCU-PD + // Resetz. When set to 1, MCU_Resetz + // will be controlled by bit [0] + +#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for MCU Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG0 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \ + 0xFFFFFFFF // This is ROW_14 [31:0] of + // FUSEFARM. [0:0] : XTAL_IS_26MHZ + // [5:1] : TOP_CLKM_RTRIM[4:0] + // [10:6] : ANA_BGAP_MAG_TRIM[4:0] + // [16:11] : ANA_BGAP_TEMP_TRIM[5:0] + // [20:17] : ANA_BGAP_V2I_TRIM[3:0] + // [25:22] : PROCESS INDICATOR + // [26:26] : Reserved [31:27] : + // FUSEROM Version + +#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG1 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \ + 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM + // 1. NWP Peripheral Present bits + // [15:8] NWP_GPT_N0_PP [15:15] + // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP + // [13:13] NWP_UDMA_PP [12:12] + // NWP_UART_N0_PP [11:11] + // NWP_UART_N1_PP [10:10] + // NWP_SSDIO_PP [9:9] + // NWP_MCSPI_N1_PP [8:8] 2. Shared + // Peripheral Present bits [7:0] + // SHARED SPI PP [6:6] + // SHARED I2C PP [5:5] SHARED + // GPIO-A PP [4:4] SHARED GPIO-B PP + // [3:3] SHARED GPIO-C PP [2:2] + // SHARED GPIO-D PP [1:1] SHARED + // GPIO-E PP [0:0] + +#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG2 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \ + 0xFFFFFFFF // This is ROW_16[15:0] & + // ROW_15[31:16] of FUSEFARM. + // [31:21] - Reserved [20:16] - + // CHIP_ID [15:15] - SSBD SOP + // Control [14:14] - SSBD TAP + // Control [13:2] - APPS Peripheral + // Present bits : APPS_CAMERA_PP + // [13:13] APPS_MMCHS_PP [12:12] + // APPS_MCASP_PP [11:11] + // APPS_MCSPI_A1_PP [10:10] + // APPS_MCSPI_A2_PP [9:9] + // APPS_UDMA_PP [8:8] APPS_WDOG_PP + // [7:7] APPS_UART_A0_PP [6:6] + // APPS_UART_A1_PP [5:5] + // APPS_GPT_A0_PP [4:4] + // APPS_GPT_A1_PP [3:3] + // APPS_GPT_A2_PP [2:2] + // APPS_GPT_A3_PP [1:1] [0:0] - NWP + // Peripheral present bits + // NWP_ACSPI_PP [0:0] + +#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG3 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \ + 0xFFFFFFFF // This is ROW_17[15:0] & + // ROW_16[31:16] of FUSEFARM : + // [31:16] - TEST_TAP_KEY(15:0) + // [15:0] - Reserved + +#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_MEM_RET_CFG register. +// +//****************************************************************************** +#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \ + 0x00000001 // 1 - Soft-compile memories in + // WTOP can be turned-off during + // WTOP-sleep mode ; 0 - + // Soft-compile memories in WTOP + // must be kept on during WTOP-sleep + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \ + 0x007FFFFF // TBD + +#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \ + 0x000FFFFF // TBD + +#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \ + 0x00000018 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3 +#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \ + 0x00000004 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \ + 0x00000002 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \ + 0x00000001 // TBD + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \ + 0x00000001 // 1 - Enable switching of sysclk + // to Coex-clk path ; 0 - Disable + // switching of sysclk to Coex-clk + // path. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_DCDC_CLK_GEN_CONFIG register. +// +//****************************************************************************** +#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \ + 0x00000001 // 1 - Enable the clock for DCDC + // (PWM-mode) ; 0 - Disable the + // clock for DCDC (PWM-mode) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG4 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \ + 0x0000FFFF // This corresponds to + // ROW_17[31:16] of the FUSEFARM : + // [15:0] : TEST_TAP_KEY(31:16) + +#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG5 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \ + 0xFFFFFFFF // Corresponds to ROW_18 of + // FUSEFARM. [29:0] - + // MEMSS_COLUMN_SEL_LSW ; [30:30] - + // WLAN GEM DISABLE ; [31:31] - + // SERIAL WIRE JTAG SELECT + +#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG6 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \ + 0x0000FFFF // Corresponds to ROW_19[15:0] of + // FUSEFARM. [15:0] : + // MEMSS_COLUMN_SEL_MSW + +#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG7 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_20[15:0] & + // ROW_19[31:16] of FUSEFARM. + // FLASH_REGION0 + +#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG8 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_21[15:0] & + // ROW_20[31:16] of FUSEFARM. + // FLASH_REGION1 + +#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG9 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_22[15:0] & + // ROW_21[31:16] of FUSEFARM. + // FLASH_REGION2 + +#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG10 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_23[15:0] & + // ROW_22[31:16] of FUSEFARM. + // FLASH_REGION3 + +#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG11 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_24[15:0] & + // ROW_23[31:16] of FUSEFARM. + // FLASH_DESCRIPTOR + +#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG0 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \ + 0xFFFFFFFF // Corresponds to bits [191:160] of + // the FUSEFARM. This is ROW_5 of + // FUSEFARM [191:160] : [31:0] : + // DIE_ID0 [31:0] : DEVX [11:0] DEVY + // [23:12] DEVWAF [29:24] DEV_SPARE + // [31:30] + +#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG1 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \ + 0xFFFFFFFF // Corresponds to bits [223:192] of + // the FUSEFARM. This is ROW_6 of + // FUSEFARM :- DEVLOT [23:0] DEVFAB + // [28:24] DEVFABBE [31:29] + +#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG2 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \ + 0xFFFFFFFF // Corresponds to bits [255:224] of + // the FUSEFARM. This is ROW_7 of + // FUSEFARM:- DEVDESREV[4:0] + // Memrepair[5:5] MakeDefined[16:6] + // CHECKSUM[30:17] Reserved : + // [31:31] + +#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG3 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \ + 0xFFFFFFFF // Corresponds to bits [287:256] of + // the FUSEFARM. This is ROW_8 of + // FUSEFARM :- DIEID0 - DEVREG + // [31:0] + +#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG4 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \ + 0xFFFFFFFF // Corresponds to bits [319:288] of + // the FUSEFARM. This is ROW_9 of + // FUSEFARM :- [7:0] - VBATMON ; + // [13:8] - BUFF_OFFSET ; [15:15] - + // DFT_GXG ; [14:14] - DFT_GLX ; + // [19:16] - PHY ROM Version ; + // [23:20] - MAC ROM Version ; + // [27:24] - NWP ROM Version ; + // [31:28] - APPS ROM Version + +#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APPS_SS_OVERRIDES_reserved_M \ + 0xFFFFFC00 + +#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10 +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \ + 0x00000200 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \ + 0x00000100 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \ + 0x00000080 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \ + 0x00000040 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \ + 0x00000020 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \ + 0x00000010 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \ + 0x00000008 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \ + 0x00000002 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_NWP_SS_OVERRIDES_reserved_M \ + 0xFFFFFC00 + +#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10 +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \ + 0x00000200 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \ + 0x00000100 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \ + 0x00000080 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \ + 0x00000040 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \ + 0x00000020 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \ + 0x00000010 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \ + 0x00000008 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \ + 0x00000002 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SHARED_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8 +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \ + 0x00000080 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \ + 0x00000040 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \ + 0x00000020 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \ + 0x00000010 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \ + 0x00000008 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \ + 0x00000004 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \ + 0x00000002 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8 +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \ + 0x00000080 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \ + 0x00000040 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \ + 0x00000020 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \ + 0x00000010 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \ + 0x00000008 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \ + 0x00000002 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_FSM_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \ + 0xFFFFF000 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12 +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \ + 0x00000800 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \ + 0x00000400 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \ + 0x00000200 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \ + 0x00000100 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \ + 0x00000080 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \ + 0x00000040 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \ + 0x00000020 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \ + 0x00000010 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \ + 0x00000008 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \ + 0x00000002 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \ + 0xFFF00000 + +#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \ + 0x00080000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \ + 0x00040000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \ + 0x00020000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \ + 0x00010000 + +#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \ + 0x0000FC00 + +#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \ + 0x00000200 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \ + 0x00000100 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \ + 0x000000F0 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \ + 0x0000000F + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \ + 0xFFC00000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22 +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \ + 0x00200000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \ + 0x00100000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \ + 0x00080000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \ + 0x00040000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \ + 0x00020000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \ + 0x00010000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \ + 0x0000FF00 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8 +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \ + 0x000000FF + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8 +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \ + 0x00000080 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \ + 0x00000040 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \ + 0x00000020 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \ + 0x00000010 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \ + 0x00000008 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \ + 0x00000004 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \ + 0x00000001 + + + + +#endif // __HW_GPRCM_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib1p2.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib1p2.h new file mode 100644 index 0000000000..95e25ff7cf --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib1p2.h @@ -0,0 +1,1750 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_HIB1P2_H__ +#define __HW_HIB1P2_H__ + +//***************************************************************************** +// +// The following are defines for the HIB1P2 register offsets. +// +//***************************************************************************** +#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \ + 0x00000000 + +#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \ + 0x00000004 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \ + 0x00000008 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \ + 0x0000000C + +#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \ + 0x00000010 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \ + 0x00000014 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \ + 0x00000018 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \ + 0x0000001C + +#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \ + 0x00000020 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \ + 0x00000024 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \ + 0x00000028 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \ + 0x00000064 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \ + 0x00000068 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \ + 0x0000006C + +#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \ + 0x00000070 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \ + 0x00000074 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \ + 0x00000078 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \ + 0x0000007C + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \ + 0x00000080 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \ + 0x00000084 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \ + 0x00000088 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \ + 0x0000008C + +#define HIB1P2_O_PMBIST_PARAMETERS0 \ + 0x00000094 + +#define HIB1P2_O_PMBIST_PARAMETERS1 \ + 0x00000098 + +#define HIB1P2_O_PMBIST_PARAMETERS2 \ + 0x0000009C + +#define HIB1P2_O_PMBIST_PARAMETERS3 \ + 0x000000A0 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \ + 0x000000A4 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \ + 0x000000A8 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \ + 0x000000AC + +#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \ + 0x000000B0 + +#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \ + 0x000000B4 + +#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \ + 0x000000B8 + +#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \ + 0x000000BC + +#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \ + 0x000000C0 + +#define HIB1P2_O_CM_OSC_16M_CONFIG \ + 0x000000C4 + +#define HIB1P2_O_SOP_SENSE_VALUE \ + 0x000000C8 + +#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \ + 0x000000CC + +#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \ + 0x000000D0 + +#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \ + 0x000000D4 + +#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \ + 0x000000D8 + +#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \ + 0x000000DC + +#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \ + 0x000000E0 + +#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \ + 0x000000E4 + +#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \ + 0x000000E8 + +#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \ + 0x000000EC + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \ + 0x000000F0 + +#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \ + 0x000000F4 + +#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \ + 0x000000F8 + +#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \ + 0x000000FC + +#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \ + 0x00000100 + +#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \ + 0x00000104 + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \ + 0x00000108 + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \ + 0x0000010C + +#define HIB1P2_O_CM_SPARE 0x00000110 +#define HIB1P2_O_PORPOL_SPARE 0x00000114 +#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \ + 0x00000118 + +#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \ + 0x0000011C + +#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \ + 0x00000120 + +#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \ + 0x00000124 + +#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \ + 0x00000128 + +#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \ + 0x0000012C + +#define HIB1P2_O_MEM_HIB_FSM_DEBUG \ + 0x00000130 + +#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \ + 0x00000134 + +#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \ + 0x00000138 + +#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \ + 0x0000013C + +#define HIB1P2_O_MEM_CM_TEST_MODE \ + 0x00000140 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \ + 0xC0000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \ + 0x30000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \ + 0x08000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \ + 0x04000000 // FSM Override value for SLDO_EN : + // Applicable only when bit [4] of + // this register is set to 1. + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \ + 0x02000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \ + 0x01000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \ + 0x00FC0000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \ + 0x0003FF00 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \ + 0x00000080 // FSM Override value for + // SKA_LDO_EN : Applicable only when + // bit [3] of this register is set + // to 1. + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \ + 0x00000040 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \ + 0x00000020 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \ + 0x00000010 // When 1, bit[26] of this register + // will be used as SLDO_EN + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \ + 0x00000008 // When 1, bit[26] of this register + // will be used as SKA_LDO_EN + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \ + 0x00000007 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \ + 0xFFC00000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \ + 0x003F0000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \ + 0x00008000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \ + 0x00004000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \ + 0x00002000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \ + 0x00001000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \ + 0x00000800 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \ + 0x000007FF + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \ + 0x80000000 // Override value for DCDC_DIG_EN : + // Applicable only when bit [31] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \ + 0x20000000 // Override value for + // DCDC_DIG_EN_SUBREG_1P8V : + // Applicable only when bit [30] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \ + 0x10000000 // Override value for + // DCDC_DIG_EN_SUBREG_1P2V : + // Applicable only when bit [29] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \ + 0x08000000 // Override value for + // DCDC_DIG_SLP_EN : Applicable only + // when bit [28] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \ + 0x04000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \ + 0x02000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \ + 0x01000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \ + 0x00800000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \ + 0x00400000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \ + 0x003F0000 // Override value for + // DCDC_DIG_VTRIM : Applicable only + // when bit [27] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \ + 0x0000C000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \ + 0x00003000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \ + 0x00000800 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \ + 0x00000780 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \ + 0x00000078 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3 +#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \ + 0x00000007 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \ + 0x20000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \ + 0x10000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \ + 0x08000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \ + 0x04000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \ + 0x02000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \ + 0x01FFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \ + 0x0F000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \ + 0x00C00000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \ + 0x00300000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16 +#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \ + 0x00008000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \ + 0x00007800 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \ + 0x00000400 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \ + 0x000003FC + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \ + 0x00000002 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \ + 0x00000001 // Override value for + // DCDC_DIG_COT_EN : Applicable only + // when bit[26] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \ + 0x7F800000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \ + 0x00400000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \ + 0x00200000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \ + 0x001FE000 // Override value for + // DCDC_DIG_ILIM_TRIM : Applicable + // only when bit [25] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \ + 0x00001800 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \ + 0x00000400 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \ + 0x00000200 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \ + 0x000001F0 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \ + 0x0000000C + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \ + 0x00000002 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS4 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \ + 0x20000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \ + 0x1FFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS5 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS6 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \ + 0x80000000 // Override for ANA DCDC EN + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \ + 0x20000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \ + 0x10000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \ + 0x08000000 // Override for ANA DCDC PWM + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \ + 0x04000000 // Override for ANA DCDC SLP + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \ + 0x02000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \ + 0x01000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \ + 0x00800000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \ + 0x00400000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \ + 0x00200000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \ + 0x001E0000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \ + 0x00018000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \ + 0x00006000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \ + 0x00001000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \ + 0x00000F00 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \ + 0x000000F0 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \ + 0x0000000F + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \ + 0x0C000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \ + 0x03000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \ + 0x00F00000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \ + 0x00008000 // (Earlier SHOOTTHRU CTRL) + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \ + 0x00004000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \ + 0x00003E00 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \ + 0x00000100 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \ + 0x00000080 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \ + 0x00000060 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \ + 0x00000010 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \ + 0x0000000C + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2 +#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \ + 0x00000003 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS16 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \ + 0x00200000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \ + 0x00100000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \ + 0x000FF000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \ + 0x00000C00 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \ + 0x00000200 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \ + 0x00000100 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \ + 0x000000F8 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \ + 0x00000006 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS17 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \ + 0x40000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \ + 0x3FFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS18 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS19 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \ + 0x20000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \ + 0x18000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \ + 0x04000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \ + 0x02000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \ + 0x01000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \ + 0x00800000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \ + 0x00400000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \ + 0x003C0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \ + 0x00020000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \ + 0x00010000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \ + 0x00008000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \ + 0x00004000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \ + 0x00002000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \ + 0x00001000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \ + 0x00000800 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \ + 0x00000400 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \ + 0x00000200 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \ + 0x000001E0 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \ + 0x0000001E + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \ + 0x0F000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \ + 0x00F00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \ + 0x0000F000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \ + 0x00000F00 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \ + 0x000000C0 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \ + 0x00000030 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \ + 0x0000000C + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \ + 0x00000003 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \ + 0xC0000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \ + 0x30000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \ + 0x0C000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \ + 0x03000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \ + 0x00800000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \ + 0x00400000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \ + 0x00200000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \ + 0x001F0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \ + 0x0000F000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \ + 0x00000800 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \ + 0x00000400 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \ + 0x000003FC + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \ + 0x00000003 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \ + 0x20000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \ + 0x1F000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \ + 0x00E00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \ + 0x001C0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \ + 0x0003C000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \ + 0x00003C00 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \ + 0x00000300 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \ + 0x00000080 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \ + 0x00000040 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \ + 0x00000020 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \ + 0x0000001F + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \ + 0x3FFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \ + 0x80000000 + +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \ + 0x7FFFF800 + +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11 +#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \ + 0x000007FF + +#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \ + 0xFFFF0000 + +#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16 +#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \ + 0x00008000 + +#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \ + 0x00007FFF + +#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \ + 0xFFFF0000 + +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16 +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \ + 0x0000E000 + +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13 +#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \ + 0x00001000 + +#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \ + 0x00000FFF + +#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \ + 0x7C000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26 +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \ + 0x03E00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21 +#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \ + 0x001FFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \ + 0xFFFFFFC0 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6 +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \ + 0x00000020 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \ + 0x00000010 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \ + 0x00000008 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \ + 0x00000004 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \ + 0x00000002 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \ + 0xFFFFFFFC + +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \ + 0x00000002 + +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_VTRIM_CFG register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \ + 0xFF000000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \ + 0x00FC0000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \ + 0x0003F000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \ + 0x00000FC0 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \ + 0x0000003F + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \ + 0xFFFF8000 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \ + 0x00007000 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \ + 0x00000E00 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \ + 0x000001C0 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \ + 0x00000038 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \ + 0x00000007 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \ + 0xFFFFFFF8 + +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3 +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \ + 0x00000007 + +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \ + 0xFFFFFFC0 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6 +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \ + 0x00000038 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3 +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \ + 0x00000007 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register. +// +//****************************************************************************** +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \ + 0xFFFFFFF8 + +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3 +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \ + 0x00000007 + +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_CM_OSC_16M_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \ + 0xFFFC0000 + +#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18 +#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \ + 0x00020000 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \ + 0x00010000 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \ + 0x0000FC00 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10 +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \ + 0x000003F0 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4 +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \ + 0x00000008 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \ + 0x00000007 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SOP_SENSE_VALUE register. +// +//****************************************************************************** +#define HIB1P2_SOP_SENSE_VALUE_reserved_M \ + 0xFFFFFF00 + +#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8 +#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \ + 0x000000FF + +#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \ + 0xFF800000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \ + 0x00400000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \ + 0x003FC000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \ + 0x00002000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \ + 0x00001FC0 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \ + 0x00000020 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \ + 0x0000001F + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \ + 0xFFFFFFFF // Corresponds to ROW_12 of + // FUSEFARM. [7:0] : + // DCDC_DIG_ILIM_TRIM_LOWV(7:0) + // [15:8] : + // DCDC_ANA_ILIM_TRIM_LOWV(7:0) + // [23:16] : + // DCDC_FLASH_ILIM_TRIM_LOWV(7:0) + // [24:24] : DTHE SHA DISABLE + // [25:25] : DTHE DES DISABLE + // [26:26] : DTHE AES DISABLE + // [31:27] : HD_BG_RTRIM (4:0) + +#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \ + 0xFFFFFFFF // Corresponds to ROW_13 of the + // FUSEFARM. [7:0] : HD_BG_MAG_TRIM + // (7:0) [14:8] : HD_BG_TEMP_TRIM + // (6:0) [15:15] : GREYOUT ENABLE + // DUTY CYCLING [31:16] : + // Reserved/Checksum + +#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_POR_TEST_CTRL register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \ + 0xFFFFFF00 + +#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8 +#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \ + 0x000000FF + +#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \ + 0x0000FF00 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \ + 0x000000FE + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \ + 0xFFF00000 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \ + 0x000FFFFF + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \ + 0xFFFFFE00 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9 +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \ + 0x00000100 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \ + 0x000000FC + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2 +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \ + 0x00000002 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16 +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16 +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \ + 0xFFFFF000 + +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12 +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \ + 0x00000FFF + +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register. +// +//****************************************************************************** +#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \ + 0xFF000000 + +#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24 +#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \ + 0x00FF0000 + +#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16 +#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \ + 0x0000FFFF + +#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PORPOL_SPARE register. +// +//****************************************************************************** +#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \ + 0xFFFFFFFF + +#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \ + 0x00000002 + +#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \ + 0x00000002 + +#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_HIB_FSM_DEBUG register. +// +//****************************************************************************** +#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \ + 0x00000700 + +#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8 +#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \ + 0x000000F0 + +#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4 +#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \ + 0x0000000F + +#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \ + 0x000FFFFF + +#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register. +// +//****************************************************************************** +#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \ + 0x00000002 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_CM_TEST_MODE register. +// +//****************************************************************************** +#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \ + 0x00000001 + + + + +#endif // __HW_HIB1P2_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib3p3.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib3p3.h new file mode 100644 index 0000000000..9701689165 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib3p3.h @@ -0,0 +1,1138 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_HIB3P3_H__ +#define __HW_HIB3P3_H__ + +//***************************************************************************** +// +// The following are defines for the HIB3P3 register offsets. +// +//***************************************************************************** +#define HIB3P3_O_MEM_HIB_REQ 0x00000000 +#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \ + 0x00000004 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \ + 0x00000008 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \ + 0x0000000C + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \ + 0x00000010 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \ + 0x00000014 + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \ + 0x00000018 + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \ + 0x0000001C + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \ + 0x00000020 + +#define HIB3P3_O_MEM_INT_OSC_CONF \ + 0x0000002C + +#define HIB3P3_O_MEM_XTAL_OSC_CONF \ + 0x00000034 + +#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \ + 0x00000038 + +#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \ + 0x0000003C + +#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \ + 0x00000040 + +#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \ + 0x00000044 + +#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050 +#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \ + 0x00000054 + +#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \ + 0x00000058 + +#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \ + 0x0000005C + +#define HIB3P3_O_MEM_HIB_UART_CONF \ + 0x00000400 + +#define HIB3P3_O_MEM_GPIO_WAKE_EN \ + 0x00000404 + +#define HIB3P3_O_MEM_GPIO_WAKE_CONF \ + 0x00000408 + +#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \ + 0x0000040C + +#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \ + 0x00000410 + +#define HIB3P3_O_MEM_JTAG_CONF 0x00000414 +#define HIB3P3_O_MEM_HIB_REG0 0x00000418 +#define HIB3P3_O_MEM_HIB_REG1 0x0000041C +#define HIB3P3_O_MEM_HIB_REG2 0x00000420 +#define HIB3P3_O_MEM_HIB_REG3 0x00000424 +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \ + 0x0000045C + +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \ + 0x00000460 + +#define HIB3P3_O_MEM_HIB_MISC_CONFIG \ + 0x00000464 + +#define HIB3P3_O_MEM_HIB_WAKE_STATUS \ + 0x00000468 + +#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \ + 0x0000046C + +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \ + 0x00000470 + +#define HIB3P3_O_HIBANA_SPARE_LOWV \ + 0x00000474 + +#define HIB3P3_O_HIB_TMUX_CTRL 0x00000478 +#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \ + 0x0000047C + +#define HIB3P3_O_HIB_COMP_TRIM 0x00000480 +#define HIB3P3_O_HIB_EN_TS 0x00000484 +#define HIB3P3_O_HIB_1P8V_DET_EN \ + 0x00000488 + +#define HIB3P3_O_HIB_VBAT_MON_EN \ + 0x0000048C + +#define HIB3P3_O_HIB_NHIB_ENABLE \ + 0x00000490 + +#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \ + 0x00000494 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REQ register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REQ_reserved_M \ + 0xFFFFFE00 + +#define HIB3P3_MEM_HIB_REQ_reserved_S 9 +#define HIB3P3_MEM_HIB_REQ_NU1_M \ + 0x000001FC + +#define HIB3P3_MEM_HIB_REQ_NU1_S 2 +#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \ + 0x00000002 // 1 - Specifies that the Hiberante + // mode is without clocks ; 0 - + // Specified that the Hibernate mode + // is with clocks This register will + // be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +#define HIB3P3_MEM_HIB_REQ_mem_hib_req \ + 0x00000001 // 1 - Request for hibernate mode + // (This is an auto-clear bit) ; 0 - + // Donot request for hibernate mode + // This register will be reset + // during Hibernate -WO-Clks mode + // (but not during Hibernate-W-Clks + // mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \ + 0x00000001 // 1 - Enable the RTC timer to + // start running ; 0 - Keep the RTC + // timer disabled This register will + // be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \ + 0x00000001 // 1 - Reset the RTC timer ; 0 - + // Donot reset the RTC timer. This + // is an auto-clear bit. This + // register will be reset during + // Hibernate -WO-Clks mode (but not + // during Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \ + 0x00000001 // 1 - Latch the running RTC timer + // into local registers. After + // programming this bit to 1, the + // F/w can read the latched RTC + // timer values from + // MEM_HIB_RTC_TIMER_LSW and + // MEM_HIB_RTC_TIMER_MSW. Before the + // F/w (APPS or NWP) wants to read + // the RTC-Timer, it has to program + // this bit to 1, then only read the + // MSW and LSW values. This is an + // auto-clear bit. This register + // will be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \ + 0xFFFFFFFF // Lower 32b value of the latched + // RTC-Timer. + +#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16 +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \ + 0x0000FFFF // Upper 32b value of the latched + // RTC-Timer. + +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \ + 0x00000001 // 1 - Enable the RTC timer based + // wakeup during Hibernate mode ; 0 + // - Disable the RTC timer based + // wakeup during Hibernate mode This + // register will be reset during + // Hibernate-WO-Clks mode (but not + // during Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \ + 0xFFFFFFFF // Configuration for RTC-Timer + // Wakeup (Lower 32b word) + +#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16 +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \ + 0x0000FFFF // Configuration for RTC-Timer + // Wakeup (Upper 16b word) + +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_INT_OSC_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16 +#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \ + 0x00008000 // 1 - Internal 32kHz Oscillator is + // valid ; 0 - Internal 32k + // oscillator clk is not valid + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \ + 0x00007E00 + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9 +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \ + 0x00000100 // When 1, the INT_32K_OSC_EN comes + // from bit [0] of this register, + // else comes from the FSM. This + // register will be reset during + // Hibernate-WO-Clks mode (but not + // during Hibernate-W-Clks mode) + +#define HIB3P3_MEM_INT_OSC_CONF_NU1 \ + 0x00000080 + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \ + 0x0000007E + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1 +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \ + 0x00000001 // Override value for INT_OSC_EN. + // Applicable only when bit [3] of + // this register is set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_XTAL_OSC_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \ + 0xFFF00000 + +#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \ + 0x00080000 // When 1, the SLICER_EN comes from + // bit [10] of this register, else + // comes from the FSM. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \ + 0x00040000 // When 1, the XTAL_EN comes from + // bit [0] of this register, else + // comes from the FSM. + +#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \ + 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL + // Clk is yet to be valid. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \ + 0x0001F800 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \ + 0x00000400 // SLICER_EN Override value : + // Applicable only when bit [19] of + // this register is set to 1. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \ + 0x00000380 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \ + 0x00000070 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \ + 0x00000008 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \ + 0x00000006 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \ + 0x00000001 // XTAL_EN Override value : + // Applicable only when bit [18] of + // this register is set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_BGAP_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \ + 0xFFF80000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19 +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \ + 0x00040000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \ + 0x0001C000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14 +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \ + 0x00001000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \ + 0x00000800 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \ + 0x00000400 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \ + 0x000003FF + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_BGAP_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \ + 0xE0000000 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29 +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \ + 0x1F000000 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24 +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \ + 0x00000008 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \ + 0x00000004 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \ + 0x00000002 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_DETECTION_STATUS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \ + 0xFFFFFF80 + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7 +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \ + 0x00000040 // 1 - 1.8 V supply forced mode. + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \ + 0x00000004 // 1 - 3.3 V supply forced mode for + // Flash supply + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \ + 0x00000002 // 1 - Forced clock mode + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \ + 0x00000001 // 1 - XTAL clock mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_MISC_CONTROLS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \ + 0xFFFFF800 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11 +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \ + 0x00000400 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \ + 0x00000200 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \ + 0x000001C0 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6 +#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \ + 0x00000020 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \ + 0x00000010 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_CONFIG register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \ + 0xFF000000 + +#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24 +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \ + 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD + // for digital path (SHARED4) ; 0 - + // Disable VDD_FLASH_INDP_PAD for + // digital path (SHARED4) ; Before + // programming this bit to 1, ensure + // that the device is in FORCED 3.3 + // supply Mode, which can be + // inferred from the register : + // MEM_HIB_DETECTION_STATUS : 0x0040 + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \ + 0x00040000 // 1 - Enable the + // VDD_FB_GPIO_MUX_PAD for digital + // path (SHARED3) ; 0 - Disable the + // VDD_FB_GPIO_MUX_PAD for digital + // path (SHARED3) ; This pin can be + // used only in modes other than + // SOP("111") + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \ + 0x00020000 // 1 - Enable the PM_TEST_PAD for + // digital GPIO path (SHARED2) ; 0 - + // Disable the PM_TEST_PAD for + // digital GPIO path (SHARED2) This + // pin can be used for digital only + // in modes other then SOP-111 + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \ + 0x00010000 // 1 - Enable the XTAL_N pin + // digital GPIO path (SHARED1); 0 - + // Disable the XTAL_N pin digital + // GPIO path (SHARED1). Before + // programming this bit to 1, ensure + // that the device is in FORCED CLK + // Mode, which can inferred from the + // register : + // MEM_HIB_DETECTION_STATUS : + // 0x0040. + +#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \ + 0x00000100 // 1 - Enable the XTAL Clock ; 0 - + // Donot enable the XTAL Clock. This + // bit has to be programmed to 1 (by + // APPS Devinit F/w), during exit + // from OFF or Hib_wo_clks modes, + // after checking if the slow_clk + // mode is XTAL_CLK mode. Once + // enabled the XTAL will be disabled + // only after entering HIB_WO_CLKS + // mode. This register will be reset + // during Hibernate -WO-Clks mode + // (but not during Hibernate-W-Clks + // mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \ + 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0 + // - Disable the HIB RTC - IRQ + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \ + 0xFFFFFFFF // Configuration for LSW of the + // RTC-Timestamp at which interrupt + // need to be generated + +#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \ + 0x0000FFFF // Configuration for MSW of thr + // RTC-Timestamp at which the + // interrupt need to be generated + +#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_UART_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1 +#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \ + 0x00000001 // 1 - Enable the UART-Autonomous + // mode wakeup during Hibernate mode + // ; This is an auto-clear bit, once + // programmed to 1, it will latched + // into an internal register which + // remain asserted until the + // Hib-wakeup is initiated. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_GPIO_WAKE_EN register. +// +//****************************************************************************** +#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \ + 0xFFFFFF00 + +#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8 +#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \ + 0x000000FF // 1 - Enable the GPIO-Autonomous + // mode wakeup during Hibernate mode + // ; This is an auto-clear bit, once + // programmed to 1, it will latched + // into an internal register which + // remain asserted until the + // Hib-wakeup is initiated. + +#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16 +#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \ + 0x0000FFFF // Configuration to say whether the + // GPIO wakeup has to happen on + // Level0 or falling-edge for the + // given group. “00” – Level0 “01” – + // Level1 “10”- Fall-edge “11”- + // Rise-edge [1:0] – Conf for GPIO0 + // [3:2] – Conf for GPIO1 [5:4] – + // Conf for GPIO2 [7:6] – Conf for + // GPIO3 [9:8] – Conf for GPIO4 + // [11:10] – Conf for GPIO5 [13:12] + // – Conf for GPIO6 + +#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \ + 0x00000004 // 1 - Override the OEN33 and RET33 + // controls of GPIOs during + // SOP-Bootdebug mode ; 0 - Donot + // override the OEN33 and RET33 + // controls of GPIOs during + // SOP-Bootdebug mode + +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \ + 0x00000004 // 1 - Override the OEN33 and RET33 + // controls of UART NRTS GPIO during + // SOP-Bootdebug mode ; 0 - Donot + // override the OEN33 and RET33 + // controls of UART NRTS GPIO during + // SOP-Bootdebug mode + +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_JTAG_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \ + 0x00000200 + +#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \ + 0x00000100 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \ + 0x00000008 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \ + 0x00000004 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG2 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG3 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \ + 0xFFFF0000 // Configuration for the number of + // slow-clks between de-assertion of + // EN_BG_3P3V to assertion of + // EN_BG_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \ + 0x00008000 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \ + 0x00006000 // Configuration for the number of + // slow-clks between assertion of + // EN_COMP_3P3V and assertion of + // EN_COMP_LATCH_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \ + 0x00001800 // Configuration for the number of + // slow-clks between assertion of + // (EN_CAP_SW_3P3V,EN_COMP_REF) and + // assertion of (EN_COMP_3P3V) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \ + 0x00000600 // Configuration for the number of + // slow-clks between assertion of + // (EN_BG_3P3V) and assertion of + // (EN_CAP_SW_3P3V, + // EN_COMP_REF_3P3V) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \ + 0x00000100 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \ + 0x00000080 // 1 - EN_VBOK4BG_REF comes from + // bit[10] of the register + // MEM_BGAP_PARAMETERS0 [0x0038]. 0 + // - EN_VBOK4BG_REF comes directly + // from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \ + 0x00000040 // 1 - EN_VBOK4BG comes from + // bit[11] of the register + // MEM_BGAP_PARAMETERS0 [0x0038]. 0 + // - EN_VBOK4BG comes directly from + // the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \ + 0x00000020 // 1 - EN_V2I comes from bit[2] of + // the register MEM_BGAP_PARAMETERS1 + // [0x003C]. 0 - EN_V2I comes + // directly from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \ + 0x00000010 // 1 - EN_POR_COMP_REF comes from + // bit[9] of the register + // MEM_HIB_MISC_CONTROLS [0x0044]. 0 + // - EN_POR_COMP_REF comes directly + // from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \ + 0x00000008 // 1 - EN_POR_COMP comes from + // bit[10] of the register + // MEM_HIB_MISC_CONTROLS [0x044]. 0 + // - EN_POR_COMP comes directly from + // the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \ + 0x00000004 // 1 - EN_CAP_SW comes from bit[1] + // of the register + // MEM_BGAP_PARAMETERS1 [0x003C]. 0 + // - EN_CAP_SW comes directly from + // Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \ + 0x00000002 // 1 - EN_BGAP comes from bit[0] of + // the register MEM_BGAP_PARAMETERS1 + // [0x003C]. 0 - EN_BGAP comes + // directly from Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \ + 0x0000C000 // Configuration for number of + // slow-clks between de-assertion of + // EN_COMP_LATCH and assertion of + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \ + 0x00003000 // Configuration for number of + // slow-clks between assertion of + // EN_COMP_REF to assertion of + // EN_COMP during HIB-Exit + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \ + 0x00000C00 // TBD + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \ + 0x00000300 // Configuration in number of + // slow-clks between assertion of + // (EN_BGAP_3P3V, EN_CAP_SW_3P3V, + // EN_ACT_IREF_3P3V, EN_COMP_REF) to + // assertion of EN_COMP_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \ + 0x000000C0 // Configuration in number of + // slow-clks between de-assertion of + // (EN_COMP_3P3V, EN_COMP_REF_3P3V, + // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V) + // to deassertion of EN_BGAP_3P3V. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \ + 0x0000003F + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_MISC_CONFIG register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_WAKE_STATUS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \ + 0x0000001E // "0100" - GPIO ; "0010" - RTC ; + // "0001" - UART Others - Reserved + +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1 +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \ + 0x00000001 // 1 - Wake from Hibernate ; 0 - + // Wake from OFF + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \ + 0x00000007 + +#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \ + 0xFFFFF800 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \ + 0x00000600 // Deassertion of EN_COMP_LATCH_3P3 + // to deassertion of (EN_COMP_3P3, + // EN_COMP_REF_3P3, EN_ACT_IREF_3P3, + // EN_CAP_SW_3P3) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \ + 0x000001C0 // Assertion of EN_COMP_LATCH_3P3 + // to deassertion of + // EN_COMP_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \ + 0x00000030 // Deassertion of (EN_CAP_SW_3P3, + // EN_COMP_REF_3P3, EN_COMP_3P3, + // EN_COMP_OUT_LATCH_3P3) to + // deassertion of EN_BGAP_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \ + 0x0000000C // Assertion of EN_COMP_3P3 to + // assertion of EN_COMPOUT_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \ + 0x00000003 // Assertion of EN_COMP_3P3 to + // assertion of EN_COMPOUT_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIBANA_SPARE_LOWV register. +// +//****************************************************************************** +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \ + 0xFFC00000 + +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22 +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \ + 0x0001FFFF + +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_TMUX_CTRL register. +// +//****************************************************************************** +#define HIB3P3_HIB_TMUX_CTRL_reserved_M \ + 0xFFFFFC00 + +#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10 +#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \ + 0x000003FF + +#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register. +// +//****************************************************************************** +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \ + 0xFFFFF000 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12 +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \ + 0x00000800 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \ + 0x00000400 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \ + 0x00000200 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \ + 0x00000100 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \ + 0x000000F0 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4 +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \ + 0x0000000F + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_COMP_TRIM register. +// +//****************************************************************************** +#define HIB3P3_HIB_COMP_TRIM_reserved_M \ + 0xFFFFFFF8 + +#define HIB3P3_HIB_COMP_TRIM_reserved_S 3 +#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \ + 0x00000007 + +#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_EN_TS register. +// +//****************************************************************************** +#define HIB3P3_HIB_EN_TS_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_HIB_EN_TS_reserved_S 1 +#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_1P8V_DET_EN register. +// +//****************************************************************************** +#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1 +#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_VBAT_MON_EN register. +// +//****************************************************************************** +#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \ + 0xFFFFFFFC + +#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2 +#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \ + 0x00000002 + +#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_NHIB_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \ + 0x00000001 + + + + +#endif // __HW_HIB3P3_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_i2c.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_i2c.h new file mode 100644 index 0000000000..17536d3e9c --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_i2c.h @@ -0,0 +1,503 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 +#define I2C_O_MCS 0x00000004 +#define I2C_O_MDR 0x00000008 +#define I2C_O_MTPR 0x0000000C +#define I2C_O_MIMR 0x00000010 +#define I2C_O_MRIS 0x00000014 +#define I2C_O_MMIS 0x00000018 +#define I2C_O_MICR 0x0000001C +#define I2C_O_MCR 0x00000020 +#define I2C_O_MCLKOCNT 0x00000024 +#define I2C_O_MBMON 0x0000002C +#define I2C_O_MBLEN 0x00000030 +#define I2C_O_MBCNT 0x00000034 +#define I2C_O_SOAR 0x00000800 +#define I2C_O_SCSR 0x00000804 +#define I2C_O_SDR 0x00000808 +#define I2C_O_SIMR 0x0000080C +#define I2C_O_SRIS 0x00000810 +#define I2C_O_SMIS 0x00000814 +#define I2C_O_SICR 0x00000818 +#define I2C_O_SOAR2 0x0000081C +#define I2C_O_SACKCTL 0x00000820 +#define I2C_O_FIFODATA 0x00000F00 +#define I2C_O_FIFOCTL 0x00000F04 +#define I2C_O_FIFOSTATUS 0x00000F08 +#define I2C_O_OBSMUXSEL0 0x00000F80 +#define I2C_O_OBSMUXSEL1 0x00000F84 +#define I2C_O_MUXROUTE 0x00000F88 +#define I2C_O_PV 0x00000FB0 +#define I2C_O_PP 0x00000FC0 +#define I2C_O_PC 0x00000FC4 +#define I2C_O_CC 0x00000FC8 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//****************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_SA_S 1 +#define I2C_MSA_RS 0x00000001 // Receive not send +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//****************************************************************************** +#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_BUSY 0x00000001 // I2C Busy +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//****************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // Data Transferred +#define I2C_MDR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//****************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period +#define I2C_MTPR_TPR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//****************************************************************************** +#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt + // Mask +#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask +#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask +#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//****************************************************************************** +#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt + // Status +#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt + // Status +#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt + // Status +#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt + // Status +#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt + // Status +#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt + // Status +#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt + // Status +#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//****************************************************************************** +#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask +#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask +#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status +#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//****************************************************************************** +#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt + // Clear +#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt + // Clear +#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt + // Clear +#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt + // Clear +#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear +#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear +#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear +#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt + // Clear +#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear +#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//****************************************************************************** +#define I2C_MCR_MMD 0x00000040 // Multi-master Disable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//****************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//****************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBLEN register. +// +//****************************************************************************** +#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length +#define I2C_MBLEN_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBCNT register. +// +//****************************************************************************** +#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count +#define I2C_MBCNT_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//****************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//****************************************************************************** +#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write +#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//****************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//****************************************************************************** +#define I2C_SIMR_IM 0x00000100 // Interrupt Mask +#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask +#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//****************************************************************************** +#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status +#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt + // Status +#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt + // Status +#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//****************************************************************************** +#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt + // Status +#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt + // Status +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//****************************************************************************** +#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask +#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask +#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear +#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//****************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//****************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFODATA register. +// +//****************************************************************************** +#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte +#define I2C_FIFODATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOCTL register. +// +//****************************************************************************** +#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment +#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush +#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable +#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger +#define I2C_FIFOCTL_RXTRIG_S 16 +#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment +#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush +#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable +#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger +#define I2C_FIFOCTL_TXTRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register. +// +//****************************************************************************** +#define I2C_FIFOSTATUS_RXABVTRIG \ + 0x00040000 // RX FIFO Above Trigger Level + +#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full +#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty +#define I2C_FIFOSTATUS_TXBLWTRIG \ + 0x00000004 // TX FIFO Below Trigger Level + +#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full +#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register. +// +//****************************************************************************** +#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3 +#define I2C_OBSMUXSEL0_LN3_S 24 +#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2 +#define I2C_OBSMUXSEL0_LN2_S 16 +#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1 +#define I2C_OBSMUXSEL0_LN1_S 8 +#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0 +#define I2C_OBSMUXSEL0_LN0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register. +// +//****************************************************************************** +#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7 +#define I2C_OBSMUXSEL1_LN7_S 24 +#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6 +#define I2C_OBSMUXSEL1_LN6_S 16 +#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5 +#define I2C_OBSMUXSEL1_LN5_S 8 +#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4 +#define I2C_OBSMUXSEL1_LN4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MUXROUTE register. +// +//****************************************************************************** +#define I2C_MUXROUTE_LN7ROUTE_M \ + 0x70000000 // Lane 7 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN7ROUTE_S 28 +#define I2C_MUXROUTE_LN6ROUTE_M \ + 0x07000000 // Lane 6 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN6ROUTE_S 24 +#define I2C_MUXROUTE_LN5ROUTE_M \ + 0x00700000 // Lane 5 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN5ROUTE_S 20 +#define I2C_MUXROUTE_LN4ROUTE_M \ + 0x00070000 // Lane 4 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN4ROUTE_S 16 +#define I2C_MUXROUTE_LN3ROUTE_M \ + 0x00007000 // Lane 3 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN3ROUTE_S 12 +#define I2C_MUXROUTE_LN2ROUTE_M \ + 0x00000700 // Lane 2 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN2ROUTE_S 8 +#define I2C_MUXROUTE_LN1ROUTE_M \ + 0x00000070 // Lane 1 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN1ROUTE_S 4 +#define I2C_MUXROUTE_LN0ROUTE_M \ + 0x00000007 // Lane 0 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN0ROUTE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PV register. +// +//****************************************************************************** +#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision +#define I2C_PV_MAJOR_S 8 +#define I2C_PV_MINOR_M 0x000000FF // Minor Revision +#define I2C_PV_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//****************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//****************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_CC register. +// +//****************************************************************************** + + + +#endif // __HW_I2C_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ints.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ints.h new file mode 100644 index 0000000000..6b40193559 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ints.h @@ -0,0 +1,117 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on CC3200. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA0 16 // GPIO Port S0 +#define INT_GPIOA1 17 // GPIO Port S1 +#define INT_GPIOA2 18 // GPIO Port S2 +#define INT_GPIOA3 19 // GPIO Port S3 +#define INT_UARTA0 21 // UART0 Rx and Tx +#define INT_UARTA1 22 // UART1 Rx and Tx +#define INT_I2CA0 24 // I2C controller +#define INT_ADCCH0 30 // ADC Sequence 0 +#define INT_ADCCH1 31 // ADC Sequence 1 +#define INT_ADCCH2 32 // ADC Sequence 2 +#define INT_ADCCH3 33 // ADC Sequence 3 +#define INT_WDT 34 // Watchdog Timer0 +#define INT_TIMERA0A 35 // Timer 0 subtimer A +#define INT_TIMERA0B 36 // Timer 0 subtimer B +#define INT_TIMERA1A 37 // Timer 1 subtimer A +#define INT_TIMERA1B 38 // Timer 1 subtimer B +#define INT_TIMERA2A 39 // Timer 2 subtimer A +#define INT_TIMERA2B 40 // Timer 2 subtimer B +#define INT_FLASH 45 // FLASH Control +#define INT_TIMERA3A 51 // Timer 3 subtimer A +#define INT_TIMERA3B 52 // Timer 3 subtimer B +#define INT_UDMA 62 // uDMA controller +#define INT_UDMAERR 63 // uDMA Error +#define INT_SHA 164 // SHA +#define INT_AES 167 // AES +#define INT_DES 169 // DES +#define INT_MMCHS 175 // SDIO +#define INT_I2S 177 // McAPS +#define INT_CAMERA 179 // Camera +#define INT_NWPIC 187 // Interprocessor communication +#define INT_PRCM 188 // Power, Reset and Clock Module +#define INT_SSPI 191 // Shared SPI +#define INT_GSPI 192 // Generic SPI +#define INT_LSPI 193 // Link SPI + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 195 //The above number plus 2? + + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + + +#endif // __HW_INTS_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcasp.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcasp.h new file mode 100644 index 0000000000..c27a007797 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcasp.h @@ -0,0 +1,1706 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_MCASP_H__ +#define __HW_MCASP_H__ + +//***************************************************************************** +// +// The following are defines for the MCASP register offsets. +// +//***************************************************************************** +#define MCASP_O_PID 0x00000000 +#define MCASP_O_ESYSCONFIG 0x00000004 // Power Idle SYSCONFIG register. +#define MCASP_O_PFUNC 0x00000010 +#define MCASP_O_PDIR 0x00000014 +#define MCASP_O_PDOUT 0x00000018 +#define MCASP_O_PDSET 0x0000001C // The pin data set register + // (PDSET) is an alias of the pin + // data output register (PDOUT) for + // writes only. Writing a 1 to the + // PDSET bit sets the corresponding + // bit in PDOUT and if PFUNC = 1 + // (GPIO function) and PDIR = 1 + // (output) drives a logic high on + // the pin. +#define MCASP_O_PDIN 0x0000001C // The pin data input register + // (PDIN) holds the I/O pin state of + // each of the McASP pins. PDIN + // allows the actual value of the + // pin to be read regardless of the + // state of PFUNC and PDIR. +#define MCASP_O_PDCLR 0x00000020 // The pin data clear register + // (PDCLR) is an alias of the pin + // data output register (PDOUT) for + // writes only. Writing a 1 to the + // PDCLR bit clears the + // corresponding bit in PDOUT and if + // PFUNC = 1 (GPIO function) and + // PDIR = 1 (output) drives a logic + // low on the pin. +#define MCASP_O_TLGC 0x00000030 // for IODFT +#define MCASP_O_TLMR 0x00000034 // for IODFT +#define MCASP_O_TLEC 0x00000038 // for IODFT +#define MCASP_O_GBLCTL 0x00000044 +#define MCASP_O_AMUTE 0x00000048 +#define MCASP_O_LBCTL 0x0000004C +#define MCASP_O_TXDITCTL 0x00000050 +#define MCASP_O_GBLCTLR 0x00000060 +#define MCASP_O_RXMASK 0x00000064 +#define MCASP_O_RXFMT 0x00000068 +#define MCASP_O_RXFMCTL 0x0000006C +#define MCASP_O_ACLKRCTL 0x00000070 +#define MCASP_O_AHCLKRCTL 0x00000074 +#define MCASP_O_RXTDM 0x00000078 +#define MCASP_O_EVTCTLR 0x0000007C +#define MCASP_O_RXSTAT 0x00000080 +#define MCASP_O_RXTDMSLOT 0x00000084 +#define MCASP_O_RXCLKCHK 0x00000088 +#define MCASP_O_REVTCTL 0x0000008C +#define MCASP_O_GBLCTLX 0x000000A0 +#define MCASP_O_TXMASK 0x000000A4 +#define MCASP_O_TXFMT 0x000000A8 +#define MCASP_O_TXFMCTL 0x000000AC +#define MCASP_O_ACLKXCTL 0x000000B0 +#define MCASP_O_AHCLKXCTL 0x000000B4 +#define MCASP_O_TXTDM 0x000000B8 +#define MCASP_O_EVTCTLX 0x000000BC +#define MCASP_O_TXSTAT 0x000000C0 +#define MCASP_O_TXTDMSLOT 0x000000C4 +#define MCASP_O_TXCLKCHK 0x000000C8 +#define MCASP_O_XEVTCTL 0x000000CC +#define MCASP_O_CLKADJEN 0x000000D0 +#define MCASP_O_DITCSRA0 0x00000100 +#define MCASP_O_DITCSRA1 0x00000104 +#define MCASP_O_DITCSRA2 0x00000108 +#define MCASP_O_DITCSRA3 0x0000010C +#define MCASP_O_DITCSRA4 0x00000110 +#define MCASP_O_DITCSRA5 0x00000114 +#define MCASP_O_DITCSRB0 0x00000118 +#define MCASP_O_DITCSRB1 0x0000011C +#define MCASP_O_DITCSRB2 0x00000120 +#define MCASP_O_DITCSRB3 0x00000124 +#define MCASP_O_DITCSRB4 0x00000128 +#define MCASP_O_DITCSRB5 0x0000012C +#define MCASP_O_DITUDRA0 0x00000130 +#define MCASP_O_DITUDRA1 0x00000134 +#define MCASP_O_DITUDRA2 0x00000138 +#define MCASP_O_DITUDRA3 0x0000013C +#define MCASP_O_DITUDRA4 0x00000140 +#define MCASP_O_DITUDRA5 0x00000144 +#define MCASP_O_DITUDRB0 0x00000148 +#define MCASP_O_DITUDRB1 0x0000014C +#define MCASP_O_DITUDRB2 0x00000150 +#define MCASP_O_DITUDRB3 0x00000154 +#define MCASP_O_DITUDRB4 0x00000158 +#define MCASP_O_DITUDRB5 0x0000015C +#define MCASP_O_XRSRCTL0 0x00000180 +#define MCASP_O_XRSRCTL1 0x00000184 +#define MCASP_O_XRSRCTL2 0x00000188 +#define MCASP_O_XRSRCTL3 0x0000018C +#define MCASP_O_XRSRCTL4 0x00000190 +#define MCASP_O_XRSRCTL5 0x00000194 +#define MCASP_O_XRSRCTL6 0x00000198 +#define MCASP_O_XRSRCTL7 0x0000019C +#define MCASP_O_XRSRCTL8 0x000001A0 +#define MCASP_O_XRSRCTL9 0x000001A4 +#define MCASP_O_XRSRCTL10 0x000001A8 +#define MCASP_O_XRSRCTL11 0x000001AC +#define MCASP_O_XRSRCTL12 0x000001B0 +#define MCASP_O_XRSRCTL13 0x000001B4 +#define MCASP_O_XRSRCTL14 0x000001B8 +#define MCASP_O_XRSRCTL15 0x000001BC +#define MCASP_O_TXBUF0 0x00000200 +#define MCASP_O_TXBUF1 0x00000204 +#define MCASP_O_TXBUF2 0x00000208 +#define MCASP_O_TXBUF3 0x0000020C +#define MCASP_O_TXBUF4 0x00000210 +#define MCASP_O_TXBUF5 0x00000214 +#define MCASP_O_TXBUF6 0x00000218 +#define MCASP_O_TXBUF7 0x0000021C +#define MCASP_O_TXBUF8 0x00000220 +#define MCASP_O_TXBUF9 0x00000224 +#define MCASP_O_TXBUF10 0x00000228 +#define MCASP_O_TXBUF11 0x0000022C +#define MCASP_O_TXBUF12 0x00000230 +#define MCASP_O_TXBUF13 0x00000234 +#define MCASP_O_TXBUF14 0x00000238 +#define MCASP_O_TXBUF15 0x0000023C +#define MCASP_O_RXBUF0 0x00000280 +#define MCASP_O_RXBUF1 0x00000284 +#define MCASP_O_RXBUF2 0x00000288 +#define MCASP_O_RXBUF3 0x0000028C +#define MCASP_O_RXBUF4 0x00000290 +#define MCASP_O_RXBUF5 0x00000294 +#define MCASP_O_RXBUF6 0x00000298 +#define MCASP_O_RXBUF7 0x0000029C +#define MCASP_O_RXBUF8 0x000002A0 +#define MCASP_O_RXBUF9 0x000002A4 +#define MCASP_O_RXBUF10 0x000002A8 +#define MCASP_O_RXBUF11 0x000002AC +#define MCASP_O_RXBUF12 0x000002B0 +#define MCASP_O_RXBUF13 0x000002B4 +#define MCASP_O_RXBUF14 0x000002B8 +#define MCASP_O_RXBUF15 0x000002BC +#define MCASP_0_WFIFOCTL 0x00001000 +#define MCASP_0_WFIFOSTS 0x00001004 +#define MCASP_0_RFIFOCTL 0x00001008 +#define MCASP_0_RFIFOSTS 0x0000100C + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PID register. +// +//****************************************************************************** +#define MCASP_PID_SCHEME_M 0xC0000000 +#define MCASP_PID_SCHEME_S 30 +#define MCASP_PID_RESV_M 0x30000000 +#define MCASP_PID_RESV_S 28 +#define MCASP_PID_FUNCTION_M 0x0FFF0000 // McASP +#define MCASP_PID_FUNCTION_S 16 +#define MCASP_PID_RTL_M 0x0000F800 +#define MCASP_PID_RTL_S 11 +#define MCASP_PID_REVMAJOR_M 0x00000700 +#define MCASP_PID_REVMAJOR_S 8 +#define MCASP_PID_CUSTOM_M 0x000000C0 // non-custom +#define MCASP_PID_CUSTOM_S 6 +#define MCASP_PID_REVMINOR_M 0x0000003F +#define MCASP_PID_REVMINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCASP_O_ESYSCONFIG register. +// +//****************************************************************************** +#define MCASP_ESYSCONFIG_RSV_M 0xFFFFFFC0 // Reserved as per PDR 3.5 +#define MCASP_ESYSCONFIG_RSV_S 6 +#define MCASP_ESYSCONFIG_OTHER_M \ + 0x0000003C // Reserved for future expansion + +#define MCASP_ESYSCONFIG_OTHER_S 2 +#define MCASP_ESYSCONFIG_IDLE_MODE_M \ + 0x00000003 // Idle Mode + +#define MCASP_ESYSCONFIG_IDLE_MODE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PFUNC register. +// +//****************************************************************************** +#define MCASP_PFUNC_AFSR 0x80000000 // AFSR PFUNC 31 0 1 +#define MCASP_PFUNC_AHCLKR 0x40000000 // AHCLKR PFUNC 30 0 1 +#define MCASP_PFUNC_ACLKR 0x20000000 // ACLKR PFUNC 29 0 1 +#define MCASP_PFUNC_AFSX 0x10000000 // AFSX PFUNC 28 0 1 +#define MCASP_PFUNC_AHCLKX 0x08000000 // AHCLKX PFUNC 27 0 1 +#define MCASP_PFUNC_ACLKX 0x04000000 // ACLKX PFUNC 26 0 1 +#define MCASP_PFUNC_AMUTE 0x02000000 // AMUTE PFUNC 25 0 1 +#define MCASP_PFUNC_RESV1_M 0x01FF0000 // Reserved +#define MCASP_PFUNC_RESV1_S 16 +#define MCASP_PFUNC_AXR15 0x00008000 // AXR PFUNC BIT 15 0 1 +#define MCASP_PFUNC_AXR14 0x00004000 // AXR PFUNC BIT 14 0 1 +#define MCASP_PFUNC_AXR13 0x00002000 // AXR PFUNC BIT 13 0 1 +#define MCASP_PFUNC_AXR12 0x00001000 // AXR PFUNC BIT 12 0 1 +#define MCASP_PFUNC_AXR11 0x00000800 // AXR PFUNC BIT 11 0 1 +#define MCASP_PFUNC_AXR10 0x00000400 // AXR PFUNC BIT 10 0 1 +#define MCASP_PFUNC_AXR9 0x00000200 // AXR PFUNC BIT 9 0 1 +#define MCASP_PFUNC_AXR8 0x00000100 // AXR PFUNC BIT 8 0 1 +#define MCASP_PFUNC_AXR7 0x00000080 // AXR PFUNC BIT 7 0 1 +#define MCASP_PFUNC_AXR6 0x00000040 // AXR PFUNC BIT 6 0 1 +#define MCASP_PFUNC_AXR5 0x00000020 // AXR PFUNC BIT 5 0 1 +#define MCASP_PFUNC_AXR4 0x00000010 // AXR PFUNC BIT 4 0 1 +#define MCASP_PFUNC_AXR3 0x00000008 // AXR PFUNC BIT 3 0 1 +#define MCASP_PFUNC_AXR2 0x00000004 // AXR PFUNC BIT 2 0 1 +#define MCASP_PFUNC_AXR1 0x00000002 // AXR PFUNC BIT 1 0 1 +#define MCASP_PFUNC_AXR0 0x00000001 // AXR PFUNC BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDIR register. +// +//****************************************************************************** +#define MCASP_PDIR_AFSR 0x80000000 // AFSR PDIR 31 0 1 +#define MCASP_PDIR_AHCLKR 0x40000000 // AHCLKR PDIR 30 0 1 +#define MCASP_PDIR_ACLKR 0x20000000 // ACLKR PDIR 29 0 1 +#define MCASP_PDIR_AFSX 0x10000000 // AFSX PDIR 28 0 1 +#define MCASP_PDIR_AHCLKX 0x08000000 // AHCLKX PDIR 27 0 1 +#define MCASP_PDIR_ACLKX 0x04000000 // ACLKX PDIR 26 0 1 +#define MCASP_PDIR_AMUTE 0x02000000 // AMUTE PDIR 25 0 1 +#define MCASP_PDIR_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDIR_RESV_S 16 +#define MCASP_PDIR_AXR15 0x00008000 // AXR PDIR BIT 15 0 1 +#define MCASP_PDIR_AXR14 0x00004000 // AXR PDIR BIT 14 0 1 +#define MCASP_PDIR_AXR13 0x00002000 // AXR PDIR BIT 13 0 1 +#define MCASP_PDIR_AXR12 0x00001000 // AXR PDIR BIT 12 0 1 +#define MCASP_PDIR_AXR11 0x00000800 // AXR PDIR BIT 11 0 1 +#define MCASP_PDIR_AXR10 0x00000400 // AXR PDIR BIT 10 0 1 +#define MCASP_PDIR_AXR9 0x00000200 // AXR PDIR BIT 9 0 1 +#define MCASP_PDIR_AXR8 0x00000100 // AXR PDIR BIT 8 0 1 +#define MCASP_PDIR_AXR7 0x00000080 // AXR PDIR BIT 7 0 1 +#define MCASP_PDIR_AXR6 0x00000040 // AXR PDIR BIT 6 0 1 +#define MCASP_PDIR_AXR5 0x00000020 // AXR PDIR BIT 5 0 1 +#define MCASP_PDIR_AXR4 0x00000010 // AXR PDIR BIT 4 0 1 +#define MCASP_PDIR_AXR3 0x00000008 // AXR PDIR BIT 3 0 1 +#define MCASP_PDIR_AXR2 0x00000004 // AXR PDIR BIT 2 0 1 +#define MCASP_PDIR_AXR1 0x00000002 // AXR PDIR BIT 1 0 1 +#define MCASP_PDIR_AXR0 0x00000001 // AXR PDIR BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDOUT register. +// +//****************************************************************************** +#define MCASP_PDOUT_AFSR 0x80000000 // AFSR PDOUT 31 0 1 +#define MCASP_PDOUT_AHCLKR 0x40000000 // AHCLKR PDOUT 30 0 1 +#define MCASP_PDOUT_ACLKR 0x20000000 // ACLKR PDOUT 29 0 1 +#define MCASP_PDOUT_AFSX 0x10000000 // AFSX PDOUT 28 0 1 +#define MCASP_PDOUT_AHCLKX 0x08000000 // AHCLKX PDOUT 27 0 1 +#define MCASP_PDOUT_ACLKX 0x04000000 // ACLKX PDOUT 26 0 1 +#define MCASP_PDOUT_AMUTE 0x02000000 // AMUTE PDOUT 25 0 1 +#define MCASP_PDOUT_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDOUT_RESV_S 16 +#define MCASP_PDOUT_AXR15 0x00008000 // AXR PDOUT BIT 15 0 1 +#define MCASP_PDOUT_AXR14 0x00004000 // AXR PDOUT BIT 14 0 1 +#define MCASP_PDOUT_AXR13 0x00002000 // AXR PDOUT BIT 13 0 1 +#define MCASP_PDOUT_AXR12 0x00001000 // AXR PDOUT BIT 12 0 1 +#define MCASP_PDOUT_AXR11 0x00000800 // AXR PDOUT BIT 11 0 1 +#define MCASP_PDOUT_AXR10 0x00000400 // AXR PDOUT BIT 10 0 1 +#define MCASP_PDOUT_AXR9 0x00000200 // AXR PDOUT BIT 9 0 1 +#define MCASP_PDOUT_AXR8 0x00000100 // AXR PDOUT BIT 8 0 1 +#define MCASP_PDOUT_AXR7 0x00000080 // AXR PDOUT BIT 7 0 1 +#define MCASP_PDOUT_AXR6 0x00000040 // AXR PDOUT BIT 6 0 1 +#define MCASP_PDOUT_AXR5 0x00000020 // AXR PDOUT BIT 5 0 1 +#define MCASP_PDOUT_AXR4 0x00000010 // AXR PDOUT BIT 4 0 1 +#define MCASP_PDOUT_AXR3 0x00000008 // AXR PDOUT BIT 3 0 1 +#define MCASP_PDOUT_AXR2 0x00000004 // AXR PDOUT BIT 2 0 1 +#define MCASP_PDOUT_AXR1 0x00000002 // AXR PDOUT BIT 1 0 1 +#define MCASP_PDOUT_AXR0 0x00000001 // AXR PDOUT BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDSET register. +// +//****************************************************************************** +#define MCASP_PDSET_AFSR 0x80000000 +#define MCASP_PDSET_AHCLKR 0x40000000 +#define MCASP_PDSET_ACLKR 0x20000000 +#define MCASP_PDSET_AFSX 0x10000000 +#define MCASP_PDSET_AHCLKX 0x08000000 +#define MCASP_PDSET_ACLKX 0x04000000 +#define MCASP_PDSET_AMUTE 0x02000000 +#define MCASP_PDSET_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDSET_RESV_S 16 +#define MCASP_PDSET_AXR15 0x00008000 +#define MCASP_PDSET_AXR14 0x00004000 +#define MCASP_PDSET_AXR13 0x00002000 +#define MCASP_PDSET_AXR12 0x00001000 +#define MCASP_PDSET_AXR11 0x00000800 +#define MCASP_PDSET_AXR10 0x00000400 +#define MCASP_PDSET_AXR9 0x00000200 +#define MCASP_PDSET_AXR8 0x00000100 +#define MCASP_PDSET_AXR7 0x00000080 +#define MCASP_PDSET_AXR6 0x00000040 +#define MCASP_PDSET_AXR5 0x00000020 +#define MCASP_PDSET_AXR4 0x00000010 +#define MCASP_PDSET_AXR3 0x00000008 +#define MCASP_PDSET_AXR2 0x00000004 +#define MCASP_PDSET_AXR1 0x00000002 +#define MCASP_PDSET_AXR0 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDIN register. +// +//****************************************************************************** +#define MCASP_PDIN_AFSR 0x80000000 +#define MCASP_PDIN_AHCLKR 0x40000000 +#define MCASP_PDIN_ACLKR 0x20000000 +#define MCASP_PDIN_AFSX 0x10000000 +#define MCASP_PDIN_AHCLKX 0x08000000 +#define MCASP_PDIN_ACLKX 0x04000000 +#define MCASP_PDIN_AMUTE 0x02000000 +#define MCASP_PDIN_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDIN_RESV_S 16 +#define MCASP_PDIN_AXR15 0x00008000 +#define MCASP_PDIN_AXR14 0x00004000 +#define MCASP_PDIN_AXR13 0x00002000 +#define MCASP_PDIN_AXR12 0x00001000 +#define MCASP_PDIN_AXR11 0x00000800 +#define MCASP_PDIN_AXR10 0x00000400 +#define MCASP_PDIN_AXR9 0x00000200 +#define MCASP_PDIN_AXR8 0x00000100 +#define MCASP_PDIN_AXR7 0x00000080 +#define MCASP_PDIN_AXR6 0x00000040 +#define MCASP_PDIN_AXR5 0x00000020 +#define MCASP_PDIN_AXR4 0x00000010 +#define MCASP_PDIN_AXR3 0x00000008 +#define MCASP_PDIN_AXR2 0x00000004 +#define MCASP_PDIN_AXR1 0x00000002 +#define MCASP_PDIN_AXR0 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDCLR register. +// +//****************************************************************************** +#define MCASP_PDCLR_AFSR 0x80000000 // AFSR PDCLR 31 0 1 +#define MCASP_PDCLR_AHCLKR 0x40000000 // AHCLKR PDCLR 30 0 1 +#define MCASP_PDCLR_ACLKR 0x20000000 // ACLKR PDCLR 29 0 1 +#define MCASP_PDCLR_AFSX 0x10000000 // AFSX PDCLR 28 0 1 +#define MCASP_PDCLR_AHCLKX 0x08000000 // AHCLKX PDCLR 27 0 1 +#define MCASP_PDCLR_ACLKX 0x04000000 // ACLKX PDCLR 26 0 1 +#define MCASP_PDCLR_AMUTE 0x02000000 // AMUTE PDCLR 25 0 1 +#define MCASP_PDCLR_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDCLR_RESV_S 16 +#define MCASP_PDCLR_AXR15 0x00008000 // AXR PDCLR BIT 15 0 1 +#define MCASP_PDCLR_AXR14 0x00004000 // AXR PDCLR BIT 14 0 1 +#define MCASP_PDCLR_AXR13 0x00002000 // AXR PDCLR BIT 13 0 1 +#define MCASP_PDCLR_AXR12 0x00001000 // AXR PDCLR BIT 12 0 1 +#define MCASP_PDCLR_AXR11 0x00000800 // AXR PDCLR BIT 11 0 1 +#define MCASP_PDCLR_AXR10 0x00000400 // AXR PDCLR BIT 10 0 1 +#define MCASP_PDCLR_AXR9 0x00000200 // AXR PDCLR BIT 9 0 1 +#define MCASP_PDCLR_AXR8 0x00000100 // AXR PDCLR BIT 8 0 1 +#define MCASP_PDCLR_AXR7 0x00000080 // AXR PDCLR BIT 7 0 1 +#define MCASP_PDCLR_AXR6 0x00000040 // AXR PDCLR BIT 6 0 1 +#define MCASP_PDCLR_AXR5 0x00000020 // AXR PDCLR BIT 5 0 1 +#define MCASP_PDCLR_AXR4 0x00000010 // AXR PDCLR BIT 4 0 1 +#define MCASP_PDCLR_AXR3 0x00000008 // AXR PDCLR BIT 3 0 1 +#define MCASP_PDCLR_AXR2 0x00000004 // AXR PDCLR BIT 2 0 1 +#define MCASP_PDCLR_AXR1 0x00000002 // AXR PDCLR BIT 1 0 1 +#define MCASP_PDCLR_AXR0 0x00000001 // AXR PDCLR BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLGC register. +// +//****************************************************************************** +#define MCASP_TLGC_RESV_M 0xFFFF0000 // Reserved +#define MCASP_TLGC_RESV_S 16 +#define MCASP_TLGC_MT_M 0x0000C000 // MISR on/off trigger command 0x0 + // 0x1 0x2 0x3 +#define MCASP_TLGC_MT_S 14 +#define MCASP_TLGC_RESV1_M 0x00003E00 // Reserved +#define MCASP_TLGC_RESV1_S 9 +#define MCASP_TLGC_MMS 0x00000100 // Source of MISR input 0 1 +#define MCASP_TLGC_ESEL 0x00000080 // Output enable select 0 1 +#define MCASP_TLGC_TOEN 0x00000040 // Test output enable control. 0 1 +#define MCASP_TLGC_MC_M 0x00000030 // States of MISR 0x0 0x1 0x2 0x3 +#define MCASP_TLGC_MC_S 4 +#define MCASP_TLGC_PC_M 0x0000000E // Pattern code 0x0 0x1 0x2 0x3 0x4 + // 0x5 0x6 0x7 +#define MCASP_TLGC_PC_S 1 +#define MCASP_TLGC_TM 0x00000001 // Tie high; do not write to this + // bit 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLMR register. +// +//****************************************************************************** +#define MCASP_TLMR_TLMR_M 0xFFFFFFFF // Contains test result signature. +#define MCASP_TLMR_TLMR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLEC register. +// +//****************************************************************************** +#define MCASP_TLEC_TLEC_M 0xFFFFFFFF // Contains number of cycles during + // which MISR sig will be + // accumulated. +#define MCASP_TLEC_TLEC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTL register. +// +//****************************************************************************** +#define MCASP_GBLCTL_XFRST 0x00001000 // Frame sync generator reset 0 1 +#define MCASP_GBLCTL_XSMRST 0x00000800 // XMT state machine reset 0 1 +#define MCASP_GBLCTL_XSRCLR 0x00000400 // XMT serializer clear 0 1 +#define MCASP_GBLCTL_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 +#define MCASP_GBLCTL_XCLKRST 0x00000100 // XMT clock divder reset 0 1 +#define MCASP_GBLCTL_RFRST 0x00000010 // Frame sync generator reset 0 1 +#define MCASP_GBLCTL_RSMRST 0x00000008 // RCV state machine reset 0 1 +#define MCASP_GBLCTL_RSRCLR 0x00000004 // RCV serializer clear 0 1 +#define MCASP_GBLCTL_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 +#define MCASP_GBLCTL_RCLKRST 0x00000001 // RCV clock divder reset 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AMUTE register. +// +//****************************************************************************** +#define MCASP_AMUTE_XDMAERR 0x00001000 // MUTETXDMAERR occur 0 1 +#define MCASP_AMUTE_RDMAERR 0x00000800 // MUTERXDMAERR occur 0 1 +#define MCASP_AMUTE_XCKFAIL 0x00000400 // XMT bad clock 0 1 +#define MCASP_AMUTE_RCKFAIL 0x00000200 // RCV bad clock 0 1 +#define MCASP_AMUTE_XSYNCERR 0x00000100 // XMT unexpected FS 0 1 +#define MCASP_AMUTE_RSYNCERR 0x00000080 // RCV unexpected FS 0 1 +#define MCASP_AMUTE_XUNDRN 0x00000040 // XMT underrun occurs 0 1 +#define MCASP_AMUTE_ROVRN 0x00000020 // RCV overun occurs 0 1 +#define MCASP_AMUTE_INSTAT 0x00000010 +#define MCASP_AMUTE_INEN 0x00000008 // drive AMUTE active on mute in + // active 0 1 +#define MCASP_AMUTE_INPOL 0x00000004 // Mute input polarity 0 1 +#define MCASP_AMUTE_MUTEN_M 0x00000003 // AMUTE pin enable 0x0 0x1 0x2 +#define MCASP_AMUTE_MUTEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_LBCTL register. +// +//****************************************************************************** +#define MCASP_LBCTL_IOLBEN 0x00000010 // IO loopback enable 0 1 +#define MCASP_LBCTL_MODE_M 0x0000000C // Loop back clock source generator + // 0x0 0x1 0x2 0x3 +#define MCASP_LBCTL_MODE_S 2 +#define MCASP_LBCTL_ORD 0x00000002 // Loopback order 0 1 +#define MCASP_LBCTL_DLBEN 0x00000001 // Loop back mode 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXDITCTL register. +// +//****************************************************************************** +#define MCASP_TXDITCTL_VB 0x00000008 // Valib bit for odd TDM 0 1 +#define MCASP_TXDITCTL_VA 0x00000004 // Valib bit for even TDM 0 1 +#define MCASP_TXDITCTL_DITEN 0x00000001 // XMT DIT Mode Enable 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTLR register. +// +//****************************************************************************** +#define MCASP_GBLCTLR_XFRST 0x00001000 +#define MCASP_GBLCTLR_XSMRST 0x00000800 +#define MCASP_GBLCTLR_XSRCLR 0x00000400 +#define MCASP_GBLCTLR_XHCLKRST 0x00000200 +#define MCASP_GBLCTLR_XCLKRST 0x00000100 +#define MCASP_GBLCTLR_RFRST 0x00000010 // Frame sync generator reset 0 1 +#define MCASP_GBLCTLR_RSMRST 0x00000008 // RCV state machine reset 0 1 +#define MCASP_GBLCTLR_RSRCLR 0x00000004 // RCV serializer clear 0 1 +#define MCASP_GBLCTLR_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 +#define MCASP_GBLCTLR_RCLKRST 0x00000001 // RCV clock divder reset 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXMASK register. +// +//****************************************************************************** +#define MCASP_RXMASK_RMASK31 0x80000000 // RMASK BIT 31 0 1 +#define MCASP_RXMASK_RMASK30 0x40000000 // RMASK BIT 30 0 1 +#define MCASP_RXMASK_RMASK29 0x20000000 // RMASK BIT 29 0 1 +#define MCASP_RXMASK_RMASK28 0x10000000 // RMASK BIT 28 0 1 +#define MCASP_RXMASK_RMASK27 0x08000000 // RMASK BIT 27 0 1 +#define MCASP_RXMASK_RMASK26 0x04000000 // RMASK BIT 26 0 1 +#define MCASP_RXMASK_RMASK25 0x02000000 // RMASK BIT 25 0 1 +#define MCASP_RXMASK_RMASK24 0x01000000 // RMASK BIT 24 0 1 +#define MCASP_RXMASK_RMASK23 0x00800000 // RMASK BIT 23 0 1 +#define MCASP_RXMASK_RMASK22 0x00400000 // RMASK BIT 22 0 1 +#define MCASP_RXMASK_RMASK21 0x00200000 // RMASK BIT 21 0 1 +#define MCASP_RXMASK_RMASK20 0x00100000 // RMASK BIT 20 0 1 +#define MCASP_RXMASK_RMASK19 0x00080000 // RMASK BIT 19 0 1 +#define MCASP_RXMASK_RMASK18 0x00040000 // RMASK BIT 18 0 1 +#define MCASP_RXMASK_RMASK17 0x00020000 // RMASK BIT 17 0 1 +#define MCASP_RXMASK_RMASK16 0x00010000 // RMASK BIT 16 0 1 +#define MCASP_RXMASK_RMASK15 0x00008000 // RMASK BIT 15 0 1 +#define MCASP_RXMASK_RMASK14 0x00004000 // RMASK BIT 14 0 1 +#define MCASP_RXMASK_RMASK13 0x00002000 // RMASK BIT 13 0 1 +#define MCASP_RXMASK_RMASK12 0x00001000 // RMASK BIT 12 0 1 +#define MCASP_RXMASK_RMASK11 0x00000800 // RMASK BIT 11 0 1 +#define MCASP_RXMASK_RMASK10 0x00000400 // RMASK BIT 10 0 1 +#define MCASP_RXMASK_RMASK9 0x00000200 // RMASK BIT 9 0 1 +#define MCASP_RXMASK_RMASK8 0x00000100 // RMASK BIT 8 0 1 +#define MCASP_RXMASK_RMASK7 0x00000080 // RMASK BIT 7 0 1 +#define MCASP_RXMASK_RMASK6 0x00000040 // RMASK BIT 6 0 1 +#define MCASP_RXMASK_RMASK5 0x00000020 // RMASK BIT 5 0 1 +#define MCASP_RXMASK_RMASK4 0x00000010 // RMASK BIT 4 0 1 +#define MCASP_RXMASK_RMASK3 0x00000008 // RMASK BIT 3 0 1 +#define MCASP_RXMASK_RMASK2 0x00000004 // RMASK BIT 2 0 1 +#define MCASP_RXMASK_RMASK1 0x00000002 // RMASK BIT 1 0 1 +#define MCASP_RXMASK_RMASK0 0x00000001 // RMASK BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXFMT register. +// +//****************************************************************************** +#define MCASP_RXFMT_RDATDLY_M 0x00030000 // RCV Frame sync delay 0x0 0 Bit + // delay 0x1 1 Bit delay 0x2 2 Bit + // delay +#define MCASP_RXFMT_RDATDLY_S 16 +#define MCASP_RXFMT_RRVRS 0x00008000 // RCV serial stream bit order 0 1 +#define MCASP_RXFMT_RPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 +#define MCASP_RXFMT_RPAD_S 13 +#define MCASP_RXFMT_RPBIT_M 0x00001F00 // Pad bit position +#define MCASP_RXFMT_RPBIT_S 8 +#define MCASP_RXFMT_RSSZ_M 0x000000F0 // RCV slot Size 0x0 0x1 0x2 0x3 + // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB + // 0xC 0xD 0xE 0xF +#define MCASP_RXFMT_RSSZ_S 4 +#define MCASP_RXFMT_RBUSEL 0x00000008 // Write to RBUF using CPU/DMA 0 + // DMA port access 1 CPU port Access +#define MCASP_RXFMT_RROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 + // 0x3 0x4 0x5 0x6 0x7 +#define MCASP_RXFMT_RROT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXFMCTL register. +// +//****************************************************************************** +#define MCASP_RXFMCTL_RMOD_M 0x0000FF80 // RCV Frame sync mode +#define MCASP_RXFMCTL_RMOD_S 7 +#define MCASP_RXFMCTL_FRWID 0x00000010 // RCV Frame sync Duration 0 1 +#define MCASP_RXFMCTL_FSRM 0x00000002 // RCV frame sync External 0 1 +#define MCASP_RXFMCTL_FSRP 0x00000001 // RCV Frame sync Polarity 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_ACLKRCTL register. +// +//****************************************************************************** +#define MCASP_ACLKRCTL_BUSY 0x00100000 +#define MCASP_ACLKRCTL_DIVBUSY 0x00080000 +#define MCASP_ACLKRCTL_ADJBUSY 0x00040000 +#define MCASP_ACLKRCTL_CLKRADJ_M \ + 0x00030000 + +#define MCASP_ACLKRCTL_CLKRADJ_S 16 +#define MCASP_ACLKRCTL_CLKRP 0x00000080 // RCV Clock Polarity 0 1 +#define MCASP_ACLKRCTL_CLKRM 0x00000020 // RCV clock source 0 1 +#define MCASP_ACLKRCTL_CLKRDIV_M \ + 0x0000001F // RCV clock devide ratio + +#define MCASP_ACLKRCTL_CLKRDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register. +// +//****************************************************************************** +#define MCASP_AHCLKRCTL_BUSY 0x00100000 +#define MCASP_AHCLKRCTL_DIVBUSY 0x00080000 +#define MCASP_AHCLKRCTL_ADJBUSY 0x00040000 +#define MCASP_AHCLKRCTL_HCLKRADJ_M \ + 0x00030000 + +#define MCASP_AHCLKRCTL_HCLKRADJ_S 16 +#define MCASP_AHCLKRCTL_HCLKRM 0x00008000 // High Freq. RCV clock Source 0 1 +#define MCASP_AHCLKRCTL_HCLKRP 0x00004000 // High Freq. clock Polarity Before + // diviser 0 1 +#define MCASP_AHCLKRCTL_HCLKRDIV_M \ + 0x00000FFF // RCV clock Divide Ratio + +#define MCASP_AHCLKRCTL_HCLKRDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXTDM register. +// +//****************************************************************************** +#define MCASP_RXTDM_RTDMS31 0x80000000 // RCV mode during TDM time slot 31 + // 0 1 +#define MCASP_RXTDM_RTDMS30 0x40000000 // RCV mode during TDM time slot 30 + // 0 1 +#define MCASP_RXTDM_RTDMS29 0x20000000 // RCV mode during TDM time slot 29 + // 0 1 +#define MCASP_RXTDM_RTDMS28 0x10000000 // RCV mode during TDM time slot 28 + // 0 1 +#define MCASP_RXTDM_RTDMS27 0x08000000 // RCV mode during TDM time slot 27 + // 0 1 +#define MCASP_RXTDM_RTDMS26 0x04000000 // RCV mode during TDM time slot 26 + // 0 1 +#define MCASP_RXTDM_RTDMS25 0x02000000 // RCV mode during TDM time slot 25 + // 0 1 +#define MCASP_RXTDM_RTDMS24 0x01000000 // RCV mode during TDM time slot 24 + // 0 1 +#define MCASP_RXTDM_RTDMS23 0x00800000 // RCV mode during TDM time slot 23 + // 0 1 +#define MCASP_RXTDM_RTDMS22 0x00400000 // RCV mode during TDM time slot 22 + // 0 1 +#define MCASP_RXTDM_RTDMS21 0x00200000 // RCV mode during TDM time slot 21 + // 0 1 +#define MCASP_RXTDM_RTDMS20 0x00100000 // RCV mode during TDM time slot 20 + // 0 1 +#define MCASP_RXTDM_RTDMS19 0x00080000 // RCV mode during TDM time slot 19 + // 0 1 +#define MCASP_RXTDM_RTDMS18 0x00040000 // RCV mode during TDM time slot 18 + // 0 1 +#define MCASP_RXTDM_RTDMS17 0x00020000 // RCV mode during TDM time slot 17 + // 0 1 +#define MCASP_RXTDM_RTDMS16 0x00010000 // RCV mode during TDM time slot 16 + // 0 1 +#define MCASP_RXTDM_RTDMS15 0x00008000 // RCV mode during TDM time slot 15 + // 0 1 +#define MCASP_RXTDM_RTDMS14 0x00004000 // RCV mode during TDM time slot 14 + // 0 1 +#define MCASP_RXTDM_RTDMS13 0x00002000 // RCV mode during TDM time slot 13 + // 0 1 +#define MCASP_RXTDM_RTDMS12 0x00001000 // RCV mode during TDM time slot 12 + // 0 1 +#define MCASP_RXTDM_RTDMS11 0x00000800 // RCV mode during TDM time slot 11 + // 0 1 +#define MCASP_RXTDM_RTDMS10 0x00000400 // RCV mode during TDM time slot 10 + // 0 1 +#define MCASP_RXTDM_RTDMS9 0x00000200 // RCV mode during TDM time slot 9 + // 0 1 +#define MCASP_RXTDM_RTDMS8 0x00000100 // RCV mode during TDM time slot 8 + // 0 1 +#define MCASP_RXTDM_RTDMS7 0x00000080 // RCV mode during TDM time slot 7 + // 0 1 +#define MCASP_RXTDM_RTDMS6 0x00000040 // RCV mode during TDM time slot 6 + // 0 1 +#define MCASP_RXTDM_RTDMS5 0x00000020 // RCV mode during TDM time slot 5 + // 0 1 +#define MCASP_RXTDM_RTDMS4 0x00000010 // RCV mode during TDM time slot 4 + // 0 1 +#define MCASP_RXTDM_RTDMS3 0x00000008 // RCV mode during TDM time slot 3 + // 0 1 +#define MCASP_RXTDM_RTDMS2 0x00000004 // RCV mode during TDM time slot 2 + // 0 1 +#define MCASP_RXTDM_RTDMS1 0x00000002 // RCV mode during TDM time slot 1 + // 0 1 +#define MCASP_RXTDM_RTDMS0 0x00000001 // RCV mode during TDM time slot 0 + // 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_EVTCTLR register. +// +//****************************************************************************** +#define MCASP_EVTCTLR_RSTAFRM 0x00000080 // RCV Start of Frame Interrupt 0 1 +#define MCASP_EVTCTLR_RDATA 0x00000020 // RCV Data Interrupt 0 1 +#define MCASP_EVTCTLR_RLAST 0x00000010 // RCV Last Slot Interrupt 0 1 +#define MCASP_EVTCTLR_RDMAERR 0x00000008 // RCV DMA Bus Error 0 1 +#define MCASP_EVTCTLR_RCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 +#define MCASP_EVTCTLR_RSYNCERR 0x00000002 // RCV Unexpected FSR Interrupt 0 1 +#define MCASP_EVTCTLR_ROVRN 0x00000001 // RCV Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXSTAT register. +// +//****************************************************************************** +#define MCASP_RXSTAT_RERR 0x00000100 // RCV Error 0 1 +#define MCASP_RXSTAT_RDMAERR 0x00000080 // RCV DMA bus error 0 1 +#define MCASP_RXSTAT_RSTAFRM 0x00000040 // Start of Frame-RCV 0 1 +#define MCASP_RXSTAT_RDATA 0x00000020 // Data Ready Flag 0 1 +#define MCASP_RXSTAT_RLAST 0x00000010 // Last Slot Interrupt Flag 0 1 +#define MCASP_RXSTAT_RTDMSLOT 0x00000008 // EvenOdd Slot 0 1 +#define MCASP_RXSTAT_RCKFAIL 0x00000004 // Bad Transmit Flag 0 1 +#define MCASP_RXSTAT_RSYNCERR 0x00000002 // Unexpected RCV Frame sync flag 0 + // 1 +#define MCASP_RXSTAT_ROVRN 0x00000001 // RCV Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register. +// +//****************************************************************************** +#define MCASP_RXTDMSLOT_RSLOTCNT_M \ + 0x000003FF // Current RCV time slot count + +#define MCASP_RXTDMSLOT_RSLOTCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXCLKCHK register. +// +//****************************************************************************** +#define MCASP_RXCLKCHK_RCNT_M 0xFF000000 // RCV clock count value +#define MCASP_RXCLKCHK_RCNT_S 24 +#define MCASP_RXCLKCHK_RMAX_M 0x00FF0000 // RCV clock maximum boundary +#define MCASP_RXCLKCHK_RMAX_S 16 +#define MCASP_RXCLKCHK_RMIN_M 0x0000FF00 // RCV clock minimum boundary +#define MCASP_RXCLKCHK_RMIN_S 8 +#define MCASP_RXCLKCHK_RPS_M 0x0000000F // RCV clock check prescaler 0x0 + // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 +#define MCASP_RXCLKCHK_RPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_REVTCTL register. +// +//****************************************************************************** +#define MCASP_REVTCTL_RDATDMA 0x00000001 // RCV data DMA request 0 Enable + // DMA Transfer 1 Disable DMA + // Transfer +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTLX register. +// +//****************************************************************************** +#define MCASP_GBLCTLX_XFRST 0x00001000 // Frame sync generator reset 0 1 +#define MCASP_GBLCTLX_XSMRST 0x00000800 // XMT state machine reset 0 1 +#define MCASP_GBLCTLX_XSRCLR 0x00000400 // XMT serializer clear 0 1 +#define MCASP_GBLCTLX_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 +#define MCASP_GBLCTLX_XCLKRST 0x00000100 // XMT clock divder reset 0 1 +#define MCASP_GBLCTLX_RFRST 0x00000010 +#define MCASP_GBLCTLX_RSMRST 0x00000008 +#define MCASP_GBLCTLX_RSRCLKR 0x00000004 +#define MCASP_GBLCTLX_RHCLKRST 0x00000002 +#define MCASP_GBLCTLX_RCLKRST 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXMASK register. +// +//****************************************************************************** +#define MCASP_TXMASK_XMASK31 0x80000000 // XMASK BIT 31 0 1 +#define MCASP_TXMASK_XMASK30 0x40000000 // XMASK BIT 30 0 1 +#define MCASP_TXMASK_XMASK29 0x20000000 // XMASK BIT 29 0 1 +#define MCASP_TXMASK_XMASK28 0x10000000 // XMASK BIT 28 0 1 +#define MCASP_TXMASK_XMASK27 0x08000000 // XMASK BIT 27 0 1 +#define MCASP_TXMASK_XMASK26 0x04000000 // XMASK BIT 26 0 1 +#define MCASP_TXMASK_XMASK25 0x02000000 // XMASK BIT 25 0 1 +#define MCASP_TXMASK_XMASK24 0x01000000 // XMASK BIT 24 0 1 +#define MCASP_TXMASK_XMASK23 0x00800000 // XMASK BIT 23 0 1 +#define MCASP_TXMASK_XMASK22 0x00400000 // XMASK BIT 22 0 1 +#define MCASP_TXMASK_XMASK21 0x00200000 // XMASK BIT 21 0 1 +#define MCASP_TXMASK_XMASK20 0x00100000 // XMASK BIT 20 0 1 +#define MCASP_TXMASK_XMASK19 0x00080000 // XMASK BIT 19 0 1 +#define MCASP_TXMASK_XMASK18 0x00040000 // XMASK BIT 18 0 1 +#define MCASP_TXMASK_XMASK17 0x00020000 // XMASK BIT 17 0 1 +#define MCASP_TXMASK_XMASK16 0x00010000 // XMASK BIT 16 0 1 +#define MCASP_TXMASK_XMASK15 0x00008000 // XMASK BIT 15 0 1 +#define MCASP_TXMASK_XMASK14 0x00004000 // XMASK BIT 14 0 1 +#define MCASP_TXMASK_XMASK13 0x00002000 // XMASK BIT 13 0 1 +#define MCASP_TXMASK_XMASK12 0x00001000 // XMASK BIT 12 0 1 +#define MCASP_TXMASK_XMASK11 0x00000800 // XMASK BIT 11 0 1 +#define MCASP_TXMASK_XMASK10 0x00000400 // XMASK BIT 10 0 1 +#define MCASP_TXMASK_XMASK9 0x00000200 // XMASK BIT 9 0 1 +#define MCASP_TXMASK_XMASK8 0x00000100 // XMASK BIT 8 0 1 +#define MCASP_TXMASK_XMASK7 0x00000080 // XMASK BIT 7 0 1 +#define MCASP_TXMASK_XMASK6 0x00000040 // XMASK BIT 6 0 1 +#define MCASP_TXMASK_XMASK5 0x00000020 // XMASK BIT 5 0 1 +#define MCASP_TXMASK_XMASK4 0x00000010 // XMASK BIT 4 0 1 +#define MCASP_TXMASK_XMASK3 0x00000008 // XMASK BIT 3 0 1 +#define MCASP_TXMASK_XMASK2 0x00000004 // XMASK BIT 2 0 1 +#define MCASP_TXMASK_XMASK1 0x00000002 // XMASK BIT 1 0 1 +#define MCASP_TXMASK_XMASK0 0x00000001 // XMASK BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXFMT register. +// +//****************************************************************************** +#define MCASP_TXFMT_XDATDLY_M 0x00030000 // XMT Frame sync delay 0x0 0 Bit + // delay 0x1 1 Bit delay 0x2 2 Bit + // delay +#define MCASP_TXFMT_XDATDLY_S 16 +#define MCASP_TXFMT_XRVRS 0x00008000 // XMT serial stream bit order 0 1 +#define MCASP_TXFMT_XPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 +#define MCASP_TXFMT_XPAD_S 13 +#define MCASP_TXFMT_XPBIT_M 0x00001F00 // Pad bit position +#define MCASP_TXFMT_XPBIT_S 8 +#define MCASP_TXFMT_XSSZ_M 0x000000F0 // XMT slot Size 0x0 0x1 0x2 0x3 + // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB + // 0xC 0xD 0xE 0xF +#define MCASP_TXFMT_XSSZ_S 4 +#define MCASP_TXFMT_XBUSEL 0x00000008 // Write to XBUF using CPU/DMA 0 + // DMA port access 1 CPU port Access +#define MCASP_TXFMT_XROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 + // 0x3 0x4 0x5 0x6 0x7 +#define MCASP_TXFMT_XROT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXFMCTL register. +// +//****************************************************************************** +#define MCASP_TXFMCTL_XMOD_M 0x0000FF80 // XMT Frame sync mode +#define MCASP_TXFMCTL_XMOD_S 7 +#define MCASP_TXFMCTL_FXWID 0x00000010 // XMT Frame sync Duration 0 1 +#define MCASP_TXFMCTL_FSXM 0x00000002 // XMT frame sync External 0 1 +#define MCASP_TXFMCTL_FSXP 0x00000001 // XMT Frame sync Polarity 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_ACLKXCTL register. +// +//****************************************************************************** +#define MCASP_ACLKXCTL_BUSY 0x00100000 +#define MCASP_ACLKXCTL_DIVBUSY 0x00080000 +#define MCASP_ACLKXCTL_ADJBUSY 0x00040000 +#define MCASP_ACLKXCTL_CLKXADJ_M \ + 0x00030000 + +#define MCASP_ACLKXCTL_CLKXADJ_S 16 +#define MCASP_ACLKXCTL_CLKXP 0x00000080 // XMT Clock Polarity 0 1 +#define MCASP_ACLKXCTL_ASYNC 0x00000040 // XMT/RCV operation sync /Async 0 + // 1 +#define MCASP_ACLKXCTL_CLKXM 0x00000020 // XMT clock source 0 1 +#define MCASP_ACLKXCTL_CLKXDIV_M \ + 0x0000001F // XMT clock devide ratio + +#define MCASP_ACLKXCTL_CLKXDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register. +// +//****************************************************************************** +#define MCASP_AHCLKXCTL_BUSY 0x00100000 +#define MCASP_AHCLKXCTL_DIVBUSY 0x00080000 +#define MCASP_AHCLKXCTL_ADJBUSY 0x00040000 +#define MCASP_AHCLKXCTL_HCLKXADJ_M \ + 0x00030000 + +#define MCASP_AHCLKXCTL_HCLKXADJ_S 16 +#define MCASP_AHCLKXCTL_HCLKXM 0x00008000 // High Freq. XMT clock Source 0 1 +#define MCASP_AHCLKXCTL_HCLKXP 0x00004000 // High Freq. clock Polarity Before + // diviser 0 1 +#define MCASP_AHCLKXCTL_HCLKXDIV_M \ + 0x00000FFF // XMT clock Divide Ratio + +#define MCASP_AHCLKXCTL_HCLKXDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXTDM register. +// +//****************************************************************************** +#define MCASP_TXTDM_XTDMS31 0x80000000 // XMT mode during TDM time slot 31 + // 0 1 +#define MCASP_TXTDM_XTDMS30 0x40000000 // XMT mode during TDM time slot 30 + // 0 1 +#define MCASP_TXTDM_XTDMS29 0x20000000 // XMT mode during TDM time slot 29 + // 0 1 +#define MCASP_TXTDM_XTDMS28 0x10000000 // XMT mode during TDM time slot 28 + // 0 1 +#define MCASP_TXTDM_XTDMS27 0x08000000 // XMT mode during TDM time slot 27 + // 0 1 +#define MCASP_TXTDM_XTDMS26 0x04000000 // XMT mode during TDM time slot 26 + // 0 1 +#define MCASP_TXTDM_XTDMS25 0x02000000 // XMT mode during TDM time slot 25 + // 0 1 +#define MCASP_TXTDM_XTDMS24 0x01000000 // XMT mode during TDM time slot 24 + // 0 1 +#define MCASP_TXTDM_XTDMS23 0x00800000 // XMT mode during TDM time slot 23 + // 0 1 +#define MCASP_TXTDM_XTDMS22 0x00400000 // XMT mode during TDM time slot 22 + // 0 1 +#define MCASP_TXTDM_XTDMS21 0x00200000 // XMT mode during TDM time slot 21 + // 0 1 +#define MCASP_TXTDM_XTDMS20 0x00100000 // XMT mode during TDM time slot 20 + // 0 1 +#define MCASP_TXTDM_XTDMS19 0x00080000 // XMT mode during TDM time slot 19 + // 0 1 +#define MCASP_TXTDM_XTDMS18 0x00040000 // XMT mode during TDM time slot 18 + // 0 1 +#define MCASP_TXTDM_XTDMS17 0x00020000 // XMT mode during TDM time slot 17 + // 0 1 +#define MCASP_TXTDM_XTDMS16 0x00010000 // XMT mode during TDM time slot 16 + // 0 1 +#define MCASP_TXTDM_XTDMS15 0x00008000 // XMT mode during TDM time slot 15 + // 0 1 +#define MCASP_TXTDM_XTDMS14 0x00004000 // XMT mode during TDM time slot 14 + // 0 1 +#define MCASP_TXTDM_XTDMS13 0x00002000 // XMT mode during TDM time slot 13 + // 0 1 +#define MCASP_TXTDM_XTDMS12 0x00001000 // XMT mode during TDM time slot 12 + // 0 1 +#define MCASP_TXTDM_XTDMS11 0x00000800 // XMT mode during TDM time slot 11 + // 0 1 +#define MCASP_TXTDM_XTDMS10 0x00000400 // XMT mode during TDM time slot 10 + // 0 1 +#define MCASP_TXTDM_XTDMS9 0x00000200 // XMT mode during TDM time slot 9 + // 0 1 +#define MCASP_TXTDM_XTDMS8 0x00000100 // XMT mode during TDM time slot 8 + // 0 1 +#define MCASP_TXTDM_XTDMS7 0x00000080 // XMT mode during TDM time slot 7 + // 0 1 +#define MCASP_TXTDM_XTDMS6 0x00000040 // XMT mode during TDM time slot 6 + // 0 1 +#define MCASP_TXTDM_XTDMS5 0x00000020 // XMT mode during TDM time slot 5 + // 0 1 +#define MCASP_TXTDM_XTDMS4 0x00000010 // XMT mode during TDM time slot 4 + // 0 1 +#define MCASP_TXTDM_XTDMS3 0x00000008 // XMT mode during TDM time slot 3 + // 0 1 +#define MCASP_TXTDM_XTDMS2 0x00000004 // XMT mode during TDM time slot 2 + // 0 1 +#define MCASP_TXTDM_XTDMS1 0x00000002 // XMT mode during TDM time slot 1 + // 0 1 +#define MCASP_TXTDM_XTDMS0 0x00000001 // XMT mode during TDM time slot 0 + // 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_EVTCTLX register. +// +//****************************************************************************** +#define MCASP_EVTCTLX_XSTAFRM 0x00000080 // XMT Start of Frame Interrupt 0 1 +#define MCASP_EVTCTLX_XDATA 0x00000020 // XMT Data Interrupt 0 1 +#define MCASP_EVTCTLX_XLAST 0x00000010 // XMT Last Slot Interrupt 0 1 +#define MCASP_EVTCTLX_XDMAERR 0x00000008 // XMT DMA Bus Error 0 1 +#define MCASP_EVTCTLX_XCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 +#define MCASP_EVTCTLX_XSYNCERR 0x00000002 // XMT Unexpected FSR Interrupt 0 1 +#define MCASP_EVTCTLX_XUNDRN 0x00000001 // XMT Underrun Interrupt 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXSTAT register. +// +//****************************************************************************** +#define MCASP_TXSTAT_XERR 0x00000100 // XMT Error 0 1 +#define MCASP_TXSTAT_XDMAERR 0x00000080 // XMT DMA bus error 0 1 +#define MCASP_TXSTAT_XSTAFRM 0x00000040 // Start of Frame-XMT 0 1 +#define MCASP_TXSTAT_XDATA 0x00000020 // Data Ready Flag 0 1 +#define MCASP_TXSTAT_XLAST 0x00000010 // Last Slot Interrupt Flag 0 1 +#define MCASP_TXSTAT_XTDMSLOT 0x00000008 // EvenOdd Slot 0 1 +#define MCASP_TXSTAT_XCKFAIL 0x00000004 // Bad Transmit Flag 0 1 +#define MCASP_TXSTAT_XSYNCERR 0x00000002 // Unexpected XMT Frame sync flag 0 + // 1 +#define MCASP_TXSTAT_XUNDRN 0x00000001 // XMT Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register. +// +//****************************************************************************** +#define MCASP_TXTDMSLOT_XSLOTCNT_M \ + 0x000003FF // Current XMT time slot count + // during reset the value of this + // register is 0b0101111111 (0x17f) + // and after reset 0 + +#define MCASP_TXTDMSLOT_XSLOTCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXCLKCHK register. +// +//****************************************************************************** +#define MCASP_TXCLKCHK_XCNT_M 0xFF000000 // XMT clock count value +#define MCASP_TXCLKCHK_XCNT_S 24 +#define MCASP_TXCLKCHK_XMAX_M 0x00FF0000 // XMT clock maximum boundary +#define MCASP_TXCLKCHK_XMAX_S 16 +#define MCASP_TXCLKCHK_XMIN_M 0x0000FF00 // XMT clock minimum boundary +#define MCASP_TXCLKCHK_XMIN_S 8 +#define MCASP_TXCLKCHK_RESV 0x00000080 // Reserved +#define MCASP_TXCLKCHK_XPS_M 0x0000000F // XMT clock check prescaler 0x0 + // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 +#define MCASP_TXCLKCHK_XPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XEVTCTL register. +// +//****************************************************************************** +#define MCASP_XEVTCTL_XDATDMA 0x00000001 // XMT data DMA request 0 Enable + // DMA Transfer 1 Disable DMA + // Transfer +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_CLKADJEN register. +// +//****************************************************************************** +#define MCASP_CLKADJEN_ENABLE 0x00000001 // One-shot clock adjust enable 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA0 register. +// +//****************************************************************************** +#define MCASP_DITCSRA0_DITCSRA0_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA0_DITCSRA0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA1 register. +// +//****************************************************************************** +#define MCASP_DITCSRA1_DITCSRA1_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA1_DITCSRA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA2 register. +// +//****************************************************************************** +#define MCASP_DITCSRA2_DITCSRA2_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status Register + +#define MCASP_DITCSRA2_DITCSRA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA3 register. +// +//****************************************************************************** +#define MCASP_DITCSRA3_DITCSRA3_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status Register + +#define MCASP_DITCSRA3_DITCSRA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA4 register. +// +//****************************************************************************** +#define MCASP_DITCSRA4_DITCSRA4_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA4_DITCSRA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA5 register. +// +//****************************************************************************** +#define MCASP_DITCSRA5_DITCSRA5_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA5_DITCSRA5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB0 register. +// +//****************************************************************************** +#define MCASP_DITCSRB0_DITCSRB0_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB0_DITCSRB0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB1 register. +// +//****************************************************************************** +#define MCASP_DITCSRB1_DITCSRB1_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB1_DITCSRB1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB2 register. +// +//****************************************************************************** +#define MCASP_DITCSRB2_DITCSRB2_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB2_DITCSRB2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB3 register. +// +//****************************************************************************** +#define MCASP_DITCSRB3_DITCSRB3_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB3_DITCSRB3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB4 register. +// +//****************************************************************************** +#define MCASP_DITCSRB4_DITCSRB4_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB4_DITCSRB4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB5 register. +// +//****************************************************************************** +#define MCASP_DITCSRB5_DITCSRB5_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB5_DITCSRB5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA0 register. +// +//****************************************************************************** +#define MCASP_DITUDRA0_DITUDRA0_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA0_DITUDRA0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA1 register. +// +//****************************************************************************** +#define MCASP_DITUDRA1_DITUDRA1_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA1_DITUDRA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA2 register. +// +//****************************************************************************** +#define MCASP_DITUDRA2_DITUDRA2_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA2_DITUDRA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA3 register. +// +//****************************************************************************** +#define MCASP_DITUDRA3_DITUDRA3_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA3_DITUDRA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA4 register. +// +//****************************************************************************** +#define MCASP_DITUDRA4_DITUDRA4_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA4_DITUDRA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA5 register. +// +//****************************************************************************** +#define MCASP_DITUDRA5_DITUDRA5_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA5_DITUDRA5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB0 register. +// +//****************************************************************************** +#define MCASP_DITUDRB0_DITUDRB0_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB0_DITUDRB0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB1 register. +// +//****************************************************************************** +#define MCASP_DITUDRB1_DITUDRB1_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB1_DITUDRB1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB2 register. +// +//****************************************************************************** +#define MCASP_DITUDRB2_DITUDRB2_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB2_DITUDRB2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB3 register. +// +//****************************************************************************** +#define MCASP_DITUDRB3_DITUDRB3_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB3_DITUDRB3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB4 register. +// +//****************************************************************************** +#define MCASP_DITUDRB4_DITUDRB4_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB4_DITUDRB4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB5 register. +// +//****************************************************************************** +#define MCASP_DITUDRB5_DITUDRB5_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB5_DITUDRB5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL0_RRDY 0x00000020 +#define MCASP_XRSRCTL0_XRDY 0x00000010 +#define MCASP_XRSRCTL0_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL0_DISMOD_S 2 +#define MCASP_XRSRCTL0_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL0_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL1_RRDY 0x00000020 +#define MCASP_XRSRCTL1_XRDY 0x00000010 +#define MCASP_XRSRCTL1_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL1_DISMOD_S 2 +#define MCASP_XRSRCTL1_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL1_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL2_RRDY 0x00000020 +#define MCASP_XRSRCTL2_XRDY 0x00000010 +#define MCASP_XRSRCTL2_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL2_DISMOD_S 2 +#define MCASP_XRSRCTL2_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL2_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL3_RRDY 0x00000020 +#define MCASP_XRSRCTL3_XRDY 0x00000010 +#define MCASP_XRSRCTL3_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL3_DISMOD_S 2 +#define MCASP_XRSRCTL3_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL3_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL4_RRDY 0x00000020 +#define MCASP_XRSRCTL4_XRDY 0x00000010 +#define MCASP_XRSRCTL4_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL4_DISMOD_S 2 +#define MCASP_XRSRCTL4_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL4_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL5_RRDY 0x00000020 +#define MCASP_XRSRCTL5_XRDY 0x00000010 +#define MCASP_XRSRCTL5_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL5_DISMOD_S 2 +#define MCASP_XRSRCTL5_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL5_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL6_RRDY 0x00000020 +#define MCASP_XRSRCTL6_XRDY 0x00000010 +#define MCASP_XRSRCTL6_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL6_DISMOD_S 2 +#define MCASP_XRSRCTL6_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL6_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL7_RRDY 0x00000020 +#define MCASP_XRSRCTL7_XRDY 0x00000010 +#define MCASP_XRSRCTL7_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL7_DISMOD_S 2 +#define MCASP_XRSRCTL7_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL7_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL8_RRDY 0x00000020 +#define MCASP_XRSRCTL8_XRDY 0x00000010 +#define MCASP_XRSRCTL8_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL8_DISMOD_S 2 +#define MCASP_XRSRCTL8_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL8_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL9_RRDY 0x00000020 +#define MCASP_XRSRCTL9_XRDY 0x00000010 +#define MCASP_XRSRCTL9_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL9_DISMOD_S 2 +#define MCASP_XRSRCTL9_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL9_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL10_RRDY 0x00000020 +#define MCASP_XRSRCTL10_XRDY 0x00000010 +#define MCASP_XRSRCTL10_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL10_DISMOD_S 2 +#define MCASP_XRSRCTL10_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL10_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL11_RRDY 0x00000020 +#define MCASP_XRSRCTL11_XRDY 0x00000010 +#define MCASP_XRSRCTL11_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL11_DISMOD_S 2 +#define MCASP_XRSRCTL11_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL11_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL12_RRDY 0x00000020 +#define MCASP_XRSRCTL12_XRDY 0x00000010 +#define MCASP_XRSRCTL12_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL12_DISMOD_S 2 +#define MCASP_XRSRCTL12_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL12_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL13_RRDY 0x00000020 +#define MCASP_XRSRCTL13_XRDY 0x00000010 +#define MCASP_XRSRCTL13_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL13_DISMOD_S 2 +#define MCASP_XRSRCTL13_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL13_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL14_RRDY 0x00000020 +#define MCASP_XRSRCTL14_XRDY 0x00000010 +#define MCASP_XRSRCTL14_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL14_DISMOD_S 2 +#define MCASP_XRSRCTL14_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL14_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL15_RRDY 0x00000020 +#define MCASP_XRSRCTL15_XRDY 0x00000010 +#define MCASP_XRSRCTL15_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL15_DISMOD_S 2 +#define MCASP_XRSRCTL15_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL15_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF0 register. +// +//****************************************************************************** +#define MCASP_TXBUF0_XBUF0_M 0xFFFFFFFF // Transmit Buffer 0 +#define MCASP_TXBUF0_XBUF0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF1 register. +// +//****************************************************************************** +#define MCASP_TXBUF1_XBUF1_M 0xFFFFFFFF // Transmit Buffer 1 +#define MCASP_TXBUF1_XBUF1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF2 register. +// +//****************************************************************************** +#define MCASP_TXBUF2_XBUF2_M 0xFFFFFFFF // Transmit Buffer 2 +#define MCASP_TXBUF2_XBUF2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF3 register. +// +//****************************************************************************** +#define MCASP_TXBUF3_XBUF3_M 0xFFFFFFFF // Transmit Buffer 3 +#define MCASP_TXBUF3_XBUF3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF4 register. +// +//****************************************************************************** +#define MCASP_TXBUF4_XBUF4_M 0xFFFFFFFF // Transmit Buffer 4 +#define MCASP_TXBUF4_XBUF4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF5 register. +// +//****************************************************************************** +#define MCASP_TXBUF5_XBUF5_M 0xFFFFFFFF // Transmit Buffer 5 +#define MCASP_TXBUF5_XBUF5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF6 register. +// +//****************************************************************************** +#define MCASP_TXBUF6_XBUF6_M 0xFFFFFFFF // Transmit Buffer 6 +#define MCASP_TXBUF6_XBUF6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF7 register. +// +//****************************************************************************** +#define MCASP_TXBUF7_XBUF7_M 0xFFFFFFFF // Transmit Buffer 7 +#define MCASP_TXBUF7_XBUF7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF8 register. +// +//****************************************************************************** +#define MCASP_TXBUF8_XBUF8_M 0xFFFFFFFF // Transmit Buffer 8 +#define MCASP_TXBUF8_XBUF8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF9 register. +// +//****************************************************************************** +#define MCASP_TXBUF9_XBUF9_M 0xFFFFFFFF // Transmit Buffer 9 +#define MCASP_TXBUF9_XBUF9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF10 register. +// +//****************************************************************************** +#define MCASP_TXBUF10_XBUF10_M 0xFFFFFFFF // Transmit Buffer 10 +#define MCASP_TXBUF10_XBUF10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF11 register. +// +//****************************************************************************** +#define MCASP_TXBUF11_XBUF11_M 0xFFFFFFFF // Transmit Buffer 11 +#define MCASP_TXBUF11_XBUF11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF12 register. +// +//****************************************************************************** +#define MCASP_TXBUF12_XBUF12_M 0xFFFFFFFF // Transmit Buffer 12 +#define MCASP_TXBUF12_XBUF12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF13 register. +// +//****************************************************************************** +#define MCASP_TXBUF13_XBUF13_M 0xFFFFFFFF // Transmit Buffer 13 +#define MCASP_TXBUF13_XBUF13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF14 register. +// +//****************************************************************************** +#define MCASP_TXBUF14_XBUF14_M 0xFFFFFFFF // Transmit Buffer 14 +#define MCASP_TXBUF14_XBUF14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF15 register. +// +//****************************************************************************** +#define MCASP_TXBUF15_XBUF15_M 0xFFFFFFFF // Transmit Buffer 15 +#define MCASP_TXBUF15_XBUF15_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF0 register. +// +//****************************************************************************** +#define MCASP_RXBUF0_RBUF0_M 0xFFFFFFFF // Receive Buffer 0 +#define MCASP_RXBUF0_RBUF0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF1 register. +// +//****************************************************************************** +#define MCASP_RXBUF1_RBUF1_M 0xFFFFFFFF // Receive Buffer 1 +#define MCASP_RXBUF1_RBUF1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF2 register. +// +//****************************************************************************** +#define MCASP_RXBUF2_RBUF2_M 0xFFFFFFFF // Receive Buffer 2 +#define MCASP_RXBUF2_RBUF2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF3 register. +// +//****************************************************************************** +#define MCASP_RXBUF3_RBUF3_M 0xFFFFFFFF // Receive Buffer 3 +#define MCASP_RXBUF3_RBUF3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF4 register. +// +//****************************************************************************** +#define MCASP_RXBUF4_RBUF4_M 0xFFFFFFFF // Receive Buffer 4 +#define MCASP_RXBUF4_RBUF4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF5 register. +// +//****************************************************************************** +#define MCASP_RXBUF5_RBUF5_M 0xFFFFFFFF // Receive Buffer 5 +#define MCASP_RXBUF5_RBUF5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF6 register. +// +//****************************************************************************** +#define MCASP_RXBUF6_RBUF6_M 0xFFFFFFFF // Receive Buffer 6 +#define MCASP_RXBUF6_RBUF6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF7 register. +// +//****************************************************************************** +#define MCASP_RXBUF7_RBUF7_M 0xFFFFFFFF // Receive Buffer 7 +#define MCASP_RXBUF7_RBUF7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF8 register. +// +//****************************************************************************** +#define MCASP_RXBUF8_RBUF8_M 0xFFFFFFFF // Receive Buffer 8 +#define MCASP_RXBUF8_RBUF8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF9 register. +// +//****************************************************************************** +#define MCASP_RXBUF9_RBUF9_M 0xFFFFFFFF // Receive Buffer 9 +#define MCASP_RXBUF9_RBUF9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF10 register. +// +//****************************************************************************** +#define MCASP_RXBUF10_RBUF10_M 0xFFFFFFFF // Receive Buffer 10 +#define MCASP_RXBUF10_RBUF10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF11 register. +// +//****************************************************************************** +#define MCASP_RXBUF11_RBUF11_M 0xFFFFFFFF // Receive Buffer 11 +#define MCASP_RXBUF11_RBUF11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF12 register. +// +//****************************************************************************** +#define MCASP_RXBUF12_RBUF12_M 0xFFFFFFFF // Receive Buffer 12 +#define MCASP_RXBUF12_RBUF12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF13 register. +// +//****************************************************************************** +#define MCASP_RXBUF13_RBUF13_M 0xFFFFFFFF // Receive Buffer 13 +#define MCASP_RXBUF13_RBUF13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF14 register. +// +//****************************************************************************** +#define MCASP_RXBUF14_RBUF14_M 0xFFFFFFFF // Receive Buffer 14 +#define MCASP_RXBUF14_RBUF14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF15 register. +// +//****************************************************************************** +#define MCASP_RXBUF15_RBUF15_M 0xFFFFFFFF // Receive Buffer 15 +#define MCASP_RXBUF15_RBUF15_S 0 + + + +#endif // __HW_MCASP_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcspi.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcspi.h new file mode 100644 index 0000000000..079e4b6b67 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcspi.h @@ -0,0 +1,1745 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_MCSPI_H__ +#define __HW_MCSPI_H__ + +//***************************************************************************** +// +// The following are defines for the MCSPI register offsets. +// +//***************************************************************************** +#define MCSPI_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) + // Used by software to track + // features bugs and compatibility +#define MCSPI_O_HL_HWINFO 0x00000004 // Information about the IP + // module's hardware configuration + // i.e. typically the module's HDL + // generics (if any). Actual field + // format and encoding is up to the + // module's designer to decide. +#define MCSPI_O_HL_SYSCONFIG 0x00000010 // 0x4402 1010 0x4402 2010 Clock + // management configuration +#define MCSPI_O_REVISION 0x00000100 // 0x4402 1100 0x4402 2100 This + // register contains the hard coded + // RTL revision number. +#define MCSPI_O_SYSCONFIG 0x00000110 // 0x4402 1110 0x4402 2110 This + // register allows controlling + // various parameters of the OCP + // interface. +#define MCSPI_O_SYSSTATUS 0x00000114 // 0x4402 1114 0x4402 2114 This + // register provides status + // information about the module + // excluding the interrupt status + // information +#define MCSPI_O_IRQSTATUS 0x00000118 // 0x4402 1118 0x4402 2118 The + // interrupt status regroups all the + // status of the module internal + // events that can generate an + // interrupt +#define MCSPI_O_IRQENABLE 0x0000011C // 0x4402 111C 0x4402 211C This + // register allows to enable/disable + // the module internal sources of + // interrupt on an event-by-event + // basis. +#define MCSPI_O_WAKEUPENABLE 0x00000120 // 0x4402 1120 0x4402 2120 The + // wakeup enable register allows to + // enable/disable the module + // internal sources of wakeup on + // event-by-event basis. +#define MCSPI_O_SYST 0x00000124 // 0x4402 1124 0x4402 2124 This + // register is used to check the + // correctness of the system + // interconnect either internally to + // peripheral bus or externally to + // device IO pads when the module is + // configured in system test + // (SYSTEST) mode. +#define MCSPI_O_MODULCTRL 0x00000128 // 0x4402 1128 0x4402 2128 This + // register is dedicated to the + // configuration of the serial port + // interface. +#define MCSPI_O_CH0CONF 0x0000012C // 0x4402 112C 0x4402 212C This + // register is dedicated to the + // configuration of the channel 0 +#define MCSPI_O_CH0STAT 0x00000130 // 0x4402 1130 0x4402 2130 This + // register provides status + // information about transmitter and + // receiver registers of channel 0 +#define MCSPI_O_CH0CTRL 0x00000134 // 0x4402 1134 0x4402 2134 This + // register is dedicated to enable + // the channel 0 +#define MCSPI_O_TX0 0x00000138 // 0x4402 1138 0x4402 2138 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX0 0x0000013C // 0x4402 113C 0x4402 213C This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH1CONF 0x00000140 // 0x4402 1140 0x4402 2140 This + // register is dedicated to the + // configuration of the channel. +#define MCSPI_O_CH1STAT 0x00000144 // 0x4402 1144 0x4402 2144 This + // register provides status + // information about transmitter and + // receiver registers of channel 1 +#define MCSPI_O_CH1CTRL 0x00000148 // 0x4402 1148 0x4402 2148 This + // register is dedicated to enable + // the channel 1 +#define MCSPI_O_TX1 0x0000014C // 0x4402 114C 0x4402 214C This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX1 0x00000150 // 0x4402 1150 0x4402 2150 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH2CONF 0x00000154 // 0x4402 1154 0x4402 2154 This + // register is dedicated to the + // configuration of the channel 2 +#define MCSPI_O_CH2STAT 0x00000158 // 0x4402 1158 0x4402 2158 This + // register provides status + // information about transmitter and + // receiver registers of channel 2 +#define MCSPI_O_CH2CTRL 0x0000015C // 0x4402 115C 0x4402 215C This + // register is dedicated to enable + // the channel 2 +#define MCSPI_O_TX2 0x00000160 // 0x4402 1160 0x4402 2160 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX2 0x00000164 // 0x4402 1164 0x4402 2164 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH3CONF 0x00000168 // 0x4402 1168 0x4402 2168 This + // register is dedicated to the + // configuration of the channel 3 +#define MCSPI_O_CH3STAT 0x0000016C // 0x4402 116C 0x4402 216C This + // register provides status + // information about transmitter and + // receiver registers of channel 3 +#define MCSPI_O_CH3CTRL 0x00000170 // 0x4402 1170 0x4402 2170 This + // register is dedicated to enable + // the channel 3 +#define MCSPI_O_TX3 0x00000174 // 0x4402 1174 0x4402 2174 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX3 0x00000178 // 0x4402 1178 0x4402 2178 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_XFERLEVEL 0x0000017C // 0x4402 117C 0x4402 217C This + // register provides transfer levels + // needed while using FIFO buffer + // during transfer. +#define MCSPI_O_DAFTX 0x00000180 // 0x4402 1180 0x4402 2180 This + // register contains the SPI words + // to transmit on the serial link + // when FIFO used and DMA address is + // aligned on 256 bit.This register + // is an image of one of MCSPI_TX(i) + // register corresponding to the + // channel which have its FIFO + // enabled. +#define MCSPI_O_DAFRX 0x000001A0 // 0x4402 11A0 0x4402 21A0 This + // register contains the SPI words + // to received on the serial link + // when FIFO used and DMA address is + // aligned on 256 bit.This register + // is an image of one of MCSPI_RX(i) + // register corresponding to the + // channel which have its FIFO + // enabled. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_HL_REV register. +// +//****************************************************************************** +#define MCSPI_HL_REV_SCHEME_M 0xC0000000 +#define MCSPI_HL_REV_SCHEME_S 30 +#define MCSPI_HL_REV_RSVD_M 0x30000000 // Reserved These bits are + // initialized to zero and writes to + // them are ignored. +#define MCSPI_HL_REV_RSVD_S 28 +#define MCSPI_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define MCSPI_HL_REV_FUNC_S 16 +#define MCSPI_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define MCSPI_HL_REV_R_RTL_S 11 +#define MCSPI_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. +#define MCSPI_HL_REV_X_MAJOR_S 8 +#define MCSPI_HL_REV_CUSTOM_M 0x000000C0 +#define MCSPI_HL_REV_CUSTOM_S 6 +#define MCSPI_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. +#define MCSPI_HL_REV_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register. +// +//****************************************************************************** +#define MCSPI_HL_HWINFO_RETMODE 0x00000040 +#define MCSPI_HL_HWINFO_FFNBYTE_M \ + 0x0000003E + +#define MCSPI_HL_HWINFO_FFNBYTE_S 1 +#define MCSPI_HL_HWINFO_USEFIFO 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCSPI_O_HL_SYSCONFIG register. +// +//****************************************************************************** +#define MCSPI_HL_SYSCONFIG_IDLEMODE_M \ + 0x0000000C // Configuration of the local + // target state management mode. By + // definition target can handle + // read/write transaction as long as + // it is out of IDLE state. 0x0 + // Force-idle mode: local target's + // idle state follows (acknowledges) + // the system's idle requests + // unconditionally i.e. regardless + // of the IP module's internal + // requirements.Backup mode for + // debug only. 0x1 No-idle mode: + // local target never enters idle + // state.Backup mode for debug only. + // 0x2 Smart-idle mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module shall not + // generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 "Smart-idle + // wakeup-capable mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2 +#define MCSPI_HL_SYSCONFIG_FREEEMU \ + 0x00000002 // Sensitivity to emulation (debug) + // suspend input signal. 0 IP module + // is sensitive to emulation suspend + // 1 IP module is not sensitive to + // emulation suspend + +#define MCSPI_HL_SYSCONFIG_SOFTRESET \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_REVISION register. +// +//****************************************************************************** +#define MCSPI_REVISION_REV_M 0x000000FF // IP revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 +#define MCSPI_REVISION_REV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register. +// +//****************************************************************************** +#define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \ + 0x00000300 // Clocks activity during wake up + // mode period 0x0 OCP and + // Functional clocks may be switched + // off. 0x1 OCP clock is maintained. + // Functional clock may be + // switched-off. 0x2 Functional + // clock is maintained. OCP clock + // may be switched-off. 0x3 OCP and + // Functional clocks are maintained. + +#define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8 +#define MCSPI_SYSCONFIG_SIDLEMODE_M \ + 0x00000018 // Power management 0x0 If an idle + // request is detected the McSPI + // acknowledges it unconditionally + // and goes in Inactive mode. + // Interrupt DMA requests and wake + // up lines are unconditionally + // de-asserted and the module wakeup + // capability is deactivated even if + // the bit + // MCSPI_SYSCONFIG[EnaWakeUp] is + // set. 0x1 If an idle request is + // detected the request is ignored + // and the module does not switch to + // wake up mode and keeps on + // behaving normally. 0x2 If an idle + // request is detected the module + // will switch to idle mode based on + // its internal activity. The wake + // up capability cannot be used. 0x3 + // If an idle request is detected + // the module will switch to idle + // mode based on its internal + // activity and the wake up + // capability can be used if the bit + // MCSPI_SYSCONFIG[EnaWakeUp] is + // set. + +#define MCSPI_SYSCONFIG_SIDLEMODE_S 3 +#define MCSPI_SYSCONFIG_ENAWAKEUP \ + 0x00000004 // WakeUp feature control 0 WakeUp + // capability is disabled 1 WakeUp + // capability is enabled + +#define MCSPI_SYSCONFIG_SOFTRESET \ + 0x00000002 // Software reset. During reads it + // always returns 0. 0 (write) + // Normal mode 1 (write) Set this + // bit to 1 to trigger a module + // reset.The bit is automatically + // reset by the hardware. + +#define MCSPI_SYSCONFIG_AUTOIDLE \ + 0x00000001 // Internal OCP Clock gating + // strategy 0 OCP clock is + // free-running 1 Automatic OCP + // clock gating strategy is applied + // based on the OCP interface + // activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register. +// +//****************************************************************************** +#define MCSPI_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register. +// +//****************************************************************************** +#define MCSPI_IRQSTATUS_EOW 0x00020000 +#define MCSPI_IRQSTATUS_WKS 0x00010000 +#define MCSPI_IRQSTATUS_RX3_FULL \ + 0x00004000 + +#define MCSPI_IRQSTATUS_TX3_UNDERFLOW \ + 0x00002000 + +#define MCSPI_IRQSTATUS_TX3_EMPTY \ + 0x00001000 + +#define MCSPI_IRQSTATUS_RX2_FULL \ + 0x00000400 + +#define MCSPI_IRQSTATUS_TX2_UNDERFLOW \ + 0x00000200 + +#define MCSPI_IRQSTATUS_TX2_EMPTY \ + 0x00000100 + +#define MCSPI_IRQSTATUS_RX1_FULL \ + 0x00000040 + +#define MCSPI_IRQSTATUS_TX1_UNDERFLOW \ + 0x00000020 + +#define MCSPI_IRQSTATUS_TX1_EMPTY \ + 0x00000010 + +#define MCSPI_IRQSTATUS_RX0_OVERFLOW \ + 0x00000008 + +#define MCSPI_IRQSTATUS_RX0_FULL \ + 0x00000004 + +#define MCSPI_IRQSTATUS_TX0_UNDERFLOW \ + 0x00000002 + +#define MCSPI_IRQSTATUS_TX0_EMPTY \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_IRQENABLE register. +// +//****************************************************************************** +#define MCSPI_IRQENABLE_EOW_ENABLE \ + 0x00020000 // End of Word count Interrupt + // Enable. 0 Interrupt disabled 1 + // Interrupt enabled + +#define MCSPI_IRQENABLE_WKE 0x00010000 // Wake Up event interrupt Enable + // in slave mode when an active + // control signal is detected on the + // SPIEN line programmed in the + // field MCSPI_CH0CONF[SPIENSLV] 0 + // Interrupt disabled 1 Interrupt + // enabled +#define MCSPI_IRQENABLE_RX3_FULL_ENABLE \ + 0x00004000 // Receiver register Full Interrupt + // Enable. Ch 3 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \ + 0x00002000 // Transmitter register Underflow + // Interrupt Enable. Ch 3 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \ + 0x00001000 // Transmitter register Empty + // Interrupt Enable. Ch3 0 Interrupt + // disabled 1 Interrupt enabled + +#define MCSPI_IRQENABLE_RX2_FULL_ENABLE \ + 0x00000400 // Receiver register Full Interrupt + // Enable. Ch 2 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \ + 0x00000200 // Transmitter register Underflow + // Interrupt Enable. Ch 2 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \ + 0x00000100 // Transmitter register Empty + // Interrupt Enable. Ch 2 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX1_FULL_ENABLE \ + 0x00000040 // Receiver register Full Interrupt + // Enable. Ch 1 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \ + 0x00000020 // Transmitter register Underflow + // Interrupt Enable. Ch 1 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \ + 0x00000010 // Transmitter register Empty + // Interrupt Enable. Ch 1 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \ + 0x00000008 // Receiver register Overflow + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX0_FULL_ENABLE \ + 0x00000004 // Receiver register Full Interrupt + // Enable. Ch 0 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \ + 0x00000002 // Transmitter register Underflow + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \ + 0x00000001 // Transmitter register Empty + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCSPI_O_WAKEUPENABLE register. +// +//****************************************************************************** +#define MCSPI_WAKEUPENABLE_WKEN 0x00000001 // WakeUp functionality in slave + // mode when an active control + // signal is detected on the SPIEN + // line programmed in the field + // MCSPI_CH0CONF[SPIENSLV] 0 The + // event is not allowed to wakeup + // the system even if the global + // control bit + // MCSPI_SYSCONF[EnaWakeUp] is set. + // 1 The event is allowed to wakeup + // the system if the global control + // bit MCSPI_SYSCONF[EnaWakeUp] is + // set. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYST register. +// +//****************************************************************************** +#define MCSPI_SYST_SSB 0x00000800 // Set status bit 0 No action. + // Writing 0 does not clear already + // set status bits; This bit must be + // cleared prior attempting to clear + // a status bit of the + // register. 1 + // Force to 1 all status bits of + // MCSPI_IRQSTATUS register. Writing + // 1 into this bit sets to 1 all + // status bits contained in the + // register. +#define MCSPI_SYST_SPIENDIR 0x00000400 // Set the direction of the + // SPIEN[3:0] lines and SPICLK line + // 0 output (as in master mode) 1 + // input (as in slave mode) +#define MCSPI_SYST_SPIDATDIR1 0x00000200 // Set the direction of the + // SPIDAT[1] 0 output 1 input +#define MCSPI_SYST_SPIDATDIR0 0x00000100 // Set the direction of the + // SPIDAT[0] 0 output 1 input +#define MCSPI_SYST_WAKD 0x00000080 // SWAKEUP output (signal data + // value of internal signal to + // system). The signal is driven + // high or low according to the + // value written into this register + // bit. 0 The pin is driven low. 1 + // The pin is driven high. +#define MCSPI_SYST_SPICLK 0x00000040 // SPICLK line (signal data value) + // If MCSPI_SYST[SPIENDIR] = 1 + // (input mode direction) this bit + // returns the value on the CLKSPI + // line (high or low) and a write + // into this bit has no effect. If + // MCSPI_SYST[SPIENDIR] = 0 (output + // mode direction) the CLKSPI line + // is driven high or low according + // to the value written into this + // register. +#define MCSPI_SYST_SPIDAT_1 0x00000020 // SPIDAT[1] line (signal data + // value) If MCSPI_SYST[SPIDATDIR1] + // = 0 (output mode direction) the + // SPIDAT[1] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIDATDIR1] = 1 (input + // mode direction) this bit returns + // the value on the SPIDAT[1] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIDAT_0 0x00000010 // SPIDAT[0] line (signal data + // value) If MCSPI_SYST[SPIDATDIR0] + // = 0 (output mode direction) the + // SPIDAT[0] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIDATDIR0] = 1 (input + // mode direction) this bit returns + // the value on the SPIDAT[0] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_3 0x00000008 // SPIEN[3] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[3] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[3] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_2 0x00000004 // SPIEN[2] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[2] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[2] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_1 0x00000002 // SPIEN[1] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[1] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[1] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_0 0x00000001 // SPIEN[0] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[0] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[0] line + // (high or low) and a write into + // this bit has no effect. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_MODULCTRL register. +// +//****************************************************************************** +#define MCSPI_MODULCTRL_FDAA 0x00000100 // FIFO DMA Address 256-bit aligned + // This register is used when a FIFO + // is managed by the module and DMA + // connected to the controller + // provides only 256 bit aligned + // address. If this bit is set the + // enabled channel which uses the + // FIFO has its datas managed + // through MCSPI_DAFTX and + // MCSPI_DAFRX registers instead of + // MCSPI_TX(i) and MCSPI_RX(i) + // registers. 0 FIFO data managed by + // MCSPI_TX(i) and MCSPI_RX(i) + // registers. 1 FIFO data managed by + // MCSPI_DAFTX and MCSPI_DAFRX + // registers. +#define MCSPI_MODULCTRL_MOA 0x00000080 // Multiple word ocp access: This + // register can only be used when a + // channel is enabled using a FIFO. + // It allows the system to perform + // multiple SPI word access for a + // single 32-bit OCP word access. + // This is possible for WL < 16. 0 + // Multiple word access disabled 1 + // Multiple word access enabled with + // FIFO +#define MCSPI_MODULCTRL_INITDLY_M \ + 0x00000070 // Initial spi delay for first + // transfer: This register is an + // option only available in SINGLE + // master mode The controller waits + // for a delay to transmit the first + // spi word after channel enabled + // and corresponding TX register + // filled. This Delay is based on + // SPI output frequency clock No + // clock output provided to the + // boundary and chip select is not + // active in 4 pin mode within this + // period. 0x0 No delay for first + // spi transfer. 0x1 The controller + // wait 4 spi bus clock 0x2 The + // controller wait 8 spi bus clock + // 0x3 The controller wait 16 spi + // bus clock 0x4 The controller wait + // 32 spi bus clock + +#define MCSPI_MODULCTRL_INITDLY_S 4 +#define MCSPI_MODULCTRL_SYSTEM_TEST \ + 0x00000008 // Enables the system test mode 0 + // Functional mode 1 System test + // mode (SYSTEST) + +#define MCSPI_MODULCTRL_MS 0x00000004 // Master/ Slave 0 Master - The + // module generates the SPICLK and + // SPIEN[3:0] 1 Slave - The module + // receives the SPICLK and + // SPIEN[3:0] +#define MCSPI_MODULCTRL_PIN34 0x00000002 // Pin mode selection: This + // register is used to configure the + // SPI pin mode in master or slave + // mode. If asserted the controller + // only use SIMOSOMI and SPICLK + // clock pin for spi transfers. 0 + // SPIEN is used as a chip select. 1 + // SPIEN is not used.In this mode + // all related option to chip select + // have no meaning. +#define MCSPI_MODULCTRL_SINGLE 0x00000001 // Single channel / Multi Channel + // (master mode only) 0 More than + // one channel will be used in + // master mode. 1 Only one channel + // will be used in master mode. This + // bit must be set in Force SPIEN + // mode. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0CONF register. +// +//****************************************************************************** +#define MCSPI_CH0CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH0CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH0CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH0CONF_TCS0_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH0CONF_TCS0_S 25 +#define MCSPI_CH0CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH0CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH0CONF[SBPOL] +#define MCSPI_CH0CONF_SPIENSLV_M \ + 0x00600000 // Channel 0 only and slave mode + // only: SPI slave select signal + // detection. Reserved bits for + // other cases. 0x0 Detection + // enabled only on SPIEN[0] 0x1 + // Detection enabled only on + // SPIEN[1] 0x2 Detection enabled + // only on SPIEN[2] 0x3 Detection + // enabled only on SPIEN[3] + +#define MCSPI_CH0CONF_SPIENSLV_S 21 +#define MCSPI_CH0CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH0CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH0CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH0CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH0CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH0CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH0CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH0CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH0CONF_TRM_S 12 +#define MCSPI_CH0CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH0CONF_WL_S 7 +#define MCSPI_CH0CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH0CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH0CONF_CLKD_S 2 +#define MCSPI_CH0CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH0CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0STAT register. +// +//****************************************************************************** +#define MCSPI_CH0STAT_RXFFF 0x00000040 +#define MCSPI_CH0STAT_RXFFE 0x00000020 +#define MCSPI_CH0STAT_TXFFF 0x00000010 +#define MCSPI_CH0STAT_TXFFE 0x00000008 +#define MCSPI_CH0STAT_EOT 0x00000004 +#define MCSPI_CH0STAT_TXS 0x00000002 +#define MCSPI_CH0STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0CTRL register. +// +//****************************************************************************** +#define MCSPI_CH0CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH0CTRL_EXTCLK_S 8 +#define MCSPI_CH0CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX0 register. +// +//****************************************************************************** +#define MCSPI_TX0_TDATA_M 0xFFFFFFFF // Channel 0 Data to transmit +#define MCSPI_TX0_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX0 register. +// +//****************************************************************************** +#define MCSPI_RX0_RDATA_M 0xFFFFFFFF // Channel 0 Received Data +#define MCSPI_RX0_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1CONF register. +// +//****************************************************************************** +#define MCSPI_CH1CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH1CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH1CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH1CONF_TCS1_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH1CONF_TCS1_S 25 +#define MCSPI_CH1CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH1CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH1CONF[SBPOL] +#define MCSPI_CH1CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH1CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH1CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH1CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH1CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH1CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH1CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH1CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH1CONF_TRM_S 12 +#define MCSPI_CH1CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH1CONF_WL_S 7 +#define MCSPI_CH1CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH1CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH1CONF_CLKD_S 2 +#define MCSPI_CH1CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH1CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1STAT register. +// +//****************************************************************************** +#define MCSPI_CH1STAT_RXFFF 0x00000040 +#define MCSPI_CH1STAT_RXFFE 0x00000020 +#define MCSPI_CH1STAT_TXFFF 0x00000010 +#define MCSPI_CH1STAT_TXFFE 0x00000008 +#define MCSPI_CH1STAT_EOT 0x00000004 +#define MCSPI_CH1STAT_TXS 0x00000002 +#define MCSPI_CH1STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1CTRL register. +// +//****************************************************************************** +#define MCSPI_CH1CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH1CTRL_EXTCLK_S 8 +#define MCSPI_CH1CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX1 register. +// +//****************************************************************************** +#define MCSPI_TX1_TDATA_M 0xFFFFFFFF // Channel 1 Data to transmit +#define MCSPI_TX1_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX1 register. +// +//****************************************************************************** +#define MCSPI_RX1_RDATA_M 0xFFFFFFFF // Channel 1 Received Data +#define MCSPI_RX1_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2CONF register. +// +//****************************************************************************** +#define MCSPI_CH2CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH2CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH2CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH2CONF_TCS2_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH2CONF_TCS2_S 25 +#define MCSPI_CH2CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH2CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH2CONF[SBPOL] +#define MCSPI_CH2CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH2CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH2CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH2CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH2CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH2CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH2CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH2CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH2CONF_TRM_S 12 +#define MCSPI_CH2CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH2CONF_WL_S 7 +#define MCSPI_CH2CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH2CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH2CONF_CLKD_S 2 +#define MCSPI_CH2CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH2CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2STAT register. +// +//****************************************************************************** +#define MCSPI_CH2STAT_RXFFF 0x00000040 +#define MCSPI_CH2STAT_RXFFE 0x00000020 +#define MCSPI_CH2STAT_TXFFF 0x00000010 +#define MCSPI_CH2STAT_TXFFE 0x00000008 +#define MCSPI_CH2STAT_EOT 0x00000004 +#define MCSPI_CH2STAT_TXS 0x00000002 +#define MCSPI_CH2STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2CTRL register. +// +//****************************************************************************** +#define MCSPI_CH2CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH2CTRL_EXTCLK_S 8 +#define MCSPI_CH2CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX2 register. +// +//****************************************************************************** +#define MCSPI_TX2_TDATA_M 0xFFFFFFFF // Channel 2 Data to transmit +#define MCSPI_TX2_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX2 register. +// +//****************************************************************************** +#define MCSPI_RX2_RDATA_M 0xFFFFFFFF // Channel 2 Received Data +#define MCSPI_RX2_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3CONF register. +// +//****************************************************************************** +#define MCSPI_CH3CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH3CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH3CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH3CONF_TCS3_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH3CONF_TCS3_S 25 +#define MCSPI_CH3CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH3CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH3CONF[SBPOL] +#define MCSPI_CH3CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH3CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH3CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH3CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH3CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH3CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH3CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH3CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH3CONF_TRM_S 12 +#define MCSPI_CH3CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH3CONF_WL_S 7 +#define MCSPI_CH3CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH3CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH3CONF_CLKD_S 2 +#define MCSPI_CH3CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH3CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3STAT register. +// +//****************************************************************************** +#define MCSPI_CH3STAT_RXFFF 0x00000040 +#define MCSPI_CH3STAT_RXFFE 0x00000020 +#define MCSPI_CH3STAT_TXFFF 0x00000010 +#define MCSPI_CH3STAT_TXFFE 0x00000008 +#define MCSPI_CH3STAT_EOT 0x00000004 +#define MCSPI_CH3STAT_TXS 0x00000002 +#define MCSPI_CH3STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3CTRL register. +// +//****************************************************************************** +#define MCSPI_CH3CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH3CTRL_EXTCLK_S 8 +#define MCSPI_CH3CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX3 register. +// +//****************************************************************************** +#define MCSPI_TX3_TDATA_M 0xFFFFFFFF // Channel 3 Data to transmit +#define MCSPI_TX3_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX3 register. +// +//****************************************************************************** +#define MCSPI_RX3_RDATA_M 0xFFFFFFFF // Channel 3 Received Data +#define MCSPI_RX3_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register. +// +//****************************************************************************** +#define MCSPI_XFERLEVEL_WCNT_M 0xFFFF0000 // Spi word counterThis register + // holds the programmable value of + // number of SPI word to be + // transferred on channel which is + // using the FIFO buffer.When + // transfer had started a read back + // in this register returns the + // current SPI word transfer index. + // 0x0000 Counter not used 0x0001 + // one word 0xFFFE 65534 spi word + // 0xFFFF 65535 spi word +#define MCSPI_XFERLEVEL_WCNT_S 16 +#define MCSPI_XFERLEVEL_AFL_M 0x0000FF00 // Buffer Almost Full This register + // holds the programmable almost + // full level value used to + // determine almost full buffer + // condition. If the user wants an + // interrupt or a DMA read request + // to be issued during a receive + // operation when the data buffer + // holds at least n bytes then the + // buffer MCSPI_MODULCTRL[AFL] must + // be set with n-1.The size of this + // register is defined by the + // generic parameter FFNBYTE. 0x00 + // one byte 0x01 2 bytes 0xFE + // 255bytes 0xFF 256bytes +#define MCSPI_XFERLEVEL_AFL_S 8 +#define MCSPI_XFERLEVEL_AEL_M 0x000000FF // Buffer Almost EmptyThis register + // holds the programmable almost + // empty level value used to + // determine almost empty buffer + // condition. If the user wants an + // interrupt or a DMA write request + // to be issued during a transmit + // operation when the data buffer is + // able to receive n bytes then the + // buffer MCSPI_MODULCTRL[AEL] must + // be set with n-1. 0x00 one byte + // 0x01 2 bytes 0xFE 255 bytes 0xFF + // 256bytes +#define MCSPI_XFERLEVEL_AEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_DAFTX register. +// +//****************************************************************************** +#define MCSPI_DAFTX_DAFTDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA + // 256 bit aligned address. "This + // Register is only is used when + // MCSPI_MODULCTRL[FDAA] is set to + // ""1"" and only one of the + // MCSPI_CH(i)CONF[FFEW] of enabled + // channels is set. If these + // conditions are not respected any + // access to this register return a + // null value." +#define MCSPI_DAFTX_DAFTDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_DAFRX register. +// +//****************************************************************************** +#define MCSPI_DAFRX_DAFRDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA + // 256 bit aligned address. "This + // Register is only is used when + // MCSPI_MODULCTRL[FDAA] is set to + // ""1"" and only one of the + // MCSPI_CH(i)CONF[FFEW] of enabled + // channels is set. If these + // conditions are not respected any + // access to this register return a + // null value." +#define MCSPI_DAFRX_DAFRDATA_S 0 + + + +#endif // __HW_MCSPI_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_memmap.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_memmap.h new file mode 100644 index 0000000000..244905dd20 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_memmap.h @@ -0,0 +1,84 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the slave_1 interface. +// +//***************************************************************************** +#define FLASH_BASE 0x01000000 +#define SRAM_BASE 0x20000000 +#define WDT_BASE 0x40000000 +#define GPIOA0_BASE 0x40004000 +#define GPIOA1_BASE 0x40005000 +#define GPIOA2_BASE 0x40006000 +#define GPIOA3_BASE 0x40007000 +#define GPIOA4_BASE 0x40024000 +#define UARTA0_BASE 0x4000C000 +#define UARTA1_BASE 0x4000D000 +#define I2CA0_BASE 0x40020000 +#define TIMERA0_BASE 0x40030000 +#define TIMERA1_BASE 0x40031000 +#define TIMERA2_BASE 0x40032000 +#define TIMERA3_BASE 0x40033000 +#define STACKDIE_CTRL_BASE 0x400F5000 +#define COMMON_REG_BASE 0x400F7000 +#define FLASH_CONTROL_BASE 0x400FD000 +#define SYSTEM_CONTROL_BASE 0x400FE000 +#define UDMA_BASE 0x400FF000 +#define SDHOST_BASE 0x44010000 +#define CAMERA_BASE 0x44018000 +#define I2S_BASE 0x4401C000 +#define SSPI_BASE 0x44020000 +#define GSPI_BASE 0x44021000 +#define LSPI_BASE 0x44022000 +#define ARCM_BASE 0x44025000 +#define APPS_CONFIG_BASE 0x44026000 +#define GPRCM_BASE 0x4402D000 +#define OCP_SHARED_BASE 0x4402E000 +#define ADC_BASE 0x4402E800 +#define HIB1P2_BASE 0x4402F000 +#define HIB3P3_BASE 0x4402F800 +#define DTHE_BASE 0x44030000 +#define SHAMD5_BASE 0x44035000 +#define AES_BASE 0x44037000 +#define DES_BASE 0x44039000 + + +#endif // __HW_MEMMAP_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mmchs.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mmchs.h new file mode 100644 index 0000000000..3096d13a99 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mmchs.h @@ -0,0 +1,1919 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_MMCHS_H__ +#define __HW_MMCHS_H__ + +//***************************************************************************** +// +// The following are defines for the MMCHS register offsets. +// +//***************************************************************************** +#define MMCHS_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) + // Used by software to track + // features bugs and compatibility +#define MMCHS_O_HL_HWINFO 0x00000004 // Information about the IP + // module's hardware configuration + // i.e. typically the module's HDL + // generics (if any). Actual field + // format and encoding is up to the + // module's designer to decide. +#define MMCHS_O_HL_SYSCONFIG 0x00000010 // Clock management configuration +#define MMCHS_O_SYSCONFIG 0x00000110 // System Configuration Register + // This register allows controlling + // various parameters of the OCP + // interface. +#define MMCHS_O_SYSSTATUS 0x00000114 // System Status Register This + // register provides status + // information about the module + // excluding the interrupt status + // information +#define MMCHS_O_CSRE 0x00000124 // Card status response error This + // register enables the host + // controller to detect card status + // errors of response type R1 R1b + // for all cards and of R5 R5b and + // R6 response for cards types SD or + // SDIO. When a bit MMCHS_CSRE[i] is + // set to 1 if the corresponding bit + // at the same position in the + // response MMCHS_RSP0[i] is set to + // 1 the host controller indicates a + // card error (MMCHS_STAT[CERR]) + // interrupt status to avoid the + // host driver reading the response + // register (MMCHS_RSP0). Note: No + // automatic card error detection + // for autoCMD12 is implemented; the + // host system has to check + // autoCMD12 response register + // (MMCHS_RESP76) for possible card + // errors. +#define MMCHS_O_SYSTEST 0x00000128 // System Test register This + // register is used to control the + // signals that connect to I/O pins + // when the module is configured in + // system test (SYSTEST) mode for + // boundary connectivity + // verification. Note: In SYSTEST + // mode a write into MMCHS_CMD + // register will not start a + // transfer. The buffer behaves as a + // stack accessible only by the + // local host (push and pop + // operations). In this mode the + // Transfer Block Size + // (MMCHS_BLK[BLEN]) and the Blocks + // count for current transfer + // (MMCHS_BLK[NBLK]) are needed to + // generate a Buffer write ready + // interrupt (MMCHS_STAT[BWR]) or a + // Buffer read ready interrupt + // (MMCHS_STAT[BRR]) and DMA + // requests if enabled. +#define MMCHS_O_CON 0x0000012C // Configuration register This + // register is used: - to select the + // functional mode or the SYSTEST + // mode for any card. - to send an + // initialization sequence to any + // card. - to enable the detection + // on DAT[1] of a card interrupt for + // SDIO cards only. and also to + // configure : - specific data and + // command transfers for MMC cards + // only. - the parameters related to + // the card detect and write protect + // input signals. +#define MMCHS_O_PWCNT 0x00000130 // Power counter register This + // register is used to program a mmc + // counter to delay command + // transfers after activating the + // PAD power this value depends on + // PAD characteristics and voltage. +#define MMCHS_O_BLK 0x00000204 // Transfer Length Configuration + // register MMCHS_BLK[BLEN] is the + // block size register. + // MMCHS_BLK[NBLK] is the block + // count register. This register + // shall be used for any card. +#define MMCHS_O_ARG 0x00000208 // Command argument Register This + // register contains command + // argument specified as bit 39-8 of + // Command-Format These registers + // must be initialized prior to + // sending the command itself to the + // card (write action into the + // register MMCHS_CMD register). + // Only exception is for a command + // index specifying stuff bits in + // arguments making a write + // unnecessary. +#define MMCHS_O_CMD 0x0000020C // Command and transfer mode + // register MMCHS_CMD[31:16] = the + // command register MMCHS_CMD[15:0] + // = the transfer mode. This + // register configures the data and + // command transfers. A write into + // the most significant byte send + // the command. A write into + // MMCHS_CMD[15:0] registers during + // data transfer has no effect. This + // register shall be used for any + // card. Note: In SYSTEST mode a + // write into MMCHS_CMD register + // will not start a transfer. +#define MMCHS_O_RSP10 0x00000210 // Command response[31:0] Register + // This 32-bit register holds bits + // positions [31:0] of command + // response type + // R1/R1b/R2/R3/R4/R5/R5b/R6 +#define MMCHS_O_RSP32 0x00000214 // Command response[63:32] Register + // This 32-bit register holds bits + // positions [63:32] of command + // response type R2 +#define MMCHS_O_RSP54 0x00000218 // Command response[95:64] Register + // This 32-bit register holds bits + // positions [95:64] of command + // response type R2 +#define MMCHS_O_RSP76 0x0000021C // Command response[127:96] + // Register This 32-bit register + // holds bits positions [127:96] of + // command response type R2 +#define MMCHS_O_DATA 0x00000220 // Data Register This register is + // the 32-bit entry point of the + // buffer for read or write data + // transfers. The buffer size is + // 32bits x256(1024 bytes). Bytes + // within a word are stored and read + // in little endian format. This + // buffer can be used as two 512 + // byte buffers to transfer data + // efficiently without reducing the + // throughput. Sequential and + // contiguous access is necessary to + // increment the pointer correctly. + // Random or skipped access is not + // allowed. In little endian if the + // local host accesses this register + // byte-wise or 16bit-wise the least + // significant byte (bits [7:0]) + // must always be written/read + // first. The update of the buffer + // address is done on the most + // significant byte write for full + // 32-bit DATA register or on the + // most significant byte of the last + // word of block transfer. Example + // 1: Byte or 16-bit access + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=1100 (2-bytes) OK + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=0100 (1-byte) OK + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=1000 (1-byte) Bad +#define MMCHS_O_PSTATE 0x00000224 // Present state register The Host + // can get status of the Host + // Controller from this 32-bit read + // only register. +#define MMCHS_O_HCTL 0x00000228 // Control register This register + // defines the host controls to set + // power wakeup and transfer + // parameters. MMCHS_HCTL[31:24] = + // Wakeup control MMCHS_HCTL[23:16] + // = Block gap control + // MMCHS_HCTL[15:8] = Power control + // MMCHS_HCTL[7:0] = Host control +#define MMCHS_O_SYSCTL 0x0000022C // SD system control register This + // register defines the system + // controls to set software resets + // clock frequency management and + // data timeout. MMCHS_SYSCTL[31:24] + // = Software resets + // MMCHS_SYSCTL[23:16] = Timeout + // control MMCHS_SYSCTL[15:0] = + // Clock control +#define MMCHS_O_STAT 0x00000230 // Interrupt status register The + // interrupt status regroups all the + // status of the module internal + // events that can generate an + // interrupt. MMCHS_STAT[31:16] = + // Error Interrupt Status + // MMCHS_STAT[15:0] = Normal + // Interrupt Status +#define MMCHS_O_IE 0x00000234 // Interrupt SD enable register + // This register allows to + // enable/disable the module to set + // status bits on an event-by-event + // basis. MMCHS_IE[31:16] = Error + // Interrupt Status Enable + // MMCHS_IE[15:0] = Normal Interrupt + // Status Enable +#define MMCHS_O_ISE 0x00000238 // Interrupt signal enable register + // This register allows to + // enable/disable the module + // internal sources of status on an + // event-by-event basis. + // MMCHS_ISE[31:16] = Error + // Interrupt Signal Enable + // MMCHS_ISE[15:0] = Normal + // Interrupt Signal Enable +#define MMCHS_O_AC12 0x0000023C // Auto CMD12 Error Status Register + // The host driver may determine + // which of the errors cases related + // to Auto CMD12 has occurred by + // checking this MMCHS_AC12 register + // when an Auto CMD12 Error + // interrupt occurs. This register + // is valid only when Auto CMD12 is + // enabled (MMCHS_CMD[ACEN]) and + // Auto CMD12Error (MMCHS_STAT[ACE]) + // is set to 1. Note: These bits are + // automatically reset when starting + // a new adtc command with data. +#define MMCHS_O_CAPA 0x00000240 // Capabilities register This + // register lists the capabilities + // of the MMC/SD/SDIO host + // controller. +#define MMCHS_O_CUR_CAPA 0x00000248 // Maximum current capabilities + // Register This register indicates + // the maximum current capability + // for each voltage. The value is + // meaningful if the voltage support + // is set in the capabilities + // register (MMCHS_CAPA). + // Initialization of this register + // (via a write access to this + // register) depends on the system + // capabilities. The host driver + // shall not modify this register + // after the initilaization. This + // register is only reinitialized by + // a hard reset (via RESETN signal) +#define MMCHS_O_FE 0x00000250 // Force Event Register for Error + // Interrupt status The force Event + // Register is not a physically + // implemented register. Rather it + // is an address at which the Error + // Interrupt Status register can be + // written. The effect of a write to + // this address will be reflected in + // the Error Interrupt Status + // Register if corresponding bit of + // the Error Interrupt Status Enable + // Register is set. +#define MMCHS_O_ADMAES 0x00000254 // ADMA Error Status Register When + // ADMA Error Interrupt is occurred + // the ADMA Error States field in + // this register holds the ADMA + // state and the ADMA System Address + // Register holds the address around + // the error descriptor. For + // recovering the error the Host + // Driver requires the ADMA state to + // identify the error descriptor + // address as follows: ST_STOP: + // Previous location set in the ADMA + // System Address register is the + // error descriptor address ST_FDS: + // Current location set in the ADMA + // System Address register is the + // error descriptor address ST_CADR: + // This sate is never set because do + // not generate ADMA error in this + // state. ST_TFR: Previous location + // set in the ADMA System Address + // register is the error descriptor + // address In case of write + // operation the Host Driver should + // use ACMD22 to get the number of + // written block rather than using + // this information since unwritten + // data may exist in the Host + // Controller. The Host Controller + // generates the ADMA Error + // Interrupt when it detects invalid + // descriptor data (Valid=0) at the + // ST_FDS state. In this case ADMA + // Error State indicates that an + // error occurs at ST_FDS state. The + // Host Driver may find that the + // Valid bit is not set in the error + // descriptor. +#define MMCHS_O_ADMASAL 0x00000258 // ADMA System address Low bits +#define MMCHS_O_REV 0x000002FC // Versions Register This register + // contains the hard coded RTL + // vendor revision number the + // version number of SD + // specification compliancy and a + // slot status bit. MMCHS_REV[31:16] + // = Host controller version + // MMCHS_REV[15:0] = Slot Interrupt + // Status + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HL_REV register. +// +//****************************************************************************** +#define MMCHS_HL_REV_SCHEME_M 0xC0000000 +#define MMCHS_HL_REV_SCHEME_S 30 +#define MMCHS_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define MMCHS_HL_REV_FUNC_S 16 +#define MMCHS_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define MMCHS_HL_REV_R_RTL_S 11 +#define MMCHS_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. +#define MMCHS_HL_REV_X_MAJOR_S 8 +#define MMCHS_HL_REV_CUSTOM_M 0x000000C0 +#define MMCHS_HL_REV_CUSTOM_S 6 +#define MMCHS_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. +#define MMCHS_HL_REV_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register. +// +//****************************************************************************** +#define MMCHS_HL_HWINFO_RETMODE 0x00000040 +#define MMCHS_HL_HWINFO_MEM_SIZE_M \ + 0x0000003C + +#define MMCHS_HL_HWINFO_MEM_SIZE_S 2 +#define MMCHS_HL_HWINFO_MERGE_MEM \ + 0x00000002 + +#define MMCHS_HL_HWINFO_MADMA_EN \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MMCHS_O_HL_SYSCONFIG register. +// +//****************************************************************************** +#define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \ + 0x00000030 // Configuration of the local + // initiator state management mode. + // By definition initiator may + // generate read/write transaction + // as long as it is out of STANDBY + // state. 0x0 Force-standby mode: + // local initiator is + // unconditionally placed in standby + // state.Backup mode for debug only. + // 0x1 No-standby mode: local + // initiator is unconditionally + // placed out of standby + // state.Backup mode for debug only. + // 0x2 Smart-standby mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator.IP module + // shall not generate + // (initiator-related) wakeup + // events. 0x3 "Smart-Standby + // wakeup-capable mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator. IP module may + // generate (master-related) wakeup + // events when in standby state.Mode + // is only relevant if the + // appropriate IP module ""mwakeup"" + // output is implemented." + +#define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4 +#define MMCHS_HL_SYSCONFIG_IDLEMODE_M \ + 0x0000000C // Configuration of the local + // target state management mode. By + // definition target can handle + // read/write transaction as long as + // it is out of IDLE state. 0x0 + // Force-idle mode: local target's + // idle state follows (acknowledges) + // the system's idle requests + // unconditionally i.e. regardless + // of the IP module's internal + // requirements.Backup mode for + // debug only. 0x1 No-idle mode: + // local target never enters idle + // state.Backup mode for debug only. + // 0x2 Smart-idle mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module shall not + // generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 "Smart-idle + // wakeup-capable mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2 +#define MMCHS_HL_SYSCONFIG_FREEEMU \ + 0x00000002 // Sensitivity to emulation (debug) + // suspend input signal. + // Functionality NOT implemented in + // MMCHS. 0 IP module is sensitive + // to emulation suspend 1 IP module + // is not sensitive to emulation + // suspend + +#define MMCHS_HL_SYSCONFIG_SOFTRESET \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register. +// +//****************************************************************************** +#define MMCHS_SYSCONFIG_STANDBYMODE_M \ + 0x00003000 // Master interface power + // Management standby/wait control. + // The bit field is only useful when + // generic parameter MADMA_EN + // (Master ADMA enable) is set as + // active otherwise it is a read + // only register read a '0'. 0x0 + // Force-standby. Mstandby is forced + // unconditionnaly. 0x1 No-standby. + // Mstandby is never asserted. 0x2 + // Smart-standby mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator.IP module + // shall not generate + // (initiator-related) wakeup + // events. 0x3 Smart-Standby + // wakeup-capable mode: "local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator. IP module may + // generate (master-related) wakeup + // events when in standby state.Mode + // is only relevant if the + // appropriate IP module ""mwakeup"" + // output is implemented." + +#define MMCHS_SYSCONFIG_STANDBYMODE_S 12 +#define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \ + 0x00000300 // Clocks activity during wake up + // mode period. Bit8: OCP interface + // clock Bit9: Functional clock 0x0 + // OCP and Functional clock may be + // switched off. 0x1 OCP clock is + // maintained. Functional clock may + // be switched-off. 0x2 Functional + // clock is maintained. OCP clock + // may be switched-off. 0x3 OCP and + // Functional clocks are maintained. + +#define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8 +#define MMCHS_SYSCONFIG_SIDLEMODE_M \ + 0x00000018 // Power management 0x0 If an idle + // request is detected the MMCHS + // acknowledges it unconditionally + // and goes in Inactive mode. + // Interrupt and DMA requests are + // unconditionally de-asserted. 0x1 + // If an idle request is detected + // the request is ignored and the + // module keeps on behaving + // normally. 0x2 Smart-idle mode: + // local target's idle state + // eventually follows (acknowledges) + // the system's idle requests + // depending on the IP module's + // internal requirements.IP module + // shall not generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 Smart-idle + // wakeup-capable mode: "local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MMCHS_SYSCONFIG_SIDLEMODE_S 3 +#define MMCHS_SYSCONFIG_ENAWAKEUP \ + 0x00000004 // Wakeup feature control 0 Wakeup + // capability is disabled 1 Wakeup + // capability is enabled + +#define MMCHS_SYSCONFIG_SOFTRESET \ + 0x00000002 + +#define MMCHS_SYSCONFIG_AUTOIDLE \ + 0x00000001 // Internal Clock gating strategy 0 + // Clocks are free-running 1 + // Automatic clock gating strategy + // is applied based on the OCP and + // MMC interface activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register. +// +//****************************************************************************** +#define MMCHS_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CSRE register. +// +//****************************************************************************** +#define MMCHS_CSRE_CSRE_M 0xFFFFFFFF // Card status response error +#define MMCHS_CSRE_CSRE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSTEST register. +// +//****************************************************************************** +#define MMCHS_SYSTEST_OBI 0x00010000 +#define MMCHS_SYSTEST_SDCD 0x00008000 +#define MMCHS_SYSTEST_SDWP 0x00004000 +#define MMCHS_SYSTEST_WAKD 0x00002000 +#define MMCHS_SYSTEST_SSB 0x00001000 +#define MMCHS_SYSTEST_D7D 0x00000800 +#define MMCHS_SYSTEST_D6D 0x00000400 +#define MMCHS_SYSTEST_D5D 0x00000200 +#define MMCHS_SYSTEST_D4D 0x00000100 +#define MMCHS_SYSTEST_D3D 0x00000080 +#define MMCHS_SYSTEST_D2D 0x00000040 +#define MMCHS_SYSTEST_D1D 0x00000020 +#define MMCHS_SYSTEST_D0D 0x00000010 +#define MMCHS_SYSTEST_DDIR 0x00000008 +#define MMCHS_SYSTEST_CDAT 0x00000004 +#define MMCHS_SYSTEST_CDIR 0x00000002 +#define MMCHS_SYSTEST_MCKD 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CON register. +// +//****************************************************************************** +#define MMCHS_CON_SDMA_LNE 0x00200000 // Slave DMA Level/Edge Request: + // The waveform of the DMA request + // can be configured either edge + // sensitive with early de-assertion + // on first access to MMCHS_DATA + // register or late de-assertion + // request remains active until last + // allowed data written into + // MMCHS_DATA. 0 Slave DMA edge + // sensitive Early DMA de-assertion + // 1 Slave DMA level sensitive Late + // DMA de-assertion +#define MMCHS_CON_DMA_MNS 0x00100000 // DMA Master or Slave selection: + // When this bit is set and the + // controller is configured to use + // the DMA Ocp master interface is + // used to get datas from system + // using ADMA2 procedure (direct + // access to the memory).This option + // is only available if generic + // parameter MADMA_EN is asserted to + // '1'. 0 The controller is slave on + // data transfers with system. 1 The + // controller is master on data + // exchange with system controller + // must be configured as using DMA. +#define MMCHS_CON_DDR 0x00080000 // Dual Data Rate mode: When this + // register is set the controller + // uses both clock edge to emit or + // receive data. Odd bytes are + // transmitted on falling edges and + // even bytes are transmitted on + // rise edges. It only applies on + // Data bytes and CRC Start end bits + // and CRC status are kept full + // cycle. This bit field is only + // meaningful and active for even + // clock divider ratio of + // MMCHS_SYSCTL[CLKD] it is + // insensitive to MMCHS_HCTL[HSPE] + // setting. 0 Standard mode : data + // are transmitted on a single edge + // depending on MMCHS_HCTRL[HSPE]. 1 + // Data Bytes and CRC are + // transmitted on both edge. +#define MMCHS_CON_BOOT_CF0 0x00040000 +#define MMCHS_CON_BOOT_ACK 0x00020000 // Book acknowledge received: When + // this bit is set the controller + // should receive a boot status on + // DAT0 line after next command + // issued. If no status is received + // a data timeout will be generated. + // 0 No acknowledge to be received 1 + // A boot status will be received on + // DAT0 line after issuing a + // command. +#define MMCHS_CON_CLKEXTFREE 0x00010000 // External clock free running: + // This register is used to maintain + // card clock out of transfer + // transaction to enable slave + // module for example to generate a + // synchronous interrupt on DAT[1]. + // The Clock will be maintain only + // if MMCHS_SYSCTL[CEN] is set. 0 + // External card clock is cut off + // outside active transaction + // period. 1 External card clock is + // maintain even out of active + // transaction period only if + // MMCHS_SYSCTL[CEN] is set. +#define MMCHS_CON_PADEN 0x00008000 // Control Power for MMC Lines: + // This register is only useful when + // MMC PADs contain power saving + // mechanism to minimize its leakage + // power. It works as a GPIO that + // directly control the ACTIVE pin + // of PADs. Excepted for DAT[1] the + // signal is also combine outside + // the module with the dedicated + // power control MMCHS_CON[CTPL] + // bit. 0 ADPIDLE module pin is not + // forced it is automatically + // generated by the MMC fsms. 1 + // ADPIDLE module pin is forced to + // active state. +#define MMCHS_CON_OBIE 0x00004000 // Out-of-Band Interrupt Enable MMC + // cards only: This bit enables the + // detection of Out-of-Band + // Interrupt on MMCOBI input pin. + // The usage of the Out-of-Band + // signal (OBI) is optional and + // depends on the system + // integration. 0 Out-of-Band + // interrupt detection disabled 1 + // Out-of-Band interrupt detection + // enabled +#define MMCHS_CON_OBIP 0x00002000 // Out-of-Band Interrupt Polarity + // MMC cards only: This bit selects + // the active level of the + // out-of-band interrupt coming from + // MMC cards. The usage of the + // Out-of-Band signal (OBI) is + // optional and depends on the + // system integration. 0 active high + // level 1 active low level +#define MMCHS_CON_CEATA 0x00001000 // CE-ATA control mode MMC cards + // compliant with CE-ATA:By default + // this bit is set to 0. It is use + // to indicate that next commands + // are considered as specific CE-ATA + // commands that potentially use + // 'command completion' features. 0 + // Standard MMC/SD/SDIO mode. 1 + // CE-ATA mode next commands are + // considered as CE-ATA commands. +#define MMCHS_CON_CTPL 0x00000800 // Control Power for DAT[1] line + // MMC and SD cards: By default this + // bit is set to 0 and the host + // controller automatically disables + // all the input buffers outside of + // a transaction to minimize the + // leakage current. SDIO cards: When + // this bit is set to 1 the host + // controller automatically disables + // all the input buffers except the + // buffer of DAT[1] outside of a + // transaction in order to detect + // asynchronous card interrupt on + // DAT[1] line and minimize the + // leakage current of the buffers. 0 + // Disable all the input buffers + // outside of a transaction. 1 + // Disable all the input buffers + // except the buffer of DAT[1] + // outside of a transaction. +#define MMCHS_CON_DVAL_M 0x00000600 // Debounce filter value All cards + // This register is used to define a + // debounce period to filter the + // card detect input signal (SDCD). + // The usage of the card detect + // input signal (SDCD) is optional + // and depends on the system + // integration and the type of the + // connector housing that + // accommodates the card. 0x0 33 us + // debounce period 0x1 231 us + // debounce period 0x2 1 ms debounce + // period 0x3 84 ms debounce period +#define MMCHS_CON_DVAL_S 9 +#define MMCHS_CON_WPP 0x00000100 // Write protect polarity For SD + // and SDIO cards only This bit + // selects the active level of the + // write protect input signal + // (SDWP). The usage of the write + // protect input signal (SDWP) is + // optional and depends on the + // system integration and the type + // of the connector housing that + // accommodates the card. 0 active + // high level 1 active low level +#define MMCHS_CON_CDP 0x00000080 // Card detect polarity All cards + // This bit selects the active level + // of the card detect input signal + // (SDCD). The usage of the card + // detect input signal (SDCD) is + // optional and depends on the + // system integration and the type + // of the connector housing that + // accommodates the card. 0 active + // high level 1 active low level +#define MMCHS_CON_MIT 0x00000040 // MMC interrupt command Only for + // MMC cards. This bit must be set + // to 1 when the next write access + // to the command register + // (MMCHS_CMD) is for writing a MMC + // interrupt command (CMD40) + // requiring the command timeout + // detection to be disabled for the + // command response. 0 Command + // timeout enabled 1 Command timeout + // disabled +#define MMCHS_CON_DW8 0x00000020 // 8-bit mode MMC select For + // SD/SDIO cards this bit must be + // set to 0. For MMC card this bit + // must be set following a valid + // SWITCH command (CMD6) with the + // correct value and extend CSD + // index written in the argument. + // Prior to this command the MMC + // card configuration register (CSD + // and EXT_CSD) must be verified for + // compliancy with MMC standard + // specification 4.x (see section + // 3.6). 0 1-bit or 4-bit Data width + // (DAT[0] used MMC SD cards) 1 + // 8-bit Data width (DAT[7:0] used + // MMC cards) +#define MMCHS_CON_MODE 0x00000010 // Mode select All cards These bits + // select between Functional mode + // and SYSTEST mode. 0 Functional + // mode. Transfers to the + // MMC/SD/SDIO cards follow the card + // protocol. MMC clock is enabled. + // MMC/SD transfers are operated + // under the control of the CMD + // register. 1 SYSTEST mode The + // signal pins are configured as + // general-purpose input/output and + // the 1024-byte buffer is + // configured as a stack memory + // accessible only by the local host + // or system DMA. The pins retain + // their default type (input output + // or in-out). SYSTEST mode is + // operated under the control of the + // SYSTEST register. +#define MMCHS_CON_STR 0x00000008 // Stream command Only for MMC + // cards. This bit must be set to 1 + // only for the stream data + // transfers (read or write) of the + // adtc commands. Stream read is a + // class 1 command (CMD11: + // READ_DAT_UNTIL_STOP). Stream + // write is a class 3 command + // (CMD20: WRITE_DAT_UNTIL_STOP). 0 + // Block oriented data transfer 1 + // Stream oriented data transfer +#define MMCHS_CON_HR 0x00000004 // Broadcast host response Only for + // MMC cards. This register is used + // to force the host to generate a + // 48-bit response for bc command + // type. "It can be used to + // terminate the interrupt mode by + // generating a CMD40 response by + // the core (see section 4.3 + // ""Interrupt Mode"" in the MMC [1] + // specification). In order to have + // the host response to be generated + // in open drain mode the register + // MMCHS_CON[OD] must be set to 1." + // When MMCHS_CON[CEATA] is set to 1 + // and MMCHS_ARG set to 0x00000000 + // when writing 0x00000000 into + // MMCHS_CMD register the host + // controller performs a 'command + // completion signal disable' token + // i.e. CMD line held to '0' during + // 47 cycles followed by a 1. 0 The + // host does not generate a 48-bit + // response instead of a command. 1 + // The host generates a 48-bit + // response instead of a command or + // a command completion signal + // disable token. +#define MMCHS_CON_INIT 0x00000002 // Send initialization stream All + // cards. When this bit is set to 1 + // and the card is idle an + // initialization sequence is sent + // to the card. "An initialization + // sequence consists of setting the + // CMD line to 1 during 80 clock + // cycles. The initialisation + // sequence is mandatory - but it is + // not required to do it through + // this bit - this bit makes it + // easier. Clock divider + // (MMCHS_SYSCTL[CLKD]) should be + // set to ensure that 80 clock + // periods are greater than 1ms. + // (see section 9.3 ""Power-Up"" in + // the MMC card specification [1] or + // section 6.4 in the SD card + // specification [2])." Note: in + // this mode there is no command + // sent to the card and no response + // is expected 0 The host does not + // send an initialization sequence. + // 1 The host sends an + // initialization sequence. +#define MMCHS_CON_OD 0x00000001 // Card open drain mode. Only for + // MMC cards. This bit must be set + // to 1 for MMC card commands 1 2 3 + // and 40 and if the MMC card bus is + // operating in open-drain mode + // during the response phase to the + // command sent. Typically during + // card identification mode when the + // card is either in idle ready or + // ident state. It is also necessary + // to set this bit to 1 for a + // broadcast host response (see + // Broadcast host response register + // MMCHS_CON[HR]) 0 No Open Drain 1 + // Open Drain or Broadcast host + // response +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_PWCNT register. +// +//****************************************************************************** +#define MMCHS_PWCNT_PWRCNT_M 0x0000FFFF // Power counter register. This + // register is used to introduce a + // delay between the PAD ACTIVE pin + // assertion and the command issued. + // 0x0000 No additional delay added + // 0x0001 TCF delay (card clock + // period) 0x0002 TCF x 2 delay + // (card clock period) 0xFFFE TCF x + // 65534 delay (card clock period) + // 0xFFFF TCF x 65535 delay (card + // clock period) +#define MMCHS_PWCNT_PWRCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_BLK register. +// +//****************************************************************************** +#define MMCHS_BLK_NBLK_M 0xFFFF0000 // Blocks count for current + // transfer This register is enabled + // when Block count Enable + // (MMCHS_CMD[BCE]) is set to 1 and + // is valid only for multiple block + // transfers. Setting the block + // count to 0 results no data blocks + // being transferred. Note: The host + // controller decrements the block + // count after each block transfer + // and stops when the count reaches + // zero. This register can be + // accessed only if no transaction + // is executing (i.e after a + // transaction has stopped). Read + // operations during transfers may + // return an invalid value and write + // operation will be ignored. In + // suspend context the number of + // blocks yet to be transferred can + // be determined by reading this + // register. When restoring transfer + // context prior to issuing a Resume + // command The local host shall + // restore the previously saved + // block count. 0x0000 Stop count + // 0x0001 1 block 0x0002 2 blocks + // 0xFFFF 65535 blocks +#define MMCHS_BLK_NBLK_S 16 +#define MMCHS_BLK_BLEN_M 0x00000FFF // Transfer Block Size. This + // register specifies the block size + // for block data transfers. Read + // operations during transfers may + // return an invalid value and write + // operations are ignored. When a + // CMD12 command is issued to stop + // the transfer a read of the BLEN + // field after transfer completion + // (MMCHS_STAT[TC] set to 1) will + // not return the true byte number + // of data length while the stop + // occurs but the value written in + // this register before transfer is + // launched. 0x000 No data transfer + // 0x001 1 byte block length 0x002 2 + // bytes block length 0x003 3 bytes + // block length 0x1FF 511 bytes + // block length 0x200 512 bytes + // block length 0x7FF 2047 bytes + // block length 0x800 2048 bytes + // block length +#define MMCHS_BLK_BLEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ARG register. +// +//****************************************************************************** +#define MMCHS_ARG_ARG_M 0xFFFFFFFF // Command argument bits [31:0] +#define MMCHS_ARG_ARG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CMD register. +// +//****************************************************************************** +#define MMCHS_CMD_INDX_M 0x3F000000 // Command index Binary encoded + // value from 0 to 63 specifying the + // command number send to card 0x00 + // CMD0 or ACMD0 0x01 CMD1 or ACMD1 + // 0x02 CMD2 or ACMD2 0x03 CMD3 or + // ACMD3 0x04 CMD4 or ACMD4 0x05 + // CMD5 or ACMD5 0x06 CMD6 or ACMD6 + // 0x07 CMD7 or ACMD7 0x08 CMD8 or + // ACMD8 0x09 CMD9 or ACMD9 0x0A + // CMD10 or ACMD10 0x0B CMD11 or + // ACMD11 0x0C CMD12 or ACMD12 0x0D + // CMD13 or ACMD13 0x0E CMD14 or + // ACMD14 0x0F CMD15 or ACMD15 0x10 + // CMD16 or ACMD16 0x11 CMD17 or + // ACMD17 0x12 CMD18 or ACMD18 0x13 + // CMD19 or ACMD19 0x14 CMD20 or + // ACMD20 0x15 CMD21 or ACMD21 0x16 + // CMD22 or ACMD22 0x17 CMD23 or + // ACMD23 0x18 CMD24 or ACMD24 0x19 + // CMD25 or ACMD25 0x1A CMD26 or + // ACMD26 0x1B CMD27 or ACMD27 0x1C + // CMD28 or ACMD28 0x1D CMD29 or + // ACMD29 0x1E CMD30 or ACMD30 0x1F + // CMD31 or ACMD31 0x20 CMD32 or + // ACMD32 0x21 CMD33 or ACMD33 0x22 + // CMD34 or ACMD34 0x23 CMD35 or + // ACMD35 0x24 CMD36 or ACMD36 0x25 + // CMD37 or ACMD37 0x26 CMD38 or + // ACMD38 0x27 CMD39 or ACMD39 0x28 + // CMD40 or ACMD40 0x29 CMD41 or + // ACMD41 0x2A CMD42 or ACMD42 0x2B + // CMD43 or ACMD43 0x2C CMD44 or + // ACMD44 0x2D CMD45 or ACMD45 0x2E + // CMD46 or ACMD46 0x2F CMD47 or + // ACMD47 0x30 CMD48 or ACMD48 0x31 + // CMD49 or ACMD49 0x32 CMD50 or + // ACMD50 0x33 CMD51 or ACMD51 0x34 + // CMD52 or ACMD52 0x35 CMD53 or + // ACMD53 0x36 CMD54 or ACMD54 0x37 + // CMD55 or ACMD55 0x38 CMD56 or + // ACMD56 0x39 CMD57 or ACMD57 0x3A + // CMD58 or ACMD58 0x3B CMD59 or + // ACMD59 0x3C CMD60 or ACMD60 0x3D + // CMD61 or ACMD61 0x3E CMD62 or + // ACMD62 0x3F CMD63 or ACMD63 +#define MMCHS_CMD_INDX_S 24 +#define MMCHS_CMD_CMD_TYPE_M 0x00C00000 // Command type This register + // specifies three types of special + // command: Suspend Resume and + // Abort. These bits shall be set to + // 00b for all other commands. 0x0 + // Others Commands 0x1 "CMD52 for + // writing ""Bus Suspend"" in CCCR" + // 0x2 "CMD52 for writing ""Function + // Select"" in CCCR" 0x3 "Abort + // command CMD12 CMD52 for writing + // "" I/O Abort"" in CCCR" +#define MMCHS_CMD_CMD_TYPE_S 22 +#define MMCHS_CMD_DP 0x00200000 // Data present select This + // register indicates that data is + // present and DAT line shall be + // used. It must be set to 0 in the + // following conditions: - command + // using only CMD line - command + // with no data transfer but using + // busy signal on DAT[0] - Resume + // command 0 Command with no data + // transfer 1 Command with data + // transfer +#define MMCHS_CMD_CICE 0x00100000 // Command Index check enable This + // bit must be set to 1 to enable + // index check on command response + // to compare the index field in the + // response against the index of the + // command. If the index is not the + // same in the response as in the + // command it is reported as a + // command index error + // (MMCHS_STAT[CIE] set to1) Note: + // The register CICE cannot be + // configured for an Auto CMD12 then + // index check is automatically + // checked when this command is + // issued. 0 Index check disable 1 + // Index check enable +#define MMCHS_CMD_CCCE 0x00080000 // Command CRC check enable This + // bit must be set to 1 to enable + // CRC7 check on command response to + // protect the response against + // transmission errors on the bus. + // If an error is detected it is + // reported as a command CRC error + // (MMCHS_STAT[CCRC] set to 1). + // Note: The register CCCE cannot be + // configured for an Auto CMD12 and + // then CRC check is automatically + // checked when this command is + // issued. 0 CRC7 check disable 1 + // CRC7 check enable +#define MMCHS_CMD_RSP_TYPE_M 0x00030000 // Response type This bits defines + // the response type of the command + // 0x0 No response 0x1 Response + // Length 136 bits 0x2 Response + // Length 48 bits 0x3 Response + // Length 48 bits with busy after + // response +#define MMCHS_CMD_RSP_TYPE_S 16 +#define MMCHS_CMD_MSBS 0x00000020 // Multi/Single block select This + // bit must be set to 1 for data + // transfer in case of multi block + // command. For any others command + // this bit shall be set to 0. 0 + // Single block. If this bit is 0 it + // is not necessary to set the + // register MMCHS_BLK[NBLK]. 1 Multi + // block. When Block Count is + // disabled (MMCHS_CMD[BCE] is set + // to 0) in Multiple block transfers + // (MMCHS_CMD[MSBS] is set to 1) the + // module can perform infinite + // transfer. +#define MMCHS_CMD_DDIR 0x00000010 // Data transfer Direction Select + // This bit defines either data + // transfer will be a read or a + // write. 0 Data Write (host to + // card) 1 Data Read (card to host) +#define MMCHS_CMD_ACEN 0x00000004 // Auto CMD12 Enable SD card only. + // When this bit is set to 1 the + // host controller issues a CMD12 + // automatically after the transfer + // completion of the last block. The + // Host Driver shall not set this + // bit to issue commands that do not + // require CMD12 to stop data + // transfer. In particular secure + // commands do not require CMD12. 0 + // Auto CMD12 disable 1 Auto CMD12 + // enable or CCS detection enabled. +#define MMCHS_CMD_BCE 0x00000002 // Block Count Enable Multiple + // block transfers only. This bit is + // used to enable the block count + // register (MMCHS_BLK[NBLK]). When + // Block Count is disabled + // (MMCHS_CMD[BCE] is set to 0) in + // Multiple block transfers + // (MMCHS_CMD[MSBS] is set to 1) the + // module can perform infinite + // transfer. 0 Block count disabled + // for infinite transfer. 1 Block + // count enabled for multiple block + // transfer with known number of + // blocks +#define MMCHS_CMD_DE 0x00000001 // DMA Enable This bit is used to + // enable DMA mode for host data + // access. 0 DMA mode disable 1 DMA + // mode enable +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP10 register. +// +//****************************************************************************** +#define MMCHS_RSP10_RSP1_M 0xFFFF0000 // Command Response [31:16] +#define MMCHS_RSP10_RSP1_S 16 +#define MMCHS_RSP10_RSP0_M 0x0000FFFF // Command Response [15:0] +#define MMCHS_RSP10_RSP0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP32 register. +// +//****************************************************************************** +#define MMCHS_RSP32_RSP3_M 0xFFFF0000 // Command Response [63:48] +#define MMCHS_RSP32_RSP3_S 16 +#define MMCHS_RSP32_RSP2_M 0x0000FFFF // Command Response [47:32] +#define MMCHS_RSP32_RSP2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP54 register. +// +//****************************************************************************** +#define MMCHS_RSP54_RSP5_M 0xFFFF0000 // Command Response [95:80] +#define MMCHS_RSP54_RSP5_S 16 +#define MMCHS_RSP54_RSP4_M 0x0000FFFF // Command Response [79:64] +#define MMCHS_RSP54_RSP4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP76 register. +// +//****************************************************************************** +#define MMCHS_RSP76_RSP7_M 0xFFFF0000 // Command Response [127:112] +#define MMCHS_RSP76_RSP7_S 16 +#define MMCHS_RSP76_RSP6_M 0x0000FFFF // Command Response [111:96] +#define MMCHS_RSP76_RSP6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_DATA register. +// +//****************************************************************************** +#define MMCHS_DATA_DATA_M 0xFFFFFFFF // Data Register [31:0] In + // functional mode (MMCHS_CON[MODE] + // set to the default value 0) A + // read access to this register is + // allowed only when the buffer read + // enable status is set to 1 + // (MMCHS_PSTATE[BRE]) otherwise a + // bad access (MMCHS_STAT[BADA]) is + // signaled. A write access to this + // register is allowed only when the + // buffer write enable status is set + // to 1(MMCHS_STATE[BWE]) otherwise + // a bad access (MMCHS_STAT[BADA]) + // is signaled and the data is not + // written. +#define MMCHS_DATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_PSTATE register. +// +//****************************************************************************** +#define MMCHS_PSTATE_CLEV 0x01000000 +#define MMCHS_PSTATE_DLEV_M 0x00F00000 // DAT[3:0] line signal level + // DAT[3] => bit 23 DAT[2] => bit 22 + // DAT[1] => bit 21 DAT[0] => bit 20 + // This status is used to check DAT + // line level to recover from errors + // and for debugging. This is + // especially useful in detecting + // the busy signal level from + // DAT[0]. The value of these + // registers after reset depends on + // the DAT lines level at that time. +#define MMCHS_PSTATE_DLEV_S 20 +#define MMCHS_PSTATE_WP 0x00080000 +#define MMCHS_PSTATE_CDPL 0x00040000 +#define MMCHS_PSTATE_CSS 0x00020000 +#define MMCHS_PSTATE_CINS 0x00010000 +#define MMCHS_PSTATE_BRE 0x00000800 +#define MMCHS_PSTATE_BWE 0x00000400 +#define MMCHS_PSTATE_RTA 0x00000200 +#define MMCHS_PSTATE_WTA 0x00000100 +#define MMCHS_PSTATE_DLA 0x00000004 +#define MMCHS_PSTATE_DATI 0x00000002 +#define MMCHS_PSTATE_CMDI 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HCTL register. +// +//****************************************************************************** +#define MMCHS_HCTL_OBWE 0x08000000 // Wakeup event enable for + // 'Out-of-Band' Interrupt. This bit + // enables wakeup events for + // 'Out-of-Band' assertion. Wakeup + // is generated if the wakeup + // feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). The + // write to this register is ignored + // when MMCHS_CON[OBIE] is not set. + // 0 Disable wakeup on 'Out-of-Band' + // Interrupt 1 Enable wakeup on + // 'Out-of-Band' Interrupt +#define MMCHS_HCTL_REM 0x04000000 // Wakeup event enable on SD card + // removal This bit enables wakeup + // events for card removal + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card removal 1 + // Enable wakeup on card removal +#define MMCHS_HCTL_INS 0x02000000 // Wakeup event enable on SD card + // insertion This bit enables wakeup + // events for card insertion + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card insertion + // 1 Enable wakeup on card insertion +#define MMCHS_HCTL_IWE 0x01000000 // Wakeup event enable on SD card + // interrupt This bit enables wakeup + // events for card interrupt + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card interrupt + // 1 Enable wakeup on card interrupt +#define MMCHS_HCTL_IBG 0x00080000 // Interrupt block at gap This bit + // is valid only in 4-bit mode of + // SDIO card to enable interrupt + // detection in the interrupt cycle + // at block gap for a multiple block + // transfer. For MMC cards and for + // SD card this bit should be set to + // 0. 0 Disable interrupt detection + // at the block gap in 4-bit mode 1 + // Enable interrupt detection at the + // block gap in 4-bit mode +#define MMCHS_HCTL_RWC 0x00040000 // Read wait control The read wait + // function is optional only for + // SDIO cards. If the card supports + // read wait this bit must be + // enabled then requesting a stop at + // block gap (MMCHS_HCTL[SBGR]) + // generates a read wait period + // after the current end of block. + // Be careful if read wait is not + // supported it may cause a conflict + // on DAT line. 0 Disable Read Wait + // Control. Suspend/Resume cannot be + // supported. 1 Enable Read Wait + // Control +#define MMCHS_HCTL_CR 0x00020000 // Continue request This bit is + // used to restart a transaction + // that was stopped by requesting a + // stop at block gap + // (MMCHS_HCTL[SBGR]). Set this bit + // to 1 restarts the transfer. The + // bit is automatically set to 0 by + // the host controller when transfer + // has restarted i.e DAT line is + // active (MMCHS_PSTATE[DLA]) or + // transferring data + // (MMCHS_PSTATE[WTA]). The Stop at + // block gap request must be + // disabled (MMCHS_HCTL[SBGR]=0) + // before setting this bit. 0 No + // affect 1 transfer restart +#define MMCHS_HCTL_SBGR 0x00010000 // Stop at block gap request This + // bit is used to stop executing a + // transaction at the next block + // gap. The transfer can restart + // with a continue request + // (MMHS_HCTL[CR]) or during a + // suspend/resume sequence. In case + // of read transfer the card must + // support read wait control. In + // case of write transfer the host + // driver shall set this bit after + // all block data written. Until the + // transfer completion + // (MMCHS_STAT[TC] set to 1) the + // host driver shall leave this bit + // set to 1. If this bit is set the + // local host shall not write to the + // data register (MMCHS_DATA). 0 + // Transfer mode 1 Stop at block gap +#define MMCHS_HCTL_SDVS_M 0x00000E00 // SD bus voltage select All cards. + // The host driver should set to + // these bits to select the voltage + // level for the card according to + // the voltage supported by the + // system (MMCHS_CAPA[VS18VS30VS33]) + // before starting a transfer. 0x5 + // 1.8V (Typical) 0x6 3.0V (Typical) + // 0x7 3.3V (Typical) +#define MMCHS_HCTL_SDVS_S 9 +#define MMCHS_HCTL_SDBP 0x00000100 // SD bus power Before setting this + // bit the host driver shall select + // the SD bus voltage + // (MMCHS_HCTL[SDVS]). If the host + // controller detects the No card + // state this bit is automatically + // set to 0. If the module is power + // off a write in the command + // register (MMCHS_CMD) will not + // start the transfer. A write to + // this bit has no effect if the + // selected SD bus voltage + // MMCHS_HCTL[SDVS] is not supported + // according to capability register + // (MMCHS_CAPA[VS*]). 0 Power off 1 + // Power on +#define MMCHS_HCTL_CDSS 0x00000080 // Card Detect Signal Selection + // This bit selects source for the + // card detection.When the source + // for the card detection is + // switched the interrupt should be + // disabled during the switching + // period by clearing the Interrupt + // Status/Signal Enable register in + // order to mask unexpected + // interrupt being caused by the + // glitch. The Interrupt + // Status/Signal Enable should be + // disabled during over the period + // of debouncing. 0 SDCD# is + // selected (for normal use) 1 The + // Card Detect Test Level is + // selected (for test purpose) +#define MMCHS_HCTL_CDTL 0x00000040 // Card Detect Test Level: This bit + // is enabled while the Card Detect + // Signal Selection is set to 1 and + // it indicates card inserted or + // not. 0 No Card 1 Card Inserted +#define MMCHS_HCTL_DMAS_M 0x00000018 // DMA Select Mode: One of + // supported DMA modes can be + // selected. The host driver shall + // check support of DMA modes by + // referring the Capabilities + // register. Use of selected DMA is + // determined by DMA Enable of the + // Transfer Mode register. This + // register is only meaningful when + // MADMA_EN is set to 1. When + // MADMA_EN is set to 0 the bit + // field is read only and returned + // value is 0. 0x0 Reserved 0x1 + // Reserved 0x2 32-bit Address ADMA2 + // is selected 0x3 Reserved +#define MMCHS_HCTL_DMAS_S 3 +#define MMCHS_HCTL_HSPE 0x00000004 // High Speed Enable: Before + // setting this bit the Host Driver + // shall check the High Speed + // Support in the Capabilities + // register. If this bit is set to 0 + // (default) the Host Controller + // outputs CMD line and DAT lines at + // the falling edge of the SD Clock. + // If this bit is set to 1 the Host + // Controller outputs CMD line and + // DAT lines at the rising edge of + // the SD Clock.This bit shall not + // be set when dual data rate mode + // is activated in MMCHS_CON[DDR]. 0 + // Normal speed mode 1 High speed + // mode +#define MMCHS_HCTL_DTW 0x00000002 // Data transfer width For MMC card + // this bit must be set following a + // valid SWITCH command (CMD6) with + // the correct value and extend CSD + // index written in the argument. + // Prior to this command the MMC + // card configuration register (CSD + // and EXT_CSD) must be verified for + // compliance with MMC standard + // specification 4.x (see section + // 3.6). This register has no effect + // when the MMC 8-bit mode is + // selected (register MMCHS_CON[DW8] + // set to1 ) For SD/SDIO cards this + // bit must be set following a valid + // SET_BUS_WIDTH command (ACMD6) + // with the value written in bit 1 + // of the argument. Prior to this + // command the SD card configuration + // register (SCR) must be verified + // for the supported bus width by + // the SD card. 0 1-bit Data width + // (DAT[0] used) 1 4-bit Data width + // (DAT[3:0] used) +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSCTL register. +// +//****************************************************************************** +#define MMCHS_SYSCTL_SRD 0x04000000 // Software reset for DAT line This + // bit is set to 1 for reset and + // released to 0 when completed. DAT + // finite state machine in both + // clock domain are also reset. Here + // below are the registers cleared + // by MMCHS_SYSCTL[SRD]: #VALUE! - + // MMCHS_PSTATE: BRE BWE RTA WTA DLA + // and DATI - MMCHS_HCTL: SBGR and + // CR - MMCHS_STAT: BRR BWR BGE and + // TC OCP and MMC buffer data + // management is reinitialized. 0 + // Reset completed 1 Software reset + // for DAT line +#define MMCHS_SYSCTL_SRC 0x02000000 // Software reset for CMD line This + // bit is set to 1 for reset and + // released to 0 when completed. CMD + // finite state machine in both + // clock domain are also reset. Here + // below the registers cleared by + // MMCHS_SYSCTL[SRC]: - + // MMCHS_PSTATE: CMDI - MMCHS_STAT: + // CC OCP and MMC command status + // management is reinitialized. 0 + // Reset completed 1 Software reset + // for CMD line +#define MMCHS_SYSCTL_SRA 0x01000000 // Software reset for all This bit + // is set to 1 for reset and + // released to 0 when completed. + // This reset affects the entire + // host controller except for the + // card detection circuit and + // capabilities registers. 0 Reset + // completed 1 Software reset for + // all the design +#define MMCHS_SYSCTL_DTO_M 0x000F0000 // Data timeout counter value and + // busy timeout. This value + // determines the interval by which + // DAT lines timeouts are detected. + // The host driver needs to set this + // bitfield based on - the maximum + // read access time (NAC) (Refer to + // the SD Specification Part1 + // Physical Layer) - the data read + // access time values (TAAC and + // NSAC) in the card specific data + // register (CSD) of the card - the + // timeout clock base frequency + // (MMCHS_CAPA[TCF]). If the card + // does not respond within the + // specified number of cycles a data + // timeout error occurs + // (MMCHS_STA[DTO]). The + // MMCHS_SYSCTL[DTO] register is + // also used to check busy duration + // to generate busy timeout for + // commands with busy response or + // for busy programming during a + // write command. Timeout on CRC + // status is generated if no CRC + // token is present after a block + // write. 0x0 TCF x 2^13 0x1 TCF x + // 2^14 0xE TCF x 2^27 0xF Reserved +#define MMCHS_SYSCTL_DTO_S 16 +#define MMCHS_SYSCTL_CLKD_M 0x0000FFC0 // Clock frequency select These + // bits define the ratio between a + // reference clock frequency (system + // dependant) and the output clock + // frequency on the CLK pin of + // either the memory card (MMC SD or + // SDIO). 0x000 Clock Ref bypass + // 0x001 Clock Ref bypass 0x002 + // Clock Ref / 2 0x003 Clock Ref / 3 + // 0x3FF Clock Ref / 1023 +#define MMCHS_SYSCTL_CLKD_S 6 +#define MMCHS_SYSCTL_CEN 0x00000004 // Clock enable This bit controls + // if the clock is provided to the + // card or not. 0 The clock is not + // provided to the card . Clock + // frequency can be changed . 1 The + // clock is provided to the card and + // can be automatically gated when + // MMCHS_SYSCONFIG[AUTOIDLE] is set + // to 1 (default value) . The host + // driver shall wait to set this bit + // to 1 until the Internal clock is + // stable (MMCHS_SYSCTL[ICS]). +#define MMCHS_SYSCTL_ICS 0x00000002 +#define MMCHS_SYSCTL_ICE 0x00000001 // Internal clock enable This + // register controls the internal + // clock activity. In very low power + // state the internal clock is + // stopped. Note: The activity of + // the debounce clock (used for + // wakeup events) and the OCP clock + // (used for reads and writes to the + // module register map) are not + // affected by this register. 0 The + // internal clock is stopped (very + // low power state). 1 The internal + // clock oscillates and can be + // automatically gated when + // MMCHS_SYSCONFIG[AUTOIDLE] is set + // to 1 (default value) . +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_STAT register. +// +//****************************************************************************** +#define MMCHS_STAT_BADA 0x20000000 +#define MMCHS_STAT_CERR 0x10000000 +#define MMCHS_STAT_ADMAE 0x02000000 +#define MMCHS_STAT_ACE 0x01000000 +#define MMCHS_STAT_DEB 0x00400000 +#define MMCHS_STAT_DCRC 0x00200000 +#define MMCHS_STAT_DTO 0x00100000 +#define MMCHS_STAT_CIE 0x00080000 +#define MMCHS_STAT_CEB 0x00040000 +#define MMCHS_STAT_CCRC 0x00020000 +#define MMCHS_STAT_CTO 0x00010000 +#define MMCHS_STAT_ERRI 0x00008000 +#define MMCHS_STAT_BSR 0x00000400 +#define MMCHS_STAT_OBI 0x00000200 +#define MMCHS_STAT_CIRQ 0x00000100 +#define MMCHS_STAT_CREM 0x00000080 +#define MMCHS_STAT_CINS 0x00000040 +#define MMCHS_STAT_BRR 0x00000020 +#define MMCHS_STAT_BWR 0x00000010 +#define MMCHS_STAT_DMA 0x00000008 +#define MMCHS_STAT_BGE 0x00000004 +#define MMCHS_STAT_TC 0x00000002 +#define MMCHS_STAT_CC 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_IE register. +// +//****************************************************************************** +#define MMCHS_IE_BADA_ENABLE 0x20000000 // Bad access to data space + // Interrupt Enable 0 Masked 1 + // Enabled +#define MMCHS_IE_CERR_ENABLE 0x10000000 // Card error interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_ADMAE_ENABLE 0x02000000 // ADMA error Interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_ACE_ENABLE 0x01000000 // Auto CMD12 error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DEB_ENABLE 0x00400000 // Data end bit error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DCRC_ENABLE 0x00200000 // Data CRC error Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_DTO_ENABLE 0x00100000 // Data timeout error Interrupt + // Enable 0 The data timeout + // detection is deactivated. The + // host controller provides the + // clock to the card until the card + // sends the data or the transfer is + // aborted. 1 The data timeout + // detection is enabled. +#define MMCHS_IE_CIE_ENABLE 0x00080000 // Command index error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CEB_ENABLE 0x00040000 // Command end bit error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CCRC_ENABLE 0x00020000 // Command CRC error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CTO_ENABLE 0x00010000 // Command timeout error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_NULL 0x00008000 // Fixed to 0 The host driver shall + // control error interrupts using + // the Error Interrupt Signal Enable + // register. Writes to this bit are + // ignored +#define MMCHS_IE_BSR_ENABLE 0x00000400 // Boot status interrupt Enable A + // write to this register when + // MMCHS_CON[BOOT_ACK] is set to 0x0 + // is ignored. 0 Masked 1 Enabled +#define MMCHS_IE_OBI_ENABLE 0x00000200 // Out-of-Band interrupt Enable A + // write to this register when + // MMCHS_CON[OBIE] is set to '0' is + // ignored. 0 Masked 1 Enabled +#define MMCHS_IE_CIRQ_ENABLE 0x00000100 // Card interrupt Enable A clear of + // this bit also clears the + // corresponding status bit. During + // 1-bit mode if the interrupt + // routine doesn't remove the source + // of a card interrupt in the SDIO + // card the status bit is reasserted + // when this bit is set to 1. 0 + // Masked 1 Enabled +#define MMCHS_IE_CREM_ENABLE 0x00000080 // Card removal Interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_CINS_ENABLE 0x00000040 // Card insertion Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_BRR_ENABLE 0x00000020 // Buffer Read Ready Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_BWR_ENABLE 0x00000010 // Buffer Write Ready Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DMA_ENABLE 0x00000008 // DMA interrupt Enable 0 Masked 1 + // Enabled +#define MMCHS_IE_BGE_ENABLE 0x00000004 // Block Gap Event Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_TC_ENABLE 0x00000002 // Transfer completed Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CC_ENABLE 0x00000001 // Command completed Interrupt + // Enable 0 Masked 1 Enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ISE register. +// +//****************************************************************************** +#define MMCHS_ISE_BADA_SIGEN 0x20000000 // Bad access to data space signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CERR_SIGEN 0x10000000 // Card error interrupt signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_ADMAE_SIGEN 0x02000000 // ADMA error signal status Enable + // 0 Masked 1 Enabled +#define MMCHS_ISE_ACE_SIGEN 0x01000000 // Auto CMD12 error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DEB_SIGEN 0x00400000 // Data end bit error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DCRC_SIGEN 0x00200000 // Data CRC error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DTO_SIGEN 0x00100000 // Data timeout error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CIE_SIGEN 0x00080000 // Command index error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CEB_SIGEN 0x00040000 // Command end bit error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CCRC_SIGEN 0x00020000 // Command CRC error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CTO_SIGEN 0x00010000 // Command timeout error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_NULL 0x00008000 // Fixed to 0 The host driver shall + // control error interrupts using + // the Error Interrupt Signal Enable + // register. Writes to this bit are + // ignored +#define MMCHS_ISE_BSR_SIGEN 0x00000400 // Boot status signal status + // EnableA write to this register + // when MMCHS_CON[BOOT_ACK] is set + // to 0x0 is ignored. 0 Masked 1 + // Enabled +#define MMCHS_ISE_OBI_SIGEN 0x00000200 // Out-Of-Band Interrupt signal + // status Enable A write to this + // register when MMCHS_CON[OBIE] is + // set to '0' is ignored. 0 Masked 1 + // Enabled +#define MMCHS_ISE_CIRQ_SIGEN 0x00000100 // Card interrupt signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CREM_SIGEN 0x00000080 // Card removal signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CINS_SIGEN 0x00000040 // Card insertion signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_BRR_SIGEN 0x00000020 // Buffer Read Ready signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_BWR_SIGEN 0x00000010 // Buffer Write Ready signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DMA_SIGEN 0x00000008 // DMA interrupt Signal status + // enable 0 Masked 1 Enabled +#define MMCHS_ISE_BGE_SIGEN 0x00000004 // Black Gap Event signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_TC_SIGEN 0x00000002 // Transfer completed signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CC_SIGEN 0x00000001 // Command completed signal status + // Enable 0 Masked 1 Enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_AC12 register. +// +//****************************************************************************** +#define MMCHS_AC12_CNI 0x00000080 +#define MMCHS_AC12_ACIE 0x00000010 +#define MMCHS_AC12_ACEB 0x00000008 +#define MMCHS_AC12_ACCE 0x00000004 +#define MMCHS_AC12_ACTO 0x00000002 +#define MMCHS_AC12_ACNE 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CAPA register. +// +//****************************************************************************** +#define MMCHS_CAPA_BIT64 0x10000000 +#define MMCHS_CAPA_VS18 0x04000000 +#define MMCHS_CAPA_VS30 0x02000000 +#define MMCHS_CAPA_VS33 0x01000000 +#define MMCHS_CAPA_SRS 0x00800000 +#define MMCHS_CAPA_DS 0x00400000 +#define MMCHS_CAPA_HSS 0x00200000 +#define MMCHS_CAPA_AD2S 0x00080000 +#define MMCHS_CAPA_MBL_M 0x00030000 +#define MMCHS_CAPA_MBL_S 16 +#define MMCHS_CAPA_BCF_M 0x00003F00 +#define MMCHS_CAPA_BCF_S 8 +#define MMCHS_CAPA_TCU 0x00000080 +#define MMCHS_CAPA_TCF_M 0x0000003F +#define MMCHS_CAPA_TCF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register. +// +//****************************************************************************** +#define MMCHS_CUR_CAPA_CUR_1V8_M \ + 0x00FF0000 + +#define MMCHS_CUR_CAPA_CUR_1V8_S 16 +#define MMCHS_CUR_CAPA_CUR_3V0_M \ + 0x0000FF00 + +#define MMCHS_CUR_CAPA_CUR_3V0_S 8 +#define MMCHS_CUR_CAPA_CUR_3V3_M \ + 0x000000FF + +#define MMCHS_CUR_CAPA_CUR_3V3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_FE register. +// +//****************************************************************************** +#define MMCHS_FE_FE_BADA 0x20000000 +#define MMCHS_FE_FE_CERR 0x10000000 +#define MMCHS_FE_FE_ADMAE 0x02000000 +#define MMCHS_FE_FE_ACE 0x01000000 +#define MMCHS_FE_FE_DEB 0x00400000 +#define MMCHS_FE_FE_DCRC 0x00200000 +#define MMCHS_FE_FE_DTO 0x00100000 +#define MMCHS_FE_FE_CIE 0x00080000 +#define MMCHS_FE_FE_CEB 0x00040000 +#define MMCHS_FE_FE_CCRC 0x00020000 +#define MMCHS_FE_FE_CTO 0x00010000 +#define MMCHS_FE_FE_CNI 0x00000080 +#define MMCHS_FE_FE_ACIE 0x00000010 +#define MMCHS_FE_FE_ACEB 0x00000008 +#define MMCHS_FE_FE_ACCE 0x00000004 +#define MMCHS_FE_FE_ACTO 0x00000002 +#define MMCHS_FE_FE_ACNE 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ADMAES register. +// +//****************************************************************************** +#define MMCHS_ADMAES_LME 0x00000004 // ADMA Length Mismatch Error: (1) + // While Block Count Enable being + // set the total data length + // specified by the Descriptor table + // is different from that specified + // by the Block Count and Block + // Length. (2) Total data length can + // not be divided by the block + // length. 0 No Error 1 Error +#define MMCHS_ADMAES_AES_M 0x00000003 // ADMA Error State his field + // indicates the state of ADMA when + // error is occurred during ADMA + // data transfer. "This field never + // indicates ""10"" because ADMA + // never stops in this state." 0x0 + // ST_STOP (Stop DMA)Contents of + // SYS_SDR register 0x1 ST_STOP + // (Stop DMA)Points the error + // descriptor 0x2 Never set this + // state(Not used) 0x3 ST_TFR + // (Transfer Data)Points the next of + // the error descriptor +#define MMCHS_ADMAES_AES_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ADMASAL register. +// +//****************************************************************************** +#define MMCHS_ADMASAL_ADMA_A32B_M \ + 0xFFFFFFFF // ADMA System address 32 bits.This + // register holds byte address of + // executing command of the + // Descriptor table. 32-bit Address + // Descriptor uses lower 32-bit of + // this register. At the start of + // ADMA the Host Driver shall set + // start address of the Descriptor + // table. The ADMA increments this + // register address which points to + // next line when every fetching a + // Descriptor line. When the ADMA + // Error Interrupt is generated this + // register shall hold valid + // Descriptor address depending on + // the ADMA state. The Host Driver + // shall program Descriptor Table on + // 32-bit boundary and set 32-bit + // boundary address to this + // register. ADMA2 ignores lower + // 2-bit of this register and + // assumes it to be 00b. + +#define MMCHS_ADMASAL_ADMA_A32B_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_REV register. +// +//****************************************************************************** +#define MMCHS_REV_VREV_M 0xFF000000 // Vendor Version Number: IP + // revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 +#define MMCHS_REV_VREV_S 24 +#define MMCHS_REV_SREV_M 0x00FF0000 +#define MMCHS_REV_SREV_S 16 +#define MMCHS_REV_SIS 0x00000001 // Slot Interrupt Status This + // status bit indicates the inverted + // state of interrupt signal for the + // module. By a power on reset or by + // setting a software reset for all + // (MMCHS_HCTL[SRA]) the interrupt + // signal shall be de-asserted and + // this status shall read 0. + + + +#endif // __HW_MMCHS_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_nvic.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_nvic.h new file mode 100644 index 0000000000..1545f22651 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_nvic.h @@ -0,0 +1,1710 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg + +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable +#define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable + +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable + +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable +#define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable + +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending + +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending +#define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending + +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending + +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending +#define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending + +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit + +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit +#define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit + +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority + +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority +#define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority +#define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority +#define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority +#define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority +#define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority +#define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority +#define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority +#define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority +#define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority +#define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority +#define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority +#define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority +#define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority +#define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority + + + +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable + +#undef NVIC_EN1_INT_M +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable + +#undef NVIC_DIS1_INT_M +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending + +#undef NVIC_PEND1_INT_M +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending + +#undef NVIC_UNPEND1_INT_M +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active + +#undef NVIC_ACTIVE1_INT_M +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor + +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor + +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number + +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number + +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number + +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number + +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset + +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset + +#define NVIC_VTABLE_OFFSET_S 9 + +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid + +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation + +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid + +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation + +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID + +#undef NVIC_SW_TRIG_INTID_M +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID + +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ocp_shared.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ocp_shared.h new file mode 100644 index 0000000000..a52f6901b7 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ocp_shared.h @@ -0,0 +1,3445 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_OCP_SHARED_H__ +#define __HW_OCP_SHARED_H__ + +//***************************************************************************** +// +// The following are defines for the OCP_SHARED register offsets. +// +//***************************************************************************** +#define OCP_SHARED_O_SEMAPHORE1 0x00000000 +#define OCP_SHARED_O_SEMAPHORE2 0x00000004 +#define OCP_SHARED_O_SEMAPHORE3 0x00000008 +#define OCP_SHARED_O_SEMAPHORE4 0x0000000C +#define OCP_SHARED_O_SEMAPHORE5 0x00000010 +#define OCP_SHARED_O_SEMAPHORE6 0x00000014 +#define OCP_SHARED_O_SEMAPHORE7 0x00000018 +#define OCP_SHARED_O_SEMAPHORE8 0x0000001C +#define OCP_SHARED_O_SEMAPHORE9 0x00000020 +#define OCP_SHARED_O_SEMAPHORE10 \ + 0x00000024 + +#define OCP_SHARED_O_SEMAPHORE11 \ + 0x00000028 + +#define OCP_SHARED_O_SEMAPHORE12 \ + 0x0000002C + +#define OCP_SHARED_O_IC_LOCKER_ID \ + 0x00000030 + +#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \ + 0x00000034 + +#define OCP_SHARED_O_WL_SEMAPHORE_PEND \ + 0x00000038 + +#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \ + 0x0000003C + +#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \ + 0x00000040 + +#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \ + 0x00000044 + +#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \ + 0x00000048 + +#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \ + 0x0000004C + +#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \ + 0x00000050 + +#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \ + 0x00000054 + +#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \ + 0x00000058 + +#define OCP_SHARED_O_SSBD_SEED 0x0000005C +#define OCP_SHARED_O_SSBD_CHK 0x00000060 +#define OCP_SHARED_O_SSBD_POLY_SEL \ + 0x00000064 + +#define OCP_SHARED_O_SPARE_REG_0 \ + 0x00000068 + +#define OCP_SHARED_O_SPARE_REG_1 \ + 0x0000006C + +#define OCP_SHARED_O_SPARE_REG_2 \ + 0x00000070 + +#define OCP_SHARED_O_SPARE_REG_3 \ + 0x00000074 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \ + 0x000000A0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \ + 0x000000A4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \ + 0x000000A8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \ + 0x000000AC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \ + 0x000000B0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \ + 0x000000B4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \ + 0x000000B8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \ + 0x000000BC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \ + 0x000000C0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \ + 0x000000C4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \ + 0x000000C8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \ + 0x000000CC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \ + 0x000000D0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \ + 0x000000D4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \ + 0x000000D8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \ + 0x000000DC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \ + 0x000000E0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \ + 0x000000E4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \ + 0x000000E8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \ + 0x000000EC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \ + 0x000000F0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \ + 0x000000F4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \ + 0x000000F8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \ + 0x000000FC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \ + 0x00000100 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \ + 0x00000104 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \ + 0x00000108 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \ + 0x0000010C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \ + 0x00000110 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \ + 0x00000114 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \ + 0x00000118 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \ + 0x0000011C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \ + 0x00000120 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \ + 0x00000124 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \ + 0x00000128 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \ + 0x0000012C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \ + 0x00000130 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \ + 0x00000134 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \ + 0x00000138 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \ + 0x0000013C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \ + 0x00000140 + +#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \ + 0x00000144 // This register provide control to + // GPIO_CC3XXV1 IO PAD. Common + // control signals to all bottom Die + // IO's are controlled via this. + +#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \ + 0x00000148 + +#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \ + 0x0000014C + +#define OCP_SHARED_O_D2D_MISC_PAD_CONF \ + 0x00000150 + +#define OCP_SHARED_O_SOP_CONF_OVERRIDE \ + 0x00000154 + +#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \ + 0x00000158 + +#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \ + 0x0000015C + +#define OCP_SHARED_O_ALT_PC_VAL_NW \ + 0x00000160 + +#define OCP_SHARED_O_ALT_PC_VAL_APPS \ + 0x00000164 + +#define OCP_SHARED_O_SPARE_REG_4 \ + 0x00000168 + +#define OCP_SHARED_O_SPARE_REG_5 \ + 0x0000016C + +#define OCP_SHARED_O_SH_SPI_CS_MASK \ + 0x00000170 + +#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \ + 0x00000174 + +#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \ + 0x00000178 + +#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \ + 0x0000017C + +#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \ + 0x00000180 + +#define OCP_SHARED_O_CC3XX_DEV_PADCONF \ + 0x00000184 + +#define OCP_SHARED_O_SPARE_REG_8 \ + 0x00000188 + +#define OCP_SHARED_O_SPARE_REG_6 \ + 0x0000018C + +#define OCP_SHARED_O_SPARE_REG_7 \ + 0x00000190 + +#define OCP_SHARED_O_APPS_WLAN_ORBIT \ + 0x00000194 + +#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \ + 0x00000198 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE1 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE2 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE3 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE4 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE5 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE6 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE7 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE8 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE9 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE10 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE11 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE12 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_IC_LOCKER_ID register. +// +//****************************************************************************** +#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \ + 0x00000007 // This register is used for + // allowing only one master OCP to + // perform write transactions to the + // OCP slaves. Each bit represents + // an IP in the following format: { + // JTAG,WLAN, NWP mcu}. As any of + // the bits is set to one, the + // correlating IP is preventing the + // other IP's from performing write + // transactions to the slaves. As + // the Inter Connect is locked, the + // only the locking IP can write to + // the register and by that + // releasing the lock. 3'b000 => IC + // is not locked. 3'b001 => IC is + // locked by NWP mcu. 3'b010 => IC + // is locked by WLAN. 3'b100 => IC + // is locked by JTAG. + +#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_MCU_SEMAPHORE_PEND register. +// +//****************************************************************************** +#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \ + 0x0000FFFF // This register specifies the + // semaphore for which the NWP mcu + // is waiting to be released. It is + // set to the serial number of a + // given locked semaphore after it + // was read by the NWP mcu. Only + // [11:0] is used. + +#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_WL_SEMAPHORE_PEND register. +// +//****************************************************************************** +#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \ + 0x0000FFFF // This register specifies the + // semaphore for which the WLAN is + // waiting to be released. It is set + // to the serial number of a given + // locked semaphore after it was + // read by the WLAN. Only [11:0] is + // used. + +#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register. +// +//****************************************************************************** +#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \ + 0x0000FFFF // This information serves the IPs + // for knowing in which platform are + // they integrated at: 0 = CC31XX. + +#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \ + 0x00000FFF // Captured/released semaphores + // status for the 12 semaphores. + // Each bit of the 12 bits + // represents a semaphore. 0 => + // Semaphore Free. 1 => Semaphore + // Captured. + +#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_CONFIG_CTRL register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \ + 0x00000010 // This bit is used to enable + // timeout mechanism for top_ocp_ic + // (for debug puropse). When 1 value + // , in case any ocp slave doesn't + // give sresponse within 16 cylcles + // top_ic will give error response + // itself to avoid bus hange. + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \ + 0x00000008 // 1 bit should be accessible only + // in devinit. This will enable 0x4 + // hack for apps processor + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \ + 0x00000004 // 1 bit, should be accessible only + // in devinit. This will enable 0x4 + // hack for nw processor + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \ + 0x00000002 // When set NW can take over apps + // rom and flash via IDCODE bus. + // Apps will able to access this + // register only during devinit and + // reset value should be 0. + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \ + 0x00000001 // When this bit is set to 0 WPSI + // host interface wil be selected, + // when this bit is set to 1 , WLAN + // host async bridge will be + // selected. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \ + 0x3FFFFFFF // This register provides memss RAM + // column configuration for column 0 + // to 9. 3 bits are allocated per + // column. This register is required + // to be configured before starting + // RAM access. Changing register + // setting while code is running + // will result into unpredictable + // memory behaviour. Register is + // supported to configured ones + // after core is booted up. 3 bit + // encoding per column is as + // follows: when 000 : WLAN, 001: + // NWP, 010: APPS, 011: PHY, 100: + // OCLA column 0 select: bit [2:0] + // :when 000 -> WLAN,001 -> NWP,010 + // -> APPS, 011 -> PHY, 100 -> OCLA + // column 1 select: bit [5:3] + // :column 2 select: bit [8 : 6]: + // column 3 select : bit [11: 9] + // column 4 select : bit [14:12] + // column 5 select : bit [17:15] + // column 6 select : bit [20:18] + // column 7 select : bit [23:21] + // column 8 select : bit [26:24] + // column 9 select : bit [29:27] + // column 10 select + +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \ + 0x00000FFF // This register provides memss RAM + // column configuration for column + // 10 to 15. 3 bits are allocated + // per column. This register is + // required to be configured before + // starting RAM access. Changing + // register setting while code is + // running will result into + // unpredictable memory behaviour. + // Register is supported to + // configured ones after core is + // booted up. 3 bit encoding per + // column is as follows: when 000 : + // WLAN, 001: NWP, 010: APPS, 011: + // PHY, 100: OCLA column 11 select : + // bit [2:0] column 12 select : bit + // [5:3] column 13 select : bit [8 : + // 6] column 14 select : + +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_WLAN_ELP_WAKE_EN register. +// +//****************************************************************************** +#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \ + 0x00000001 // when '1' : signal will enabled + // ELP power doamin when '0': ELP is + // not powered up. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register. +// +//****************************************************************************** +#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. This register is not used + // , similar register availble in + // GPRCM space. + +#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register. +// +//****************************************************************************** +#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_SEED register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_CHK register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_POLY_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \ + 0x00000003 // 2 bit, Writable only during + // devinit, and whole 2 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_0 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \ + 0xFFFFFFFF // Devinit code should look for + // whether corresponding fuse is + // blown and if blown write to the + // 11th bit of this register to + // disable flshtst interface + +#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_1 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_2 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_3 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \ + 0xFFFFFFFF // APPS Software register + +#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." "For example in + // case of I2C Value gets latched at + // rising edge of RET33.""" """ 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \ + 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." "For example in + // case of I2C Value gets latched at + // rising edge of RET33.""" """ 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \ + 0x00000080 // when '1' enable ISO A control to + // D2D Pads else ISO is disabled. + // For these PADS to be functional + // this signals should be set 0. + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \ + 0x00000040 // when '1' enable ISO Y control to + // D2D Pads else ISO is disabled. + // For these PADS to be functional + // this signals should be set 0. + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \ + 0x00000020 // If level ‘1’ enables the PAD to + // ODI path for JTAG PADS [PAD 23, + // 24, 28, 29]. Else ODI is pulled + // ‘Low’ regardless of PAD level." + // "Value gets latched at rising + // edge of RET33.""" """ + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \ + 0x00000018 // 00’: hysteriris = 10% of VDDS + // (difference between upper and + // lower threshold of the schmit + // trigger) ‘01’: hysteriris = 20% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger) ‘10’: hysteriris = 30% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger) ‘11’: hysteriris = 40% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger)" """ + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3 +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \ + 0x00000004 // If logic ‘0’ there is no + // hysteresis. Set to ‘1’ to enable + // hysteresis. Leave the choice to + // customers""" + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \ + 0x00000002 // Normal functional operation set + // this to logic ‘1’ to increase the + // speed of the o/p buffer at the + // cost of 0.2uA static current + // consumption per IO. During IDDQ + // test and during Hibernate this + // would be forced to logic ‘0’. + // Value is not latched at rising + // edge of RET33."" + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \ + 0x00000001 // If level ‘1’ enables the PAD to + // ODI path. Else ODI is pulled + // ‘Low’ regardless of PAD level." + // "Value gets latched at rising + // edge of RET33.""" """ + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \ + 0x0000003F // this register implements common + // IO control to all devement mode + // PADs; these PADs are DEV_PAD33 to + // DEV_PAD39. Bit [1:0] : Drive + // strength control. These 2 bits + // are connected to DEV PAD drive + // strength control. possible drive + // stregnths are 2MA, 4MA and 6 MA + // for the these IO's. bit 0: when + // set to logic value '1' enable 2MA + // drive strength for DEVPAD01 to 07 + // bit 1: when set to logic value + // '1' enable 4MA drive strength for + // DEVPAD01 to 07. bit[3:2] : WK + // PULL UP and PULL down control. + // These 2 bits provide IWKPUEN and + // IWKPDEN control for all DEV IO's. + // bit 2: when set to logic value + // '1' enable WKPU to DEVPAD01 to 07 + // bit 3: when set to logic value + // '1' enable WKPD to DEVPAD01 to + // 07. bit 4: WK PULL control for + // DEV_PKG_DETECT pin. when '1' + // pullup enabled else it is + // disable. bit 5: when set to logic + // value '1' enable 8MA drive + // strength for DEVPAD01 to 07. + +#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \ + 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + // this register control OEN2X pin + // of D2D TOSTACK PAD: OEN1X and + // OEN2X decoding is as follows: + // "when ""00"" :" "when ""01"" : + // dirve strength is '1' and output + // buffer enabled." "when ""10"" : + // drive strength is 2 and output + // buffer is disabled." "when ""11"" + // : dirve strength is '3' and + // output buffer enabled." + +#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_MISC_PAD_CONF register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \ + 0x00000200 // This register provide OEN2X + // control to D2D PADS OEN/OEN2X + // control. When 0 : Act as input + // buffer else output buffer with + // drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \ + 0x00000100 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \ + 0x00000080 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \ + 0x00000040 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \ + 0x00000020 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \ + 0x00000010 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \ + 0x00000008 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \ + 0x00000007 // D2D SPARE PAD OEN/OEN2X control. + // When 0: Act as input buffer else + // output buffer with drive strength + // 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SOP_CONF_OVERRIDE register. +// +//****************************************************************************** +#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \ + 0x00000001 // when '1' : signal will ovberride + // SoP setting of JTAG PADS. when + // '0': SoP setting will control + // JTAG PADs [ TDI, TDO, TMS, TCK] + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \ + 0x00000020 // This register contains debug + // subsystem status bits From APPS + // MCU status bit to indicates + // whether serial wire or 4 pins + // jtag select. + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \ + 0x00000010 // cjtag bypass bit select + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \ + 0x00000008 // serial wire interface bit select + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \ + 0x00000004 // apps tap enable status + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \ + 0x00000002 // tap enable status + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \ + 0x00000001 // ssbd unlock status + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \ + 0x0000FFFF // debug mux select register. Upper + // 8 bits are used for debug module + // selection. Lower 8 bit [7:0] used + // inside debug module for selecting + // module specific signals. + // Bits[15:8: when set x"00" : GPRCM + // debug bus. When "o1" : SDIO debug + // debug bus when x"02" : + // autonoumous SPI when x"03" : + // TOPIC when x"04": memss when + // x"25": mcu debug bus : APPS debug + // when x"45": mcu debug bus : NWP + // debug when x"65": mcu debug bus : + // AHB2VBUS debug when x"85": mcu + // debug bus : VBUS2HAB debug when + // x"95": mcu debug bus : RCM debug + // when x"A5": mcu debug bus : + // crypto debug when x"06": WLAN + // debug bus when x"07": debugss bus + // when x"08": ADC debug when x"09": + // SDIO PHY debug bus then "others" + // : no debug is selected + +#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_ALT_PC_VAL_NW register. +// +//****************************************************************************** +#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \ + 0xFFFFFFFF // 32 bit. Program counter value + // for 0x4 address when Alt_pc_en_nw + // is set. + +#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_ALT_PC_VAL_APPS register. +// +//****************************************************************************** +#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \ + 0xFFFFFFFF // 32 bit. Program counter value + // for 0x4 address when + // Alt_pc_en_apps is set + +#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_4 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \ + 0xFFFFFFFE // HW register + +#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1 +#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \ + 0x00000001 // Data to the top die launched at + // negative edge instead of positive + // edge. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_5 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \ + 0xFFFFFFFF // HW register + +#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SH_SPI_CS_MASK register. +// +//****************************************************************************** +#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \ + 0x0000000F // ( chip select 0 is unmasked + // after reset. When ‘1’ : CS is + // unmasked or else masked. Valid + // configurations are 1000, 0100, + // 0010 or 0001. Any other setting + // can lead to unpredictable + // behavior. + +#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEVICE_TYPE register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \ + 0x00000060 // reserved bits tied off "00". + +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5 +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \ + 0x0000001F // CC3XX Device type information. + +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register. +// +//****************************************************************************** +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \ + 0x000000F0 // [4] 1: switch between + // WLAN_I2C_SCL and + // TOP_GPIO_PORT4_I2C closes 0: + // switch opens [5] 1: switch + // between WLAN_I2C_SCL and + // TOP_VSENSE_PORT closes 0: switch + // opens [6] 1: switch between + // WLAN_I2C_SCL and WLAN_ANA_TP4 + // closes 0: switch opens [7] + // Reserved + +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4 +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \ + 0x0000000F // [0] 1: switch between + // WLAN_I2C_SDA and + // TOP_GPIO_PORT3_I2C closes 0: + // switch opens [1] 1: switch + // between WLAN_I2C_SDA and + // TOP_IFORCE_PORT closes 0: switch + // opens [2] 1: switch between + // WLAN_I2C_SDA and WLAN_ANA_TP3 + // closes 0: switch opens [3] + // Reserved + +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \ + 0x00000001 // when '0' indicates package type + // is development. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_AUTONMS_SPICLK_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \ + 0x00000002 // This bit is used to bypass MCPSI + // autonomous mode .if this bit is 1 + // autonomous MCSPI logic will be + // bypassed and it will act as link + // SPI + +#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \ + 0x00000001 // This bit is used in SPI + // Autonomous mode to switch clock + // from system clock to SPI clk that + // is coming from PAD. When value 1 + // PAD SPI clk is used as system + // clock in LPDS mode by SPI as well + // as autonomous wrapper logic. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEV_PADCONF register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \ + 0x0000FFFF + +#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_IDMEM_TIM_UPDATE register. +// +//****************************************************************************** +#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \ + 0xFFFFFFFF + +#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_6 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_7 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_APPS_WLAN_ORBIT register. +// +//****************************************************************************** +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \ + 0xFFFFFC00 // Spare bit + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10 +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \ + 0x00000200 // A rising edge on this bit + // indicates that the test case + // passes. This bit would be brought + // out on the pin interface during + // ORBIT. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \ + 0x00000100 // This register bit is writable by + // the FW and when set to 1 it + // indicates the start of a test + // execution. A failing edge on this + // bit indicates that the test + // execution is complete. This bit + // would be brought out on the pin + // interface during ORBIT. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \ + 0x000000FC // Implies the test case ID that + // needs to run. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2 +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \ + 0x00000002 // This bit is used to trigger the + // execution of test cases within + // the (ROM based) IP. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \ + 0x00000001 // When this bit is 1 it implies + // ORBIT mode of operation and the + // (ROM based) IP start the + // execution from a test case + // perspective + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register. +// +//****************************************************************************** +#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \ + 0xFFFFFFFF // scratch pad register. + +#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0 + + + +#endif // __HW_OCP_SHARED_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_shamd5.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_shamd5.h new file mode 100644 index 0000000000..cf6254f5d2 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_shamd5.h @@ -0,0 +1,1242 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_SHAMD5_H__ +#define __HW_SHAMD5_H__ + +//***************************************************************************** +// +// The following are defines for the SHAMD5_P register offsets. +// +//***************************************************************************** +#define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for + // MD5 [159:128] for SHA-1 [255:224] + // for SHA-2 / HMAC Key [31:0] for + // HMAC key proc READ: Outer Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 +#define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for + // MD5 [127:96] for SHA-1 [223:192] + // for SHA-2 / HMAC Key [63:32] for + // HMAC key proc READ: Outer Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 +#define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for + // MD5 [95:64] for SHA-1 [191:160] + // for SHA-2 / HMAC Key [95:64] for + // HMAC key proc READ: Outer Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA-2 +#define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for + // MD5 [63:31] for SHA-1 [159:128] + // for SHA-2 / HMAC Key [127:96] for + // HMAC key proc READ: Outer Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 +#define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for + // SHA-1 [127:96] for SHA-2 / HMAC + // Key [159:128] for HMAC key proc + // READ: Outer Digest [31:0] for + // SHA-1 [127:96] for SHA-2 +#define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for + // SHA-2 / HMAC Key [191:160] for + // HMAC key proc READ: Outer Digest + // [95:64] for SHA-2 +#define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for + // SHA-2 / HMAC Key [223:192] for + // HMAC key proc READ: Outer Digest + // [63:32] for SHA-2 +#define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for + // SHA-2 / HMAC Key [255:224] for + // HMAC key proc READ: Outer Digest + // [31:0] for SHA-2 +#define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 / HMAC + // Key [287:256] for HMAC key proc + // READ: Intermediate / Inner Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 / + // Result Digest/MAC [127:96] for + // MD5 [159:128] for SHA-1 [223:192] + // for SHA-2 224 [255:224] for SHA-2 + // 256 +#define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 / HMAC + // Key [319:288] for HMAC key proc + // READ: Intermediate / Inner Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 / + // Result Digest/MAC [95:64] for MD5 + // [127:96] for SHA-1 [191:160] for + // SHA-2 224 [223:192] for SHA-2 256 +#define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA- 2 / HMAC Key + // [351:320] for HMAC key proc READ: + // Intermediate / Inner Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA-2 / Result + // Digest/MAC [63:32] for MD5 + // [95:64] for SHA-1 [159:128] for + // SHA-2 224 [191:160] for SHA-2 256 +#define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 / HMAC Key + // [383:352] for HMAC key proc READ: + // Intermediate / Inner Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 / Result + // Digest/MAC [31:0] for MD5 [63:32] + // for SHA-1 [127:96] for SHA-2 224 + // [159:128] for SHA-2 256 +#define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest + // [31:0] for SHA-1 [127:96] for + // SHA-2 / HMAC Key [415:384] for + // HMAC key proc READ: Intermediate + // / Inner Digest [31:0] for SHA-1 + // [127:96] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-1 + // [95:64] for SHA-2 224 [127:96] + // for SHA-2 256 +#define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest + // [95:64] for SHA-2 / HMAC Key + // [447:416] for HMAC key proc READ: + // Intermediate / Inner Digest + // [95:64] for SHA-2 / Result + // Digest/MAC [63:32] for SHA-2 224 + // [95:64] for SHA-2 256 +#define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest + // [63:32] for SHA-2 / HMAC Key + // [479:448] for HMAC key proc READ: + // Intermediate / Inner Digest + // [63:32] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-2 224 + // [63:32] for SHA-2 256 +#define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest + // [31:0] for SHA-2 / HMAC Key + // [511:480] for HMAC key proc READ: + // Intermediate / Inner Digest + // [31:0] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-2 256 +#define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count + // ([31:6] only [5:0] assumed 0) + // READ: Result / IntermediateDigest + // Count The initial digest byte + // count for hash/HMAC continue + // operations (HMAC Key Processing = + // 0 and Use Algorithm Constants = + // 0) on the Secure World must be + // written to this register prior to + // starting the operation by writing + // to S_HASH_MODE. When either HMAC + // Key Processing is 1 or Use + // Algorithm Constants is 1 this + // register does not need to be + // written it will be overwritten + // with 64 (1 hash block of key XOR + // ipad) or 0 respectively + // automatically. When starting a + // HMAC operation from pre-computes + // (HMAC Key Processing is 0) then + // the value 64 must be written here + // to compensate for the appended + // key XOR ipad block. Note that the + // value written should always be a + // 64 byte multiple the lower 6 bits + // written are ignored. The updated + // digest byte count (initial digest + // byte count + bytes processed) can + // be read from this register when + // the status register indicates + // that the operation is done or + // suspended due to a context switch + // request or when a Secure World + // context out DMA is requested. In + // Advanced DMA mode when not + // suspended with a partial result + // reading the SHAMD5_DIGEST_COUNT + // register triggers the Hash/HMAC + // Engine to start the next context + // input DMA. Therefore reading the + // SHAMD5_DIGEST_COUNT register + // should always be the last + // context-read action if not + // suspended with a partial result + // (i.e. PartHashReady interrupt not + // pending). +#define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE +#define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining + // Byte Count (bytes) READ: + // Remaining Byte Count. The value + // programmed MUST be a 64-byte + // multiple if Close Hash is set to + // 0. This register is also the + // trigger to start processing: once + // this register is written the core + // will commence requesting input + // data via DMA or IRQ (if + // programmed length > 0) and start + // processing. The remaining byte + // count for the active operation + // can be read from this register + // when the interrupt status + // register indicates that the + // operation is suspended due to a + // context switch request. +#define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0 +#define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1 +#define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2 +#define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3 +#define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4 +#define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5 +#define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6 +#define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7 +#define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8 +#define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9 +#define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10 +#define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11 +#define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12 +#define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13 +#define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14 +#define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15 +#define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV +#define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG +#define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS +#define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS +#define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The + // SHAMD5_IRQENABLE register contains + // an enable bit for each unique + // interrupt for the public side. An + // interrupt is enabled when both + // the global enable in + // SHAMD5_SYSCONFIG (PIT_en) and the + // bit in this register are both set + // to 1. An interrupt that is + // enabled is propagated to the + // SINTREQUEST_P output. Please note + // that the dedicated partial hash + // output (SINTREQUEST_PART_P) is + // not affected by this register it + // is only affected by the global + // enable SHAMD5_SYSCONFIG (PIT_en). +#define SHAMD5_O_HASH512_ODIGEST_A \ + 0x00000200 + +#define SHAMD5_O_HASH512_ODIGEST_B \ + 0x00000204 + +#define SHAMD5_O_HASH512_ODIGEST_C \ + 0x00000208 + +#define SHAMD5_O_HASH512_ODIGEST_D \ + 0x0000020C + +#define SHAMD5_O_HASH512_ODIGEST_E \ + 0x00000210 + +#define SHAMD5_O_HASH512_ODIGEST_F \ + 0x00000214 + +#define SHAMD5_O_HASH512_ODIGEST_G \ + 0x00000218 + +#define SHAMD5_O_HASH512_ODIGEST_H \ + 0x0000021C + +#define SHAMD5_O_HASH512_ODIGEST_I \ + 0x00000220 + +#define SHAMD5_O_HASH512_ODIGEST_J \ + 0x00000224 + +#define SHAMD5_O_HASH512_ODIGEST_K \ + 0x00000228 + +#define SHAMD5_O_HASH512_ODIGEST_L \ + 0x0000022C + +#define SHAMD5_O_HASH512_ODIGEST_M \ + 0x00000230 + +#define SHAMD5_O_HASH512_ODIGEST_N \ + 0x00000234 + +#define SHAMD5_O_HASH512_ODIGEST_O \ + 0x00000238 + +#define SHAMD5_O_HASH512_ODIGEST_P \ + 0x0000023C + +#define SHAMD5_O_HASH512_IDIGEST_A \ + 0x00000240 + +#define SHAMD5_O_HASH512_IDIGEST_B \ + 0x00000244 + +#define SHAMD5_O_HASH512_IDIGEST_C \ + 0x00000248 + +#define SHAMD5_O_HASH512_IDIGEST_D \ + 0x0000024C + +#define SHAMD5_O_HASH512_IDIGEST_E \ + 0x00000250 + +#define SHAMD5_O_HASH512_IDIGEST_F \ + 0x00000254 + +#define SHAMD5_O_HASH512_IDIGEST_G \ + 0x00000258 + +#define SHAMD5_O_HASH512_IDIGEST_H \ + 0x0000025C + +#define SHAMD5_O_HASH512_IDIGEST_I \ + 0x00000260 + +#define SHAMD5_O_HASH512_IDIGEST_J \ + 0x00000264 + +#define SHAMD5_O_HASH512_IDIGEST_K \ + 0x00000268 + +#define SHAMD5_O_HASH512_IDIGEST_L \ + 0x0000026C + +#define SHAMD5_O_HASH512_IDIGEST_M \ + 0x00000270 + +#define SHAMD5_O_HASH512_IDIGEST_N \ + 0x00000274 + +#define SHAMD5_O_HASH512_IDIGEST_O \ + 0x00000278 + +#define SHAMD5_O_HASH512_IDIGEST_P \ + 0x0000027C + +#define SHAMD5_O_HASH512_DIGEST_COUNT \ + 0x00000280 + +#define SHAMD5_O_HASH512_MODE 0x00000284 +#define SHAMD5_O_HASH512_LENGTH 0x00000288 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_DIGEST_COUNT register. +// +//****************************************************************************** +#define SHAMD5_DIGEST_COUNT_DATA_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DIGEST_COUNT_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_MODE register. +// +//****************************************************************************** +#define SHAMD5_MODE_HMAC_OUTER_HASH \ + 0x00000080 // The HMAC Outer Hash is performed + // on the hash digest when the inner + // hash hash finished (block length + // exhausted and final hash + // performed if close_hash is 1). + // This bit should normally be set + // together with close_hash to + // finish the inner hash first or + // Block Length should be zero (HMAC + // continue with the just outer hash + // to be done). Auto cleared + // internally when outer hash + // performed. 0 No operation 1 hmac + // processing + +#define SHAMD5_MODE_HMAC_KEY_PROC \ + 0x00000020 // Performs HMAC key processing on + // the 512 bit HMAC key loaded into + // the SHAMD5_IDIGEST_{A to H} and + // SHAMD5_ODIGEST_{A to H} register + // block. Once HMAC key processing + // is finished this bit is + // automatically cleared and the + // resulting Inner and Outer digest + // is available from + // SHAMD5_IDIGEST_{A to H} and + // SHAMD5_ODIGEST_{A to H} + // respectively after which regular + // hash processing (using + // SHAMD5_IDIGEST_{A to H} as initial + // digest) will commence until the + // Block Length is exhausted. 0 No + // operation. 1 Hmac processing. + +#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the + // hash/HMAC will be 'closed' at the + // end of the block as per + // MD5/SHA-1/SHA-2 specification + // (i.e. appropriate padding is + // added) or no padding is done + // allowing the hash to be continued + // later. However if the hash/HMAC + // is not closed then the Block + // Length MUST be a multiple of 64 + // bytes to ensure correct + // operation. Auto cleared + // internally when hash closed. 0 No + // padding hash computation can be + // contimued. 1 Last packet will be + // padded. +#define SHAMD5_MODE_ALGO_CONSTANT \ + 0x00000008 // The initial digest register will + // be overwritten with the algorithm + // constants for the selected + // algorithm when hashing and the + // initial digest count register + // will be reset to 0. This will + // start a normal hash operation. + // When continuing an existing hash + // or when performing an HMAC + // operation this register must be + // set to 0 and the + // intermediate/inner digest or HMAC + // key and digest count need to be + // written to the context input + // registers prior to writing + // SHAMD5_MODE. Auto cleared + // internally after first block + // processed. 0 Use pre-calculated + // digest (from an other operation) + // 1 Use constants of the selected + // algo. + +#define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash + // algorithm to be used for + // processing: 0x0 md5_128 algorithm + // 0x1 sha1_160 algorithm 0x2 + // sha2_224 algorithm 0x3 sha2_256 + // algorithm +#define SHAMD5_MODE_ALGO_S 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_LENGTH register. +// +//****************************************************************************** +#define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data +#define SHAMD5_LENGTH_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA0_IN_DATA0_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA0_IN_DATA0_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA1_IN_DATA1_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA1_IN_DATA1_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA2_IN_DATA2_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA2_IN_DATA2_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA3_IN_DATA3_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA3_IN_DATA3_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA4_IN_DATA4_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA4_IN_DATA4_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA5_IN_DATA5_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA5_IN_DATA5_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA6_IN_DATA6_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA6_IN_DATA6_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA7_IN_DATA7_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA7_IN_DATA7_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA8_IN_DATA8_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA8_IN_DATA8_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA9_IN_DATA9_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA9_IN_DATA9_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA10_IN_DATA10_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA10_IN_DATA10_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA11_IN_DATA11_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA11_IN_DATA11_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA12_IN_DATA12_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA12_IN_DATA12_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA13_IN_DATA13_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA13_IN_DATA13_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA14_IN_DATA14_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA14_IN_DATA14_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA15_IN_DATA15_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA15_IN_DATA15_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_REVISION register. +// +//****************************************************************************** +#define SHAMD5_REVISION_SCHEME_M 0xC0000000 +#define SHAMD5_REVISION_SCHEME_S 30 +#define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define SHAMD5_REVISION_FUNC_S 16 +#define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define SHAMD5_REVISION_R_RTL_S 11 +#define SHAMD5_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. + +#define SHAMD5_REVISION_X_MAJOR_S 8 +#define SHAMD5_REVISION_CUSTOM_M 0x000000C0 +#define SHAMD5_REVISION_CUSTOM_S 6 +#define SHAMD5_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. + +#define SHAMD5_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register. +// +//****************************************************************************** +#define SHAMD5_SYSCONFIG_PADVANCED \ + 0x00000080 // If set to 1 Advanced mode is + // enabled for the Secure World. If + // set to 0 Legacy mode is enabled + // for the Secure World. + +#define SHAMD5_SYSCONFIG_PCONT_SWT \ + 0x00000040 // Finish all pending data and + // context DMA input requests (but + // will not assert any new requests) + // finish processing all data in the + // module and provide a saved + // context (partial hash result + // updated digest count remaining + // length updated mode information + // where applicable) for the last + // operation that was interrupted so + // that it can be resumed later. + +#define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008 +#define SHAMD5_SYSCONFIG_PIT_EN 0x00000004 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register. +// +//****************************************************************************** +#define SHAMD5_SYSSTATUS_RESETDONE \ + 0x00000001 // data + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register. +// +//****************************************************************************** +#define SHAMD5_IRQSTATUS_CONTEXT_READY \ + 0x00000008 // indicates that the secure side + // context input registers are + // available for a new context for + // the next packet to be processed. + +#define SHAMD5_IRQSTATUS_PARTHASH_READY \ + 0x00000004 // After a secure side context + // switch request this bit will read + // as 1 indicating that the saved + // context is available from the + // secure side context output + // registers. Note that if the + // context switch request coincides + // with a final hash (when hashing) + // or an outer hash (when doing + // HMAC) that PartHashReady will not + // become active but a regular + // Output Ready will occur instead + // (indicating that the result is + // final and therefore no + // continuation is required). + +#define SHAMD5_IRQSTATUS_INPUT_READY \ + 0x00000002 // indicates that the secure side + // data FIFO is ready to receive the + // next 64 byte data block. + +#define SHAMD5_IRQSTATUS_OUTPUT_READY \ + 0x00000001 // Indicates that a (partial) + // result or saved context is + // available from the secure side + // context output registers. + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register. +// +//****************************************************************************** +#define SHAMD5_IRQENABLE_M_CONTEXT_READY \ + 0x00000008 // mask for context ready + +#define SHAMD5_IRQENABLE_M_PARTHASH_READY \ + 0x00000004 // mask for partial hash + +#define SHAMD5_IRQENABLE_M_INPUT_READY \ + 0x00000002 // mask for input_ready + +#define SHAMD5_IRQENABLE_M_OUTPUT_READY \ + 0x00000001 // mask for output_ready + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_A_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_B_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_C_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_D_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_E_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_F_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_G_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_H_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_I register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_I_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_I_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_J register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_J_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_J_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_K register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_K_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_K_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_L register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_L_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_L_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_M register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_M_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_M_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_N register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_N_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_N_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_O register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_O_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_O_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_P register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_A_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_B_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_C_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_D_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_E_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_F_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_G_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_H_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_I register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_I_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_I_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_J register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_J_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_J_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_K register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_K_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_K_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_L register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_L_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_L_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_M register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_M_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_M_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_N register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_N_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_N_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_O register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_O_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_O_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_P register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_DIGEST_COUNT register. +// +//****************************************************************************** +#define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_MODE register. +// +//****************************************************************************** +#define SHAMD5_HASH512_MODE_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_MODE_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_LENGTH register. +// +//****************************************************************************** +#define SHAMD5_HASH512_LENGTH_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_LENGTH_DATA_S 0 + + + +#endif // __HW_SHAMD5_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_stack_die_ctrl.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_stack_die_ctrl.h new file mode 100644 index 0000000000..eba31e4f07 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_stack_die_ctrl.h @@ -0,0 +1,764 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + + +#ifndef __HW_STACK_DIE_CTRL_H__ +#define __HW_STACK_DIE_CTRL_H__ + +//***************************************************************************** +// +// The following are defines for the STACK_DIE_CTRL register offsets. +// +//***************************************************************************** +#define STACK_DIE_CTRL_O_STK_UP_RESET \ + 0x00000000 // Can be written only by Base + // Processor. Writing to this + // register will reset the stack + // processor reset will be + // de-asserted upon clearing this + // register. + +#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \ + 0x00000004 // This register defines who among + // base processor and stack + // processor have highest priority + // for Sram Access. Can be written + // only by Base Processor. + +#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \ + 0x00000008 // In Spinlock mode this Register + // defines who among base processor + // and stack processor have access + // to Sram Bank2 right now. In + // Handshake mode this Register + // defines who among base processor + // and stack processor have access + // to Sram Bank2 and Bank3 right + // now. Its Clear only register and + // is set by hardware. Lower bit can + // be cleared only by Base Processor + // and Upper bit Cleared only by the + // Stack processor. + +#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \ + 0x0000000C // In Spinlock mode whenever Base + // processor wants the access to + // Sram Bank2 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by Stack + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \ + 0x00000010 // In Spinlock mode Whenever Stack + // processor wants the access to + // Sram Bank2 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by the Base + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \ + 0x00000014 // Register defines who among base + // processor and stack processor + // have access to Sram Bank3 right + // now. Its Clear only register and + // is set by hardware. Lower bit can + // be cleared only by Base Processor + // and Upper bit Cleared only by the + // Stack processor. + +#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \ + 0x00000018 // In Spinlock mode whenever Base + // processor wants the access to + // Sram Bank3 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by Stack + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \ + 0x0000001C // In Spinlock mode Whenever Stack + // processor wants the access to + // Sram Bank3 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by the Base + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \ + 0x00000020 // Read State Machine timing + // configuration register. Generally + // Bit 4 and 3 will be identical. + // For stacked die always 43 are 0 + // and 6:5 == 1 for 120Mhz. + +#define STACK_DIE_CTRL_O_RDSM_CFG_EE \ + 0x00000024 // Read State Machine timing + // configuration register. Generally + // Bit 4 and 3 will be identical. + // For stacked die always 43 are 0 + // and 6:5 == 1 for 120Mhz. + +#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \ + 0x00000028 // Reading this register Base + // procesor will able to know the + // reason for the interrupt. This is + // clear only register - set by HW + // upon an interrupt to Base + // processor and can be cleared only + // by BASE processor. + +#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \ + 0x0000002C // Reading this register Stack + // procesor will able to know the + // reason for the interrupt. This is + // clear only register - set by HW + // upon an interrupt to Stack + // processor and can be cleared only + // by Stack processor. + +#define STACK_DIE_CTRL_O_STK_CLK_EN \ + 0x00000030 // Can be written only by base + // processor. Controls the enable + // pin of the cgcs for the clocks + // going to CM3 dft ctrl block and + // Sram. + +#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \ + 0x00000034 // Can be written only by the base + // processor. Decides the ram + // sharing mode :: handshake or + // Spinlock mode. + +#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \ + 0x00000038 // Stores the last bus fault + // address. + +#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \ + 0x0000003C // write only registers on read + // returns 0.W Write 1 to clear the + // bust fault to store the new bus + // fault address + +#define STACK_DIE_CTRL_O_RESET_CAUSE \ + 0x00000040 // Reset cause value captured from + // the ICR_CLKRST block. + +#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \ + 0x00000044 // Watchdog timer event value + // captured from the ICR_CLKRST + // block + +#define STACK_DIE_CTRL_O_DMA_REQ \ + 0x00000048 // To send Dma Request to bottom + // die. + +#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \ + 0x0000004C // Address offset within SRAM to + // which CM3 should jump after + // reset. + +#define STACK_DIE_CTRL_O_SW_REG1 \ + 0x00000050 // These are sw registers for + // topdie processor and bottom die + // processor to communicate. Both + // can set and read these registers. + // In case of write clash bottom + // die's processor wins and top die + // processor access is ignored. + +#define STACK_DIE_CTRL_O_SW_REG2 \ + 0x00000054 // These are sw registers for + // topdie processor and bottom die + // processor to communicate. Both + // can set and read these registers. + // In case of write clash bottom + // die's processor wins and top die + // processor access is ignored. + +#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \ + 0x00000058 // By posting the request Flash can + // be put into low-power mode + // (Sleep) without powering down the + // Flash. Earlier (in Garnet) this + // was fully h/w controlled and the + // control for this was coming from + // SysCtl while entering into Cortex + // Deep-sleep mode. But for our + // device the D2D i/f doesnt support + // this. The Firmware has to program + // the register in the top-die for + // entering into this mode and wait + // for an interrupt. + +#define STACK_DIE_CTRL_O_MISC_CTL \ + 0x0000005C // Miscellanious control register. + +#define STACK_DIE_CTRL_O_SW_DFT_CTL \ + 0x000000FC // DFT control and status bits + +#define STACK_DIE_CTRL_O_PADN_CTL_0 \ + 0x00000100 // Mainly for For controlling the + // pads OEN pins. There are total 60 + // pads and hence 60 control registe + // i.e n value varies from 0 to 59. + // Here is the mapping for the + // pad_ctl register number and the + // functionality : 0 D2DPAD_DMAREQ1 + // 1 D2DPAD_DMAREQ0 2 + // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 + // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 + // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 + // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS + // 10 D2DPAD_JTAG_TDI 11-27 + // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE + // -1:0] 28-56 D2DPAD_TOSTACK + // [D2D_TOSTACK_SIZE -1:0] 57-59 + // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE + // -1:0] 0:00 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_RESET register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \ + 0x00000001 // 1 :Assert Reset 0 : Deassert the + // Reset + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \ + 0x00000003 // 00 : Equal Priority 01 : Stack + // Processor have priority 10 : Base + // Processor have priority 11 : + // Unused + +#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \ + 0x00000002 // Stack Processor should clear it + // when it is done with the sram + // bank usage. Set by HW It is set + // when Stack Processor is granted + // the access to this bank + +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \ + 0x00000001 // Base Processor should clear it + // when it is done wth the sram + // usage. Set by HW It is set when + // Base Processor is granted the + // access to this bank + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \ + 0x00000001 // Base Processor will set when + // Sram access is needed in Spin + // Lock mode. In Handshake mode + // Stack Processor will set to + // inform Base Processor that it is + // done with the processing of data + // in SRAM and is now ready to use + // by the base processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \ + 0x00000001 // Stack Processor will set when + // Sram access is needed in Spin + // Lock mode. In Handshake mode Base + // Processor will set to inform + // Stack Processor to start + // processing the data in the Ram. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \ + 0x00000002 // Stack Processor should clear it + // when it is done with the sram + // bank usage. Set by HW It is set + // when Stack Processor is granted + // the access to this bank. + +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \ + 0x00000001 // Base Processor should clear it + // when it is done wth the sram + // usage. Set by HW it is set when + // Base Processor is granted the + // access to this bank. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \ + 0x00000001 // Base Processor will set when + // Sram access is needed in Spin + // Lock mode. Not used in handshake + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \ + 0x00000001 // Stack Processor will set when + // Sram access is needed in Spin + // Lock mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RDSM_CFG_CPU register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \ + 0x000000C0 // Bank Clock Hi Time 00 : HCLK + // pulse 01 : 1 cycle of HCLK 10 : + // 1.5 cycles of HCLK 11 : 2 cycles + // of HCLK + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6 +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \ + 0x00000020 // FLCLK 0 : indicates flash clock + // rise aligns on HCLK rise 1 : + // indicates flash clock rise aligns + // on HCLK fall + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \ + 0x00000010 // 0 : Always register flash rdata + // before sending to CPU 1 : Drive + // Flash rdata directly out on MISS + // (Both ICODE / DCODE) + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \ + 0x0000000F // Number of wait states inserted + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RDSM_CFG_EE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \ + 0x000000C0 // Bank Clock Hi Time 00 : HCLK + // pulse 01 : 1 cycle of HCLK 10 : + // 1.5 cycles of HCLK 11 : 2 cycles + // of HCLK + +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6 +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \ + 0x00000020 // FLCLK 0 : indicates flash clock + // rise aligns on HCLK rise 1 : + // indicates flash clock rise aligns + // on HCLK fall + +#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \ + 0x00000010 // 0 : Always register flash rdata + // before sending to CPU 1 : Drive + // Flash rdata directly out on MISS + // (Both ICODE / DCODE) + +#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \ + 0x0000000F // Number of wait states inserted + +#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \ + 0x00000010 // Set when Relinquish Interrupt + // sent to Base processor for Bank3. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \ + 0x00000008 // Set when Relinquish Interrupt + // sent to Base processor for Bank2. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \ + 0x00000004 // Set when Bank3 is granted to + // Base processor. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \ + 0x00000002 // Set when Bank2 is granted to + // BAse processor. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \ + 0x00000001 // Set when there Base processor do + // an Invalid access to Sram. Ex : + // Accessing the bank which is not + // granted for BAse processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \ + 0x00000008 // Set when Relinquish Interrupt + // sent to Stack processor for + // Bank3. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \ + 0x00000004 // Set when Relinquish Interrupt + // sent to Stack processor for + // Bank2. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \ + 0x00000002 // Set when Bank3 is granted to + // Stack processor. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \ + 0x00000001 // Set when Bank2 is granted to + // Stack processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_CLK_EN register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \ + 0x00000004 // Enable the clock going to sram. + +#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \ + 0x00000002 // Enable the clock going to dft + // control block + +#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \ + 0x00000001 // Enable the clock going to Cm3 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \ + 0x00000001 // 0 : Handshake Mode 1 : Spinlock + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \ + 0xFFFFFFFF // Fault Address + +#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BUS_FAULT_CLR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \ + 0x00000001 // When set it'll clear the bust + // fault address register to store + // the new bus fault address + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RESET_CAUSE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_DMA_REQ register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \ + 0x00000002 // Generate DMAREQ1 on setting this + // bit. + +#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \ + 0x00000001 // Generate DMAREQ0 on setting this + // bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_REG1 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_REG2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \ + 0x00000002 // captures the status of of + // fmc_lpm_ack + +#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \ + 0x00000001 // When set assert + // iflpe2fmc_lpm_req to FMC. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_MISC_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \ + 0x00000080 // 1 : will reset the async wdog + // timer runing on piosc clock + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \ + 0x00000020 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \ + 0x00000010 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \ + 0x00000008 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \ + 0x00000004 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 3 goes to Bank3 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank2 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \ + 0x00000002 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 2 goes to Bank2 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank2 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \ + 0x00000001 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 1 goes to Bank1 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_DFT_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \ + 0x20000000 // when set to '1' all flash + // control signals switch over to + // CM3 control when '0' it is under + // the D2D interface control + +#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \ + 0x10000000 // 1 indicates in SWIF mode the + // control signals to flash are from + // FMC CPU read controls the clock + // and address. that is one can give + // address via FMC and read through + // IDMEM. + +#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \ + 0x00800000 // 'CPU Done' bit for PBIST. Write + // '1' to indicate test done. + +#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \ + 0x00400000 // 'CPU Fail' bit for PBIST. Write + // '1' to indicate test failed. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \ + 0x00001000 // when set to '1' flash bank 4 + // (EEPROM) is owned by the CM3for + // reads over DCODE bus. When '0' + // access control given to D2D + // interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \ + 0x00000800 // when set to '1' flash bank 3 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \ + 0x00000400 // when set to '1' flash bank 2 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \ + 0x00000200 // when set to '1' flash bank 1 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \ + 0x00000100 // when set to '1' flash bank 0 is + // owned by the CM3 for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_PADN_CTL_0 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \ + 0x00000008 // This bit is valid for only the + // spare pads ie for n=57 to 59. + // value to drive at the output of + // the pad + +#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \ + 0x00000004 // This bit is valid for only the + // spare pads ie for n=57 to 59. + // captures the 'Y' pin of the pad + // which is the data being driven + // into the die + +#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \ + 0x00000002 // OEN2X control when '1' enables + // the output with 1x. Total drive + // strength is decided bu oen1x + // setting + oen2x setting. + +#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \ + 0x00000001 // OEN1X control when '1' enables + // the output with 1x . Total drive + // strength is decided bu oen1x + // setting + oen2x setting. + + + + +#endif // __HW_STACK_DIE_CTRL_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_timer.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_timer.h new file mode 100644 index 0000000000..b6844ec675 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_timer.h @@ -0,0 +1,778 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +//***************************************************************************** + +//##### INTERNAL BEGIN ##### +// +// This is an auto-generated file. Do not edit by hand. +// Created by version 6779 of DriverLib. +// +//##### INTERNAL END ##### + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the Timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // GPTM Configuration +#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode +#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode +#define TIMER_O_CTL 0x0000000C // GPTM Control +//##### GARNET BEGIN ##### +#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize +//##### GARNET END ##### +#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask +#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status +#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status +#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear +#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load +#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load +#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match +#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match +#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale +#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale +#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match +#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match +#define TIMER_O_TAR 0x00000048 // GPTM Timer A +#define TIMER_O_TBR 0x0000004C // GPTM Timer B +#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value +#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value +#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide +#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot +#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot +#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value +#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value +#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event +#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties + + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) + // counter configuration +#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The + // function is controlled by bits + // 1:0 of GPTMTAMR and GPTMTBMR + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +//##### GARNET END ##### +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +//##### GARNET END ##### +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable +//##### GARNET BEGIN ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11 +#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of + // GPTM11 is triggered +#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of + // GPTM11 is triggered +#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM11 is + // triggered +#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10 +#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of + // GPTM10 is triggered +#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of + // GPTM10 is triggered +#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM10 is + // triggered +#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9 +#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of + // GPTM9 is triggered +#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of + // GPTM9 is triggered +#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM9 is + // triggered +#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8 +#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of + // GPTM8 is triggered +#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of + // GPTM8 is triggered +#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM8 is + // triggered +#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7 +#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of + // GPTM7 is triggered +#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of + // GPTM7 is triggered +#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM7 is + // triggered +#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6 +#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of + // GPTM6 is triggered +#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of + // GPTM6 is triggered +#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM6 is + // triggered +#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Mask +//##### GARNET END ##### +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match + // Interrupt Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt + // Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt + // Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match + // Interrupt Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt + // Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt + // Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Raw Interrupt Status +//##### GARNET END ##### +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw + // Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw + // Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw + // Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw + // Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw + // Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw + // Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Masked Interrupt Status +//##### GARNET END ##### +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked + // Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked + // Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked + // Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked + // Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Clear +//##### GARNET END ##### +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match + // Interrupt Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt + // Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt + // Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match + // Interrupt Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt + // Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt + // Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +//##### GARNET END ##### +#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load + // Register High +#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load + // Register Low +#define TIMER_TAILR_TAILRH_S 16 +#define TIMER_TAILR_TAILRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAILR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +//##### GARNET END ##### +#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_TBILRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBILR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +//##### GARNET END ##### +#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High +#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low +#define TIMER_TAMATCHR_TAMRH_S 16 +#define TIMER_TAMATCHR_TAMRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAMATCHR_TAMR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +//##### GARNET END ##### +#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low +//##### GARNET BEGIN ##### +#define TIMER_TBMATCHR_TBMR_S 0 +//##### GARNET END ##### +#define TIMER_TBMATCHR_TBMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +//##### GARNET END ##### +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +//##### GARNET BEGIN ##### +#define TIMER_TAPR_TAPSRH_S 8 +//##### GARNET END ##### +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +//##### GARNET END ##### +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +//##### GARNET BEGIN ##### +#define TIMER_TBPR_TBPSRH_S 8 +//##### GARNET END ##### +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +//##### GARNET END ##### +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +//##### GARNET BEGIN ##### +#define TIMER_TAPMR_TAPSMRH_S 8 +//##### GARNET END ##### +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +//##### GARNET END ##### +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +//##### GARNET BEGIN ##### +#define TIMER_TBPMR_TBPSMRH_S 8 +//##### GARNET END ##### +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +//##### GARNET END ##### +#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High +#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAR_TARH_S 16 +#define TIMER_TAR_TARL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +//##### GARNET END ##### +#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B +#define TIMER_TBR_TBRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +//##### GARNET END ##### +#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High +#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAV_TAVH_S 16 +#define TIMER_TAV_TAVL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAV_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +//##### GARNET END ##### +#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register +#define TIMER_TBV_TBVL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start +#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are + // 32 bits each with an 16-bit + // prescale counter +//##### GARNET END ##### + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CFG +// register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CTL +// register. +// +//***************************************************************************** +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_RIS +// register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAILR +// register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBILR +// register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAR +// register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBR +// register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the timer +// registers. +// +//***************************************************************************** +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnMR +// register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPR +// register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPMR +// register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +#endif + +#endif // __HW_TIMER_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_types.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_types.h new file mode 100644 index 0000000000..d7a6ab4fed --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_types.h @@ -0,0 +1,76 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif // __HW_TYPES_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_uart.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_uart.h new file mode 100644 index 0000000000..ae50ac381f --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_uart.h @@ -0,0 +1,417 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 +#define UART_O_RSR 0x00000004 +#define UART_O_ECR 0x00000004 +#define UART_O_FR 0x00000018 +#define UART_O_ILPR 0x00000020 +#define UART_O_IBRD 0x00000024 +#define UART_O_FBRD 0x00000028 +#define UART_O_LCRH 0x0000002C +#define UART_O_CTL 0x00000030 +#define UART_O_IFLS 0x00000034 +#define UART_O_IM 0x00000038 +#define UART_O_RIS 0x0000003C +#define UART_O_MIS 0x00000040 +#define UART_O_ICR 0x00000044 +#define UART_O_DMACTL 0x00000048 +#define UART_O_LCTL 0x00000090 +#define UART_O_LSS 0x00000094 +#define UART_O_LTIM 0x00000098 +#define UART_O_9BITADDR 0x000000A4 +#define UART_O_9BITAMASK 0x000000A8 +#define UART_O_PP 0x00000FC0 +#define UART_O_CC 0x00000FC8 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//****************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//****************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//****************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//****************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect +#define UART_FR_DSR 0x00000002 // Data Set Ready +#define UART_FR_CTS 0x00000001 // Clear To Send +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//****************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//****************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//****************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//****************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 : + // UART_LCRH_WLEN_5 : 5 bits + // (default) 0x00000020 : + // UART_LCRH_WLEN_6 : 6 bits + // 0x00000040 : UART_LCRH_WLEN_7 : 7 + // bits 0x00000060 : + // UART_LCRH_WLEN_8 : 8 bits +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//****************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RI 0x00002000 // Ring Indicator +#define UART_CTL_DCD 0x00001000 // Data Carrier Detect +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_LIN 0x00000040 // LIN Mode Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//****************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX_S 3 +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//****************************************************************************** +#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask +#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask +#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask +#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask +#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt + // Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt + // Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//****************************************************************************** +#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt + // Status +#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status +#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt + // Status +#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt + // Status +#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw + // Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw + // Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem + // Raw Interrupt Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//****************************************************************************** +#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt + // Status +#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt + // Status +#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt + // Status +#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt + // Status +#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked + // Interrupt Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked + // Interrupt Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem + // Masked Interrupt Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//****************************************************************************** +#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear +#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear +#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt + // Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//****************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCTL register. +// +//****************************************************************************** +#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 : + // UART_LCTL_BLEN_13T : Sync break + // length is 13T bits (default) + // 0x00000010 : UART_LCTL_BLEN_14T : + // Sync break length is 14T bits + // 0x00000020 : UART_LCTL_BLEN_15T : + // Sync break length is 15T bits + // 0x00000030 : UART_LCTL_BLEN_16T : + // Sync break length is 16T bits +#define UART_LCTL_BLEN_S 4 +#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LSS register. +// +//****************************************************************************** +#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot +#define UART_LSS_TSS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LTIM register. +// +//****************************************************************************** +#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value +#define UART_LTIM_TIMER_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UART_O_9BITADDR register. +// +//****************************************************************************** +#define UART_9BITADDR_9BITEN \ + 0x00008000 // Enable 9-Bit Mode + +#define UART_9BITADDR_ADDR_M \ + 0x000000FF // Self Address for 9-Bit Mode + +#define UART_9BITADDR_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UART_O_9BITAMASK register. +// +//****************************************************************************** +#define UART_9BITAMASK_RANGE_M \ + 0x0000FF00 // Self Address Range for 9-Bit + // Mode + +#define UART_9BITAMASK_RANGE_S 8 +#define UART_9BITAMASK_MASK_M \ + 0x000000FF // Self Address Mask for 9-Bit Mode + +#define UART_9BITAMASK_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//****************************************************************************** +#define UART_PP_MSE 0x00000008 // Modem Support Extended +#define UART_PP_MS 0x00000004 // Modem Support +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//****************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source + // 0x00000005 : UART_CC_CS_PIOSC : + // PIOSC 0x00000000 : + // UART_CC_CS_SYSCLK : The system + // clock (default) +#define UART_CC_CS_S 0 + + + +#endif // __HW_UART_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_udma.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_udma.h new file mode 100644 index 0000000000..9a495baea8 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_udma.h @@ -0,0 +1,336 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// The following are defines for the UDMA register offsets. +// +//***************************************************************************** +#define UDMA_O_STAT 0x00000000 +#define UDMA_O_CFG 0x00000004 +#define UDMA_O_CTLBASE 0x00000008 +#define UDMA_O_ALTBASE 0x0000000C +#define UDMA_O_WAITSTAT 0x00000010 +#define UDMA_O_SWREQ 0x00000014 +#define UDMA_O_USEBURSTSET 0x00000018 +#define UDMA_O_USEBURSTCLR 0x0000001C +#define UDMA_O_REQMASKSET 0x00000020 +#define UDMA_O_REQMASKCLR 0x00000024 +#define UDMA_O_ENASET 0x00000028 +#define UDMA_O_ENACLR 0x0000002C +#define UDMA_O_ALTSET 0x00000030 +#define UDMA_O_ALTCLR 0x00000034 +#define UDMA_O_PRIOSET 0x00000038 +#define UDMA_O_PRIOCLR 0x0000003C +#define UDMA_O_ERRCLR 0x0000004C +#define UDMA_O_CHASGN 0x00000500 +#define UDMA_O_CHIS 0x00000504 +#define UDMA_O_CHMAP0 0x00000510 +#define UDMA_O_CHMAP1 0x00000514 +#define UDMA_O_CHMAP2 0x00000518 +#define UDMA_O_CHMAP3 0x0000051C +#define UDMA_O_PV 0x00000FB0 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_STAT register. +// +//****************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_DMACHANS_S 16 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status + // 0x00000090 : UDMA_STAT_STATE_DONE + // : Done 0x00000000 : + // UDMA_STAT_STATE_IDLE : Idle + // 0x00000010 : + // UDMA_STAT_STATE_RD_CTRL : Reading + // channel controller data + // 0x00000030 : + // UDMA_STAT_STATE_RD_DSTENDP : + // Reading destination end pointer + // 0x00000040 : + // UDMA_STAT_STATE_RD_SRCDAT : + // Reading source data 0x00000020 : + // UDMA_STAT_STATE_RD_SRCENDP : + // Reading source end pointer + // 0x00000080 : + // UDMA_STAT_STATE_STALL : Stalled + // 0x000000A0 : + // UDMA_STAT_STATE_UNDEF : Undefined + // 0x00000060 : UDMA_STAT_STATE_WAIT + // : Waiting for uDMA request to + // clear 0x00000070 : + // UDMA_STAT_STATE_WR_CTRL : Writing + // channel controller data + // 0x00000050 : + // UDMA_STAT_STATE_WR_DSTDAT : + // Writing destination data +#define UDMA_STAT_STATE_S 4 +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CFG register. +// +//****************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CTLBASE register. +// +//****************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTBASE register. +// +//****************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_WAITSTAT register. +// +//****************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M \ + 0xFFFFFFFF // Channel [n] Wait Status + +#define UDMA_WAITSTAT_WAITREQ_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SWREQ register. +// +//****************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request +#define UDMA_SWREQ_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UDMA_O_USEBURSTSET register. +// +//****************************************************************************** +#define UDMA_USEBURSTSET_SET_M \ + 0xFFFFFFFF // Channel [n] Useburst Set + +#define UDMA_USEBURSTSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UDMA_O_USEBURSTCLR register. +// +//****************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M \ + 0xFFFFFFFF // Channel [n] Useburst Clear + +#define UDMA_USEBURSTCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_REQMASKSET register. +// +//****************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set +#define UDMA_REQMASKSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register. +// +//****************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear +#define UDMA_REQMASKCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ENASET register. +// +//****************************************************************************** +#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set +#define UDMA_ENASET_CHENSET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ENACLR register. +// +//****************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear +#define UDMA_ENACLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTSET register. +// +//****************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set +#define UDMA_ALTSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTCLR register. +// +//****************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear +#define UDMA_ALTCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PRIOSET register. +// +//****************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set +#define UDMA_PRIOSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PRIOCLR register. +// +//****************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear +#define UDMA_PRIOCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ERRCLR register. +// +//****************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHASGN register. +// +//****************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHIS register. +// +//****************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status +#define UDMA_CHIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP0 register. +// +//****************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH0SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP1 register. +// +//****************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH8SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP2 register. +// +//****************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH16SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP3 register. +// +//****************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH24SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PV register. +// +//****************************************************************************** +#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision +#define UDMA_PV_MAJOR_S 8 +#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision +#define UDMA_PV_MINOR_S 0 + + + +#endif // __HW_UDMA_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_wdt.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_wdt.h new file mode 100644 index 0000000000..00b14acbe3 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_wdt.h @@ -0,0 +1,131 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// The following are defines for the WDT register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 +#define WDT_O_VALUE 0x00000004 +#define WDT_O_CTL 0x00000008 +#define WDT_O_ICR 0x0000000C +#define WDT_O_RIS 0x00000010 +#define WDT_O_MIS 0x00000014 +#define WDT_O_TEST 0x00000418 +#define WDT_O_LOCK 0x00000C00 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//****************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//****************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//****************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit + // is not used in cc3xx, WDOG shall + // always generate RESET to system + // irrespective of this bit setting. +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//****************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//****************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//****************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//****************************************************************************** +#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable +#define WDT_TEST_STALL_EN_S 10 +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//****************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_S 0 +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + + + + + +#endif // __HW_WDT_H__ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200/cc3200.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200/cc3200.h new file mode 100644 index 0000000000..d9a3c1cc78 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200/cc3200.h @@ -0,0 +1,118 @@ + + +#ifndef __CC3200_H +#define __CC3200_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + +typedef enum +{ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ + +} IRQn_Type; + + +#include "core_cm4.h" + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif // __CC3200_H \ No newline at end of file diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200/cmparams.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200/cmparams.h new file mode 100644 index 0000000000..a98242b1bc --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200/cmparams.h @@ -0,0 +1,119 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file CC3200/cmparams.h + * @brief ARM Cortex-M4 parameters for the CC3200. + * + * @defgroup ARMCMx_CC3200 CC3200 Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * CC3200 platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/* Defines required for correct CMSIS header functioning */ +#define __MPU_PRESENT 1 /**< MPU present */ +#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 1 /**< Use different SysTick Config */ +#define __FPU_PRESENT 1 /**< FPU present */ + +/* The following two defines are needed by ChibiOS */ +#define SVCall_IRQn -5 +#define PendSV_IRQn -3 + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 1 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 184 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +// /* If the device type is not externally defined, for example from the Makefile, +// then a file named board.h is included. This file must contain a device +// definition compatible with the vendor include file.*/ +// #if !defined(STM32F405xx) && !defined(STM32F415xx) && \ +// !defined(STM32F407xx) && !defined(STM32F417xx) && \ +// !defined(STM32F427xx) && !defined(STM32F437xx) && \ +// !defined(STM32F429xx) && !defined(STM32F439xx) && \ +// !defined(STM32F401xC) && !defined(STM32F401xE) && \ +// !defined(STM32F410Cx) && !defined(STM32F410Rx) && \ +// !defined(STM32F411xE) && !defined(STM32F446xx) && \ +// !defined(STM32F469xx) && !defined(STM32F479xx) +#include "board.h" +// #endif + +typedef int IRQn_Type; + +#include "core_cm4.h" + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +//#include "cc3200.h" + + +/* Including the CCWare peripheral headers.*/ +#include "asmdefs.h" +#include "hw_adc.h" +#include "hw_aes.h" +#include "hw_apps_config.h" +#include "hw_apps_rcm.h" +#include "hw_camera.h" +#include "hw_common_reg.h" +#include "hw_des.h" +#include "hw_dthe.h" +#include "hw_flash_ctrl.h" +#include "hw_gpio.h" +#include "hw_gprcm.h" +#include "hw_hib1p2.h" +#include "hw_hib3p3.h" +#include "hw_i2c.h" +#include "hw_ints.h" +#include "hw_mcasp.h" +#include "hw_mcspi.h" +#include "hw_memmap.h" +#include "hw_mmchs.h" +#include "hw_nvic.h" +#include "hw_ocp_shared.h" +#include "hw_shamd5.h" +#include "hw_stack_die_ctrl.h" +#include "hw_timer.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "hw_udma.h" +#include "hw_wdt.h" + +#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8) +#error "CCWare NUM_INTERRUPTS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.c new file mode 100644 index 0000000000..6349b509fb --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.c @@ -0,0 +1,432 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file GPIO/hal_pal_lld.c + * @brief TICC3200 PAL subsystem low level driver. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if TICC3200_HAS_GPIOA || defined(__DOXYGEN__) +#define GPIOA_BIT (1 << 0) +#if TICC3200_GPIO_GPIOA_USE_AHB && defined(TM4C123x) +#define GPIOA_AHB_BIT (1 << 0) +#else +#define GPIOA_AHB_BIT 0 +#endif +#else +#define GPIOA_BIT 0 +#define GPIOA_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOB || defined(__DOXYGEN__) +#define GPIOB_BIT (1 << 1) +#if TICC3200_GPIO_GPIOB_USE_AHB && defined(TM4C123x) +#define GPIOB_AHB_BIT (1 << 1) +#else +#define GPIOB_AHB_BIT 0 +#endif +#else +#define GPIOB_BIT 0 +#define GPIOB_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOC || defined(__DOXYGEN__) +#define GPIOC_BIT (1 << 2) +#if TICC3200_GPIO_GPIOC_USE_AHB && defined(TM4C123x) +#define GPIOC_AHB_BIT (1 << 2) +#else +#define GPIOC_AHB_BIT 0 +#endif +#else +#define GPIOC_BIT 0 +#define GPIOC_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOD || defined(__DOXYGEN__) +#define GPIOD_BIT (1 << 3) +#if TICC3200_GPIO_GPIOD_USE_AHB && defined(TM4C123x) +#define GPIOD_AHB_BIT (1 << 3) +#else +#define GPIOD_AHB_BIT 0 +#endif +#else +#define GPIOD_BIT 0 +#define GPIOD_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOE || defined(__DOXYGEN__) +#define GPIOE_BIT (1 << 4) +#if TICC3200_GPIO_GPIOE_USE_AHB && defined(TM4C123x) +#define GPIOE_AHB_BIT (1 << 4) +#else +#define GPIOE_AHB_BIT 0 +#endif +#else +#define GPIOE_BIT 0 +#define GPIOE_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOF || defined(__DOXYGEN__) +#define GPIOF_BIT (1 << 5) +#if TICC3200_GPIO_GPIOF_USE_AHB && defined(TM4C123x) +#define GPIOF_AHB_BIT (1 << 5) +#else +#define GPIOF_AHB_BIT 0 +#endif +#else +#define GPIOF_BIT 0 +#define GPIOF_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOG || defined(__DOXYGEN__) +#define GPIOG_BIT (1 << 6) +#if TICC3200_GPIO_GPIOG_USE_AHB && defined(TM4C123x) +#define GPIOG_AHB_BIT (1 << 6) +#else +#define GPIOG_AHB_BIT 0 +#endif +#else +#define GPIOG_BIT 0 +#define GPIOG_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOH || defined(__DOXYGEN__) +#define GPIOH_BIT (1 << 7) +#if TICC3200_GPIO_GPIOH_USE_AHB && defined(TM4C123x) +#define GPIOH_AHB_BIT (1 << 7) +#else +#define GPIOH_AHB_BIT 0 +#endif +#else +#define GPIOH_BIT 0 +#define GPIOH_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOJ || defined(__DOXYGEN__) +#define GPIOJ_BIT (1 << 8) +#if TICC3200_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) +#define GPIOJ_AHB_BIT (1 << 8) +#else +#define GPIOJ_AHB_BIT 0 +#endif +#else +#define GPIOJ_BIT 0 +#define GPIOJ_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOK || defined(__DOXYGEN__) +#define GPIOK_BIT (1 << 9) +#define GPIOK_AHB_BIT (1 << 9) +#else +#define GPIOK_BIT 0 +#define GPIOK_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOL || defined(__DOXYGEN__) +#define GPIOL_BIT (1 << 10) +#define GPIOL_AHB_BIT (1 << 10) +#else +#define GPIOL_BIT 0 +#define GPIOL_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOM || defined(__DOXYGEN__) +#define GPIOM_BIT (1 << 11) +#define GPIOM_AHB_BIT (1 << 11) +#else +#define GPIOM_BIT 0 +#define GPIOM_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPION || defined(__DOXYGEN__) +#define GPION_BIT (1 << 12) +#define GPION_AHB_BIT (1 << 12) +#else +#define GPION_BIT 0 +#define GPION_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOP || defined(__DOXYGEN__) +#define GPIOP_BIT (1 << 13) +#define GPIOP_AHB_BIT (1 << 13) +#else +#define GPIOP_BIT 0 +#define GPIOP_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOQ || defined(__DOXYGEN__) +#define GPIOQ_BIT (1 << 14) +#define GPIOQ_AHB_BIT (1 << 14) +#else +#define GPIOQ_BIT 0 +#define GPIOQ_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOR || defined(__DOXYGEN__) +#define GPIOR_BIT (1 << 15) +#define GPIOR_AHB_BIT (1 << 15) +#else +#define GPIOR_BIT 0 +#define GPIOR_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOS || defined(__DOXYGEN__) +#define GPIOS_BIT (1 << 16) +#define GPIOS_AHB_BIT (1 << 16) +#else +#define GPIOS_BIT 0 +#define GPIOS_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOT || defined(__DOXYGEN__) +#define GPIOT_BIT (1 << 17) +#define GPIOT_AHB_BIT (1 << 17) +#else +#define GPIOT_BIT 0 +#define GPIOT_AHB_BIT 0 +#endif + +#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ + GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ + GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ + GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ + GPIOS_BIT | GPIOR_BIT) + +#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \ + GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \ + GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \ + GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \ + GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \ + GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT) + +#define GPIOC_JTAG_MASK (0x0F) +#define GPIOD_NMI_MASK (0x80) +#define GPIOF_NMI_MASK (0x01) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the port with the port configuration. + * + * @param[in] port the port identifier + * @param[in] config the port configuration + */ +static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) +{ + HWREG(port + GPIO_O_DATA) = config->data; + HWREG(port + GPIO_O_DIR) = config->dir; + HWREG(port + GPIO_O_AFSEL) = config->afsel; + HWREG(port + GPIO_O_DR2R) = config->dr2r; + HWREG(port + GPIO_O_DR4R) = config->dr4r; + HWREG(port + GPIO_O_DR8R) = config->dr8r; + HWREG(port + GPIO_O_ODR) = config->odr; + HWREG(port + GPIO_O_PUR) = config->pur; + HWREG(port + GPIO_O_PDR) = config->pdr; + HWREG(port + GPIO_O_SLR) = config->slr; + HWREG(port + GPIO_O_DEN) = config->den; + HWREG(port + GPIO_O_AMSEL) = config->amsel; + HWREG(port + GPIO_O_PCTL) = config->pctl; +} + +/** + * @brief Unlocks the masked pins of the GPIO peripheral. + * @note This function is only useful for PORTC0-3, PORTD7 and PORTF0. + * + * @param[in] port the port identifier + * @param[in] mask the pin mask + */ +static void gpio_unlock(ioportid_t port, ioportmask_t mask) +{ + + HWREG(port + GPIO_O_LOCK) = GPIO_LOCK_KEY; + HWREG(port + GPIO_O_CR) = mask; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Tiva I/O ports configuration. + * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled. + * + * @param[in] config the Tiva ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) +{ + /* + * Enables all GPIO clocks. + */ + HWREG(SYSCTL_RCGCGPIO) = RCGCGPIO_MASK; +#if defined(TM4C123x) + HWREG(SYSCTL_GPIOHBCTL) = GPIOHBCTL_MASK; +#endif + + /* Wait until all GPIO modules are ready */ + while (!((HWREG(SYSCTL_PRGPIO) & RCGCGPIO_MASK) == RCGCGPIO_MASK)) + ; + +#if TICC3200_HAS_GPIOA + gpio_init(GPIOA, &config->PAData); +#endif +#if TICC3200_HAS_GPIOB + gpio_init(GPIOB, &config->PBData); +#endif +#if TICC3200_HAS_GPIOC + /* Unlock JTAG pins.*/ + gpio_unlock(GPIOC, GPIOC_JTAG_MASK); + gpio_init(GPIOC, &config->PCData); +#endif +#if TICC3200_HAS_GPIOD + /* Unlock NMI pin.*/ + gpio_unlock(GPIOD, GPIOD_NMI_MASK); + gpio_init(GPIOD, &config->PDData); +#endif +#if TICC3200_HAS_GPIOE + gpio_init(GPIOE, &config->PEData); +#endif +#if TICC3200_HAS_GPIOF + /* Unlock NMI pin.*/ + gpio_unlock(GPIOF, GPIOF_NMI_MASK); + gpio_init(GPIOF, &config->PFData); +#endif +#if TICC3200_HAS_GPIOG || defined(__DOXYGEN__) + gpio_init(GPIOG, &config->PGData); +#endif +#if TICC3200_HAS_GPIOH || defined(__DOXYGEN__) + gpio_init(GPIOH, &config->PHData); +#endif +#if TICC3200_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_init(GPIOJ, &config->PJData); +#endif +#if TICC3200_HAS_GPIOK || defined(__DOXYGEN__) + gpio_init(GPIOK, &config->PKData); +#endif +#if TICC3200_HAS_GPIOL || defined(__DOXYGEN__) + gpio_init(GPIOL, &config->PLData); +#endif +#if TICC3200_HAS_GPIOM || defined(__DOXYGEN__) + gpio_init(GPIOM, &config->PMData); +#endif +#if TICC3200_HAS_GPION || defined(__DOXYGEN__) + gpio_init(GPION, &config->PNData); +#endif +#if TICC3200_HAS_GPIOP || defined(__DOXYGEN__) + gpio_init(GPIOP, &config->PPData); +#endif +#if TICC3200_HAS_GPIOQ || defined(__DOXYGEN__) + gpio_init(GPIOQ, &config->PQData); +#endif +#if TICC3200_HAS_GPIOR || defined(__DOXYGEN__) + gpio_init(GPIOR, &config->PRData); +#endif +#if TICC3200_HAS_GPIOS || defined(__DOXYGEN__) + gpio_init(GPIOS, &config->PSData); +#endif +#if TICC3200_HAS_GPIOT || defined(__DOXYGEN__) + gpio_init(GPIOT, &config->PTData); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) +{ + uint32_t dir = (mode & PAL_TICC3200_DIR_MASK) >> 0; + uint32_t afsel = (mode & PAL_TICC3200_AFSEL_MASK) >> 1; + uint32_t dr2r = (mode & PAL_TICC3200_DR2R_MASK) >> 2; + uint32_t dr4r = (mode & PAL_TICC3200_DR4R_MASK) >> 3; + uint32_t dr8r = (mode & PAL_TICC3200_DR8R_MASK) >> 4; + uint32_t odr = (mode & PAL_TICC3200_ODR_MASK) >> 5; + uint32_t pur = (mode & PAL_TICC3200_PUR_MASK) >> 6; + uint32_t pdr = (mode & PAL_TICC3200_PDR_MASK) >> 7; + uint32_t slr = (mode & PAL_TICC3200_SLR_MASK) >> 8; + uint32_t den = (mode & PAL_TICC3200_DEN_MASK) >> 9; + uint32_t amsel = (mode & PAL_TICC3200_AMSEL_MASK) >> 10; + uint32_t pctl = (mode & PAL_TICC3200_PCTL_MASK) >> 11; + uint32_t bit = 0; + + while(TRUE) { + uint32_t pctl_mask = (7 << (4 * bit)); + uint32_t bit_mask = (1 << bit); + + if ((mask & 1) != 0) { + HWREG(port + GPIO_O_DIR) = (HWREG(port + GPIO_O_DIR) & ~bit_mask) | dir; + HWREG(port + GPIO_O_AFSEL) = (HWREG(port + GPIO_O_AFSEL) & ~bit_mask) | afsel; + HWREG(port + GPIO_O_DR2R) = (HWREG(port + GPIO_O_DR2R) & ~bit_mask) | dr2r; + HWREG(port + GPIO_O_DR4R) = (HWREG(port + GPIO_O_DR4R) & ~bit_mask) | dr4r; + HWREG(port + GPIO_O_DR8R) = (HWREG(port + GPIO_O_DR8R) & ~bit_mask) | dr8r; + HWREG(port + GPIO_O_ODR) = (HWREG(port + GPIO_O_ODR) & ~bit_mask) | odr; + HWREG(port + GPIO_O_PUR) = (HWREG(port + GPIO_O_PUR) & ~bit_mask) | pur; + HWREG(port + GPIO_O_PDR) = (HWREG(port + GPIO_O_PDR) & ~bit_mask) | pdr; + HWREG(port + GPIO_O_SLR) = (HWREG(port + GPIO_O_SLR) & ~bit_mask) | slr; + HWREG(port + GPIO_O_DEN) = (HWREG(port + GPIO_O_DEN) & ~bit_mask) | den; + HWREG(port + GPIO_O_AMSEL) = (HWREG(port + GPIO_O_AMSEL) & ~bit_mask) | amsel; + HWREG(port + GPIO_O_PCTL) = (HWREG(port + GPIO_O_PCTL) & ~pctl_mask) | pctl; + } + + mask >>= 1; + if (!mask) { + return; + } + + dir <<= 1; + afsel <<= 1; + dr2r <<= 1; + dr4r <<= 1; + dr8r <<= 1; + odr <<= 1; + pur <<= 1; + pdr <<= 1; + slr <<= 1; + den <<= 1; + amsel <<= 1; + pctl <<= 4; + + bit++; + } +} + +#endif /* HAL_USE_PAL */ + +/** + * @} + */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.h new file mode 100644 index 0000000000..f73d22fb81 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.h @@ -0,0 +1,806 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file GPIO/hal_pal_lld.h + * @brief TICC3200 PAL subsystem low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name TICC3200 specific I/O mode flags + * @{ + */ +#define PAL_TICC3200_DIR_MASK (1 << 0) +#define PAL_TICC3200_DIR_INPUT (0 << 0) +#define PAL_TICC3200_DIR_OUTPUT (1 << 0) + +#define PAL_TICC3200_AFSEL_MASK (1 << 1) +#define PAL_TICC3200_AFSEL_GPIO (0 << 1) +#define PAL_TICC3200_AFSEL_ALTERNATE (1 << 1) + +#define PAL_TICC3200_DR2R_MASK (1 << 2) +#define PAL_TICC3200_DR2R_DISABLE (0 << 2) +#define PAL_TICC3200_DR2R_ENABLE (1 << 2) + +#define PAL_TICC3200_DR4R_MASK (1 << 3) +#define PAL_TICC3200_DR4R_DISABLE (0 << 3) +#define PAL_TICC3200_DR4R_ENABLE (1 << 3) + +#define PAL_TICC3200_DR8R_MASK (1 << 4) +#define PAL_TICC3200_DR8R_DISABLE (0 << 4) +#define PAL_TICC3200_DR8R_ENABLE (1 << 4) + +#define PAL_TICC3200_ODR_MASK (1 << 5) +#define PAL_TICC3200_ODR_PUSHPULL (0 << 5) +#define PAL_TICC3200_ODR_OPENDRAIN (1 << 5) + +#define PAL_TICC3200_PUR_MASK (1 << 6) +#define PAL_TICC3200_PUR_DISABLE (0 << 6) +#define PAL_TICC3200_PUR_ENABLE (1 << 6) + +#define PAL_TICC3200_PDR_MASK (1 << 7) +#define PAL_TICC3200_PDR_DISABLE (0 << 7) +#define PAL_TICC3200_PDR_ENABLE (1 << 7) + +#define PAL_TICC3200_SLR_MASK (1 << 8) +#define PAL_TICC3200_SLR_DISABLE (0 << 8) +#define PAL_TICC3200_SLR_ENABLE (1 << 8) + +#define PAL_TICC3200_DEN_MASK (1 << 9) +#define PAL_TICC3200_DEN_DISABLE (0 << 9) +#define PAL_TICC3200_DEN_ENABLE (1 << 9) + +#define PAL_TICC3200_AMSEL_MASK (1 << 10) +#define PAL_TICC3200_AMSEL_DISABLE (0 << 10) +#define PAL_TICC3200_AMSEL_ENABLE (1 << 10) + +#define PAL_TICC3200_PCTL_MASK (7 << 11) +#define PAL_TICC3200_PCTL(n) ((n) << 11) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_TICC3200_AFSEL_ALTERNATE | \ + PAL_TICC3200_PCTL(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief This mode is implemented as input. + */ +#define PAL_MODE_RESET PAL_MODE_INPUT + +/** + * @brief This mode is implemented as input with pull-up. + */ +#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT (PAL_TICC3200_DEN_ENABLE | \ + PAL_TICC3200_DIR_INPUT) + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_TICC3200_DIR_INPUT | \ + PAL_TICC3200_PUR_ENABLE | \ + PAL_TICC3200_DEN_ENABLE) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_TICC3200_DIR_INPUT | \ + PAL_TICC3200_PDR_ENABLE | \ + PAL_TICC3200_DEN_ENABLE) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG (PAL_TICC3200_DEN_DISABLE | \ + PAL_TICC3200_AMSEL_ENABLE) + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_TICC3200_DIR_OUTPUT | \ + PAL_TICC3200_DR2R_ENABLE | \ + PAL_TICC3200_ODR_PUSHPULL | \ + PAL_TICC3200_DEN_ENABLE) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_TICC3200_DIR_OUTPUT | \ + PAL_TICC3200_DR2R_ENABLE | \ + PAL_TICC3200_ODR_OPENDRAIN | \ + PAL_TICC3200_DEN_ENABLE) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((ioportid_t)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief GPIO port setup info. + */ +typedef struct +{ + /** @brief Initial value for DATA register.*/ + uint32_t data; + /** @brief Initial value for DIR register.*/ + uint32_t dir; + /** @brief Initial value for AFSEL register.*/ + uint32_t afsel; + /** @brief Initial value for DR2R register.*/ + uint32_t dr2r; + /** @brief Initial value for DR4R register.*/ + uint32_t dr4r; + /** @brief Initial value for DR8R register.*/ + uint32_t dr8r; + /** @brief Initial value for ODR register.*/ + uint32_t odr; + /** @brief Initial value for PUR register.*/ + uint32_t pur; + /** @brief Initial value for PDR register.*/ + uint32_t pdr; + /** @brief Initial value for SLR register.*/ + uint32_t slr; + /** @brief Initial value for DEN register.*/ + uint32_t den; + /** @brief Initial value for AMSEL register.*/ + uint32_t amsel; + /** @brief Initial value for PCTL register.*/ + uint32_t pctl; +} tiva_gpio_setup_t; + +/** + * @brief Tiva GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct +{ + /** @brief GPIO port A setup data.*/ + tiva_gpio_setup_t PAData; + /** @brief GPIO port B setup data.*/ + tiva_gpio_setup_t PBData; + /** @brief GPIO port C setup data.*/ + tiva_gpio_setup_t PCData; + /** @brief GPIO port D setup data.*/ + tiva_gpio_setup_t PDData; + /** @brief GPIO port E setup data.*/ + tiva_gpio_setup_t PEData; + /** @brief GPIO port F setup data.*/ + tiva_gpio_setup_t PFData; +#if TICC3200_HAS_GPIOG || defined(__DOXYGEN__) + /** @brief GPIO port G setup data.*/ + tiva_gpio_setup_t PGData; +#endif +#if TICC3200_HAS_GPIOH || defined(__DOXYGEN__) + /** @brief GPIO port H setup data.*/ + tiva_gpio_setup_t PHData; +#endif +#if TICC3200_HAS_GPIOJ || defined(__DOXYGEN__) + /** @brief GPIO port J setup data.*/ + tiva_gpio_setup_t PJData; +#endif +#if TICC3200_HAS_GPIOK || defined(__DOXYGEN__) + /** @brief GPIO port K setup data.*/ + tiva_gpio_setup_t PKData; +#endif +#if TICC3200_HAS_GPIOL || defined(__DOXYGEN__) + /** @brief GPIO port L setup data.*/ + tiva_gpio_setup_t PLData; +#endif +#if TICC3200_HAS_GPIOM || defined(__DOXYGEN__) + /** @brief GPIO port M setup data.*/ + tiva_gpio_setup_t PMData; +#endif +#if TICC3200_HAS_GPION || defined(__DOXYGEN__) + /** @brief GPIO port N setup data.*/ + tiva_gpio_setup_t PNData; +#endif +#if TICC3200_HAS_GPIOP || defined(__DOXYGEN__) + /** @brief GPIO port P setup data.*/ + tiva_gpio_setup_t PPData; +#endif +#if TICC3200_HAS_GPIOQ || defined(__DOXYGEN__) + /** @brief GPIO port Q setup data.*/ + tiva_gpio_setup_t PQData; +#endif +#if TICC3200_HAS_GPIOR || defined(__DOXYGEN__) + /** @brief GPIO port R setup data.*/ + tiva_gpio_setup_t PRData; +#endif +#if TICC3200_HAS_GPIOS || defined(__DOXYGEN__) + /** @brief GPIO port S setup data.*/ + tiva_gpio_setup_t PSData; +#endif +#if TICC3200_HAS_GPIOT || defined(__DOXYGEN__) + /** @brief GPIO port T setup data.*/ + tiva_gpio_setup_t PTData; +#endif +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Port Identifier. + */ +typedef uint32_t ioportid_t; + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +#if defined(TM4C123x) + +/** + * @brief GPIOA AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set + * to @p FALSE the APB bus is used to access GPIOA. + */ +#if !defined(TICC3200_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOA_USE_AHB TRUE +#endif + +/** + * @brief GPIOB AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set + * to @p FALSE the APB bus is used to access GPIOB. + */ +#if !defined(TICC3200_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOB_USE_AHB TRUE +#endif + +/** + * @brief GPIOC AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set + * to @p FALSE the APB bus is used to access GPIOC. + */ +#if !defined(TICC3200_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOC_USE_AHB TRUE +#endif + +/** + * @brief GPIOD AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set + * to @p FALSE the APB bus is used to access GPIOD. + */ +#if !defined(TICC3200_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOD_USE_AHB TRUE +#endif + +/** + * @brief GPIOE AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set + * to @p FALSE the APB bus is used to access GPIOE. + */ +#if !defined(TICC3200_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOE_USE_AHB TRUE +#endif + +/** + * @brief GPIOF AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set + * to @p FALSE the APB bus is used to access GPIOF. + */ +#if !defined(TICC3200_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOF_USE_AHB TRUE +#endif + +/** + * @brief GPIOG AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set + * to @p FALSE the APB bus is used to access GPIOG. + */ +#if !defined(TICC3200_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOG_USE_AHB TRUE +#endif + +/** + * @brief GPIOH AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set + * to @p FALSE the APB bus is used to access GPIOH. + */ +#if !defined(TICC3200_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOH_USE_AHB TRUE +#endif + +/** + * @brief GPIOJ AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set + * to @p FALSE the APB bus is used to access GPIOJ. + */ +#if !defined(TICC3200_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOJ_USE_AHB TRUE +#endif + +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TICC3200_GPIO_GPIOA_USE_AHB && defined(TM4C123x) +#define GPIOA GPIO_PORTA_AHB_BASE +#else +#define GPIOA GPIO_PORTA_BASE +#endif + +#if TICC3200_GPIO_GPIOB_USE_AHB && defined(TM4C123x) +#define GPIOB GPIO_PORTB_AHB_BASE +#else +#define GPIOB GPIO_PORTB_BASE +#endif + +#if TICC3200_GPIO_GPIOC_USE_AHB && defined(TM4C123x) +#define GPIOC GPIO_PORTC_AHB_BASE +#else +#define GPIOC GPIO_PORTC_BASE +#endif + +#if TICC3200_GPIO_GPIOD_USE_AHB && defined(TM4C123x) +#define GPIOD GPIO_PORTD_AHB_BASE +#else +#define GPIOD GPIO_PORTD_BASE +#endif + +#if TICC3200_GPIO_GPIOE_USE_AHB && defined(TM4C123x) +#define GPIOE GPIO_PORTE_AHB_BASE +#else +#define GPIOE GPIO_PORTE_BASE +#endif + +#if TICC3200_GPIO_GPIOF_USE_AHB && defined(TM4C123x) +#define GPIOF GPIO_PORTF_AHB_BASE +#else +#define GPIOF GPIO_PORTF_BASE +#endif + +#if TICC3200_GPIO_GPIOG_USE_AHB && defined(TM4C123x) +#define GPIOG GPIO_PORTG_AHB_BASE +#else +#define GPIOG GPIO_PORTG_BASE +#endif + +#if TICC3200_GPIO_GPIOH_USE_AHB && defined(TM4C123x) +#define GPIOH GPIO_PORTH_AHB_BASE +#else +#define GPIOH GPIO_PORTH_BASE +#endif + +#if TICC3200_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) +#define GPIOJ GPIO_PORTJ_AHB_BASE +#else +#define GPIOJ GPIO_PORTJ_BASE +#endif + +#define GPIOK GPIO_PORTK_BASE +#define GPIOL GPIO_PORTL_BASE +#define GPIOM GPIO_PORTM_BASE +#define GPION GPIO_PORTN_BASE +#define GPIOP GPIO_PORTP_BASE +#define GPIOQ GPIO_PORTQ_BASE +#define GPIOR GPIO_PORTR_BASE +#define GPIOS GPIO_PORTS_BASE +#define GPIOT GPIO_PORTT_BASE + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 GPIOA + +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 GPIOB + +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 GPIOC + +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 GPIOD + +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 GPIOE + +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 GPIOF + +/** + * @brief GPIO port G identifier. + */ +#if TICC3200_HAS_GPIOG || defined(__DOXYGEN__) +#define IOPORT7 GPIOG +#endif + +/** + * @brief GPIO port H identifier. + */ +#if TICC3200_HAS_GPIOH || defined(__DOXYGEN__) +#define IOPORT8 GPIOH +#endif + +/** + * @brief GPIO port J identifier. + */ +#if TICC3200_HAS_GPIOJ || defined(__DOXYGEN__) +#define IOPORT9 GPIOJ +#endif + +/** + * @brief GPIO port K identifier. + */ +#if TICC3200_HAS_GPIOK || defined(__DOXYGEN__) +#define IOPORT10 GPIOK +#endif + +/** + * @brief GPIO port L identifier. + */ +#if TICC3200_HAS_GPIOL || defined(__DOXYGEN__) +#define IOPORT11 GPIOL +#endif + +/** + * @brief GPIO port M identifier. + */ +#if TICC3200_HAS_GPIOM || defined(__DOXYGEN__) +#define IOPORT12 GPIOM +#endif + +/** + * @brief GPIO port N identifier. + */ +#if TICC3200_HAS_GPION || defined(__DOXYGEN__) +#define IOPORT13 GPION +#endif + +/** + * @brief GPIO port P identifier. + */ +#if TICC3200_HAS_GPIOP || defined(__DOXYGEN__) +#define IOPORT14 GPIOP +#endif + +/** + * @brief GPIO port Q identifier. + */ +#if TICC3200_HAS_GPIOQ || defined(__DOXYGEN__) +#define IOPORT15 GPIOQ +#endif + +/** + * @brief GPIO port R identifier. + */ +#if TICC3200_HAS_GPIOR || defined(__DOXYGEN__) +#define IOPORT16 GPIOR +#endif + +/** + * @brief GPIO port S identifier. + */ +#if TICC3200_HAS_GPIOS || defined(__DOXYGEN__) +#define IOPORT17 GPIOS +#endif + +/** + * @brief GPIO port T identifier. + */ +#if TICC3200_HAS_GPIOT || defined(__DOXYGEN__) +#define IOPORT18 GPIOT +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) (HWREG((port) + GPIO_O_GPIO_DATA + (0xff << 2))) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) pal_lld_readport(port) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) (HWREG((port) + GPIO_O_GPIO_DATA + (0xff << 2)) = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) (HWREG((port) + (GPIO_O_GPIO_DATA + (bits << 2))) = 0xFF) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) (HWREG((port) + (GPIO_O_GPIO_DATA + (bits << 2))) = 0) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + (((mask) << (offset)) << 2)))) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + (((mask) << (offset)) << 2))) = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) (HWREG((port) + (GPIO_O_GPIO_DATA + ((1 << (pad)) << 2)))) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + ((1 << (pad)) << 2))) = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + ((1 << (pad)) << 2))) = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + ((1 << (pad)) << 2))) = 0) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.c new file mode 100644 index 0000000000..06b2f946c6 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.c @@ -0,0 +1,244 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file GPTM/hal_st_lld.c + * @brief ST Driver subsystem low level driver code. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + +#if (TICC3200_ST_USE_WIDE_TIMER == TRUE) + +#if TICC3200_ST_TIMER_NUMBER == 0 +#define ST_HANDLER TICC3200_WGPT0A_HANDLER +#define ST_NUMBER TICC3200_WGPT0A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 0))) + +#elif TICC3200_ST_TIMER_NUMBER == 1 +#define ST_HANDLER TICC3200_WGPT1A_HANDLER +#define ST_NUMBER TICC3200_WGPT1A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 1))) + +#elif TICC3200_ST_TIMER_NUMBER == 2 +#define ST_HANDLER TICC3200_WGPT2A_HANDLER +#define ST_NUMBER TICC3200_WGPT2A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 2))) + +#elif TICC3200_ST_TIMER_NUMBER == 3 +#define ST_HANDLER TICC3200_WGPT3A_HANDLER +#define ST_NUMBER TICC3200_WGPT3A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 3))) + +#elif TICC3200_ST_TIMER_NUMBER == 4 +#define ST_HANDLER TICC3200_WGPT4A_HANDLER +#define ST_NUMBER TICC3200_WGPT4A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 4))) + +#elif TICC3200_ST_TIMER_NUMBER == 5 +#define ST_HANDLER TICC3200_WGPT5A_HANDLER +#define ST_NUMBER TICC3200_WGPT5A_NUMBER +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5))) + +#else +#error "TICC3200_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF +#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" +#endif + +#elif (TICC3200_ST_USE_WIDE_TIMER == FALSE) + +#if TICC3200_ST_TIMER_NUMBER == 0 +#define ST_HANDLER TICC3200_GPT0A_HANDLER +#define ST_NUMBER TICC3200_GPT0A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 0))) + +#elif TICC3200_ST_TIMER_NUMBER == 1 +#define ST_HANDLER TICC3200_GPT1A_HANDLER +#define ST_NUMBER TICC3200_GPT1A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 1))) + +#elif TICC3200_ST_TIMER_NUMBER == 2 +#define ST_HANDLER TICC3200_GPT2A_HANDLER +#define ST_NUMBER TICC3200_GPT2A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 2))) + +#elif TICC3200_ST_TIMER_NUMBER == 3 +#define ST_HANDLER TICC3200_GPT3A_HANDLER +#define ST_NUMBER TICC3200_GPT3A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 3))) + +#elif TICC3200_ST_TIMER_NUMBER == 4 +#define ST_HANDLER TICC3200_GPT4A_HANDLER +#define ST_NUMBER TICC3200_GPT4A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 4))) + +#elif TICC3200_ST_TIMER_NUMBER == 5 +#define ST_HANDLER TICC3200_GPT5A_HANDLER +#define ST_NUMBER TICC3200_GPT5A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 5))) + +#else +#error "TICC3200_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if (TICC3200_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFF +#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" +#endif + +#endif + +#if TICC3200_SYSCLK % OSAL_ST_FREQUENCY != 0 +#error "the selected ST frequency is not obtainable because integer rounding" +#endif + +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) +/** + * @brief System Timer vector. + * @details This interrupt is used for system tick in periodic mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(SysTick_Handler) +{ + OSAL_IRQ_PROLOGUE(); + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) +/** + * @brief GPT interrupt handler. + * @details This interrupt is used for system tick in free running mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(ST_HANDLER) +{ + uint32_t mis; + + OSAL_IRQ_PROLOGUE(); + + mis = HWREG(TICC3200_ST_TIM + TIMER_O_MIS); + HWREG(TICC3200_ST_TIM + TIMER_O_ICR) = mis; + + if (mis & TIMER_IMR_TAMIM) { + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + } + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) +{ +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + /* Free running counter mode.*/ + + /* Enabling timer clock.*/ + ST_ENABLE_CLOCK(); + + /* Wait until timer peripheral is ready */ + ST_WAIT_CLOCK(); + + /* Initializing the counter in free running down mode.*/ + HWREG(TICC3200_ST_TIM + TIMER_O_CTL) = 0; + HWREG(TICC3200_ST_TIM + TIMER_O_CFG) = TIMER_CFG_16_BIT; /* Timer split mode */ + HWREG(TICC3200_ST_TIM + TIMER_O_TAMR) = ( + TIMER_TAMR_TAMR_PERIOD | /* Periodic mode */ + TIMER_TAMR_TAMIE | /* Match interrupt enable */ + TIMER_TAMR_TASNAPS); /* Snapshot mode */ + + HWREG(TICC3200_ST_TIM + TIMER_O_TAPR) = (TICC3200_SYSCLK / OSAL_ST_FREQUENCY) - 1; + HWREG(TICC3200_ST_TIM + TIMER_O_CTL) = ( + TIMER_CTL_TAEN | /* Timer A enable */ + TIMER_CTL_TASTALL); /* Timer A stall when paused */ + + /* IRQ enabled.*/ + nvicEnableVector(ST_NUMBER, TICC3200_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = (TICC3200_SYSCLK / OSAL_ST_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, TICC3200_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** + * @} + */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.h new file mode 100644 index 0000000000..013211d173 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.h @@ -0,0 +1,199 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file GPTM/hal_st_lld.h + * @brief ST Driver subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +#include "mcuconf.h" +#include "ticc3200_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(TICC3200_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_ST_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPTx unit (by number) to be used for free running operations. + * @note You must select a 32 bits timer if a 32 bits @p systick_t type + * is required. + */ +#if !defined(TICC3200_ST_TIMER_NUMBER) || defined(__DOXYGEN__) +#define TICC3200_ST_TIMER_NUMBER 0 +#endif + +/** + * @brief When set to @p TRUE a wide timer is used. When set to @p FALSE a + * normal timer is used. + */ +#if !defined(TICC3200_ST_USE_WIDE_TIMER) || defined(__DOXYGEN__) +#define TICC3200_ST_USE_WIDE_TIMER TRUE +#endif + +/** + * @} + */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TICC3200_ST_TIMER_NUMBER == 0 +#if !TICC3200_HAS_GPT0 +#error "GPT0 not present" +#endif +#define TICC3200_ST_TIM TIMERA0_BASE + +#elif TICC3200_ST_TIMER_NUMBER == 1 +#if !TICC3200_HAS_GPT1 +#error "GPT1 not present" +#endif +#define TICC3200_ST_TIM TIMERA1_BASE + +#elif TICC3200_ST_TIMER_NUMBER == 2 +#if !TICC3200_HAS_GPT2 +#error "GPT2 not present" +#endif +#define TICC3200_ST_TIM TIMERA2_BASE + +#elif TICC3200_ST_TIMER_NUMBER == 3 +#if !TICC3200_HAS_GPT3 +#error "GPT3 not present" +#endif +#define TICC3200_ST_TIM TIMERA3_BASE + +#else +#error "TICC3200_ST_TIMER_NUMBER specifies an unsupported timer" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) +{ + return (systime_t) (((systime_t) 0xffffffff) - HWREG(TICC3200_ST_TIM + TIMER_O_TAV)); +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] time the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t time) +{ + HWREG(TICC3200_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); + HWREG(TICC3200_ST_TIM + TIMER_O_ICR) = HWREG(TICC3200_ST_TIM + TIMER_O_MIS); + HWREG(TICC3200_ST_TIM + TIMER_O_IMR) = TIMER_IMR_TAMIM; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) +{ + HWREG(TICC3200_ST_TIM + TIMER_O_IMR) = 0; +} + +/** + * @brief Sets the alarm time. + * + * @param[in] time the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t time) +{ + HWREG(TICC3200_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) +{ + return (systime_t) (((systime_t)0xffffffff) - HWREG(TICC3200_ST_TIM + TIMER_O_TAMATCHR)); +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) +{ + return (bool) ((HWREG(TICC3200_ST_TIM + TIMER_O_IMR) & TIMER_IMR_TAMIM) !=0); +} + +#endif /* HAL_ST_LLD_H */ + +/** + * @} + */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC/hal_rtc_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC/hal_rtc_lld.h new file mode 100644 index 0000000000..8ead7b02d6 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC/hal_rtc_lld.h @@ -0,0 +1,188 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file RTCv1/hal_rtc_lld.h + * @brief TCC3200 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef HAL_RTC_LLD_H +#define HAL_RTC_LLD_H + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Implementation capabilities + */ +/** + * @brief This RTC implementation supports callbacks. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief One alarm comparator available. + */ +#define RTC_ALARMS 1 + +/** + * @brief Presence of a local persistent storage. + */ +#define RTC_HAS_STORAGE FALSE +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/* + * RTC driver system settings. + */ +#define TICC3200_RTC_IRQ_PRIORITY 15 +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !TICC3200_HAS_RTC +#error "RTC not present in the selected device" +#endif + +#if TICC3200_RTCCLK == 0 +#error "RTC clock not enabled" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief FileStream specific methods. + */ +#define _rtc_driver_methods \ + _file_stream_methods + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct RTCAlarm RTCAlarm; + +/** + * @brief Type of an RTC alarm. + * @details Meaningful on platforms with more than 1 alarm comparator. + */ +typedef uint32_t rtcalarm_t; + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_SECOND = 0, /** Triggered every second. */ + RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ + RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Structure representing an RTC alarm time stamp. + */ +struct RTCAlarm { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +}; + +#if RTC_HAS_STORAGE || defined(__DOXYGEN__) +/** + * @extends FileStream + * + * @brief @p RTCDriver virtual methods table. + */ +struct RTCDriverVMT { + _rtc_driver_methods +}; +#endif + +/** + * @brief Structure representing an RTC driver. + */ +struct RTCDriver{ +#if RTC_HAS_STORAGE || defined(__DOXYGEN__) + /** + * @brief Virtual Methods Table. + */ + const struct RTCDriverVMT *vmt; +#endif + /** + * @brief Pointer to the RTC registers block. + */ + RTC_TypeDef *rtc; + /** + * @brief Callback pointer. + */ + rtccb_t callback; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern RTCDriver RTCD1; +#if RTC_HAS_STORAGE +extern struct RTCDriverVMT _rtc_lld_vmt; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_set_prescaler(void); + void rtc_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + RTCAlarm *alarmspec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); + void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec); + void rtcSTM32SetSec(RTCDriver *rtcp, uint32_t tv_sec); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* HAL_RTC_LLD_H */ + +/** @} */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART/hal_serial_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART/hal_serial_lld.h new file mode 100644 index 0000000000..5c976131c7 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART/hal_serial_lld.h @@ -0,0 +1,437 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file UART/hal_serial_lld.h + * @brief TICC3200 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef HAL_SERIAL_LLD_H +#define HAL_SERIAL_LLD_H + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Advanced buffering support switch. + * @details This constants enables the advanced buffering support in the + * low level driver, the queue buffer is no more part of the + * @p SerialDriver structure, each driver can have a different + * queue size. + */ +#define SERIAL_ADVANCED_BUFFERING_SUPPORT TRUE + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE. + */ +#if !defined(TICC3200_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART0 FALSE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART1 FALSE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART2 FALSE +#endif + +/** + * @brief UART3 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART3) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART3 FALSE +#endif + +/** + * @brief UART4 driver enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART4) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART4 FALSE +#endif + +/** + * @brief UART5 driver enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART5) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART5 FALSE +#endif + +/** + * @brief UART6 driver enable switch. + * @details If set to @p TRUE the support for UART6 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART6) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART6 FALSE +#endif + +/** + * @brief UART7 driver enable switch. + * @details If set to @p TRUE the support for UART7 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART7) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART7 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART0_PRIORITY 5 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART1_PRIORITY 5 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART2_PRIORITY 5 +#endif + +/** + * @brief UART3 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART3_PRIORITY 5 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART4_PRIORITY 5 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART5_PRIORITY 5 +#endif + +/** + * @brief UART6 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART6_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART6_PRIORITY 5 +#endif + +/** + * @brief UART7 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART7_PRIORITY 5 +#endif + +/** + * @brief Input buffer size for UART0. + */ +#if !defined(TICC3200_SERIAL_UART0_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART0_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART0. + */ +#if !defined(TICC3200_SERIAL_UART0_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART0_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART1. + */ +#if !defined(TICC3200_SERIAL_UART1_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART1. + */ +#if !defined(TICC3200_SERIAL_UART1_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART2. + */ +#if !defined(TICC3200_SERIAL_UART2_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART2_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART2. + */ +#if !defined(TICC3200_SERIAL_UART2_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART2_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART3. + */ +#if !defined(TICC3200_SERIAL_UART3_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART3_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART3. + */ +#if !defined(TICC3200_SERIAL_UART3_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART3_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART4. + */ +#if !defined(TICC3200_SERIAL_UART4_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART4_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART4. + */ +#if !defined(TICC3200_SERIAL_UART4_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART4_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART5. + */ +#if !defined(TICC3200_SERIAL_UART5_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART5_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART5. + */ +#if !defined(TICC3200_SERIAL_UART5_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART5_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART6. + */ +#if !defined(TICC3200_SERIAL_UART6_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART6_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART6. + */ +#if !defined(TICC3200_SERIAL_UART6_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART6_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART7. + */ +#if !defined(TICC3200_SERIAL_UART7_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART7_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART7. + */ +#if !defined(TICC3200_SERIAL_UART7_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART7_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !TICC3200_SERIAL_USE_UART0 && !TICC3200_SERIAL_USE_UART1 && \ + !TICC3200_SERIAL_USE_UART2 && !TICC3200_SERIAL_USE_UART3 && \ + !TICC3200_SERIAL_USE_UART4 && !TICC3200_SERIAL_USE_UART5 && \ + !TICC3200_SERIAL_USE_UART6 && !TICC3200_SERIAL_USE_UART7 +#error "SERIAL driver activated but no UART peripheral assigned" +#endif + +#if TICC3200_SERIAL_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART0_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +#if TICC3200_SERIAL_USE_UART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART1_PRIORITY) +#error "Invalid IRQ priority assigned to UART1" +#endif + +#if TICC3200_SERIAL_USE_UART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART2_PRIORITY) +#error "Invalid IRQ priority assigned to UART2" +#endif + +#if TICC3200_SERIAL_USE_UART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART3_PRIORITY) +#error "Invalid IRQ priority assigned to UART3" +#endif + +#if TICC3200_SERIAL_USE_UART4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART4_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if TICC3200_SERIAL_USE_UART5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART5_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if TICC3200_SERIAL_USE_UART6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART6_PRIORITY) +#error "Invalid IRQ priority assigned to UART6" +#endif + +#if TICC3200_SERIAL_USE_UART7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART7_PRIORITY) +#error "Invalid IRQ priority assigned to UART7" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Tiva Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields. */ + /** + * @brief Initialization value for the CTL register. + */ + uint16_t ctl; + /** + * @brief Initialization value for the LCRH register. + */ + uint8_t lcrh; + /** + * @brief Initialization value for the IFLS register. + */ + uint8_t ifls; + /** + * @brief Initialization value for the CC register. + */ + uint8_t cc; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + input_queue_t iqueue; \ + /* Output queue.*/ \ + output_queue_t oqueue; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + uint32_t uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TICC3200_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#if TICC3200_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#if TICC3200_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#if TICC3200_SERIAL_USE_UART3 && !defined(__DOXYGEN__) +extern SerialDriver SD4; +#endif + +#if TICC3200_SERIAL_USE_UART4 && !defined(__DOXYGEN__) +extern SerialDriver SD5; +#endif + +#if TICC3200_SERIAL_USE_UART5 && !defined(__DOXYGEN__) +extern SerialDriver SD6; +#endif + +#if TICC3200_SERIAL_USE_UART6 && !defined(__DOXYGEN__) +extern SerialDriver SD7; +#endif + +#if TICC3200_SERIAL_USE_UART7 && !defined(__DOXYGEN__) +extern SerialDriver SD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* HAL_SERIAL_LLD_H */ + +/** @} */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.c new file mode 100644 index 0000000000..c963351959 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.c @@ -0,0 +1,131 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file TI/TICC3200/hal_lld.c + * @brief TI CC3200 HAL Driver subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) +{ +} + +/** + * @brief CC3200 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p mcuconf.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void ti3200_clock_init(void) +{ + uint32_t rcc, rcc2, i; + + /* 1. Bypass the PLL and system clock divider by setting the BYPASS bit and + * clearing the USESYSDIV bit in the RCC register, thereby configuring the + * microcontroller to run off a "raw" clock source and allowing for the new + * PLL configuration to be validated before switching the system clock to the + * PLL. */ + /* read */ + + rcc = HWREG(SYSCTL_RCC); + rcc2 = HWREG(SYSCTL_RCC2); + + /* modify */ + rcc |= SYSCTL_RCC_BYPASS; + rcc &= ~SYSCTL_RCC_USESYSDIV; + rcc2 |= SYSCTL_RCC2_BYPASS2 | SYSCTL_RCC2_USERCC2; + + /* write */ + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; + + /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and + * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically + * pulls valid PLL configuration data for the appropriate crystal, and + * clearing the PWRDN bit powers and enables the PLL and its output. */ + /* modify */ + rcc &= ~(SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_XTAL_M | SYSCTL_RCC_PWRDN | SYSCTL_RCC_MOSCDIS); + rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_MOSCDIS)); + rcc2 &= ~(SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_PWRDN2); + rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_DIV400)); + + /* write */ + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; + for(i = 100000; i; i--); + + /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the + * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for + * the microcontroller. */ + /* modify */ + rcc &= ~SYSCTL_RCC_SYSDIV_M; + rcc |= (TIVA_SYSDIV & SYSCTL_RCC_SYSDIV_M) | SYSCTL_RCC_USESYSDIV; + rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB); + rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB)); + + /* write */ + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; + + /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw + * Interrupt Status (RIS) register. */ + while ((HWREG(SYSCTL_RIS) & SYSCTL_RIS_PLLLRIS) == 0); + + /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */ + rcc &= ~SYSCTL_RCC_BYPASS; + rcc2 &= ~SYSCTL_RCC2_BYPASS2; + rcc |= (TIVA_BYPASS_VALUE << 11); + rcc2 |= (TIVA_BYPASS_VALUE << 11); + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; + +#if HAL_USE_PWM + HWREG(SYSCTL_RCC) |= TIVA_PWM_FIELDS; +#endif + +#if defined(TICC3200_UDMA_REQUIRED) + udmaInit(); +#endif +} + +/** + * @} + */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.h new file mode 100644 index 0000000000..d21223665f --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.h @@ -0,0 +1,234 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file TI/TICC3200/hal_lld.h + * @brief TI CC3200 HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - TODO: add required macros + * + * @addtogroup HAL + * @{ + */ + +#ifndef HAL_LLD_H +#define HAL_LLD_H + +#include "ticc3200_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ + +#define PLATFORM_NAME "TI CC3200" + +/** + * @} + */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +#if !defined(TICC3200_OSCSRC) +#define TICC3200_OSCSRC SYSCTL_RCC2_OSCSRC2_MO +#endif + +#if !defined(TICC3200_MOSC_ENABLE) +#define TICC3200_MOSC_ENABLE TRUE +#endif + +#if !defined(TICC3200_DIV400_VALUE) +#define TICC3200_DIV400_VALUE 1 +#endif + +#if !defined(TICC3200_SYSDIV_VALUE) +#define TICC3200_SYSDIV_VALUE 2 +#endif + +#if !defined(TICC3200_USESYSDIV_ENABLE) +#define TICC3200_USESYSDIV_ENABLE FALSE +#endif + +#if !defined(TICC3200_SYSDIV2LSB_ENABLE) +#define TICC3200_SYSDIV2LSB_ENABLE FALSE +#endif + +#if !defined(TICC3200_BYPASS_VALUE) +#define TICC3200_BYPASS_VALUE 0 +#endif + +/** + * @} + */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(TICC3200_MCUCONF) +#error "Using a wrong mcuconf.h file, TICC3200_MCUCONF not defined" +#endif + +/* + * Oscillator-related checks. + */ +#if !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && \ + !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO) && \ + !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO4) && \ + !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_30) && \ + !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_32) +#error "Invalid value for TICC3200_OSCSRC defined" +#endif + +// #if TICC3200_XTAL_VALUE == 4000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_4MHZ +// #elif TICC3200_XTAL_VALUE == 4096000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_4_09MHZ +// #elif TICC3200_XTAL_VALUE == 4915200 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_4_91MHZ +// #elif TICC3200_XTAL_VALUE == 5000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_5MHZ +// #elif TICC3200_XTAL_VALUE == 5120000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_5_12MHZ +// #elif TICC3200_XTAL_VALUE == 6000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_6MHZ +// #elif TICC3200_XTAL_VALUE == 6144000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_6_14MHZ +// #elif TICC3200_XTAL_VALUE == 7372800 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_7_37MHZ +// #elif TICC3200_XTAL_VALUE == 8000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_8MHZ +// #elif TICC3200_XTAL_VALUE == 8192000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_8_19MHZ +// #elif TICC3200_XTAL_VALUE == 10000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_10MHZ +// #elif TICC3200_XTAL_VALUE == 12000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_12MHZ +// #elif TICC3200_XTAL_VALUE == 12288000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_12_2MHZ +// #elif TICC3200_XTAL_VALUE == 13560000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_13_5MHZ +// #elif TICC3200_XTAL_VALUE == 14318180 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_14_3MHZ +// #elif TICC3200_XTAL_VALUE == 16000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_16MHZ +// #elif TICC3200_XTAL_VALUE == 16384000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_16_3MHZ +// #elif TICC3200_XTAL_VALUE == 18000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_18MHZ +// #elif TICC3200_XTAL_VALUE == 20000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_20MHZ +// #elif TICC3200_XTAL_VALUE == 24000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_24MHZ +// #elif TICC3200_XTAL_VALUE == 25000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_25MHZ +// #else +// #error "Invalid value for TICC3200_XTAL_VALUE defined" +// #endif + +// #if TICC3200_MOSC_ENABLE == TRUE +// #define TICC3200_MOSCDIS (0 << 0) +// #define TICC3200_XTAL TICC3200_XTAL_ +// #elif TICC3200_MOSC_ENABLE == FALSE +// #define TICC3200_MOSCDIS (1 << 0) +// #define TICC3200_XTAL 0 +// #else +// #error "Invalid value for TICC3200_MOSC_ENABLE defined" +// #endif + +// #if TICC3200_DIV400_VALUE == 1 +// #define TICC3200_DIV400 (1 << 30) +// #elif TICC3200_DIV400_VALUE == 0 +// #define TICC3200_DIV400 (0 << 30) +// #else +// #error "Invalid value for TICC3200_DIV400_VALUE defined" +// #endif + +// #if (TICC3200_SYSDIV_VALUE >= 0x02) && (TICC3200_SYSDIV_VALUE <= 0x3f) +// #define TICC3200_SYSDIV (TICC3200_SYSDIV_VALUE << 23) +// #define TICC3200_SYSDIV2 (TICC3200_SYSDIV_VALUE << 23) +// #else +// #error "Invalid value for TICC3200_SYSDIV_VALUE defined" +// #endif + +// #if TICC3200_USESYSDIV_ENABLE == TRUE +// #define TICC3200_USESYSDIV (1 << 22) +// #elif TICC3200_USESYSDIV_ENABLE == FALSE +// #define TICC3200_USESYSDIV (0 << 22) +// #else +// #error "Invalid value for TICC3200_USESYSDIV_ENABLE defined" +// #endif + +// #if TICC3200_SYSDIV2LSB_ENABLE == TRUE +// #define TICC3200_SYSDIV2LSB (1 << 22) +// #elif TICC3200_SYSDIV2LSB_ENABLE == FALSE +// #define TICC3200_SYSDIV2LSB (0 << 22) +// #else +// #error "Invalid value for TICC3200_SYSDIV2LSB_ENABLE defined" +// #endif + +// #if TICC3200_BYPASS_VALUE == 1 +// #define TICC3200_SRC 16000000 +// #elif TICC3200_BYPASS_VALUE == 0 +// #define TICC3200_SRC (200000000 + (TICC3200_DIV400_VALUE * 200000000)) +// #else +// #error "Invalid value for TICC3200_BYPASS_VALUE defined" +// #endif + +// #if (TICC3200_OSCSRC == TICC3200_RCC_OSCSRC_MOSC) && (TICC3200_MOSC_ENABLE == FALSE) +// #error "Main Oscillator selected but not enabled" +// #endif + +/* + * System Clock calculation + */ +#define TICC3200_SYSCLK (TICC3200_SRC / (((TICC3200_SYSDIV_VALUE << TICC3200_DIV400_VALUE /*& TICC3200_BYPASS_VALUE*/) | (TICC3200_SYSDIV2LSB >> 22)) + 1)) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "ticc3200_isr.h" +// #include "TICC3200_udma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void ti3200_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LLD_H */ + +/** + * @} + */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_isr.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_isr.h new file mode 100644 index 0000000000..889551d871 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_isr.h @@ -0,0 +1,40 @@ + +/** + * @file TICC3200/ticc3200_isr.h + * @brief TICC3200 ISR remapper driver header. + * + * @addtogroup TICC3200_ISR + * @{ + */ + +#ifndef _TICC3200_ISR_H_ +#define _TICC3200_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ + +// /* UDMA units.*/ +// #define TICC3200_UDMA_SW_HANDLER VectorF8 +// #define TICC3200_UDMA_ERR_HANDLER VectorFC + +// #define TICC3200_UDMA_SW_NUMBER 46 +// #define TICC3200_UDMA_ERR_NUMBER 47 + +/* GPIO units.*/ +#define TICC3200_GPIOA_HANDLER INT_GPIOA0 +#define TICC3200_GPIOB_HANDLER INT_GPIOA1 +#define TICC3200_GPIOC_HANDLER INT_GPIOA2 +#define TICC3200_GPIOD_HANDLER INT_GPIOA3 + +#define TICC3200_GPIOA_NUMBER 0 +#define TICC3200_GPIOB_NUMBER 1 +#define TICC3200_GPIOC_NUMBER 2 +#define TICC3200_GPIOD_NUMBER 3 + +#endif // _TICC3200_ISR_H_ \ No newline at end of file diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_registry.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_registry.h new file mode 100644 index 0000000000..0f974458a1 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_registry.h @@ -0,0 +1,31 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file TICC3200/TICC3200_registry.h + * @brief TICC3200 capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _TICC3200_REGISTRY_H_ +#define _TICC3200_REGISTRY_H_ + +#define TICC3200_HAS_GPIOA TRUE +#define TICC3200_HAS_GPIOB TRUE +#define TICC3200_HAS_GPIOC TRUE + +#define TICC3200_HAS_GPT0 TRUE +#define TICC3200_HAS_GPT1 TRUE +#define TICC3200_HAS_GPT2 TRUE +#define TICC3200_HAS_GPT3 TRUE + +#define TICC3200_HAS_UART0 TRUE +#define TICC3200_HAS_UART1 TRUE + +#define TICC3200_HAS_RTC TRUE + +#endif // _TICC3200_REGISTRY_H_ diff --git a/targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld b/targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld deleted file mode 100644 index 580c8a01e6..0000000000 --- a/targets/TI-RTOS/CC3200/nanoCLR/cc3200_CLR.ld +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************** -* blinky.ld -* -* GCC Linker script for blinky application. -* -* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - - -HEAP_SIZE = 0x00010000; - -MEMORY -{ - /* SRAM size of 240KB for cc3200 ES 1.33 device onward */ - SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 0x3C000 -} - -SECTIONS -{ - .text : - { - _text = .; - KEEP(*(.intvecs)) - *(.text*) - *(.rodata*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(8); - _etext = .; - } > SRAM - - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > SRAM - - __init_data = .; - - .data : AT(__init_data) - { - _data = .; - *(.data*) - . = ALIGN (8); - _edata = .; - } > SRAM - - .bss : - { - _bss = .; - *(.bss*) - *(COMMON) - _ebss = .; - } > SRAM - - .heap : - { - _heap = .; - . = . + HEAP_SIZE; - . = ALIGN(8); - _eheap = .; - - } -} - diff --git a/targets/TI-RTOS/CC3200/nanoCLR/main.c b/targets/TI-RTOS/CC3200/nanoCLR/main.c deleted file mode 100644 index e9431873ca..0000000000 --- a/targets/TI-RTOS/CC3200/nanoCLR/main.c +++ /dev/null @@ -1,222 +0,0 @@ -//***************************************************************************** -// -// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ -// -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -//***************************************************************************** -// -// Application Name - Blinky -// Application Overview - The objective of this application is to showcase the -// GPIO control using Driverlib api calls. The LEDs -// connected to the GPIOs on the LP are used to indicate -// the GPIO output. The GPIOs are driven high-low -// periodically in order to turn on-off the LEDs. -// Application Details - -// http://processors.wiki.ti.com/index.php/CC32xx_Blinky_Application -// or -// docs\examples\CC32xx_Blinky_Application.pdf -// -//***************************************************************************** - -//**************************************************************************** -// -//! \addtogroup blinky -//! @{ -// -//**************************************************************************** - -// Standard includes -#include - -// Driverlib includes -#include "hw_types.h" -#include "hw_ints.h" -#include "hw_memmap.h" -#include "hw_common_reg.h" -#include "interrupt.h" -#include "hw_apps_rcm.h" -#include "prcm.h" -#include "rom.h" -#include "rom_map.h" -#include "prcm.h" -#include "gpio.h" -#include "utils.h" - -// Common interface includes -#include "gpio_if.h" - -#include "pinmux.h" - -#define APPLICATION_VERSION "1.1.1" - -//***************************************************************************** -// GLOBAL VARIABLES -- Start -//***************************************************************************** -#if defined(ccs) -extern void (* const g_pfnVectors[])(void); -#endif -#if defined(ewarm) -extern uVectorEntry __vector_table; -#endif -//***************************************************************************** -// GLOBAL VARIABLES -- End -//***************************************************************************** - - -//***************************************************************************** -// LOCAL FUNCTION PROTOTYPES -//***************************************************************************** -void LEDBlinkyRoutine(); -static void BoardInit(void); - -//***************************************************************************** -// LOCAL FUNCTION DEFINITIONS -//***************************************************************************** - -//***************************************************************************** -// -//! Configures the pins as GPIOs and peroidically toggles the lines -//! -//! \param None -//! -//! This function -//! 1. Configures 3 lines connected to LEDs as GPIO -//! 2. Sets up the GPIO pins as output -//! 3. Periodically toggles each LED one by one by toggling the GPIO line -//! -//! \return None -// -//***************************************************************************** -void LEDBlinkyRoutine() -{ - // - // Toggle the lines initially to turn off the LEDs. - // The values driven are as required by the LEDs on the LP. - // - GPIO_IF_LedOff(MCU_ALL_LED_IND); - while(1) - { - // - // Alternately toggle hi-low each of the GPIOs - // to switch the corresponding LED on/off. - // - MAP_UtilsDelay(8000000); - GPIO_IF_LedOn(MCU_RED_LED_GPIO); - MAP_UtilsDelay(8000000); - GPIO_IF_LedOff(MCU_RED_LED_GPIO); - MAP_UtilsDelay(8000000); - GPIO_IF_LedOn(MCU_ORANGE_LED_GPIO); - MAP_UtilsDelay(8000000); - GPIO_IF_LedOff(MCU_ORANGE_LED_GPIO); - MAP_UtilsDelay(8000000); - GPIO_IF_LedOn(MCU_GREEN_LED_GPIO); - MAP_UtilsDelay(8000000); - GPIO_IF_LedOff(MCU_GREEN_LED_GPIO); - } - -} -//***************************************************************************** -// -//! Board Initialization & Configuration -//! -//! \param None -//! -//! \return None -// -//***************************************************************************** -static void -BoardInit(void) -{ -/* In case of TI-RTOS vector table is initialize by OS itself */ -#ifndef USE_TIRTOS - // - // Set vector table base - // -#if defined(ccs) - MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]); -#endif -#if defined(ewarm) - MAP_IntVTableBaseSet((unsigned long)&__vector_table); -#endif -#endif - - // - // Enable Processor - // - MAP_IntMasterEnable(); - MAP_IntEnable(FAULT_SYSTICK); - - PRCMCC3200MCUInit(); -} -//**************************************************************************** -// -//! Main function -//! -//! \param none -//! -//! This function -//! 1. Invokes the LEDBlinkyTask -//! -//! \return None. -// -//**************************************************************************** -int -main() -{ - // - // Initialize Board configurations - // - BoardInit(); - - // - // Power on the corresponding GPIO port B for 9,10,11. - // Set up the GPIO lines to mode 0 (GPIO) - // - PinMuxConfig(); - GPIO_IF_LedConfigure(LED1|LED2|LED3); - - GPIO_IF_LedOff(MCU_ALL_LED_IND); - - // - // Start the LEDBlinkyRoutine - // - LEDBlinkyRoutine(); - return 0; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** From da31df65acf1cb170e3039251538dda807975fc5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 6 Feb 2019 16:46:14 +0000 Subject: [PATCH 04/90] Add process of TI Simplelink SDK to main CMake --- CMakeLists.txt | 103 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index d1395aad37..7c07acad4c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -629,6 +629,109 @@ endif() ################################################################# + +################################################################# +# handling TI Simplelink CC32xx SDK + +# check if TI_SL_CC32xx_SDK_SOURCE was specified or if it's empty (default is empty) +set(NO_TI_SL_CC32xx_SDK_SOURCE TRUE) +if(TI_SL_CC32xx_SDK_SOURCE) + if(NOT "${TI_SL_CC32xx_SDK_SOURCE}" STREQUAL "") + set(NO_TI_SL_CC32xx_SDK_SOURCE FALSE) + endif() +endif() + +if(NO_TI_SL_CC32xx_SDK_SOURCE) + # no TI Simplelink CC32xx SDK source specified, download it from it's repo + + # hack to make the FindGit to work in Windows platforms (check the module comment for details) + include(Hack_SetGitSearchPath) + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + message(STATUS "TI Simplelink CC32xx SDK (latest available code from v2.40.01.01") + set(TI_SL_CC32xx_SDK_TAG "2.40.01.01") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download/CMakeLists.txt") + + # setup CMake project for TI Simplelink CC32xx SDK download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download") + + # run build on TI Simplelink CC32xx SDK download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download") + + # add TI Simplelink CC32xx SDK as external project + ExternalProject_Add( + SLCC32xxSDK + PREFIX SimpleLinkCC32xxSdk + SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source + GIT_REPOSITORY https://github.com/nanoframework/ChibiOS + GIT_TAG ${TI_SL_CC32xx_SDK_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for TI Simplelink CC32xx SDK CMake project + ExternalProject_Get_Property(SLCC32xxSDK SOURCE_DIR) + +else() + # TI Simplelink CC32xx SDK source was specified + + # sanity check is source path exists + if(EXISTS "${TI_SL_CC32xx_SDK_SOURCE}/") + message(STATUS "TI Simplelink CC32xx SDK source from: ${TI_SL_CC32xx_SDK_SOURCE}") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/TI_SL_CC32xx_SDK_SOURCE") + file(COPY "${TI_SL_CC32xx_SDK_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source") + else() + message(STATUS "Using local cache of TI Simplelink CC32xx SDK source from ${TI_SL_CC32xx_SDK_SOURCE}") + endif() + + set(SLCC32xxSDK_INCLUDE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdkS_Source/include) + else() + message(FATAL_ERROR "Couldn't find TI Simplelink CC32xx SDK source at ${TI_SL_CC32xx_SDK_SOURCE}/") + endif() + + # add TI Simplelink CC32xx SDK as external project + ExternalProject_Add( + SLCC32xxSDK + PREFIX SimpleLinkCC32xxSdk + SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for TI Simplelink CC32xx SDK CMake project + ExternalProject_Get_Property(SLCC32xxSDK SOURCE_DIR) + +endif() + +################################################################# + + ####################### # ChibiOS if(RTOS_CHIBIOS_CHECK) From ebe2eb38eceaf14e685784d35563d8eb1de19dd7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 6 Feb 2019 16:51:56 +0000 Subject: [PATCH 05/90] Add skeleton for TI_CC3220SF_LAUNCHXL target MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/CMakeLists.txt | 250 ++++++++++++++++++ .../common/CMakeLists.txt | 11 + .../common/Device_BlockStorage-DEBUG.c | 102 +++++++ .../common/Device_BlockStorage.c | 102 +++++++ .../nanoCLR/CC3220SF_CLR.ld | 129 +++++++++ .../nanoCLR/CMakeLists.txt | 11 + .../TI_CC3220SF_LAUNCHXL/nanoCLR/main.c | 107 ++++++++ .../TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp | 12 + .../nanoCLR/target_board.h.in | 19 ++ .../TI_CC3220SF_LAUNCHXL/target_common.c | 24 ++ .../TI_CC3220SF_LAUNCHXL/target_common.h.in | 36 +++ 11 files changed, 803 insertions(+) create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/CMakeLists.txt create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.c create mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.h.in diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/CMakeLists.txt b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/CMakeLists.txt new file mode 100644 index 0000000000..edea1a2e31 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/CMakeLists.txt @@ -0,0 +1,250 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +# configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" +# "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +# set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# # nF feature: networking +# if(USE_NETWORKING_OPTION) +# find_package(CHIBIOS_LWIP REQUIRED) +# find_package(NF_NETWORKING REQUIRED) +# endif() + +# # nF feature: filesystem +# if(USE_FILESYSTEM_OPTION) +# find_package(CHIBIOS_FATFS REQUIRED) +# endif() + +# # security provider is mbedTLS +# if(NF_SECURITY_MBEDTLS) +# find_package(mbedTLS REQUIRED) +# endif() + +####################################### + +add_subdirectory("common") +# add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +# add_executable( +# # executables for project, project sources +# ${NANOBOOTER_PROJECT_NAME}.elf + +# "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + +# # need to add configuration manager to allow get/store configuration blocks +# "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager.c" + +# ${COMMON_PROJECT_SOURCES} +# ${NANOBOOTER_PROJECT_SOURCES} + +# ${TARGET_CMSIS_COMMON_SOURCES} +# ${TARGET_CMSIS_NANOBOOTER_SOURCES} + +# ${TARGET_CHIBIOS_COMMON_SOURCES} +# ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + +# ${CHIBIOS_SOURCES} +# ${ChibiOSnfOverlay_SOURCES} + +# ${WireProtocol_SOURCES} +# ) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + # ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + "${NF_CoreCLR_SOURCES}" + "${NF_Debugger_SOURCES}" + "${NF_Diagnostics_SOURCES}" + + # # sources for ChibiOS FatFS + # "${CHIBIOS_FATFS_SOURCES}" + + # # sources for nanoFramework Network LWIP, Sockets and TLS + # "${CHIBIOS_LWIP_SOURCES}" + # "${NF_Networking_SOURCES}" + # "${mbedTLS_SOURCES}" + + # sources for nanoFramework APIs + "${TARGET_NANO_APIS_SOURCES}" +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +# add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# # add dependencies from CHIBIOS_NETWORK_COMPONENTS (this is required to make sure that ChibiOS network components are unzip at the proper locations before the build starts) +# # only required if networking is ON +# if(USE_NETWORKING_OPTION) +# add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) +# add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) + +# # add dependency for security provider mbedTLS +# if(NF_SECURITY_MBEDTLS) +# add_dependencies(${NANOCLR_PROJECT_NAME}.elf mbedTLS) +# endif() +# endif() + +# # add dependencies from CHIBIOS_FILESYSTEM_COMPONENTS (this is required to make sure that ChibiOS filesystem components are unzip at the proper locations before the build starts) +# # only required if filesystem is ON +# if(USE_FILESYSTEM_OPTION) +# add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) +# add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) +# endif() + +# include common directories +include_directories( + "${CMAKE_CURRENT_BINARY_DIR}" + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# # include directories for nanoBooter +# target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC +# "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" +# ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + +# ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} +# ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} + +# # includes for ChibiOS LwIP +# "${CHIBIOS_LWIP_INCLUDE_DIRS}" +# ) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + "${NF_CoreCLR_INCLUDE_DIRS}" + "${NF_Debugger_INCLUDE_DIRS}" + "${NF_Diagnostics_INCLUDE_DIRS}" + + # includes for nanoFramework APIs + "${TARGET_NANO_APIS_INCLUDES}" + + # # includes for ChibiOS FatFS + # "${CHIBIOS_FATFS_INCLUDE_DIRS}" + + # # includes for ChibiOS LwIP + # "${CHIBIOS_LWIP_INCLUDE_DIRS}" + + # # incudes for Networking and TLS + # "${NF_Networking_INCLUDE_DIRS}" + # "${mbedTLS_INCLUDE_DIRS}" +) + +# set compiler options +# nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# # mbed TLS requires a config file +# if(NF_SECURITY_MBEDTLS) +# # this seems to be only option to properly set a compiler define through the command line that needs to be a string literal +# SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${CMAKE_CURRENT_SOURCE_DIR}/mbedtls_config.h>\"") +# endif() + +# set compiler definitions +# nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + # nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F76xx_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/CC3220SF_CLR-DEBUG.ld) +else() + # nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F76xx_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/CC3220SF_CLR.ld) +endif() + +# set linker options +# nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +# set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x1800") + +# generate output files +# nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt new file mode 100644 index 0000000000..8a93289ea7 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +# list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 0000000000..d72e90abd0 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,102 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 6 } // 080C0000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c new file mode 100644 index 0000000000..0e39196da2 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c @@ -0,0 +1,102 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 0x08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 } // 08080000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld new file mode 100644 index 0000000000..4e27091060 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld @@ -0,0 +1,129 @@ +/***************************************************************************** +* blinky.ld +* +* GCC Linker script for blinky application. +* +* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +/* +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * CC3220SF generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x01000800, len = 0x0FF800 /* flash size less the space reserved for application deployment*/ + flash_itcm : org = 0x00000000, len = 0 + deployment : org = 0x01000800, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 0x00040000 /* SRAM */ + ram1 : org = 0x00000000, len = 0 /* */ + ram2 : org = 0x00000000, len = 0 /* */ + ram3 : org = 0x00000000, len = 0 /* */ + ram4 : org = 0x00000000, len = 0 /* */ + ram5 : org = 0x00000000, len = 0 /* */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..c61dda6ef2 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c new file mode 100644 index 0000000000..8961dc1f25 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c @@ -0,0 +1,107 @@ + +// // Simplelink includes +// #include "simplelink.h" + +// // Driverlib includes +// #include "hw_types.h" +// #include "hw_ints.h" +// #include "hw_memmap.h" +// #include "hw_common_reg.h" +// #include "interrupt.h" +// #include "hw_apps_rcm.h" +// #include "prcm.h" +// #include "rom.h" +// #include "rom_map.h" +// #include "prcm.h" +// #include "gpio.h" +// #include "utils.h" + +// //Free_rtos/ti-rtos includes +// #include "osi.h" + +// // Common interface includes +// #include "gpio_if.h" +// #include "common.h" +// #include "pinmux.h" + + +void BlinkerThread(void const * argument) +{ + (void)argument; + + // palSetLineMode(1, PAL_MODE_OUTPUT_PUSHPULL); + + + // loop until thread receives a request to terminate + while (!chThdShouldTerminateX()) { + + // palSetPad(GPIOD, GPIOD_LED3); + // osDelay(500); + // palClearPad(GPIOD, GPIOD_LED3); + // osDelay(500); + + } + // nothing to deinitialize or cleanup, so it's safe to return +} +osThreadDef(BlinkerThread, osPriorityNormal, 128, "BlinkerThread"); + +// Application entry point. +int main(void) { + + osThreadId blinkerThreadId; + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + +// // init SWO as soon as possible to make it available to output ASAP +// #if (SWO_OUTPUT == TRUE) +// SwoInit(); +// #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + +// // the following IF is not mandatory, it's just providing a way for a user to 'force' +// // the board to remain in nanoBooter and not launching nanoCLR + +// // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter +// // the user button in this board has a pull-up resistor so the check has to be inverted +// if (palReadPad(GPIOA, GPIOA_BUTTON)) +// { +// // check for valid CLR image +// if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) +// { +// // there seems to be a valid CLR image +// // launch nanoCLR +// LaunchCLR((uint32_t)&__nanoImage_end__); +// } +// } + +// // Initializes a serial-over-USB CDC driver. +// sduObjectInit(&SDU1); +// sduStart(&SDU1, &serusbcfg); + +// // Activates the USB driver and then the USB bus pull-up on D+. +// // Note, a delay is inserted in order to not have to disconnect the cable after a reset. +// usbDisconnectBus(serusbcfg.usbp); +// chThdSleepMilliseconds(1500); +// usbStart(serusbcfg.usbp, &usbcfg); +// usbConnectBus(serusbcfg.usbp); + + // Creates the blinker thread, it does not start immediately. + blinkerThreadId = osThreadCreate(osThread(BlinkerThread), NULL); + +// // create the receiver thread +// receiverThreadId = osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // Normal main() thread + while (true) { + osDelay(500); + } +} diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..076a50fc68 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..2a7e8d2e8c --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.c b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.c new file mode 100644 index 0000000000..948e58f1fb --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0,//ConvertCOM_DebugHandle(0), + 115200, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.h.in b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.h.in new file mode 100644 index 0000000000..ee8cc5cf39 --- /dev/null +++ b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.h.in @@ -0,0 +1,36 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00040000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x01000800) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x000FF800) + +///////////////////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ From 1f36712750374a78a2157f04b3240512dc644d0d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 7 Feb 2019 16:36:25 +0000 Subject: [PATCH 06/90] Further work with CC3220 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Update CMakes to process new RTOS option: TI_SIMPLELINK. - Add CMakes with GCC options, toolchain and sources for this RTOS and CC32xx series. - Add new target TI_CC3220SF_LAUNCHXL. - Update CMakes accordingly. - Add new options to cmake-variants template. - Clean up TI-RTOS. - Remove target TI_CC3200 from old attempt with that chip. Signed-off-by: José Simões --- CMake/FreeRTOS.CMakeLists.cmake.in | 2 +- CMake/Modules/FindTI_SimpleLink.cmake | 116 +++ .../TI_SimpleLink_CC32xx_GCC_options.cmake | 48 + .../TI_SimpleLink_CC32xx_sources.cmake | 159 +++ CMake/TI_SimpleLink_target_os.h.in | 25 + CMake/toolchain.TI_SimpleLink.GCC.cmake | 174 ++++ CMakeLists.txt | 352 +++++-- cmake-variants.TEMPLATE.json | 11 +- .../TI_CC3200_LAUNCHPAD/CMakeLists.txt | 190 ---- .../ChibiOS/TI_CC3200_LAUNCHPAD/board.c | 23 - .../ChibiOS/TI_CC3200_LAUNCHPAD/board.h | 32 - .../TI_CC3200_LAUNCHPAD/common/CMakeLists.txt | 11 - .../common/Device_BlockStorage.c | 95 -- .../TI_CC3200_LAUNCHPAD/heap_useNewlib.c | 156 --- .../nanoBooter/CMakeLists.txt | 4 - .../nanoCLR/CMakeLists.txt | 13 - .../TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld | 164 --- .../TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h | 516 ---------- .../TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h | 384 ------- .../TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h | 20 - .../TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c | 112 -- .../TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c | 964 ------------------ .../TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h | 76 -- .../TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h | 9 - .../TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.c | 91 -- .../TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.h | 49 - .../nanoCLR/target_board.h.in | 19 - .../ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c | 791 -------------- .../TI_CC3200_LAUNCHPAD/target_common.c | 31 - .../TI_CC3200_LAUNCHPAD/target_common.h.in | 33 - .../TI_CC3220SF_LAUNCHXL/CMakeLists.txt | 250 ----- .../nanoCLR/CC3220SF_CLR.ld | 129 --- .../TI_CC3220SF_LAUNCHXL/nanoCLR/main.c | 107 -- targets/TI-RTOS/common/include/target_types.h | 101 -- .../TI_CC3220SF_LAUNCHXL/CMakeLists.txt | 129 +++ .../TI_CC3220SF_LAUNCHXL/FreeRTOSConfig.h | 207 ++++ .../common/CMakeLists.txt | 0 .../common/Device_BlockStorage-DEBUG.c | 0 .../common/Device_BlockStorage.c | 0 .../nanoCLR/CC3220SF_CLR-DEBUG.ld | 142 +++ .../nanoCLR/CC3220SF_CLR.ld | 142 +++ .../nanoCLR/CMakeLists.txt | 2 +- .../TI_CC3220SF_LAUNCHXL/nanoCLR/main.c | 373 +++++++ .../TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp | 0 .../nanoCLR/target_board.h.in | 0 .../TI_CC3220SF_LAUNCHXL/target_common.c | 0 .../TI_CC3220SF_LAUNCHXL/target_common.h.in | 0 47 files changed, 1762 insertions(+), 4490 deletions(-) create mode 100644 CMake/Modules/FindTI_SimpleLink.cmake create mode 100644 CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake create mode 100644 CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake create mode 100644 CMake/TI_SimpleLink_target_os.h.in create mode 100644 CMake/toolchain.TI_SimpleLink.GCC.cmake delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/CMakeLists.txt delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.c delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.h delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/CMakeLists.txt delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/Device_BlockStorage.c delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/heap_useNewlib.c delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoBooter/CMakeLists.txt delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/CMakeLists.txt delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.c delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.h delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/target_board.h.in delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.c delete mode 100644 targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.h.in delete mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/CMakeLists.txt delete mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld delete mode 100644 targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c delete mode 100644 targets/TI-RTOS/common/include/target_types.h create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/FreeRTOSConfig.h rename targets/{FreeRTOS => TI-SimpleLink}/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt (100%) rename targets/{FreeRTOS => TI-SimpleLink}/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c (100%) rename targets/{FreeRTOS => TI-SimpleLink}/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c (100%) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld rename targets/{FreeRTOS => TI-SimpleLink}/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt (80%) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c rename targets/{FreeRTOS => TI-SimpleLink}/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp (100%) rename targets/{FreeRTOS => TI-SimpleLink}/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in (100%) rename targets/{FreeRTOS => TI-SimpleLink}/TI_CC3220SF_LAUNCHXL/target_common.c (100%) rename targets/{FreeRTOS => TI-SimpleLink}/TI_CC3220SF_LAUNCHXL/target_common.h.in (100%) diff --git a/CMake/FreeRTOS.CMakeLists.cmake.in b/CMake/FreeRTOS.CMakeLists.cmake.in index 1b13613219..585659714b 100644 --- a/CMake/FreeRTOS.CMakeLists.cmake.in +++ b/CMake/FreeRTOS.CMakeLists.cmake.in @@ -9,7 +9,7 @@ ExternalProject_Add( FreeRTOS PREFIX FreeRTOS SOURCE_DIR ${CMAKE_BINARY_DIR}/FreeRTOS_Source - SVN_REPOSITORY ${FREERTOS_SVN_REPOSITORY}/FreeRTOS/Source + SVN_REPOSITORY https://svn.code.sf.net/p/freertos/code/tags/${FREERTOS_VERSION_TAG}/FreeRTOS/Source/ TIMEOUT 10 LOG_DOWNLOAD 1 # Disable all other steps diff --git a/CMake/Modules/FindTI_SimpleLink.cmake b/CMake/Modules/FindTI_SimpleLink.cmake new file mode 100644 index 0000000000..16d9d4280a --- /dev/null +++ b/CMake/Modules/FindTI_SimpleLink.cmake @@ -0,0 +1,116 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################################################################################### +# WHEN ADDING A NEW series add the respective name to the list bellow along with the CMake files with GCC options and source files +################################################################################################################################### + +# check if the series name is supported + +set(TI_SIMPLELINK_SUPPORTED_SERIES "CC32xx" CACHE INTERNAL "supported TI series names") + +list(FIND TI_SIMPLELINK_SUPPORTED_SERIES ${TARGET_SERIES} TARGET_SERIES_NAME_INDEX) +if(TI_SIMPLELINK_SUPPORTED_SERIES EQUAL -1) + if(TARGET_SERIES_NAME_INDEX EQUAL -1) + message(FATAL_ERROR "\n\nSorry but ${TARGET_SERIES} is not supported at this time...\nYou can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") + else() + # series is supported by TI + set(TARGET_VENDOR "TI" CACHE INTERNAL "target vendor is TI") + endif() +endif() + +# including here the CMake files for the source files specific to the target series +include(TI_SimpleLink_${TARGET_SERIES}_sources) + +# and here the GCC options tuned for the target series +include(TI_SimpleLink_${TARGET_SERIES}_GCC_options) + +# includes for FreeRTOS +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/FreeRTOS_Source/include") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/FreeRTOS_Source/portable/GCC/ARM_CM3") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${TARGET_BASE_LOCATION}") + +# source files for FreeRTOS +set(FreeRTOS_SRCS + + # FreeRTOS + croutine.c + event_groups.c + list.c + queue.c + stream_buffer.c + tasks.c + timers.c + port.c + heap_4.c + clock.c + memory.c + mqueue.c + pthread_barrier.c + pthread_cond.c + pthread.c + pthread_mutex.c + pthread_rwlock.c + sched.c + semaphore.c + sleep.c + timer.c + PTLS.c + aeabi_portable.c + ClockP_freertos.c + DebugP_freertos.c + MutexP_freertos.c + SemaphoreP_freertos.c + SystemP_freertos.c + HwiPCC32XX_freertos.c + PowerCC32XX_freertos.c + startup_cc32xx_gcc.c + +) + +foreach(SRC_FILE ${FreeRTOS_SRCS}) + set(FreeRTOS_SCR_FILE SRC_FILE -NOTFOUND) + find_file(FreeRTOS_SCR_FILE ${SRC_FILE} + PATHS + + # FreeRTOS + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/posix/freertos" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/source" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/kernel/freertos/dpl" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/kernel/freertos/startup" + "${PROJECT_BINARY_DIR}/FreeRTOS_Source/portable/MemMang" + "${PROJECT_BINARY_DIR}/FreeRTOS_Source/portable/GCC/ARM_CM3" + "${PROJECT_BINARY_DIR}/FreeRTOS_Source" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${FreeRTOS_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${FreeRTOS_SCR_FILE}) +endforeach() + +# other source files +set(Other_SRCS + + # board files + CC3220SF_LAUNCHXL.c + +) + +foreach(SRC_FILE ${Other_SRCS}) + set(Other_SCR_FILE SRC_FILE -NOTFOUND) + find_file(Other_SCR_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/boards/CC3220SF_LAUNCHXL" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Other_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${Other_SCR_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(TI_SimpleLink DEFAULT_MSG TI_SimpleLink_INCLUDE_DIRS TI_SimpleLink_SOURCES) diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake new file mode 100644 index 0000000000..df67197cf2 --- /dev/null +++ b/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake @@ -0,0 +1,48 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options bellow +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +# -mfpu=fpv5-sp-d16 +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--print-memory-usage -mcpu=cortex-m4 -march=armv7e-m -mthumb -nostartfiles -std=c99 -mfloat-abi=soft -ffunction-sections -fdata-sections -g -gstrict-dwarf -Wall " CACHE INTERNAL "executable linker flags") + + +function(NF_SET_COMPILER_OPTIONS TARGET) + + # include any extra options comming from any extra args? + target_compile_options(${TARGET} PUBLIC ${ARGN} -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -mabi=aapcs -gstrict-dwarf -nostdlib -Wall -w -static -ffunction-sections -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -mstructure-size-boundary=8 -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) + + # this series has FPU + target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=TRUE) + +endfunction() + + +function(NF_SET_LINKER_OPTIONS TARGET) + + # request specs from newlib nano + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") + + # set extra linker flags + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # set optimization flags + nf_set_optimization_options(${TARGET}) + + # set link map + nf_set_link_map(${TARGET}) + +endfunction() diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake new file mode 100644 index 0000000000..4280edbfb1 --- /dev/null +++ b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake @@ -0,0 +1,159 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# includes for SimpleLink CC32xx SDK +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/posix/gcc") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/boards/CC3220SF_LAUNCHXL") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx/driverlib") + +# source files for board drivers +set(BoardDrivers_SRCS + + # board drivers + # NVS.c + # NVSRAM.c + # NVSSPI25X.c + # SD.c + # SDSPI.c + # SDFatFS.c + List.c + RingBuf.c + ADC.c + ADCCC32XX.c + # Camera.c + # CameraCC32XXDMA.c + Capture.c + CaptureCC32XX.c + CryptoCC32XX.c + UDMACC32XX.c + GPIOCC32XX.c + I2C.c + I2CCC32XX.c + I2S.c + I2SCC32XXDMA.c + PowerCC32XX.c + PowerCC32XX_asm.sm4g + PWM.c + PWMTimerCC32XX.c + SDHostCC32XX.c + SPI.c + SPICC32XXDMA.c + SPICC32XXDMA.c + Timer.c + TimerCC32XX.c + UART.c + UARTCC32XX.c + UARTCC32XXDMA.c + Watchdog.c + WatchdogCC32XX.c +) + +foreach(SRC_FILE ${BoardDrivers_SRCS}) + set(BoardDrivers_SCR_FILE SRC_FILE -NOTFOUND) + find_file(BoardDrivers_SCR_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/nvs" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/sd" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/adc" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/camera" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/capture" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/crypto" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/dma" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/gpio" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/i2c" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/i2s" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/power" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/pwm" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/sd" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/spi" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/timer" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/uart" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/watchdog" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/utils" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${BoardDrivers_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${BoardDrivers_SCR_FILE}) +endforeach() + +# need to specify a language for this assembler source file because its not using a standard extension +set_source_files_properties("${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/power/PowerCC32XX_asm.sm4g" PROPERTIES LANGUAGE ASM) + +# source files for drivers library +set(DriversLibrary_SRCS + + #drivers library + adc.c + aes.c + camera.c + cpu.c + crc.c + des.c + flash.c + gpio.c + hwspinlock.c + i2c.c + interrupt.c + i2s.c + pin.c + prcm.c + sdhost.c + shamd5.c + spi.c + systick.c + timer.c + uart.c + udma.c + utils.c + wdt.c + + # display specific + DisplayUart.c +) + +foreach(SRC_FILE ${DriversLibrary_SRCS}) + set(DriversLibrary_SCR_FILE SRC_FILE -NOTFOUND) + find_file(DriversLibrary_SCR_FILE ${SRC_FILE} + PATHS + + #drivers library + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx/driverlib" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/display" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${DriversLibrary_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${DriversLibrary_SCR_FILE}) +endforeach() + +# other source files +set(Other_SRCS + + # board files + CC3220SF_LAUNCHXL.c + +) + +foreach(SRC_FILE ${Other_SRCS}) + set(Other_SCR_FILE SRC_FILE -NOTFOUND) + find_file(Other_SCR_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/boards/CC3220SF_LAUNCHXL" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Other_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${Other_SCR_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(SimpleLinkCC32xxSDK DEFAULT_MSG TI_SimpleLink_INCLUDE_DIRS TI_SimpleLink_SOURCES) diff --git a/CMake/TI_SimpleLink_target_os.h.in b/CMake/TI_SimpleLink_target_os.h.in new file mode 100644 index 0000000000..577c2e33cf --- /dev/null +++ b/CMake/TI_SimpleLink_target_os.h.in @@ -0,0 +1,25 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_OS_H_ +#define _TARGET_OS_H_ + +#define VERSION_MAJOR @nanoFramework_VERSION_MAJOR@U +#define VERSION_MINOR @nanoFramework_VERSION_MINOR@U +#define VERSION_BUILD @nanoFramework_VERSION_PATCH@U +#define VERSION_REVISION @nanoFramework_VERSION_TWEAK@U + +#define DP_FLOATINGPOINT @TARGET_DP_FLOATINGPOINT@ + +#define SUPPORT_ANY_BASE_CONVERSION @TARGET_SUPPORT_ANY_BASE_CONVERSION@ + +#define HAS_CONFIG_BLOCK @TARGET_HAS_CONFIG_BLOCK@ + +#endif /* _TARGET_OS_H_ */ diff --git a/CMake/toolchain.TI_SimpleLink.GCC.cmake b/CMake/toolchain.TI_SimpleLink.GCC.cmake new file mode 100644 index 0000000000..4f3d8284a0 --- /dev/null +++ b/CMake/toolchain.TI_SimpleLink.GCC.cmake @@ -0,0 +1,174 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +INCLUDE(CMakeForceCompiler) + +################################################### +# set C and C++ flags for compiler detection tests +################################################### +# IMPORTANT: these flags need to be removed after +# the compiler detection otherwise they'll get +# added to all compiler build calls and +# will colide with the use of nano.specs +################################################### +set(CMAKE_C_FLAGS_INIT "-specs=nosys.specs") +set(CMAKE_CXX_FLAGS_INIT "-specs=nosys.specs") +################################################### + + +# set toolchain directories +set(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_PREFIX}/bin) +set(TOOLCHAIN_INC_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/include) +set(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/lib) + +# the name of the operating system for which CMake is to build +set(CMAKE_SYSTEM_NAME Generic) + +# name of the CPU CMake is building for +set(CMAKE_SYSTEM_PROCESSOR arm) + +# macro to setup compilers +macro(SET_COMPILER_VAR var name) + find_program(CMAKE_${var} arm-none-eabi-${name} HINTS ${TOOLCHAIN_BIN_DIR} DOC "${name} tool") +endmacro() + +# setup C compiler +if(NOT CMAKE_C_COMPILER) + SET_COMPILER_VAR(C_COMPILER gcc) +endif() + +# setup C++ compiler +if(NOT CMAKE_CXX_COMPILER) + SET_COMPILER_VAR(CXX_COMPILER g++) +endif() + +# setup Assembler compiler +SET_COMPILER_VAR(ASM-ATT_COMPILER as) + +# other toolchain configurations +set(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objcopy CACHE INTERNAL "objcopy tool") +set(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objdump CACHE INTERNAL "objdump tool") +set(CMAKE_SIZE ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-size CACHE INTERNAL "size tool") +set(CMAKE_DEBUGER ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-gdb CACHE INTERNAL "debuger") + +# root paths to search on the filesystem for cross-compiling +set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_PREFIX}/arm-none-eabi ${EXTRA_FIND_PATH}) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +# set required C and C++ standard for ALL targets +set(CMAKE_C_STANDARD 11 CACHE INTERNAL "C standard for all targets") +set(CMAKE_CXX_STANDARD 11 CACHE INTERNAL "C++ standard for all targets") + +# set all C and C++ extensions to be OFF on ALL targets +# this forces the use of -std=c11 and -std=c++11 instead of -std=gnu11 and -std=gnu++11 +set(CMAKE_C_EXTENSIONS OFF CACHE INTERNAL "C compiler extensions OFF") +set(CMAKE_CXX_EXTENSIONS OFF CACHE INTERNAL "C++ compiler extensions OFF") + + +function(NF_ADD_HEX_BIN_DUMP_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + + # add targets for HEX, BIN and S19 formats with no output so they will always be built + add_custom_target(${TARGET}.hex DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Oihex ${FILENAME} ${FILENAME}.hex) + add_custom_target(${TARGET}.s19 DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Osrec ${FILENAME} ${FILENAME}.s19) + add_custom_target(${TARGET}.bin DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Obinary ${FILENAME} ${FILENAME}.bin) + add_custom_target(${TARGET}.dump DEPENDS ${TARGET} COMMAND ${CMAKE_OBJDUMP} -d -EL -S ${FILENAME} ${FILENAME}.dump) +endfunction() + + +function(NF_PRINT_SIZE_OF_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} -A -x ${FILENAME}) +endfunction() + + +function(NF_SET_OPTIMIZATION_OPTIONS TARGET) + + target_compile_options(${TARGET} PRIVATE + $<$:-Og -femit-class-debug-always -g3 -ggdb> + $<$:-O3 -flto -fuse-linker-plugin -fno-fat-lto-objects> + $<$:-Os -flto -fuse-linker-plugin -fno-fat-lto-objects> + $<$:-Os -femit-class-debug-always -g3 -ggdb> + ) + +endfunction() + + +function(NF_SET_LINK_MAP TARGET) + + # need to remove the .elf suffix from target name + string(FIND ${TARGET} "." TARGET_EXTENSION_DOT_INDEX) + string(SUBSTRING ${TARGET} 0 ${TARGET_EXTENSION_DOT_INDEX} TARGET_SHORT) + + # add linker flags to generate map file + set_property(TARGET ${TARGET_SHORT}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=${PROJECT_SOURCE_DIR}/build/${TARGET_SHORT}.map") + +endfunction() + + +function(NF_SET_COMPILER_DEFINITIONS TARGET) + + # definition for platform + # (always ARM here) + target_compile_definitions(${TARGET} PUBLIC "-DPLATFORM_ARM ") + + # definitions required for SimpleLink CC32xx SDK + target_compile_definitions(${TARGET} PUBLIC -Dgcc -DPTLS_TLS_INDEX=0 -DBOARD_DISPLAY_USE_UART_ANSI=0 -DBOARD_DISPLAY_USE_LCD=0 -DconfigNUM_THREAD_LOCAL_STORAGE_POINTERS=1) + + # build types that have debugging capabilities AND are NOT RTM have to have the define 'NANOCLR_ENABLE_SOURCELEVELDEBUGGING' + if((NOT NF_BUILD_RTM) OR NF_FEATURE_DEBUGGER) + target_compile_definitions(${TARGET} PUBLIC "-DNANOCLR_ENABLE_SOURCELEVELDEBUGGING ") + endif() + + # set compiler definition for RTM build option + if(NF_BUILD_RTM) + target_compile_definitions(${TARGET} PUBLIC -DBUILD_RTM) + endif() + + # set compiler definition for using Application Domains feature + if(NF_FEATURE_USE_APPDOMAINS) + target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_USE_APPDOMAINS) + endif() + + # set compiler definition for implementing (or not) CRC32 in Wire Protocol + if(NF_WP_IMPLEMENTS_CRC32) + target_compile_definitions(${TARGET} PUBLIC -DWP_IMPLEMENTS_CRC32) + endif() + + # set definition for Wire Protocol trace mask + target_compile_definitions(${TARGET} PUBLIC -DTRACE_MASK=${WP_TRACE_MASK}) + + # set compiler definition regarding inclusion of trace messages and checks on CLR + if(NF_PLATFORM_NO_CLR_TRACE) + target_compile_definitions(${TARGET} PUBLIC -DPLATFORM_NO_CLR_TRACE=1) + endif() + + # set compiler definition regarding CLR IL inlining + if(NF_CLR_NO_IL_INLINE) + target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_NO_IL_INLINE=1) + endif() + + # include any extra compiler definitions comming from extra args + target_compile_definitions(${TARGET} PUBLIC ${ARGN}) + +endfunction() + + +function(NF_SET_LINKER_FILE TARGET LINKER_FILE_NAME) + + # set linker file name + set_target_properties(${TARGET} PROPERTIES LINK_FLAGS "-T${LINKER_FILE_NAME}") + +endfunction() diff --git a/CMakeLists.txt b/CMakeLists.txt index 7c07acad4c..67f3b29019 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,7 +53,7 @@ endif() # list of supported RTOSes # when adding a new RTOS add the corresponding string bellow AND... # ... also on the compare block bellow -set(RTOS_SUPPORTED "CHIBIOS" "FREERTOS_ESP32" "TIRTOS" CACHE INTERNAL "supported RTOS options") +set(RTOS_SUPPORTED "CHIBIOS" "FREERTOS_ESP32" "TI_SIMPLELINK" CACHE INTERNAL "supported RTOS options") list(FIND RTOS_SUPPORTED ${RTOS} RTOS_INDEX) if(RTOS_INDEX EQUAL -1) @@ -63,27 +63,27 @@ else() endif() string(COMPARE EQUAL "CHIBIOS" "${RTOS}" RTOS_CHIBIOS_CHECK) -string(COMPARE EQUAL "FREERTOS_ESP32" "${RTOS}" RTOS_FREERTOS_CHECK) -string(COMPARE EQUAL "TIRTOS" "${RTOS}" RTOS_TIRTOS_CHECK) +string(COMPARE EQUAL "FREERTOS_ESP32" "${RTOS}" RTOS_FREERTOS_ESP32_CHECK) +string(COMPARE EQUAL "TI_SIMPLELINK" "${RTOS}" RTOS_TI_SIMPLELINK_CHECK) ########################################################################## if(RTOS_FREERTOS_ESP32_CHECK) set(RTOS_FREERTOS_ESP32_CHECK TRUE) + set(RTOS_TI_SIMPLELINK_CHECK FALSE) set(RTOS_CHIBIOS_CHECK FALSE) - set(RTOS_TIRTOS_CHECK FALSE) endif() if(RTOS_CHIBIOS_CHECK) set(RTOS_CHIBIOS_CHECK TRUE) set(RTOS_FREERTOS_ESP32_CHECK FALSE) - set(RTOS_TIRTOS_CHECK FALSE) + set(RTOS_TI_SIMPLELINK_CHECK FALSE) endif() -if(RTOS_TIRTOS_CHECK) - set(RTOS_CHIBIOS_CHECK FALSE) +if(RTOS_TI_SIMPLELINK_CHECK) + set(RTOS_TI_SIMPLELINK_CHECK TRUE) set(RTOS_FREERTOS_ESP32_CHECK FALSE) - set(RTOS_TIRTOS_CHECK TRUE) + set(RTOS_CHIBIOS_CHECK FALSE) endif() ####################### @@ -122,6 +122,10 @@ elseif(RTOS_FREERTOS_ESP32_CHECK) message(STATUS "\nSetting Toolchain file for FreeRTOS ESP32 \n") set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.FreeRtos.ESP32.${TOOLCHAIN}.cmake) +elseif(RTOS_TI_SIMPLELINK_CHECK) + message(STATUS "\nSetting Toolchain file for FreeRTOS CC32XX \n") + set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.TI_SimpleLink.${TOOLCHAIN}.cmake) + # else() # # find out the chip vendor in order to move on with the appropriate configuration @@ -629,109 +633,6 @@ endif() ################################################################# - -################################################################# -# handling TI Simplelink CC32xx SDK - -# check if TI_SL_CC32xx_SDK_SOURCE was specified or if it's empty (default is empty) -set(NO_TI_SL_CC32xx_SDK_SOURCE TRUE) -if(TI_SL_CC32xx_SDK_SOURCE) - if(NOT "${TI_SL_CC32xx_SDK_SOURCE}" STREQUAL "") - set(NO_TI_SL_CC32xx_SDK_SOURCE FALSE) - endif() -endif() - -if(NO_TI_SL_CC32xx_SDK_SOURCE) - # no TI Simplelink CC32xx SDK source specified, download it from it's repo - - # hack to make the FindGit to work in Windows platforms (check the module comment for details) - include(Hack_SetGitSearchPath) - - # check for Git (needed here for advanced warning to user if it's not installed) - find_package(Git) - - # check if Git was found, if not report to user and abort - if(NOT GIT_EXECUTABLE) - message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") - endif() - - message(STATUS "TI Simplelink CC32xx SDK (latest available code from v2.40.01.01") - set(TI_SL_CC32xx_SDK_TAG "2.40.01.01") - - # need to setup a separate CMake project to download the code from the GitHub repository - # otherwise it won't be available before the actual build step - configure_file("CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in" - "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download/CMakeLists.txt") - - # setup CMake project for TI Simplelink CC32xx SDK download - execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . - RESULT_VARIABLE result - WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download") - - # run build on TI Simplelink CC32xx SDK download CMake project to perform the download - execute_process(COMMAND ${CMAKE_COMMAND} --build . - RESULT_VARIABLE result - WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download") - - # add TI Simplelink CC32xx SDK as external project - ExternalProject_Add( - SLCC32xxSDK - PREFIX SimpleLinkCC32xxSdk - SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source - GIT_REPOSITORY https://github.com/nanoframework/ChibiOS - GIT_TAG ${TI_SL_CC32xx_SDK_TAG} # target specified branch - GIT_SHALLOW 1 # download only the tip of the branch, not the complete history - TIMEOUT 10 - LOG_DOWNLOAD 1 - - # Disable all other steps - INSTALL_COMMAND "" - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - ) - - # get source dir for TI Simplelink CC32xx SDK CMake project - ExternalProject_Get_Property(SLCC32xxSDK SOURCE_DIR) - -else() - # TI Simplelink CC32xx SDK source was specified - - # sanity check is source path exists - if(EXISTS "${TI_SL_CC32xx_SDK_SOURCE}/") - message(STATUS "TI Simplelink CC32xx SDK source from: ${TI_SL_CC32xx_SDK_SOURCE}") - - # check if we already have the sources, no need to copy again - if(NOT EXISTS "${CMAKE_BINARY_DIR}/TI_SL_CC32xx_SDK_SOURCE") - file(COPY "${TI_SL_CC32xx_SDK_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source") - else() - message(STATUS "Using local cache of TI Simplelink CC32xx SDK source from ${TI_SL_CC32xx_SDK_SOURCE}") - endif() - - set(SLCC32xxSDK_INCLUDE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdkS_Source/include) - else() - message(FATAL_ERROR "Couldn't find TI Simplelink CC32xx SDK source at ${TI_SL_CC32xx_SDK_SOURCE}/") - endif() - - # add TI Simplelink CC32xx SDK as external project - ExternalProject_Add( - SLCC32xxSDK - PREFIX SimpleLinkCC32xxSdk - SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source - - # Disable all other steps - INSTALL_COMMAND "" - CONFIGURE_COMMAND "" - BUILD_COMMAND "" - ) - - # get source dir for TI Simplelink CC32xx SDK CMake project - ExternalProject_Get_Property(SLCC32xxSDK SOURCE_DIR) - -endif() - -################################################################# - - ####################### # ChibiOS if(RTOS_CHIBIOS_CHECK) @@ -1214,4 +1115,233 @@ elseif(RTOS_FREERTOS_ESP32_CHECK) endif() +####################### +# TI_SIMPLELINK +elseif(RTOS_TI_SIMPLELINK_CHECK) + + # set target base location + # this has to be set before the class library modules are pulled in + if(EXISTS ${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/${TI_BOARD}) + # set target base location + set(TARGET_BASE_LOCATION "${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/${TI_BOARD}") + message(STATUS "Support for target board '${TI_BOARD}' found") + else() + # board NOT found + # can't continue + message(FATAL_ERROR "\n\nSorry but support for ${TI_BOARD} target is not available...\n\nYou can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") + endif() + + if("${TARGET_SERIES}" STREQUAL "CC32xx") + + # CC32xx series is using TI SimpleLink CC32xx SDK and FreeRTOS + + # check if TI_SL_CC32xx_SDK_SOURCE was specified or if it's empty (default is empty) + set(NO_TI_SL_CC32xx_SDK_SOURCE TRUE) + if(TI_SL_CC32xx_SDK_SOURCE) + if(NOT "${TI_SL_CC32xx_SDK_SOURCE}" STREQUAL "") + set(NO_TI_SL_CC32xx_SDK_SOURCE FALSE) + endif() + endif() + + if(NO_TI_SL_CC32xx_SDK_SOURCE) + # no TI SimpleLink CC32xx SDK source specified, download it from our repo + + # hack to make the FindGit to work in Windows platforms (check the module comment for details) + include(Hack_SetGitSearchPath) + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + message(STATUS "TI SimpleLink CC32xx SDK (latest available code from v2.40.01.01") + set(TI_SL_CC32xx_SDK_TAG "2.40.01.01") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download/CMakeLists.txt") + + # setup CMake project for TI SimpleLink CC32xx SDK download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download") + + # run build on TI SimpleLink CC32xx SDK download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download") + + # add TI SimpleLink CC32xx SDK as external project + ExternalProject_Add( + SimpleLinkCC32xxSDK + PREFIX SimpleLinkCC32xxSdk + SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source + GIT_REPOSITORY https://github.com/nanoframework/ChibiOS + GIT_TAG ${TI_SL_CC32xx_SDK_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for TI SimpleLink CC32xx SDK CMake project + ExternalProject_Get_Property(SimpleLinkCC32xxSDK SOURCE_DIR) + + else() + # TI SimpleLink CC32xx SDK source was specified + + # sanity check is source path exists + if(EXISTS "${TI_SL_CC32xx_SDK_SOURCE}/") + message(STATUS "TI SimpleLink CC32xx SDK source from: ${TI_SL_CC32xx_SDK_SOURCE}") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/TI_SL_CC32xx_SDK_SOURCE") + file(COPY "${TI_SL_CC32xx_SDK_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source") + else() + message(STATUS "Using local cache of TI SimpleLink CC32xx SDK source from ${TI_SL_CC32xx_SDK_SOURCE}") + endif() + + set(SimpleLinkCC32xxSDK_INCLUDE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdkS_Source/ti/devices/cc32xx) + else() + message(FATAL_ERROR "Couldn't find TI SimpleLink CC32xx SDK source at ${TI_SL_CC32xx_SDK_SOURCE}/") + endif() + + # add TI SimpleLink CC32xx SDK as external project + ExternalProject_Add( + SimpleLinkCC32xxSDK + PREFIX SimpleLinkCC32xxSdk + SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for TI SimpleLink CC32xx SDK CMake project + ExternalProject_Get_Property(SimpleLinkCC32xxSDK SOURCE_DIR) + endif() + + # check if FREERTOS_SOURCE was specified or if it's empty (default is empty) + set(NO_FREERTOS_SOURCE TRUE) + if(FREERTOS_SOURCE) + if(NOT "${FREERTOS_SOURCE}" STREQUAL "") + set(NO_FREERTOS_SOURCE FALSE) + endif() + endif() + + if(NO_FREERTOS_SOURCE) + # no FreeRTOS source specified, download it from it's repo + + # check for SVN (needed here for advanced warning to user if it's not installed) + find_package(Subversion) + + # check if SVN was found, if not report to user and abort + if(NOT SUBVERSION_FOUND) + message(FATAL_ERROR "error: could not find SVN, make sure you have it installed.") + endif() + + # FreeRTOS version + set(FREERTOS_VERSION_EMPTY TRUE) + + # check if build was requested with a specifc FreeRTOS version + if(DEFINED FREERTOS_VERSION) + if(NOT "${FREERTOS_VERSION}" STREQUAL "") + set(FREERTOS_VERSION_EMPTY FALSE) + endif() + endif() + + # FreeRTOS version + set(FREERTOS_VERSION_EMPTY TRUE) + + # check if build was requested with a specifc FreeRTOS version + if(FREERTOS_VERSION_EMPTY) + # no FreeRTOS version actualy specified, must be empty which is fine, we'll default to a known good version + set(FREERTOS_VERSION_TAG "V10.1.1") + else() + # set SVN tag + set(FREERTOS_VERSION_TAG "${FREERTOS_VERSION}") + endif() + + message(STATUS "RTOS is: FreeRTOS ${FREERTOS_VERSION} from GitHub repo") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("CMake/FreeRTOS.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/FreeRTOS_Download/CMakeLists.txt") + + # setup CMake project for FreeRTOS download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/FreeRTOS_Download") + + # run build on FreeRTOS download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/FreeRTOS_Download") + + # add FreeRTOS as external project + ExternalProject_Add( + FreeRTOS + PREFIX FreeRTOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/FreeRTOS_Source + SVN_REPOSITORY https://svn.code.sf.net/p/freertos/code/tags/${FREERTOS_VERSION_TAG}/FreeRTOS/Source/ + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + else() + # FreeRTOS source was specified + + # sanity check is source path exists + if(EXISTS "${FREERTOS_SOURCE}/") + message(STATUS "RTOS is: FreeRTOS (source from: ${FREERTOS_SOURCE})") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/FreeRTOS_Source") + file(COPY "${FREERTOS_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/FreeRTOS_Source") + else() + message(STATUS "Using local cache of FreeRTOS source from ${FREERTOS_SOURCE}") + endif() + + set(FREERTOS_INCLUDE_DIR ${CMAKE_BINARY_DIR}/FreeRTOS_Source/include) + else() + message(FATAL_ERROR "Couldn't find FreeRTOS source at ${FREERTOS_SOURCE}/") + endif() + + # add FreeRTOS as external project + ExternalProject_Add( + FreeRTOS + PREFIX FreeRTOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/FreeRTOS_Source + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for FreeRTOS CMake project + ExternalProject_Get_Property(FreeRTOS SOURCE_DIR) + + endif() + + # Define base path for the class libraries + set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/${TI_BOARD}/nanoCLR") + + add_subdirectory(targets/TI-SimpleLink/${TI_BOARD}) + + endif() + endif() diff --git a/cmake-variants.TEMPLATE.json b/cmake-variants.TEMPLATE.json index 0979011a61..ec0f6d922b 100644 --- a/cmake-variants.TEMPLATE.json +++ b/cmake-variants.TEMPLATE.json @@ -34,22 +34,19 @@ "BUILD_VERSION" : "0.9.99.999", "TOOLCHAIN_PREFIX" : "", "TOOL_HEX2DFU_PREFIX" : "", - "TI_CC3200_SDK_PATH" : "", - "TI_XDCTOOLS_INSTALLATION_DIR" : "", - "TIRTOS_BIOS_INSTALLATION_DIR" : "", - "TIRTOS_UIA_INSTALLATION_DIR" : "", - "TARGET_SERIES" : "", "ESP32_IDF_PATH" : "/esp-idf", "ESP32_LIBS_PATH" : "/libs", - "TARGET_SERIES" : "", + "TARGET_SERIES" : "", "USE_RNG" : "", "DP_FLOATINGPOINT" : "", "SUPPORT_ANY_BASE_CONVERSION" : "", - "RTOS" : "", + "RTOS" : "", "CHIBIOS_SOURCE" : "", "CHIBIOS_CONTRIB_REQUIRED" : "OFF-default-ON-to-include_ChibiOS-Contrib-repository-in-the-build", "CHIBIOS_CONTRIB_SOURCE" : "", "CHIBIOS_BOARD" : "", + "TI_BOARD" : "", + "TI_SL_CC32xx_SDK_SOURCE" : "", "SWO_OUTPUT" : "OFF-default-ON-to-enable-ARM-CortexM-Single-Wire-Output", "NF_BUILD_RTM" : "OFF-default-ON-to-enable-RTM-build", "NF_WP_TRACE_ERRORS" : "OFF-default-ON-to-enable-trace-error-messages-wire-protocol", diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/CMakeLists.txt deleted file mode 100644 index f38c6b908e..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/CMakeLists.txt +++ /dev/null @@ -1,190 +0,0 @@ -# -# Copyright (c) 2017 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# - -cmake_minimum_required(VERSION 3.0) -ENABLE_LANGUAGE(ASM) - -# add header files with common OS definitions and board definitions specific for each image -configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" - "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) -configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" - "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) - -# set(NANOBOOTER_PROJECT_NAME "nanoBooter") -set(NANOCLR_PROJECT_NAME "nanoCLR") - -find_package(BuildUtils REQUIRED) -find_package(CHIBIOS REQUIRED) -find_package(ChibiOSnfOverlay REQUIRED) -find_package(WireProtocol REQUIRED) - -# packages for nanoFramework libraries -####################################### -# mandatory -find_package(NF_CoreCLR REQUIRED) - -####################################### -# optional - -# nF feature: debugger -if(NF_FEATURE_DEBUGGER) - find_package(NF_Debugger REQUIRED) - find_package(NF_Diagnostics REQUIRED) -endif() - -# # nF feature: networking -# if(USE_NETWORKING_OPTION) -# find_package(CHIBIOS_LWIP REQUIRED) -# endif() - -# # nF feature: filesystem -# if(USE_FILESYSTEM_OPTION) -# find_package(CHIBIOS_FATFS REQUIRED) -# endif() - -#################################################### -# sources for target specifc stuff related with APIs -list(APPEND API_RELATED_TARGET_SOURCES "") - -# Windows.Devices.SerialCommunication -if(API_Windows.Devices.SerialCommunication) - list(APPEND API_RELATED_TARGET_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/target_windows_devices_serialcommunication_config.cpp") -endif() - -####################################### - -add_subdirectory("common") -# add_subdirectory("nanoBooter") -add_subdirectory("nanoCLR") - -# ####################### -# # nanoBooter executable - -# add_executable( -# # executables for project, project sources -# ${NANOBOOTER_PROJECT_NAME}.elf - -# "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" - -# ${COMMON_PROJECT_SOURCES} -# ${NANOBOOTER_PROJECT_SOURCES} - -# ${TARGET_CMSIS_COMMON_SOURCES} -# ${TARGET_CMSIS_NANOBOOTER_SOURCES} - -# ${TARGET_CHIBIOS_COMMON_SOURCES} -# ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} - -# ${CHIBIOS_SOURCES} -# ${ChibiOSnfOverlay_SOURCES} - -# ${WireProtocol_SOURCES} -# ) - -####################### -# nanoCLR executable - -add_executable( - # executables for project, project sources - ${NANOCLR_PROJECT_NAME}.elf - - "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" - # "heap_useNewlib.c" - # "osi_chibios.c" - - ${COMMON_PROJECT_SOURCES} - ${NANOCLR_PROJECT_SOURCES} - - ${TARGET_CMSIS_COMMON_SOURCES} - ${TARGET_CMSIS_NANOCLR_SOURCES} - - ${TARGET_CHIBIOS_COMMON_SOURCES} - ${TARGET_CHIBIOS_NANOCLR_SOURCES} - - ${CHIBIOS_SOURCES} - ${ChibiOSnfOverlay_SOURCES} - - # sources for nanoFramework libraries - "${NF_CoreCLR_SOURCES}" - "${NF_Debugger_SOURCES}" - "${NF_Diagnostics_SOURCES}" - - # sources for nanoFramework APIs - "${TARGET_NANO_APIS_SOURCES}" -) - -# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) -add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) - -# include common directories -include_directories( - "${CMAKE_CURRENT_BINARY_DIR}" - ${CMAKE_CURRENT_SOURCE_DIR} - ${CMAKE_CURRENT_SOURCE_DIR}/common - ${PROJECT_SOURCE_DIR}/src/CLR/Core - ${PROJECT_SOURCE_DIR}/src/CLR/Include - ${PROJECT_SOURCE_DIR}/src/HAL/Include - ${PROJECT_SOURCE_DIR}/src/PAL/Include - - ${WireProtocol_INCLUDE_DIRS} - ${CHIBIOS_INCLUDE_DIRS} - ${ChibiOSnfOverlay_INCLUDE_DIRS} - - ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} - ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} -) - -# include directories for nanoCLR -target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC - "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR" - ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR - - ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} - ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} - - # directories for nanoFramework libraries - "${NF_CoreCLR_INCLUDE_DIRS}" - "${NF_Debugger_INCLUDE_DIRS}" - "${NF_Diagnostics_INCLUDE_DIRS}" - - # includes for nanoFramework APIs - "${TARGET_NANO_APIS_INCLUDES}" - - # includes for ChibiOS LwIP - # "${CHIBIOS_LWIP_INCLUDE_DIRS}" -) - -# set compiler options -# nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) -nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) - -# set compiler definitions -# nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) -nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) - -# set linker file -# nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F76xx_booter.ld) -nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/cc3200_CLR.ld) - -# set linker options -# using FPU requires enabling printf with FP support for newlib nano, but just for nanoCLR target, don't need to overload nanoBooter with that -# nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf FALSE) -nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf FALSE) - -# add other linker flags -################################################### -# the size of the CLR managed heap is defined here -################################################### -set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x1800") - -# add libraries -# target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/simplelink/gcc/exe/libsimplelink.a) -# target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/driverlib/gcc/exe/libdriver.a) -# target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/oslib/gcc/exe/libtirtos.a) -# target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${TI_CC3200_SDK_PATH}/oslib/gcc/exe/freertos.a) - -# generate output files -# nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) -nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.c deleted file mode 100644 index f5b2ba5f9f..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.c +++ /dev/null @@ -1,23 +0,0 @@ - - -#include "hal.h" - - -/** - * @brief Early initialization code. - * @details This initialization is performed just after reset before BSS and - * DATA segments initialization. - */ -void __early_init(void) -{ - ticc3200_clock_init(); -} - -/** - * @brief Late initialization code. - * @note This initialization is performed after BSS and DATA segments - * initialization and before invoking the main() function. - */ -void boardInit(void) -{ -} diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.h deleted file mode 100644 index 31a52231e0..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/board.h +++ /dev/null @@ -1,32 +0,0 @@ - -#ifndef BOARD_H -#define BOARD_H - -/* - * Setup for Texas Instruments CC3200 Launchpad Board - */ - -/* - * Board identifier. - */ -#define BOARD_TI_CC3200_LAUNCHPAD -#define BOARD_NAME "Texas Instruments CC3200 Launchpad" - -/* - * MCU type and revision as defined in the TI header. - */ -#define PART_CC3200 -#define TARGET_IS_CC3200 - - -#if !defined(_FROM_ASM_) -#ifdef __cplusplus -extern "C" { -#endif - void boardInit(void); -#ifdef __cplusplus -} -#endif -#endif /* _FROM_ASM_ */ - -#endif // BOARD_H \ No newline at end of file diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/CMakeLists.txt deleted file mode 100644 index ad042a37bc..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2017 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# - -# append common source files -# list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") -list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage.c") - -# make var global -set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/Device_BlockStorage.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/Device_BlockStorage.c deleted file mode 100644 index c1b87a35c1..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/common/Device_BlockStorage.c +++ /dev/null @@ -1,95 +0,0 @@ -// -// Copyright (c) 2018 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include - -const BlockRange BlockRange1[] = // 32KB blocks -{ - { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter - { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 08008000 nanoCLR -}; - -const BlockRange BlockRange2[] = //128KB block -{ - { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR -}; - -const BlockRange BlockRange3[] = // 256KB blocks -{ - { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 08040000 deployment -}; - -const BlockRegionInfo BlockRegions[] = -{ - { - 0x08000000, // start address for block region - 4, // total number of blocks in this region - 0x8000, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange1, - }, - - { - 0x08020000, // start address for block region - 1, // total number of blocks in this region - 0x20000, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange2), - BlockRange2, - }, - - { - 0x08040000, // start address for block region - 7, // total number of blocks in this region - 0x40000, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange3), - BlockRange3, - }, - -}; - - -const DeviceBlockInfo Device_BlockInfo = -{ - { - false, // BOOL Removable; - true, // BOOL SupportsXIP; - false, // BOOL WriteProtected; - false // BOOL SupportsCopyBack - }, - ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; - BlockRegions, // const BlockRegionInfo* pRegions; -}; - -MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = -{ - { // BLOCK_CONFIG - { - 0, // GPIO_PIN Pin; - false, // BOOL ActiveState; - }, - - &Device_BlockInfo, // BlockDeviceinfo - }, - - { // CPU_MEMORY_CONFIG - 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; - true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; - 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; - 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; - 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; - 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; - 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; - 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable - 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead - 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable - }, - - 0, // UINT32 ChipProtection; - 0, // UINT32 ManufacturerCode; - 0, // UINT32 DeviceCode; -}; - -BlockStorageDevice Device_BlockStorage; diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/heap_useNewlib.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/heap_useNewlib.c deleted file mode 100644 index 6ad783a69b..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/heap_useNewlib.c +++ /dev/null @@ -1,156 +0,0 @@ -/** - * \file heap_useNewlib.c - * \brief Wrappers required to use newlib malloc-family within FreeRTOS. - * - * \par Overview - * Route FreeRTOS memory management functions to newlib's malloc family. - * Thus newlib and FreeRTOS share memory-management routines and memory pool, - * and all newlib's internal memory-management requirements are supported. - * - * \author Dave Nadler - * \date 2-July-2017 - * - * \see http://www.nadler.com/embedded/newlibAndFreeRTOS.html - * \see https://sourceware.org/newlib/libc.html#Reentrancy - * \see https://sourceware.org/newlib/libc.html#malloc - * \see https://sourceware.org/newlib/libc.html#index-_005f_005fenv_005flock - * \see https://sourceware.org/newlib/libc.html#index-_005f_005fmalloc_005flock - * \see https://sourceforge.net/p/freertos/feature-requests/72/ - * \see http://www.billgatliff.com/newlib.html - * \see http://wiki.osdev.org/Porting_Newlib - * \see http://www.embecosm.com/appnotes/ean9/ean9-howto-newlib-1.0.html - * - * - * \copyright - * (c) Dave Nadler 2017, All Rights Reserved. - * Web: http://www.nadler.com - * email: drn@nadler.com - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * - Use or redistributions of source code must retain the above copyright notice, - * this list of conditions, ALL ORIGINAL COMMENTS, and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include // maps to newlib... -#include // mallinfo... -#include // ENOMEM - -#include "newlib.h" -#if (__NEWLIB__ != 2) || (__NEWLIB_MINOR__ != 5) - #warning "This wrapper was verified for newlib version 2.5.0; please ensure newlib's external requirements for malloc-family are unchanged!" -#endif - -#include "FreeRTOS.h" // defines public interface we're implementing here -#if !defined(configUSE_NEWLIB_REENTRANT) || (configUSE_NEWLIB_REENTRANT!=1) - #warning "#define configUSE_NEWLIB_REENTRANT 1 // Required for thread-safety of newlib sprintf, strtok, etc..." - // If you're *really* sure you don't need FreeRTOS's newlib reentrancy support, remove this warning... -#endif -#include "task.h" - -// ================================================================================================ -// External routines required by newlib's malloc (sbrk/_sbrk, __malloc_lock/unlock) -// ================================================================================================ - -#ifndef NDEBUG - static int totalBytesProvidedBySBRK = 0; -#endif -extern char __HeapBase, __HeapLimit, HEAP_SIZE; // make sure to define these symbols in linker command file -static int heapBytesRemaining = (int)&HEAP_SIZE; // that's (&__HeapLimit)-(&__HeapBase) - -//! sbrk/_sbrk version supporting reentrant newlib (depends upon above symbols defined by linker control file). -char * sbrk(int incr) { - static char *currentHeapEnd = &__HeapBase; - vTaskSuspendAll(); // Note: safe to use before FreeRTOS scheduler started - char *previousHeapEnd = currentHeapEnd; - if (currentHeapEnd + incr > &__HeapLimit) { - #if( configUSE_MALLOC_FAILED_HOOK == 1 ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - #elif 0 - // If you want to alert debugger or halt... - while(1) { __asm("bkpt #0"); }; // Stop in GUI as if at a breakpoint (if debugging, otherwise loop forever) - #else - // If you prefer to believe your application will gracefully trap out-of-memory... - _impure_ptr->_errno = ENOMEM; // newlib's thread-specific errno - xTaskResumeAll(); - #endif - return (char *)-1; // the malloc-family routine that called sbrk will return 0 - } - currentHeapEnd += incr; - heapBytesRemaining -= incr; - #ifndef NDEBUG - totalBytesProvidedBySBRK += incr; - #endif - xTaskResumeAll(); - return (char *) previousHeapEnd; -} -//! Synonym for sbrk. -char * _sbrk(int incr) { return sbrk(incr); }; - -void __malloc_lock() { vTaskSuspendAll(); }; -void __malloc_unlock() { (void)xTaskResumeAll(); }; - -// newlib also requires implementing locks for the application's environment memory space, -// accessed by newlib's setenv() and getenv() functions. -// As these are trivial functions, momentarily suspend task switching (rather than semaphore). -// ToDo: Move __env_lock/unlock to a separate newlib helper file. -void __env_lock() { vTaskSuspendAll(); }; -void __env_unlock() { (void)xTaskResumeAll(); }; - -/// /brief Wrap malloc/malloc_r to help debug who requests memory and why. -/// Add to the linker command line: -Xlinker --wrap=malloc -Xlinker --wrap=_malloc_r -// Note: These functions are normally unused and stripped by linker. -void *__wrap_malloc(size_t nbytes) { - extern void * __real_malloc(size_t nbytes); - void *p = __real_malloc(nbytes); // Solely for debug breakpoint... - return p; -}; -void *__wrap__malloc_r(void *reent, size_t nbytes) { - extern void * __real__malloc_r(size_t nbytes); - void *p = __real__malloc_r(nbytes); // Solely for debug breakpoint... - return p; -}; - - -// ================================================================================================ -// Implement FreeRTOS's memory API using newlib-provided malloc family. -// ================================================================================================ - -void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION { - - void *p = malloc(xSize); - return p; -} -void vPortFree( void *pv ) PRIVILEGED_FUNCTION { - free(pv); -}; - -size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION { - struct mallinfo mi = mallinfo(); - return mi.fordblks + heapBytesRemaining; -} - -// GetMinimumEverFree is not available in newlib's malloc implementation. -// So, no implementation provided: size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; - -//! No implementation needed, but stub provided in case application already calls vPortInitialiseBlocks -void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION {}; diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoBooter/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoBooter/CMakeLists.txt deleted file mode 100644 index 7535bcf31a..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoBooter/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# -# Copyright (c) 2018 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/CMakeLists.txt deleted file mode 100644 index 246391d098..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2017 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# - -# append nanoCLR source files -list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main_blink.c") -# list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") -# list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") -# list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/pinmux.c") - -# make var global -set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld deleted file mode 100644 index dd708baed7..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/cc3200_CLR.ld +++ /dev/null @@ -1,164 +0,0 @@ -/***************************************************************************** -* blinky.ld -* -* GCC Linker script for blinky application. -* -* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -/* -// -// Copyright (c) 2017 The nanoFramework project contributors -// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. -// See LICENSE file in the project root for full license information. -// -*/ - -/* - * CC3200 generic setup. - * - * RAM0 - Data, Heap. - * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. - * - * Notes: - * BSS is placed in DTCM RAM in order to simplify DMA buffers management. - */ -MEMORY -{ - flash : org = 0x08008000, len = 2M - 32k - 1792k /* flash size less the space reserved for nanoBooter and application deployment*/ - flash_itcm : org = 0x00208000, len = 2M - 32k - 1792k - deployment : org = 0x08040000, len = 1792k /* space reserved for application deployment */ - ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ - ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20020000, len = 368k /* SRAM1 */ - ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ - ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ - ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* For each data/text section two region are defined, a virtual region - and a load region (_LMA suffix).*/ - -/* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash_itcm); -REGION_ALIAS("VECTORS_FLASH_LMA", flash); - -/* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash_itcm); -REGION_ALIAS("XTORS_FLASH_LMA", flash); - -/* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash_itcm); -REGION_ALIAS("TEXT_FLASH_LMA", flash); - -/* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash); -REGION_ALIAS("RODATA_FLASH_LMA", flash); - -/* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash_itcm); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash); - -/* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts.*/ -REGION_ALIAS("MAIN_STACK_RAM", ram3); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram3); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram3); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); - -/* rules inclusion.*/ -INCLUDE rules_stacks.ld - -/*===========================================================================*/ -/* Custom sections for STM32F7xx. */ -/*===========================================================================*/ - -/* RAM region to be used for nocache segment.*/ -REGION_ALIAS("NOCACHE_RAM", ram3); - -/* RAM region to be used for eth segment.*/ -REGION_ALIAS("ETH_RAM", ram3); - -SECTIONS -{ - /* Special section for non cache-able areas.*/ - .nocache (NOLOAD) : ALIGN(4) - { - __nocache_base__ = .; - *(.nocache) - *(.nocache.*) - *(.bss.__nocache_*) - . = ALIGN(4); - __nocache_end__ = .; - } > NOCACHE_RAM - - /* Special section for Ethernet DMA non cache-able areas.*/ - .eth (NOLOAD) : ALIGN(4) - { - __eth_base__ = .; - *(.eth) - *(.eth.*) - *(.bss.__eth_*) - . = ALIGN(4); - __eth_end__ = .; - } > ETH_RAM -} - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* Data rules inclusion.*/ -INCLUDE rules_data.ld - -/* nanoCLR rules inclusion.*/ -INCLUDE rules_clr.ld diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h deleted file mode 100644 index 49157f296d..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/chconf.h +++ /dev/null @@ -1,516 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -/** - * @file templates/chconf.h - * @brief Configuration file template. - * @details A copy of this file must be placed in each project directory, it - * contains the application specific kernel settings. - * - * @addtogroup config - * @details Kernel related settings and hooks. - * @{ - */ - -#ifndef CHCONF_H -#define CHCONF_H - -#define _CHIBIOS_RT_CONF_ - -/*===========================================================================*/ -/** - * @name System timers settings - * @{ - */ -/*===========================================================================*/ - -/** - * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. - */ -#define CH_CFG_ST_RESOLUTION 32 - -/** - * @brief System tick frequency. - * @details Frequency of the system timer that drives the system ticks. This - * setting also defines the system tick time unit. - */ -#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond - -/** - * @brief Time delta constant for the tick-less mode. - * @note If this value is zero then the system uses the classic - * periodic tick. This value represents the minimum number - * of ticks that is safe to specify in a timeout directive. - * The value one is not valid, timeouts are rounded up to - * this value. - */ -#define CH_CFG_ST_TIMEDELTA 0 - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel parameters and options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Round robin interval. - * @details This constant is the number of system ticks allowed for the - * threads before preemption occurs. Setting this value to zero - * disables the preemption for threads with equal priority and the - * round robin becomes cooperative. Note that higher priority - * threads can still preempt, the kernel is always preemptive. - * @note Disabling the round robin preemption makes the kernel more compact - * and generally faster. - * @note The round robin preemption is not supported in tickless mode and - * must be set to zero in that case. - */ -#define CH_CFG_TIME_QUANTUM 0 - -/** - * @brief Managed RAM size. - * @details Size of the RAM area to be managed by the OS. If set to zero - * then the whole available RAM is used. The core memory is made - * available to the heap allocator and/or can be used directly through - * the simplified core memory allocator. - * - * @note In order to let the OS manage the whole RAM the linker script must - * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_CFG_USE_MEMCORE. - */ -#define CH_CFG_MEMCORE_SIZE 0 - -/** - * @brief Idle thread automatic spawn suppression. - * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread. The application @p main() - * function becomes the idle thread and must implement an - * infinite loop. - */ -#define CH_CFG_NO_IDLE_THREAD FALSE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Performance options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief OS optimization. - * @details If enabled then time efficient rather than space efficient code - * is used when two possible implementations exist. - * - * @note This is not related to the compiler optimization options. - * @note The default is @p TRUE. - */ -#define CH_CFG_OPTIMIZE_SPEED TRUE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Subsystem options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Time Measurement APIs. - * @details If enabled then the time measurement APIs are included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_TM TRUE - -/** - * @brief Threads registry APIs. - * @details If enabled then the registry APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_REGISTRY TRUE - -/** - * @brief Threads synchronization APIs. - * @details If enabled then the @p chThdWait() function is included in - * the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_WAITEXIT TRUE - -/** - * @brief Semaphores APIs. - * @details If enabled then the Semaphores APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_SEMAPHORES TRUE - -/** - * @brief Semaphores queuing mode. - * @details If enabled then the threads are enqueued on semaphores by - * priority rather than in FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE - -/** - * @brief Mutexes APIs. - * @details If enabled then the mutexes APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_MUTEXES TRUE - -/** - * @brief Enables recursive behavior on mutexes. - * @note Recursive mutexes are heavier and have an increased - * memory footprint. - * - * @note The default is @p FALSE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE - -/** - * @brief Conditional Variables APIs. - * @details If enabled then the conditional variables APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MUTEXES. - */ -#define CH_CFG_USE_CONDVARS TRUE - -/** - * @brief Conditional Variables APIs with timeout. - * @details If enabled then the conditional variables APIs with timeout - * specification are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_CONDVARS. - */ -#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE - -/** - * @brief Events Flags APIs. - * @details If enabled then the event flags APIs are included in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_EVENTS TRUE - -/** - * @brief Events Flags APIs with timeout. - * @details If enabled then the events APIs with timeout specification - * are included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_EVENTS. - */ -#define CH_CFG_USE_EVENTS_TIMEOUT TRUE - -/** - * @brief Synchronous Messages APIs. - * @details If enabled then the synchronous messages APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_MESSAGES TRUE - -/** - * @brief Synchronous Messages queuing mode. - * @details If enabled then messages are served by priority rather than in - * FIFO order. - * - * @note The default is @p FALSE. Enable this if you have special - * requirements. - * @note Requires @p CH_CFG_USE_MESSAGES. - */ -#define CH_CFG_USE_MESSAGES_PRIORITY FALSE - -/** - * @brief Mailboxes APIs. - * @details If enabled then the asynchronous messages (mailboxes) APIs are - * included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_SEMAPHORES. - */ -#define CH_CFG_USE_MAILBOXES TRUE - -/** - * @brief Core Memory Manager APIs. - * @details If enabled then the core memory manager APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_MEMCORE TRUE - -/** - * @brief Heap Allocator APIs. - * @details If enabled then the memory heap allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or - * @p CH_CFG_USE_SEMAPHORES. - * @note Mutexes are recommended. - */ -#define CH_CFG_USE_HEAP TRUE - -/** - * @brief Memory Pools Allocator APIs. - * @details If enabled then the memory pools allocator APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - */ -#define CH_CFG_USE_MEMPOOLS TRUE - -/** - * @brief Dynamic Threads APIs. - * @details If enabled then the dynamic threads creation APIs are included - * in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_CFG_USE_WAITEXIT. - * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. - */ -#define CH_CFG_USE_DYNAMIC TRUE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Debug options - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Debug option, kernel statistics. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_STATISTICS FALSE - -/** - * @brief Debug option, system state check. - * @details If enabled the correct call protocol for system APIs is checked - * at runtime. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_SYSTEM_STATE_CHECK FALSE - -/** - * @brief Debug option, parameters checks. - * @details If enabled then the checks on the API functions input - * parameters are activated. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_ENABLE_CHECKS FALSE - -/** - * @brief Debug option, consistency checks. - * @details If enabled then all the assertions in the kernel code are - * activated. This includes consistency checks inside the kernel, - * runtime anomalies and port-defined checks. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_ENABLE_ASSERTS FALSE - -/** - * @brief Debug option, trace buffer. - * @details If enabled then the trace buffer is activated. - * - * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. - */ -#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED - -/** - * @brief Trace buffer entries. - * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is - * different from @p CH_DBG_TRACE_MASK_DISABLED. - */ -#define CH_DBG_TRACE_BUFFER_SIZE 128 - -/** - * @brief Debug option, stack checks. - * @details If enabled then a runtime stack check is performed. - * - * @note The default is @p FALSE. - * @note The stack check is performed in a architecture/port dependent way. - * It may not be implemented or some ports. - * @note The default failure mode is to halt the system with the global - * @p panic_msg variable set to @p NULL. - */ -#define CH_DBG_ENABLE_STACK_CHECK FALSE - -/** - * @brief Debug option, stacks initialization. - * @details If enabled then the threads working area is filled with a byte - * value when a thread is created. This can be useful for the - * runtime measurement of the used stack. - * - * @note The default is @p FALSE. - */ -#define CH_DBG_FILL_THREADS FALSE - -/** - * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p thread_t structure that - * counts the system ticks occurred while executing the thread. - * - * @note The default is @p FALSE. - * @note This debug option is not currently compatible with the - * tickless mode. - */ -#define CH_DBG_THREADS_PROFILING FALSE - -/** @} */ - -/*===========================================================================*/ -/** - * @name Kernel hooks - * @{ - */ -/*===========================================================================*/ - -/** - * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p thread_t structure. - */ -#define CH_CFG_THREAD_EXTRA_FIELDS \ - /* Add threads custom fields here.*/ - -/** - * @brief Threads initialization hook. - * @details User initialization code added to the @p chThdInit() API. - * - * @note It is invoked from within @p chThdInit() and implicitly from all - * the threads creation APIs. - */ -#define CH_CFG_THREAD_INIT_HOOK(tp) { \ - /* Add threads initialization code here.*/ \ -} - -/** - * @brief Threads finalization hook. - * @details User finalization code added to the @p chThdExit() API. - */ -#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ - /* Add threads finalization code here.*/ \ -} - -/** - * @brief Context switch hook. - * @details This hook is invoked just before switching between threads. - */ -#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ - /* Context switch code here.*/ \ -} - -/** - * @brief ISR enter hook. - */ -#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ - /* IRQ prologue code here.*/ \ -} - -/** - * @brief ISR exit hook. - */ -#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ - /* IRQ epilogue code here.*/ \ -} - -/** - * @brief Idle thread enter hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to activate a power saving mode. - */ -#define CH_CFG_IDLE_ENTER_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle thread leave hook. - * @note This hook is invoked within a critical zone, no OS functions - * should be invoked from here. - * @note This macro can be used to deactivate a power saving mode. - */ -#define CH_CFG_IDLE_LEAVE_HOOK() { \ - /* Idle-enter code here.*/ \ -} - -/** - * @brief Idle Loop hook. - * @details This hook is continuously invoked by the idle thread loop. - */ -#define CH_CFG_IDLE_LOOP_HOOK() { \ - /* Idle loop code here.*/ \ -} - -/** - * @brief System tick event hook. - * @details This hook is invoked in the system tick handler immediately - * after processing the virtual timers queue. - */ -#define CH_CFG_SYSTEM_TICK_HOOK() { \ - /* System tick event code here.*/ \ -} - -/** - * @brief System halt hook. - * @details This hook is invoked in case to a system halting error before - * the system is halted. - */ -#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ - /* System halt code here.*/ \ -} - -/** - * @brief Trace hook. - * @details This hook is invoked each time a new record is written in the - * trace buffer. - */ -#define CH_CFG_TRACE_HOOK(tep) { \ - /* Trace code here.*/ \ -} - -/** @} */ - -/*===========================================================================*/ -/* Port-specific settings (override port settings defaulted in chcore.h). */ -/*===========================================================================*/ - -/////////////////////////////////////////////////////////////////////////////// -// address of vector table for nanoCLR -//#define CORTEX_VTOR_INIT 0x08008000U -/////////////////////////////////////////////////////////////////////////////// - -#endif /* CHCONF_H */ - -/** @} */ - diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h deleted file mode 100644 index 056f370803..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf.h +++ /dev/null @@ -1,384 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -/** - * @file templates/halconf.h - * @brief HAL configuration header. - * @details HAL configuration file, this file allows to enable or disable the - * various device drivers from your application. You may also use - * this file in order to override the device drivers default settings. - * - * @addtogroup HAL_CONF - * @{ - */ - -#ifndef HALCONF_H -#define HALCONF_H - -// FIXME #include -#include "mcuconf.h" - -/** - * @brief Enables the PAL subsystem. - */ -#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) -#define HAL_USE_PAL TRUE -#endif - -/** - * @brief Enables the ADC subsystem. - */ -// this option is set at target_platform.h (from config file) -// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -// #define HAL_USE_ADC FALSE -// #endif - -/** - * @brief Enables the CAN subsystem. - */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif - -/** - * @brief Enables the DAC subsystem. - */ -#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) -#define HAL_USE_DAC FALSE -#endif - -/** - * @brief Enables the EXT subsystem. - */ -// this option is set at target_platform.h (from config file) -// #if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -// #define HAL_USE_EXT FALSE -// #endif - -/** - * @brief Enables the GPT subsystem. - */ -#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) -#define HAL_USE_GPT FALSE -#endif - -/** - * @brief Enables the I2C subsystem. - */ -// this option is set at target_platform.h (from config file) -//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -//#define HAL_USE_I2C TRUE -//#endif -/** - * @brief Enables the I2S subsystem. - */ -#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) -#define HAL_USE_I2S FALSE -#endif - -/** - * @brief Enables the ICU subsystem. - */ -#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE -#endif - -/** - * @brief Enables the MAC subsystem. - */ -// this option is set at target_platform.h (from config file) -// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) -// #define HAL_USE_MAC TRUE -// #endif - -/** - * @brief Enables the MMC_SPI subsystem. - */ -#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) -#define HAL_USE_MMC_SPI FALSE -#endif - -/** - * @brief Enables the PWM subsystem. - */ -// this option is set at target_platform.h (from config file) -// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -// #define HAL_USE_PWM FALSE -// #endif - -/** - * @brief Enables the RTC subsystem. - */ -// this option is set at target_platform.h (from config file) -// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) -// #define HAL_USE_RTC TRUE -// #endif - -/** - * @brief Enables the SDC subsystem. - */ -// this option is set at target_platform.h (from config file) -// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) -// #define HAL_USE_SDC FALSE -// #endif - -/** - * @brief Enables the SERIAL subsystem. - */ -#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL FALSE -#endif - -/** - * @brief Enables the SERIAL over USB subsystem. - */ -#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) -#define HAL_USE_SERIAL_USB FALSE -#endif - -/** - * @brief Enables the SPI subsystem. - */ -// this option is set at target_platform.h (from config file) -// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -// #define HAL_USE_SPI FALSE -// #endif - -/** - * @brief Enables the UART subsystem. - */ -// this option is set at target_platform.h (from config file) -// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) -// #define HAL_USE_UART FALSE -// #endif - -/** - * @brief Enables the USB subsystem. - */ -#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB FALSE -#endif - -/** - * @brief Enables the WDG subsystem. - */ -#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) -#define HAL_USE_WDG FALSE -#endif - -/*===========================================================================*/ -/* ADC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) -#define ADC_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define ADC_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* CAN driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Sleep mode related APIs inclusion switch. - */ -#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) -#define CAN_USE_SLEEP_MODE TRUE -#endif - -/*===========================================================================*/ -/* I2C driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables the mutual exclusion APIs on the I2C bus. - */ -#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define I2C_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* MAC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) -#define MAC_USE_ZERO_COPY FALSE -#endif - -/** - * @brief Enables an event sources for incoming packets. - */ -#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) -#define MAC_USE_EVENTS TRUE -#endif - -/*===========================================================================*/ -/* MMC_SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - * This option is recommended also if the SPI driver does not - * use a DMA channel and heavily loads the CPU. - */ -#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) -#define MMC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SDC driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Number of initialization attempts before rejecting the card. - * @note Attempts are performed at 10mS intervals. - */ -#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) -#define SDC_INIT_RETRY 100 -#endif - -/** - * @brief Include support for MMC cards. - * @note MMC support is not yet implemented so this option must be kept - * at @p FALSE. - */ -#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) -#define SDC_MMC_SUPPORT FALSE -#endif - -/** - * @brief Delays insertions. - * @details If enabled this options inserts delays into the MMC waiting - * routines releasing some extra CPU time for the threads with - * lower priority, this may slow down the driver a bit however. - */ -#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) -#define SDC_NICE_WAITING TRUE -#endif - -/*===========================================================================*/ -/* SERIAL driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Default bit rate. - * @details Configuration parameter, this is the baud rate selected for the - * default configuration. - */ -#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) -#define SERIAL_DEFAULT_BITRATE 115200 -#endif - -/** - * @brief Serial buffers size. - * @details Configuration parameter, you can change the depth of the queue - * buffers depending on the requirements of your application. - * @note The default is 16 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_BUFFERS_SIZE 16 -#endif - -/*===========================================================================*/ -/* SERIAL_USB driver related setting. */ -/*===========================================================================*/ - -/** - * @brief Serial over USB buffers size. - * @details Configuration parameter, the buffer size must be a multiple of - * the USB data endpoint maximum packet size. - * @note The default is 256 bytes for both the transmission and receive - * buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_SIZE 64 -#endif - -/** - * @brief Serial over USB number of buffers. - * @note The default is 2 buffers. - */ -#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) -#define SERIAL_USB_BUFFERS_NUMBER 1 -#endif - -/*===========================================================================*/ -/* SPI driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) -#define SPI_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define SPI_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* UART driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) -#define UART_USE_WAIT TRUE -#endif - -/** - * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) -#define UART_USE_MUTUAL_EXCLUSION TRUE -#endif - -/*===========================================================================*/ -/* USB driver related settings. */ -/*===========================================================================*/ - -/** - * @brief Enables synchronous APIs. - * @note Disabling this option saves both code and data space. - */ -#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) -#define USB_USE_WAIT FALSE -#endif - -// header for nanoFramework overlay -#include "halconf_nf.h" - -#endif /* HALCONF_H */ - -/** @} */ - diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h deleted file mode 100644 index 1371a05162..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/halconf_nf.h +++ /dev/null @@ -1,20 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - -#ifndef _HALCONF_NF_H_ -#define _HALCONF_NF_H_ - -// Enables the ChibiOS community overlay. -#if !defined(HAL_USE_COMMUNITY) -#define HAL_USE_COMMUNITY TRUE -#endif - -// enables STM32 Flash driver -#if !defined(HAL_USE_STM32_FLASH) -//#define HAL_USE_STM32_FLASH TRUE -#endif - -#endif // _HALCONF_NF_H_ - diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c deleted file mode 100644 index 801a272181..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_blink.c +++ /dev/null @@ -1,112 +0,0 @@ - -#include -#include -#include - - -// // Simplelink includes -// #include "simplelink.h" - -// // Driverlib includes -// #include "hw_types.h" -// #include "hw_ints.h" -// #include "hw_memmap.h" -// #include "hw_common_reg.h" -// #include "interrupt.h" -// #include "hw_apps_rcm.h" -// #include "prcm.h" -// #include "rom.h" -// #include "rom_map.h" -// #include "prcm.h" -// #include "gpio.h" -// #include "utils.h" - -// //Free_rtos/ti-rtos includes -// #include "osi.h" - -// // Common interface includes -// #include "gpio_if.h" -// #include "common.h" -// #include "pinmux.h" - - -void BlinkerThread(void const * argument) -{ - (void)argument; - - // palSetLineMode(1, PAL_MODE_OUTPUT_PUSHPULL); - - - // loop until thread receives a request to terminate - while (!chThdShouldTerminateX()) { - - // palSetPad(GPIOD, GPIOD_LED3); - // osDelay(500); - // palClearPad(GPIOD, GPIOD_LED3); - // osDelay(500); - - } - // nothing to deinitialize or cleanup, so it's safe to return -} -osThreadDef(BlinkerThread, osPriorityNormal, 128, "BlinkerThread"); - -// Application entry point. -int main(void) { - - osThreadId blinkerThreadId; - - // HAL initialization, this also initializes the configured device drivers - // and performs the board-specific initializations. - halInit(); - -// // init SWO as soon as possible to make it available to output ASAP -// #if (SWO_OUTPUT == TRUE) -// SwoInit(); -// #endif - - // The kernel is initialized but not started yet, this means that - // main() is executing with absolute priority but interrupts are already enabled. - osKernelInitialize(); - osDelay(20); // Let init stabilize - -// // the following IF is not mandatory, it's just providing a way for a user to 'force' -// // the board to remain in nanoBooter and not launching nanoCLR - -// // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter -// // the user button in this board has a pull-up resistor so the check has to be inverted -// if (palReadPad(GPIOA, GPIOA_BUTTON)) -// { -// // check for valid CLR image -// if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) -// { -// // there seems to be a valid CLR image -// // launch nanoCLR -// LaunchCLR((uint32_t)&__nanoImage_end__); -// } -// } - -// // Initializes a serial-over-USB CDC driver. -// sduObjectInit(&SDU1); -// sduStart(&SDU1, &serusbcfg); - -// // Activates the USB driver and then the USB bus pull-up on D+. -// // Note, a delay is inserted in order to not have to disconnect the cable after a reset. -// usbDisconnectBus(serusbcfg.usbp); -// chThdSleepMilliseconds(1500); -// usbStart(serusbcfg.usbp, &usbcfg); -// usbConnectBus(serusbcfg.usbp); - - // Creates the blinker thread, it does not start immediately. - blinkerThreadId = osThreadCreate(osThread(BlinkerThread), NULL); - -// // create the receiver thread -// receiverThreadId = osThreadCreate(osThread(ReceiverThread), NULL); - - // start kernel, after this main() will behave like a thread with priority osPriorityNormal - osKernelStart(); - - // Normal main() thread - while (true) { - osDelay(500); - } -} diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c deleted file mode 100644 index 05cc17cab9..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/main_wlan.c +++ /dev/null @@ -1,964 +0,0 @@ - -// Standard includes -#include -#include - -#include "ch.h" -#include "hal.h" - -// Simplelink includes -#include "simplelink.h" - -//Driverlib includes -#include "hw_types.h" -#include "hw_ints.h" -#include "rom.h" -#include "rom_map.h" -#include "interrupt.h" -#include "prcm.h" -#include "utils.h" - -//Free_rtos/ti-rtos includes -#include "osi.h" - -//Common interface includes -#include "gpio_if.h" -#ifndef NOTERM -#include "uart_if.h" -#endif -#include "common.h" -#include "pinmux.h" - - -#define APPLICATION_NAME "WLAN STATION" -#define APPLICATION_VERSION "1.1.1" - -#define HOST_NAME "www.ti.com" - -// -// Values for below macros shall be modified for setting the 'Ping' properties -// -#define PING_INTERVAL 1000 /* In msecs */ -#define PING_TIMEOUT 3000 /* In msecs */ -#define PING_PKT_SIZE 20 /* In bytes */ -#define NO_OF_ATTEMPTS 3 - -#define OSI_STACK_SIZE 2048 - -// Application specific status/error codes -typedef enum{ - // Choosing -0x7D0 to avoid overlap w/ host-driver's error codes - LAN_CONNECTION_FAILED = -0x7D0, - INTERNET_CONNECTION_FAILED = LAN_CONNECTION_FAILED - 1, - DEVICE_NOT_IN_STATION_MODE = INTERNET_CONNECTION_FAILED - 1, - - STATUS_CODE_MAX = -0xBB8 -}e_AppStatusCodes; - - -//***************************************************************************** -// GLOBAL VARIABLES -- Start -//***************************************************************************** -unsigned long g_ulStatus = 0;//SimpleLink Status -unsigned long g_ulPingPacketsRecv = 0; //Number of Ping Packets received -unsigned long g_ulGatewayIP = 0; //Network Gateway IP address -unsigned char g_ucConnectionSSID[SSID_LEN_MAX+1]; //Connection SSID -unsigned char g_ucConnectionBSSID[BSSID_LEN_MAX]; //Connection BSSID - -#if defined(gcc) -extern void (* const g_pfnVectors[])(void); -#endif -#if defined(ewarm) -extern uVectorEntry __vector_table; -#endif -//***************************************************************************** -// GLOBAL VARIABLES -- End -//***************************************************************************** - - - -//**************************************************************************** -// LOCAL FUNCTION PROTOTYPES -//**************************************************************************** -static long WlanConnect(); -void WlanStationMode( void *pvParameters ); -static long CheckLanConnection(); -static long CheckInternetConnection(); -static void InitializeAppVariables(); -static long ConfigureSimpleLinkToDefaultState(); - - -#ifdef USE_FREERTOS -//***************************************************************************** -// FreeRTOS User Hook Functions enabled in FreeRTOSConfig.h -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Application defined hook (or callback) function - assert -//! -//! \param[in] pcFile - Pointer to the File Name -//! \param[in] ulLine - Line Number -//! -//! \return none -//! -//***************************************************************************** -void -vAssertCalled( const char *pcFile, unsigned long ulLine ) -{ - //Handle Assert here - while(1) - { - } -} - -//***************************************************************************** -// -//! \brief Application defined idle task hook -//! -//! \param none -//! -//! \return none -//! -//***************************************************************************** -void -vApplicationIdleHook( void) -{ - //Handle Idle Hook for Profiling, Power Management etc -} - -//***************************************************************************** -// -//! \brief Application defined malloc failed hook -//! -//! \param none -//! -//! \return none -//! -//***************************************************************************** -void vApplicationMallocFailedHook() -{ - //Handle Memory Allocation Errors - while(1) - { - } -} - -//***************************************************************************** -// -//! \brief Application defined stack overflow hook -//! -//! \param none -//! -//! \return none -//! -//***************************************************************************** -void vApplicationStackOverflowHook( OsiTaskHandle *pxTask, - signed char *pcTaskName) -{ - //Handle FreeRTOS Stack Overflow - while(1) - { - } -} -#endif //USE_FREERTOS - - -//***************************************************************************** -// SimpleLink Asynchronous Event Handlers -- Start -//***************************************************************************** - - -//***************************************************************************** -// -//! \brief The Function Handles WLAN Events -//! -//! \param[in] pWlanEvent - Pointer to WLAN Event Info -//! -//! \return None -//! -//***************************************************************************** -void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) -{ - switch(pWlanEvent->Event) - { - case SL_WLAN_CONNECT_EVENT: - { - SET_STATUS_BIT(g_ulStatus, STATUS_BIT_CONNECTION); - - // - // Information about the connected AP (like name, MAC etc) will be - // available in 'slWlanConnectAsyncResponse_t'-Applications - // can use it if required - // - // slWlanConnectAsyncResponse_t *pEventData = NULL; - // pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected; - // - - // Copy new connection SSID and BSSID to global parameters - memcpy(g_ucConnectionSSID,pWlanEvent->EventData. - STAandP2PModeWlanConnected.ssid_name, - pWlanEvent->EventData.STAandP2PModeWlanConnected.ssid_len); - memcpy(g_ucConnectionBSSID, - pWlanEvent->EventData.STAandP2PModeWlanConnected.bssid, - SL_BSSID_LENGTH); - - UART_PRINT("[WLAN EVENT] STA Connected to the AP: %s ," - "BSSID: %x:%x:%x:%x:%x:%x\n\r", - g_ucConnectionSSID,g_ucConnectionBSSID[0], - g_ucConnectionBSSID[1],g_ucConnectionBSSID[2], - g_ucConnectionBSSID[3],g_ucConnectionBSSID[4], - g_ucConnectionBSSID[5]); - } - break; - - case SL_WLAN_DISCONNECT_EVENT: - { - slWlanConnectAsyncResponse_t* pEventData = NULL; - - CLR_STATUS_BIT(g_ulStatus, STATUS_BIT_CONNECTION); - CLR_STATUS_BIT(g_ulStatus, STATUS_BIT_IP_AQUIRED); - - pEventData = &pWlanEvent->EventData.STAandP2PModeDisconnected; - - // If the user has initiated 'Disconnect' request, - //'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED_DISCONNECTION - if(SL_WLAN_DISCONNECT_USER_INITIATED_DISCONNECTION == pEventData->reason_code) - { - UART_PRINT("[WLAN EVENT]Device disconnected from the AP: %s," - "BSSID: %x:%x:%x:%x:%x:%x on application's request \n\r", - g_ucConnectionSSID,g_ucConnectionBSSID[0], - g_ucConnectionBSSID[1],g_ucConnectionBSSID[2], - g_ucConnectionBSSID[3],g_ucConnectionBSSID[4], - g_ucConnectionBSSID[5]); - } - else - { - UART_PRINT("[WLAN ERROR]Device disconnected from the AP AP: %s," - "BSSID: %x:%x:%x:%x:%x:%x on an ERROR..!! \n\r", - g_ucConnectionSSID,g_ucConnectionBSSID[0], - g_ucConnectionBSSID[1],g_ucConnectionBSSID[2], - g_ucConnectionBSSID[3],g_ucConnectionBSSID[4], - g_ucConnectionBSSID[5]); - } - memset(g_ucConnectionSSID,0,sizeof(g_ucConnectionSSID)); - memset(g_ucConnectionBSSID,0,sizeof(g_ucConnectionBSSID)); - } - break; - - default: - { - UART_PRINT("[WLAN EVENT] Unexpected event [0x%x]\n\r", - pWlanEvent->Event); - } - break; - } -} - -//***************************************************************************** -// -//! \brief This function handles network events such as IP acquisition, IP -//! leased, IP released etc. -//! -//! \param[in] pNetAppEvent - Pointer to NetApp Event Info -//! -//! \return None -//! -//***************************************************************************** -void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) -{ - switch(pNetAppEvent->Event) - { - case SL_NETAPP_IPV4_IPACQUIRED_EVENT: - { - SlIpV4AcquiredAsync_t *pEventData = NULL; - - SET_STATUS_BIT(g_ulStatus, STATUS_BIT_IP_AQUIRED); - - //Ip Acquired Event Data - pEventData = &pNetAppEvent->EventData.ipAcquiredV4; - - //Gateway IP address - g_ulGatewayIP = pEventData->gateway; - - UART_PRINT("[NETAPP EVENT] IP Acquired: IP=%d.%d.%d.%d , " - "Gateway=%d.%d.%d.%d\n\r", - SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.ip,3), - SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.ip,2), - SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.ip,1), - SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.ip,0), - SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.gateway,3), - SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.gateway,2), - SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.gateway,1), - SL_IPV4_BYTE(pNetAppEvent->EventData.ipAcquiredV4.gateway,0)); - } - break; - - default: - { - UART_PRINT("[NETAPP EVENT] Unexpected event [0x%x] \n\r", - pNetAppEvent->Event); - } - break; - } -} - - -//***************************************************************************** -// -//! \brief This function handles HTTP server events -//! -//! \param[in] pServerEvent - Contains the relevant event information -//! \param[in] pServerResponse - Should be filled by the user with the -//! relevant response information -//! -//! \return None -//! -//**************************************************************************** -void SimpleLinkHttpServerCallback(SlHttpServerEvent_t *pHttpEvent, - SlHttpServerResponse_t *pHttpResponse) -{ - // Unused in this application -} - -//***************************************************************************** -// -//! \brief This function handles General Events -//! -//! \param[in] pDevEvent - Pointer to General Event Info -//! -//! \return None -//! -//***************************************************************************** -void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent) -{ - // - // Most of the general errors are not FATAL are are to be handled - // appropriately by the application - // - UART_PRINT("[GENERAL EVENT] - ID=[%d] Sender=[%d]\n\n", - pDevEvent->EventData.deviceEvent.status, - pDevEvent->EventData.deviceEvent.sender); -} - - -//***************************************************************************** -// -//! This function handles socket events indication -//! -//! \param[in] pSock - Pointer to Socket Event Info -//! -//! \return None -//! -//***************************************************************************** -void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) -{ - // - // This application doesn't work w/ socket - Events are not expected - // - switch( pSock->Event ) - { - case SL_SOCKET_TX_FAILED_EVENT: - switch( pSock->socketAsyncEvent.SockTxFailData.status) - { - case SL_ECLOSE: - UART_PRINT("[SOCK ERROR] - close socket (%d) operation " - "failed to transmit all queued packets\n\n", - pSock->socketAsyncEvent.SockTxFailData.sd); - break; - default: - UART_PRINT("[SOCK ERROR] - TX FAILED : socket %d , reason " - "(%d) \n\n", - pSock->socketAsyncEvent.SockTxFailData.sd, pSock->socketAsyncEvent.SockTxFailData.status); - break; - } - break; - - default: - UART_PRINT("[SOCK EVENT] - Unexpected Event [%x0x]\n\n",pSock->Event); - break; - } - -} - - -//***************************************************************************** -// -//! \brief This function handles ping report events -//! -//! \param[in] pPingReport - Ping report statistics -//! -//! \return None -//! -//***************************************************************************** -static void SimpleLinkPingReport(SlPingReport_t *pPingReport) -{ - SET_STATUS_BIT(g_ulStatus, STATUS_BIT_PING_DONE); - g_ulPingPacketsRecv = pPingReport->PacketsReceived; -} - -//***************************************************************************** -// SimpleLink Asynchronous Event Handlers -- End -//***************************************************************************** - - - -//***************************************************************************** -// -//! \brief This function initializes the application variables -//! -//! \param None -//! -//! \return None -//! -//***************************************************************************** -static void InitializeAppVariables() -{ - g_ulStatus = 0; - g_ulPingPacketsRecv = 0; - g_ulGatewayIP = 0; - memset(g_ucConnectionSSID,0,sizeof(g_ucConnectionSSID)); - memset(g_ucConnectionBSSID,0,sizeof(g_ucConnectionBSSID)); -} - - -//***************************************************************************** -//! \brief This function puts the device in its default state. It: -//! - Set the mode to STATION -//! - Configures connection policy to Auto and AutoSmartConfig -//! - Deletes all the stored profiles -//! - Enables DHCP -//! - Disables Scan policy -//! - Sets Tx power to maximum -//! - Sets power policy to normal -//! - Unregister mDNS services -//! - Remove all filters -//! -//! \param none -//! \return On success, zero is returned. On error, negative is returned -//***************************************************************************** - -static long ConfigureSimpleLinkToDefaultState() -{ - SlVersionFull ver = {0}; - _WlanRxFilterOperationCommandBuff_t RxFilterIdMask = {0}; - - unsigned char ucVal = 1; - unsigned char ucConfigOpt = 0; - unsigned char ucConfigLen = 0; - unsigned char ucPower = 0; - - long lRetVal = -1; - long lMode = -1; - - lMode = sl_Start(0, 0, 0); - ASSERT_ON_ERROR(lMode); - - // If the device is not in station-mode, try configuring it in station-mode - if (ROLE_STA != lMode) - { - if (ROLE_AP == lMode) - { - // If the device is in AP mode, we need to wait for this event - // before doing anything - while(!IS_IP_ACQUIRED(g_ulStatus)) - { -#ifndef SL_PLATFORM_MULTI_THREADED - _SlNonOsMainLoopTask(); -#endif - } - } - - // Switch to STA role and restart - lRetVal = sl_WlanSetMode(ROLE_STA); - ASSERT_ON_ERROR(lRetVal); - - lRetVal = sl_Stop(0xFF); - ASSERT_ON_ERROR(lRetVal); - - lRetVal = sl_Start(0, 0, 0); - ASSERT_ON_ERROR(lRetVal); - - // Check if the device is in station again - if (ROLE_STA != lRetVal) - { - // We don't want to proceed if the device is not coming up in STA-mode - ASSERT_ON_ERROR(DEVICE_NOT_IN_STATION_MODE); - } - } - - // Get the device's version-information - ucConfigOpt = SL_DEVICE_GENERAL_VERSION; - ucConfigLen = sizeof(ver); - lRetVal = sl_DevGet(SL_DEVICE_GENERAL_CONFIGURATION, &ucConfigOpt, - &ucConfigLen, (unsigned char *)(&ver)); - ASSERT_ON_ERROR(lRetVal); - - UART_PRINT("Host Driver Version: %s\n\r",SL_DRIVER_VERSION); - UART_PRINT("Build Version %d.%d.%d.%d.31.%d.%d.%d.%d.%d.%d.%d.%d\n\r", - ver.NwpVersion[0],ver.NwpVersion[1],ver.NwpVersion[2],ver.NwpVersion[3], - ver.ChipFwAndPhyVersion.FwVersion[0],ver.ChipFwAndPhyVersion.FwVersion[1], - ver.ChipFwAndPhyVersion.FwVersion[2],ver.ChipFwAndPhyVersion.FwVersion[3], - ver.ChipFwAndPhyVersion.PhyVersion[0],ver.ChipFwAndPhyVersion.PhyVersion[1], - ver.ChipFwAndPhyVersion.PhyVersion[2],ver.ChipFwAndPhyVersion.PhyVersion[3]); - - // Set connection policy to Auto + SmartConfig - // (Device's default connection policy) - lRetVal = sl_WlanPolicySet(SL_POLICY_CONNECTION, - SL_CONNECTION_POLICY(1, 0, 0, 0, 1), NULL, 0); - ASSERT_ON_ERROR(lRetVal); - - // Remove all profiles - lRetVal = sl_WlanProfileDel(0xFF); - ASSERT_ON_ERROR(lRetVal); - - - - // - // Device in station-mode. Disconnect previous connection if any - // The function returns 0 if 'Disconnected done', negative number if already - // disconnected Wait for 'disconnection' event if 0 is returned, Ignore - // other return-codes - // - lRetVal = sl_WlanDisconnect(); - if(0 == lRetVal) - { - // Wait - while(IS_CONNECTED(g_ulStatus)) - { -#ifndef SL_PLATFORM_MULTI_THREADED - _SlNonOsMainLoopTask(); -#endif - } - } - - // Enable DHCP client - lRetVal = sl_NetCfgSet(SL_IPV4_STA_P2P_CL_DHCP_ENABLE,1,1,&ucVal); - ASSERT_ON_ERROR(lRetVal); - - // Disable scan - ucConfigOpt = SL_SCAN_POLICY(0); - lRetVal = sl_WlanPolicySet(SL_POLICY_SCAN , ucConfigOpt, NULL, 0); - ASSERT_ON_ERROR(lRetVal); - - // Set Tx power level for station mode - // Number between 0-15, as dB offset from max power - 0 will set max power - ucPower = 0; - lRetVal = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, - WLAN_GENERAL_PARAM_OPT_STA_TX_POWER, 1, (unsigned char *)&ucPower); - ASSERT_ON_ERROR(lRetVal); - - // Set PM policy to normal - lRetVal = sl_WlanPolicySet(SL_POLICY_PM , SL_NORMAL_POLICY, NULL, 0); - ASSERT_ON_ERROR(lRetVal); - - // Unregister mDNS services - lRetVal = sl_NetAppMDNSUnRegisterService(0, 0); - ASSERT_ON_ERROR(lRetVal); - - // Remove all 64 filters (8*8) - memset(RxFilterIdMask.FilterIdMask, 0xFF, 8); - lRetVal = sl_WlanRxFilterSet(SL_REMOVE_RX_FILTER, (_u8 *)&RxFilterIdMask, - sizeof(_WlanRxFilterOperationCommandBuff_t)); - ASSERT_ON_ERROR(lRetVal); - - lRetVal = sl_Stop(SL_STOP_TIMEOUT); - ASSERT_ON_ERROR(lRetVal); - - InitializeAppVariables(); - - return lRetVal; // Success -} - -//***************************************************************************** -//! \brief This function checks the LAN connection by pinging the AP's gateway -//! -//! \param None -//! -//! \return 0 on success, negative error-code on error -//! -//***************************************************************************** -static long CheckLanConnection() -{ - SlPingStartCommand_t pingParams = {0}; - SlPingReport_t pingReport = {0}; - - long lRetVal = -1; - - CLR_STATUS_BIT(g_ulStatus, STATUS_BIT_PING_DONE); - g_ulPingPacketsRecv = 0; - - // Set the ping parameters - pingParams.PingIntervalTime = PING_INTERVAL; - pingParams.PingSize = PING_PKT_SIZE; - pingParams.PingRequestTimeout = PING_TIMEOUT; - pingParams.TotalNumberOfAttempts = NO_OF_ATTEMPTS; - pingParams.Flags = 0; - pingParams.Ip = g_ulGatewayIP; - - // Check for LAN connection - lRetVal = sl_NetAppPingStart((SlPingStartCommand_t*)&pingParams, SL_AF_INET, - (SlPingReport_t*)&pingReport, SimpleLinkPingReport); - ASSERT_ON_ERROR(lRetVal); - - // Wait for NetApp Event - while(!IS_PING_DONE(g_ulStatus)) - { -#ifndef SL_PLATFORM_MULTI_THREADED - _SlNonOsMainLoopTask(); -#endif - } - - if(0 == g_ulPingPacketsRecv) - { - //Problem with LAN connection - ASSERT_ON_ERROR(LAN_CONNECTION_FAILED); - } - - // LAN connection is successful - return SUCCESS; -} - - -//***************************************************************************** -//! \brief This function checks the internet connection by pinging -//! the external-host (HOST_NAME) -//! -//! \param None -//! -//! \return 0 on success, negative error-code on error -//! -//***************************************************************************** -static long CheckInternetConnection() -{ - SlPingStartCommand_t pingParams = {0}; - SlPingReport_t pingReport = {0}; - - unsigned long ulIpAddr = 0; - long lRetVal = -1; - - CLR_STATUS_BIT(g_ulStatus, STATUS_BIT_PING_DONE); - g_ulPingPacketsRecv = 0; - - // Set the ping parameters - pingParams.PingIntervalTime = PING_INTERVAL; - pingParams.PingSize = PING_PKT_SIZE; - pingParams.PingRequestTimeout = PING_TIMEOUT; - pingParams.TotalNumberOfAttempts = NO_OF_ATTEMPTS; - pingParams.Flags = 0; - pingParams.Ip = g_ulGatewayIP; - - // Get external host IP address - lRetVal = sl_NetAppDnsGetHostByName((signed char*)HOST_NAME, sizeof(HOST_NAME), - &ulIpAddr, SL_AF_INET); - ASSERT_ON_ERROR(lRetVal); - - // Replace the ping address to match HOST_NAME's IP address - pingParams.Ip = ulIpAddr; - - // Try to ping HOST_NAME - lRetVal = sl_NetAppPingStart((SlPingStartCommand_t*)&pingParams, SL_AF_INET, - (SlPingReport_t*)&pingReport, SimpleLinkPingReport); - ASSERT_ON_ERROR(lRetVal); - - // Wait - while(!IS_PING_DONE(g_ulStatus)) - { - // Wait for Ping Event -#ifndef SL_PLATFORM_MULTI_THREADED - _SlNonOsMainLoopTask(); -#endif - } - - if (0 == g_ulPingPacketsRecv) - { - // Problem with internet connection - ASSERT_ON_ERROR(INTERNET_CONNECTION_FAILED); - } - - // Internet connection is successful - return SUCCESS; -} - - -//**************************************************************************** -// -//! \brief Connecting to a WLAN Accesspoint -//! -//! This function connects to the required AP (SSID_NAME) with Security -//! parameters specified in te form of macros at the top of this file -//! -//! \param None -//! -//! \return None -//! -//! \warning If the WLAN connection fails or we don't aquire an IP -//! address, It will be stuck in this function forever. -// -//**************************************************************************** -static long WlanConnect() -{ - SlSecParams_t secParams = {0}; - long lRetVal = 0; - - secParams.Key = (signed char*)SECURITY_KEY; - secParams.KeyLen = strlen(SECURITY_KEY); - secParams.Type = SECURITY_TYPE; - - lRetVal = sl_WlanConnect((signed char*)SSID_NAME, strlen(SSID_NAME), 0, &secParams, 0); - ASSERT_ON_ERROR(lRetVal); - - // Wait for WLAN Event - while((!IS_CONNECTED(g_ulStatus)) || (!IS_IP_ACQUIRED(g_ulStatus))) - { - // Toggle LEDs to Indicate Connection Progress - GPIO_IF_LedOff(MCU_IP_ALLOC_IND); - MAP_UtilsDelay(800000); - GPIO_IF_LedOn(MCU_IP_ALLOC_IND); - MAP_UtilsDelay(800000); - } - - return SUCCESS; - -} - -//**************************************************************************** -// -//! \brief Start simplelink, connect to the ap and run the ping test -//! -//! This function starts the simplelink, connect to the ap and start the ping -//! test on the default gateway for the ap -//! -//! \param[in] pvParameters - Pointer to the list of parameters that -//! can bepassed to the task while creating it -//! -//! \return None -// -//**************************************************************************** -void WlanStationMode( void *pvParameters ) -{ - - long lRetVal = -1; - InitializeAppVariables(); - - // - // Following function configure the device to default state by cleaning - // the persistent settings stored in NVMEM (viz. connection profiles & - // policies, power policy etc) - // - // Applications may choose to skip this step if the developer is sure - // that the device is in its default state at start of applicaton - // - // Note that all profiles and persistent settings that were done on the - // device will be lost - // - lRetVal = ConfigureSimpleLinkToDefaultState(); - if(lRetVal < 0) - { - if (DEVICE_NOT_IN_STATION_MODE == lRetVal) - { - UART_PRINT("Failed to configure the device in its default state\n\r"); - } - - LOOP_FOREVER(); - } - - UART_PRINT("Device is configured in default state \n\r"); - - // - // Assumption is that the device is configured in station mode already - // and it is in its default state - // - lRetVal = sl_Start(0, 0, 0); - if (lRetVal < 0 || ROLE_STA != lRetVal) - { - UART_PRINT("Failed to start the device \n\r"); - LOOP_FOREVER(); - } - - UART_PRINT("Device started as STATION \n\r"); - - // - //Connecting to WLAN AP - // - lRetVal = WlanConnect(); - if(lRetVal < 0) - { - UART_PRINT("Failed to establish connection w/ an AP \n\r"); - LOOP_FOREVER(); - } - - UART_PRINT("Connection established w/ AP and IP is aquired \n\r"); - UART_PRINT("Pinging...! \n\r"); - - // - // Checking the Lan connection by pinging to AP gateway - // - lRetVal = CheckLanConnection(); - if(lRetVal < 0) - { - UART_PRINT("Device couldn't ping the gateway \n\r"); - LOOP_FOREVER(); - } - - // Turn on GREEN LED when device gets PING response from AP - GPIO_IF_LedOn(MCU_EXECUTE_SUCCESS_IND); - - // - // Checking the internet connection by pinging to external host - // - lRetVal = CheckInternetConnection(); - if(lRetVal < 0) - { - UART_PRINT("Device couldn't ping the external host \n\r"); - LOOP_FOREVER(); - } - - // Turn on ORAGE LED when device gets PING response from AP - GPIO_IF_LedOn(MCU_ORANGE_LED_GPIO); - - UART_PRINT("Device pinged both the gateway and the external host \n\r"); - - UART_PRINT("WLAN STATION example executed successfully \n\r"); - - // - // power off the network processor - // - lRetVal = sl_Stop(SL_STOP_TIMEOUT); - - LOOP_FOREVER(); - -} -//***************************************************************************** -// -//! Application startup display on UART -//! -//! \param none -//! -//! \return none -//! -//***************************************************************************** -static void -DisplayBanner(char * AppName) -{ - - UART_PRINT("\n\n\n\r"); - UART_PRINT("\t\t *************************************************\n\r"); - UART_PRINT("\t\t CC3200 %s Application \n\r", AppName); - UART_PRINT("\t\t *************************************************\n\r"); - UART_PRINT("\n\n\n\r"); -} -//***************************************************************************** -// -//! \brief Board Initialization & Configuration -//! -//! \param None -//! -//! \return None -// -//***************************************************************************** -static void -BoardInit(void) -{ -// In case of TI-RTOS vector table is initialize by OS itself -#ifndef USE_TIRTOS - // - // Set vector table base - // -#if defined(ccs) || defined(gcc) - MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]); -#endif -#if defined(ewarm) - MAP_IntVTableBaseSet((unsigned long)&__vector_table); -#endif -#endif //USE_TIRTOS - - // The kernel is initialized but not started yet, this means that - // main() is executing with absolute priority but interrupts are already enabled. - osKernelInitialize(); - - // - // Enable Processor - // - MAP_IntMasterEnable(); - MAP_IntEnable(FAULT_SYSTICK); - - PRCMCC3200MCUInit(); -} - - -//***************************************************************************** -// MAIN FUNCTION -//***************************************************************************** -void main() -{ - long lRetVal = -1; - - // HAL initialization, this also initializes the configured device drivers - // and performs the board-specific initializations. - halInit(); - - // - // Board Initialization - // - BoardInit(); - - // - // configure the GPIO pins for LEDs,UART - // - PinMuxConfig(); - - // - // Configure the UART - // -#ifndef NOTERM - InitTerm(); -#endif //NOTERM - - // - // Display Application Banner - // - DisplayBanner(APPLICATION_NAME); - - // - // Configure all 3 LEDs - // - GPIO_IF_LedConfigure(LED1|LED2|LED3); - - // switch off all LEDs - GPIO_IF_LedOff(MCU_ALL_LED_IND); - - // - // Start the SimpleLink Host - // - lRetVal = VStartSimpleLinkSpawnTask(SPAWN_TASK_PRIORITY); - if(lRetVal < 0) - { - ERR_PRINT(lRetVal); - LOOP_FOREVER(); - } - - // - // Start the WlanStationMode task - // - lRetVal = osi_TaskCreate( WlanStationMode, \ - (const signed char*)"Wlan Station Task", \ - OSI_STACK_SIZE, NULL, 1, NULL ); - if(lRetVal < 0) - { - ERR_PRINT(lRetVal); - LOOP_FOREVER(); - } - - // - // Start the task scheduler - // - osi_start(); - } - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h deleted file mode 100644 index 9acef485fe..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf.h +++ /dev/null @@ -1,76 +0,0 @@ -// -// Copyright (c) 2018 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - -#ifndef MCUCONF_H -#define MCUCONF_H - -/* - * CC3200 drivers configuration. - * The following settings override the default settings present in - * the various device driver implementation headers. - * Note that the settings for each driver only have effect if the whole - * driver is enabled in halconf.h. - * - * IRQ priorities: - * 7...0 Lowest...Highest. - */ - -#define TICC3200_MCUCONF - - -/* - * HAL driver system settings. - */ -#define TICC3200_OSCSRC SYSCTL_RCC2_OSCSRC2_MO -#define TICC3200_MOSC_ENABLE TRUE -#define TICC3200_DIV400_VALUE 1 -#define TICC3200_SYSDIV_VALUE 2 -#define TICC3200_USESYSDIV_ENABLE FALSE -#define TICC3200_SYSDIV2LSB_ENABLE FALSE -#define TICC3200_BYPASS_VALUE 0 -#define TICC3200_PWM_FIELDS (SYSCTL_RCC_USEPWMDIV | \ - SYSCTL_RCC_PWMDIV_8) - -/* - * GPIO driver system settings. - */ -#define TICC3200_GPIO_GPIOA_USE_AHB TRUE -#define TICC3200_GPIO_GPIOB_USE_AHB TRUE -#define TICC3200_GPIO_GPIOC_USE_AHB TRUE -#define TICC3200_GPIO_GPIOD_USE_AHB TRUE -#define TICC3200_GPIO_GPIOE_USE_AHB TRUE -#define TICC3200_GPIO_GPIOF_USE_AHB TRUE - -/* - * GPT driver system settings. - */ -#define TICC3200_GPT_USE_GPT0 FALSE -#define TICC3200_GPT_USE_GPT1 FALSE -#define TICC3200_GPT_USE_GPT2 FALSE -#define TICC3200_GPT_USE_GPT3 FALSE - -#define TICC3200_GPT_GPT0A_IRQ_PRIORITY 7 -#define TICC3200_GPT_GPT1A_IRQ_PRIORITY 7 -#define TICC3200_GPT_GPT2A_IRQ_PRIORITY 7 -#define TICC3200_GPT_GPT3A_IRQ_PRIORITY 7 -/* - * SERIAL driver system settings. - */ -#define TICC3200_SERIAL_USE_UART0 TRUE -#define TICC3200_SERIAL_USE_UART1 FALSE -#define TICC3200_SERIAL_UART0_PRIORITY 5 -#define TICC3200_SERIAL_UART1_PRIORITY 5 - -/* - * ST driver system settings. - */ -#define TICC3200_ST_IRQ_PRIORITY 2 -#define TICC3200_ST_TIMER_NUMBER 0 -#define TICC3200_ST_TIMER_LETTER A - -// header for nanoFramework overlay drivers -#include "mcuconf_nf.h" - -#endif /* MCUCONF_H */ diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h deleted file mode 100644 index 37dc82fd91..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/mcuconf_nf.h +++ /dev/null @@ -1,9 +0,0 @@ -// -// Copyright (c) 2018 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - -#ifndef _MCUCONF_NF_H_ -#define _MCUCONF_NF_H_ - -#endif // _MCUCONF_NF_H_ diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.c deleted file mode 100644 index 8d42df1685..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.c +++ /dev/null @@ -1,91 +0,0 @@ -//***************************************************************************** -// pinmux.c -// -// configure the device pins for different peripheral signals -// -// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ -// -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -// This file was automatically generated on 7/21/2014 at 3:06:20 PM -// by TI PinMux version 3.0.334 -// -//***************************************************************************** - -#include "pinmux.h" -#include "hw_types.h" -#include "hw_memmap.h" -#include "hw_gpio.h" -#include "pin.h" -#include "rom.h" -#include "rom_map.h" -#include "gpio.h" -#include "prcm.h" - -//***************************************************************************** -void -PinMuxConfig(void) -{ - // - // Enable Peripheral Clocks - // - MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK); - MAP_PRCMPeripheralClkEnable(PRCM_UARTA0, PRCM_RUN_MODE_CLK); - - // - // Configure PIN_55 for UART0 UART0_TX - // - MAP_PinTypeUART(PIN_55, PIN_MODE_3); - - // - // Configure PIN_57 for UART0 UART0_RX - // - MAP_PinTypeUART(PIN_57, PIN_MODE_3); - - // - // Configure PIN_64 for GPIOOutput - // - MAP_PinTypeGPIO(PIN_64, PIN_MODE_0, false); - MAP_GPIODirModeSet(GPIOA1_BASE, 0x2, GPIO_DIR_MODE_OUT); - - // - // Configure PIN_01 for GPIOOutput - // - MAP_PinTypeGPIO(PIN_01, PIN_MODE_0, false); - MAP_GPIODirModeSet(GPIOA1_BASE, 0x4, GPIO_DIR_MODE_OUT); - - // - // Configure PIN_02 for GPIOOutput - // - MAP_PinTypeGPIO(PIN_02, PIN_MODE_0, false); - MAP_GPIODirModeSet(GPIOA1_BASE, 0x8, GPIO_DIR_MODE_OUT); -} diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.h b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.h deleted file mode 100644 index 8d560a61ae..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/pinmux.h +++ /dev/null @@ -1,49 +0,0 @@ -//***************************************************************************** -// pinmux.h -// -// function prototype for pinmuxconfig -// -// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ -// -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -// This file was automatically generated on 7/21/2014 at 3:06:20 PM -// by TI PinMux version 3.0.334 -// -//***************************************************************************** - -#ifndef __PINMUX_H__ -#define __PINMUX_H__ - -extern void PinMuxConfig(void); - -#endif // __PINMUX_H__ diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/target_board.h.in b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/target_board.h.in deleted file mode 100644 index 48da76acbc..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/nanoCLR/target_board.h.in +++ /dev/null @@ -1,19 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_BOARD_NANOCLR_H_ -#define _TARGET_BOARD_NANOCLR_H_ - -#include -#include - -#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION - -#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c deleted file mode 100644 index e366395cf7..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/osi_chibios.c +++ /dev/null @@ -1,791 +0,0 @@ -//***************************************************************************** -// osi_chibios.c -// -// Interface APIs for ChibiOS function calls -// -// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ -// -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - - -#include -#include -#include -#include -#include -#include - -#include "rom.h" -#include "rom_map.h" -#include "hw_types.h" -#include "interrupt.h" - -//Local function definition -static void vSimpleLinkSpawnTask( void *pvParameters ); - -// Queue Handler -// Queue size -#define slQUEUE_SIZE 3 - -osMessageQDef(simpleLink_mailbox, slQUEUE_SIZE, tSimpleLinkSpawnMsg); -osMessageQId(simpleLink_mailbox_id); - -osThreadId SimpleLinkSpawnTaskHndl; - - -/*! - \brief This function registers an interrupt in NVIC table - - The sync object is used for synchronization between different thread or ISR and - a thread. - - \param iIntrNum - Interrupt number to register - \param pEntry - Pointer to the interrupt handler - \param ucPriority - priority of the interrupt - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_InterruptRegister(int iIntrNum,P_OSI_INTR_ENTRY pEntry,unsigned char ucPriority) -{ - MAP_IntRegister(iIntrNum,(void(*)(void))pEntry); - MAP_IntPrioritySet(iIntrNum, ucPriority); - MAP_IntEnable(iIntrNum); - return OSI_OK; -} - -/*! - \brief This function De registers an interrupt in NVIC table - - - \param iIntrNum - Interrupt number to De register - - \return none - \note - \warning -*/ - -void osi_InterruptDeRegister(int iIntrNum) -{ - MAP_IntDisable(iIntrNum); - MAP_IntUnregister(iIntrNum); -} - -/*! - \brief This function creates a sync object - - The sync object is used for synchronization between different thread or ISR and - a thread. - - \param pSyncObj - pointer to the sync object control block - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_SyncObjCreate(OsiSyncObj_t* pSyncObj) -{ - if(pSyncObj == NULL) - { - return OSI_INVALID_PARAMS; - } - - osSemaphoreId semaphore_id = osSemaphoreCreate(NULL, 1); - if (semaphore_id == NULL) - { - *pSyncObj = NULL; - return OSI_FAILURE; - } - - *pSyncObj = (OsiSyncObj_t)semaphore_id; - - return OSI_OK; -} - -/*! - \brief This function deletes a sync object - - \param pSyncObj - pointer to the sync object control block - - \return upon successful deletion the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_SyncObjDelete(OsiSyncObj_t* pSyncObj) -{ - if(pSyncObj == NULL) - { - return OSI_INVALID_PARAMS; - } - - osSemaphoreDelete((osSemaphoreId*) pSyncObj); - - return OSI_OK; -} - -/*! - \brief This function generates a sync signal for the object. - - All suspended threads waiting on this sync object are resumed - - \param pSyncObj - pointer to the sync object control block - - \return upon successful signaling the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note the function could be called from ISR context - \warning -*/ -OsiReturnVal_e osi_SyncObjSignal(OsiSyncObj_t* pSyncObj) -{ - if(pSyncObj == NULL) - { - return OSI_INVALID_PARAMS; - } - - osSemaphoreRelease((osSemaphoreId)*pSyncObj); - - return OSI_OK; -} -/*! - \brief This function generates a sync signal for the object - from ISR context. - - All suspended threads waiting on this sync object are resumed - - \param pSyncObj - pointer to the sync object control block - - \return upon successful signalling the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note the function is called from ISR context - \warning -*/ -OsiReturnVal_e osi_SyncObjSignalFromISR(OsiSyncObj_t* pSyncObj) -{ - if(pSyncObj == NULL) - { - return OSI_INVALID_PARAMS; - } - - osSemaphoreRelease((osSemaphoreId)*pSyncObj); - - return OSI_OK; -} - -/*! - \brief This function waits for a sync signal of the specific sync object - - \param pSyncObj - pointer to the sync object control block - \param Timeout - numeric value specifies the maximum number of mSec to - stay suspended while waiting for the sync signal - Currently, the simple link driver uses only two values: - - OSI_WAIT_FOREVER - - OSI_NO_WAIT - - \return upon successful reception of the signal within the timeout window return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_SyncObjWait(OsiSyncObj_t* pSyncObj , OsiTime_t Timeout) -{ - if(pSyncObj == NULL) - { - return OSI_INVALID_PARAMS; - } - - if(osSemaphoreWait((osSemaphoreId)*pSyncObj, (uint32_t) Timeout) != osOK) - { - return OSI_OPERATION_FAILED; - } - - return OSI_OK; -} - -/*! - \brief This function clears a sync object - - \param pSyncObj - pointer to the sync object control block - - \return upon successful clearing the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_SyncObjClear(OsiSyncObj_t* pSyncObj) -{ - if(pSyncObj == NULL) - { - return OSI_INVALID_PARAMS; - } - - if (OSI_OK == osi_SyncObjWait(pSyncObj,0) ) - { - return OSI_OK; - } - else - { - return OSI_OPERATION_FAILED; - } -} - -/*! - \brief This function creates a locking object. - - The locking object is used for protecting a shared resources between different - threads. - - \param pLockObj - pointer to the locking object control block - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_LockObjCreate(OsiLockObj_t* pLockObj) -{ - if(pLockObj == NULL) - { - return OSI_INVALID_PARAMS; - } - - - osSemaphoreId semaphore_id = osSemaphoreCreate(NULL, 1); - if (semaphore_id == NULL) - { - *pLockObj = NULL; - return OSI_FAILURE; - } - - *pLockObj = (OsiLockObj_t)semaphore_id; - - return OSI_OK; -} - -/*! - \brief This function creates a Task. - - Creates a new Task and add it to the last of tasks that are ready to run - - \param pEntry - pointer to the Task Function - \param pcName - Task Name String - \param usStackDepth - Stack Size in bytes - \param pvParameters - pointer to structure to be passed to the Task Function - \param uxPriority - Task Priority - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_TaskCreate(P_OSI_TASK_ENTRY pEntry,const signed char * const pcName, - unsigned short usStackDepth, void *pvParameters, - unsigned long uxPriority,OsiTaskHandle* pTaskHandle) -{ - - osThreadDef_t threadDefinition; - threadDefinition.stacksize = usStackDepth; - threadDefinition.tpriority = uxPriority; - threadDefinition.name = pcName; - - osThreadId id = osThreadCreate(&threadDefinition, pvParameters); - - if(id != NULL) - { - *pTaskHandle = (OsiTaskHandle)id; - } - - if(id == NULL) - { - return OSI_FAILURE; - } - - return OSI_OK; -} - -/*! - \brief This function Deletes a Task. - - Deletes a Task and remove it from list of running task - - \param pTaskHandle - Task Handle - - \note - \warning -*/ -void osi_TaskDelete(OsiTaskHandle* pTaskHandle) -{ - osThreadTerminate((osThreadId)pTaskHandle); -} - -/*! - \brief This function deletes a locking object. - - \param pLockObj - pointer to the locking object control block - - \return upon successful deletion the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_LockObjDelete(OsiLockObj_t* pLockObj) -{ - osSemaphoreDelete((osSemaphoreId)*pLockObj ); - - return OSI_OK; -} - -/*! - \brief This function locks a locking object. - - All other threads that call this function before this thread calls - the osi_LockObjUnlock would be suspended - - \param pLockObj - pointer to the locking object control block - \param Timeout - numeric value specifies the maximum number of mSec to - stay suspended while waiting for the locking object - Currently, the simple link driver uses only two values: - - OSI_WAIT_FOREVER - - OSI_NO_WAIT - - - \return upon successful reception of the locking object the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_LockObjLock(OsiLockObj_t* pLockObj , OsiTime_t Timeout) -{ - if(pLockObj == NULL) - { - return OSI_INVALID_PARAMS; - } - - //Take Semaphore - if(osSemaphoreWait((osSemaphoreId)*pLockObj, (uint32_t) Timeout) != osOK) - { - return OSI_OPERATION_FAILED; - } - - return OSI_OK; -} - -/*! - \brief This function unlock a locking object. - - \param pLockObj - pointer to the locking object control block - - \return upon successful unlocking the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -OsiReturnVal_e osi_LockObjUnlock(OsiLockObj_t* pLockObj) -{ - - if(NULL == pLockObj) - { - return OSI_INVALID_PARAMS; - } - - //Release Semaphore - if(osSemaphoreRelease((osSemaphoreId)*pLockObj) == osOK) - { - return OSI_OK; - } - else - { - return OSI_OPERATION_FAILED; - } -} - -/*! - \brief This function call the pEntry callback from a different context - - \param pEntry - pointer to the entry callback function - - \param pValue - pointer to any type of memory structure that would be - passed to pEntry callback from the execution thread. - - \param flags - execution flags - reserved for future usage - - \return upon successful registration of the spawn the function should return 0 - (the function is not blocked till the end of the execution of the function - and could be returned before the execution is actually completed) - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ - -OsiReturnVal_e osi_Spawn(P_OSI_SPAWN_ENTRY pEntry , void* pValue , unsigned long flags) -{ - tSimpleLinkSpawnMsg Msg; - Msg.pEntry = pEntry; - Msg.pValue = pValue; - - if(osMessagePut(simpleLink_mailbox_id, &Msg, osWaitForever) == osOK) - { - return OSI_OK; - } - - return OSI_OPERATION_FAILED; -} - -/*! - \brief This is the simplelink spawn task to call SL callback from a different context - - \param pvParameters - pointer to the task parameter - - \return void - \note - \warning -*/ -void vSimpleLinkSpawnTask(void *pvParameters) -{ - tSimpleLinkSpawnMsg* Msg; - osEvent event; - - for(;;) - { - event = osMessageGet(simpleLink_mailbox_id, osWaitForever); - if(event.status == osEventMessage) - { - Msg = (tSimpleLinkSpawnMsg*)event.value.p; - Msg->pEntry(Msg->pValue); - } - } -} - -/*! - \brief This is the API to create SL spawn task and create the SL queue - - \param uxPriority - task priority - - \return void - \note - \warning -*/ -OsiReturnVal_e VStartSimpleLinkSpawnTask(unsigned long uxPriority) -{ - simpleLink_mailbox_id = osMessageCreate(osMessageQ(simpleLink_mailbox), NULL); - - osThreadDef(vSimpleLinkSpawnTask, uxPriority, 2048, "SimpleLinkTask"); - - SimpleLinkSpawnTaskHndl = osThreadCreate(osThread(vSimpleLinkSpawnTask), NULL); - if (SimpleLinkSpawnTaskHndl == NULL) - { - return OSI_OPERATION_FAILED; - } - - return OSI_OK; -} - -/*! - \brief This is the API to delete SL spawn task and delete the SL queue - - \param none - - \return void - \note - \warning -*/ -void VDeleteSimpleLinkSpawnTask( void ) -{ - osThreadTerminate(SimpleLinkSpawnTaskHndl); -} - -/*! - \brief This function to call the memory allocation function of the RTOS - - \param pMem - pointer to the memory which needs to be freed - - \return - void * - \note - \warning -*/ - -void * mem_Malloc(unsigned long Size) -{ - return ( void * )chHeapAlloc(NULL, Size); -} - -/*! - \brief This function to call the memory de-allocation function of the RTOS - - \param pMem - pointer to the memory which needs to be freed - - \return - void - \note - \warning -*/ -void mem_Free(void *pMem) -{ - chHeapFree(pMem); -} - -/*! - \brief This function call the memset function - \param pBuf - pointer to the memory to be fill - \param Val - Value to be fill - \param Size - Size of the memory which needs to be fill - - \return - void - \note - \warning -*/ - -void mem_set(void *pBuf, int Val, size_t Size) -{ - memset(pBuf, Val, Size); -} - -/*! - \brief This function call the memset function - \param pDst - pointer to the destination - \param pSrc - pointer to the source - \param Size - Size of the memory which needs to be copy - - \return - void - \note - \warning -*/ -void mem_copy(void *pDst, void *pSrc, size_t Size) -{ - memcpy(pDst, pSrc, Size); -} - - -/*! - \brief This function use to entering into critical section - \param void - \return - void - \note - \warning -*/ - -unsigned long osi_EnterCritical(void) -{ - chSysLock(); - return 0; -} - -/*! - \brief This function use to exit critical section - \param void - \return - void - \note - \warning -*/ - -void osi_ExitCritical(unsigned long ulKey) -{ - chSysUnlock(); -} - -/*! - \brief This function is used to create the MsgQ - - \param pMsgQ - pointer to the message queue - \param pMsgQName - msg queue name - \param MsgSize - size of message on the queue - \param MaxMsgs - max. number of msgs that the queue can hold - - \return - OsiReturnVal_e - \note - \warning -*/ -OsiReturnVal_e osi_MsgQCreate(OsiMsgQ_t* pMsgQ , - char* pMsgQName, - unsigned long MsgSize, - unsigned long MaxMsgs) -{ - - if(NULL == pMsgQ) - { - return OSI_INVALID_PARAMS; - } - - *pMsgQ = (OsiMsgQ_t)osMessageCreate((osMessageQDef_t*)pMsgQ, NULL); - - if (*pMsgQ == NULL) - { - return OSI_OPERATION_FAILED; - } - - return OSI_OK; -} -/*! - \brief This function is used to delete the MsgQ - - \param pMsgQ - pointer to the message queue - - \return - OsiReturnVal_e - \note - \warning -*/ -OsiReturnVal_e osi_MsgQDelete(OsiMsgQ_t* pMsgQ) -{ - return OSI_OK; -} -/*! - \brief This function is used to write data to the MsgQ - - \param pMsgQ - pointer to the message queue - \param pMsg - pointer to the Msg strut to read into - \param Timeout - timeout to wait for the Msg to be available - - \return - OsiReturnVal_e - \note - \warning -*/ - -OsiReturnVal_e osi_MsgQWrite(OsiMsgQ_t* pMsgQ, void* pMsg , OsiTime_t Timeout) -{ - - if(NULL == pMsgQ) - { - return OSI_INVALID_PARAMS; - } - - if(osMessagePut((osMessageQDef_t*)pMsgQ, pMsg, osWaitForever) == osOK) - { - return OSI_OK; - } - - return OSI_OPERATION_FAILED; -} -/*! - \brief This function is used to read data from the MsgQ - - \param pMsgQ - pointer to the message queue - \param pMsg - pointer to the Msg strut to read into - \param Timeout - timeout to wait for the Msg to be available - - \return - OsiReturnVal_e - \note - \warning -*/ - -OsiReturnVal_e osi_MsgQRead(OsiMsgQ_t* pMsgQ, void* pMsg , OsiTime_t Timeout) -{ - osEvent event; - - - if(NULL == pMsgQ) - { - return OSI_INVALID_PARAMS; - } - - event = osMessageGet((osMessageQDef_t*)pMsgQ, Timeout); - if(event.status == osEventMessage) - { - pMsg = event.value.p; - - return OSI_OK; - } - - return OSI_OPERATION_FAILED; -} - -/*! - \brief This function used to suspend the task for the specified number of milli secs - \param MilliSecs - Time in millisecs to suspend the task - \return - void - \note - \warning -*/ -void osi_Sleep(unsigned int MilliSecs) -{ - osDelay(MilliSecs); -} - -/*! - \brief This function used to disable the tasks - \param - void - \return - Key with the suspended tasks - \note - \warning -*/ -unsigned long osi_TaskDisable(void) -{ - return OSI_OK; -} - -/*! - \brief This function used to start the scheduler - \param void - \return - void - \note - \warning -*/ -void osi_start() -{ - osKernelStart(); -} - -/*! - \brief This function used to resume all the tasks - \param key - returned from suspend tasks - \return - void - \note - \warning -*/ -void osi_TaskEnable(unsigned long key) -{ - -} - -/*! - \brief This function used to save the OS context before sleep - \param void - \return - void - \note - \warning -*/ -void osi_ContextSave() -{ - -} -/*! - \brief This function used to restore the OS context after sleep - \param void - \return - void - \note - \warning -*/ -void osi_ContextRestore() -{ - -} diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.c b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.c deleted file mode 100644 index f3374923e4..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.c +++ /dev/null @@ -1,31 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// -#include -#include -#include "target_board.h" -#include "target_common.h" - -HAL_SYSTEM_CONFIG HalSystemConfig = -{ - { true }, // HAL_DRIVER_CONFIG_HEADER Header; - - //--// - - { // unsigned int DebuggerPorts[MAX_DEBUGGERS]; - 0//ConvertCOM_DebugHandle(0), - }, - - { - 0//ConvertCOM_DebugHandle(0), - }, - - 0,//ConvertCOM_DebugHandle(0), - 115200, - 0, // STDIO = COM2 or COM1 - - { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, - { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } -}; diff --git a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.h.in b/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.h.in deleted file mode 100644 index 4309fa60bd..0000000000 --- a/targets/CMSIS-OS/ChibiOS/TI_CC3200_LAUNCHPAD/target_common.h.in +++ /dev/null @@ -1,33 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - -////////////////////////////////////////////////////////////////////////////// -// This file was automatically generated by a tool. // -// Any changes you make here will be overwritten when it's generated again. // -////////////////////////////////////////////////////////////////////////////// - -#ifndef _TARGET_COMMON_H_ -#define _TARGET_COMMON_H_ - -#include - -///////////////////////////////////////////////////////////////////////////////////////// -// The following addresses and sizes should be filled in according to the SoC data-sheet -// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR - -// RAM base address -#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0) -// RAM size -#define RAM1_MEMORY_Size ((uint32_t)0x00020000) - -// FLASH base address -#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) -// FLASH size -#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) - -///////////////////////////////////////////////////////////////////////////////////////// - - -#endif /* _TARGET_COMMON_H_ */ diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/CMakeLists.txt b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/CMakeLists.txt deleted file mode 100644 index edea1a2e31..0000000000 --- a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/CMakeLists.txt +++ /dev/null @@ -1,250 +0,0 @@ -# -# Copyright (c) 2017 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# - -cmake_minimum_required(VERSION 3.0) -ENABLE_LANGUAGE(ASM) - -# add header files with common OS definitions and board definitions specific for each image -# configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" -# "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) -configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" - "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) -configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" - "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) - -# set(NANOBOOTER_PROJECT_NAME "nanoBooter") -set(NANOCLR_PROJECT_NAME "nanoCLR") - -find_package(BuildUtils REQUIRED) -find_package(CHIBIOS REQUIRED) -find_package(ChibiOSnfOverlay REQUIRED) -find_package(WireProtocol REQUIRED) - -# packages for nanoFramework libraries -####################################### -# mandatory -find_package(NF_CoreCLR REQUIRED) - -####################################### -# optional - -# ChibiOS contrib repo -if(CHIBIOS_CONTRIB_REQUIRED) - find_package(ChibiOS-Contrib REQUIRED) -endif() - -# nF feature: debugger -if(NF_FEATURE_DEBUGGER) - find_package(NF_Debugger REQUIRED) - find_package(NF_Diagnostics REQUIRED) -endif() - -# # nF feature: networking -# if(USE_NETWORKING_OPTION) -# find_package(CHIBIOS_LWIP REQUIRED) -# find_package(NF_NETWORKING REQUIRED) -# endif() - -# # nF feature: filesystem -# if(USE_FILESYSTEM_OPTION) -# find_package(CHIBIOS_FATFS REQUIRED) -# endif() - -# # security provider is mbedTLS -# if(NF_SECURITY_MBEDTLS) -# find_package(mbedTLS REQUIRED) -# endif() - -####################################### - -add_subdirectory("common") -# add_subdirectory("nanoBooter") -add_subdirectory("nanoCLR") - -####################### -# nanoBooter executable - -# add_executable( -# # executables for project, project sources -# ${NANOBOOTER_PROJECT_NAME}.elf - -# "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" - -# # need to add configuration manager to allow get/store configuration blocks -# "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager.c" - -# ${COMMON_PROJECT_SOURCES} -# ${NANOBOOTER_PROJECT_SOURCES} - -# ${TARGET_CMSIS_COMMON_SOURCES} -# ${TARGET_CMSIS_NANOBOOTER_SOURCES} - -# ${TARGET_CHIBIOS_COMMON_SOURCES} -# ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} - -# ${CHIBIOS_SOURCES} -# ${ChibiOSnfOverlay_SOURCES} - -# ${WireProtocol_SOURCES} -# ) - -####################### -# nanoCLR executable - -add_executable( - # executables for project, project sources - ${NANOCLR_PROJECT_NAME}.elf - - "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" - - ${COMMON_PROJECT_SOURCES} - ${NANOCLR_PROJECT_SOURCES} - - ${TARGET_CMSIS_COMMON_SOURCES} - ${TARGET_CMSIS_NANOCLR_SOURCES} - - ${TARGET_CHIBIOS_COMMON_SOURCES} - ${TARGET_CHIBIOS_NANOCLR_SOURCES} - - ${CHIBIOS_SOURCES} - ${CHIBIOS_CONTRIB_SOURCES} - ${ChibiOSnfOverlay_SOURCES} - - # ${WireProtocol_SOURCES} - - # sources for nanoFramework libraries - "${NF_CoreCLR_SOURCES}" - "${NF_Debugger_SOURCES}" - "${NF_Diagnostics_SOURCES}" - - # # sources for ChibiOS FatFS - # "${CHIBIOS_FATFS_SOURCES}" - - # # sources for nanoFramework Network LWIP, Sockets and TLS - # "${CHIBIOS_LWIP_SOURCES}" - # "${NF_Networking_SOURCES}" - # "${mbedTLS_SOURCES}" - - # sources for nanoFramework APIs - "${TARGET_NANO_APIS_SOURCES}" -) - -# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) -# add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) -add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) - -# # add dependencies from CHIBIOS_NETWORK_COMPONENTS (this is required to make sure that ChibiOS network components are unzip at the proper locations before the build starts) -# # only required if networking is ON -# if(USE_NETWORKING_OPTION) -# add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) -# add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) - -# # add dependency for security provider mbedTLS -# if(NF_SECURITY_MBEDTLS) -# add_dependencies(${NANOCLR_PROJECT_NAME}.elf mbedTLS) -# endif() -# endif() - -# # add dependencies from CHIBIOS_FILESYSTEM_COMPONENTS (this is required to make sure that ChibiOS filesystem components are unzip at the proper locations before the build starts) -# # only required if filesystem is ON -# if(USE_FILESYSTEM_OPTION) -# add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) -# add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) -# endif() - -# include common directories -include_directories( - "${CMAKE_CURRENT_BINARY_DIR}" - ${CMAKE_CURRENT_SOURCE_DIR} - ${CMAKE_CURRENT_SOURCE_DIR}/common - ${PROJECT_SOURCE_DIR}/src/CLR/Core - ${PROJECT_SOURCE_DIR}/src/CLR/Include - ${PROJECT_SOURCE_DIR}/src/HAL/Include - ${PROJECT_SOURCE_DIR}/src/PAL/Include - - ${WireProtocol_INCLUDE_DIRS} - ${CHIBIOS_INCLUDE_DIRS} - ${ChibiOSnfOverlay_INCLUDE_DIRS} - ${CHIBIOS_CONTRIB_INCLUDE_DIRS} - - ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} - ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} -) - -# # include directories for nanoBooter -# target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC -# "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" -# ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter - -# ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} -# ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} - -# # includes for ChibiOS LwIP -# "${CHIBIOS_LWIP_INCLUDE_DIRS}" -# ) - -# include directories for nanoCLR -target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC - "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR" - ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR - - ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} - ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} - - # directories for nanoFramework libraries - "${NF_CoreCLR_INCLUDE_DIRS}" - "${NF_Debugger_INCLUDE_DIRS}" - "${NF_Diagnostics_INCLUDE_DIRS}" - - # includes for nanoFramework APIs - "${TARGET_NANO_APIS_INCLUDES}" - - # # includes for ChibiOS FatFS - # "${CHIBIOS_FATFS_INCLUDE_DIRS}" - - # # includes for ChibiOS LwIP - # "${CHIBIOS_LWIP_INCLUDE_DIRS}" - - # # incudes for Networking and TLS - # "${NF_Networking_INCLUDE_DIRS}" - # "${mbedTLS_INCLUDE_DIRS}" -) - -# set compiler options -# nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) -nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) - -# # mbed TLS requires a config file -# if(NF_SECURITY_MBEDTLS) -# # this seems to be only option to properly set a compiler define through the command line that needs to be a string literal -# SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${CMAKE_CURRENT_SOURCE_DIR}/mbedtls_config.h>\"") -# endif() - -# set compiler definitions -# nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) -nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) - -# set linker files -if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) - # nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F76xx_booter-DEBUG.ld) - nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/CC3220SF_CLR-DEBUG.ld) -else() - # nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F76xx_booter.ld) - nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/CC3220SF_CLR.ld) -endif() - -# set linker options -# nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) -nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) - -# add other linker flags -########################################################### -# the sizes of CRT heap and ChibiOS stacks are defined here -# set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2000") -set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x1800") - -# generate output files -# nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) -nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld deleted file mode 100644 index 4e27091060..0000000000 --- a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld +++ /dev/null @@ -1,129 +0,0 @@ -/***************************************************************************** -* blinky.ld -* -* GCC Linker script for blinky application. -* -* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -/* -// -// Copyright (c) 2019 The nanoFramework project contributors -// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. -// See LICENSE file in the project root for full license information. -// -*/ - -/* - * CC3220SF generic setup. - * - * RAM0 - Data, Heap. - * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. - * - * Notes: - * BSS is placed in DTCM RAM in order to simplify DMA buffers management. - */ -MEMORY -{ - flash : org = 0x01000800, len = 0x0FF800 /* flash size less the space reserved for application deployment*/ - flash_itcm : org = 0x00000000, len = 0 - deployment : org = 0x01000800, len = 0 /* space reserved for application deployment */ - ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ - ram0 : org = 0x20000000, len = 0x00040000 /* SRAM */ - ram1 : org = 0x00000000, len = 0 /* */ - ram2 : org = 0x00000000, len = 0 /* */ - ram3 : org = 0x00000000, len = 0 /* */ - ram4 : org = 0x00000000, len = 0 /* */ - ram5 : org = 0x00000000, len = 0 /* */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - -/* For each data/text section two region are defined, a virtual region - and a load region (_LMA suffix).*/ - -/* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash); -REGION_ALIAS("VECTORS_FLASH_LMA", flash); - -/* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash); -REGION_ALIAS("XTORS_FLASH_LMA", flash); - -/* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash); -REGION_ALIAS("TEXT_FLASH_LMA", flash); - -/* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash); -REGION_ALIAS("RODATA_FLASH_LMA", flash); - -/* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash); - -/* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts.*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -/* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); - -/* rules inclusion.*/ -INCLUDE rules_stacks.ld - -/* Code rules inclusion.*/ -INCLUDE rules_code.ld - -/* Data rules inclusion.*/ -INCLUDE rules_data.ld - -/* nanoCLR rules inclusion.*/ -INCLUDE rules_clr.ld diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c b/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c deleted file mode 100644 index 8961dc1f25..0000000000 --- a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c +++ /dev/null @@ -1,107 +0,0 @@ - -// // Simplelink includes -// #include "simplelink.h" - -// // Driverlib includes -// #include "hw_types.h" -// #include "hw_ints.h" -// #include "hw_memmap.h" -// #include "hw_common_reg.h" -// #include "interrupt.h" -// #include "hw_apps_rcm.h" -// #include "prcm.h" -// #include "rom.h" -// #include "rom_map.h" -// #include "prcm.h" -// #include "gpio.h" -// #include "utils.h" - -// //Free_rtos/ti-rtos includes -// #include "osi.h" - -// // Common interface includes -// #include "gpio_if.h" -// #include "common.h" -// #include "pinmux.h" - - -void BlinkerThread(void const * argument) -{ - (void)argument; - - // palSetLineMode(1, PAL_MODE_OUTPUT_PUSHPULL); - - - // loop until thread receives a request to terminate - while (!chThdShouldTerminateX()) { - - // palSetPad(GPIOD, GPIOD_LED3); - // osDelay(500); - // palClearPad(GPIOD, GPIOD_LED3); - // osDelay(500); - - } - // nothing to deinitialize or cleanup, so it's safe to return -} -osThreadDef(BlinkerThread, osPriorityNormal, 128, "BlinkerThread"); - -// Application entry point. -int main(void) { - - osThreadId blinkerThreadId; - - // HAL initialization, this also initializes the configured device drivers - // and performs the board-specific initializations. - halInit(); - -// // init SWO as soon as possible to make it available to output ASAP -// #if (SWO_OUTPUT == TRUE) -// SwoInit(); -// #endif - - // The kernel is initialized but not started yet, this means that - // main() is executing with absolute priority but interrupts are already enabled. - osKernelInitialize(); - osDelay(20); // Let init stabilize - -// // the following IF is not mandatory, it's just providing a way for a user to 'force' -// // the board to remain in nanoBooter and not launching nanoCLR - -// // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter -// // the user button in this board has a pull-up resistor so the check has to be inverted -// if (palReadPad(GPIOA, GPIOA_BUTTON)) -// { -// // check for valid CLR image -// if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) -// { -// // there seems to be a valid CLR image -// // launch nanoCLR -// LaunchCLR((uint32_t)&__nanoImage_end__); -// } -// } - -// // Initializes a serial-over-USB CDC driver. -// sduObjectInit(&SDU1); -// sduStart(&SDU1, &serusbcfg); - -// // Activates the USB driver and then the USB bus pull-up on D+. -// // Note, a delay is inserted in order to not have to disconnect the cable after a reset. -// usbDisconnectBus(serusbcfg.usbp); -// chThdSleepMilliseconds(1500); -// usbStart(serusbcfg.usbp, &usbcfg); -// usbConnectBus(serusbcfg.usbp); - - // Creates the blinker thread, it does not start immediately. - blinkerThreadId = osThreadCreate(osThread(BlinkerThread), NULL); - -// // create the receiver thread -// receiverThreadId = osThreadCreate(osThread(ReceiverThread), NULL); - - // start kernel, after this main() will behave like a thread with priority osPriorityNormal - osKernelStart(); - - // Normal main() thread - while (true) { - osDelay(500); - } -} diff --git a/targets/TI-RTOS/common/include/target_types.h b/targets/TI-RTOS/common/include/target_types.h deleted file mode 100644 index 1a305a1cc4..0000000000 --- a/targets/TI-RTOS/common/include/target_types.h +++ /dev/null @@ -1,101 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// Portions Copyright (c) Microsoft Corporation. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef _TIRTOS_TYPES_H_ -#define _TIRTOS_TYPES_H_ - -#include - -/* - * ======== [U]Int ======== - */ -typedef int_least8_t xdc_Int8; -typedef uint_least8_t xdc_UInt8; -typedef int_least16_t xdc_Int16; -typedef uint_least16_t xdc_UInt16; -typedef int_least32_t xdc_Int32; -typedef uint_least32_t xdc_UInt32; - -#ifdef xdc__INT64__ - typedef int_least64_t xdc_Int64; - typedef uint_least64_t xdc_UInt64; -#endif - -#ifdef xdc__INT40__ - typedef int_least40_t xdc_Int40; - typedef uint_least40_t xdc_UInt40; - - /* the following unqualified names are here because 40-bit types are not - * supported by xdc/std.h - */ - #ifndef xdc__nolocalnames - typedef xdc_Int40 Int40; - typedef xdc_UInt40 UInt40; - #endif -#endif - -/* - * ======== Bits ======== - */ -#ifdef xdc__BITS8__ - typedef uint8_t xdc_Bits8; -#endif -#ifdef xdc__BITS16__ - typedef uint16_t xdc_Bits16; -#endif -#ifdef xdc__BITS32__ - typedef uint32_t xdc_Bits32; -#endif -#ifdef xdc__BITS64__ - typedef uint64_t xdc_Bits64; -#endif - -/* - * ======== [UI]Arg ======== - */ -typedef intptr_t xdc_IArg; -typedef uintptr_t xdc_UArg; - -/* - * ======== restrict ======== - */ -#define xdc__RESTRICT__ - - -/* - * ======== ti_targets_mkPragma ======== - */ -#define ti_targets_mkPragma(x) _Pragma(#x) - -/* - * ======== xdc__META ======== - */ -#define xdc__META(n,s) \ - ti_targets_mkPragma(DATA_SECTION(n, "xdc.meta")) \ - const char (n)[] = {s} - -/* - * ======== __ti__ ======== - * These symbols are used by RTSC tools to indicate presence/absence of - * assorted #pragma options in TI compiler. - */ -#define __ti__ -#define __ti__align -#define __ti__sect - -#if (xdc_target__sizeof_IArg > xdc_target__sizeof_Ptr) \ - || (xdc_target__sizeof_IArg > xdc_target__sizeof_Fxn) - -#define xdc__ARGTOPTR -#define xdc__ARGTOFXN -static inline xdc_Ptr xdc_iargToPtr(xdc_IArg a) { return ((xdc_Ptr)(int)a); } -static inline xdc_Ptr xdc_uargToPtr(xdc_UArg a) { return ((xdc_Ptr)(int)a); } -static inline xdc_Fxn xdc_iargToFxn(xdc_IArg a) { return ((xdc_Fxn)(int)a); } -static inline xdc_Fxn xdc_uargToFxn(xdc_UArg a) { return ((xdc_Fxn)(int)a); } - -#endif - -#endif // _TIRTOS_TYPES_H_ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt new file mode 100644 index 0000000000..af8e98d9da --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt @@ -0,0 +1,129 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) +# set(CMAKE_ASM_SOURCE_FILE_EXTENSIONS sm4g) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +configure_file("${CMAKE_SOURCE_DIR}/CMake/TI_SimpleLink_target_os.h.in" + "${CMAKE_BINARY_DIR}/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_os.h" @ONLY) + +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(TI_SimpleLink REQUIRED) +# find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +# find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +####################################### + +# add_subdirectory("common") +add_subdirectory("nanoCLR") + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + # "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + # ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_TI_SimpleLink_NANOCLR_SOURCES} + + ${TI_SimpleLink_SOURCES} + + # ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + # "${NF_CoreCLR_SOURCES}" + # "${NF_Debugger_SOURCES}" + # "${NF_Diagnostics_SOURCES}" + + # sources for nanoFramework APIs + # "${TARGET_NANO_APIS_SOURCES}" +) + +# add dependency from TI SimpleLink CC32xx SDK and FreeRTOS (this is required to make sure that those repos are downloaded before the build starts) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf SimpleLinkCC32xxSDK) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf FreeRTOS) + +# include common directories +include_directories( + "${CMAKE_CURRENT_BINARY_DIR}" + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${TI_SimpleLink_INCLUDE_DIRS} + + ${TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + "${NF_CoreCLR_INCLUDE_DIRS}" + "${NF_Debugger_INCLUDE_DIRS}" + "${NF_Diagnostics_INCLUDE_DIRS}" + + # includes for nanoFramework APIs + "${TARGET_NANO_APIS_INCLUDES}" +) + +# set compiler options +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/CC3220SF_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/CC3220SF_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the size of CRT heap stacks is defined here +# set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x1800") + +# generate output files +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/FreeRTOSConfig.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/FreeRTOSConfig.h new file mode 100644 index 0000000000..6e7fc37917 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/FreeRTOSConfig.h @@ -0,0 +1,207 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/****************************************************************************** + See http://www.freertos.org/a00110.html for an explanation of the + definitions contained in this file. +******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* Constants related to the behaviour or the scheduler. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 0 +#define configMAX_PRIORITIES ( 10UL ) +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ + +/* Constants used to specify if only static allocation is to be supported (in +which case a heap_n.c file is not required), only dynamic allocation is to be +supported, or if both static and dynamic allocation are supported. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ ( ( unsigned long ) 80000000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 ) +#define configMAX_TASK_NAME_LEN ( 12 ) + +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 0x8000 ) ) + +/* Default stack size for TI-POSIX threads (in words) */ +#define configPOSIX_STACK_SIZE ( ( unsigned short ) 512 ) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_TICKLESS_IDLE 1 +#define configUSE_APPLICATION_TASK_TAG 1 /* Need by POSIX/pthread */ +#define configUSE_CO_ROUTINES 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TASK_NOTIFICATIONS 1 + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 1 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } +#define configQUEUE_REGISTRY_SIZE 0 + +/* + * Minimum number of full tick periods of idle time required to run Power + * sleep policy function. + */ +#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 5 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (5) +#define configTIMER_QUEUE_LENGTH (20) +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +#define configENABLE_BACKWARD_COMPATIBILITY 0 + +#if defined(__TI_COMPILER_VERSION__) +#include +#define traceTASK_DELETE( pxTCB ) PTLS_taskDeleteHook( pxTCB ) +#elif defined(__IAR_SYSTEMS_ICC__) +#ifndef __IAR_SYSTEMS_ASM__ +#include +#define traceTASK_DELETE( pxTCB ) Mtx_taskDeleteHook( pxTCB ) +#endif +#endif + +/* + * Enable thread local storage + * + * Assign TLS array index ownership here to avoid collisions. + * TLS storage is needed to implement thread-safe errno with + * TI and IAR compilers. With GNU compiler, we enable newlib. + */ +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) + +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 1 + +#if defined(__TI_COMPILER_VERSION__) +#define PTLS_TLS_INDEX 0 /* ti.posix.freertos.PTLS */ +#elif defined(__IAR_SYSTEMS_ICC__) +#define MTX_TLS_INDEX 0 /* ti.posix.freertos.Mtx */ +#endif + +#elif defined(__GNUC__) +/* note: system locks required by newlib are not implemented */ +#define configUSE_NEWLIB_REENTRANT 1 +#endif + +/* + * Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is only + * necessary if the linker does not automatically remove functions that are not + * referenced anyway. + */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Cortex-M3/4 interrupt priority configuration follows...................... */ + +/* Use the system definition, if there is one. */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 8 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* + * The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL + * INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER + * PRIORITY THAN THIS! (higher priorities are lower numeric values. + */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1 + +/* + * Priority 7 (shifted 5 since only the top 3 bits are implemented). + * Priority 7 is the lowest priority. + */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* + * Priority 1 (shifted 5 since only the top 3 bits are implemented). + * Priority 1 is the second highest priority. + * Priority 0 is the highest priority. + * !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. + */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* The trace facility is turned on to make some functions available for use in +CLI commands. */ +#define configUSE_TRACE_FACILITY 1 + +/* Constants related to the generation of run time stats. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#define portGET_RUN_TIME_COUNTER_VALUE() 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt similarity index 100% rename from targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c similarity index 100% rename from targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c similarity index 100% rename from targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld new file mode 100644 index 0000000000..f2454ba5a9 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +STACKSIZE = 0x800; + +MEMORY +{ + FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x0FF800 + SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +REGION_ALIAS("REGION_HDR", FLASH_HDR); +REGION_ALIAS("REGION_TEXT", FLASH); +REGION_ALIAS("REGION_BSS", SRAM); +REGION_ALIAS("REGION_DATA", SRAM); +REGION_ALIAS("REGION_STACK", SRAM); +REGION_ALIAS("REGION_HEAP", SRAM); +REGION_ALIAS("REGION_ARM_EXIDX", FLASH); +REGION_ALIAS("REGION_ARM_EXTAB", FLASH); + +SECTIONS { + + .dbghdr : ALIGN (2048) { + KEEP (*(.dbghdr)) + } > REGION_HDR + + PROVIDE (_resetVecs_base_address = + DEFINED(_resetVecs_base_address) ? _resetVecs_base_address : 0x01000800); + + .resetVecs (_resetVecs_base_address) : AT (_resetVecs_base_address) { + KEEP (*(.resetVecs)) + } > REGION_TEXT + + .ramVecs (NOLOAD) : ALIGN(1024) { + KEEP (*(.ramVecs)) + } > REGION_DATA + + .text : { + CREATE_OBJECT_SYMBOLS + *(.text) + *(.text.*) + . = ALIGN(0x4); + KEEP (*(.ctors)) + . = ALIGN(0x4); + KEEP (*(.dtors)) + . = ALIGN(0x4); + __init_array_start = .; + KEEP (*(.init_array*)) + __init_array_end = .; + *(.init) + *(.fini*) + } > REGION_TEXT AT> REGION_TEXT + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : { + *(.rodata) + *(.rodata*) + } > REGION_TEXT AT> REGION_TEXT + + .data : ALIGN (4) { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + *(.data) + *(.data*) + . = ALIGN (4); + __data_end__ = .; + } > REGION_DATA AT> REGION_TEXT + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX + + .ARM.extab : { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB + + .bss : { + __bss_start__ = .; + *(.shbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN (4); + __bss_end__ = .; + } > REGION_BSS AT> REGION_BSS + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + KEEP(*(.heap)) + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > REGION_HEAP AT> REGION_HEAP + + .stack (NOLOAD) : ALIGN(0x8) { + _stack = .; + __stack = .; + KEEP(*(.stack)) + . += STACKSIZE; + _stack_end = .; + __stack_end = .; + } > REGION_STACK AT> REGION_STACK +} + +ENTRY(resetISR) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld new file mode 100644 index 0000000000..f2454ba5a9 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +STACKSIZE = 0x800; + +MEMORY +{ + FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x0FF800 + SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +REGION_ALIAS("REGION_HDR", FLASH_HDR); +REGION_ALIAS("REGION_TEXT", FLASH); +REGION_ALIAS("REGION_BSS", SRAM); +REGION_ALIAS("REGION_DATA", SRAM); +REGION_ALIAS("REGION_STACK", SRAM); +REGION_ALIAS("REGION_HEAP", SRAM); +REGION_ALIAS("REGION_ARM_EXIDX", FLASH); +REGION_ALIAS("REGION_ARM_EXTAB", FLASH); + +SECTIONS { + + .dbghdr : ALIGN (2048) { + KEEP (*(.dbghdr)) + } > REGION_HDR + + PROVIDE (_resetVecs_base_address = + DEFINED(_resetVecs_base_address) ? _resetVecs_base_address : 0x01000800); + + .resetVecs (_resetVecs_base_address) : AT (_resetVecs_base_address) { + KEEP (*(.resetVecs)) + } > REGION_TEXT + + .ramVecs (NOLOAD) : ALIGN(1024) { + KEEP (*(.ramVecs)) + } > REGION_DATA + + .text : { + CREATE_OBJECT_SYMBOLS + *(.text) + *(.text.*) + . = ALIGN(0x4); + KEEP (*(.ctors)) + . = ALIGN(0x4); + KEEP (*(.dtors)) + . = ALIGN(0x4); + __init_array_start = .; + KEEP (*(.init_array*)) + __init_array_end = .; + *(.init) + *(.fini*) + } > REGION_TEXT AT> REGION_TEXT + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : { + *(.rodata) + *(.rodata*) + } > REGION_TEXT AT> REGION_TEXT + + .data : ALIGN (4) { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + *(.data) + *(.data*) + . = ALIGN (4); + __data_end__ = .; + } > REGION_DATA AT> REGION_TEXT + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX + + .ARM.extab : { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB + + .bss : { + __bss_start__ = .; + *(.shbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN (4); + __bss_end__ = .; + } > REGION_BSS AT> REGION_BSS + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + KEEP(*(.heap)) + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > REGION_HEAP AT> REGION_HEAP + + .stack (NOLOAD) : ALIGN(0x8) { + _stack = .; + __stack = .; + KEEP(*(.stack)) + . += STACKSIZE; + _stack_end = .; + __stack_end = .; + } > REGION_STACK AT> REGION_STACK +} + +ENTRY(resetISR) diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt similarity index 80% rename from targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt index c61dda6ef2..91132fa734 100644 --- a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt @@ -5,7 +5,7 @@ # append nanoCLR source files list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") -list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") +# list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") # make var global set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c new file mode 100644 index 0000000000..010aafe07b --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c @@ -0,0 +1,373 @@ +#include + +/* POSIX Header files */ +#include + +/* RTOS header files */ +#include "FreeRTOS.h" +#include "task.h" + +/* TI-RTOS Header files */ +#include + +/* Example/Board Header files */ +#include "Board.h" + +extern void * mainThread(void *arg0); + + +////////////////////////////// +#define SL_STOP_TIMEOUT (200) +#define APPLICATION_NAME "out of box" +#define APPLICATION_VERSION "1.00.00.09" + +////////////////////////////// + +/* Stack size in bytes */ +#define THREADSTACKSIZE 4096 + +/* + * ======== main ======== + */ +int main(void) +{ + pthread_t thread; + pthread_attr_t pAttrs; + struct sched_param priParam; + int retc; + int detachState; + + /* Call board init functions */ + Board_initGeneral(); + + /* Set priority and stack size attributes */ + pthread_attr_init(&pAttrs); + priParam.sched_priority = 1; + + detachState = PTHREAD_CREATE_DETACHED; + retc = pthread_attr_setdetachstate(&pAttrs, detachState); + if(retc != 0) + { + /* pthread_attr_setdetachstate() failed */ + while(1) + { + ; + } + } + + pthread_attr_setschedparam(&pAttrs, &priParam); + + retc |= pthread_attr_setstacksize(&pAttrs, THREADSTACKSIZE); + if(retc != 0) + { + /* pthread_attr_setstacksize() failed */ + while(1) + { + ; + } + } + + retc = pthread_create(&thread, &pAttrs, mainThread, NULL); + if(retc != 0) + { + /* pthread_create() failed */ + while(1) + { + ; + } + } + + /* Start the FreeRTOS scheduler */ + vTaskStartScheduler(); + + return (0); +} + +//***************************************************************************** +// +//! \brief Application defined malloc failed hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void vApplicationMallocFailedHook() +{ + /* Handle Memory Allocation Errors */ + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Application defined stack overflow hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void vApplicationStackOverflowHook(TaskHandle_t pxTask, + char *pcTaskName) +{ + //Handle FreeRTOS Stack Overflow + while(1) + { + } +} + +void vApplicationTickHook(void) +{ + /* + * This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). + */ +} + +void vPreSleepProcessing(uint32_t ulExpectedIdleTime) +{ +} + +//***************************************************************************** +// +//! \brief Application defined idle task hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void +vApplicationIdleHook(void) +{ + /* Handle Idle Hook for Profiling, Power Management etc */ +} + +//***************************************************************************** +// +//! \brief Overwrite the GCC _sbrk function which check the heap limit related +//! to the stack pointer. +//! In case of freertos this checking will fail. +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void * _sbrk(uint32_t delta) +{ + extern char _end; /* Defined by the linker */ + extern char __HeapLimit; + static char *heap_end; + static char *heap_limit; + char *prev_heap_end; + + if(heap_end == 0) + { + heap_end = &_end; + heap_limit = &__HeapLimit; + } + + prev_heap_end = heap_end; + if(prev_heap_end + delta > heap_limit) + { + return((void *) -1L); + } + heap_end += delta; + return((void *) prev_heap_end); +} + + +// /***************************************************************************** +// Local Functions +// *****************************************************************************/ +// //***************************************************************************** +// // +// //! Application Boarders display on UART +// //! +// //! \param ch - Character to be displayed , n - number of time to display +// //! +// //! \return none +// //! +// //***************************************************************************** +// void printBorder(char ch, +// int n) +// { +// int i = 0; + +// for(i = 0; i < n; i++) +// { +// putch(ch); +// } +// } + +// //***************************************************************************** +// // +// //! Application startup display on UART +// //! +// //! \param none +// //! +// //! \return none +// //! +// //***************************************************************************** +// int32_t DisplayBanner(char * AppName, +// char * AppVer) +// { +// int32_t ret = 0; +// uint8_t macAddress[SL_MAC_ADDR_LEN]; +// uint16_t macAddressLen = SL_MAC_ADDR_LEN; +// uint16_t ConfigSize = 0; +// uint8_t ConfigOpt = SL_DEVICE_GENERAL_VERSION; +// SlDeviceVersion_t ver = {0}; +// char lineBreak[] = "\n\r"; +// ConfigSize = sizeof(SlDeviceVersion_t); + +// /* Print device version info. */ +// ret = +// sl_DeviceGet(SL_DEVICE_GENERAL, &ConfigOpt, &ConfigSize, +// (uint8_t*)(&ver)); +// ASSERT_ON_ERROR(ret); + +// /* Print device Mac address */ +// ret = sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, +// &macAddress[0]); +// ASSERT_ON_ERROR(ret); + +// UART_PRINT(lineBreak); +// UART_PRINT("\t"); +// printBorder('=', 44); +// UART_PRINT(lineBreak); +// UART_PRINT("\t %s Example Ver: %s",AppName, AppVer); +// UART_PRINT(lineBreak); +// UART_PRINT("\t"); +// printBorder('=', 44); +// UART_PRINT(lineBreak); +// UART_PRINT(lineBreak); +// UART_PRINT("\t CHIP: 0x%x",ver.ChipId); +// UART_PRINT(lineBreak); +// UART_PRINT("\t MAC: %d.%d.%d.%d",ver.FwVersion[0],ver.FwVersion[1], +// ver.FwVersion[2], +// ver.FwVersion[3]); +// UART_PRINT(lineBreak); +// UART_PRINT("\t PHY: %d.%d.%d.%d",ver.PhyVersion[0],ver.PhyVersion[1], +// ver.PhyVersion[2], +// ver.PhyVersion[3]); +// UART_PRINT(lineBreak); +// UART_PRINT("\t NWP: %d.%d.%d.%d",ver.NwpVersion[0],ver.NwpVersion[1], +// ver.NwpVersion[2], +// ver.NwpVersion[3]); +// UART_PRINT(lineBreak); +// UART_PRINT("\t ROM: %d",ver.RomVersion); +// UART_PRINT(lineBreak); +// UART_PRINT("\t HOST: %s", SL_DRIVER_VERSION); +// UART_PRINT(lineBreak); +// UART_PRINT("\t MAC address: %02x:%02x:%02x:%02x:%02x:%02x", macAddress[0], +// macAddress[1], macAddress[2], macAddress[3], macAddress[4], +// macAddress[5]); +// UART_PRINT(lineBreak); +// UART_PRINT(lineBreak); +// UART_PRINT("\t"); +// printBorder('=', 44); +// UART_PRINT(lineBreak); +// UART_PRINT(lineBreak); + +// return(ret); +// } + +//***************************************************************************** +// +//! This function clears and enables a GPIO pin interrupt flag +//! +//! \param index - GPIO index +//! +//! \return None +//! +//***************************************************************************** +static void GPIO_clearAndEnable(uint8_t index) +{ + GPIO_clearInt(index); + GPIO_enableInt(index); +} + + +void * mainThread(void *arg) +{ + int32_t RetVal; + pthread_attr_t pAttrs; + pthread_attr_t pAttrs_spawn; + struct sched_param priParam; + struct timespec ts = {0}; + + GPIO_init(); + SPI_init(); + I2C_init(); + + /* init Terminal, and print App name */ + //InitTerm(); + + /* initialize the realtime clock */ + clock_settime(CLOCK_REALTIME, &ts); + + /* Switch off all LEDs on boards */ + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + + // /* create the sl_Task */ + // pthread_attr_init(&pAttrs_spawn); + // priParam.sched_priority = SPAWN_TASK_PRIORITY; + // RetVal = pthread_attr_setschedparam(&pAttrs_spawn, &priParam); + // RetVal |= pthread_attr_setstacksize(&pAttrs_spawn, TASK_STACK_SIZE); + + // RetVal = pthread_create(&gSpawnThread, &pAttrs_spawn, sl_Task, NULL); + + // if(RetVal) + // { + // /* Handle Error */ + // UART_PRINT("Unable to create sl_Task thread \n"); + // while(1) + // { + // ; + // } + // } + // RetVal = sl_Start(0, 0, 0); + // if(RetVal >= 0) + // { + // DisplayBanner(APPLICATION_NAME, APPLICATION_VERSION); + // RetVal = sl_Stop(SL_STOP_TIMEOUT); + // if(RetVal < 0) + // { + // /* Handle Error */ + // UART_PRINT("\n sl_Stop failed\n"); + // while(1) + // { + // ; + // } + // } + // } + // else if((RetVal < 0) && (RetVal != SL_ERROR_RESTORE_IMAGE_COMPLETE)) + // { + // /* Handle Error */ + // UART_PRINT("\n sl_Start failed\n"); + // UART_PRINT("\n %s Example Ver. %s\n",APPLICATION_NAME, + // APPLICATION_VERSION); + // while(1) + // { + // ; + // } + // } + + while(1) + { + /* Turn on user LED */ + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + usleep(50000); + /* Turn off user LED */ + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + usleep(50000); + } + + return(0); +} \ No newline at end of file diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp similarity index 100% rename from targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in similarity index 100% rename from targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c similarity index 100% rename from targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.c rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c diff --git a/targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.h.in b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in similarity index 100% rename from targets/FreeRTOS/TI_CC3220SF_LAUNCHXL/target_common.h.in rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in From 1d146fc6d5337d67acc2e6291183afcfa3ddc276 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Feb 2019 00:52:39 +0000 Subject: [PATCH 07/90] Work on TI_CC3220SF_LAUNCHXL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Add target common files, CLR and includes. - Further work on CMakes. Signed-off-by: José Simões --- CMake/Modules/FindNF_CoreCLR.cmake | 1 + .../TI_SimpleLink_CC32xx_GCC_options.cmake | 2 +- CMake/toolchain.TI_SimpleLink.GCC.cmake | 2 +- CMakeLists.txt | 8 +- .../Include/CLR_Startup_Thread.h | 12 + targets/TI-SimpleLink/Include/CMakeLists.txt | 14 + .../Include/TargetPAL_BlockStorage.h | 11 + .../Include/WireProtocol_ReceiverThread.h | 12 + targets/TI-SimpleLink/Include/targetHAL.h | 76 ++++ .../TI-SimpleLink/Include/targetHAL_Time.h | 14 + .../TI-SimpleLink/Include/targetPAL_Time.h | 9 + .../TI_CC3220SF_LAUNCHXL/CMakeLists.txt | 52 ++- .../common/CMakeLists.txt | 1 - .../common/Device_BlockStorage-DEBUG.c | 45 +-- .../nanoCLR/CC3220SF_CLR-DEBUG.ld | 6 + .../nanoCLR/CC3220SF_CLR.ld | 3 + .../nanoCLR/CMakeLists.txt | 2 +- .../TI_CC3220SF_LAUNCHXL/nanoCLR/main.c | 11 +- .../nanoCLR/target_board.h.in | 3 - .../TI_CC3220SF_LAUNCHXL/target_common.c | 4 + .../TI_CC3220SF_LAUNCHXL/target_common.h.in | 2 + targets/TI-SimpleLink/common/CMakeLists.txt | 21 ++ .../TI-SimpleLink/common/FreeRTOS-openocd.c | 20 + targets/TI-SimpleLink/common/GenericPort.cpp | 29 ++ .../common/Target_BlockStorage.c | 120 ++++++ .../common/WireProtocol_HAL_Interface.c | 141 +++++++ .../common/WireProtocol_ReceiverThread.c | 31 ++ targets/TI-SimpleLink/common/platform_heap.c | 18 + targets/TI-SimpleLink/common/rules_clr.ld | 15 + targets/TI-SimpleLink/common/syscalls.c | 45 +++ targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp | 354 ++++++++++++++++++ .../CLR_RT_InteropAssembliesTable.cpp.in | 23 ++ .../nanoCLR/CLR_Startup_Thread.c | 19 + targets/TI-SimpleLink/nanoCLR/CMakeLists.txt | 86 +++++ targets/TI-SimpleLink/nanoCLR/Memory.cpp | 30 ++ targets/TI-SimpleLink/nanoCLR/nanoCRT.cpp | 205 ++++++++++ targets/TI-SimpleLink/nanoCLR/targetHAL.cpp | 147 ++++++++ .../TI-SimpleLink/nanoCLR/targetHAL_Power.c | 29 ++ .../TI-SimpleLink/nanoCLR/targetHAL_Time.cpp | 133 +++++++ targets/TI-SimpleLink/nanoCLR/targetPAL.c | 8 + .../nanoCLR/targetPAL_Events.cpp | 179 +++++++++ .../TI-SimpleLink/nanoCLR/targetPAL_Time.cpp | 67 ++++ .../nanoCLR/target_platform.h.in | 18 + 43 files changed, 1949 insertions(+), 79 deletions(-) create mode 100644 targets/TI-SimpleLink/Include/CLR_Startup_Thread.h create mode 100644 targets/TI-SimpleLink/Include/CMakeLists.txt create mode 100644 targets/TI-SimpleLink/Include/TargetPAL_BlockStorage.h create mode 100644 targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h create mode 100644 targets/TI-SimpleLink/Include/targetHAL.h create mode 100644 targets/TI-SimpleLink/Include/targetHAL_Time.h create mode 100644 targets/TI-SimpleLink/Include/targetPAL_Time.h create mode 100644 targets/TI-SimpleLink/common/CMakeLists.txt create mode 100644 targets/TI-SimpleLink/common/FreeRTOS-openocd.c create mode 100644 targets/TI-SimpleLink/common/GenericPort.cpp create mode 100644 targets/TI-SimpleLink/common/Target_BlockStorage.c create mode 100644 targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c create mode 100644 targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c create mode 100644 targets/TI-SimpleLink/common/platform_heap.c create mode 100644 targets/TI-SimpleLink/common/rules_clr.ld create mode 100644 targets/TI-SimpleLink/common/syscalls.c create mode 100644 targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/CLR_RT_InteropAssembliesTable.cpp.in create mode 100644 targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c create mode 100644 targets/TI-SimpleLink/nanoCLR/CMakeLists.txt create mode 100644 targets/TI-SimpleLink/nanoCLR/Memory.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/nanoCRT.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/targetHAL.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c create mode 100644 targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/targetPAL.c create mode 100644 targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/targetPAL_Time.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/target_platform.h.in diff --git a/CMake/Modules/FindNF_CoreCLR.cmake b/CMake/Modules/FindNF_CoreCLR.cmake index 9d37719588..68d9febaa4 100644 --- a/CMake/Modules/FindNF_CoreCLR.cmake +++ b/CMake/Modules/FindNF_CoreCLR.cmake @@ -71,6 +71,7 @@ set(NF_CoreCLR_SRCS TypeSystem.cpp nanoSupport_CRC32.c nanoHAL_SystemInformation.cpp + # Various.cpp # CoreLib corlib_native_System_AppDomain.cpp diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake index df67197cf2..85e7a795b2 100644 --- a/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake +++ b/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake @@ -12,7 +12,7 @@ set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTER # need to specify linker flags here # -mfpu=fpv5-sp-d16 -set(CMAKE_EXE_LINKER_FLAGS " -Wl,--print-memory-usage -mcpu=cortex-m4 -march=armv7e-m -mthumb -nostartfiles -std=c99 -mfloat-abi=soft -ffunction-sections -fdata-sections -g -gstrict-dwarf -Wall " CACHE INTERNAL "executable linker flags") +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mcpu=cortex-m4 -march=armv7e-m -mthumb -nostartfiles -std=c99 -mfloat-abi=soft -ffunction-sections -fdata-sections -g -gstrict-dwarf -Wall " CACHE INTERNAL "executable linker flags") function(NF_SET_COMPILER_OPTIONS TARGET) diff --git a/CMake/toolchain.TI_SimpleLink.GCC.cmake b/CMake/toolchain.TI_SimpleLink.GCC.cmake index 4f3d8284a0..d31f2c0d1d 100644 --- a/CMake/toolchain.TI_SimpleLink.GCC.cmake +++ b/CMake/toolchain.TI_SimpleLink.GCC.cmake @@ -113,7 +113,7 @@ function(NF_SET_LINK_MAP TARGET) string(SUBSTRING ${TARGET} 0 ${TARGET_EXTENSION_DOT_INDEX} TARGET_SHORT) # add linker flags to generate map file - set_property(TARGET ${TARGET_SHORT}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=${PROJECT_SOURCE_DIR}/build/${TARGET_SHORT}.map") + set_property(TARGET ${TARGET_SHORT}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=${PROJECT_SOURCE_DIR}/build/${TARGET_SHORT}.map,--library-path=${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/common") endfunction() diff --git a/CMakeLists.txt b/CMakeLists.txt index 67f3b29019..4bd4ca7522 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1130,7 +1130,13 @@ elseif(RTOS_TI_SIMPLELINK_CHECK) # can't continue message(FATAL_ERROR "\n\nSorry but support for ${TI_BOARD} target is not available...\n\nYou can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") endif() - + + # add target TI SimpliLink dirs + add_subdirectory(targets/TI-SimpleLink/common) + add_subdirectory(targets/TI-SimpleLink/Include) + add_subdirectory(targets/TI-SimpleLink/nanoCLR) + + if("${TARGET_SERIES}" STREQUAL "CC32xx") # CC32xx series is using TI SimpleLink CC32xx SDK and FreeRTOS diff --git a/targets/TI-SimpleLink/Include/CLR_Startup_Thread.h b/targets/TI-SimpleLink/Include/CLR_Startup_Thread.h new file mode 100644 index 0000000000..3c394ef4be --- /dev/null +++ b/targets/TI-SimpleLink/Include/CLR_Startup_Thread.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _CLRSTARTUPTHREAD_ +#define _CLRSTARTUPTHREAD_ + +// declaration of RTOS thread +void CLRStartupThread(void const * argument); + +#endif //_CLRSTARTUPTHREAD_ diff --git a/targets/TI-SimpleLink/Include/CMakeLists.txt b/targets/TI-SimpleLink/Include/CMakeLists.txt new file mode 100644 index 0000000000..38729eda6c --- /dev/null +++ b/targets/TI-SimpleLink/Include/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append include directory for target TI SimpleLink +list(APPEND TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS "${CMAKE_CURRENT_SOURCE_DIR}") + +# make var global +set(TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS ${TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS} CACHE INTERNAL "make global") + +# add header with target platform definitions +configure_file("${CMAKE_SOURCE_DIR}/CMake/TI_SimpleLink_target_os.h.in" + "${CMAKE_BINARY_DIR}/targets/TI-SimpleLink/${TI_BOARD}/target_os.h" @ONLY) diff --git a/targets/TI-SimpleLink/Include/TargetPAL_BlockStorage.h b/targets/TI-SimpleLink/Include/TargetPAL_BlockStorage.h new file mode 100644 index 0000000000..1828f7503b --- /dev/null +++ b/targets/TI-SimpleLink/Include/TargetPAL_BlockStorage.h @@ -0,0 +1,11 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_BLOCKSTORAGE_H_ +#define _TARGET_PAL_BLOCKSTORAGE_H_ 1 + +#include + +#endif // _TARGET_PAL_BLOCKSTORAGE_H_ diff --git a/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h b/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h new file mode 100644 index 0000000000..5bae805e8c --- /dev/null +++ b/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_RECEIVERTHREAD_H_ +#define _WIREPROTOCOL_RECEIVERTHREAD_H_ + +// declaration of RTOS thread +void ReceiverThread(void const * argument); + +#endif //_WIREPROTOCOL_RECEIVERTHREAD_H_ diff --git a/targets/TI-SimpleLink/Include/targetHAL.h b/targets/TI-SimpleLink/Include/targetHAL.h new file mode 100644 index 0000000000..880267d9ee --- /dev/null +++ b/targets/TI-SimpleLink/Include/targetHAL.h @@ -0,0 +1,76 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_H_ +#define _TARGET_HAL_H_ + +#include +#include + +#define GLOBAL_LOCK(x) portENTER_CRITICAL(); +#define GLOBAL_UNLOCK(x) portEXIT_CRITICAL(); +#define ASSERT_IRQ_MUST_BE_OFF() // TODO need to determine if this needs implementation + +// Definitions for Sockets/Network +#define GLOBAL_LOCK_SOCKETS(x) + +#define PLATFORM_DEPENDENT__SOCKETS_MAX_COUNT 16 + +#define LPCSTR const char* + +// these macros are to be used at entry/exit of native interrupt handlers +#define NATIVE_INTERRUPT_START SystemState_SetNoLock( SYSTEM_STATE_ISR ); \ + SystemState_SetNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); +#define NATIVE_INTERRUPT_END SystemState_ClearNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); \ + SystemState_ClearNoLock( SYSTEM_STATE_ISR ); + +#define TRUE true +#define FALSE false + +#if !defined(BUILD_RTM) + +inline void HARD_Breakpoint() { }; + +#define HARD_BREAKPOINT() HARD_Breakpoint() + +// #if defined(_DEBUG) +// #define DEBUG_HARD_BREAKPOINT() HARD_Breakpoint() +// #else +// #define DEBUG_HARD_BREAKPOINT() +// #endif + +// #else + +// #define HARD_BREAKPOINT() +// #define DEBUG_HARD_BREAKPOINT() + +#endif // !defined(BUILD_RTM) + +inline bool Target_HasNanoBooter() { return false; }; + +#define NANOCLR_STOP() HARD_BREAKPOINT() + +inline void HAL_AssertEx() +{ + __asm__("BKPT"); + while(true) { /*nop*/ } +} + +// Provides information whether the configuration block storage requires erase command before sending the update command +// The 'weak' implementation for TI SimpleLink targets is false +// If a target implements the store differently it has to provide a 'strong' implementation of this. +__nfweak bool Target_ConfigUpdateRequiresErase() { return false; }; + +extern int HeapBegin; +extern int HeapEnd; + +extern uint32_t __nanoImage_start__; +extern uint32_t __nanoImage_end__; +extern uint32_t __nanoConfig_start__; +extern uint32_t __nanoConfig_end__; +extern uint32_t __deployment_start__; +extern uint32_t __deployment_end__; + +#endif //_TARGET_HAL_H_ diff --git a/targets/TI-SimpleLink/Include/targetHAL_Time.h b/targets/TI-SimpleLink/Include/targetHAL_Time.h new file mode 100644 index 0000000000..a456444d36 --- /dev/null +++ b/targets/TI-SimpleLink/Include/targetHAL_Time.h @@ -0,0 +1,14 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_TIME_H_ +#define _TARGET_HAL_TIME_H_ 1 + +#include +#include + +#define HAL_Time_CurrentSysTicks xTaskGetTickCount + +#endif //_TARGET_HAL_TIME_H_ diff --git a/targets/TI-SimpleLink/Include/targetPAL_Time.h b/targets/TI-SimpleLink/Include/targetPAL_Time.h new file mode 100644 index 0000000000..815979a703 --- /dev/null +++ b/targets/TI-SimpleLink/Include/targetPAL_Time.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_TIME_H_ +#define _TARGET_PAL_TIME_H_ 1 + +#endif //_TARGET_PAL_TIME_H_ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt index af8e98d9da..63723fa606 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt @@ -5,27 +5,23 @@ cmake_minimum_required(VERSION 3.0) ENABLE_LANGUAGE(ASM) -# set(CMAKE_ASM_SOURCE_FILE_EXTENSIONS sm4g) # add header files with common OS definitions and board definitions specific for each image configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) - -configure_file("${CMAKE_SOURCE_DIR}/CMake/TI_SimpleLink_target_os.h.in" - "${CMAKE_BINARY_DIR}/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_os.h" @ONLY) set(NANOCLR_PROJECT_NAME "nanoCLR") find_package(BuildUtils REQUIRED) find_package(TI_SimpleLink REQUIRED) -# find_package(WireProtocol REQUIRED) +find_package(WireProtocol REQUIRED) # packages for nanoFramework libraries ####################################### # mandatory -# find_package(NF_CoreCLR REQUIRED) +find_package(NF_CoreCLR REQUIRED) ####################################### # optional @@ -38,7 +34,7 @@ endif() ####################################### -# add_subdirectory("common") +add_subdirectory("common") add_subdirectory("nanoCLR") ####################### @@ -48,52 +44,54 @@ add_executable( # executables for project, project sources ${NANOCLR_PROJECT_NAME}.elf - # "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" - # ${COMMON_PROJECT_SOURCES} + ${COMMON_PROJECT_SOURCES} ${NANOCLR_PROJECT_SOURCES} + ${TARGET_TI_SimpleLink_COMMON_SOURCES} + ${TARGET_TI_SimpleLink_NANOCLR_SOURCES} ${TI_SimpleLink_SOURCES} - # ${WireProtocol_SOURCES} + ${WireProtocol_SOURCES} # sources for nanoFramework libraries - # "${NF_CoreCLR_SOURCES}" - # "${NF_Debugger_SOURCES}" - # "${NF_Diagnostics_SOURCES}" + "${NF_CoreCLR_SOURCES}" + "${NF_Debugger_SOURCES}" + "${NF_Diagnostics_SOURCES}" # sources for nanoFramework APIs - # "${TARGET_NANO_APIS_SOURCES}" + "${TARGET_NANO_APIS_SOURCES}" ) # add dependency from TI SimpleLink CC32xx SDK and FreeRTOS (this is required to make sure that those repos are downloaded before the build starts) -add_dependencies(${NANOCLR_PROJECT_NAME}.elf SimpleLinkCC32xxSDK) add_dependencies(${NANOCLR_PROJECT_NAME}.elf FreeRTOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf SimpleLinkCC32xxSDK) # include common directories include_directories( "${CMAKE_CURRENT_BINARY_DIR}" - ${CMAKE_CURRENT_SOURCE_DIR} - ${CMAKE_CURRENT_SOURCE_DIR}/common - ${PROJECT_SOURCE_DIR}/src/CLR/Core - ${PROJECT_SOURCE_DIR}/src/CLR/Include - ${PROJECT_SOURCE_DIR}/src/HAL/Include - ${PROJECT_SOURCE_DIR}/src/PAL/Include + "${CMAKE_CURRENT_SOURCE_DIR}" + "${CMAKE_CURRENT_SOURCE_DIR}/common" + "${PROJECT_SOURCE_DIR}/src/CLR/Core" + "${PROJECT_SOURCE_DIR}/src/CLR/Include" + "${PROJECT_SOURCE_DIR}/src/HAL/Include" + "${PROJECT_SOURCE_DIR}/src/PAL/Include" - ${WireProtocol_INCLUDE_DIRS} - ${TI_SimpleLink_INCLUDE_DIRS} + "${WireProtocol_INCLUDE_DIRS}" + "${TI_SimpleLink_INCLUDE_DIRS}" - ${TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS} + "${TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS}" ) # include directories for nanoCLR target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR" - ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + "${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR" - ${TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS} + "${TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS}" # directories for nanoFramework libraries "${NF_CoreCLR_INCLUDE_DIRS}" @@ -123,7 +121,7 @@ nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) # add other linker flags ########################################################### # the size of CRT heap stacks is defined here -# set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x1800") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__crt_heap_size__=0x0") # generate output files nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt index 8a93289ea7..42be0d5f5a 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt @@ -4,7 +4,6 @@ # # append common source files -# list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") # make var global diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index d72e90abd0..c181527942 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -1,38 +1,14 @@ // -// Copyright (c) 2018 The nanoFramework project contributors +// Copyright (c) 2019 The nanoFramework project contributors // See LICENSE file in the project root for full license information. // #include #include -// 32kB blocks const BlockRange BlockRange1[] = { - { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 08008000 configuration block - /////////////////////////////////////////////////////////////////////////////////////// - - { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08010000 nanoCLR -}; - -//128kB block -const BlockRange BlockRange2[] = -{ - { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR -}; - -// 256kB blocks -const BlockRange BlockRange3[] = -{ - { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08040000 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 6 } // 080C0000 deployment + { BlockRange_BLOCKTYPE_DEPLOYMENT , 1, 1 }, // 08008000 configuration block }; const BlockRegionInfo BlockRegions[] = @@ -44,23 +20,6 @@ const BlockRegionInfo BlockRegions[] = ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, }, - - { - 0x08020000, // start address for block region - 1, // total number of blocks in this region - 0x20000, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange2), - BlockRange2, - }, - - { - 0x08040000, // start address for block region - 7, // total number of blocks in this region - 0x40000, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange3), - BlockRange3, - }, - }; const DeviceBlockInfo Device_BlockInfo = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index f2454ba5a9..2da13f2e66 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -139,4 +139,10 @@ SECTIONS { } > REGION_STACK AT> REGION_STACK } +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", SRAM); + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld + ENTRY(resetISR) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld index f2454ba5a9..bed7cf8700 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld @@ -139,4 +139,7 @@ SECTIONS { } > REGION_STACK AT> REGION_STACK } +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld + ENTRY(resetISR) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt index 91132fa734..c61dda6ef2 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt @@ -5,7 +5,7 @@ # append nanoCLR source files list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") -# list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") # make var global set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c index 010aafe07b..a49ac9115d 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c @@ -1,5 +1,6 @@ -#include +#include +#include /* POSIX Header files */ #include @@ -13,6 +14,14 @@ /* Example/Board Header files */ #include "Board.h" +#include +#include +#include +#include + +extern void CLRStartupThread(void const * argument); + + extern void * mainThread(void *arg0); diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in index 2a7e8d2e8c..25bf6abd7a 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in @@ -12,8 +12,5 @@ #define _TARGET_BOARD_NANOCLR_H_ #include -#include - -#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) #endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c index 948e58f1fb..cc302074d9 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c @@ -22,3 +22,7 @@ HAL_SYSTEM_CONFIG HalSystemConfig = }; HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// FIXME TODO +uint32_t __nanoImage_start__ = 0; +uint32_t __nanoImage_end__ = 0; diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in index ee8cc5cf39..605485b882 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in @@ -33,4 +33,6 @@ #define PLATFORM_HAS_RNG TRUE ///////////////////////////////////// +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TI_BOARD@ built with TI SL CC32xx SDK v2.40.01.01" + #endif /* _TARGET_COMMON_H_ */ diff --git a/targets/TI-SimpleLink/common/CMakeLists.txt b/targets/TI-SimpleLink/common/CMakeLists.txt new file mode 100644 index 0000000000..08ee98f0cb --- /dev/null +++ b/targets/TI-SimpleLink/common/CMakeLists.txt @@ -0,0 +1,21 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append target TI SimpleLink common source files +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platform_heap.c") + +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_ReceiverThread.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c") + +# list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_ESP32FlashDriver.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage.c") + +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/FreeRTOS-openocd.c") + +# list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/GenericPort.cpp") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/syscalls.c") + +# make var global +set(TARGET_TI_SimpleLink_COMMON_SOURCES ${TARGET_TI_SimpleLink_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/TI-SimpleLink/common/FreeRTOS-openocd.c b/targets/TI-SimpleLink/common/FreeRTOS-openocd.c new file mode 100644 index 0000000000..81a3ab77ab --- /dev/null +++ b/targets/TI-SimpleLink/common/FreeRTOS-openocd.c @@ -0,0 +1,20 @@ +/* + * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer + * present in the kernel, so it has to be supplied by other means for + * OpenOCD's threads awareness. + * + * Add this file to your project, and, if you're using --gc-sections, + * ``--undefined=uxTopUsedPriority'' (or + * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final + * linking) to your LDFLAGS; same with all the other symbols you need. + */ + +#include "FreeRTOS.h" + +#ifdef __GNUC__ +#define USED __attribute__((used)) +#else +#define USED +#endif + +const int USED uxTopUsedPriority = configMAX_PRIORITIES - 1; diff --git a/targets/TI-SimpleLink/common/GenericPort.cpp b/targets/TI-SimpleLink/common/GenericPort.cpp new file mode 100644 index 0000000000..d7d75b3256 --- /dev/null +++ b/targets/TI-SimpleLink/common/GenericPort.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nanoCLR_Types.h" +#include "nanoCLR_Runtime.h" + +uint32_t GenericPort_Write( int portNum, const char* data, size_t size ) +{ + (void)portNum; + if (g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions == CLR_RT_ExecutionEngine::c_fDebugger_StateProgramRunning) + { + char* p = (char*)data; + int counter = 0; + + // send characters directly to the trace port + while(*p != '\0' || counter < (int)size) + { + // ets_printf( "%c", *p++); + counter++; + } + return counter; + } + else + { + return (uint32_t)size; + } +} diff --git a/targets/TI-SimpleLink/common/Target_BlockStorage.c b/targets/TI-SimpleLink/common/Target_BlockStorage.c new file mode 100644 index 0000000000..19b3af659d --- /dev/null +++ b/targets/TI-SimpleLink/common/Target_BlockStorage.c @@ -0,0 +1,120 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +// #include + +/////////////////////////////////////////////////// +// BlockStream +/////////////////////////////////////////////////// +bool BlockStorageStream_Initialize(BlockStorageStream* stream, unsigned int blockUsage) +{ + // 'reset' CurrentIndex + stream->CurrentIndex = 0; + + stream->BlockLength = 0; + + // set usage according to parameter + stream->Usage = blockUsage; + + // initialize base address and length from linker symbols + if(blockUsage == StorageUsage_CLR) + { + // set BaseAddress to the start of the region + stream->BaseAddress = (unsigned int)&__nanoImage_start__; + // set Length to the region size + // need to cast the pointers to make sure the compiler implements the correct math + stream->Length = ((uint32_t)&__nanoImage_end__) - ((uint32_t)&__nanoImage_start__); + } + else if(blockUsage == StorageUsage_DEPLOYMENT) + { + // set BaseAddress to the start of the region + // FIXME TODO + //stream->BaseAddress = (unsigned int)g_esp32_flash_start_ptr; + // set Length to the region size + // need to cast the pointers to make sure the compiler implements the correct math + // FIXME TODO + //stream->Length = (uint32_t)g_pFlashDriver_partition->size; + } + + return true; +} + +/////////////////////////////////////////////////// +// BlockStorageList +/////////////////////////////////////////////////// + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +BlockStorageList BlockStorage; + +// map here the Block Storage Interface to the ESP32 driver +IBlockStorageDevice ESP32Flash_BlockStorageInterface = +{ + // FIXME TODO + // &Esp32FlashDriver_InitializeDevice, + // &Esp32FlashDriver_UninitializeDevice, + // &Esp32FlashDriver_GetDeviceInfo, + // &Esp32FlashDriver_Read, + // &Esp32FlashDriver_Write, + // NULL, + // &Esp32FlashDriver_IsBlockErased, + // &Esp32FlashDriver_EraseBlock, + // &Esp32FlashDriver_SetPowerState +}; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &ESP32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} + +bool BlockStorageList_FindDeviceForPhysicalAddress(BlockStorageDevice** pBSD, unsigned int physicalAddress, ByteAddress* blockAddress) +{ + *pBSD = NULL; + + BlockStorageDevice* block = (BlockStorageDevice*)BlockStorageList_GetFirstDevice; + + // this has to add to make metadataprocessor happy + if(!block) return true; + + DeviceBlockInfo* pDeviceInfo = BlockStorageDevice_GetDeviceInfo((BlockStorageDevice*)&block); + + for(unsigned int i=0; i < pDeviceInfo->NumRegions; i++) + { + BlockRegionInfo* pRegion = &pDeviceInfo->Regions[i]; + + if(pRegion->Start <= physicalAddress && physicalAddress < (pRegion->Start + pRegion->NumBlocks * pRegion->BytesPerBlock)) + { + *pBSD = block; + + // get block start address + *blockAddress = (ByteAddress)((physicalAddress - pRegion->Start) / pRegion->BytesPerBlock); + *blockAddress *= pRegion->BytesPerBlock; + *blockAddress += pRegion->Start; + + return true; + } + } + + return false; +} + +bool BlockStorageList_AddDevice(BlockStorageDevice* pBSD, IBlockStorageDevice* vtable, void* config, bool init) +{ + (void)init; + + pBSD->m_BSD = vtable; + pBSD->m_context = config; + + BlockStorage.PrimaryDevice = pBSD; + + return true; +} + +BlockStorageDevice* BlockStorageList_GetFirstDevice() +{ + return BlockStorage.PrimaryDevice; +} diff --git a/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c b/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c new file mode 100644 index 0000000000..f7b487894e --- /dev/null +++ b/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c @@ -0,0 +1,141 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#include + +#include +#include +#include +#include + +WP_Message inboundMessage; + +bool WP_Initialise(COM_HANDLE port); + +//////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////// +// The functions bellow are the ones that need to be ported to new channels/HALs when required +// These are to be considered as a reference implementations when working on new ports +// +// This reference implementation provides communication through: +// - serial port (UART/USART) +// +//////////////////////////////////////////////////////////////////////////////////////////////// +#if (HAL_USE_SERIAL == TRUE) + +static bool WP_Port_Intitialised = false; +// static uart_port_t WP_Port = UART_NUM_0; + +// #define ESP32_UART_RXD_PINS {3,32,16} +// #define ESP32_UART_TXD_PINS {1,33,17} +// #define ESP32_UART_CTS_PINS {19,6,8} +// #define ESP32_UART_RTS_PINS {22,11,7} + + +// // Pins +// static const char g_ESP32_Uart_RxD_Pins[] = ESP32_UART_RXD_PINS; +// static const char g_ESP32_Uart_TxD_Pins[] = ESP32_UART_TXD_PINS; + + +bool WP_Initialise(COM_HANDLE port) +{ + (void)port; + + // if ( WP_Port > UART_NUM_2 ) return false; + + // uart_config_t uart_config = { + // .baud_rate = 115200, //baudrate + // .data_bits = UART_DATA_8_BITS, //data bit mode + // .parity = UART_PARITY_DISABLE, //parity mode + // .stop_bits = UART_STOP_BITS_1, //stop bit mode + // .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, //hardware flow control(cts/rts) + // .rx_flow_ctrl_thresh = 120, //flow control threshold + // }; + + // uart_param_config(WP_Port, &uart_config); + + // uart_set_pin(WP_Port, g_ESP32_Uart_TxD_Pins[WP_Port], g_ESP32_Uart_RxD_Pins[WP_Port], UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + + // // Setup UART driver(without UART queue) + // uart_driver_install(WP_Port, 1024 * 2, 512, 0, NULL, 0); + + WP_Port_Intitialised = true; + + return true; +} + + +int WP_ReceiveBytes(uint8_t* ptr, uint16_t* size) +{ + // TODO: Initialise Port if not already done, Wire Protocol should be calling this directly at startup + //if (!WP_Port_Intitialised) WP_Initialise(WP_Port); + + // save for latter comparison + uint16_t requestedSize = *size; + + // //int readData = 0; + // // sanity check for request of 0 size + // if(*size) + // { + // ////////////////////////////////////////////////////////// + // // PORTING CHANGE REQUIRED HERE // + // ////////////////////////////////////////////////////////// + // // change here to read (size) bytes from the input stream + // // preferably with read timeout and being able to check + // // if the requested number of bytes was actually read + // ////////////////////////////////////////////////////////// + + // // non blocking read from serial port with 100ms timeout + // volatile size_t read = uart_read_bytes( WP_Port, ptr, (uint32_t)requestedSize, (TickType_t) 100 / portTICK_PERIOD_MS); + + // ptr += read; + // *size -= read; + + // // check if the requested read matches the actual read count + // return (requestedSize == read); + // } + + return true; +} + +#else +#error "Wire Protocol needs a transport." +#endif + +#if (HAL_USE_SERIAL == TRUE) + +int WP_TransmitMessage(WP_Message* message) +{ + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // change here to write (size) bytes to the output stream + // preferably with timeout and being able to check + // if the write was sucessfull or at least buffered + ////////////////////////////////////////////////////////// + + //if (!WP_Port_Intitialised) WP_Initialise(WP_Port); + + //TODO Check if timeout required + // write header to output stream + + //if ( uart_write_bytes( WP_Port, (const char*)&message->m_header, sizeof(message->m_header) ) != sizeof(message->m_header)) return false; + + // if there is anything on the payload send it to the output stream + if(message->m_header.m_size && message->m_payload) + { + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // see description above + ////////////////////////////////////////////////////////// + //if (uart_write_bytes(WP_Port, (const char*)message->m_payload, message->m_header.m_size ) != (int)message->m_header.m_size ) return false; + } + + return true; +} + +#else +#error "Wire Protocol needs a transport." +#endif diff --git a/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c b/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c new file mode 100644 index 0000000000..f3413e7d71 --- /dev/null +++ b/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "WireProtocol_HAL_Interface.h" + +extern WP_Message inboundMessage; + +void WP_Message_Initialize(WP_Message* a); +void WP_Message_PrepareReception(WP_Message* a); +void WP_Message_Process(WP_Message* a); + +void ReceiverThread(void const * argument) +{ + (void)argument; + + // loop forever + while (1) + { + + WP_Message_Initialize(&inboundMessage); + WP_Message_PrepareReception(&inboundMessage); + + WP_Message_Process(&inboundMessage); + + // Allow other tasks a chance to run + vTaskDelay(0); + } +} diff --git a/targets/TI-SimpleLink/common/platform_heap.c b/targets/TI-SimpleLink/common/platform_heap.c new file mode 100644 index 0000000000..d2507def1a --- /dev/null +++ b/targets/TI-SimpleLink/common/platform_heap.c @@ -0,0 +1,18 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void* platform_malloc(size_t size) { + return malloc(size); +} + +void platform_free(void* ptr) { + free(ptr); +} + +void* platform_realloc(void* ptr, size_t size) { + return realloc(ptr, size); +} diff --git a/targets/TI-SimpleLink/common/rules_clr.ld b/targets/TI-SimpleLink/common/rules_clr.ld new file mode 100644 index 0000000000..e93593855b --- /dev/null +++ b/targets/TI-SimpleLink/common/rules_clr.ld @@ -0,0 +1,15 @@ + SECTIONS +{ + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = LOADADDR(.clr_managed_heap)); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM +} diff --git a/targets/TI-SimpleLink/common/syscalls.c b/targets/TI-SimpleLink/common/syscalls.c new file mode 100644 index 0000000000..e56deb951a --- /dev/null +++ b/targets/TI-SimpleLink/common/syscalls.c @@ -0,0 +1,45 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// these are stubs to keep the linker happy when these are pulled in + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * _gettimeofday primitive (Stub function) + * */ + +/* + * Structure used in select() call, taken from the BSD file sys/time.h. + */ +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; + +struct timezone { + int tz_minuteswest; /* minutes west of Greenwich */ + int tz_dsttime; /* type of dst correction */ +}; + +int _gettimeofday (struct timeval * tp, struct timezone * tzp) +{ + (void)tp; + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp b/targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp new file mode 100644 index 0000000000..d57bb57f0a --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp @@ -0,0 +1,354 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include + +struct Settings +{ + CLR_SETTINGS m_clrOptions; + bool m_fInitialized; + + //--// + + HRESULT Initialize(CLR_SETTINGS params) + { + NANOCLR_HEADER(); + + m_clrOptions = params; + + NANOCLR_CHECK_HRESULT(CLR_RT_ExecutionEngine::CreateInstance()); +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Created EE.\r\n" ); +#endif + +#if !defined(BUILD_RTM) + if(params.WaitForDebugger) + { + CLR_EE_DBG_SET( Stopped ); + } +#endif + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.StartHardware()); +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Started Hardware.\r\n" ); +#endif + + m_fInitialized = true; + + NANOCLR_NOCLEANUP(); + } + + + HRESULT LoadAssembly( const CLR_RECORD_ASSEMBLY* header, CLR_RT_Assembly*& assm ) + { + NANOCLR_HEADER(); + + const CLR_RT_NativeAssemblyData *pNativeAssmData; + + NANOCLR_CHECK_HRESULT(CLR_RT_Assembly::CreateInstance( header, assm )); + + // Get handlers for native functions in assembly + pNativeAssmData = GetAssemblyNativeData( assm->m_szName ); + + // If pNativeAssmData not NULL- means this assembly has native calls and there is pointer to table with native calls. + if ( pNativeAssmData != NULL ) + { + // First verify that check sum in assembly object matches hardcoded check sum. + if ( assm->m_header->nativeMethodsChecksum != pNativeAssmData->m_checkSum ) + { + CLR_Debug::Printf("***********************************************************************\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* ERROR!!!! Firmware version does not match managed code version!!!! *\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* Invalid native checksum: %s 0x%08X!=0x%08X *\r\n", + assm->m_szName, + assm->m_header->nativeMethodsChecksum, + pNativeAssmData->m_checkSum + ); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("***********************************************************************\r\n"); + + NANOCLR_SET_AND_LEAVE(CLR_E_ASSM_WRONG_CHECKSUM); + } + + // Assembly has valid pointer to table with native methods. Save it. + assm->m_nativeCode = (const CLR_RT_MethodHandler *)pNativeAssmData->m_pNativeMethods; + } + g_CLR_RT_TypeSystem.Link( assm ); + NANOCLR_NOCLEANUP(); + } + + + HRESULT Load() + { + NANOCLR_HEADER(); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Create TS.\r\n" ); +#endif + //NANOCLR_CHECK_HRESULT(LoadKnownAssemblies( (char*)&__deployment_start__, (char*)&__deployment_end__ )); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Loading Deployment Assemblies.\r\n" ); +#endif + + LoadDeploymentAssemblies(); + + //--// + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolving.\r\n" ); +#endif + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.ResolveAll()); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.PrepareForExecution()); + +#if defined(NANOCLR_PROFILE_HANDLER) + CLR_PROF_Handler::Calibrate(); +#endif + + NANOCLR_CLEANUP(); + +#if !defined(BUILD_RTM) + if(FAILED(hr)) CLR_Debug::Printf( "Error: %08x\r\n", hr ); +#endif + + NANOCLR_CLEANUP_END(); + } + + HRESULT LoadKnownAssemblies( char* start, char* end ) + { + //--// + NANOCLR_HEADER(); + char *assStart = start; + char *assEnd = end; + const CLR_RECORD_ASSEMBLY* header; + +#if !defined(BUILD_RTM) + CLR_Debug::Printf(" Loading start at %x, end %x\r\n", (unsigned int)assStart, (unsigned int)assEnd); +#endif + + g_buildCRC = SUPPORT_ComputeCRC( assStart, (unsigned int)assEnd -(unsigned int) assStart, 0 ); + + + header = (const CLR_RECORD_ASSEMBLY*)assStart; + + while((char*)header + sizeof(CLR_RECORD_ASSEMBLY) < assEnd && header->GoodAssembly()) + { + CLR_RT_Assembly* assm; + + // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem + NANOCLR_CHECK_HRESULT(LoadAssembly( header, assm )); + + header = (const CLR_RECORD_ASSEMBLY*)ROUNDTOMULTIPLE((size_t)header + header->TotalSize(), CLR_UINT32); + } + + NANOCLR_NOCLEANUP(); + } + + + HRESULT ContiguousBlockAssemblies(BlockStorageStream stream) + { + NANOCLR_HEADER(); + + const CLR_RECORD_ASSEMBLY* header; + unsigned char * assembliesBuffer ; + unsigned int headerInBytes = sizeof(CLR_RECORD_ASSEMBLY); + unsigned char * headerBuffer = NULL; + + while(stream.CurrentIndex < stream.Length) + { + // check if there is enough stream length to continue + if((stream.Length - stream.CurrentIndex ) < headerInBytes) + { + // not enough stream to read, leave now + break; + } + + if(!BlockStorageStream_Read(&stream, &headerBuffer, headerInBytes )) break; + + header = (const CLR_RECORD_ASSEMBLY*)headerBuffer; + + // check header first before read + if(!header->GoodHeader()) + { + // check failed, try to continue to the next + continue; + } + + unsigned int assemblySizeInByte = ROUNDTOMULTIPLE(header->TotalSize(), CLR_UINT32); + + // advance stream beyond header + BlockStorageStream_Seek(&stream, -headerInBytes, BlockStorageStream_SeekCurrent); + + // read the assembly + if(!BlockStorageStream_Read(&stream, &assembliesBuffer, assemblySizeInByte)) break; + + header = (const CLR_RECORD_ASSEMBLY*)assembliesBuffer; + + if(!header->GoodAssembly()) + { + // check failed, try to continue to the next + continue; + } + + // we have good Assembly + CLR_RT_Assembly* assm; + + CLR_Debug::Printf( "Attaching deployed file.\r\n" ); + + // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem + if (FAILED(LoadAssembly(header, assm))) + { + // load failed, try to continue to the next + continue; + } + + // load successfull, mark as deployed + assm->m_flags |= CLR_RT_Assembly::Deployed; + } + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT LoadDeploymentAssemblies() + { + NANOCLR_HEADER(); + + // perform initialization of BlockStorageStream structure + BlockStorageStream stream; + + // init the stream for deployment storage + if (!BlockStorageStream_Initialize(&stream, StorageUsage_DEPLOYMENT)) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "ERROR: failed to initialize DEPLOYMENT storage\r\n" ); +#endif + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + ContiguousBlockAssemblies(stream); + + NANOCLR_NOCLEANUP(); + } + + void Cleanup() + { + CLR_RT_ExecutionEngine::DeleteInstance(); + + memset( &g_CLR_RT_ExecutionEngine, 0, sizeof(g_CLR_RT_ExecutionEngine)); + memset( &g_CLR_RT_WellKnownTypes, 0, sizeof(g_CLR_RT_WellKnownTypes)); + memset( &g_CLR_RT_WellKnownMethods, 0, sizeof(g_CLR_RT_WellKnownMethods)); + memset( &g_CLR_RT_TypeSystem, 0, sizeof(g_CLR_RT_TypeSystem)); + memset( &g_CLR_RT_EventCache, 0, sizeof(g_CLR_RT_EventCache)); + memset( &g_CLR_RT_GarbageCollector, 0, sizeof(g_CLR_RT_GarbageCollector)); + memset( &g_CLR_HW_Hardware, 0, sizeof(g_CLR_HW_Hardware)); + + m_fInitialized = false; + } + + Settings() + { + m_fInitialized = false; + } + +}; + + +static Settings s_ClrSettings; + +void ClrStartup(CLR_SETTINGS params) +{ + NATIVE_PROFILE_CLR_STARTUP(); + Settings settings; + ASSERT(sizeof(CLR_RT_HeapBlock_Raw) == sizeof(CLR_RT_HeapBlock)); + bool softReboot; + + do + { + softReboot = false; + + CLR_RT_Assembly::InitString(); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "\r\nnanoCLR (Build %d.%d.%d.%d)\r\n\r\n", VERSION_MAJOR, VERSION_MINOR, VERSION_BUILD, VERSION_REVISION ); +#endif + + CLR_RT_Memory::Reset(); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Starting...\r\n" ); +#endif + + + HRESULT hr; + + if(SUCCEEDED(hr = s_ClrSettings.Initialize(params))) + { + if(SUCCEEDED(hr = s_ClrSettings.Load())) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Ready.\r\n" ); +#endif + + (void)g_CLR_RT_ExecutionEngine.Execute( NULL, params.MaxContextSwitches ); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Done.\r\n" ); +#endif + } + } + + // process setting of power mode, if reboot was requested along with a power mode "higher" then PowerLevel__Active + if(CLR_EE_REBOOT_IS( ClrOnly ) && g_CLR_HW_Hardware.m_powerLevel > PowerLevel__Active) + { + CPU_SetPowerMode(g_CLR_HW_Hardware.m_powerLevel); + } + + if( CLR_EE_DBG_IS_NOT( RebootPending )) + { +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_EE_DBG_SET_MASK(StateProgramExited, StateMask); + CLR_EE_DBG_EVENT_BROADCAST(CLR_DBG_Commands::c_Monitor_ProgramExit, 0, NULL, WP_Flags_c_NonCritical); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(params.EnterDebuggerLoopAfterExit) + { + CLR_DBG_Debugger::Debugger_WaitForCommands(); + } + } + + // DO NOT USE 'ELSE IF' here because the state can change in Debugger_WaitForCommands() call + + if( CLR_EE_DBG_IS( RebootPending )) + { + if(CLR_EE_REBOOT_IS( ClrOnly )) + { + softReboot = true; + + params.WaitForDebugger = CLR_EE_REBOOT_IS(WaitForDebugger); + + s_ClrSettings.Cleanup(); + + nanoHAL_Uninitialize(); + + //re-init the hal for the reboot (initially it is called in bootentry) + nanoHAL_Initialize(); + } + else + { + CPU_Reset(); + } + } + + } while( softReboot ); + +} diff --git a/targets/TI-SimpleLink/nanoCLR/CLR_RT_InteropAssembliesTable.cpp.in b/targets/TI-SimpleLink/nanoCLR/CLR_RT_InteropAssembliesTable.cpp.in new file mode 100644 index 0000000000..23341df577 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/CLR_RT_InteropAssembliesTable.cpp.in @@ -0,0 +1,23 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#include + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_mscorlib; +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Native; +@CLR_RT_NativeAssemblyDataDeclarations@ + +const CLR_RT_NativeAssemblyData *g_CLR_InteropAssembliesNativeData[] = +{ + &g_CLR_AssemblyNative_mscorlib, + &g_CLR_AssemblyNative_nanoFramework_Runtime_Native, + @CLR_RT_NativeAssemblyDataTableEntries@ + NULL +}; diff --git a/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c b/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c new file mode 100644 index 0000000000..7dd1dd19d6 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c @@ -0,0 +1,19 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +void CLRStartupThread(void const * argument) +{ + CLR_SETTINGS* clrSettings = (CLR_SETTINGS*)argument; + + nanoHAL_Initialize_C(); + + ClrStartup(*clrSettings); + + // nothing to deinitialize or cleanup, so it's safe to return +} diff --git a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt new file mode 100644 index 0000000000..e4502a2dde --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt @@ -0,0 +1,86 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +include(NF_NativeAssemblies) + +# add header file with common target definitions +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_platform.h" @ONLY) + +# append nanoHAL +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp") + +# append target ChibiOS nanoCLR source files +# list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_App_Interface.c) +# list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c) +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CLR_Startup_Thread.c") +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c") + +# append target HAL source files +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Power.c") +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp") + +# append watchdog only if option is ON +# if(HAL_USE_WDG_OPTION) +# list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Watchdog.c") +# endif() + +# append target PAL source files +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Events.cpp") +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Time.cpp") + +# append other CLR core files +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CLRStartup.cpp") +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Memory.cpp") + +# append nanoCRT +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoCRT.cpp") + +# append files from Runtime.Native +# list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp") + +# append TRNG only if option is ON +if(USE_RNG) + + # # append random implementation for all series, except F0 + # if( ${TARGET_SERIES} STREQUAL "STM32L0xx" OR + # ${TARGET_SERIES} STREQUAL "STM32F4xx" OR + # ${TARGET_SERIES} STREQUAL "STM32F7xx" OR + # ${TARGET_SERIES} STREQUAL "STM32H7xx") + + # list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetRandom.cpp") + + # else() + # # this series doesn't feature hardware TRNG, report + # message(ERROR "This CPU doesn't have a Random Number Generation. Please change USE_RNG option to OFF.") + # endif() + +endif() + +# add native assemblies +ParseNativeAssemblies() + +# configure code file with Interop Assemblies table and... +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/CLR_RT_InteropAssembliesTable.cpp.in" + "${CMAKE_CURRENT_BINARY_DIR}/CLR_RT_InteropAssembliesTable.cpp" @ONLY) +# ... now add Interop Assemblies table to ChibiOS nanoCLR sources list +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_BINARY_DIR}/CLR_RT_InteropAssembliesTable.cpp") + +# make var global +set(TARGET_TI_SimpleLink_NANOCLR_SOURCES ${TARGET_TI_SimpleLink_NANOCLR_SOURCES} CACHE INTERNAL "make global") + +# append target ChibiOS nanoCLR include directory +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}) +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_BINARY_DIR}) +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) + +# append PAL include directory +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) + +# append Runtime.Native include directory +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Runtime.Native) + +# make var global +set(TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/targets/TI-SimpleLink/nanoCLR/Memory.cpp b/targets/TI-SimpleLink/nanoCLR/Memory.cpp new file mode 100644 index 0000000000..e488b377c9 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Memory.cpp @@ -0,0 +1,30 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +// void HeapLocation(unsigned char*& baseAddress, unsigned int& sizeInBytes) +// { +// NATIVE_PROFILE_PAL_HEAP(); + +// baseAddress = (unsigned char*) &HeapBegin; +// sizeInBytes = (unsigned int)((size_t)&HeapEnd - (size_t)&HeapBegin); +// } + +// Define an area for the CLR managed heap +#if !defined(MANAGED_HEAP_SIZE) +#define MANAGED_HEAP_SIZE (64*1024) +#endif + +uint32_t managedHeap[MANAGED_HEAP_SIZE/ sizeof(uint32_t)]; + +void HeapLocation(unsigned char*& baseAddress, unsigned int& sizeInBytes) +{ + NATIVE_PROFILE_PAL_HEAP(); + + baseAddress = (unsigned char*)&managedHeap; + sizeInBytes = sizeof(managedHeap); +} diff --git a/targets/TI-SimpleLink/nanoCLR/nanoCRT.cpp b/targets/TI-SimpleLink/nanoCLR/nanoCRT.cpp new file mode 100644 index 0000000000..45e1fa3ecb --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/nanoCRT.cpp @@ -0,0 +1,205 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +//--// +/* STDIO stubs */ +//--// + +#if !defined(BUILD_RTM) + +void hal_fprintf_SetLoggingCallback( LOGGING_CALLBACK fpn ) +{ + (void)fpn; + NATIVE_PROFILE_PAL_CRT(); + +} + +#endif + +//--// + +#if defined(PLATFORM_EMULATED_FLOATINGPOINT) + +// no floating point, fixed point + +int hal_snprintf_float( char* buffer, size_t len, const char* format, int32_t f ) +{ + NATIVE_PROFILE_PAL_CRT(); + + uint32_t i ; + uint32_t dec; + + if ( f < 0 ) + { + // negative number + i = (uint32_t) -f ; + dec = i & (( 1<>HAL_FLOAT_SHIFT); + + if (dec !=0) dec = (dec * (uint32_t)HAL_FLOAT_PRECISION + (1<< (HAL_FLOAT_SHIFT-1))) >>HAL_FLOAT_SHIFT; + + return hal_snprintf( buffer, len, "-%d.%03u", i, (uint32_t)dec); + + } + else + { + // positive number + i = (uint32_t) f ; + dec = f & (( 1<>HAL_FLOAT_SHIFT); + + if (dec !=0) dec = (dec * (uint32_t)HAL_FLOAT_PRECISION + (1<< (HAL_FLOAT_SHIFT-1))) >>HAL_FLOAT_SHIFT; + + return hal_snprintf( buffer, len, "%d.%03u", i, (uint32_t)dec); + } +} + +int hal_snprintf_double( char* buffer, size_t len, const char* format, int64_t& d ) +{ + NATIVE_PROFILE_PAL_CRT(); + + uint64_t i; + uint32_t dec; // 32 bit is enough for decimal part + + if ( d < 0 ) + { + // negative number + i = (uint64_t)-d; + + i += ((1 << (HAL_DOUBLE_SHIFT-1)) / HAL_DOUBLE_PRECISION); // add broad part of rounding increment before split + + dec = i & (( 1<> HAL_DOUBLE_SHIFT ; + + if (dec !=0) dec = (dec * HAL_DOUBLE_PRECISION + ((1 << (HAL_DOUBLE_SHIFT-1)) % HAL_DOUBLE_PRECISION)) >> HAL_DOUBLE_SHIFT; + + return hal_snprintf( buffer, len, "-%lld.%04u", (int64_t)i, (uint32_t)dec); + + } + else + { + + // positive number + i = (uint64_t)d; + + i += ((1 << (HAL_DOUBLE_SHIFT-1)) / HAL_DOUBLE_PRECISION); // add broad part of rounding increment before split + + dec = i & (( 1<> HAL_DOUBLE_SHIFT; + + if (dec !=0) dec = (dec * HAL_DOUBLE_PRECISION + ((1 << (HAL_DOUBLE_SHIFT-1)) % HAL_DOUBLE_PRECISION)) >> HAL_DOUBLE_SHIFT; + + return hal_snprintf( buffer, len, "%lld.%04u", (int64_t)i, (uint32_t)dec); + } +} + +#else + +#endif + +// because debug_printf needs to be called in both C and C++ we need a proxy to allow it to be called in 'C' +extern "C" { + +#if !defined(BUILD_RTM) + + void debug_printf(const char* format, ...) + { + char buffer[256]; + va_list arg_ptr; + + va_start( arg_ptr, format ); + + int len = vsnprintf( buffer, sizeof(buffer)-1, format, arg_ptr ); + + DebuggerPort_Write( HalSystemConfig.stdio, buffer, len, 0 ); // skip null terminator + + va_end( arg_ptr ); + } + +#else + __inline void debug_printf( const char *format, ... ) {} +#endif // !defined(BUILD_RTM) +} + +int hal_strcpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strcpy + + size_t len; + if(strDst == NULL || strSrc == NULL || sizeInBytes == 0) {_ASSERTE(FALSE); return 1;} + + len = hal_strlen_s(strSrc); + if(sizeInBytes < len + 1) {_ASSERTE(FALSE); return 1;} + + strcpy( strDst, strSrc ); + return 0; + +#define strcpy DoNotUse_*strcpy [] +} + +int hal_strncpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc, size_t count ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strncpy + if(strDst == NULL || strSrc == NULL || sizeInBytes == 0) {_ASSERTE(FALSE); return 1;} + + if (sizeInBytes < count + 1) + { + _ASSERTE(FALSE); + strDst[0] = 0; + return 1; + } + + strDst[count] = 0; + strncpy( strDst, strSrc, count ); + return 0; + +#define strncpy DoNotUse_*strncpy [] +} + +size_t hal_strlen_s (const char * str) +{ + NATIVE_PROFILE_PAL_CRT(); + + const char *eos = str; + while( *eos++ ) ; + return( eos - str - 1 ); +} + +int hal_strncmp_s ( const char* str1, const char* str2, size_t num ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strncmp + if(str1 == NULL || str2 == NULL) {_ASSERTE(FALSE); return 1;} + + return strncmp( str1, str2, num ); + +#define strncmp DoNotUse_*strncmp [] +} + +// Compares 2 ASCII strings case insensitive. Does not take locale into account. +int hal_stricmp( const char * dst, const char * src ) +{ + int f = 0, l = 0; + + do + { + if ( ((f = (unsigned char)(*(dst++))) >= 'A') && (f <= 'Z') ) + { + f -= 'A' - 'a'; + } + if ( ((l = (unsigned char)(*(src++))) >= 'A') && (l <= 'Z') ) + { + l -= 'A' - 'a'; + } + } + while ( f && (f == l) ); + + return(f - l); +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp b/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp new file mode 100644 index 0000000000..8da9cd23fb --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp @@ -0,0 +1,147 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include + +// +// Reboot handlers clean up on reboot +// +static ON_SOFT_REBOOT_HANDLER s_rebootHandlers[16] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; + +void HAL_AddSoftRebootHandler(ON_SOFT_REBOOT_HANDLER handler) +{ + for(unsigned int i=0; i 0) ? true : false; +} + +void SystemState_Set(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(irq); + + SystemState_SetNoLock(state); + + GLOBAL_UNLOCK(irq); +} + +void SystemState_Clear(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(irq); + + SystemState_ClearNoLock(state ); + + GLOBAL_UNLOCK(irq); +} + +bool SystemState_Query(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(irq); + + return SystemState_QueryNoLock(state); + + GLOBAL_UNLOCK(irq); +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c b/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c new file mode 100644 index 0000000000..4f5e6a9616 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c @@ -0,0 +1,29 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// FIXME TODO +inline void CPU_Reset(){ }; + +// CPU sleep is not currently implemented in this target +inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents){ (void)level; (void)wakeEvents; }; + +inline bool CPU_IsSoftRebootSupported() { return true; }; + +void CPU_SetPowerMode(PowerLevel_type powerLevel) +{ + switch(powerLevel) + { + case PowerLevel__Off: + // gracefully shutdown everything + // FIXME TODO + break; + + default: + // all the other power modes are unsupported here + break; + } +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp b/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp new file mode 100644 index 0000000000..171e965f5b --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp @@ -0,0 +1,133 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include +#include + +// Converts FreeRTOS Tickcount to .NET ticks (100 nanoseconds) +uint64_t HAL_Time_SysTicksToTime(unsigned int sysTicks) +{ + return (((int64_t)sysTicks * (int64_t)1000000 + (int64_t)configTICK_RATE_HZ - 1) / (int64_t)configTICK_RATE_HZ) * 10; +} + +// Returns the current date time from the RTC +uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) +{ + SYSTEMTIME st; + + //struct timeval tv; + + //gettimeofday(&tv, NULL); + + // Convert from Unix time(year since 1900) to SYSTEMTIME(Years since 1601) + //int64_t time = ((int64_t)tv.tv_sec * (int64_t)TIME_CONVERSION__TO_SECONDS) + TIME_UNIX_EPOCH_AS_TICKS; + + //HAL_Time_ToSystemTime(time, &st ); + + // zero 'time' fields if date part only is required + if(datePartOnly) + { + st.wMilliseconds = 0; + st.wSecond = 0; + st.wMinute = 0; + st.wHour = 0; + } + + return HAL_Time_ConvertFromSystemTime( &st ); +}; + +void HAL_Time_SetUtcTime(uint64_t utcTime) +{ + SYSTEMTIME systemTime; + + HAL_Time_ToSystemTime(utcTime, &systemTime); + + struct tm newTime; + + newTime.tm_year = systemTime.wYear - 1900; // years since 1900 + newTime.tm_mon = systemTime.wMonth - 1; // months since January 0-11 + newTime.tm_mday = systemTime.wDay; // day of the month 1-31 + newTime.tm_wday = systemTime.wDayOfWeek; // days since Sunday 0-6 + newTime.tm_hour = (uint32_t)systemTime.wHour; // hours since midnight 0-23 + newTime.tm_min = (uint32_t)systemTime.wMinute; // minutes after the hour 0-59 + newTime.tm_sec = (uint32_t)systemTime.wSecond; // seconds after the minute 0-59 + + time_t t = mktime(&newTime); + //struct timeval now = { .tv_sec = t, .tv_usec = 0 }; + //settimeofday(&now, NULL); +} + +bool HAL_Time_TimeSpanToStringEx( const int64_t& ticks, char*& buf, size_t& len ) +{ + uint64_t ticksAbs; + uint64_t rest; + + if(ticks < 0) + { + ticksAbs = -ticks; + + CLR_SafeSprintf( buf, len, "-" ); + } + else + { + ticksAbs = ticks; + } + + rest = ticksAbs % ( 1000 * TIME_CONVERSION__TICKUNITS); + ticksAbs = ticksAbs / ( 1000 * TIME_CONVERSION__TICKUNITS); // Convert to seconds. + + if(ticksAbs > TIME_CONVERSION__ONEDAY) // More than one day. + { + CLR_SafeSprintf( buf, len, "%d.", (int32_t)(ticksAbs / TIME_CONVERSION__ONEDAY) ); ticksAbs %= TIME_CONVERSION__ONEDAY; + } + + CLR_SafeSprintf( buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEHOUR) ); ticksAbs %= TIME_CONVERSION__ONEHOUR ; + CLR_SafeSprintf( buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEMINUTE)); ticksAbs %= TIME_CONVERSION__ONEMINUTE; + CLR_SafeSprintf( buf, len, "%02d" , (int32_t)(ticksAbs / TIME_CONVERSION__ONESECOND)); ticksAbs %= TIME_CONVERSION__ONESECOND; + + ticksAbs = (uint32_t)rest; + if(ticksAbs) + { + CLR_SafeSprintf( buf, len, ".%07d", (uint32_t)ticksAbs ); + } + + return len != 0; +} + +bool DateTimeToString(const int64_t& time, char*& buf, size_t& len ) +{ + SYSTEMTIME st; + + HAL_Time_ToSystemTime( time, &st ); + + return CLR_SafeSprintf(buf, len, "%4d/%02d/%02d %02d:%02d:%02d.%03d", st.wYear, st.wMonth, st.wDay, st.wHour, st.wMinute, st.wSecond, st.wMilliseconds ); +} + +char* DateTimeToString(const int64_t& time) +{ + static char rgBuffer[128]; + char* szBuffer = rgBuffer; + size_t iBuffer = ARRAYSIZE(rgBuffer); + + DateTimeToString( time, szBuffer, iBuffer ); + + return rgBuffer; +} + +const char* HAL_Time_CurrentDateTimeToString() +{ + return DateTimeToString(HAL_Time_CurrentDateTime(false)); +} + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks) +{ + return ((ticks * (uint64_t)configTICK_RATE_HZ) / 1000); +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetPAL.c b/targets/TI-SimpleLink/nanoCLR/targetPAL.c new file mode 100644 index 0000000000..d7b7376bc0 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetPAL.c @@ -0,0 +1,8 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp b/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp new file mode 100644 index 0000000000..bb79b5b357 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp @@ -0,0 +1,179 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks); + +// timer for bool events +static TimerHandle_t boolEventsTimer; +static bool* saveTimerCompleteFlag = 0; + +volatile uint32_t systemEvents; + +static void local_Events_SetBoolTimer_Callback( TimerHandle_t xTimer ); + +set_Event_Callback g_Event_Callback = NULL; +void* g_Event_Callback_Arg = NULL; + +bool Events_Initialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // init events + systemEvents = 0; + + boolEventsTimer = xTimerCreate( "boolEventsTimer", 10, pdFALSE, (void *)0, local_Events_SetBoolTimer_Callback); + + return true; +} + +bool Events_Uninitialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + xTimerDelete(boolEventsTimer,0); + + return true; +} + +void Events_Set( uint32_t events ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // set events + systemEvents |= events; + + if( g_Event_Callback != NULL ) + { + g_Event_Callback( g_Event_Callback_Arg ); + } +} + +uint32_t Events_Get( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // get the requested flags from system events state and... + uint32_t returnEvents = (systemEvents & eventsOfInterest); + + // ... clear the requested flags atomically + systemEvents &= ~eventsOfInterest; + + // give the caller notice of just the events they asked for ( and were cleared already ) + return returnEvents; +} + +uint32_t Events_MaskedRead( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + return (systemEvents & eventsOfInterest); +} + +static void local_Events_SetBoolTimer_Callback( TimerHandle_t xTimer ) +{ + (void)xTimer; + + NATIVE_PROFILE_PAL_EVENTS(); + + *saveTimerCompleteFlag = true; +} + +void Events_SetCallback( set_Event_Callback pfn, void* arg ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + g_Event_Callback = pfn; + g_Event_Callback_Arg = arg; +} + +void Events_SetBoolTimer( bool* timerCompleteFlag, uint32_t millisecondsFromNow ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // we assume only 1 can be active, abort previous just in case + xTimerStop( boolEventsTimer, 0 ); + + if(timerCompleteFlag != NULL) + { + + xTimerChangePeriod( boolEventsTimer, millisecondsFromNow / portTICK_PERIOD_MS, 0 ); + +// Was going to just change existing timer but vTimerSetTimerID() does not exist in this version of FreeRTOS +// As only one timer running at a time we will just save it in global memory + saveTimerCompleteFlag = timerCompleteFlag; + // vTimerSetTimerID( boolEventsTimer, (void *)timerCompleteFlag ); + xTimerStart(boolEventsTimer, 0); + } +} + +uint32_t Events_WaitForEvents( uint32_t powerLevel, uint32_t wakeupSystemEvents, uint32_t timeoutMilliseconds ) +{ + // schedule an interrupt for this far in the future + // timeout is in milliseconds, need to convert to ticks + uint64_t countsRemaining = CPU_MillisecondsToTicks(timeoutMilliseconds); + + #if defined(HAL_PROFILE_ENABLED) + Events_WaitForEvents_Calls++; + #endif + + uint64_t expireTimeInTicks = HAL_Time_CurrentTime() + countsRemaining; + bool runContinuations = true; + + while(true) + { + uint32_t events = Events_MaskedRead( wakeupSystemEvents ); + if(events) + { + return events; + } + + if(expireTimeInTicks <= HAL_Time_CurrentTime()) + { + break; + } + + // first check and possibly run any continuations + // but only if we have slept after stalling + if(runContinuations && !SystemState_QueryNoLock(SYSTEM_STATE_NO_CONTINUATIONS)) + { + // if we stall on time, don't check again until after we sleep + runContinuations = HAL_CONTINUATION::Dequeue_And_Execute(); + } + else + { + // try stalled continuations again after sleeping + runContinuations = true; + + HAL_COMPLETION::WaitForInterrupts(expireTimeInTicks, powerLevel, wakeupSystemEvents ); + } + + // no events, pass control to the OS + taskYIELD(); + + // check if reboot or exit flags were set when the other OS threads executed + if(CLR_EE_DBG_IS(RebootPending) || CLR_EE_DBG_IS(ExitPending)) + { + break; + } + } + + return 0; +} + +void FreeManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2) +{ + (void)category; + (void)subCategory; + (void)data1; + (void)data2; + + NATIVE_PROFILE_PAL_EVENTS(); +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetPAL_Time.cpp b/targets/TI-SimpleLink/nanoCLR/targetPAL_Time.cpp new file mode 100644 index 0000000000..283f34ada5 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetPAL_Time.cpp @@ -0,0 +1,67 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +static TimerHandle_t nextEventTimer; + +static void NextEventTimer_Callback( TimerHandle_t xTimer ) +{ + (void)xTimer; + + // this call also schedules the next one, if there is one + HAL_COMPLETION::DequeueAndExec(); +} + +HRESULT Time_Initialize() +{ + nextEventTimer = xTimerCreate( "NextEventTimer", 10, pdFALSE, (void *)0, NextEventTimer_Callback); + + return S_OK; +} + +HRESULT Time_Uninitialize() +{ + xTimerDelete(nextEventTimer, 0); + + return S_OK; +} + +void Time_SetCompare ( uint64_t compareValueTicks ) +{ + if(compareValueTicks == 0) + { + // compare value is 0 so dequeue and schedule immediately + HAL_COMPLETION::DequeueAndExec(); + } + else if(compareValueTicks == HAL_COMPLETION_IDLE_VALUE) + { + // wait for infinity, don't need to do anything here + return; + } + else + { + if (HAL_Time_CurrentTime() >= compareValueTicks) + { + // already missed the event, dequeue and execute immediately + HAL_COMPLETION::DequeueAndExec(); + } + else + { + xTimerStop( nextEventTimer, 0 ); + + // compareValueTicks is the time (in sys ticks) that is being requested to fire an HAL_COMPLETION::DequeueAndExec() + // need to subtract the current system time to set when the timer will fire + compareValueTicks -= HAL_Time_CurrentTime(); + + // no need to stop the timer even if it's running because the API does it anyway + // need to convert from nF ticks to milliseconds and then to FreeRTOS sys ticks to load the timer + xTimerChangePeriod(nextEventTimer, compareValueTicks, 0); + } + } +} diff --git a/targets/TI-SimpleLink/nanoCLR/target_platform.h.in b/targets/TI-SimpleLink/nanoCLR/target_platform.h.in new file mode 100644 index 0000000000..04cdd7d1c8 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/target_platform.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_TI_SIMPLELINK_NANOCLR_H_ +#define _TARGET_TI_SIMPLELINK_NANOCLR_H_ + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif /* _TARGET_TI_SIMPLELINK_NANOCLR_H_ */ From fbd57f5472c40bdf422e638434acba4f78ea5b2a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Feb 2019 00:53:18 +0000 Subject: [PATCH 08/90] Remove unused CMake modules. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../CHIBIOS_TICC3200_GCC_options.cmake | 56 ---- CMake/Modules/CHIBIOS_TICC3200_sources.cmake | 298 ------------------ 2 files changed, 354 deletions(-) delete mode 100644 CMake/Modules/CHIBIOS_TICC3200_GCC_options.cmake delete mode 100644 CMake/Modules/CHIBIOS_TICC3200_sources.cmake diff --git a/CMake/Modules/CHIBIOS_TICC3200_GCC_options.cmake b/CMake/Modules/CHIBIOS_TICC3200_GCC_options.cmake deleted file mode 100644 index 6f9b84569c..0000000000 --- a/CMake/Modules/CHIBIOS_TICC3200_GCC_options.cmake +++ /dev/null @@ -1,56 +0,0 @@ -# -# Copyright (c) 2017 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# - -# FPU preference for using hardware FP unit or soft library -if(USE_FPU_IS_TRUE) - set(FLOAT_ABI_OPTION "-mfloat-abi=hard") -elseif() - set(FLOAT_ABI_OPTION "-mfloat-abi=soft") -endif() - -################################################################# -# WHEN ADDING A NEW SERIES add the appropriate GCC options bellow -################################################################# - -# need to specify this for assembler -set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") - -# need to specify linker flags here -# -mfpu=fpv5-sp-d16 -set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=soft -mabi=aapcs -nostartfiles -lgcc -lc -lm -lrdimon " CACHE INTERNAL "executable linker flags") - - -function(NF_SET_COMPILER_OPTIONS TARGET) - - # include any extra options comming from any extra args? - target_compile_options(${TARGET} PUBLIC ${ARGN} -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=soft -mabi=aapcs -gstrict-dwarf -nostdlib -Wall -w -static -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -mstructure-size-boundary=8 -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) - -endfunction() - - -function(NF_SET_LINKER_OPTIONS TARGET PRINTF_FLOAT_SUPPORT) - - # request to include support for float printf form newlib nano - if(PRINTF_FLOAT_SUPPORT) - set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs -u _printf_float") - else() - set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") - endif() - - # set extra linker flags - set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") - - # set optimization linker flags for RELEASE and MinSizeRel - if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") - set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fno-strict-aliasing ") - endif() - - # set optimization flags - nf_set_optimization_options(${TARGET}) - - # set link map - nf_set_link_map(${TARGET}) - -endfunction() diff --git a/CMake/Modules/CHIBIOS_TICC3200_sources.cmake b/CMake/Modules/CHIBIOS_TICC3200_sources.cmake deleted file mode 100644 index e4b9c22bde..0000000000 --- a/CMake/Modules/CHIBIOS_TICC3200_sources.cmake +++ /dev/null @@ -1,298 +0,0 @@ -# -# Copyright (c) 2017 The nanoFramework project contributors -# See LICENSE file in the project root for full license information. -# - -# List of the ChibiOS generic CC3200 startup and CMSIS files. - -# set include directories for CC3200 SDK -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/example/common) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/inc) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/driverlib) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/driver) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/driver/hal) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/framework/pm) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/framework/timer) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/middleware/soc) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/oslib) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink/include) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/include) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/flc) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/ota) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/simplelink_extlib/provisioninglib) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source/include) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source/portable/GCC/ARM_CM4) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/TI-RTOS/common/include) - -# XDC tools includes -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_XDCTOOLS_INSTALLATION_DIR}/packages) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_XDCTOOLS_INSTALLATION_DIR}/packages/xdc) -# # list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/xdc) -# # list(APPEND CHIBIOS_INCLUDE_DIRS ${TI_CC3200_SDK_PATH}/ti_rtos/ti_rtos_config/ewarm/iar/tirtos/ti/targets) - -# ChibiOS includes -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/license) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/include) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/boards/${CHIBIOS_BOARD}) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/osal/rt) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/oslib/include) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC) -# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/abstractions/cmsis_os) - -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/rt/include) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/abstractions/cmsis_os) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200) - - -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/CMSIS/include) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200) - -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART) -list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC) - - -# source files for CC3200 SDK -set(CHIBIOS_PORT_SRCS - - # startup code - crt1.c - vectors.c - crt0_v7m.S - - nvic.c - hal_lld.c - - # - hal_st_lld.c - hal_pal_lld.c - - # examples common - # button_if.c - # gpio_if.c - # i2c_if.c - # i2s_if.c - # network_common.c - # network_if.c - #######startup_gcc.c - # timer_if.c - # uart_if.c - # udma_if.c - # utils_if.c - # wdt_if.c - - # drivers - # adc.c - # aes.c - # camera.c - # cpu.c - # crc.c - # des.c - # flash.c - # gpio.c - # i2c.c - # i2s.c - # interrupt.c - # pin.c - # prcm.c - # sdhost.c - # shamd5.c - # spi.c - # systick.c - # timer.c - # uart.c - # udma.c - # utils.c - # wdt.c - - # middleware/driver/hal - # dma_hal.c - # gpio_hal.c - # hw_timer32.c - # hw_timer32.c - # rtc_hal.c - # spi_hal.c - # uart_hal.c - # util64.c - - # middleware/driver - # spi_drv.c - # uart_drv.c - - # middleware/framework/pm - # cc_pm.c - - # middleware/framework/timer - # cc_timer.c - - # middleware/soc - # cc_io_park.c - # cc_pm_ops.c - - # netapps - - # oslib - # osi_tirtos.c - # osi_freertos.c - # port.c - # heap_2.c - - # FreeRTOS - # croutine.c - # event_groups.c - # list.c - # queue.c - # tasks.c - # timers.c - - # simplelink - # cc_pal_pm.c - # cc_pal.c - # device.c - # flowcont.c - # fs.c - # netapp.c - # netcfg.c - # nonos.c - # socket.c - # spawn.c - # wlan.c - - # simplelink_extlib - # flc.c - # CdnClient.c - # LogClient.c - # OtaApp.c - # OtaClient.c - # OtaHttp.c - # cfg_confirm.c - # events_handler.c - # networkListHndl.c - # provisioning_logic.c - - - # # ChibiOS - - # # OSAL RT - # osal.c - - # # RT - # chsys.c - # chdebug.c - # chvt.c - # chschd.c - # chthreads.c - # chtm.c - # chstats.c - # chdynamic.c - # chregistry.c - # chsem.c - # chmtx.c - # chcond.c - # chevents.c - # chmsg.c - - # chheap.c - # chmboxes.c - # chmemcore.c - # chmempools.c - - # # required to use malloc and other newlib stuff - # syscalls.c - - # # CMSIS - # cmsis_os.c - - # # board file(s) - # # board.c - - # # RT - # chcore.c - # chcore_v7m.c - # chcoreasm_v7m.S - - # startup code - # crt1.c - # vectors.c - # crt0_v7m.S - - # nvic.c - # hal_lld.c - # hal_ext_lld_isr.c - -) - -foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) - set(CC3200_SCR_FILE SRC_FILE -NOTFOUND) - find_file(CC3200_SCR_FILE ${SRC_FILE} - PATHS - - # examples common - # ${TI_CC3200_SDK_PATH}/example/common - - # drivers - # ${TI_CC3200_SDK_PATH}/driverlib - - # middleware - # ${TI_CC3200_SDK_PATH}/middleware/driver - # ${TI_CC3200_SDK_PATH}/middleware/driver/hal - # ${TI_CC3200_SDK_PATH}/middleware/framework/pm - # ${TI_CC3200_SDK_PATH}/middleware/framework/timer - # ${TI_CC3200_SDK_PATH}/middleware/soc - - # netapps - - # oslib - # ${TI_CC3200_SDK_PATH}/oslib - # ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source - # ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source/portable/GCC/ARM_CM4 - # ${TI_CC3200_SDK_PATH}/third_party/FreeRTOS/source/portable/MemMang - - # simplelink - # ${TI_CC3200_SDK_PATH}/simplelink - # ${TI_CC3200_SDK_PATH}/simplelink/source - - # simplelink_extlib - # ${TI_CC3200_SDK_PATH}/simplelink_extlib/flc - # ${TI_CC3200_SDK_PATH}/simplelink_extlib/ota - # ${TI_CC3200_SDK_PATH}/simplelink_extlib/provisioninglib - - # ChibiOS - # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/src - # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/osal/rt - # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/rt/src - # # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx - # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/oslib/src - # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/abstractions/cmsis_os - # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC - # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC - # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx - ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/various - ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC - ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC - ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx - ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx - - ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200 - ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM - ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO - ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART - - CMAKE_FIND_ROOT_PATH_BOTH - ) - # message("${SRC_FILE} >> ${CC3200_SCR_FILE}") # debug helper - list(APPEND CHIBIOS_SOURCES ${CC3200_SCR_FILE}) -endforeach() From f603eb9b5fa66978a600f593f85932faad294ac7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Feb 2019 08:53:40 +0000 Subject: [PATCH 09/90] Work on Receiver and CLR threads MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Fix declaration and thread creation from main(). - Work WP HAL interface by pulling in the SL UART API. - Add WP monitor commands and app interface files. Signed-off-by: José Simões --- .../Include/WireProtocol_ReceiverThread.h | 2 +- .../TI_CC3220SF_LAUNCHXL/Board.h | 107 ++++++++++++ .../TI_CC3220SF_LAUNCHXL/nanoCLR/main.c | 72 +++++--- .../common/WireProtocol_HAL_Interface.c | 160 +++++++++--------- .../common/WireProtocol_ReceiverThread.c | 3 +- .../nanoCLR/CLR_Startup_Thread.c | 2 +- targets/TI-SimpleLink/nanoCLR/CMakeLists.txt | 6 +- .../nanoCLR/WireProtocol_App_Interface.c | 30 ++++ .../nanoCLR/WireProtocol_MonitorCommands.c | 7 + 9 files changed, 275 insertions(+), 114 deletions(-) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h create mode 100644 targets/TI-SimpleLink/nanoCLR/WireProtocol_App_Interface.c create mode 100644 targets/TI-SimpleLink/nanoCLR/WireProtocol_MonitorCommands.c diff --git a/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h b/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h index 5bae805e8c..2ab358a686 100644 --- a/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h +++ b/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h @@ -7,6 +7,6 @@ #define _WIREPROTOCOL_RECEIVERTHREAD_H_ // declaration of RTOS thread -void ReceiverThread(void const * argument); +void* ReceiverThread(void* argument); #endif //_WIREPROTOCOL_RECEIVERTHREAD_H_ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h new file mode 100644 index 0000000000..9f41650760 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOARD_H +#define __BOARD_H + +#define Board_CC3220SF_LAUNCHXL + +#ifdef __cplusplus +extern "C" { +#endif + +#include "CC3220SF_LAUNCHXL.h" + +#define Board_init CC3220SF_LAUNCHXL_initGeneral +#define Board_initGeneral CC3220SF_LAUNCHXL_initGeneral + +#define Board_ADC0 CC3220SF_LAUNCHXL_ADC0 +#define Board_ADC1 CC3220SF_LAUNCHXL_ADC1 + +#define Board_CAPTURE0 CC3220SF_LAUNCHXL_CAPTURE0 +#define Board_CAPTURE1 CC3220SF_LAUNCHXL_CAPTURE1 + +#define Board_CRYPTO0 CC3220SF_LAUNCHXL_CRYPTO0 + +#define Board_GPIO_LED_ON CC3220SF_LAUNCHXL_GPIO_LED_ON +#define Board_GPIO_LED_OFF CC3220SF_LAUNCHXL_GPIO_LED_OFF +#define Board_GPIO_LED0 CC3220SF_LAUNCHXL_GPIO_LED_D10 +/* + * CC3220SF_LAUNCHXL_GPIO_LED_D8 and CC3220SF_LAUNCHXL_GPIO_LED_D9 are shared with the I2C + * and PWM peripherals. In order for those examples to work, these LEDs are + * taken out of gpioPinCOnfig[] + */ +#define Board_GPIO_LED1 CC3220SF_LAUNCHXL_GPIO_LED_D10 +#define Board_GPIO_LED2 CC3220SF_LAUNCHXL_GPIO_LED_D10 + +#define Board_GPIO_BUTTON0 CC3220SF_LAUNCHXL_GPIO_SW2 +#define Board_GPIO_BUTTON1 CC3220SF_LAUNCHXL_GPIO_SW3 + +#define Board_GPIO_TMP116_EN CC3220SF_LAUNCHXL_GPIO_TMP116_EN + +#define Board_I2C0 CC3220SF_LAUNCHXL_I2C0 +#define Board_I2C_TMP CC3220SF_LAUNCHXL_I2C0 + +#define Board_I2S0 CC3220SF_LAUNCHXL_I2S0 + +#define Board_PWM0 CC3220SF_LAUNCHXL_PWM6 +#define Board_PWM1 CC3220SF_LAUNCHXL_PWM7 + +#define Board_SD0 CC3220SF_LAUNCHXL_SD0 + +#define Board_SDFatFS0 CC3220SF_LAUNCHXL_SD0 + +/* CC3220SF_LAUNCHXL_SPI0 is reserved for the NWP */ +#define Board_SPI0 CC3220SF_LAUNCHXL_SPI1 +#define Board_SPI_MASTER CC3220SF_LAUNCHXL_SPI1 +#define Board_SPI_SLAVE CC3220SF_LAUNCHXL_SPI1 +#define Board_SPI_MASTER_READY CC3220SF_LAUNCHXL_SPI_MASTER_READY +#define Board_SPI_SLAVE_READY CC3220SF_LAUNCHXL_SPI_SLAVE_READY + +#define Board_TIMER0 CC3220SF_LAUNCHXL_TIMER0 +#define Board_TIMER1 CC3220SF_LAUNCHXL_TIMER1 +#define Board_TIMER2 CC3220SF_LAUNCHXL_TIMER2 + +#define Board_UART0 CC3220SF_LAUNCHXL_UART0 +#define Board_UART1 CC3220SF_LAUNCHXL_UART1 + +#define Board_WATCHDOG0 CC3220SF_LAUNCHXL_WATCHDOG0 + +/* Board specific I2C address */ +#define Board_TMP006_ADDR (0x41) +#define Board_I2C_TMP006_ADDR Board_TMP006_ADDR + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H */ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c index a49ac9115d..c1c7915fd3 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c @@ -19,11 +19,8 @@ #include #include -extern void CLRStartupThread(void const * argument); - - -extern void * mainThread(void *arg0); - +extern void * CLRStartupThread(void *arg0); +extern void * ReceiverThread(void *arg0); ////////////////////////////// #define SL_STOP_TIMEOUT (200) @@ -43,40 +40,65 @@ int main(void) pthread_t thread; pthread_attr_t pAttrs; struct sched_param priParam; + + pthread_t receiverThread; + pthread_attr_t receiverThreadAttributes; + struct sched_param receiverThreadParams; + + pthread_t nanoCLRThread; + pthread_attr_t nanoCLRThreadAttributes; + struct sched_param nanoCLRThreadParams; + + int retc; - int detachState; /* Call board init functions */ Board_initGeneral(); - /* Set priority and stack size attributes */ - pthread_attr_init(&pAttrs); - priParam.sched_priority = 1; + GPIO_init(); + UART_init(); + SPI_init(); + I2C_init(); - detachState = PTHREAD_CREATE_DETACHED; - retc = pthread_attr_setdetachstate(&pAttrs, detachState); - if(retc != 0) - { - /* pthread_attr_setdetachstate() failed */ - while(1) - { - ; - } + // receiver thread + receiverThreadParams.sched_priority = 1; + retc = pthread_attr_setschedparam(&receiverThreadAttributes, &receiverThreadParams); + retc |= pthread_attr_setdetachstate(&receiverThreadAttributes, PTHREAD_CREATE_DETACHED); + retc |= pthread_attr_setstacksize(&receiverThreadAttributes, 2048); + if (retc != 0) { + /* failed to set attributes */ + while (1) {} } - pthread_attr_setschedparam(&pAttrs, &priParam); - - retc |= pthread_attr_setstacksize(&pAttrs, THREADSTACKSIZE); + retc = pthread_create(&thread, &receiverThreadAttributes, ReceiverThread, NULL); if(retc != 0) { - /* pthread_attr_setstacksize() failed */ + /* pthread_create() failed */ while(1) { ; } } - retc = pthread_create(&thread, &pAttrs, mainThread, NULL); + // CLR thread + nanoCLRThreadParams.sched_priority = 1; + retc = pthread_attr_setschedparam(&nanoCLRThreadAttributes, &nanoCLRThreadParams); + retc |= pthread_attr_setdetachstate(&nanoCLRThreadAttributes, PTHREAD_CREATE_DETACHED); + retc |= pthread_attr_setstacksize(&nanoCLRThreadAttributes, 15000); + if (retc != 0) { + /* failed to set attributes */ + while (1) {} + } + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = false; + + retc = pthread_create(&thread, &nanoCLRThreadAttributes, CLRStartupThread, &clrSettings); if(retc != 0) { /* pthread_create() failed */ @@ -311,10 +333,6 @@ void * mainThread(void *arg) struct sched_param priParam; struct timespec ts = {0}; - GPIO_init(); - SPI_init(); - I2C_init(); - /* init Terminal, and print App name */ //InitTerm(); diff --git a/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c b/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c index f7b487894e..828e9a5b5f 100644 --- a/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c +++ b/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c @@ -2,8 +2,10 @@ // Copyright (c) 2019 The nanoFramework project contributors // See LICENSE file in the project root for full license information. // -#include +#include +#include +#include #include #include #include @@ -22,120 +24,118 @@ bool WP_Initialise(COM_HANDLE port); // - serial port (UART/USART) // //////////////////////////////////////////////////////////////////////////////////////////////// -#if (HAL_USE_SERIAL == TRUE) - -static bool WP_Port_Intitialised = false; -// static uart_port_t WP_Port = UART_NUM_0; - -// #define ESP32_UART_RXD_PINS {3,32,16} -// #define ESP32_UART_TXD_PINS {1,33,17} -// #define ESP32_UART_CTS_PINS {19,6,8} -// #define ESP32_UART_RTS_PINS {22,11,7} - - -// // Pins -// static const char g_ESP32_Uart_RxD_Pins[] = ESP32_UART_RXD_PINS; -// static const char g_ESP32_Uart_TxD_Pins[] = ESP32_UART_TXD_PINS; +UART_Handle uart = NULL; +UART_Params uartParams; bool WP_Initialise(COM_HANDLE port) { (void)port; - // if ( WP_Port > UART_NUM_2 ) return false; - - // uart_config_t uart_config = { - // .baud_rate = 115200, //baudrate - // .data_bits = UART_DATA_8_BITS, //data bit mode - // .parity = UART_PARITY_DISABLE, //parity mode - // .stop_bits = UART_STOP_BITS_1, //stop bit mode - // .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, //hardware flow control(cts/rts) - // .rx_flow_ctrl_thresh = 120, //flow control threshold - // }; - - // uart_param_config(WP_Port, &uart_config); - - // uart_set_pin(WP_Port, g_ESP32_Uart_TxD_Pins[WP_Port], g_ESP32_Uart_RxD_Pins[WP_Port], UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); - - // // Setup UART driver(without UART queue) - // uart_driver_install(WP_Port, 1024 * 2, 512, 0, NULL, 0); - - WP_Port_Intitialised = true; + // Create a UART with data processing off + UART_Params_init(&uartParams); + uartParams.readTimeout = 500; + uartParams.writeDataMode = UART_DATA_BINARY; + uartParams.readDataMode = UART_DATA_BINARY; + uartParams.readReturnMode = UART_RETURN_FULL; + uartParams.readEcho = UART_ECHO_OFF; + uartParams.baudRate = 115200; + + uart = UART_open(Board_UART0, &uartParams); + + if (uart == NULL) + { + // UART_open() failed + while (1); + } return true; } - int WP_ReceiveBytes(uint8_t* ptr, uint16_t* size) { - // TODO: Initialise Port if not already done, Wire Protocol should be calling this directly at startup - //if (!WP_Port_Intitialised) WP_Initialise(WP_Port); + if(uart == NULL) + { + WP_Initialise(NULL); + } // save for latter comparison uint16_t requestedSize = *size; - // //int readData = 0; - // // sanity check for request of 0 size - // if(*size) - // { - // ////////////////////////////////////////////////////////// - // // PORTING CHANGE REQUIRED HERE // - // ////////////////////////////////////////////////////////// - // // change here to read (size) bytes from the input stream - // // preferably with read timeout and being able to check - // // if the requested number of bytes was actually read - // ////////////////////////////////////////////////////////// + //int readData = 0; + // sanity check for request of 0 size + if(*size) + { + ////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + ////////////////////////////////////////////////////////// + // change here to read (size) bytes from the input stream + // preferably with read timeout and being able to check + // if the requested number of bytes was actually read + ////////////////////////////////////////////////////////// - // // non blocking read from serial port with 100ms timeout - // volatile size_t read = uart_read_bytes( WP_Port, ptr, (uint32_t)requestedSize, (TickType_t) 100 / portTICK_PERIOD_MS); + // non blocking read from serial port with 100ms timeout + size_t read = UART_read(uart, ptr, requestedSize); - // ptr += read; - // *size -= read; + ptr += read; + *size -= read; - // // check if the requested read matches the actual read count - // return (requestedSize == read); - // } + // check if the requested read matches the actual read count + return (requestedSize == read); + } return true; } -#else -#error "Wire Protocol needs a transport." -#endif - -#if (HAL_USE_SERIAL == TRUE) - int WP_TransmitMessage(WP_Message* message) { + uint32_t writeResult; + bool operationResult = false; + + if(uart == NULL) + { + WP_Initialise(NULL); + } + /////////////////////////////////////////////////////////// // PORTING CHANGE REQUIRED HERE // /////////////////////////////////////////////////////////// // change here to write (size) bytes to the output stream // preferably with timeout and being able to check - // if the write was sucessfull or at least buffered + // if the write was successfull or at least buffered ////////////////////////////////////////////////////////// - //if (!WP_Port_Intitialised) WP_Initialise(WP_Port); + TRACE( TRACE_HEADERS, "TXMSG: 0x%08X, 0x%08X, 0x%08X\n", message->m_header.m_cmd, message->m_header.m_flags, message->m_header.m_size ); - //TODO Check if timeout required - // write header to output stream - - //if ( uart_write_bytes( WP_Port, (const char*)&message->m_header, sizeof(message->m_header) ) != sizeof(message->m_header)) return false; + // write header to uart + writeResult = UART_write(uart, (const void *)&message->m_header, sizeof(message->m_header)); - // if there is anything on the payload send it to the output stream - if(message->m_header.m_size && message->m_payload) + if(writeResult == sizeof(message->m_header)) { - /////////////////////////////////////////////////////////// - // PORTING CHANGE REQUIRED HERE // - /////////////////////////////////////////////////////////// - // see description above - ////////////////////////////////////////////////////////// - //if (uart_write_bytes(WP_Port, (const char*)message->m_payload, message->m_header.m_size ) != (int)message->m_header.m_size ) return false; + operationResult = true; + + // if there is anything on the payload send it to the output stream + if(message->m_header.m_size && message->m_payload) + { + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // see description above + ////////////////////////////////////////////////////////// + + // reset flag + operationResult = false; + + writeResult = UART_write(uart, (const void *)message->m_payload, message->m_header.m_size); + + if(writeResult == message->m_header.m_size) + { + operationResult = true; + + TRACE0( TRACE_ERRORS, "TXMSG: OK\n"); + } + } } - return true; + return operationResult; } - -#else -#error "Wire Protocol needs a transport." -#endif diff --git a/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c b/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c index f3413e7d71..c2901fe8c8 100644 --- a/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c +++ b/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c @@ -12,14 +12,13 @@ void WP_Message_Initialize(WP_Message* a); void WP_Message_PrepareReception(WP_Message* a); void WP_Message_Process(WP_Message* a); -void ReceiverThread(void const * argument) +void* ReceiverThread(void* argument) { (void)argument; // loop forever while (1) { - WP_Message_Initialize(&inboundMessage); WP_Message_PrepareReception(&inboundMessage); diff --git a/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c b/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c index 7dd1dd19d6..fa09cebf7d 100644 --- a/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c +++ b/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c @@ -7,7 +7,7 @@ #include #include -void CLRStartupThread(void const * argument) +void* CLRStartupThread(void* argument) { CLR_SETTINGS* clrSettings = (CLR_SETTINGS*)argument; diff --git a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt index e4502a2dde..cf27bb7390 100644 --- a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt +++ b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt @@ -12,9 +12,9 @@ configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in" # append nanoHAL list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp") -# append target ChibiOS nanoCLR source files -# list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_App_Interface.c) -# list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c) +# append target nanoCLR source files +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_App_Interface.c) +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c) list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CLR_Startup_Thread.c") list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c") diff --git a/targets/TI-SimpleLink/nanoCLR/WireProtocol_App_Interface.c b/targets/TI-SimpleLink/nanoCLR/WireProtocol_App_Interface.c new file mode 100644 index 0000000000..21259693d8 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/WireProtocol_App_Interface.c @@ -0,0 +1,30 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +// declaration for wrapper function +extern int CLR_Messaging_ProcessPayload(WP_Message* msg); + +//////////////////////////////////////////////////// + +int WP_App_ProcessHeader(WP_Message* message) +{ + // check for reception buffer overflow + if(message->m_header.m_size > sizeof(receptionBuffer)) + { + return false; + } + + message->m_payload = receptionBuffer; + return true; +} + +int WP_App_ProcessPayload(WP_Message* message) +{ + return CLR_Messaging_ProcessPayload(message); +} diff --git a/targets/TI-SimpleLink/nanoCLR/WireProtocol_MonitorCommands.c b/targets/TI-SimpleLink/nanoCLR/WireProtocol_MonitorCommands.c new file mode 100644 index 0000000000..74e05b66ff --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/WireProtocol_MonitorCommands.c @@ -0,0 +1,7 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// file empty on purpose +// in nanoCLR the MonitorCommands are implemented in Debugger From 682f5c2206e9e12b90e9c71c00ad483f424e70da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Feb 2019 13:14:53 +0000 Subject: [PATCH 10/90] Remove target CLR startup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp | 354 ------------------- targets/TI-SimpleLink/nanoCLR/CMakeLists.txt | 1 - 2 files changed, 355 deletions(-) delete mode 100644 targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp diff --git a/targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp b/targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp deleted file mode 100644 index d57bb57f0a..0000000000 --- a/targets/TI-SimpleLink/nanoCLR/CLRStartup.cpp +++ /dev/null @@ -1,354 +0,0 @@ -// -// Copyright (c) 2019 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include -#include -#include -#include -#include - -struct Settings -{ - CLR_SETTINGS m_clrOptions; - bool m_fInitialized; - - //--// - - HRESULT Initialize(CLR_SETTINGS params) - { - NANOCLR_HEADER(); - - m_clrOptions = params; - - NANOCLR_CHECK_HRESULT(CLR_RT_ExecutionEngine::CreateInstance()); -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "Created EE.\r\n" ); -#endif - -#if !defined(BUILD_RTM) - if(params.WaitForDebugger) - { - CLR_EE_DBG_SET( Stopped ); - } -#endif - - NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.StartHardware()); -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "Started Hardware.\r\n" ); -#endif - - m_fInitialized = true; - - NANOCLR_NOCLEANUP(); - } - - - HRESULT LoadAssembly( const CLR_RECORD_ASSEMBLY* header, CLR_RT_Assembly*& assm ) - { - NANOCLR_HEADER(); - - const CLR_RT_NativeAssemblyData *pNativeAssmData; - - NANOCLR_CHECK_HRESULT(CLR_RT_Assembly::CreateInstance( header, assm )); - - // Get handlers for native functions in assembly - pNativeAssmData = GetAssemblyNativeData( assm->m_szName ); - - // If pNativeAssmData not NULL- means this assembly has native calls and there is pointer to table with native calls. - if ( pNativeAssmData != NULL ) - { - // First verify that check sum in assembly object matches hardcoded check sum. - if ( assm->m_header->nativeMethodsChecksum != pNativeAssmData->m_checkSum ) - { - CLR_Debug::Printf("***********************************************************************\r\n"); - CLR_Debug::Printf("* *\r\n"); - CLR_Debug::Printf("* ERROR!!!! Firmware version does not match managed code version!!!! *\r\n"); - CLR_Debug::Printf("* *\r\n"); - CLR_Debug::Printf("* *\r\n"); - CLR_Debug::Printf("* Invalid native checksum: %s 0x%08X!=0x%08X *\r\n", - assm->m_szName, - assm->m_header->nativeMethodsChecksum, - pNativeAssmData->m_checkSum - ); - CLR_Debug::Printf("* *\r\n"); - CLR_Debug::Printf("***********************************************************************\r\n"); - - NANOCLR_SET_AND_LEAVE(CLR_E_ASSM_WRONG_CHECKSUM); - } - - // Assembly has valid pointer to table with native methods. Save it. - assm->m_nativeCode = (const CLR_RT_MethodHandler *)pNativeAssmData->m_pNativeMethods; - } - g_CLR_RT_TypeSystem.Link( assm ); - NANOCLR_NOCLEANUP(); - } - - - HRESULT Load() - { - NANOCLR_HEADER(); - -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "Create TS.\r\n" ); -#endif - //NANOCLR_CHECK_HRESULT(LoadKnownAssemblies( (char*)&__deployment_start__, (char*)&__deployment_end__ )); - -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "Loading Deployment Assemblies.\r\n" ); -#endif - - LoadDeploymentAssemblies(); - - //--// - -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "Resolving.\r\n" ); -#endif - NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.ResolveAll()); - - NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.PrepareForExecution()); - -#if defined(NANOCLR_PROFILE_HANDLER) - CLR_PROF_Handler::Calibrate(); -#endif - - NANOCLR_CLEANUP(); - -#if !defined(BUILD_RTM) - if(FAILED(hr)) CLR_Debug::Printf( "Error: %08x\r\n", hr ); -#endif - - NANOCLR_CLEANUP_END(); - } - - HRESULT LoadKnownAssemblies( char* start, char* end ) - { - //--// - NANOCLR_HEADER(); - char *assStart = start; - char *assEnd = end; - const CLR_RECORD_ASSEMBLY* header; - -#if !defined(BUILD_RTM) - CLR_Debug::Printf(" Loading start at %x, end %x\r\n", (unsigned int)assStart, (unsigned int)assEnd); -#endif - - g_buildCRC = SUPPORT_ComputeCRC( assStart, (unsigned int)assEnd -(unsigned int) assStart, 0 ); - - - header = (const CLR_RECORD_ASSEMBLY*)assStart; - - while((char*)header + sizeof(CLR_RECORD_ASSEMBLY) < assEnd && header->GoodAssembly()) - { - CLR_RT_Assembly* assm; - - // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem - NANOCLR_CHECK_HRESULT(LoadAssembly( header, assm )); - - header = (const CLR_RECORD_ASSEMBLY*)ROUNDTOMULTIPLE((size_t)header + header->TotalSize(), CLR_UINT32); - } - - NANOCLR_NOCLEANUP(); - } - - - HRESULT ContiguousBlockAssemblies(BlockStorageStream stream) - { - NANOCLR_HEADER(); - - const CLR_RECORD_ASSEMBLY* header; - unsigned char * assembliesBuffer ; - unsigned int headerInBytes = sizeof(CLR_RECORD_ASSEMBLY); - unsigned char * headerBuffer = NULL; - - while(stream.CurrentIndex < stream.Length) - { - // check if there is enough stream length to continue - if((stream.Length - stream.CurrentIndex ) < headerInBytes) - { - // not enough stream to read, leave now - break; - } - - if(!BlockStorageStream_Read(&stream, &headerBuffer, headerInBytes )) break; - - header = (const CLR_RECORD_ASSEMBLY*)headerBuffer; - - // check header first before read - if(!header->GoodHeader()) - { - // check failed, try to continue to the next - continue; - } - - unsigned int assemblySizeInByte = ROUNDTOMULTIPLE(header->TotalSize(), CLR_UINT32); - - // advance stream beyond header - BlockStorageStream_Seek(&stream, -headerInBytes, BlockStorageStream_SeekCurrent); - - // read the assembly - if(!BlockStorageStream_Read(&stream, &assembliesBuffer, assemblySizeInByte)) break; - - header = (const CLR_RECORD_ASSEMBLY*)assembliesBuffer; - - if(!header->GoodAssembly()) - { - // check failed, try to continue to the next - continue; - } - - // we have good Assembly - CLR_RT_Assembly* assm; - - CLR_Debug::Printf( "Attaching deployed file.\r\n" ); - - // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem - if (FAILED(LoadAssembly(header, assm))) - { - // load failed, try to continue to the next - continue; - } - - // load successfull, mark as deployed - assm->m_flags |= CLR_RT_Assembly::Deployed; - } - - NANOCLR_NOCLEANUP_NOLABEL(); - } - - HRESULT LoadDeploymentAssemblies() - { - NANOCLR_HEADER(); - - // perform initialization of BlockStorageStream structure - BlockStorageStream stream; - - // init the stream for deployment storage - if (!BlockStorageStream_Initialize(&stream, StorageUsage_DEPLOYMENT)) - { -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "ERROR: failed to initialize DEPLOYMENT storage\r\n" ); -#endif - NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); - } - - ContiguousBlockAssemblies(stream); - - NANOCLR_NOCLEANUP(); - } - - void Cleanup() - { - CLR_RT_ExecutionEngine::DeleteInstance(); - - memset( &g_CLR_RT_ExecutionEngine, 0, sizeof(g_CLR_RT_ExecutionEngine)); - memset( &g_CLR_RT_WellKnownTypes, 0, sizeof(g_CLR_RT_WellKnownTypes)); - memset( &g_CLR_RT_WellKnownMethods, 0, sizeof(g_CLR_RT_WellKnownMethods)); - memset( &g_CLR_RT_TypeSystem, 0, sizeof(g_CLR_RT_TypeSystem)); - memset( &g_CLR_RT_EventCache, 0, sizeof(g_CLR_RT_EventCache)); - memset( &g_CLR_RT_GarbageCollector, 0, sizeof(g_CLR_RT_GarbageCollector)); - memset( &g_CLR_HW_Hardware, 0, sizeof(g_CLR_HW_Hardware)); - - m_fInitialized = false; - } - - Settings() - { - m_fInitialized = false; - } - -}; - - -static Settings s_ClrSettings; - -void ClrStartup(CLR_SETTINGS params) -{ - NATIVE_PROFILE_CLR_STARTUP(); - Settings settings; - ASSERT(sizeof(CLR_RT_HeapBlock_Raw) == sizeof(CLR_RT_HeapBlock)); - bool softReboot; - - do - { - softReboot = false; - - CLR_RT_Assembly::InitString(); - -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "\r\nnanoCLR (Build %d.%d.%d.%d)\r\n\r\n", VERSION_MAJOR, VERSION_MINOR, VERSION_BUILD, VERSION_REVISION ); -#endif - - CLR_RT_Memory::Reset(); - -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "Starting...\r\n" ); -#endif - - - HRESULT hr; - - if(SUCCEEDED(hr = s_ClrSettings.Initialize(params))) - { - if(SUCCEEDED(hr = s_ClrSettings.Load())) - { -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "Ready.\r\n" ); -#endif - - (void)g_CLR_RT_ExecutionEngine.Execute( NULL, params.MaxContextSwitches ); - -#if !defined(BUILD_RTM) - CLR_Debug::Printf( "Done.\r\n" ); -#endif - } - } - - // process setting of power mode, if reboot was requested along with a power mode "higher" then PowerLevel__Active - if(CLR_EE_REBOOT_IS( ClrOnly ) && g_CLR_HW_Hardware.m_powerLevel > PowerLevel__Active) - { - CPU_SetPowerMode(g_CLR_HW_Hardware.m_powerLevel); - } - - if( CLR_EE_DBG_IS_NOT( RebootPending )) - { -#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) - CLR_EE_DBG_SET_MASK(StateProgramExited, StateMask); - CLR_EE_DBG_EVENT_BROADCAST(CLR_DBG_Commands::c_Monitor_ProgramExit, 0, NULL, WP_Flags_c_NonCritical); -#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) - - if(params.EnterDebuggerLoopAfterExit) - { - CLR_DBG_Debugger::Debugger_WaitForCommands(); - } - } - - // DO NOT USE 'ELSE IF' here because the state can change in Debugger_WaitForCommands() call - - if( CLR_EE_DBG_IS( RebootPending )) - { - if(CLR_EE_REBOOT_IS( ClrOnly )) - { - softReboot = true; - - params.WaitForDebugger = CLR_EE_REBOOT_IS(WaitForDebugger); - - s_ClrSettings.Cleanup(); - - nanoHAL_Uninitialize(); - - //re-init the hal for the reboot (initially it is called in bootentry) - nanoHAL_Initialize(); - } - else - { - CPU_Reset(); - } - } - - } while( softReboot ); - -} diff --git a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt index cf27bb7390..ab0656fbe6 100644 --- a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt +++ b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt @@ -32,7 +32,6 @@ list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/ta list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Time.cpp") # append other CLR core files -list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CLRStartup.cpp") list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Memory.cpp") # append nanoCRT From 3cbd591e030953089f9d5b9b0fd84be17fb23365 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Feb 2019 20:36:27 +0000 Subject: [PATCH 11/90] Add dummy blockstorage definition --- .../common/Device_BlockStorage-DEBUG.c | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index c181527942..6f6372d562 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -8,18 +8,30 @@ const BlockRange BlockRange1[] = { - { BlockRange_BLOCKTYPE_DEPLOYMENT , 1, 1 }, // 08008000 configuration block + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x01000800 nanoCLR +}; + +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT , 0, 0 }, // 0x08000000 nanoCLR }; const BlockRegionInfo BlockRegions[] = { { - 0x08000000, // start address for block region - 4, // total number of blocks in this region - 0x8000, // total number of bytes per block + 0x01000800, // start address for block region + 1, // total number of blocks in this region + 0x0FF800, // total number of bytes per block ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, }, + { + 0x08000000, // start address for block region + 1, // total number of blocks in this region + 0x0FF800, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange2, + }, }; const DeviceBlockInfo Device_BlockInfo = From 8ae582d93f1cdd362742fa82e4ad5c5c15072364 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Feb 2019 20:36:42 +0000 Subject: [PATCH 12/90] Add dummy flash driver --- .../Target_BlockStorage_CC32xxFlashDriver.h | 28 ++++++++ targets/TI-SimpleLink/common/CMakeLists.txt | 2 +- .../common/Target_BlockStorage.c | 29 ++++---- .../Target_BlockStorage_CC32xxFlashDriver.c | 68 +++++++++++++++++++ 4 files changed, 111 insertions(+), 16 deletions(-) create mode 100644 targets/TI-SimpleLink/Include/Target_BlockStorage_CC32xxFlashDriver.h create mode 100644 targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c diff --git a/targets/TI-SimpleLink/Include/Target_BlockStorage_CC32xxFlashDriver.h b/targets/TI-SimpleLink/Include/Target_BlockStorage_CC32xxFlashDriver.h new file mode 100644 index 0000000000..7097fd80ea --- /dev/null +++ b/targets/TI-SimpleLink/Include/Target_BlockStorage_CC32xxFlashDriver.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_CC32XXFLASH_DRIVER_H_ +#define _TARGET_CC32XXFLASH_DRIVER_H_ 1 + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +bool CC32xxFlashDriver_InitializeDevice(void*); +bool CC32xxFlashDriver_UninitializeDevice(void*); +DeviceBlockInfo* CC32xxFlashDriver_GetDeviceInfo(void*); +bool CC32xxFlashDriver_Read(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer); +bool CC32xxFlashDriver_Write(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite); +bool CC32xxFlashDriver_IsBlockErased(void*, ByteAddress blockAddress, unsigned int length); +bool CC32xxFlashDriver_EraseBlock(void*, ByteAddress address); +void CC32xxFlashDriver_SetPowerState(void*, unsigned int state); + +#ifdef __cplusplus +} +#endif + +#endif //_TARGET_CC32XXFLASH_DRIVER_H_ diff --git a/targets/TI-SimpleLink/common/CMakeLists.txt b/targets/TI-SimpleLink/common/CMakeLists.txt index 08ee98f0cb..e9221eec40 100644 --- a/targets/TI-SimpleLink/common/CMakeLists.txt +++ b/targets/TI-SimpleLink/common/CMakeLists.txt @@ -9,7 +9,7 @@ list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/pla list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_ReceiverThread.c") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c") -# list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_ESP32FlashDriver.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_CC32xxFlashDriver.c") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage.c") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/FreeRTOS-openocd.c") diff --git a/targets/TI-SimpleLink/common/Target_BlockStorage.c b/targets/TI-SimpleLink/common/Target_BlockStorage.c index 19b3af659d..79a1f7fcb1 100644 --- a/targets/TI-SimpleLink/common/Target_BlockStorage.c +++ b/targets/TI-SimpleLink/common/Target_BlockStorage.c @@ -5,7 +5,7 @@ #include #include -// #include +#include /////////////////////////////////////////////////// // BlockStream @@ -33,7 +33,7 @@ bool BlockStorageStream_Initialize(BlockStorageStream* stream, unsigned int bloc { // set BaseAddress to the start of the region // FIXME TODO - //stream->BaseAddress = (unsigned int)g_esp32_flash_start_ptr; + //stream->BaseAddress = (unsigned int)g_CC32xx_flash_start_ptr; // set Length to the region size // need to cast the pointers to make sure the compiler implements the correct math // FIXME TODO @@ -51,24 +51,23 @@ extern struct BlockStorageDevice Device_BlockStorage; extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; BlockStorageList BlockStorage; -// map here the Block Storage Interface to the ESP32 driver -IBlockStorageDevice ESP32Flash_BlockStorageInterface = +// map here the Block Storage Interface to the CC32xx driver +IBlockStorageDevice CC32xxFlash_BlockStorageInterface = { - // FIXME TODO - // &Esp32FlashDriver_InitializeDevice, - // &Esp32FlashDriver_UninitializeDevice, - // &Esp32FlashDriver_GetDeviceInfo, - // &Esp32FlashDriver_Read, - // &Esp32FlashDriver_Write, - // NULL, - // &Esp32FlashDriver_IsBlockErased, - // &Esp32FlashDriver_EraseBlock, - // &Esp32FlashDriver_SetPowerState + &CC32xxFlashDriver_InitializeDevice, + &CC32xxFlashDriver_UninitializeDevice, + &CC32xxFlashDriver_GetDeviceInfo, + &CC32xxFlashDriver_Read, + &CC32xxFlashDriver_Write, + NULL, + &CC32xxFlashDriver_IsBlockErased, + &CC32xxFlashDriver_EraseBlock, + &CC32xxFlashDriver_SetPowerState }; void BlockStorage_AddDevices() { - BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &ESP32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &CC32xxFlash_BlockStorageInterface, &Device_BlockStorageConfig, false); } bool BlockStorageList_FindDeviceForPhysicalAddress(BlockStorageDevice** pBSD, unsigned int physicalAddress, ByteAddress* blockAddress) diff --git a/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c b/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c new file mode 100644 index 0000000000..3ff331ce8a --- /dev/null +++ b/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c @@ -0,0 +1,68 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool CC32xxFlashDriver_InitializeDevice(void* context) +{ + (void)context; + + // SimpleLink driver takes care of this, so always true + return true; +} + +bool CC32xxFlashDriver_UninitializeDevice(void* context) +{ + (void)context; + + // SimpleLink driver takes care of this, so always true + return true; +} + +DeviceBlockInfo* CC32xxFlashDriver_GetDeviceInfo(void* context) +{ + (void)context; + + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = context; + + return config->BlockConfig.BlockDeviceInformation; +} + +bool CC32xxFlashDriver_Read(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer) +{ + (void)context; + + // ... and always return true + return true; +} + +bool CC32xxFlashDriver_Write(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite) +{ + (void)context; + + return true; +} + +bool CC32xxFlashDriver_IsBlockErased(void* context, ByteAddress blockAddress, unsigned int length) +{ + (void)context; + + return true; +} + +bool CC32xxFlashDriver_EraseBlock(void* context, ByteAddress address) +{ + (void)context; + + return true; +} + +void CC32xxFlashDriver_SetPowerState(void* context, unsigned int state) +{ + (void)context; + (void)state; + + // nothing to be done here +} From 25c810b780bac58c17e87d1fc3ab08142dd50931 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Feb 2019 20:37:26 +0000 Subject: [PATCH 13/90] Add values to flash addresses --- targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c index cc302074d9..300b375b1c 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c @@ -23,6 +23,6 @@ HAL_SYSTEM_CONFIG HalSystemConfig = HAL_TARGET_CONFIGURATION g_TargetConfiguration; -// FIXME TODO -uint32_t __nanoImage_start__ = 0; -uint32_t __nanoImage_end__ = 0; +// these addresses are the start and end address of flash region FLASH +uint32_t __nanoImage_start__ = FLASH1_MEMORY_StartAddress; +uint32_t __nanoImage_end__ = (FLASH1_MEMORY_StartAddress + FLASH1_MEMORY_Size); From cf50a556177fc9d41af2c9e0887bb2d3713eb458 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 11 Feb 2019 16:07:06 +0000 Subject: [PATCH 14/90] Add SimpleLink source files by task --- .../targetSimpleLinkCC32xx_LinkLocalTask.h | 239 ++ .../targetSimpleLinkCC32xx_ProvisioningTask.h | 145 + .../Include/targetSimpleLinkCC32xx_Threads.h | 105 + .../nanoCLR/CMakeLists.txt | 1 + .../TI_CC3220SF_LAUNCHXL/nanoCLR/main.c | 365 +-- targets/TI-SimpleLink/nanoCLR/CMakeLists.txt | 7 + .../targetSimpleLinkCC32xx_LinkLocalTask.c | 2838 +++++++++++++++++ .../targetSimpleLinkCC32xx_ProvisioningTask.c | 1546 +++++++++ .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 1178 +++++++ 9 files changed, 6075 insertions(+), 349 deletions(-) create mode 100644 targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_LinkLocalTask.h create mode 100644 targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_ProvisioningTask.h create mode 100644 targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h create mode 100644 targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c create mode 100644 targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c create mode 100644 targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c diff --git a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_LinkLocalTask.h b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_LinkLocalTask.h new file mode 100644 index 0000000000..f799a3b16c --- /dev/null +++ b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_LinkLocalTask.h @@ -0,0 +1,239 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SIMPLELINK_CC32XX_LINKLOCAL_TASK_H_ +#define _SIMPLELINK_CC32XX_LINKLOCAL_TASK_H_ + +/* TI-DRIVERS Header files */ +#include + +/* POSIX Header files */ +#include +#include + +#define OOB_IS_NETAPP_MORE_DATA(flags) ((flags & \ + SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) \ + == \ + SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) +#define OOB_IS_NETAPP_ERROR(flags) ((flags & \ + SL_NETAPP_REQUEST_RESPONSE_FLAGS_ERROR) \ + == \ + SL_NETAPP_REQUEST_RESPONSE_FLAGS_ERROR) + +/* header fields definitions */ +#define WEB_SERVER_VERSION "HTTP Version:" +#define WEB_SERVER_REQUEST_URI "Request URI:" +#define WEB_SERVER_QUERY_STRING "Query String:" +#define WEB_SERVER_HEADER_CONTENT_TYPE "Content-Type: " +#define WEB_SERVER_HEADER_CONTENT_LEN "Content-Length: " +#define WEB_SERVER_HEADER_LOCATION "Location: " +#define WEB_SERVER_HEADER_SERVER "Server: " +#define WEB_SERVER_HEADER_USER_AGENT "User-Agent: " +#define WEB_SERVER_HEADER_COOKIE "Cookie:" +#define WEB_SERVER_HEADER_SET_COOKIE "Set-Cookie: " +#define WEB_SERVER_HEADER_UPGRADE "Upgrade: " +#define WEB_SERVER_HEADER_REFERER "Referer: " +#define WEB_SERVER_HEADER_ACCEPT "Accept: " +#define WEB_SERVER_HEADER_CONTENT_ENCODING "Content-Encoding: " +#define WEB_SERVER_HEADER_CONTENT_DISPOSITION "Content-Disposition: " +#define WEB_SERVER_HEADER_CONNECTION "Connection: " +#define WEB_SERVER_HEADER_ETAG "Etag: " +#define WEB_SERVER_HEADER_DATE "Date: " +#define WEB_SERVER_HEADER_HOST "Host: " +#define WEB_SERVER_HEADER_ACCEPT_ENCODING "Accept-Encoding: " +#define WEB_SERVER_HEADER_ACCEPT_LANGUAGE "Accept-Language: " +#define WEB_SERVER_HEADER_CONTENT_LANGUAGE "Content-Language: " + +/* Content types list */ +#define TEXT_HTML "text/html" +#define TEXT_CSS "text/css" +#define TEXT_XML "text/xml" +#define APPLICATION_JSON "application/json" +#define IMAGE_PNG "image/png" +#define IMAGE_GIF "image/gif" +#define TEXT_PLAIN "text/plain" +#define TEXT_CSV "text/csv" +#define APPLICATION_JAVASCRIPT "application/javascript" +#define IMAGE_JPEG "image/jpeg" +#define APPLICATION_PDF "application/pdf" +#define APPLICATION_ZIP "application/zip" +#define SHOCKWAVE_FLASH "application/x-shockwave-flash" +#define AUDIO_X_AAC "audio/x-aac" +#define IMAGE_X_ICON "image/x-icon" +#define TEXT_VCARD "text/vcard" +#define APPLICATION_OCTEC_STREAM "application/octet-stream" +#define VIDEO_AVI "video/avi" +#define VIDEO_MPEG "video/mpeg" +#define VIDEO_MP4 "video/mp4" +#define FORM_URLENCODED "application/x-www-form-urlencoded" + +/* MIME types list */ +#define TEXT_HTML_MIME ".html" +#define TEXT_CSS_MIME ".css" +#define TEXT_XML_MIME ".xml" +#define APPLICATION_JSON_MIME ".json" +#define IMAGE_PNG_MIME ".png" +#define IMAGE_GIF_MIME ".gif" +#define TEXT_PLAIN_MIME ".txt" +#define TEXT_CSV_MIME ".csv" +#define APPLICATION_JAVASCRIPT_MIME ".js" +#define IMAGE_JPEG_MIME ".jpg" +#define APPLICATION_PDF_MIME ".pdf" +#define APPLICATION_ZIP_MIME ".zip" +#define SHOCKWAVE_FLASH_MIME ".swf" +#define AUDIO_X_AAC_MIME ".aac" +#define IMAGE_X_ICON_MIME ".ico" +#define TEXT_VCARD_MIME ".vcf" +#define APPLICATION_OCTEC_STREAM_MIME ".bin" +#define VIDEO_AVI_MIME ".avi" +#define VIDEO_MPEG_MIME ".mpeg" +#define VIDEO_MP4_MIME ".mp4" +/* dummy - no such extension */ + +#define URL_ENCODED_MIME ".form" +typedef enum +{ +/* Content types list */ + HttpContentTypeList_TextHtml, + HttpContentTypeList_TextCSS, + HttpContentTypeList_TextXML, + HttpContentTypeList_ApplicationJson, + HttpContentTypeList_ImagePNG, + HttpContentTypeList_ImageGIF, + HttpContentTypeList_TextPlain, + HttpContentTypeList_TextCSV, + HttpContentTypeList_ApplicationJavascript, + HttpContentTypeList_ImageJPEG, + HttpContentTypeList_ApplicationPDF, + HttpContentTypeList_ApplicationZIP, + HttpContentTypeList_ShokewaveFlash, + HttpContentTypeList_AudioXAAC, + HttpContentTypeList_ImageXIcon, + HttpContentTypeList_TextVcard, + HttpContentTypeList_ApplicationOctecStream, + HttpContentTypeList_VideoAVI, + HttpContentTypeList_VideoMPEG, + HttpContentTypeList_VideoMP4, + HttpContentTypeList_UrlEncoded, +}HttpContentTypeList; + +#define CONTENT_LEN_TYPE 0xFF + +/* offsets of TLV structure of parameters parsed in NetApp request */ +#define ARGV_TYPE_OFFSET 0 +#define ARGV_LEN_OFFSET 2 +#define ARGV_VALUE_OFFSET 3 + +typedef struct _http_headerFieldType_t_ +{ + SlNetAppMetadataHTTPTypes_e headerType; + char * headerText; +}http_headerFieldType_t; + +typedef struct _http_contentTypeMapping_t_ +{ + HttpContentTypeList contentType; + char *contentTypeText; + char *mimeExt; +}http_contentTypeMapping_t; + +typedef struct _http_charValuesPair_t_ +{ + char *characteristic; + char *value[5]; +}http_charValuesPair_t; + +typedef struct _http_RequestObj_t_ +{ + uint8_t requestIdx; + uint8_t httpMethod; + char *service; + http_charValuesPair_t charValues[10]; + int32_t (*serviceCallback)(uint8_t, + uint8_t *, + uint8_t **, + SlNetAppRequest_t *); +}http_RequestObj_t; + +typedef enum +{ + LedIdx_RedLed, + LedIdx_OrangeLed, + LedIdx_GreenLed, + LedIdx_MaxLed, +}LedIdx; + +typedef enum +{ + LedValues_Off, + LedValues_On, + LedValues_Toggle, + LedValues_MaxLed, +}LedValues; + +typedef enum +{ + SensorIdx_XAxis, + SensorIdx_YAxis, + SensorIdx_ZAxis, + SensorIdx_FarnTemp, + SensorIdx_MaxSensor, +}SensorIdx; + +typedef enum +{ + DeviceIdx_Ssid, + DeviceIdx_IpAddress, + DeviceIdx_MacAddress, + DeviceIdx_AppID, + DeviceIdx_MaxDevice, +}DeviceIdx; + +typedef enum +{ + OtaIdx_Version, + OtaIdx_MaxOTA, +}OtaIdx; + +typedef struct LinkLocal_ControlBlock_t +{ + sem_t otaReportServerStartSignal; + sem_t otaReportServerStopSignal; + mqd_t reportServerMQueue; +}LinkLocal_CB; + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ +extern LinkLocal_CB LinkLocal_ControlBlock; + +//**************************************************************************** +// FUNCTION PROTOTYPES +//**************************************************************************** + +//***************************************************************************** +// +//! \brief This function fetches the device type and prints it +//! +//! \param[in] None +//! +//! \return device type +//! +//**************************************************************************** +uint32_t getDeviceType(); + +//***************************************************************************** +// +//! \brief This task handles LinkLocal transactions with the client +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void * linkLocalTask(void *pvParameters); + +#endif //_SIMPLELINK_CC32XX_LINKLOCAL_TASK_H_ diff --git a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_ProvisioningTask.h b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_ProvisioningTask.h new file mode 100644 index 0000000000..3b13f6ee8f --- /dev/null +++ b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_ProvisioningTask.h @@ -0,0 +1,145 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SIMPLELINK_CC32XX_PROVISIONING_TASK_H_ +#define _SIMPLELINK_CC32XX_PROVISIONING_TASK_H_ + +#include + +/* POSIX Header files */ +#include +#include +#include + +#include +// #include +// #include + +/*! + * \brief Provisioning events + */ +typedef enum +{ + PrvnEvent_Triggered, + PrvnEvent_Started, + PrvnEvent_StartFailed, + PrvnEvent_ConfirmationSuccess, + PrvnEvent_ConfirmationFailed, + PrvnEvent_Stopped, + PrvnEvent_WaitForConn, + PrvnEvent_Timeout, + PrvnEvent_Error, + PrvnEvent_Max, +}PrvnEvent; + +/*! + * \brief Provisioning states + */ +typedef enum +{ + PrvnState_Init, + PrvnState_Idle, + PrvnState_WaitForConfirmation, + PrvnState_Completed, + PrvnState_Error, + PrvnState_Max +}PrvnState; + +typedef struct Provisioning_ControlBlock_t +{ + sem_t connectionAsyncEvent; + sem_t provisioningDoneSignal; + sem_t provisioningConnDoneToOtaServerSignal; +}Provisioning_CB; + + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ +extern Provisioning_CB Provisioning_ControlBlock; + +//**************************************************************************** +// FUNCTION PROTOTYPES +//**************************************************************************** + +//***************************************************************************** +// +//! \brief This function signals the application events +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +_i16 SignalProvisioningEvent(PrvnEvent event); + +//***************************************************************************** +// +//! \brief This function gets the current provisioning state +//! +//! \param[in] None +//! +//! \return provisioning state +//! +//**************************************************************************** +PrvnState GetProvisioningState(); + +//***************************************************************************** +// +//! \brief The interrupt handler for the LED timer +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void LedTimerIntHandler(sigval val); + +//***************************************************************************** +// +//! \brief This function starts the led toggling timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t StartLedEvtTimer(uint32_t timeout); + +//***************************************************************************** +// +//! \brief This function stops the led toggling timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t StopLedEvtTimer(void); + +//***************************************************************************** +// +//! \brief This function stops provisioning process +//! +//! \param[in] None +//! +//! \return SL_RET_CODE_PROVISIONING_IN_PROGRESS if provisioning was running, otherwise 0 +//! +//**************************************************************************** +int32_t provisioningStop(void); + +//***************************************************************************** +// +//! \brief This is the main provisioning task +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void * provisioningTask(void *pvParameters); + +#endif //_SIMPLELINK_CC32XX_PROVISIONING_TASK_H_ diff --git a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h new file mode 100644 index 0000000000..a7fc8466bc --- /dev/null +++ b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h @@ -0,0 +1,105 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SIMPLELINK_CC32XX_THREADS_H_ +#define _SIMPLELINK_CC32XX_THREADS_H_ + +#include + +/* POSIX Header files */ +#include +#include +#include + +#include +// #include +// #include + + +#define SL_STOP_TIMEOUT (200) + +#define UART_PRINT Report +#define DBG_PRINT Report +// #define ERR_PRINT(x) Report("Error [%d] at line [%d] in function [%s] \n\r",\ +// x, __LINE__, \ +// __FUNCTION__) +#define ERR_PRINT(x) + +/* check the error code and handle it */ +#define ASSERT_ON_ERROR(error_code) \ + { \ + if(error_code < 0) \ + { \ + ERR_PRINT(error_code); \ + return error_code; \ + } \ + } + +#define SET_STATUS_BIT(status_variable, bit) status_variable |= (1 << (bit)) + +#define CLR_STATUS_BIT(status_variable, bit) status_variable &= ~(1 << (bit)) + +#define GET_STATUS_BIT(status_variable, bit) \ + (0 != (status_variable & (1 << (bit)))) + +#define APPS_WDT_START_KEY 0xAE42DB15 +#define HWREG(x) (*((volatile unsigned long *)(x))) + +typedef enum +{ + /* If this bit is set: Network Processor is powered up */ + AppStatusBits_NwpInit = 0, + /* If this bit is set: the device is connected to + the AP or client is connected to device (AP) */ + AppStatusBits_Connection = 1, + /* If this bit is set: the device has leased IP to + any connected client */ + AppStatusBits_IpLeased = 2, + /* If this bit is set: the device has acquired an IP */ + AppStatusBits_IpAcquired = 3, + /* If this bit is set: the SmartConfiguration process is + started from SmartConfig app */ + AppStatusBits_SmartconfigStart = 4, + /* If this bit is set: the device (P2P mode) found any + p2p-device in scan */ + AppStatusBits_P2pDevFound = 5, + /* If this bit is set: the device (P2P mode) found any + p2p-negotiation request */ + AppStatusBits_P2pReqReceived = 6, + /* If this bit is set: the device(P2P mode) + connection to client(or reverse way) is failed */ + AppStatusBits_ConnectionFailed = 7, + /* If this bit is set: the device has completed the ping operation */ + AppStatusBits_PingDone = 8, + /* If this bit is set: the device has acquired an IPv6 address */ + AppStatusBits_Ipv6lAcquired = 9, + /* If this bit is set: the device has acquired an IPv6 address */ + AppStatusBits_Ipv6gAcquired = 10, + + AppStatusBits_AuthenticationFailed = 11, + AppStatusBits_ResetRequired = 12, +}AppStatusBits; + +// nF Control block for SimpleLink +typedef struct nanoFramework_ControlBlock_t +{ + + uint32_t status;/* SimpleLink Status */ + + // uint32_t gatewayIP;/* Network Gateway IP address */ + + // uint8_t connectionSSID[SL_WLAN_SSID_MAX_LENGTH + 1];/* Connection SSID */ + + // uint8_t ssidLen;/* Connection SSID */ + + // uint8_t connectionBSSID[SL_WLAN_BSSID_LENGTH];/* Connection BSSID */ + +}nanoFramework_CB; + +extern nanoFramework_CB nF_ControlBlock; + + +#endif //_SIMPLELINK_CC32XX_THREADS_H_ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt index c61dda6ef2..07917ed851 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt @@ -6,6 +6,7 @@ # append nanoCLR source files list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/ti_drivers_net_wifi_Config.c") # make var global set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c index c1c7915fd3..2b55ff707c 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c @@ -3,34 +3,21 @@ #include /* POSIX Header files */ #include +#include /* RTOS header files */ #include "FreeRTOS.h" #include "task.h" -/* TI-RTOS Header files */ -#include - /* Example/Board Header files */ #include "Board.h" -#include -#include -#include -#include - -extern void * CLRStartupThread(void *arg0); -extern void * ReceiverThread(void *arg0); - -////////////////////////////// -#define SL_STOP_TIMEOUT (200) -#define APPLICATION_NAME "out of box" -#define APPLICATION_VERSION "1.00.00.09" - ////////////////////////////// /* Stack size in bytes */ -#define THREADSTACKSIZE 4096 +#define THREADSTACKSIZE 2024 + +extern void * mainThread(void *arg0); /* * ======== main ======== @@ -38,57 +25,14 @@ extern void * ReceiverThread(void *arg0); int main(void) { pthread_t thread; - pthread_attr_t pAttrs; - struct sched_param priParam; - - pthread_t receiverThread; - pthread_attr_t receiverThreadAttributes; - struct sched_param receiverThreadParams; - - pthread_t nanoCLRThread; - pthread_attr_t nanoCLRThreadAttributes; - struct sched_param nanoCLRThreadParams; - - + pthread_attr_t threadAttributes; + struct sched_param priorityParameters; + int retc; /* Call board init functions */ Board_initGeneral(); - GPIO_init(); - UART_init(); - SPI_init(); - I2C_init(); - - // receiver thread - receiverThreadParams.sched_priority = 1; - retc = pthread_attr_setschedparam(&receiverThreadAttributes, &receiverThreadParams); - retc |= pthread_attr_setdetachstate(&receiverThreadAttributes, PTHREAD_CREATE_DETACHED); - retc |= pthread_attr_setstacksize(&receiverThreadAttributes, 2048); - if (retc != 0) { - /* failed to set attributes */ - while (1) {} - } - - retc = pthread_create(&thread, &receiverThreadAttributes, ReceiverThread, NULL); - if(retc != 0) - { - /* pthread_create() failed */ - while(1) - { - ; - } - } - - // CLR thread - nanoCLRThreadParams.sched_priority = 1; - retc = pthread_attr_setschedparam(&nanoCLRThreadAttributes, &nanoCLRThreadParams); - retc |= pthread_attr_setdetachstate(&nanoCLRThreadAttributes, PTHREAD_CREATE_DETACHED); - retc |= pthread_attr_setstacksize(&nanoCLRThreadAttributes, 15000); - if (retc != 0) { - /* failed to set attributes */ - while (1) {} - } // CLR settings to launch CLR thread CLR_SETTINGS clrSettings; @@ -98,7 +42,15 @@ int main(void) clrSettings.WaitForDebugger = false; clrSettings.EnterDebuggerLoopAfterExit = false; - retc = pthread_create(&thread, &nanoCLRThreadAttributes, CLRStartupThread, &clrSettings); + /* Set priority and stack size attributes */ + pthread_attr_init(&threadAttributes); + priorityParameters.sched_priority = 1; + + retc = pthread_attr_setdetachstate(&threadAttributes, PTHREAD_CREATE_DETACHED); + + pthread_attr_setschedparam(&threadAttributes, &priorityParameters); + retc |= pthread_attr_setstacksize(&threadAttributes, THREADSTACKSIZE); + retc |= pthread_create(&thread, &threadAttributes, mainThread, &clrSettings); if(retc != 0) { /* pthread_create() failed */ @@ -113,288 +65,3 @@ int main(void) return (0); } - -//***************************************************************************** -// -//! \brief Application defined malloc failed hook -//! -//! \param none -//! -//! \return none -//! -//***************************************************************************** -void vApplicationMallocFailedHook() -{ - /* Handle Memory Allocation Errors */ - while(1) - { - } -} - -//***************************************************************************** -// -//! \brief Application defined stack overflow hook -//! -//! \param none -//! -//! \return none -//! -//***************************************************************************** -void vApplicationStackOverflowHook(TaskHandle_t pxTask, - char *pcTaskName) -{ - //Handle FreeRTOS Stack Overflow - while(1) - { - } -} - -void vApplicationTickHook(void) -{ - /* - * This function will be called by each tick interrupt if - * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - * added here, but the tick hook is called from an interrupt context, so - * code must not attempt to block, and only the interrupt safe FreeRTOS API - * functions can be used (those that end in FromISR()). - */ -} - -void vPreSleepProcessing(uint32_t ulExpectedIdleTime) -{ -} - -//***************************************************************************** -// -//! \brief Application defined idle task hook -//! -//! \param none -//! -//! \return none -//! -//***************************************************************************** -void -vApplicationIdleHook(void) -{ - /* Handle Idle Hook for Profiling, Power Management etc */ -} - -//***************************************************************************** -// -//! \brief Overwrite the GCC _sbrk function which check the heap limit related -//! to the stack pointer. -//! In case of freertos this checking will fail. -//! \param none -//! -//! \return none -//! -//***************************************************************************** -void * _sbrk(uint32_t delta) -{ - extern char _end; /* Defined by the linker */ - extern char __HeapLimit; - static char *heap_end; - static char *heap_limit; - char *prev_heap_end; - - if(heap_end == 0) - { - heap_end = &_end; - heap_limit = &__HeapLimit; - } - - prev_heap_end = heap_end; - if(prev_heap_end + delta > heap_limit) - { - return((void *) -1L); - } - heap_end += delta; - return((void *) prev_heap_end); -} - - -// /***************************************************************************** -// Local Functions -// *****************************************************************************/ -// //***************************************************************************** -// // -// //! Application Boarders display on UART -// //! -// //! \param ch - Character to be displayed , n - number of time to display -// //! -// //! \return none -// //! -// //***************************************************************************** -// void printBorder(char ch, -// int n) -// { -// int i = 0; - -// for(i = 0; i < n; i++) -// { -// putch(ch); -// } -// } - -// //***************************************************************************** -// // -// //! Application startup display on UART -// //! -// //! \param none -// //! -// //! \return none -// //! -// //***************************************************************************** -// int32_t DisplayBanner(char * AppName, -// char * AppVer) -// { -// int32_t ret = 0; -// uint8_t macAddress[SL_MAC_ADDR_LEN]; -// uint16_t macAddressLen = SL_MAC_ADDR_LEN; -// uint16_t ConfigSize = 0; -// uint8_t ConfigOpt = SL_DEVICE_GENERAL_VERSION; -// SlDeviceVersion_t ver = {0}; -// char lineBreak[] = "\n\r"; -// ConfigSize = sizeof(SlDeviceVersion_t); - -// /* Print device version info. */ -// ret = -// sl_DeviceGet(SL_DEVICE_GENERAL, &ConfigOpt, &ConfigSize, -// (uint8_t*)(&ver)); -// ASSERT_ON_ERROR(ret); - -// /* Print device Mac address */ -// ret = sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, -// &macAddress[0]); -// ASSERT_ON_ERROR(ret); - -// UART_PRINT(lineBreak); -// UART_PRINT("\t"); -// printBorder('=', 44); -// UART_PRINT(lineBreak); -// UART_PRINT("\t %s Example Ver: %s",AppName, AppVer); -// UART_PRINT(lineBreak); -// UART_PRINT("\t"); -// printBorder('=', 44); -// UART_PRINT(lineBreak); -// UART_PRINT(lineBreak); -// UART_PRINT("\t CHIP: 0x%x",ver.ChipId); -// UART_PRINT(lineBreak); -// UART_PRINT("\t MAC: %d.%d.%d.%d",ver.FwVersion[0],ver.FwVersion[1], -// ver.FwVersion[2], -// ver.FwVersion[3]); -// UART_PRINT(lineBreak); -// UART_PRINT("\t PHY: %d.%d.%d.%d",ver.PhyVersion[0],ver.PhyVersion[1], -// ver.PhyVersion[2], -// ver.PhyVersion[3]); -// UART_PRINT(lineBreak); -// UART_PRINT("\t NWP: %d.%d.%d.%d",ver.NwpVersion[0],ver.NwpVersion[1], -// ver.NwpVersion[2], -// ver.NwpVersion[3]); -// UART_PRINT(lineBreak); -// UART_PRINT("\t ROM: %d",ver.RomVersion); -// UART_PRINT(lineBreak); -// UART_PRINT("\t HOST: %s", SL_DRIVER_VERSION); -// UART_PRINT(lineBreak); -// UART_PRINT("\t MAC address: %02x:%02x:%02x:%02x:%02x:%02x", macAddress[0], -// macAddress[1], macAddress[2], macAddress[3], macAddress[4], -// macAddress[5]); -// UART_PRINT(lineBreak); -// UART_PRINT(lineBreak); -// UART_PRINT("\t"); -// printBorder('=', 44); -// UART_PRINT(lineBreak); -// UART_PRINT(lineBreak); - -// return(ret); -// } - -//***************************************************************************** -// -//! This function clears and enables a GPIO pin interrupt flag -//! -//! \param index - GPIO index -//! -//! \return None -//! -//***************************************************************************** -static void GPIO_clearAndEnable(uint8_t index) -{ - GPIO_clearInt(index); - GPIO_enableInt(index); -} - - -void * mainThread(void *arg) -{ - int32_t RetVal; - pthread_attr_t pAttrs; - pthread_attr_t pAttrs_spawn; - struct sched_param priParam; - struct timespec ts = {0}; - - /* init Terminal, and print App name */ - //InitTerm(); - - /* initialize the realtime clock */ - clock_settime(CLOCK_REALTIME, &ts); - - /* Switch off all LEDs on boards */ - GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); - - // /* create the sl_Task */ - // pthread_attr_init(&pAttrs_spawn); - // priParam.sched_priority = SPAWN_TASK_PRIORITY; - // RetVal = pthread_attr_setschedparam(&pAttrs_spawn, &priParam); - // RetVal |= pthread_attr_setstacksize(&pAttrs_spawn, TASK_STACK_SIZE); - - // RetVal = pthread_create(&gSpawnThread, &pAttrs_spawn, sl_Task, NULL); - - // if(RetVal) - // { - // /* Handle Error */ - // UART_PRINT("Unable to create sl_Task thread \n"); - // while(1) - // { - // ; - // } - // } - // RetVal = sl_Start(0, 0, 0); - // if(RetVal >= 0) - // { - // DisplayBanner(APPLICATION_NAME, APPLICATION_VERSION); - // RetVal = sl_Stop(SL_STOP_TIMEOUT); - // if(RetVal < 0) - // { - // /* Handle Error */ - // UART_PRINT("\n sl_Stop failed\n"); - // while(1) - // { - // ; - // } - // } - // } - // else if((RetVal < 0) && (RetVal != SL_ERROR_RESTORE_IMAGE_COMPLETE)) - // { - // /* Handle Error */ - // UART_PRINT("\n sl_Start failed\n"); - // UART_PRINT("\n %s Example Ver. %s\n",APPLICATION_NAME, - // APPLICATION_VERSION); - // while(1) - // { - // ; - // } - // } - - while(1) - { - /* Turn on user LED */ - GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); - usleep(50000); - /* Turn off user LED */ - GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); - usleep(50000); - } - - return(0); -} \ No newline at end of file diff --git a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt index ab0656fbe6..f8e474b643 100644 --- a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt +++ b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt @@ -37,6 +37,13 @@ list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Me # append nanoCRT list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoCRT.cpp") +# append SimpleLink target specific files +if("${TARGET_SERIES}" STREQUAL "CC32xx") + list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetSimpleLinkCC32xx_Threads.c") + list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetSimpleLinkCC32xx_LinkLocalTask.c") + list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetSimpleLinkCC32xx_ProvisioningTask.c") +endif() + # append files from Runtime.Native # list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp") diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c new file mode 100644 index 0000000000..07cc62dadd --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c @@ -0,0 +1,2838 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +/* standard includes */ +#include +#include + +/* TI-DRIVERS Header files */ +#include +#include +#include + +/* Example/Board Header files */ +#include +#include +#include + +/* driverlib Header files */ +#include +#include + + +#define NETAPP_MAX_RX_FRAGMENT_LEN SL_NETAPP_REQUEST_MAX_DATA_LEN +#define NETAPP_MAX_METADATA_LEN (100) +#define NETAPP_MAX_ARGV_TO_CALLBACK SL_FS_MAX_FILE_NAME_LENGTH + 50 +#define NUMBER_OF_URI_SERVICES (6) + +#define LED_TOGGLE_OTA_PROCESS_TIMEOUT (100) /* In msecs */ + +#define DEV_TYPE_CC3220R (0x010) +#define DEV_TYPE_CC3220RS (0x018) +#define DEV_TYPE_CC3220FS (0x019) +#define DEV_TYPE_CC323XR (0x110) +#define DEV_TYPE_CC323XRS (0x118) +#define DEV_TYPE_CC323XFS (0x119) + +#define MAC_ADDR_STR_LEN (18) +#define IP_ADDR_STR_LEN (16) +#define SENSOR_VALUE_STR_LEN (4) + + +/**************************************************************************** + LOCAL FUNCTION PROTOTYPES +****************************************************************************/ + +//***************************************************************************** +// +//! \brief This function prepare error netapp response in case memory could +//! not be allocated +//! +//! \param[in] pNetAppResponse netapp response structure +//! +//! \return none +//! +//**************************************************************************** +void NetAppRequestErrorResponse(SlNetAppResponse_t *pNetAppResponse); + +//***************************************************************************** +// +//! \brief This function fetches the device MAC address +//! +//! \param[out] buffer to occupy the MAC address in string format +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceMacAddress(uint8_t *macAddress); + +//***************************************************************************** +// +//! Function to read accelarometer +//! +//! \param none +//! +//! \return SUCCESS or FAILURE +//! +//***************************************************************************** +uint8_t accelarometerReading(void); + +//***************************************************************************** +// +//! Function to read temperature +//! +//! \param none +//! +//! \return SUCCESS or FAILURE +//! +//***************************************************************************** +uint8_t temperatureReading(void); + +//***************************************************************************** +// +//! \brief this function composes an element type from metadata/payload +//!(TLV structure) +//! +//! \param[in] isAnswer states whether this is a value or a parameter +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] elementVal value of element +//! +//! \return element type +//! +//**************************************************************************** +uint16_t setElementType(uint8_t isValue, + uint8_t requestIdx, + uint8_t elementVal); + +//***************************************************************************** +// +//! \brief This function prepares metadata for HTTP GET requests +//! +//! \param[in] parsingStatus validity of HTTP GET request +//! +//! \param[in] contentLen content length in respond to +//! HTTP GET request +//! +//! \return metadataLen +//! +//**************************************************************************** +uint16_t prepareGetMetadata(int32_t parsingStatus, + uint32_t contentLen, + HttpContentTypeList contentTypeId); + +//***************************************************************************** +// +//! \brief This function prepares metadata for HTTP POST/PUT requests +//! +//! \param[in] parsingStatus validity of HTTP POST/PUT request +//! +//! \return metadataLen +//! +//**************************************************************************** +uint16_t preparePostMetadata(int32_t parsingStatus); + +//***************************************************************************** +// +//! \brief This function fetches the device IP address +//! +//! \param[in] none +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceIpAddress(void); + +//***************************************************************************** +// +//! \brief This function fetches the SSID the device is connected to +//! +//! \param[in] none +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceSSID(void); + +//***************************************************************************** +// +//! \brief This function flushes the netapp data from the client +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \param[in] flags netapp flags for more data +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaFlushNetappReq(SlNetAppRequest_t *netAppRequest, + uint32_t *flags); + +//***************************************************************************** +// +//! \brief This is a filesystem service callback function for HTTP PUT +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaPutCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is the ota service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is a light service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t lightGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is a light service callback function for HTTP POST +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t lightPostCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is a sensors service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t sensorGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is a generic device service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t deviceGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This function create mailbox message queue between linkLocal task +//! and driver task +//! +//! \param[in] None +//! +//! \return 0 on success or -ve on error +//! +//**************************************************************************** +void initLinkLocalDB(void); + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the payload +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] pPhrase pointer to HTTP metadata payload +//! +//! \param[in] payloadLen HTTP metadata or payload length +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseUrlEncoded(uint8_t requestIdx, + uint8_t * pPhrase, + uint16_t phraseLen, + uint8_t *argcCallback, + uint8_t **argvCallback); + +//***************************************************************************** +// +//! \brief This function maps header type to its string value +//! +//! \param[in] httpHeaderType http header type +//! +//! \param[out] httpHeaderText http header text +//! +//! \return none +//! +//**************************************************************************** +void convertHeaderType2Text(uint8_t httpHeaderType, + uint8_t **httpHeaderText); + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the metadata +//! +//! \param[in] requestType HTTP method (GET, POST, PUT or DEL) +//! +//! \param[in] pMetadata pointer to HTTP metadata +//! +//! \param[in] metadataLen HTTP metadata length +//! +//! \param[out] requestIdx request index to indicate the message +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseHttpRequestMetadata(uint8_t requestType, + uint8_t * pMetadata, + uint16_t metadataLen, + uint8_t *requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback); + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the payload +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] pPayload pointer to HTTP payload +//! +//! \param[in] payloadLen HTTP payload length +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseHttpRequestPayload(uint8_t requestIdx, + uint8_t * pPayload, + uint16_t payloadLen, + uint8_t *argcCallback, + uint8_t **argvCallback); + +//***************************************************************************** +// +//! \brief This function checks that the content requested via HTTP message exists +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \param[out] requestIdx request index to indicate the message +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t httpCheckContentInDB(SlNetAppRequest_t *netAppRequest, + uint8_t *requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback); + +//***************************************************************************** +// +//! \brief This function parse and execute HTTP GET requests +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return None +//! +//**************************************************************************** +void httpGetHandler(SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This function parse and execute HTTP POST/PUT requests +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return None +//! +//**************************************************************************** +void httpPostHandler(SlNetAppRequest_t *netAppRequest); + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ + +const uint8_t pageNotFound[] = "404 - Sorry page not found"; + +/* metadata and content buffer are allocated + static as these are shared in all use cases*/ +/* however, it is possible to set those dynamically as well */ +uint8_t gMetadataBuffer[NETAPP_MAX_METADATA_LEN]; +uint8_t gPayloadBuffer[NETAPP_MAX_RX_FRAGMENT_LEN]; +//uint8_t gOtaVersion[VERSION_STR_SIZE + 1]; + +uint8_t gHttpPostBuffer[NETAPP_MAX_ARGV_TO_CALLBACK]; +uint8_t gHttpGetBuffer[NETAPP_MAX_ARGV_TO_CALLBACK]; + +int8_t xVal, yVal, zVal; +float temperatureVal; +I2C_Handle i2cHandle; + +/* database to hold ota archive */ +//OtaArchive_t gOtaArcive; + +/* message queue for http messages between server and client */ +mqd_t linkLocalMQueue; +pthread_mutex_t *sensorLockObj = NULL; /* Lock Object for sensor readings */ + +http_RequestObj_t httpRequest[NUMBER_OF_URI_SERVICES] = +{ + {0, SL_NETAPP_REQUEST_HTTP_GET, "/ota", { + {NULL} + }, NULL}, + {1, SL_NETAPP_REQUEST_HTTP_PUT, "/ota", { + {NULL} + }, NULL}, + {2, SL_NETAPP_REQUEST_HTTP_GET, "/light", { + {NULL} + }, NULL}, + {3, SL_NETAPP_REQUEST_HTTP_POST, "/light", { + {NULL} + }, NULL}, + {4, SL_NETAPP_REQUEST_HTTP_GET, "/sensor", { + {NULL} + }, NULL}, + {5, SL_NETAPP_REQUEST_HTTP_GET, "/device", { + {NULL} + }, NULL}, +}; + +http_headerFieldType_t g_HeaderFields [] = +{ + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_VERSION, WEB_SERVER_VERSION}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REQUEST_URI, WEB_SERVER_REQUEST_URI}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_QUERY_STRING, + WEB_SERVER_QUERY_STRING}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_TYPE, + WEB_SERVER_HEADER_CONTENT_TYPE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN, + WEB_SERVER_HEADER_CONTENT_LEN}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_LOCATION, + WEB_SERVER_HEADER_LOCATION}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SERVER, WEB_SERVER_HEADER_SERVER}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_USER_AGENT, + WEB_SERVER_HEADER_USER_AGENT}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_COOKIE, WEB_SERVER_HEADER_COOKIE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SET_COOKIE, + WEB_SERVER_HEADER_SET_COOKIE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_UPGRADE, WEB_SERVER_HEADER_UPGRADE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REFERER, WEB_SERVER_HEADER_REFERER}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ACCEPT, WEB_SERVER_HEADER_ACCEPT}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_ENCODING, + WEB_SERVER_HEADER_CONTENT_ENCODING}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_DISPOSITION, + WEB_SERVER_HEADER_CONTENT_DISPOSITION}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONNECTION, + WEB_SERVER_HEADER_CONNECTION}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ETAG, WEB_SERVER_HEADER_ETAG}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_DATE, WEB_SERVER_HEADER_DATE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HEADER_HOST, WEB_SERVER_HEADER_HOST}, + {SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_ENCODING, + WEB_SERVER_HEADER_ACCEPT_ENCODING}, + {SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_LANGUAGE, + WEB_SERVER_HEADER_ACCEPT_LANGUAGE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_CONTENT_LANGUAGE, + WEB_SERVER_HEADER_CONTENT_LANGUAGE} +}; + +http_contentTypeMapping_t g_ContentTypes [] = +{ + {HttpContentTypeList_TextHtml, TEXT_HTML, TEXT_HTML_MIME}, + {HttpContentTypeList_TextCSS, TEXT_CSS, TEXT_CSS_MIME}, + {HttpContentTypeList_TextXML, TEXT_XML, TEXT_XML_MIME}, + {HttpContentTypeList_ApplicationJson, APPLICATION_JSON, + APPLICATION_JSON_MIME}, + {HttpContentTypeList_ImagePNG, IMAGE_PNG, IMAGE_PNG_MIME}, + {HttpContentTypeList_ImageGIF, IMAGE_GIF, IMAGE_GIF_MIME}, + {HttpContentTypeList_TextPlain, TEXT_PLAIN, TEXT_PLAIN_MIME}, + {HttpContentTypeList_TextCSV, TEXT_CSV, TEXT_CSV_MIME}, + {HttpContentTypeList_ApplicationJavascript, APPLICATION_JAVASCRIPT, + APPLICATION_JAVASCRIPT_MIME}, + {HttpContentTypeList_ImageJPEG, IMAGE_JPEG, IMAGE_JPEG_MIME}, + {HttpContentTypeList_ApplicationPDF, APPLICATION_PDF, + APPLICATION_PDF_MIME}, + {HttpContentTypeList_ApplicationZIP, APPLICATION_ZIP, + APPLICATION_ZIP_MIME}, + {HttpContentTypeList_ShokewaveFlash, SHOCKWAVE_FLASH, + SHOCKWAVE_FLASH_MIME}, + {HttpContentTypeList_AudioXAAC, AUDIO_X_AAC, AUDIO_X_AAC_MIME}, + {HttpContentTypeList_ImageXIcon, IMAGE_X_ICON, IMAGE_X_ICON_MIME}, + {HttpContentTypeList_TextVcard, TEXT_VCARD, TEXT_VCARD_MIME}, + {HttpContentTypeList_ApplicationOctecStream, APPLICATION_OCTEC_STREAM, + APPLICATION_OCTEC_STREAM_MIME}, + {HttpContentTypeList_VideoAVI, VIDEO_AVI, VIDEO_AVI_MIME}, + {HttpContentTypeList_VideoMPEG, VIDEO_MPEG, VIDEO_MPEG_MIME}, + {HttpContentTypeList_VideoMP4, VIDEO_MP4, VIDEO_MP4_MIME}, + {HttpContentTypeList_UrlEncoded, FORM_URLENCODED, URL_ENCODED_MIME} +}; + +LinkLocal_CB LinkLocal_ControlBlock; + +extern int snprintf(char *_string, + size_t _n, + const char *_format, + ...); + +/***************************************************************************** + Callback Functions +*****************************************************************************/ + +//***************************************************************************** +// +//! \brief This function is registered as netapp request callback +//! +//! \param[in] pNetAppRequest netapp request structure +//! +//! \param[out] pNetAppResponse netapp response structure +//! +//! \return none +//! +//**************************************************************************** +void SimpleLinkNetAppRequestEventHandler(SlNetAppRequest_t *pNetAppRequest, + SlNetAppResponse_t *pNetAppResponse) +{ + SlNetAppRequest_t *netAppRequest; + int32_t msgqRetVal; + + //INFO_PRINT( + // "[Link local task] NetApp Request Received - AppId = %d, Type = %d," + // "Handle = %d\n\r", + // pNetAppRequest->AppId, pNetAppRequest->Type, pNetAppRequest->Handle); + + if((pNetAppRequest->Type == SL_NETAPP_REQUEST_HTTP_GET) || + (pNetAppRequest->Type == SL_NETAPP_REQUEST_HTTP_DELETE) || + (pNetAppRequest->Type == SL_NETAPP_REQUEST_HTTP_POST) || + (pNetAppRequest->Type == SL_NETAPP_REQUEST_HTTP_PUT)) + { + /* Prepare pending response */ + pNetAppResponse->Status = SL_NETAPP_RESPONSE_PENDING; + pNetAppResponse->ResponseData.pMetadata = NULL; + pNetAppResponse->ResponseData.MetadataLen = 0; + pNetAppResponse->ResponseData.pPayload = NULL; + pNetAppResponse->ResponseData.PayloadLen = 0; + pNetAppResponse->ResponseData.Flags = 0; + } + else + { + NetAppRequestErrorResponse(pNetAppResponse); + + return; + } + + netAppRequest = (SlNetAppRequest_t *) malloc (sizeof(SlNetAppRequest_t)); + if(NULL == netAppRequest) + { + NetAppRequestErrorResponse(pNetAppResponse); + + return; + } + + memset(netAppRequest,0,sizeof(SlNetAppRequest_t)); + netAppRequest->AppId = pNetAppRequest->AppId; + netAppRequest->Type = pNetAppRequest->Type; + netAppRequest->Handle = pNetAppRequest->Handle; + netAppRequest->requestData.Flags = pNetAppRequest->requestData.Flags; + + /* Copy Metadata */ + if(pNetAppRequest->requestData.MetadataLen > 0) + { + netAppRequest->requestData.pMetadata = (uint8_t *) malloc ( + pNetAppRequest->requestData.MetadataLen); + if(NULL == netAppRequest->requestData.pMetadata) + { + NetAppRequestErrorResponse(pNetAppResponse); + free(netAppRequest); + return; + } + sl_Memcpy(netAppRequest->requestData.pMetadata, + pNetAppRequest->requestData.pMetadata, + pNetAppRequest->requestData.MetadataLen); + netAppRequest->requestData.MetadataLen = + pNetAppRequest->requestData.MetadataLen; + } + else + { + netAppRequest->requestData.MetadataLen = 0; + } + + /* Copy the payload */ + if(pNetAppRequest->requestData.PayloadLen > 0) + { + netAppRequest->requestData.pPayload = (uint8_t *) malloc ( + pNetAppRequest->requestData.PayloadLen); + if(NULL == netAppRequest->requestData.pPayload) + { + NetAppRequestErrorResponse(pNetAppResponse); + + if(netAppRequest->requestData.pMetadata != NULL) + { + free(netAppRequest->requestData.pMetadata); + } + free(netAppRequest); + return; + } + sl_Memcpy (netAppRequest->requestData.pPayload, + pNetAppRequest->requestData.pPayload, + pNetAppRequest->requestData.PayloadLen); + netAppRequest->requestData.PayloadLen = + pNetAppRequest->requestData.PayloadLen; + } + else + { + netAppRequest->requestData.PayloadLen = 0; + } + + msgqRetVal = mq_send(linkLocalMQueue, (char *)&netAppRequest, 1, 0); + if(msgqRetVal < 0) + { + //UART_PRINT("[Link local task] could not send element to msg queue\n\r"); + while(1) + { + ; + } + } +} + +//***************************************************************************** +// +//! \brief This is a filesystem service callback function for HTTP PUT +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the +//! service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaPutCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray; + uint16_t metadataLen; + uint8_t *filename; + int32_t status; + uint32_t flags; + uint32_t fileLen = 0; + uint16_t elementType; + int16_t otaState, processedBytes, unprocessedBytes, chunkLen, otaChunkLen; + int32_t accumulatedLen; + uint8_t otaProgressBar; + uint32_t deviceType; + struct timespec ts; + + StartLedEvtTimer(LED_TOGGLE_OTA_PROCESS_TIMEOUT); + + status = 0; + accumulatedLen = 0; + deviceType = getDeviceType(); + argvArray = *argvCallback; + + /* get the filename */ + filename = argvArray + 2 * ARGV_VALUE_OFFSET + 1; + + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + + /* search for the file length */ + while((*argcCallback > 0) && (*((uint16_t *)argvArray) != elementType)) + { + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + + (*argcCallback)--; + } + + if(*((uint16_t *)argvArray) == elementType) + { + sl_Memcpy ((uint8_t*)&fileLen, (argvArray + ARGV_VALUE_OFFSET), + *(argvArray + ARGV_LEN_OFFSET)); + } + + //UART_PRINT("[Link local task] Received OTA filename %s, len = %lu \n\r", + // filename, + // fileLen); + + /* Init the Tar parser module */ + //OtaArchive_Init(&gOtaArcive); + + otaProgressBar = 0; + + /* at this point start the report server in the background */ + /* signal to ota task */ + sem_post(&LinkLocal_ControlBlock.otaReportServerStartSignal); + + /* set the flags to check for more data */ + flags = netAppRequest->requestData.Flags; + + /* must be archive file name */ + if(strstr((const char *)filename, ".tar") == NULL) + { + //UART_PRINT( + // "[Link local task] OTA filename should be in *.tar format\n\r"); + status = -1; + goto exit_ota_put; + } + + /* updating versions */ + // OtaArchive_CheckVersion(&gOtaArcive, filename); + + sl_Memcpy(gPayloadBuffer, netAppRequest->requestData.pPayload, + netAppRequest->requestData.PayloadLen); + // status = + // (int32_t)OtaArchive_Process(&gOtaArcive, gPayloadBuffer, + // netAppRequest->requestData.PayloadLen, + // &processedBytes); + //INFO_PRINT("[Link local task] Received OTA payload %d. Processed %d \n\r", + // netAppRequest->requestData.PayloadLen, + // processedBytes); + + // if(status < 0) + // { + // goto exit_ota_put; + // } + // else if(status == ARCHIVE_STATUS_DOWNLOAD_DONE) + // { + // otaProgressBar = 100; + // mq_send(LinkLocal_ControlBlock.reportServerMQueue, + // (char *)&otaProgressBar, 1, + // 0); + + // /* Tar file parsing completed */ + // //UART_PRINT( + // // "[Link local task] sl_extLib_OtaRun: ---- " + // // "Download file completed %s\r\n", + // // filename); + + // status = 0; + + // goto exit_ota_put; + // } + unprocessedBytes = netAppRequest->requestData.PayloadLen - processedBytes; + accumulatedLen += processedBytes; + otaProgressBar = (accumulatedLen * 100) / fileLen; + mq_send(LinkLocal_ControlBlock.reportServerMQueue, (char *)&otaProgressBar, + 1, + 0); + + while(OOB_IS_NETAPP_MORE_DATA(flags) || + ((unprocessedBytes > 0) && + ((fileLen - accumulatedLen) < NETAPP_MAX_RX_FRAGMENT_LEN))) + { + /* copy the unprocessed part to the start of the buffer */ + if(unprocessedBytes > 0) + { + sl_Memcpy(&gPayloadBuffer[0], &gPayloadBuffer[processedBytes], + unprocessedBytes); + } + + if(OOB_IS_NETAPP_MORE_DATA(flags)) + { + chunkLen = NETAPP_MAX_RX_FRAGMENT_LEN - unprocessedBytes; + status = + sl_NetAppRecv(netAppRequest->Handle, (uint16_t *)&chunkLen, + &gPayloadBuffer[unprocessedBytes], + (unsigned long *)&flags); + //INFO_PRINT( + // "[Link local task] sl_NetAppRecv payload=%d, flags=%d \n\r", + // chunkLen, flags); + if(status < 0) + { + //UART_PRINT( + // "[Link local task] sl_NetAppRecv error=%d, flags=%d \n\r", + // status, flags); + /* Stop the parsing of the archive file */ + // OtaArchive_Abort(&gOtaArcive); + + goto exit_ota_put; + } + } + else + { + /* cover cases where netapp has no more data and + download is close to 100%. + Archive module needs more processing time to complete */ + //INFO_PRINT( + // "[Link local task] No more data in NetApp but archive module " + // "still has processing to do \n\r"); + status = 0; + chunkLen = 0; + } + + //otaState = OtaArchive_GetSktatus(&gOtaArcive); + //INFO_PRINT("[Link local task] OTA state is %d \n\r", otaState); + // if(otaState == OtaArchiveState_OpenFile) + // { + // //INFO_PRINT("[Link local task] File size is %d \n\r", + // // gOtaArcive.CurrTarObj.FileSize); + // } + + // if(otaState == OtaArchiveState_OpenFile) + // { + // if(strstr((const char *)gOtaArcive.CurrTarObj.pFileName, + // "mcuimg.bin") != NULL) + // { + // if((deviceType == DEV_TYPE_CC3220FS) || + // (deviceType == DEV_TYPE_CC323XFS)) + // { + // //UART_PRINT( + // // "[Link local task] mcu image of CC32xxR or CC32xxRS " + // // "cannot be programmed onto CC32xxSF\n\r"); + + // /* Stop the parsing of the archive file */ + // OtaArchive_Abort(&gOtaArcive); + + // goto exit_ota_put; + // } + // } + + // if(strstr((const char *)gOtaArcive.CurrTarObj.pFileName, + // "mcuflashimg.bin") != NULL) + // { + // if((deviceType == DEV_TYPE_CC3220R) || + // (deviceType == DEV_TYPE_CC3220RS) || + // (deviceType == DEV_TYPE_CC323XR) || + // (deviceType == DEV_TYPE_CC323XRS)) + // { + // //UART_PRINT( + // // "[Link local task] mcu image of CC32xxSF cannot be " + // // "programmed onto CC32xxR or CC32xxRS\n\r"); + + // /* Stop the parsing of the archive file */ + // OtaArchive_Abort(&gOtaArcive); + + // goto exit_ota_put; + // } + // } + // } + + otaChunkLen = chunkLen + unprocessedBytes; + // status = + // (int32_t)OtaArchive_Process(&gOtaArcive, gPayloadBuffer, + // otaChunkLen, + // &processedBytes); + + //INFO_PRINT( + // "[Link local task] Received OTA payload=%d. Processed=%d \n\r", + // otaChunkLen, processedBytes); + if(status < 0) + { + //UART_PRINT("[Link local task] OtaArchive error %d \n\r", status); + goto exit_ota_put; + } + // else if(status == ARCHIVE_STATUS_DOWNLOAD_DONE) + // { + // clock_gettime(CLOCK_REALTIME, &ts); + // ts.tv_nsec += 1000000; + // if(ts.tv_nsec > 1000000000) + // { + // ts.tv_nsec -= 1000000000; + // ts.tv_sec++; + // } + + // otaProgressBar = 100; + // mq_timedsend(LinkLocal_ControlBlock.reportServerMQueue, + // (char *)&otaProgressBar, 1, 0, + // &ts); + // /* Tar file parsing completed */ + // //UART_PRINT( + // // "[Link local task] sl_extLib_OtaRun: ---- Download " + // // "file completed %s\r\n", + // // filename); + + // status = 0; + + // goto exit_ota_put; + // } + unprocessedBytes = otaChunkLen - processedBytes; + accumulatedLen += processedBytes; + otaProgressBar = (accumulatedLen * 100) / fileLen; + + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_nsec += 1000000; + if(ts.tv_nsec > 1000000000) + { + ts.tv_nsec -= 1000000000; + ts.tv_sec++; + } + + mq_timedsend(LinkLocal_ControlBlock.reportServerMQueue, + (char *)&otaProgressBar, 1, 0, + &ts); + } + +exit_ota_put: + + + + /* several use cases can occur at this point + + + ▼use case▼| good | bad | no rx bufer | internal error | + --------------------------------------------------------------- + status | 0 | <0 | 0 | 0 | + --------------------------------------------------------------- + progress bar| 100 | <100 | <100 | <100 | + --------------------------------------------------------------- + flags | 0 | N/A | 0 | 80000000 | + --------------------------------------------------------------- + send metada?| yes | yes | yes | no | + --------------------------------------------------------------- + notes | | | bad case | bad case | + --------------------------------------------------------------- + + + */ + + /* progress bar is not yet 100% - bad case*/ + if(otaProgressBar != 100) + { + status = -1; + } + //UART_PRINT("[Link local task] ota put done. status=%d \r\n", status); + if(status == 0) + { + /* flush the netapp data from client */ + otaFlushNetappReq(netAppRequest, &flags); + } + + /* sending metadata is not allowed in case of internal error */ + if(OOB_IS_NETAPP_ERROR(flags)) + { + //UART_PRINT("[Link local task] sl_NetAppRecv error, flags=%d \n\r", + // flags); + } + else + { + metadataLen = preparePostMetadata(status); + + //INFO_PRINT("[Link local task] ota put, sending metadata \r\n"); + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA); + } + + if(status != 0) + { + /* mark progress bar to 0xFF so ota task + would get restarted to reopen socket */ + otaProgressBar = 0xFF; + + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_nsec += 1000000; + if(ts.tv_nsec > 1000000000) + { + ts.tv_nsec -= 1000000000; + ts.tv_sec++; + } + + mq_timedsend(LinkLocal_ControlBlock.reportServerMQueue, + (char *)&otaProgressBar, 1, 0, + &ts); + } + + //UART_PRINT("[Link local task] waiting for signal from report server\r\n"); + + /* waits for ota response server to + finish sending report messages to client */ + sem_wait(&LinkLocal_ControlBlock.otaReportServerStopSignal); + + StopLedEvtTimer(); + if(status == 0) + { + //GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + } + else + { + //GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + } + + if(status == 0) + { + /* it means Tar file is downloaded and parsed correctly. + Need to reset the MCU */ + mcuReboot(); + } + + return(status); +} + +//***************************************************************************** +// +//! \brief This is the ota service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray, *pPayload; + uint16_t metadataLen, elementType; + int32_t status = 0; + + argvArray = *argvCallback; + pPayload = gPayloadBuffer; + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + /* content length is irrelevant for GET */ + if(*((uint16_t *)argvArray) != elementType) + { + switch(*(argvArray + ARGV_VALUE_OFFSET)) + { + case OtaIdx_Version: + + // status = OtaArchive_GetCurrentVersion(gOtaVersion); + // if(status < 0) + // { + // //UART_PRINT( + // // "[Link local task] ota bundle version file does " + // // "not exist\r\n"); + // strcpy((char *)gMetadataBuffer, "no version file exists"); + // status = 0; + // } + // else + // { + // //sl_Memcpy(gMetadataBuffer, gOtaVersion, VERSION_STR_SIZE); + // gMetadataBuffer[VERSION_STR_SIZE] = '\0'; + // } + + break; + } + + sl_Memcpy ( + pPayload, + httpRequest[requestIdx].charValues[*(argvArray + + ARGV_VALUE_OFFSET)]. + characteristic, + strlen((const char *)httpRequest[requestIdx]. + charValues[*(argvArray+ARGV_VALUE_OFFSET)] + .characteristic)); + pPayload += strlen( + (const char *)httpRequest[requestIdx]. + charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + characteristic); + *pPayload++ = '='; + sl_Memcpy (pPayload, gMetadataBuffer, + strlen((const char *)gMetadataBuffer)); + pPayload += strlen((const char *)gMetadataBuffer); + *pPayload++ = '&'; + } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + /* NULL terminate the payload */ + *(pPayload - 1) = '\0'; + + metadataLen = + prepareGetMetadata(status, strlen( + (const char *)gPayloadBuffer), + HttpContentTypeList_UrlEncoded); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + //INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", metadataLen); + /* mark as last segment */ + sl_NetAppSend(netAppRequest->Handle, + strlen ((const char *)gPayloadBuffer), + gPayloadBuffer, + 0); + //INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + // strlen ((const char *)gPayloadBuffer)); + + return(status); +} + +//***************************************************************************** +// +//! \brief This is a light service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t lightGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray, *pPayload; + //uint8_t ledIdx = Board_GPIO_LED0; + uint16_t ledState, metadataLen, elementType; + + argvArray = *argvCallback; + pPayload = gPayloadBuffer; + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + // /* content length is irrelevant for GET */ + // if(*((uint16_t *)argvArray) != elementType) + // { + // switch(*(argvArray + ARGV_VALUE_OFFSET)) + // { + // case LedIdx_RedLed: + // ledIdx = Board_GPIO_LED0; + // break; + // case LedIdx_OrangeLed: + // ledIdx = Board_GPIO_LED0; + // break; + // case LedIdx_GreenLed: + // ledIdx = Board_GPIO_LED0; + // break; + // } + + // ledState = GPIO_read(ledIdx); + // sl_Memcpy ( + // pPayload, + // httpRequest[requestIdx].charValues[*(argvArray + + // ARGV_VALUE_OFFSET)]. + // characteristic, + // strlen((const char *)httpRequest[requestIdx]. + // charValues[*(argvArray+ARGV_VALUE_OFFSET)] + // .characteristic)); + // pPayload += strlen( + // (const char *)httpRequest[requestIdx]. + // charValues[*(argvArray + ARGV_VALUE_OFFSET)] + // .characteristic); + // *pPayload++ = '='; + // sl_Memcpy ( + // pPayload, + // httpRequest[requestIdx]. + // charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + // value[ledState],strlen((const char *)httpRequest[requestIdx]. + // charValues[*(argvArray + + // ARGV_VALUE_OFFSET)]. + // value[ledState])); + + // pPayload += strlen( + // (const char *)httpRequest[requestIdx]. + // charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + // value[ledState]); + // *pPayload++ = '&'; + // } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + /* NULL terminate the payload */ + *(pPayload - 1) = '\0'; + + metadataLen = prepareGetMetadata(0, + strlen((const char *)gPayloadBuffer), + HttpContentTypeList_UrlEncoded); + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + //INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", metadataLen); + /* mark as last segment */ + sl_NetAppSend ( netAppRequest->Handle, + strlen ((const char *)gPayloadBuffer), + gPayloadBuffer, 0); + //INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + // strlen ((const char *)gPayloadBuffer)); + + return(0); +} + +//***************************************************************************** +// +//! \brief This is a light service callback function for HTTP POST +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t lightPostCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray; + uint16_t metadataLen, elementType; + uint16_t ledState = 0xFF; + //uint16_t ledIdx = Board_GPIO_LED0; + argvArray = *argvCallback; + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + // /* content length is irrelevant for POST */ + // if(*((uint16_t *)argvArray) != elementType) + // { + // /* means it is the value, not the parameter */ + // if(*(argvArray + 1) & 0x80) + // { + // /* get the light operation */ + // switch(*(argvArray + ARGV_VALUE_OFFSET)) + // { + // case LedValues_Off: + // ledState = Board_GPIO_LED_OFF; + // break; + // case LedValues_On: + // ledState = Board_GPIO_LED_ON; + // break; + // case LedValues_Toggle: + // ledState = 0xFF; + // break; + // } + + // if(ledState == 0xFF) + // { + // GPIO_toggle(ledIdx); + // } + // else + // { + // GPIO_write(ledIdx, ledState); + // } + // } + // else /* means it is the parameter, not the value */ + // { + // /* apply to the right light */ + // switch(*(argvArray + ARGV_VALUE_OFFSET)) + // { + // case LedIdx_RedLed: + // ledIdx = Board_GPIO_LED0; + // break; + // } + // } + // } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + metadataLen = preparePostMetadata(0); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA); + + return(0); +} + +//***************************************************************************** +// +//! \brief This is a sensors service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t sensorGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray, *pPayload; + uint16_t metadataLen, elementType; + int16_t value = 0; + int32_t status; + + argvArray = *argvCallback; + pPayload = gPayloadBuffer; + + /* Read accelerometer axis values */ + status = accelarometerReading(); + if(status != 0) + { + //UART_PRINT( + // "[Link local task] Failed to read data from accelerometer\n\r"); + } + + /* Read temperature sensor values */ + status = temperatureReading(); + if(status != 0) + { + //UART_PRINT( + // "[Link local task] Failed to" + // " read data from temperature sensor\n\r"); + } + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + /* content length is irrelevant for GET */ + if(*((uint16_t *)argvArray) != elementType) + { + switch(*(argvArray + ARGV_VALUE_OFFSET)) + { + case SensorIdx_XAxis: + value = xVal; + break; + case SensorIdx_YAxis: + value = yVal; + break; + case SensorIdx_ZAxis: + value = zVal; + break; + case SensorIdx_FarnTemp: + value = (int16_t)temperatureVal; + break; + } + + sl_Memcpy ( + pPayload, + httpRequest[requestIdx].charValues[*(argvArray + + ARGV_VALUE_OFFSET)]. + characteristic, + strlen((const char *)httpRequest[requestIdx]. + charValues[*(argvArray+ARGV_VALUE_OFFSET)]. + characteristic)); + pPayload += strlen( + (const char *)httpRequest[requestIdx]. + charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + characteristic); + *pPayload++ = '='; + + snprintf((char *)pPayload, SENSOR_VALUE_STR_LEN, "%d", value); + /* add the value length */ + pPayload += strlen((const char *)pPayload); + *pPayload++ = '&'; + } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + /* NULL terminate the payload */ + *(pPayload - 1) = '\0'; + + metadataLen = prepareGetMetadata(0, + strlen((const char *)gPayloadBuffer), + HttpContentTypeList_UrlEncoded); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + //INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", metadataLen); + /* mark as last segment */ + sl_NetAppSend (netAppRequest->Handle, strlen ( + (const char *)gPayloadBuffer), gPayloadBuffer, 0); + //INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + // strlen ((const char *)gPayloadBuffer)); + + return(0); +} + +//***************************************************************************** +// +//! \brief This is a generic device service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t deviceGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray, *pPayload; + uint16_t metadataLen, elementType; + int32_t status; + uint32_t deviceType; + + argvArray = *argvCallback; + pPayload = gPayloadBuffer; + deviceType = getDeviceType(); + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + /* content length is irrelevant for GET */ + if(*((uint16_t *)argvArray) != elementType) + { + switch(*(argvArray + ARGV_VALUE_OFFSET)) + { + case DeviceIdx_Ssid: + status = getDeviceSSID(); + if(status != 0) + { + //UART_PRINT( + // "[Link local task] failed to get SSID. IP_ACQ=%d, " + // "IP_LEASED=%d\n\r", + // GET_STATUS_BIT(OutOfBox_ControlBlock.status, + // AppStatusBits_IpAcquired), + // GET_STATUS_BIT(OutOfBox_ControlBlock.status, + // AppStatusBits_IpLeased)); + goto exit_device_get; + } + break; + case DeviceIdx_IpAddress: + status = getDeviceIpAddress(); + if(status != 0) + { + goto exit_device_get; + } + break; + case DeviceIdx_MacAddress: + status = getDeviceMacAddress(gMetadataBuffer); + if(status != 0) + { + goto exit_device_get; + } + break; + case DeviceIdx_AppID: + /* 3235 applies for both CC3230 and CC3235 */ + if(deviceType == DEV_TYPE_CC323XFS) + { + strcpy((char *)gMetadataBuffer, "out_of_box_3235_fs"); + } + else if(deviceType == DEV_TYPE_CC323XRS) + { + strcpy((char *)gMetadataBuffer, "out_of_box_3235_rs"); + } + else if(deviceType == DEV_TYPE_CC323XR) + { + strcpy((char *)gMetadataBuffer, "out_of_box_3235_r"); + } + else if(deviceType == DEV_TYPE_CC3220FS) + { + strcpy((char *)gMetadataBuffer, "out_of_box_fs"); + } + else if(deviceType == DEV_TYPE_CC3220RS) + { + strcpy((char *)gMetadataBuffer, "out_of_box_rs"); + } + else if(deviceType == DEV_TYPE_CC3220R) + { + strcpy((char *)gMetadataBuffer, "out_of_box_r"); + } + else + { + //UART_PRINT( + // "[Link local task] device type %d is not supported\n\r", + // deviceType); + status = -1; + + goto exit_device_get; + } + + status = 0; + + break; + } + + sl_Memcpy ( + pPayload, + httpRequest[requestIdx].charValues[*(argvArray + + ARGV_VALUE_OFFSET)]. + characteristic, + strlen((const char *)httpRequest[requestIdx]. + charValues[*(argvArray+ARGV_VALUE_OFFSET)]. + characteristic)); + pPayload += strlen( + (const char *)httpRequest[requestIdx]. + charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + characteristic); + *pPayload++ = '='; + sl_Memcpy (pPayload, gMetadataBuffer, + strlen((const char *)gMetadataBuffer)); + pPayload += strlen((const char *)gMetadataBuffer); + *pPayload++ = '&'; + } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + /* NULL terminate the payload */ + *(pPayload - 1) = '\0'; + + status = 0; + +exit_device_get: + if(status != 0) + { + strcpy((char *)gPayloadBuffer, (const char *)pageNotFound); + } + + metadataLen = + prepareGetMetadata(status, + strlen((const char *)gPayloadBuffer), + HttpContentTypeList_UrlEncoded); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + //INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", metadataLen); + /* mark as last segment */ + sl_NetAppSend (netAppRequest->Handle, strlen ( + (const char *)gPayloadBuffer), gPayloadBuffer, 0); + //INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + // strlen ((const char *)gPayloadBuffer)); + + return(status); +} + +//***************************************************************************** +// Local Functions +//***************************************************************************** + +//***************************************************************************** +// +//! \brief This function prepare error netapp response in case memory could +//! not be allocated +//! +//! \param[in] pNetAppResponse netapp response structure +//! +//! \return none +//! +//**************************************************************************** +void NetAppRequestErrorResponse(SlNetAppResponse_t *pNetAppResponse) +{ + //UART_PRINT( + // "[Link local task] could not allocate memory for netapp request\n\r"); + + /* Prepare error response */ + pNetAppResponse->Status = SL_NETAPP_RESPONSE_NONE; + pNetAppResponse->ResponseData.pMetadata = NULL; + pNetAppResponse->ResponseData.MetadataLen = 0; + pNetAppResponse->ResponseData.pPayload = NULL; + pNetAppResponse->ResponseData.PayloadLen = 0; + pNetAppResponse->ResponseData.Flags = 0; +} + +//***************************************************************************** +// +//! \brief This function fetches the device MAC address +//! +//! \param[out] buffer to occupy the MAC address in string format +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceMacAddress(uint8_t *macAddress) +{ + uint8_t macAddressVal[6]; + uint16_t macAddressLen; + int32_t status; + + macAddress[0] = '\0'; + + /* Get the device's MAC address */ + macAddressLen = 6; + status = + sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,NULL,&macAddressLen, + (uint8_t *)macAddressVal); + if(status < 0) + { + return(status); + } + + snprintf((char *)macAddress, MAC_ADDR_STR_LEN, + "%02x:%02x:%02x:%02x:%02x:%02x", + macAddressVal[0], + macAddressVal[1], + macAddressVal[2], + macAddressVal[3], + macAddressVal[4], + macAddressVal[5]); + + return(0); +} + +//***************************************************************************** +// +//! Function to read accelarometer +//! +//! \param none +//! +//! \return SUCCESS or FAILURE +//! +//***************************************************************************** +uint8_t accelarometerReading(void) +{ + int8_t xValRead, yValRead, zValRead; + int32_t status; + + if(sensorLockObj != NULL) + { + pthread_mutex_lock(sensorLockObj); + } + + /* Read accelarometer axis values */ + status = BMA2xxReadNew(i2cHandle, &xValRead, &yValRead, &zValRead); + if(status != 0) + { + /* try to read again */ + status = BMA2xxReadNew(i2cHandle, &xValRead, &yValRead, &zValRead); + if(status != 0) /* leave previous values */ + { + //UART_PRINT( + // "[Link local task] Failed to read data from accelarometer\n\r"); + } + } + + if(status == 0) + { + xVal = xValRead; + yVal = yValRead; + zVal = zValRead; + } + + if(sensorLockObj != NULL) + { + pthread_mutex_unlock(sensorLockObj); + } + + return(status); +} + +//***************************************************************************** +// +//! Function to read temperature +//! +//! \param none +//! +//! \return SUCCESS or FAILURE +//! +//***************************************************************************** +uint8_t temperatureReading(void) +{ + int32_t status; + float fTempRead; + + /* Read temperature axis values */ + status = TMP006DrvGetTemp(i2cHandle, &fTempRead); + if(status != 0) + { + /* try to read again */ + status = TMP006DrvGetTemp(i2cHandle, &fTempRead); + if(status != 0) /* leave previous values */ + { + //UART_PRINT( + // "[Link local task] Failed to read data from" + // " temperature sensor\n\r"); + } + } + + if(status == 0) + { + fTempRead = (fTempRead > 100) ? 100 : fTempRead; + temperatureVal = fTempRead; + } + + return(status); +} + +//***************************************************************************** +// +//! \brief this function composes an element type from metadata/payload +//! (TLV structure) +//! +//! \param[in] isAnswer states whether this is a value or a parameter +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] elementVal value of element +//! +//! \return element type +//! +//**************************************************************************** +uint16_t setElementType(uint8_t isValue, + uint8_t requestIdx, + uint8_t elementVal) +{ + uint16_t elementType; + + elementType = elementVal; + elementType |= (((isValue << 7) | (requestIdx & 0x7F)) << 8); + + return(elementType); +} + +//***************************************************************************** +// +//! \brief This function prepares metadata for HTTP GET requests +//! +//! \param[in] parsingStatus validity of HTTP GET request +//! +//! \param[in] contentLen content length in respond to +//! HTTP GET request +//! +//! \return metadataLen +//! +//**************************************************************************** +uint16_t prepareGetMetadata(int32_t parsingStatus, + uint32_t contentLen, + HttpContentTypeList contentTypeId) +{ + char *contentType; + uint8_t *pMetadata; + uint16_t metadataLen; + + contentType = g_ContentTypes[contentTypeId].contentTypeText; + + pMetadata = gMetadataBuffer; + + /* http status */ + *pMetadata = (uint8_t) SL_NETAPP_REQUEST_METADATA_TYPE_STATUS; + pMetadata++; + *(uint16_t *)pMetadata = (uint16_t) 2; + pMetadata += 2; + + if(parsingStatus < 0) + { + *(uint16_t *)pMetadata = + (uint16_t) SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; + } + else + { + *(uint16_t *)pMetadata = (uint16_t) SL_NETAPP_HTTP_RESPONSE_200_OK; + } + + pMetadata += 2; + + /* Content type */ + *pMetadata = (uint8_t) SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_TYPE; + pMetadata++; + (*(uint16_t *)pMetadata) = (uint16_t) strlen ((const char *)contentType); + pMetadata += 2; + sl_Memcpy (pMetadata, contentType, strlen((const char *)contentType)); + pMetadata += strlen((const char *)contentType); + + /* Content len */ + *pMetadata = SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN; + pMetadata++; + *(uint16_t *)pMetadata = (uint16_t) 4; + pMetadata += 2; + *(uint32_t *)pMetadata = (uint32_t) contentLen; + + metadataLen = 5 + 7 + strlen ((const char *)contentType) + 3; + + return(metadataLen); +} + +//***************************************************************************** +// +//! \brief This function prepares metadata for HTTP POST/PUT requests +//! +//! \param[in] parsingStatus validity of HTTP POST/PUT request +//! +//! \return metadataLen +//! +//**************************************************************************** +uint16_t preparePostMetadata(int32_t parsingStatus) +{ + uint8_t *pMetadata; + uint16_t metadataLen; + + pMetadata = gMetadataBuffer; + + /* http status */ + *pMetadata = (uint8_t) SL_NETAPP_REQUEST_METADATA_TYPE_STATUS; + pMetadata++; + *(uint16_t *)pMetadata = (uint16_t) 2; + pMetadata += 2; + + if(parsingStatus < 0) + { + *(uint16_t *)pMetadata = + (uint16_t) SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; + } + else + {/* no need for content so browser stays on the same page */ + *(uint16_t *)pMetadata = + (uint16_t) SL_NETAPP_HTTP_RESPONSE_204_OK_NO_CONTENT; + } + + pMetadata += 2; + + metadataLen = 5; + + return(metadataLen); +} + +//***************************************************************************** +// +//! \brief This function fetches the device IP address +//! +//! \param[in] none +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceIpAddress(void) +{ + uint16_t ConfigOpt; + uint16_t ipLen; + SlNetCfgIpV4Args_t ipV4 = {0}; + int32_t status; + + gMetadataBuffer[0] = '\0'; + + /* Get the device's IP address */ + ipLen = sizeof(SlNetCfgIpV4Args_t); + ConfigOpt = 0; + status = + sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&ipLen, + (uint8_t *)&ipV4); + if(status < 0) + { + return(status); + } + + snprintf((char *)gMetadataBuffer, IP_ADDR_STR_LEN, "%d.%d.%d.%d", + (int)SL_IPV4_BYTE(ipV4.Ip,3), + (int)SL_IPV4_BYTE(ipV4.Ip,2), + (int)SL_IPV4_BYTE(ipV4.Ip,1), + (int)SL_IPV4_BYTE(ipV4.Ip,0)); + + return(0); +} + +//***************************************************************************** +// +//! \brief This function fetches the SSID the device is connected to +//! +//! \param[in] none +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceSSID(void) +{ + uint16_t len = 32; + uint16_t config_opt = SL_WLAN_AP_OPT_SSID; + /* simplelink as station connected to AP */ + if(GET_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_IpAcquired) && + GET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_Connection)) + { + // sl_Memcpy ((uint8_t *)gMetadataBuffer, + // (const uint8_t *)nF_ControlBlock.connectionSSID, + // nF_ControlBlock.ssidLen); + // gMetadataBuffer[nF_ControlBlock.ssidLen] = '\0'; + } + /* simplelink as AP with connected client */ + else if(GET_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_IpAcquired) && + GET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpLeased)) + { + // sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, + // (uint8_t *)nF_ControlBlock.connectionSSID); + // nF_ControlBlock.ssidLen = len - 1; + // sl_Memcpy ((uint8_t *)gMetadataBuffer, + // (const uint8_t *)nF_ControlBlock.connectionSSID, + // nF_ControlBlock.ssidLen); + // gMetadataBuffer[nF_ControlBlock.ssidLen] = '\0'; + } + else + { + return(-1); + } + + return(0); +} + +//***************************************************************************** +// +//! \brief This function flushes the netapp data from the client +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \param[in] flags netapp flags for more data +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaFlushNetappReq(SlNetAppRequest_t *netAppRequest, + uint32_t *flags) +{ + int32_t status; + int32_t chunkLen; + + status = 0; + + while((*flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) == + SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) + { + chunkLen = NETAPP_MAX_RX_FRAGMENT_LEN; + status = + sl_NetAppRecv(netAppRequest->Handle, (uint16_t *)&chunkLen, + gPayloadBuffer, + (_u32 *)flags); + //INFO_PRINT("[Link local task] flushing NetApp packet, len=%d \n\r", + // chunkLen); + if(status < 0) + { + return(status); + } + + if(*flags == 0) + { + break; + } + } + + return(status); +} + +//***************************************************************************** +// +//! \brief This function create mailbox message queue between linkLocal task +//! and driver task +//! +//! \param[in] None +//! +//! \return 0 on success or -ve on error +//! +//**************************************************************************** +void initLinkLocalDB(void) +{ + httpRequest[0].charValues[0].characteristic = "version"; + httpRequest[0].serviceCallback = otaGetCallback; + + httpRequest[1].charValues[0].characteristic = "filename"; + httpRequest[1].serviceCallback = otaPutCallback; + + httpRequest[2].charValues[0].characteristic = "redled"; + httpRequest[2].charValues[0].value[0] = "off"; + httpRequest[2].charValues[0].value[1] = "on"; + httpRequest[2].charValues[0].value[2] = "toggle"; + httpRequest[2].charValues[1].characteristic = "orangeled"; + httpRequest[2].charValues[1].value[0] = "off"; + httpRequest[2].charValues[1].value[1] = "on"; + httpRequest[2].charValues[1].value[2] = "toggle"; + httpRequest[2].charValues[2].characteristic = "greenled"; + httpRequest[2].charValues[2].value[0] = "off"; + httpRequest[2].charValues[2].value[1] = "on"; + httpRequest[2].charValues[2].value[2] = "toggle"; + httpRequest[2].serviceCallback = lightGetCallback; + + httpRequest[3].charValues[0].characteristic = "redled"; + httpRequest[3].charValues[0].value[0] = "off"; + httpRequest[3].charValues[0].value[1] = "on"; + httpRequest[3].charValues[0].value[2] = "toggle"; + httpRequest[3].serviceCallback = lightPostCallback; + + httpRequest[4].charValues[0].characteristic = "axisx"; + httpRequest[4].charValues[1].characteristic = "axisy"; + httpRequest[4].charValues[2].characteristic = "axisz"; + httpRequest[4].charValues[3].characteristic = "temp"; + httpRequest[4].serviceCallback = sensorGetCallback; + + httpRequest[5].charValues[0].characteristic = "ssid"; + httpRequest[5].charValues[1].characteristic = "ipaddress"; + httpRequest[5].charValues[2].characteristic = "macaddress"; + httpRequest[5].charValues[3].characteristic = "appname"; + httpRequest[5].serviceCallback = deviceGetCallback; +} + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the payload +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] pPhrase pointer to HTTP metadata payload +//! +//! \param[in] payloadLen HTTP metadata or payload length +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseUrlEncoded(uint8_t requestIdx, + uint8_t * pPhrase, + uint16_t phraseLen, + uint8_t *argcCallback, + uint8_t **argvCallback) +{ + uint8_t *token; + uint8_t characteristic, value, isValueExpected, loopIdx; + int32_t status = -1; + uint8_t *argvArray; + uint8_t remainingLen, actualLen; + uint16_t elementType; + + argvArray = *argvCallback; + /* it means parameters already exist - fast forward to the end of argv */ + if(*argcCallback > 0) + { + loopIdx = *argcCallback; + while(loopIdx > 0) + { + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + + loopIdx--; + } + } + + /* check if values are expected per characteristic */ + /* it is a 2 steps procedure: */ + /* 1) check that '=' sign exists */ + /* 2) check that the value is not NULL */ + /* if not, return */ + isValueExpected = 0; + token = (uint8_t *)strchr((char *)pPhrase, '='); + if(token != NULL) + { /* it means no value supplied */ + if((*(token + 1) == '&') || (*(token + 1) == '\0')) + { + return(-1); + } + else + { + isValueExpected = 1; + } + } + + /* Parse payload list */ + token = (uint8_t *)strtok((char *)pPhrase, "=&"); + + if(NULL == token) /* it means there is no url encoded data */ + { + return(0); + } + + while(token && ((pPhrase + phraseLen) > token)) + { + status = -1; + characteristic = 0; + + /* run over all possible characteristics, if exist */ + while(httpRequest[requestIdx].charValues[characteristic].characteristic + != NULL) + { + if(!strncmp((const char *)token, + (const char *)httpRequest[requestIdx].charValues[ + characteristic]. + characteristic, + strlen((const char *)httpRequest[requestIdx].charValues + [ + characteristic].characteristic))) + { + status = 0; + + /* found a characteristic. save its index number */ + (*argcCallback)++; + elementType = setElementType(0, requestIdx, characteristic); + sl_Memcpy ((uint8_t*)argvArray, (uint8_t*)&elementType, + ARGV_LEN_OFFSET); + argvArray += ARGV_LEN_OFFSET; + *argvArray++ = 1; /* length field */ + *argvArray++ = characteristic; + /* remaining length is for cases where the last value is of + string type */ + remainingLen =(uint8_t) + (phraseLen -(uint8_t)(token -pPhrase) - + strlen((const char *)token) - 1); + + //UART_PRINT ( + // "[Link local task] characteristic is: %s\n\r", + // (int8_t *)httpRequest[requestIdx]. + // charValues[characteristic]. + // characteristic); + break; + } + else + { + characteristic++; + } + } + /* it means the characteristics is not valid/known */ + if(-1 == status) + { + return(status); + } + + token = (uint8_t *)strtok(NULL, "=&"); + + if(isValueExpected) + { + status = -1; + value = 0; + + if(token != NULL) + { + /* it means any value is OK */ + if(NULL == + httpRequest[requestIdx]. + charValues[characteristic].value[value]) + { + status = 0; + + /* found a string value. copy its content */ + (*argcCallback)++; + elementType = setElementType(1, requestIdx, value); + sl_Memcpy ((uint8_t*)argvArray, (uint8_t*)&elementType, + ARGV_LEN_OFFSET); + argvArray += ARGV_LEN_OFFSET; + if(strlen((const char *)token) > remainingLen) + { + actualLen = remainingLen; + } + else + { + actualLen = strlen((const char *)token); + } + + *argvArray++ = (actualLen + 1); + sl_Memcpy(argvArray, token, actualLen); + argvArray += actualLen; + *argvArray++ = '\0'; + + //UART_PRINT ("[Link local task] value is: %s\n\r", + // (int8_t *)(argvArray - actualLen - 1)); + } + else + { + /* run over all possible values, if exist */ + while(httpRequest[requestIdx].charValues[characteristic]. + value[value] != NULL) + { + if(!strncmp((const char *)token, + (const char *)httpRequest[requestIdx]. + charValues[ + characteristic].value[value], + strlen((const char *)httpRequest[requestIdx + ].charValues[ + characteristic].value[value]))) + { + status = 0; + + /* found a value. save its index number */ + (*argcCallback)++; + elementType = setElementType(1, requestIdx, value); + sl_Memcpy ((uint8_t*)argvArray, + (uint8_t*)&elementType, + ARGV_LEN_OFFSET); + argvArray += ARGV_LEN_OFFSET; + *argvArray++ = 1; /* length field */ + *argvArray++ = value; + + //UART_PRINT ( + // "[Link local task] value is: %s\n\r", + // (int8_t *)httpRequest[requestIdx]. + // charValues[ + // characteristic].value[value]); + + break; + } + else + { + value++; + } + } + /* it means the value is not valid/known */ + if(-1 == status) + { + return(status); + } + } + } + token = (uint8_t *)strtok(NULL, (const char *)"=&"); + } + } + + return(status); +} + +//***************************************************************************** +// +//! \brief This function maps header type to its string value +//! +//! \param[in] httpHeaderType http header type +//! +//! \param[out] httpHeaderText http header text +//! +//! \return none +//! +//**************************************************************************** +void convertHeaderType2Text(uint8_t httpHeaderType, + uint8_t **httpHeaderText) +{ + int i; + *httpHeaderText = NULL; + + for(i = 0; i < sizeof (g_HeaderFields) / sizeof(http_headerFieldType_t); + i++) + { + if(g_HeaderFields[i].headerType == httpHeaderType) + { + *httpHeaderText = (uint8_t *)(g_HeaderFields[i].headerText); + break; + } + } +} + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the metadata +//! +//! \param[in] requestType HTTP method (GET, POST, PUT or DEL) +//! +//! \param[in] pMetadata pointer to HTTP metadata +//! +//! \param[in] metadataLen HTTP metadata length +//! +//! \param[out] requestIdx request index to indicate the message +//! +//! \param[out] argcCallback count of input params to +//! the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseHttpRequestMetadata(uint8_t requestType, + uint8_t * pMetadata, + uint16_t metadataLen, + uint8_t *requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback) +{ + uint8_t *pTlv; + uint8_t *pEnd; + + int32_t status = -1; + uint8_t loopIdx; + uint8_t type; + uint16_t len; + uint32_t value; + uint8_t *typeText; + uint8_t nullTerminator; + uint8_t *argvArray; + uint16_t elementType; + + argvArray = *argvCallback; + + *requestIdx = 0xFF; + pTlv = pMetadata; + pEnd = pMetadata + metadataLen; + + if(metadataLen < 3) + { + //UART_PRINT("[Link local task] Metadata parsing error\n\r"); + + return(-1); + } + + //INFO_PRINT ("[Link local task] Metadata:\n\r"); + + while(pTlv < pEnd) + { + type = *pTlv; + pTlv++; + len = *(uint16_t *)pTlv; + pTlv += 2; + + convertHeaderType2Text(type, &typeText); + + if(typeText != NULL) + { + //INFO_PRINT ("[Link local task] %s ", typeText); + } + + switch(type) + { + case SL_NETAPP_REQUEST_METADATA_TYPE_STATUS: + /* there are browsers that seem to send many 0 type for no reason */ + /* in this case, do not print anything */ + break; + + case SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN: + /* it means there is a content length and URI is OK. Add it to the argv */ + if(0 == status) + { + /* it means parameters already exist from query type */ + if(*argcCallback > 0) + { + loopIdx = *argcCallback; + while(loopIdx > 0) + { + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + + loopIdx--; + } + } + + (*argcCallback)++; + /* add content type */ + elementType = setElementType(1, *requestIdx, CONTENT_LEN_TYPE); + sl_Memcpy ((uint8_t*)argvArray, (uint8_t*)&elementType, + ARGV_LEN_OFFSET); + argvArray += ARGV_LEN_OFFSET; + *argvArray++ = len; /* add content length */ + sl_Memcpy ((uint8_t*)argvArray, pTlv, len); + sl_Memcpy ((uint8_t*)&value, pTlv, len); + + //INFO_PRINT ("%d\n\r", (uint32_t)value); + } + + break; + + case SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REQUEST_URI: + /* this is the 1st stop in every http method. + zero out the character counter argument */ + *argcCallback = 0; + + for(loopIdx = 0; loopIdx < NUMBER_OF_URI_SERVICES; loopIdx++) + { + if((strncmp((const char *)pTlv, + (const char *)httpRequest[loopIdx].service, + strlen((const char *)httpRequest[loopIdx].service))) + == 0) + { + if(requestType == httpRequest[loopIdx].httpMethod) + { + status = 0; + *requestIdx = httpRequest[loopIdx].requestIdx; + //INFO_PRINT ("%s\n\r", httpRequest[loopIdx].service); + + break; + } + } + } + + if(status != 0) + { + //INFO_PRINT ("unknown service\n\r"); + } + + break; + + case SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_QUERY_STRING: + if(0 == status) + { + status = parseUrlEncoded(*requestIdx, pTlv, len, argcCallback, + argvCallback); + + if(status != 0) + { + //INFO_PRINT ( + // "query string in metadata section is not" + // " valid/known\n\r"); + } + } + + break; + + default: + nullTerminator = *(pTlv + len); + *(pTlv + len) = '\0'; + //INFO_PRINT("%s\n\r", pTlv); + *(pTlv + len) = nullTerminator; + + break; + } + pTlv += len; + } + + return(status); +} + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the payload +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] pPayload pointer to HTTP payload +//! +//! \param[in] payloadLen HTTP payload length +//! +//! \param[out] argcCallback count of input params to the +//! service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseHttpRequestPayload(uint8_t requestIdx, + uint8_t * pPayload, + uint16_t payloadLen, + uint8_t *argcCallback, + uint8_t **argvCallback) +{ + int32_t status = -1; + + status = parseUrlEncoded(requestIdx, pPayload, payloadLen, argcCallback, + argvCallback); + + if(status != 0) + { + //UART_PRINT ( + // "[Link local task] query string in payload section is " + // "not valid/known\n\r"); + } + + return(status); +} + +//***************************************************************************** +// +//! \brief This function checks that the content requested via HTTP +//! message exists +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \param[out] requestIdx request index to indicate the message +//! +//! \param[out] argcCallback count of input params to the service +//! callback +//! +//! \param[out] argvCallback set of input params to the service +//! callback +//! +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t httpCheckContentInDB(SlNetAppRequest_t *netAppRequest, + uint8_t *requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback) +{ + int32_t status = -1; + + if(netAppRequest->AppId != SL_NETAPP_HTTP_SERVER_ID) + { + return(status); + } + + status = + parseHttpRequestMetadata(netAppRequest->Type, + netAppRequest->requestData.pMetadata, + netAppRequest->requestData.MetadataLen, + requestIdx, argcCallback, + argvCallback); + + /* PUT does not contain parseable data - only POST does */ + if((0 == status) && (netAppRequest->requestData.PayloadLen != 0) && + (netAppRequest->Type != SL_NETAPP_REQUEST_HTTP_PUT)) + { + status = + parseHttpRequestPayload(*requestIdx, + netAppRequest->requestData.pPayload, + netAppRequest->requestData.PayloadLen, + argcCallback, + argvCallback); + } + + return(status); +} + +//***************************************************************************** +// +//! \brief This function parse and execute HTTP GET requests +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return None +//! +//**************************************************************************** +void httpGetHandler(SlNetAppRequest_t *netAppRequest) +{ + uint16_t metadataLen; + int32_t status; + uint8_t requestIdx; + + uint8_t argcCallback; + uint8_t *argvArray; + uint8_t **argvCallback = &argvArray; + + argvArray = gHttpGetBuffer; + + status = httpCheckContentInDB(netAppRequest, &requestIdx, &argcCallback, + argvCallback); + + if(status < 0) + { + metadataLen = + prepareGetMetadata(status, strlen ( + (const char *)pageNotFound), + HttpContentTypeList_TextHtml); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + //INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", + // metadataLen); +/* mark as last segment */ + sl_NetAppSend (netAppRequest->Handle, + strlen ((const char *)pageNotFound), + (uint8_t *)pageNotFound,0); + + //INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + // strlen ((const char *)pageNotFound)); + } + else + { + httpRequest[requestIdx].serviceCallback(requestIdx, &argcCallback, + argvCallback, + netAppRequest); + } +} + +//***************************************************************************** +// +//! \brief This function parse and execute HTTP POST/PUT requests +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return None +//! +//**************************************************************************** +void httpPostHandler(SlNetAppRequest_t *netAppRequest) +{ + uint16_t metadataLen; + int32_t status; + uint8_t requestIdx; + + uint8_t argcCallback; + uint8_t *argvArray; + uint8_t **argvCallback = &argvArray; + + argvArray = gHttpPostBuffer; + + status = httpCheckContentInDB(netAppRequest,&requestIdx,&argcCallback, + argvCallback); + + if(status < 0) + { + metadataLen = preparePostMetadata(status); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA); + } + else + { + httpRequest[requestIdx].serviceCallback(requestIdx, &argcCallback, + argvCallback, + netAppRequest); + } +} + +//**************************************************************************** +// MAIN FUNCTION +//**************************************************************************** + +//***************************************************************************** +// +//! \brief This function fetches the device type and prints it +//! +//! \param[in] None +//! +//! \return device type +//! +//**************************************************************************** +uint32_t getDeviceType(void) +{ + uint32_t deviceType; + uint16_t configSize = 0; + uint8_t configOpt = SL_DEVICE_GENERAL_VERSION; + SlDeviceVersion_t ver = {0}; + configSize = sizeof(SlDeviceVersion_t); + + /* Print device version info. */ + sl_DeviceGet(SL_DEVICE_GENERAL, &configOpt, &configSize, (uint8_t*)(&ver)); + + deviceType = ver.ChipId & 0xFF; + /* Update deviceType to 323XX or 3220X */ + if((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_DIEID_READ_REG4) >> 24) & 0x02) + { + deviceType |= (0x01 << 8); + } + + switch(deviceType) + { + case DEV_TYPE_CC323XR: // 323xR + //UART_PRINT("[Provisioning task] detected device is CC323xR\n\r"); + break; + case DEV_TYPE_CC323XRS: // 323xRS + //UART_PRINT("[Provisioning task] detected device is CC323xRS\n\r"); + break; + case DEV_TYPE_CC323XFS: // 323xFS + //UART_PRINT("[Provisioning task] detected device is CC323xSF\n\r"); + break; + case DEV_TYPE_CC3220R: // 3220R + //UART_PRINT("[Provisioning task] detected device is CC3220R\n\r"); + break; + case DEV_TYPE_CC3220RS: // 3220RS + //UART_PRINT("[Provisioning task] detected device is CC3220RS\n\r"); + break; + case DEV_TYPE_CC3220FS: // 3220FS + //UART_PRINT("[Provisioning task] detected device is CC3220SF\n\r"); + break; + default: + break; + } + + return(deviceType); +} + +//***************************************************************************** +// +//! \brief This task handles LinkLocal transactions with the client +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void * linkLocalTask(void *pvParameters) +{ + mq_attr attr; + int32_t msgqRetVal; + I2C_Params i2cParams; + + /* initializes I2C */ + I2C_Params_init(&i2cParams); + i2cParams.bitRate = I2C_400kHz; + // i2cHandle = I2C_open(Board_I2C0, &i2cParams); + // if(i2cHandle == NULL) + // { + // //UART_PRINT("[Link local task] Error Initializing I2C\n\r"); + // } + + /* Setup mutex operations for sensors reading */ + sensorLockObj = malloc(sizeof(pthread_mutex_t)); + pthread_mutex_init(sensorLockObj, (pthread_mutexattr_t*)NULL); + + /* initializes mailbox for http messages */ + attr.mq_maxmsg = 10; /* queue size */ + attr.mq_msgsize = sizeof(SlNetAppRequest_t*); /* Size of message */ + linkLocalMQueue = mq_open("linklocal msg q", O_CREAT, 0, &attr); + if(linkLocalMQueue == NULL) + { + //UART_PRINT("[Link local task] could not create msg queue\n\r"); + while(1) + { + ; + } + } + + initLinkLocalDB(); + + /* waits for valid local connection - via provisioning task */ + sem_wait(&Provisioning_ControlBlock.provisioningDoneSignal); + + while(1) + { + SlNetAppRequest_t *netAppRequest; + + msgqRetVal = + mq_receive(linkLocalMQueue, (char *)&netAppRequest, + sizeof(SlNetAppRequest_t*), NULL); + if(msgqRetVal < 0) + { + //UART_PRINT( + // "[Link local task] could not receive element from msg \ + // queue\n\r"); + while(1) + { + ; + } + } + + //INFO_PRINT( + // "[Link local task] NetApp Request Received - handle from main " + // "context AppId = %d, Type = %d, Handle = %d\n\r", + // netAppRequest->AppId, netAppRequest->Type, netAppRequest->Handle); + + //INFO_PRINT("[Link local task] Metadata len = %d\n\r", + // netAppRequest->requestData.MetadataLen); + + if((netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_GET) || + (netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_DELETE)) + { + if(netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_GET) + { + //UART_PRINT("[Link local task] HTTP GET Request\n\r"); + } + else + { + //UART_PRINT("[Link local task] HTTP DELETE Request\n\r"); + } + + httpGetHandler(netAppRequest); + } + else if((netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_POST) || + (netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_PUT)) + { + if(netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_POST) + { + //UART_PRINT("[Link local task] HTTP POST Request\n\r"); + } + else + { + //UART_PRINT("[Link local task] HTTP PUT Request\n\r"); + } + + //INFO_PRINT( + // "[Link local task] Data received, len = %d, flags= %x\n\r", + // netAppRequest->requestData.PayloadLen, + // netAppRequest->requestData.Flags); + + httpPostHandler(netAppRequest); + } + + if(netAppRequest->requestData.MetadataLen > 0) + { + free (netAppRequest->requestData.pMetadata); + } + if(netAppRequest->requestData.PayloadLen > 0) + { + free (netAppRequest->requestData.pPayload); + } + + free (netAppRequest); + } +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c new file mode 100644 index 0000000000..50354c154a --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c @@ -0,0 +1,1546 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/* standard includes */ +#include +#include + +/* driverlib Header files */ +#include +#include +#include + +/* TI-DRIVERS Header files */ +#include +#include +#include +#include +#include + +/* Example/Board Header files */ +#include +#include +#include +// #include "platform.h" +// #include "ota_archive.h" + +/* POSIX Header files */ +#include +#include + +/* In msecs. Used to detect good/bad sl_start() */ +#define ASYNC_EVT_TIMEOUT (5000) +/*In sec. Used for connecting to stored profile */ +#define PROFILE_ASYNC_EVT_TIMEOUT (5) +#define LED_TOGGLE_CONFIGURATION_TIMEOUT (1000) /* In msecs */ +#define LED_TOGGLE_CONFIRMATION_TIMEOUT (500) /* In msecs */ +#define LED_TOGGLE_CONNECTION_TIMEOUT (250) /* In msecs */ +/* Provisioning inactivity timeout in seconds */ +#define PROVISIONING_INACTIVITY_TIMEOUT (600) + +#define ROLE_SELECTION_BY_SL (0xFF) + + +/*! + * \brief Provisioning modes + */ +typedef enum +{ + PrvsnMode_AP, /* AP provisioning (AP role) */ + PrvsnMode_SC, /* Smart Config provisioning (STA role) */ + PrvsnMode_APSC /* AP + Smart Config provisioning (AP role) */ +}PrvsnMode; + +/** By default, setting the provisioning mode to AP + Smart Config. + * Other values could be PrvsnMode_SC or PrvsnMode_AP + */ +#define PROVISIONING_MODE PrvsnMode_APSC + +/*! + * \brief Provisioning status + */ +typedef enum +{ + PrvsnStatus_Stopped, + PrvsnStatus_InProgress +}PrvsnStatus; + +/* + * \brief Application state's context + */ +typedef struct _Provisioning_AppContext_t_ +{ + PrvnState currentState; /* Current state of provisioning */ + uint32_t pendingEvents; /* Events pending to be processed */ +/* SimpleLink's role - STATION/AP/P2P */ + uint8_t role; +/* SimpleLink's default role, try not to change this */ + uint8_t defaultRole; + PrvsnMode provisioningMode; /* Provisioning Mode */ + PrvsnStatus provisioningStatus; /* */ + + uint32_t asyncEvtTimeout; /* Timeout value*/ + + uint32_t ledToggleTimeout; /* Timeout value */ +}Provisioning_AppContext; + +/*! + * \brief Function pointer to the event handler + */ +typedef int32_t (*fptr_EventHandler)(void); + +/*! + * \brief Entry in the lookup table + */ +typedef struct +{ + fptr_EventHandler p_evtHndl; /* Pointer to the event handler */ + PrvnState nextState; /* Next state of provisioning */ +}s_TblEntry; + + + +/**************************************************************************** + LOCAL FUNCTION PROTOTYPES +****************************************************************************/ + +//***************************************************************************** +// +//! \brief This function initializes provisioning process +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void provisioningInit(void); + +//***************************************************************************** +// +//! \brief This function starts provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t provisioningStart(void); + +//***************************************************************************** +// +//! \brief main provisioning loop +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t provisioningAppTask(void); + +//***************************************************************************** +//! \brief This function puts the device in its default state. It: +//! - Set the mode to AP +//! - Configures connection policy to Auto +//! - Deletes all the stored profiles +//! - Enables DHCP +//! - Disable IPV6 +//! - Disables Scan policy +//! - Sets Tx power to maximum +//! - Sets power policy to normal +//! - Unregister mDNS services +//! - Remove all filters +//! +//! IMPORTANT NOTE - This is an example reset function, user must +//! update this function to match the application settings. +//! +//! \param none +//! \return On success, zero is returned. On error, negative is returned +//***************************************************************************** +static int32_t ConfigureSimpleLinkToDefaultState(void); + +//***************************************************************************** +// +//! \brief This function starts the SimpleLink in the configured role. +//! The device notifies the host asynchronously +//! when the initialization is +//! completed +//! +//! \param[in] role Device shall be configured in this role +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t InitSimplelink(uint8_t const role); + +//***************************************************************************** +// +//! \brief This function handles 'APP_EVENT_STARTED' event +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t HandleStrtdEvt(void); + +//***************************************************************************** +// +//! \brief This function starts the async-event timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t StartAsyncEvtTimer(uint32_t timeout); + +//***************************************************************************** +// +//! \brief This function stops the async-event timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t StopAsyncEvtTimer(void); + +//***************************************************************************** +// +//! \brief internal error detection during provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportError(void); + +//***************************************************************************** +// +//! \brief internal report current state during provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportSM(void); + +//***************************************************************************** +// +//! \brief steps following a successful provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportSuccess(void); + +//***************************************************************************** +// +//! \brief wait for connection following a successful provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t WaitForConn(void); + +//***************************************************************************** +// +//! \brief checks for local link connecion to peer device +//! when set as Station, checks for AP connection +//! when set as Access Point, no check is required +//! +//! \param[out] deviceRole role of the device +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t validateLocalLinkConnection(SlWlanMode_e *deviceRole); + +//***************************************************************************** +// +//! Notify if device return to factory image +//! +//! \param None +//! +//! \return None +// +//***************************************************************************** +static void NotifyReturnToFactoryImage(void); + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ +/*! + * \brief Application state's context + */ +Provisioning_AppContext gAppCtx; + +timer_t gAsyncEventTimer; +timer_t gLedTimer; +/*! + * \brief Application lookup/transition table + */ +const s_TblEntry gProvisioningTransitionTable[PrvnState_Max][PrvnEvent_Max] = +{ + /* PrvnState_Init */ + { + /* Event: PrvnEvent_Triggered */ + {provisioningStart, PrvnState_Idle }, + /* Event: PrvnEvent_Started */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_StartFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationSuccess */ + /* special case where confirmation is received after application is + restarted and NWP is still in provisioning */ + {ReportSM, PrvnState_Completed }, + /* in this case, need to move to COMPLETED state */ + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Stopped */ + /* in case of auto provisioning */ + {ReportSM, PrvnState_Init }, + /* Event: PrvnEvent_WaitForConn */ + {ReportSM, PrvnState_Error }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + }, + /* PrvnState_Idle */ + { + /* Event: PrvnEvent_Triggered */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Started */ + {HandleStrtdEvt, PrvnState_WaitForConfirmation }, + /* Event: PrvnEvent_StartFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationSuccess */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Stopped */ + {ReportSM, PrvnState_Init }, + /* Event: PrvnEvent_WaitForConn */ + {ReportSM, PrvnState_Error }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + }, + /* PrvnState_WaitForConfirmation */ + { + /* Event: PrvnEvent_Triggered */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Started */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_StartFailed */ + {ReportSM, PrvnState_Idle }, + /* Event: PrvnEvent_ConfirmationSuccess */ + {ReportSM, PrvnState_Completed }, + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportSM, PrvnState_WaitForConfirmation }, + /* Event: PrvnEvent_Stopped */ + {ReportSM, PrvnState_Init }, + /* Event: PrvnEvent_WaitForConn */ + {ReportSM, PrvnState_Error }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + }, + /* PrvnState_Completed */ + { + /* Event: PrvnEvent_Triggered */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Started */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_StartFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationSuccess */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Stopped */ + {ReportSuccess, PrvnState_Init }, + /* Event: PrvnEvent_WaitForConn */ + /* this state should cover cases where + feedback failed but profile exists */ + {WaitForConn, PrvnState_Init }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + }, + /* PrvnState_Error */ + { + /* Event: PrvnEvent_Triggered */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Started */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_StartFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationSuccess */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Stopped */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_WaitForConn */ + {ReportSM, PrvnState_Error }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + } +}; + +Provisioning_CB Provisioning_ControlBlock; + +/***************************************************************************** + Callback Functions +*****************************************************************************/ + +//***************************************************************************** +// +//! \brief The device init callback +//! +//! \param[in] status Mode the device is configured in +//! +//! \return None +//! +//**************************************************************************** +void SimpleLinkInitCallback(uint32_t status, + SlDeviceInitInfo_t *DeviceInitInfo) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + // UART_PRINT("[Provisioning task] Device started in %s role\n\r", + // (0 == status) ? "Station" : \ + // ((2 == status) ? "AP" : "P2P")); + + /** While provisioning is ongoing, the appropriate role is choosen by the + * device itself, and host can remain agnostic to these details + */ + if(pCtx->role == ROLE_SELECTION_BY_SL) + { + SignalProvisioningEvent(PrvnEvent_Started); + } + else + { + /* Either trigger an error/started event here */ + if(pCtx->role == status) + { + SignalProvisioningEvent(PrvnEvent_Started); + } + else + { + // UART_PRINT("[Provisioning task] But the intended role is %s \n\r", \ + // (0 == pCtx->role) ? "Station" : \ + // ((2 == pCtx->role) ? "AP" : "P2P")); + SignalProvisioningEvent(PrvnEvent_Error); + } + } +} + +//***************************************************************************** +// +//! \brief The interrupt handler for the async-evt timer +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void AsyncEvtTimerIntHandler(sigval val) +{ + /* Clear the timer interrupt. */ + Platform_TimerInterruptClear(); + + /* One Shot */ + /* TBD - Check role for One-shot/periodic */ + StopAsyncEvtTimer(); + SignalProvisioningEvent(PrvnEvent_Timeout); +} + +//***************************************************************************** +// +//! \brief The interrupt handler for the LED timer +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void LedTimerIntHandler(sigval val) +{ + /* Clear the timer interrupt. */ + Platform_TimerInterruptClear(); + + GPIO_toggle(Board_GPIO_LED0); +} + +//***************************************************************************** +// Local Functions +//***************************************************************************** + +//***************************************************************************** +// +//! \brief This function initializes provisioning process +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void provisioningInit(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + Platform_TimerInit(AsyncEvtTimerIntHandler, &gAsyncEventTimer); + + /** By default, setting the provisioning mode to AP + Smart Config. + * Other values could be PrvsnMode_SC or PrvsnMode_AP + */ + pCtx->provisioningMode = PROVISIONING_MODE; + switch(pCtx->provisioningMode) + { + case PrvsnMode_APSC: pCtx->defaultRole = ROLE_AP; + break; + + case PrvsnMode_AP: pCtx->defaultRole = ROLE_AP; + break; + + case PrvsnMode_SC: pCtx->defaultRole = ROLE_STA; + break; + } + + /* Provisioning has not started yet */ + pCtx->provisioningStatus = PrvsnStatus_Stopped; + pCtx->currentState = PrvnState_Init; +} + +//***************************************************************************** +// +//! \brief This function starts provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t provisioningStart(void) +{ + int32_t retVal = 0; + Provisioning_AppContext *const pCtx = &gAppCtx; + SlDeviceVersion_t ver = {0}; + uint8_t configOpt = 0; + uint16_t configLen = 0; + + /* check if provisioning is running */ + /* if auto provisioning - the command stops it automatically */ + /* in case host triggered provisioning - need to stop it explicitly */ + configOpt = SL_DEVICE_GENERAL_VERSION; + configLen = sizeof(ver); + retVal = + sl_DeviceGet(SL_DEVICE_GENERAL, &configOpt, &configLen, + (uint8_t *)(&ver)); + if(SL_RET_CODE_PROVISIONING_IN_PROGRESS == retVal) + { + // UART_PRINT( + // "[Provisioning task] Provisioning is already running," + // " stopping it...\r\n"); + retVal = + sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP,ROLE_STA,0,NULL, + 0); + + /* return SL_RET_CODE_PROVISIONING_IN_PROGRESS to indicate the SM + to stay in the same state*/ + return(SL_RET_CODE_PROVISIONING_IN_PROGRESS); + } + + /* + IMPORTANT NOTE - This is an example reset function, user must update + this function to match the application settings. + */ + retVal = ConfigureSimpleLinkToDefaultState(); + + if(retVal < 0) + { + // UART_PRINT( + // "[Provisioning task] Failed to configure the device in its default " + // "state \n\r"); + return(retVal); + } + + // UART_PRINT( + // "[Provisioning task] Device is configured \ + // in default state \n\r" ); + + /* Provisioning has not started yet */ + pCtx->provisioningStatus = PrvsnStatus_Stopped; + + /* Set the LED toggling timeout before starting the timer */ + pCtx->ledToggleTimeout = LED_TOGGLE_CONFIGURATION_TIMEOUT; + StartLedEvtTimer(pCtx->ledToggleTimeout); + + retVal = InitSimplelink(pCtx->defaultRole); + if(retVal < 0) + { + // UART_PRINT("[Provisioning task] Failed to initialize the device\n\r"); + return(retVal); + } + + return(retVal); +} + +//***************************************************************************** +// +//! \brief main provisioning loop +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t provisioningAppTask(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + s_TblEntry *pEntry = NULL; + uint16_t eventIdx = 0; + int32_t retVal = 0; + + for(eventIdx = 0; eventIdx < PrvnEvent_Max; eventIdx++) + { + if(0 != (pCtx->pendingEvents & (1 << eventIdx))) + { + if(eventIdx != PrvnEvent_Triggered) + { + /** Events received - Stop the respective timer if its still + * running + */ + StopAsyncEvtTimer(); + } + + pEntry = + (s_TblEntry *)&gProvisioningTransitionTable[pCtx->currentState] + [ + eventIdx]; + if(NULL != pEntry->p_evtHndl) + { + /* no state transition is required */ + retVal = pEntry->p_evtHndl(); + if(retVal == SL_RET_CODE_PROVISIONING_IN_PROGRESS) + { + pCtx->pendingEvents &= ~(1 << eventIdx); + continue; + } + else if(retVal < 0) + { + // UART_PRINT( + // "[Provisioning task]" + // " Event handler failed, error=%d\n\r", + // retVal); + while(1) /*this is to let other tasks recover by + mcu reset, e.g. in case of switching + to AP mode */ + { + usleep(1000); + } + } + } + + if(pEntry->nextState != pCtx->currentState) + { + pCtx->currentState = pEntry->nextState; + } + + pCtx->pendingEvents &= ~(1 << eventIdx); + } + + /* No more events to handle. Break.! */ + if(0 == pCtx->pendingEvents) + { + break; + } + } + + usleep(1000); + + return(0); +} + +//***************************************************************************** +//! \brief This function puts the device in its default state. It: +//! - Set the mode to AP +//! - Configures connection policy to Auto +//! - Deletes all the stored profiles +//! - Enables DHCP +//! - Disable IPV6 +//! - Disables Scan policy +//! - Sets Tx power to maximum +//! - Sets power policy to normal +//! - Unregister mDNS services +//! - Remove all filters +//! +//! IMPORTANT NOTE - This is an example reset function, user must +//! update this function to match the application settings. +//! +//! \param none +//! \return On success, zero is returned. On error, negative is returned +//***************************************************************************** +static int32_t ConfigureSimpleLinkToDefaultState(void) +{ + SlWlanRxFilterOperationCommandBuff_t RxFilterIdMask; + + uint8_t ucConfigOpt = 0; + uint16_t ifBitmap = 0; + uint8_t ucPower = 0; + + int32_t ret = -1; + int32_t mode = -1; + + memset(&RxFilterIdMask,0,sizeof(SlWlanRxFilterOperationCommandBuff_t)); + + /* Start Simplelink - Blocking mode */ + mode = sl_Start(0, 0, 0); + if(SL_RET_CODE_DEV_ALREADY_STARTED != mode) + { + ASSERT_ON_ERROR(mode); + } + + /* If the device is not in AP mode, try configuring it in AP mode + in case device is already started + (got SL_RET_CODE_DEV_ALREADY_STARTED error code), then mode would remain + -1 and in this case we do not know the role. Move to AP role anyway */ + if(ROLE_AP != mode) + { + /* Switch to AP role and restart */ + ret = sl_WlanSetMode(ROLE_AP); + ASSERT_ON_ERROR(ret); + + ret = sl_Stop(SL_STOP_TIMEOUT); + ASSERT_ON_ERROR(ret); + + ret = sl_Start(0, 0, 0); + ASSERT_ON_ERROR(ret); + + /* Check if the device is in AP again */ + if(ROLE_AP != ret) + { + return(ret); + } + } + + /* Set connection policy to Auto (no AutoProvisioning) */ + ret = sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION, + SL_WLAN_CONNECTION_POLICY(1, 0, 0, 0), NULL, 0); + ASSERT_ON_ERROR(ret); + + /* Remove all profiles */ + ret = sl_WlanProfileDel(0xFF); + ASSERT_ON_ERROR(ret); + + /* Enable DHCP client */ + ret = sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_DHCP,0,0); + ASSERT_ON_ERROR(ret); + + /* Disable IPV6 */ + ifBitmap = 0; + ret = + sl_NetCfgSet(SL_NETCFG_IF, SL_NETCFG_IF_STATE, sizeof(ifBitmap), + (uint8_t *)&ifBitmap); + ASSERT_ON_ERROR(ret); + + /* Disable scan */ + ucConfigOpt = SL_WLAN_SCAN_POLICY(0, 0); + ret = sl_WlanPolicySet(SL_WLAN_POLICY_SCAN, ucConfigOpt, NULL, 0); + ASSERT_ON_ERROR(ret); + + /* Set Tx power level for station mode + Number between 0-15, as dB offset from max power - 0 will + set max power */ + ucPower = 0; + ret = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, + SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER, 1, + (uint8_t *)&ucPower); + ASSERT_ON_ERROR(ret); + + /* Set PM policy to normal */ + ret = sl_WlanPolicySet(SL_WLAN_POLICY_PM, SL_WLAN_NORMAL_POLICY, NULL, 0); + ASSERT_ON_ERROR(ret); + + /* Unregister mDNS services */ + ret = sl_NetAppMDNSUnRegisterService(0, 0, 0); + ASSERT_ON_ERROR(ret); + + /* Remove all 64 filters (8*8) */ + memset(RxFilterIdMask.FilterBitmap, 0xFF, 8); + ret = sl_WlanSet(SL_WLAN_RX_FILTERS_ID, + SL_WLAN_RX_FILTER_REMOVE, + sizeof(SlWlanRxFilterOperationCommandBuff_t), + (uint8_t *)&RxFilterIdMask); + ASSERT_ON_ERROR(ret); + + ret = sl_Stop(SL_STOP_TIMEOUT); + ASSERT_ON_ERROR(ret); + + return(ret); +} + +//***************************************************************************** +// +//! \brief This function starts the SimpleLink in the configured role. +//! The device notifies the host asynchronously +//! when the initialization is +//! completed +//! +//! \param[in] role Device shall be configured in this role +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t InitSimplelink(uint8_t const role) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + int32_t retVal = -1; + + pCtx->role = role; + pCtx->pendingEvents = 0; + + retVal = sl_Start(0, 0, (P_INIT_CALLBACK)SimpleLinkInitCallback); + ASSERT_ON_ERROR(retVal); + + /* Start timer */ + pCtx->asyncEvtTimeout = ASYNC_EVT_TIMEOUT; + retVal = StartAsyncEvtTimer(pCtx->asyncEvtTimeout); + ASSERT_ON_ERROR(retVal); + + return(retVal); +} + +//***************************************************************************** +// +//! \brief This function handles 'APP_EVENT_STARTED' event +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** + +static int32_t HandleStrtdEvt(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + int32_t retVal = 0; + + /** If provisioning has already started, don't do anything here + * The state-machine shall keep waiting for the provisioning status + */ + if(PrvsnStatus_Stopped == pCtx->provisioningStatus) + { + SlDeviceVersion_t firmwareVersion = {0}; + + uint8_t ucConfigOpt = 0; + uint16_t ucConfigLen = 0; + + /* Get the device's version-information */ + ucConfigOpt = SL_DEVICE_GENERAL_VERSION; + ucConfigLen = sizeof(firmwareVersion); + retVal = sl_DeviceGet(SL_DEVICE_GENERAL, &ucConfigOpt, \ + &ucConfigLen, + (unsigned char *)(&firmwareVersion)); + ASSERT_ON_ERROR(retVal); + + // UART_PRINT("[Provisioning task] Host Driver Version: %s\n\r", + // SL_DRIVER_VERSION); + // UART_PRINT( + // "[Provisioning task] Build Version " + // "%d.%d.%d.%d.31.%d.%d.%d.%d.%d.%d.%d.%d\n\r", \ + // firmwareVersion.NwpVersion[0], \ + // firmwareVersion.NwpVersion[1], \ + // firmwareVersion.NwpVersion[2], \ + // firmwareVersion.NwpVersion[3], \ + // firmwareVersion.FwVersion[0], \ + // firmwareVersion.FwVersion[1], \ + // firmwareVersion.FwVersion[2], \ + // firmwareVersion.FwVersion[3], \ + // firmwareVersion.PhyVersion[0], \ + // firmwareVersion.PhyVersion[1], \ + // firmwareVersion.PhyVersion[2], \ + // firmwareVersion.PhyVersion[3]); + + /* Start provisioning process */ + // UART_PRINT("[Provisioning task] Starting Provisioning - "); + // UART_PRINT( + // "[Provisioning task] in mode %d (0 = AP, 1 = SC, 2 = AP+SC)\r\n", + // pCtx->provisioningMode); + + retVal = sl_WlanProvisioning(pCtx->provisioningMode, ROLE_STA, + PROVISIONING_INACTIVITY_TIMEOUT, NULL,0); + ASSERT_ON_ERROR(retVal); + + pCtx->provisioningStatus = PrvsnStatus_InProgress; + // UART_PRINT( + // "[Provisioning task] Provisioning Started. Waiting to " + // "be provisioned..!! \r\n"); + } + + return(retVal); +} + +//***************************************************************************** +// +//! \brief This function starts the async-event timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t StartAsyncEvtTimer(uint32_t timeout) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + pCtx->asyncEvtTimeout = timeout; + Platform_TimerStart(pCtx->asyncEvtTimeout, gAsyncEventTimer, 0); + return(0); +} + +//***************************************************************************** +// +//! \brief This function stops the async-event timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t StopAsyncEvtTimer(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + if(0 != pCtx->asyncEvtTimeout) + { + Platform_TimerStop(gAsyncEventTimer); + pCtx->asyncEvtTimeout = 0; + } + + return(0); +} + +//***************************************************************************** +// +//! \brief internal error detection during provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportError(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + uint16_t eventIdx = 0; + + for(eventIdx = 0; eventIdx < PrvnEvent_Max; eventIdx++) + { + if(0 != (pCtx->pendingEvents & (1 << eventIdx))) + { + break; + } + } + + // UART_PRINT("[Provisioning task]" + // " Unexpected SM: State = %d, Event = %d\n\r",\ + // pCtx->currentState, eventIdx); + return(-1); +} + +//***************************************************************************** +// +//! \brief internal report current state during provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportSM(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + uint16_t eventIdx = 0; + + for(eventIdx = 0; eventIdx < PrvnEvent_Max; eventIdx++) + { + if(0 != (pCtx->pendingEvents & (1 << eventIdx))) + { + break; + } + } + + if(PrvnEvent_Stopped == eventIdx) + { + StopLedEvtTimer(); + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + } + + return(0); +} + +//***************************************************************************** +// +//! \brief steps following a successful provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportSuccess(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + uint16_t ConfigOpt; + uint16_t ipLen; + SlNetCfgIpV4Args_t ipV4 = {0}; + int32_t retVal; + + // UART_PRINT("[Provisioning task] " + // "Provisioning completed successfully..!\n\r"); + pCtx->provisioningStatus = PrvsnStatus_Stopped; + StopLedEvtTimer(); + + /* Get the device's IP address */ + ipLen = sizeof(SlNetCfgIpV4Args_t); + ConfigOpt = 0; + retVal = + sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&ipLen, + (uint8_t *)&ipV4); + if(retVal == 0) + { + // UART_PRINT("[Provisioning task] IP address is %d.%d.%d.%d\n\r", \ + // SL_IPV4_BYTE(ipV4.Ip,3), \ + // SL_IPV4_BYTE(ipV4.Ip,2), \ + // SL_IPV4_BYTE(ipV4.Ip,1), \ + // SL_IPV4_BYTE(ipV4.Ip,0)); + } + + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + + /* signal to linklocal task */ + sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); + + /* signal to report server task */ + sem_post(&Provisioning_ControlBlock.provisioningConnDoneToOtaServerSignal); + + return(0); +} + +//***************************************************************************** +// +//! \brief wait for connection following a successful provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t WaitForConn(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + struct timespec ts; + int32_t retVal; + + // while(((!IS_IPV6L_ACQUIRED(OutOfBox_ControlBlock.status) || + // !IS_IPV6G_ACQUIRED(OutOfBox_ControlBlock.status)) && + // !IS_IP_ACQUIRED(OutOfBox_ControlBlock.status)) || + // !IS_CONNECTED(OutOfBox_ControlBlock.status)) + // { + // clock_gettime(CLOCK_REALTIME, &ts); + // ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; + + // retVal = sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, + // &ts); + // /* freertos return -1 in case of timeout */ + // if((retVal == 116) || (retVal == -1)) + // { + // UART_PRINT( + // "[Provisioning task] Cannot connect to AP or profile does" + // " not exist\n\r"); + // GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + // /* this state is set so that PrvnEvent_Triggered + // would invoke provisioning again */ + // pCtx->currentState = PrvnState_Init; + // SignalProvisioningEvent(PrvnEvent_Triggered); + + // return(0); + // } + // } + + // UART_PRINT("[Provisioning task] Connection to AP succeeded\n\r"); + + return(ReportSuccess()); +} + +//***************************************************************************** +// +//! \brief checks for local link connecion to peer device +//! when set as Station, checks for AP connection +//! when set as Access Point, no check is required +//! +//! \param[out] deviceRole role of the device +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t validateLocalLinkConnection(SlWlanMode_e *deviceRole) +{ + uint16_t ConfigOpt; + uint16_t ipLen; + SlNetCfgIpV4Args_t ipV4 = {0}; + int32_t retVal; + uint32_t ocpRegVal; + + struct timespec ts; + + retVal = sl_Start(0, 0, 0); + /* when calibration fails, reboot is required */ + if(SL_ERROR_CALIB_FAIL == retVal) + { + mcuReboot(); + } + else + { + ASSERT_ON_ERROR(retVal); + } + + // /* if in AP role + // * 1) check OCP register value + // * 2) if set, it means user set AP mode via switch. + // * check for IP_ACQUIRED to indicate NWP is running + // * 4) if not set, procede with STATION role + // */ + // if(retVal == ROLE_AP) + // { + // *deviceRole = ROLE_AP; + // ocpRegVal = MAP_PRCMOCRRegisterRead(OCP_REGISTER_INDEX); + // ocpRegVal &= (1 << OCP_REGISTER_OFFSET); + // if(ocpRegVal) + // { + // if(IS_IP_ACQUIRED(OutOfBox_ControlBlock.status)) + // { + // return(0); + // } + // else + // { + // clock_gettime(CLOCK_REALTIME, &ts); + // ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; + + // retVal = sem_timedwait( + // &Provisioning_ControlBlock.connectionAsyncEvent, &ts); + // /* freertos return -1 in case of timeout */ + // if((retVal == 116) || (retVal == -1)) + // { + // UART_PRINT( + // "[Provisioning task] AP role failed to initialize\n\r"); + // GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + // retVal = -1; + // } + // return(retVal); + // } + // } + // } + + // if(retVal != ROLE_STA) + // { + // retVal = sl_WlanSetMode(ROLE_STA); + // ASSERT_ON_ERROR(retVal); + + // retVal = sl_Stop(SL_STOP_TIMEOUT); + // ASSERT_ON_ERROR(retVal); + + // retVal = sl_Start(0, 0, 0); + // if(retVal < 0 || (retVal != ROLE_STA)) + // { + // ASSERT_ON_ERROR(retVal); + // } + // UART_PRINT("[Provisioning task] Device started as STATION \n\r"); + // } + + // *deviceRole = ROLE_STA; + + // while(((!IS_IPV6L_ACQUIRED(OutOfBox_ControlBlock.status) || + // !IS_IPV6G_ACQUIRED(OutOfBox_ControlBlock.status)) && + // !IS_IP_ACQUIRED(OutOfBox_ControlBlock.status)) || + // !IS_CONNECTED(OutOfBox_ControlBlock.status)) + // { + // clock_gettime(CLOCK_REALTIME, &ts); + // ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; + + // retVal = sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, + // &ts); + // /* freertos return -1 in case of timeout */ + // if((retVal == 116) || (retVal == -1)) + // { + // UART_PRINT( + // "[Provisioning task] Cannot connect to AP or" + // " profile does not exist\n\r"); + // GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + // retVal = -1; + + // return(retVal); + // } + // } + + // UART_PRINT("[Provisioning task] Connection to AP succeeded\n\r"); + + // /* Get the device's IP address */ + // ipLen = sizeof(SlNetCfgIpV4Args_t); + // ConfigOpt = 0; + // sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&ipLen, + // (uint8_t *)&ipV4); + // if(retVal < 0) + // { + // return(retVal); + // } + + // UART_PRINT("[Provisioning task] IP address is %d.%d.%d.%d\n\r", \ + // SL_IPV4_BYTE(ipV4.Ip,3), \ + // SL_IPV4_BYTE(ipV4.Ip,2), \ + // SL_IPV4_BYTE(ipV4.Ip,1), \ + // SL_IPV4_BYTE(ipV4.Ip,0)); + + return(0); +} + +//***************************************************************************** +// +//! Notify if device return to factory image +//! +//! \param None +//! +//! \return None +// +//***************************************************************************** +static void NotifyReturnToFactoryImage(void) +{ + if(((HWREG(HIB3P3_BASE + 0x00000418) & (1 << 7)) != 0) && + ((HWREG(0x4402F0C8) & 0x01) != 0)) + { + // UART_PRINT("Return To Factory Image successful, Do a power cycle(POR)" + // " of the device using switch SW1-Reset\n\r"); + while(1) + { + ; + } + } +} + +//**************************************************************************** +// MAIN FUNCTION +//**************************************************************************** + +//***************************************************************************** +// +//! \brief This function signals the application events +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int16_t SignalProvisioningEvent(PrvnEvent event) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + pCtx->pendingEvents |= (1 << event); + + return(0); +} + +//***************************************************************************** +// +//! \brief This function gets the current provisioning state +//! +//! \param[in] None +//! +//! \return provisioning state +//! +//**************************************************************************** +PrvnState GetProvisioningState() +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + return(pCtx->currentState); +} + +//***************************************************************************** +// +//! \brief This function starts the led toggling timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t StartLedEvtTimer(uint32_t timeout) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + pCtx->ledToggleTimeout = timeout; + Platform_TimerStart(pCtx->ledToggleTimeout, gLedTimer, 1); + + return(0); +} + +//***************************************************************************** +// +//! \brief This function stops the led toggling timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t StopLedEvtTimer(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + if(0 != pCtx->ledToggleTimeout) + { + Platform_TimerStop(gLedTimer); + pCtx->ledToggleTimeout = 0; + } + + return(0); +} + +//***************************************************************************** +// +//! \brief This function stops provisioning process +//! +//! \param[in] None +//! +//! \return SL_RET_CODE_PROVISIONING_IN_PROGRESS if provisioning was running, +//! otherwise 0 +//! +//**************************************************************************** +int32_t provisioningStop(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + int32_t retVal; + PrvnState provisioningState; + SlDeviceVersion_t ver = {0}; + uint8_t configOpt = 0; + uint16_t configLen = 0; + + /* check if provisioning is running */ + configOpt = SL_DEVICE_GENERAL_VERSION; + configLen = sizeof(ver); + retVal = + sl_DeviceGet(SL_DEVICE_GENERAL, &configOpt, &configLen, + (uint8_t *)(&ver)); + if(SL_RET_CODE_PROVISIONING_IN_PROGRESS == retVal) + { + // UART_PRINT( + // "[Provisioning task] Provisioning is already running, " + // "stopping it...\r\n"); + retVal = + sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP,ROLE_STA,0,NULL, + 0); + + /* wait for the stopped event to arrive - wait for PrvnState_Init */ + do + { + provisioningState = GetProvisioningState(); + usleep(1000); + } + while(provisioningState != PrvnState_Init); + + pCtx->provisioningStatus = PrvsnStatus_Stopped; + + retVal = SL_RET_CODE_PROVISIONING_IN_PROGRESS; + } + else if(retVal < 0) + { + return(retVal); + } + else + { + retVal = 0; + } + + return(retVal); +} + +//***************************************************************************** +// +//! \brief This is the main provisioning task +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void * provisioningTask(void *pvParameters) +{ + int32_t retVal = -1; + Provisioning_AppContext *const pCtx = &gAppCtx; + SlWlanMode_e deviceRole; + SlFsControl_t FsControl; + int32_t status; + + /* Check the wakeup source. If first time entry or wakeup from HIB */ + if(MAP_PRCMSysResetCauseGet() == 0) + { + //UART_PRINT("[Provisioning task] Wake up on Power ON\n\r"); + } + else if(MAP_PRCMSysResetCauseGet() == PRCM_HIB_EXIT) + { + //UART_PRINT("[Provisioning task] Woken up from Hibernate\n\r"); + } + + /* + Following function first try to connect to a stored profile. + If fails, it first configure the device to default state by cleaning + the persistent settings stored in NVMEM (viz. connection profiles & + policies, power policy etc) + + Applications may choose to skip this step if the developer is sure + that the device is in its desired state at start of applicaton + + Note that all profiles and persistent settings that were done on the + device will be lost */ + + /* initialize one-time parameters for provisioning */ + provisioningInit(); + + /* Configure Provisioning Toggle LED */ + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + + Platform_TimerInit(LedTimerIntHandler, &gLedTimer); + + /* Set the LED toggling timeout before starting the timer */ + pCtx->ledToggleTimeout = LED_TOGGLE_CONFIRMATION_TIMEOUT; + + StartLedEvtTimer(pCtx->ledToggleTimeout); + + /* check whether return-to-default occured */ + NotifyReturnToFactoryImage(); + + /* 1) try to connect to a stored profile if in STATION mode + * 2) if successful, procede and validate ota bundle and then try to connect + to cloud + * 3) if unsuccessful when in STATION mode, procede to provisioning + * 4) if in AP mode, procede and validate ota bundle + */ + retVal = validateLocalLinkConnection(&deviceRole); + getDeviceType(); + /* at this point, provisioning has not started yet, unless auto provisioning + is running */ + /* in this case, if provisioning from mobile app is running, it would not be + possible to send most of the commands to the device */ + /* need to stop provisioning */ + provisioningStop(); + + StopLedEvtTimer(); + + /* 1) in case coming from ota procedure, a profile should reside on serial + flash and connect immediately + * 2) check if pending commit and set commit the bundle + * 3) On failure, reset the MCU to rollback */ +/* it means OtaArchive is in + SL_FS_BUNDLE_STATE_PENDING_COMMIT */ + // if(OtaArchive_GetPendingCommit()) + // {/* validation of new ota bundle failed, + // reverting to previous bundle */ + // if(retVal != 0) + // { + // /* rollback is not required for production devices + // - but it is not harmfull */ + // FsControl.IncludeFilters = 0; + // status = + // sl_FsCtl(SL_FS_CTL_BUNDLE_ROLLBACK, 0, NULL, + // (uint8_t *)&FsControl, + // sizeof(SlFsControl_t), NULL, 0, + // NULL); + // if(status < 0) + // { + // //UART_PRINT( + // // "[Provisioning task] Rollback error sl_FsCtl, status=%d\n\r", + // // status); + // } + + // mcuReboot(); + // } + // /* validation of new ota bundle succeeded, + // commit the new ota bundle */ + // else + // { + // //UART_PRINT( + // // "[Provisioning task] committing new ota download... \n\r"); + // if(OtaArchive_Commit() < 0) + // { + // //UART_PRINT( + // // "[Provisioning task] failed to commit new download, " + // // "reverting to previous copy by reseting the device \n\r"); + // mcuReboot(); + // } + // //UART_PRINT("[Provisioning task] commit succeeded \n\r"); + + // /* need to stop the WDT so MCU is not reset */ + // PowerCC32XX_reset(PowerCC32XX_PERIPH_WDT); + // } + // } + + if(deviceRole == ROLE_STA) + { + /* it means a connection to AP has been established, + no need to trigger provisioning */ + if(retVal == 0) + { + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + + /* signal to linklocal task */ + sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); + + /* signal to report server task */ + sem_post( + &Provisioning_ControlBlock. + provisioningConnDoneToOtaServerSignal); + } + /* it means a connection to AP failed, trigger provisioning */ + else if(retVal < 0) + { + SignalProvisioningEvent(PrvnEvent_Triggered); + } + } +/* it means device is initialized as AP, no need to trigger provisioning */ + if((retVal == 0) && (deviceRole == ROLE_AP)) + { + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + + /* signal to linklocal task */ + sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); + + /* signal to report server task */ + sem_post( + &Provisioning_ControlBlock.provisioningConnDoneToOtaServerSignal); + } + + do + { + retVal = provisioningAppTask(); + } + while(!retVal); /* Exit on failure */ + + return(0); +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c new file mode 100644 index 0000000000..343188ca31 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -0,0 +1,1178 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +/* POSIX Header files */ +#include +#include + +/* RTOS header files */ +#include "FreeRTOS.h" +#include "task.h" + +/* TI-RTOS Header files */ +#include + +/* Example/Board Header files */ +#include "Board.h" +#include + +#include +#include +#include +#include +#include +#include +#include + +extern void * CLRStartupThread(void *arg0); +extern void * ReceiverThread(void *arg0); + +////////////////////////////// +#define SL_STOP_TIMEOUT (200) +#define APPLICATION_NAME "out of box" +#define APPLICATION_VERSION "1.00.00.09" + +#define SPAWN_TASK_PRIORITY (9) +#define TASK_STACK_SIZE (2048) + +////////////////////////////// + +/* Stack size in bytes */ +#define THREADSTACKSIZE 4096 + +pthread_t provisioningThread = (pthread_t)NULL; +pthread_t slThread = (pthread_t)NULL; +pthread_t receiverThread = (pthread_t)NULL; +pthread_t nanoCLRThread = (pthread_t)NULL; + +nanoFramework_CB nF_ControlBlock; + +/***************************************************************************** + Callback Functions +*****************************************************************************/ + +//***************************************************************************** +// +//! The Function Handles WLAN Events +//! +//! \param[in] pWlanEvent - Pointer to WLAN Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) +{ + switch(pWlanEvent->Id) + { + case SL_WLAN_EVENT_CONNECT: + { + SET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6gAcquired); + + /* + Information about the connected AP (like name, MAC etc) will be + available in 'slWlanConnectAsyncResponse_t'-Applications + can use it if required: + + slWlanConnectAsyncResponse_t *pEventData = NULL; + pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected; + */ + + /* Copy new connection SSID and BSSID to global parameters */ + // memcpy(nF_ControlBlock.connectionSSID, + // pWlanEvent->Data.Connect.SsidName, + // pWlanEvent->Data.Connect.SsidLen); + + // nF_ControlBlock.ssidLen = pWlanEvent->Data.Connect.SsidLen; + + // memcpy(nF_ControlBlock.connectionBSSID, + // pWlanEvent->Data.Connect.Bssid, + // SL_WLAN_BSSID_LENGTH); + + //UART_PRINT( + // "[WLAN EVENT] STA Connected to the AP: %s ," + // "BSSID: %x:%x:%x:%x:%x:%x\n\r", + // nF_ControlBlock.connectionSSID, + // nF_ControlBlock.connectionBSSID[0], + // nF_ControlBlock.connectionBSSID[1], + // nF_ControlBlock.connectionBSSID[2], + // nF_ControlBlock.connectionBSSID[3], + // nF_ControlBlock.connectionBSSID[4], + // nF_ControlBlock.connectionBSSID[5]); + + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + } + break; + + case SL_WLAN_EVENT_DISCONNECT: + { + SlWlanEventDisconnect_t* pEventData = NULL; + + CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6gAcquired); + + pEventData = &pWlanEvent->Data.Disconnect; + + /* If the user has initiated 'Disconnect' request, + 'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED. + */ + if(SL_WLAN_DISCONNECT_USER_INITIATED == pEventData->ReasonCode) + { + //UART_PRINT( + // "[WLAN EVENT]Device disconnected from the " + // "AP: %s, BSSID: %x:%x:%x:%x:%x:%x " + // "on application's request \n\r", + // nF_ControlBlock.connectionSSID, + // nF_ControlBlock.connectionBSSID[0], + // nF_ControlBlock.connectionBSSID[1], + // nF_ControlBlock.connectionBSSID[2], + // nF_ControlBlock.connectionBSSID[3], + // nF_ControlBlock.connectionBSSID[4], + // nF_ControlBlock.connectionBSSID[5]); + } + else + { + //UART_PRINT( + // "[WLAN ERROR]Device disconnected from the AP AP: %s," + // "BSSID: %x:%x:%x:%x:%x:%x on an ERROR..!! \n\r", + // nF_ControlBlock.connectionSSID, + // nF_ControlBlock.connectionBSSID[0], + // nF_ControlBlock.connectionBSSID[1], + // nF_ControlBlock.connectionBSSID[2], + // nF_ControlBlock.connectionBSSID[3], + // nF_ControlBlock.connectionBSSID[4], + // nF_ControlBlock.connectionBSSID[5]); + } + // memset(nF_ControlBlock.connectionSSID, 0, + // sizeof(nF_ControlBlock.connectionSSID)); + // memset(nF_ControlBlock.connectionBSSID, 0, + // sizeof(nF_ControlBlock.connectionBSSID)); + } + break; + + case SL_WLAN_EVENT_STA_ADDED: + { + //UART_PRINT( + // "[WLAN EVENT] External Station connected to SimpleLink AP\r\n"); + + //UART_PRINT("[WLAN EVENT] STA BSSID: %02x:%02x:%02x:%02x:%02x:%02x\r\n", + // pWlanEvent->Data.STAAdded.Mac[0], + // pWlanEvent->Data.STAAdded.Mac[1], + // pWlanEvent->Data.STAAdded.Mac[2], + // pWlanEvent->Data.STAAdded.Mac[3], + // pWlanEvent->Data.STAAdded.Mac[4], + // pWlanEvent->Data.STAAdded.Mac[5]); + } + break; + + case SL_WLAN_EVENT_STA_REMOVED: + { + //UART_PRINT( + // "[WLAN EVENT] External Station disconnected from SimpleLink AP\r\n"); + } + break; + + case SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED: + { + //UART_PRINT("[WLAN EVENT] Profile Added\r\n"); + } + break; + + case SL_WLAN_EVENT_PROVISIONING_STATUS: + { + uint16_t status = + pWlanEvent->Data.ProvisioningStatus.ProvisioningStatus; + switch(status) + { + case SL_WLAN_PROVISIONING_GENERAL_ERROR: + case SL_WLAN_PROVISIONING_ERROR_ABORT: + { + //UART_PRINT("[WLAN EVENT] Provisioning Error status=%d\r\n",status); + // SignalProvisioningEvent(PrvnEvent_Error); + } + break; + case SL_WLAN_PROVISIONING_ERROR_ABORT_INVALID_PARAM: + case SL_WLAN_PROVISIONING_ERROR_ABORT_HTTP_SERVER_DISABLED: + case SL_WLAN_PROVISIONING_ERROR_ABORT_PROFILE_LIST_FULL: + { + //UART_PRINT("[WLAN EVENT] Provisioning Error status=%d\r\n",status); + // SignalProvisioningEvent(PrvnEvent_StartFailed); + } + break; + case SL_WLAN_PROVISIONING_ERROR_ABORT_PROVISIONING_ALREADY_STARTED: + { + //UART_PRINT("[WLAN EVENT] Provisioning already started"); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_NETWORK_NOT_FOUND: + { + //UART_PRINT("[WLAN EVENT] Confirmation fail: network not found\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_CONNECTION_FAILED: + { + //UART_PRINT("[WLAN EVENT] Confirmation fail: Connection failed\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; + + case + SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_CONNECTION_SUCCESS_IP_NOT_ACQUIRED + : + { + //UART_PRINT( + // "[WLAN EVENT] Confirmation fail: IP address not acquired\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS_FEEDBACK_FAILED: + { + //UART_PRINT( + // "[WLAN EVENT] Connection Success " + // "(feedback to Smartphone app failed)\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS: + { + //UART_PRINT("[WLAN EVENT] Confirmation Success!\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationSuccess); + } + break; + + case SL_WLAN_PROVISIONING_AUTO_STARTED: + { + //UART_PRINT("[WLAN EVENT] Auto-Provisioning Started\r\n"); + /* stop auto provisioning - + may trigger in case of returning to default */ + // SignalProvisioningEvent(PrvnEvent_Stopped); + } + break; + + case SL_WLAN_PROVISIONING_STOPPED: + { + //UART_PRINT("[WLAN EVENT] Provisioning stopped\r\n"); + if(ROLE_STA == pWlanEvent->Data.ProvisioningStatus.Role) + { + //UART_PRINT(" [WLAN EVENT] - WLAN Connection Status:%d\r\n", + // pWlanEvent->Data.ProvisioningStatus.WlanStatus); + + if(SL_WLAN_STATUS_CONNECTED == + pWlanEvent->Data.ProvisioningStatus.WlanStatus) + { + //UART_PRINT(" [WLAN EVENT] - Connected to SSID:%s\r\n", + // pWlanEvent->Data.ProvisioningStatus.Ssid); + + // memcpy (nF_ControlBlock.connectionSSID, + // pWlanEvent->Data.ProvisioningStatus.Ssid, + // pWlanEvent->Data.ProvisioningStatus.Ssidlen); + // nF_ControlBlock.ssidLen = + // pWlanEvent->Data.ProvisioningStatus.Ssidlen; + + /* Provisioning is stopped by the device and + provisioning is done successfully */ + // SignalProvisioningEvent(PrvnEvent_Stopped); + + break; + } + else + { + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6gAcquired); + + /* Provisioning is stopped by the device and provisioning + is not done yet, still need to connect to AP */ + // SignalProvisioningEvent(PrvnEvent_WaitForConn); + + break; + } + } + } + + // SignalProvisioningEvent(PrvnEvent_Stopped); + + break; + + case SL_WLAN_PROVISIONING_SMART_CONFIG_SYNCED: + { + //UART_PRINT("[WLAN EVENT] Smart Config Synced!\r\n"); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_WLAN_CONNECT: + { + SET_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6gAcquired); + + //UART_PRINT("[WLAN EVENT] Connection to AP succeeded\r\n"); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_IP_ACQUIRED: + { + SET_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_IpAcquired); + + //UART_PRINT("[WLAN EVENT] IP address acquired\r\n"); + } + break; + + case SL_WLAN_PROVISIONING_SMART_CONFIG_SYNC_TIMEOUT: + { + //UART_PRINT("[WLAN EVENT] Smart Config Sync timeout\r\n"); + } + break; + + default: + { + //UART_PRINT("[WLAN EVENT] Unknown Provisioning Status: %d\r\n", + // pWlanEvent->Data.ProvisioningStatus.ProvisioningStatus); + } + break; + } + } + break; + + default: + { + //UART_PRINT("[WLAN EVENT] Unexpected event [0x%x]\n\r", + // pWlanEvent->Id); + + // SignalProvisioningEvent(PrvnEvent_Error); + } + break; + } +} + +//***************************************************************************** +// +//! The Function Handles the Fatal errors +//! +//! \param[in] slFatalErrorEvent - Pointer to Fatal Error Event info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkFatalErrorEventHandler(SlDeviceFatal_t *slFatalErrorEvent) +{ + uint8_t msg = 4; + int32_t msgqRetVal; + + switch(slFatalErrorEvent->Id) + { + case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: + { + //UART_PRINT("[ERROR] - FATAL ERROR: Abort NWP event detected: " + // "AbortType=%d, AbortData=0x%x\n\r", + // slFatalErrorEvent->Data.DeviceAssert.Code, + // slFatalErrorEvent->Data.DeviceAssert.Value); + } + break; + + case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: + { + //UART_PRINT("[ERROR] - FATAL ERROR: Driver Abort detected. \n\r"); + } + break; + + case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: + { + //UART_PRINT("[ERROR] - FATAL ERROR: No Cmd Ack detected " + // "[cmd opcode = 0x%x] \n\r", + // slFatalErrorEvent->Data.NoCmdAck.Code); + } + break; + + case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: + { + //UART_PRINT("[ERROR] - FATAL ERROR: Sync loss detected n\r"); + } + break; + + case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: + { + //UART_PRINT("[ERROR] - FATAL ERROR: Async event timeout detected " + // "[event opcode =0x%x] \n\r", + // slFatalErrorEvent->Data.CmdTimeout.Code); + } + break; + + default: + //UART_PRINT("[ERROR] - FATAL ERROR: Unspecified error detected \n\r"); + break; + } + + // msgqRetVal = mq_send(controlMQueue, (char *)&msg, 1, 0); + // if(msgqRetVal < 0) + // { + // //UART_PRINT("[Control task] could not send element to msg queue\n\r"); + // while(1) + // { + // ; + // } + // } +} + +//***************************************************************************** +// +//! This function handles network events such as IP acquisition, IP +//! leased, IP released etc. +//! +//! \param[in] pNetAppEvent - Pointer to NetApp Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) +{ + SlNetAppEventData_u *pNetAppEventData = NULL; + + if(NULL == pNetAppEvent) + { + return; + } + + pNetAppEventData = &pNetAppEvent->Data; + + switch(pNetAppEvent->Id) + { + case SL_NETAPP_EVENT_IPV4_ACQUIRED: + { + SlIpV4AcquiredAsync_t *pEventData = NULL; + + SET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpAcquired); + + /* Ip Acquired Event Data */ + pEventData = &pNetAppEvent->Data.IpAcquiredV4; + + /* Gateway IP address */ + // nF_ControlBlock.gatewayIP = pEventData->Gateway; + + //UART_PRINT("[NETAPP EVENT] IP Acquired: IP=%d.%d.%d.%d , " + // "Gateway=%d.%d.%d.%d\n\r", + // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Ip,3), + // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Ip,2), + // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Ip,1), + // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Ip,0), + // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,3), + // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,2), + // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,1), + // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,0)); + + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + } + break; + + case SL_NETAPP_EVENT_IPV6_ACQUIRED: + { + if(!GET_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6lAcquired)) + { + SET_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6lAcquired); + //UART_PRINT("[NETAPP EVENT] Local IPv6 Acquired\n\r"); + } + else + { + SET_STATUS_BIT(nF_ControlBlock.status, + AppStatusBits_Ipv6gAcquired); + //UART_PRINT("[NETAPP EVENT] Global IPv6 Acquired\n\r"); + } + + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + } + break; + + case SL_NETAPP_EVENT_DHCPV4_LEASED: + { + SET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpLeased); + + //UART_PRINT( + // "[NETAPP EVENT] IPv4 leased %d.%d.%d.%d for " + // "device %02x:%02x:%02x:%02x:%02x:%02x\n\r", \ + // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpLeased.IpAddress,3), \ + // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpLeased.IpAddress,2), \ + // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpLeased.IpAddress,1), \ + // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpLeased.IpAddress,0), \ + // pNetAppEventData->IpLeased.Mac[0], \ + // pNetAppEventData->IpLeased.Mac[1], \ + // pNetAppEventData->IpLeased.Mac[2], \ + // pNetAppEventData->IpLeased.Mac[3], \ + // pNetAppEventData->IpLeased.Mac[4], \ + // pNetAppEventData->IpLeased.Mac[5]); + } + break; + + case SL_NETAPP_EVENT_DHCPV4_RELEASED: + { + CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpLeased); + + //UART_PRINT( + // "[NETAPP EVENT] IPv4 released %d.%d.%d.%d for " + // "device %02x:%02x:%02x:%02x:%02x:%02x\n\r", \ + // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpReleased.IpAddress, + // 3), \ + // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpReleased.IpAddress, + // 2), \ + // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpReleased.IpAddress, + // 1), \ + // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpReleased.IpAddress, + // 0), \ + // pNetAppEventData->IpReleased.Mac[0], \ + // pNetAppEventData->IpReleased.Mac[1], \ + // pNetAppEventData->IpReleased.Mac[2], \ + // pNetAppEventData->IpReleased.Mac[3], \ + // pNetAppEventData->IpReleased.Mac[4], \ + // pNetAppEventData->IpReleased.Mac[5]); + + //UART_PRINT("Reason: "); + switch(pNetAppEventData->IpReleased.Reason) + { + case SL_IP_LEASE_PEER_RELEASE: //UART_PRINT("Peer released\n\r"); + break; + + case SL_IP_LEASE_PEER_DECLINE: //UART_PRINT("Peer declined\n\r"); + break; + + case SL_IP_LEASE_EXPIRED: //UART_PRINT("Lease expired\n\r"); + break; + } + } + break; + + case SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT: + { + //UART_PRINT("[NETAPP EVENT] DHCP IPv4 Acquire timeout\n\r"); + } + break; + + default: + { + //UART_PRINT("[NETAPP EVENT] Unexpected event [0x%x] \n\r", + // pNetAppEvent->Id); + } + break; + } +} + +//***************************************************************************** +// +//! This function handles HTTP server events +//! +//! \param[in] pServerEvent - Contains the relevant event information +//! \param[in] pServerResponse - Should be filled by the user with the +//! relevant response information +//! +//! \return None +//! +//**************************************************************************** +void SimpleLinkHttpServerEventHandler(SlNetAppHttpServerEvent_t *pHttpEvent, + SlNetAppHttpServerResponse_t * + pHttpResponse) +{ + /* Unused in this application */ + //UART_PRINT("[HTTP SERVER EVENT] Unexpected HTTP server event \n\r"); +} + +//***************************************************************************** +// +//! This function handles General Events +//! +//! \param[in] pDevEvent - Pointer to General Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent) +{ + uint8_t msg = 4; + int32_t msgqRetVal; + + /* + Most of the general errors are not FATAL are are to be handled + appropriately by the application. + */ + if(NULL == pDevEvent) + { + return; + } + switch(pDevEvent->Id) + { + case SL_DEVICE_EVENT_RESET_REQUEST: + { + //UART_PRINT("[GENERAL EVENT] Reset Request Event\r\n"); + } + break; + + default: + { + //UART_PRINT("[GENERAL EVENT] - ID=[%d] Sender=[%d]\n\n", + // pDevEvent->Data.Error.Code, + // pDevEvent->Data.Error.Source); + + // msgqRetVal = mq_send(controlMQueue, (char *)&msg, 1, 0); + // if(msgqRetVal < 0) + // { + // //UART_PRINT("[Control task] could not send element to msg queue\n\r"); + // while(1) + // { + // ; + // } + // } + } + break; + } +} + +//***************************************************************************** +// +//! This function handles socket events indication +//! +//! \param[in] pSock - Pointer to Socket Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) +{ + if(SL_SOCKET_ASYNC_EVENT == pSock->Event) + { + //UART_PRINT("[SOCK ERROR] an event received on socket %d\r\n", + // pSock->SocketAsyncEvent.SockAsyncData.Sd); + switch(pSock->SocketAsyncEvent.SockAsyncData.Type) + { + case SL_SSL_NOTIFICATION_CONNECTED_SECURED: + //UART_PRINT("[SOCK ERROR] SSL handshake done"); + break; + case SL_SSL_NOTIFICATION_HANDSHAKE_FAILED: + //UART_PRINT("[SOCK ERROR] SSL handshake failed with error %d\r\n", + // pSock->SocketAsyncEvent.SockAsyncData.Val); + break; + case SL_SSL_ACCEPT: + //UART_PRINT( + // "[SOCK ERROR] Recoverable error occurred " + // "during the handshake %d\r\n", + // pSock->SocketAsyncEvent.SockAsyncData.Val); + break; + case SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED: + //UART_PRINT("[SOCK ERROR] Other peer terminated the SSL layer.\r\n"); + break; + case SL_SSL_NOTIFICATION_WRONG_ROOT_CA: + //UART_PRINT("[SOCK ERROR] Used wrong CA to verify the peer.\r\n"); + + break; + default: + break; + } + } + + /* This application doesn't work w/ socket - Events are not expected */ + switch(pSock->Event) + { + case SL_SOCKET_TX_FAILED_EVENT: + switch(pSock->SocketAsyncEvent.SockTxFailData.Status) + { + case SL_ERROR_BSD_ECLOSE: + //UART_PRINT("[SOCK ERROR] - close socket (%d) operation " + // "failed to transmit all queued packets\n\r", + // pSock->SocketAsyncEvent.SockTxFailData.Sd); + break; + default: + //UART_PRINT("[SOCK ERROR] - TX FAILED : socket %d , " + // "reason (%d) \n\n", + // pSock->SocketAsyncEvent.SockTxFailData.Sd, + // pSock->SocketAsyncEvent.SockTxFailData.Status); + break; + } + break; + + default: + //UART_PRINT("[SOCK EVENT] - Unexpected Event [%x0x]\n\n",pSock->Event); + break; + } +} + +void SimpleLinkNetAppRequestMemFreeEventHandler(uint8_t *buffer) +{ + /* Unused in this application */ +} + + +//////////// these are comming from link task, they probably don't belong here + +void SimpleLinkSocketTriggerEventHandler(SlSockTriggerEvent_t *pSlTriggerEvent) +{ + // Unused in this application + (void)pSlTriggerEvent; +} + + + + +/* + * ======== main ======== + */ +void * mainThread(void *arg) +{ + struct sched_param priorityParams; + + pthread_attr_t slThreadAttributes; + pthread_attr_t threadAttributes; + + int retc; + struct timespec ts = {0}; + + + GPIO_init(); + UART_init(); + SPI_init(); + I2C_init(); + + /* initialize the realtime clock */ + clock_settime(CLOCK_REALTIME, &ts); + + // Switch off all LEDs on boards + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + + + /* clear SimpleLink Status */ + nF_ControlBlock.status = 0; + + // initializes signals for all tasks + sem_init(&Provisioning_ControlBlock.connectionAsyncEvent, 0, 0); + sem_init(&Provisioning_ControlBlock.provisioningDoneSignal, 0, 0); + sem_init(&Provisioning_ControlBlock.provisioningConnDoneToOtaServerSignal, + 0, + 0); + sem_init(&LinkLocal_ControlBlock.otaReportServerStartSignal, 0, 0); + sem_init(&LinkLocal_ControlBlock.otaReportServerStopSignal, 0, 0); + + + // create the sl_Task + pthread_attr_init(&slThreadAttributes); + priorityParams.sched_priority = SPAWN_TASK_PRIORITY; + retc = pthread_attr_setschedparam(&slThreadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&slThreadAttributes, TASK_STACK_SIZE); + + retc = pthread_create(&slThread, &slThreadAttributes, sl_Task, NULL); + + if(retc) + { + /* Handle Error */ + ////UART_PRINT("Unable to create sl_Task thread \n"); + while(1) + { + ; + } + } + + retc = sl_Start(NULL, NULL, NULL); + if(retc > 0) + { + // we are good! + } + else if((retc < 0) && (retc != SL_ERROR_RESTORE_IMAGE_COMPLETE)) + { + // Handle Error + // //UART_PRINT("\n sl_Start failed\n"); + // //UART_PRINT("\n %s Example Ver. %s\n",APPLICATION_NAME, + // APPLICATION_VERSION); + while(1) + { + ; + } + } + + // // provisioning task + // pthread_attr_init(&threadAttributes); + // priorityParams.sched_priority = 1; + // retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + // retc |= pthread_attr_setstacksize(&threadAttributes, TASK_STACK_SIZE); + // retc = pthread_create(&provisioningThread, &threadAttributes, provisioningTask, NULL); + // if (retc != 0) { + // /* failed to set attributes */ + // while (1) {} + // } + + // retc |= pthread_attr_setstacksize(&threadAttributes, 2048); + // if(retc) + // { + // /* Handle Error */ + // // UART_PRINT("Unable to create provisioningTask thread \n"); + // while(1) + // { + // ; + // } + // } + + // receiver thread + pthread_attr_init(&slThreadAttributes); + priorityParams.sched_priority = 1; + retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&threadAttributes, 2048); + if (retc != 0) { + /* failed to set attributes */ + while (1) {} + } + + retc = pthread_create(&receiverThread, &threadAttributes, ReceiverThread, NULL); + if(retc != 0) + { + /* pthread_create() failed */ + while(1) + { + ; + } + } + + // // CLR thread + // pthread_attr_init(&slThreadAttributes); + // priorityParams.sched_priority = 1; + // retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + // retc |= pthread_attr_setstacksize(&threadAttributes, 10000); + // if (retc != 0) { + // /* failed to set attributes */ + // while (1) {} + // } + + // // forward CLR_SETTINGS to CLR startup thread + // retc = pthread_create(&nanoCLRThread, &threadAttributes, CLRStartupThread, arg); + // if(retc != 0) + // { + // /* pthread_create() failed */ + // while(1) + // { + // ; + // } + // } + + +while(1) +{ + + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + vTaskDelay(500); + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + vTaskDelay(500); + +} + return (0); +} + +//***************************************************************************** +// +//! \brief Application defined malloc failed hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void vApplicationMallocFailedHook() +{ + /* Handle Memory Allocation Errors */ + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Application defined stack overflow hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void vApplicationStackOverflowHook(TaskHandle_t pxTask, + char *pcTaskName) +{ + //Handle FreeRTOS Stack Overflow + while(1) + { + } +} + +void vApplicationTickHook(void) +{ + /* + * This function will be called by each tick interrupt if + * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + * added here, but the tick hook is called from an interrupt context, so + * code must not attempt to block, and only the interrupt safe FreeRTOS API + * functions can be used (those that end in FromISR()). + */ +} + +void vPreSleepProcessing(uint32_t ulExpectedIdleTime) +{ +} + +//***************************************************************************** +// +//! \brief Application defined idle task hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void +vApplicationIdleHook(void) +{ + /* Handle Idle Hook for Profiling, Power Management etc */ +} + +//***************************************************************************** +// +//! \brief Overwrite the GCC _sbrk function which check the heap limit related +//! to the stack pointer. +//! In case of freertos this checking will fail. +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void * _sbrk(uint32_t delta) +{ + extern char _end; /* Defined by the linker */ + extern char __HeapLimit; + static char *heap_end; + static char *heap_limit; + char *prev_heap_end; + + if(heap_end == 0) + { + heap_end = &_end; + heap_limit = &__HeapLimit; + } + + prev_heap_end = heap_end; + if(prev_heap_end + delta > heap_limit) + { + return((void *) -1L); + } + heap_end += delta; + return((void *) prev_heap_end); +} + + +// /***************************************************************************** +// Local Functions +// *****************************************************************************/ +// //***************************************************************************** +// // +// //! Application Boarders display on UART +// //! +// //! \param ch - Character to be displayed , n - number of time to display +// //! +// //! \return none +// //! +// //***************************************************************************** +// void printBorder(char ch, +// int n) +// { +// int i = 0; + +// for(i = 0; i < n; i++) +// { +// putch(ch); +// } +// } + +// //***************************************************************************** +// // +// //! Application startup display on UART +// //! +// //! \param none +// //! +// //! \return none +// //! +// //***************************************************************************** +// int32_t DisplayBanner(char * AppName, +// char * AppVer) +// { +// int32_t ret = 0; +// uint8_t macAddress[SL_MAC_ADDR_LEN]; +// uint16_t macAddressLen = SL_MAC_ADDR_LEN; +// uint16_t ConfigSize = 0; +// uint8_t ConfigOpt = SL_DEVICE_GENERAL_VERSION; +// SlDeviceVersion_t ver = {0}; +// char lineBreak[] = "\n\r"; +// ConfigSize = sizeof(SlDeviceVersion_t); + +// /* Print device version info. */ +// ret = +// sl_DeviceGet(SL_DEVICE_GENERAL, &ConfigOpt, &ConfigSize, +// (uint8_t*)(&ver)); +// ASSERT_ON_ERROR(ret); + +// /* Print device Mac address */ +// ret = sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, +// &macAddress[0]); +// ASSERT_ON_ERROR(ret); + +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t"); +// printBorder('=', 44); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t %s Example Ver: %s",AppName, AppVer); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t"); +// printBorder('=', 44); +// //UART_PRINT(lineBreak); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t CHIP: 0x%x",ver.ChipId); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t MAC: %d.%d.%d.%d",ver.FwVersion[0],ver.FwVersion[1], +// ver.FwVersion[2], +// ver.FwVersion[3]); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t PHY: %d.%d.%d.%d",ver.PhyVersion[0],ver.PhyVersion[1], +// ver.PhyVersion[2], +// ver.PhyVersion[3]); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t NWP: %d.%d.%d.%d",ver.NwpVersion[0],ver.NwpVersion[1], +// ver.NwpVersion[2], +// ver.NwpVersion[3]); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t ROM: %d",ver.RomVersion); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t HOST: %s", SL_DRIVER_VERSION); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t MAC address: %02x:%02x:%02x:%02x:%02x:%02x", macAddress[0], +// macAddress[1], macAddress[2], macAddress[3], macAddress[4], +// macAddress[5]); +// //UART_PRINT(lineBreak); +// //UART_PRINT(lineBreak); +// //UART_PRINT("\t"); +// printBorder('=', 44); +// //UART_PRINT(lineBreak); +// //UART_PRINT(lineBreak); + +// return(ret); +// } + +//***************************************************************************** +// +//! This function clears and enables a GPIO pin interrupt flag +//! +//! \param index - GPIO index +//! +//! \return None +//! +//***************************************************************************** +static void GPIO_clearAndEnable(uint8_t index) +{ + GPIO_clearInt(index); + GPIO_enableInt(index); +} + +void Platform_TimerInit(void (*timerIntHandler)(sigval val), + timer_t *timerId) +{ + sigevent sev; + + /* Create Timer */ + sev.sigev_notify = SIGEV_SIGNAL; + sev.sigev_notify_function = timerIntHandler; + timer_create(CLOCK_MONOTONIC, &sev, timerId); +} + +void Platform_TimerStart(uint32_t asyncEvtTimeoutMsec, + timer_t timerId, + uint8_t periodic) +{ + struct itimerspec value; + + /* set the timeout */ + value.it_value.tv_sec = (asyncEvtTimeoutMsec / 1000); + value.it_value.tv_nsec = (asyncEvtTimeoutMsec % 1000) * 1000000; + + value.it_value.tv_sec += (value.it_value.tv_nsec / 1000000000); + value.it_value.tv_nsec = value.it_value.tv_nsec % 1000000000; + + if(periodic) + { + /* set as periodic timer */ + value.it_interval.tv_sec = value.it_value.tv_sec; + value.it_interval.tv_nsec = value.it_value.tv_nsec; + } + else + { + /* set as one shot timer */ + value.it_interval.tv_sec = 0; + value.it_interval.tv_nsec = 0; + } + + /* kick the timer */ + timer_settime(timerId, 0, &value, NULL); +} + +void Platform_TimerStop(timer_t timerId) +{ + struct itimerspec value; + + /* stop timer */ + value.it_interval.tv_sec = 0; + value.it_interval.tv_nsec = 0; + value.it_value.tv_sec = 0; + value.it_value.tv_nsec = 0; + timer_settime(timerId, 0, &value, NULL); +} + +void Platform_TimerInterruptClear(void) +{ + /* Do nothing... */ +} + +//***************************************************************************** +// +//! \brief This function reboot the M4 host processor +//! +//! \param[in] none +//! +//! \return none +//! +//**************************************************************************** +void mcuReboot(void) +{ + /* stop network processor activities before reseting the MCU */ + sl_Stop(SL_STOP_TIMEOUT); + + // UART_PRINT("[Common] CC32xx MCU reset request\r\n"); + + /* Reset the MCU in order to test the bundle */ + PRCMHibernateCycleTrigger(); +} From 56f27e6c32248d64128e8f17951acdb79af5a101 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 11 Feb 2019 16:07:20 +0000 Subject: [PATCH 15/90] Add SL config file --- .../nanoCLR/ti_drivers_net_wifi_Config.c | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c new file mode 100644 index 0000000000..789076f16c --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c @@ -0,0 +1,28 @@ + +/* TI-DRIVERS Header files */ +#include + +/* + * =============================== SimpleLink Wifi =============================== + */ + +/* + * ======== SimpleLinkWifi_config ======== + */ +const SlWifiCC32XXConfig_t SimpleLinkWifiCC32XX_config = { + + .Mode = ROLE_STA, + .Ipv4Mode = SL_NETCFG_IPV4_STA_ADDR_MODE, + .ConnectionPolicy = SL_WLAN_CONNECTION_POLICY(1,0,0,1), + .PMPolicy = SL_WLAN_NORMAL_POLICY, + .MaxSleepTimeMS = 0, + .ScanPolicy = SL_WLAN_SCAN_POLICY(0,0), + .ScanIntervalInSeconds = 0, + .Ipv4Config = SL_NETCFG_ADDR_DHCP, + .Ipv4 = 0, + .IpMask = 0, + .IpGateway = 0, + .IpDnsServer = 0, + .ProvisioningStop = 0, + .DeleteAllProfile = 0 +}; From 49dfa300ed494f6107ee76e0bd1db706fd2cd941 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 11 Feb 2019 16:07:36 +0000 Subject: [PATCH 16/90] Add source files for SimpleLink --- .../TI_SimpleLink_CC32xx_sources.cmake | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake index 4280edbfb1..719ce8f6fd 100644 --- a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake +++ b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake @@ -133,6 +133,45 @@ foreach(SRC_FILE ${DriversLibrary_SRCS}) list(APPEND TI_SimpleLink_SOURCES ${DriversLibrary_SCR_FILE}) endforeach() +# source files for SimpleLink +set(SimpleLink_SRCS + + device.c + driver.c + flowcont.c + fs.c + netapp.c + netcfg.c + netutil.c + nonos.c + sl_socket.c + spawn.c + wlan.c + cc_pal.c + eventreg.c + wlanconfig.c + + # eventreg.c + +) + +foreach(SRC_FILE ${SimpleLink_SRCS}) + set(SimpleLink_SCR_FILE SRC_FILE -NOTFOUND) + find_file(SimpleLink_SCR_FILE ${SRC_FILE} + PATHS + + #drivers library + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi/porting" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi/source" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${SimpleLink_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${SimpleLink_SCR_FILE}) +endforeach() + + # other source files set(Other_SRCS From 55ba45a474c54f15ab7954701b8584e8f5291fe0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 11 Feb 2019 16:07:52 +0000 Subject: [PATCH 17/90] Add build define to use FreeRTOS --- CMake/toolchain.TI_SimpleLink.GCC.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMake/toolchain.TI_SimpleLink.GCC.cmake b/CMake/toolchain.TI_SimpleLink.GCC.cmake index d31f2c0d1d..1ff59ecb6f 100644 --- a/CMake/toolchain.TI_SimpleLink.GCC.cmake +++ b/CMake/toolchain.TI_SimpleLink.GCC.cmake @@ -125,7 +125,7 @@ function(NF_SET_COMPILER_DEFINITIONS TARGET) target_compile_definitions(${TARGET} PUBLIC "-DPLATFORM_ARM ") # definitions required for SimpleLink CC32xx SDK - target_compile_definitions(${TARGET} PUBLIC -Dgcc -DPTLS_TLS_INDEX=0 -DBOARD_DISPLAY_USE_UART_ANSI=0 -DBOARD_DISPLAY_USE_LCD=0 -DconfigNUM_THREAD_LOCAL_STORAGE_POINTERS=1) + target_compile_definitions(${TARGET} PUBLIC -Dgcc -DPTLS_TLS_INDEX=0 -DBOARD_DISPLAY_USE_UART_ANSI=0 -DBOARD_DISPLAY_USE_LCD=0 -DconfigNUM_THREAD_LOCAL_STORAGE_POINTERS=1 -DSL_PLATFORM_MULTI_THREADED) # build types that have debugging capabilities AND are NOT RTM have to have the define 'NANOCLR_ENABLE_SOURCELEVELDEBUGGING' if((NOT NF_BUILD_RTM) OR NF_FEATURE_DEBUGGER) From c33ebce7e0424918c670fd4ad076f25c84cc07e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 14 Feb 2019 03:30:29 +0000 Subject: [PATCH 18/90] Add target block files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../target_BlockStorage.c | 15 ++++ .../target_BlockStorage.h | 12 ++++ .../common/Target_BlockStorage.c | 68 +++---------------- targets/TI-SimpleLink/nanoCLR/targetHAL.cpp | 6 ++ 4 files changed, 41 insertions(+), 60 deletions(-) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.h diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c new file mode 100644 index 0000000000..91a870a322 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice CC32xxFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &CC32xxFlash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.h new file mode 100644 index 0000000000..74d115d382 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 2 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 2 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/targets/TI-SimpleLink/common/Target_BlockStorage.c b/targets/TI-SimpleLink/common/Target_BlockStorage.c index 79a1f7fcb1..f045fc90f6 100644 --- a/targets/TI-SimpleLink/common/Target_BlockStorage.c +++ b/targets/TI-SimpleLink/common/Target_BlockStorage.c @@ -31,13 +31,14 @@ bool BlockStorageStream_Initialize(BlockStorageStream* stream, unsigned int bloc } else if(blockUsage == StorageUsage_DEPLOYMENT) { - // set BaseAddress to the start of the region - // FIXME TODO - //stream->BaseAddress = (unsigned int)g_CC32xx_flash_start_ptr; - // set Length to the region size - // need to cast the pointers to make sure the compiler implements the correct math + // deployment is stored at SPI flash + // if there is a DEPLOYMENT file, get it's size + // FIXME TODO - //stream->Length = (uint32_t)g_pFlashDriver_partition->size; + + // if not, return 0 as stream length + stream->BaseAddress = 0; + stream->Length = 0; } return true; @@ -49,7 +50,7 @@ bool BlockStorageStream_Initialize(BlockStorageStream* stream, unsigned int bloc extern struct BlockStorageDevice Device_BlockStorage; extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; -BlockStorageList BlockStorage; +extern BlockStorageList g_BlockStorage; // map here the Block Storage Interface to the CC32xx driver IBlockStorageDevice CC32xxFlash_BlockStorageInterface = @@ -64,56 +65,3 @@ IBlockStorageDevice CC32xxFlash_BlockStorageInterface = &CC32xxFlashDriver_EraseBlock, &CC32xxFlashDriver_SetPowerState }; - -void BlockStorage_AddDevices() -{ - BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &CC32xxFlash_BlockStorageInterface, &Device_BlockStorageConfig, false); -} - -bool BlockStorageList_FindDeviceForPhysicalAddress(BlockStorageDevice** pBSD, unsigned int physicalAddress, ByteAddress* blockAddress) -{ - *pBSD = NULL; - - BlockStorageDevice* block = (BlockStorageDevice*)BlockStorageList_GetFirstDevice; - - // this has to add to make metadataprocessor happy - if(!block) return true; - - DeviceBlockInfo* pDeviceInfo = BlockStorageDevice_GetDeviceInfo((BlockStorageDevice*)&block); - - for(unsigned int i=0; i < pDeviceInfo->NumRegions; i++) - { - BlockRegionInfo* pRegion = &pDeviceInfo->Regions[i]; - - if(pRegion->Start <= physicalAddress && physicalAddress < (pRegion->Start + pRegion->NumBlocks * pRegion->BytesPerBlock)) - { - *pBSD = block; - - // get block start address - *blockAddress = (ByteAddress)((physicalAddress - pRegion->Start) / pRegion->BytesPerBlock); - *blockAddress *= pRegion->BytesPerBlock; - *blockAddress += pRegion->Start; - - return true; - } - } - - return false; -} - -bool BlockStorageList_AddDevice(BlockStorageDevice* pBSD, IBlockStorageDevice* vtable, void* config, bool init) -{ - (void)init; - - pBSD->m_BSD = vtable; - pBSD->m_context = config; - - BlockStorage.PrimaryDevice = pBSD; - - return true; -} - -BlockStorageDevice* BlockStorageList_GetFirstDevice() -{ - return BlockStorage.PrimaryDevice; -} diff --git a/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp b/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp index 8da9cd23fb..0bbe42bae0 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp +++ b/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp @@ -51,9 +51,13 @@ void nanoHAL_Initialize() HAL_CONTINUATION::InitializeList(); HAL_COMPLETION ::InitializeList(); + BlockStorageList_Initialize(); + // initialize block storage devices BlockStorage_AddDevices(); + BlockStorageList_InitializeDevices(); + // clear managed heap region unsigned char* heapStart = NULL; unsigned int heapSize = 0; @@ -90,6 +94,8 @@ void nanoHAL_Uninitialize() } } + BlockStorageList_UnInitializeDevices(); + //PalEvent_Uninitialize(); // TODO need to call this but it's preventing the debug session from starting From b26e8cdc32b212b7ff1d4444c259dc23788fd715 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Feb 2019 16:53:02 +0000 Subject: [PATCH 19/90] Update Block Storage stuff to match new structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Both platform and target level Signed-off-by: José Simões --- .../common/Device_BlockStorage-DEBUG.c | 3 + .../common/Device_BlockStorage.c | 47 +++---------- .../target_BlockStorage.c | 2 +- targets/TI-SimpleLink/common/CMakeLists.txt | 2 +- .../common/Target_BlockStorage.c | 67 ------------------- .../Target_BlockStorage_CC32xxFlashDriver.c | 10 --- .../common/platform_BlockStorage.c | 22 ++++++ 7 files changed, 38 insertions(+), 115 deletions(-) delete mode 100644 targets/TI-SimpleLink/common/Target_BlockStorage.c create mode 100644 targets/TI-SimpleLink/common/platform_BlockStorage.c diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index 6f6372d562..4d3dd41b6c 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -19,6 +19,7 @@ const BlockRange BlockRange2[] = const BlockRegionInfo BlockRegions[] = { { + (0), // no attributes for this region 0x01000800, // start address for block region 1, // total number of blocks in this region 0x0FF800, // total number of bytes per block @@ -26,6 +27,7 @@ const BlockRegionInfo BlockRegions[] = BlockRange1, }, { + (0), // no attributes for this region 0x08000000, // start address for block region 1, // total number of blocks in this region 0x0FF800, // total number of bytes per block @@ -37,6 +39,7 @@ const BlockRegionInfo BlockRegions[] = const DeviceBlockInfo Device_BlockInfo = { (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; }; diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c index 0e39196da2..b3095c5b6d 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c @@ -9,63 +9,38 @@ // 32kB blocks const BlockRange BlockRange1[] = { - { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter - - /////////////////////////////////////////////////////////////////////////////////////// - // because this target is using a configuration block need to add the - // configuration manager files to the CMake and call ConfigurationManager_Initialize() - // in nanoBooter so the configuration can be managed when in booter mode - /////////////////////////////////////////////////////////////////////////////////////// - { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 0x08008000 configuration block - /////////////////////////////////////////////////////////////////////////////////////// - - { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08010000 nanoCLR + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x01000800 nanoCLR }; -//128kB block const BlockRange BlockRange2[] = { - { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08020000 nanoCLR -}; - -// 256kB blocks -const BlockRange BlockRange3[] = -{ - { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 08040000 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 } // 08080000 deployment + { BlockRange_BLOCKTYPE_DEPLOYMENT , 0, 0 }, // 0x08000000 nanoCLR }; const BlockRegionInfo BlockRegions[] = { { - 0x08000000, // start address for block region - 4, // total number of blocks in this region - 0x8000, // total number of bytes per block + (0), // no attributes for this region + 0x01000800, // start address for block region + 1, // total number of blocks in this region + 0x0FF800, // total number of bytes per block ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, }, - { - 0x08020000, // start address for block region + (0), // no attributes for this region + 0x08000000, // start address for block region 1, // total number of blocks in this region - 0x20000, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange2), + 0x0FF800, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange2, }, - - { - 0x08040000, // start address for block region - 7, // total number of blocks in this region - 0x40000, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange3), - BlockRange3, - }, - }; const DeviceBlockInfo Device_BlockInfo = { (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; }; diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c index 91a870a322..ab075246ab 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c @@ -11,5 +11,5 @@ extern IBlockStorageDevice CC32xxFlash_BlockStorageInterface; void BlockStorage_AddDevices() { - BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &CC32xxFlash_BlockStorageInterface, &Device_BlockStorageConfig, false); + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &CC32xxFlash_BlockStorageInterface, &Device_BlockStorageConfig, true); } diff --git a/targets/TI-SimpleLink/common/CMakeLists.txt b/targets/TI-SimpleLink/common/CMakeLists.txt index e9221eec40..dc25728d4f 100644 --- a/targets/TI-SimpleLink/common/CMakeLists.txt +++ b/targets/TI-SimpleLink/common/CMakeLists.txt @@ -10,7 +10,7 @@ list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Wir list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_CC32xxFlashDriver.c") -list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platform_BlockStorage.c") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/FreeRTOS-openocd.c") diff --git a/targets/TI-SimpleLink/common/Target_BlockStorage.c b/targets/TI-SimpleLink/common/Target_BlockStorage.c deleted file mode 100644 index f045fc90f6..0000000000 --- a/targets/TI-SimpleLink/common/Target_BlockStorage.c +++ /dev/null @@ -1,67 +0,0 @@ -// -// Copyright (c) 2017 The nanoFramework project contributors -// See LICENSE file in the project root for full license information. -// - -#include -#include -#include - -/////////////////////////////////////////////////// -// BlockStream -/////////////////////////////////////////////////// -bool BlockStorageStream_Initialize(BlockStorageStream* stream, unsigned int blockUsage) -{ - // 'reset' CurrentIndex - stream->CurrentIndex = 0; - - stream->BlockLength = 0; - - // set usage according to parameter - stream->Usage = blockUsage; - - // initialize base address and length from linker symbols - if(blockUsage == StorageUsage_CLR) - { - // set BaseAddress to the start of the region - stream->BaseAddress = (unsigned int)&__nanoImage_start__; - // set Length to the region size - // need to cast the pointers to make sure the compiler implements the correct math - stream->Length = ((uint32_t)&__nanoImage_end__) - ((uint32_t)&__nanoImage_start__); - } - else if(blockUsage == StorageUsage_DEPLOYMENT) - { - // deployment is stored at SPI flash - // if there is a DEPLOYMENT file, get it's size - - // FIXME TODO - - // if not, return 0 as stream length - stream->BaseAddress = 0; - stream->Length = 0; - } - - return true; -} - -/////////////////////////////////////////////////// -// BlockStorageList -/////////////////////////////////////////////////// - -extern struct BlockStorageDevice Device_BlockStorage; -extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; -extern BlockStorageList g_BlockStorage; - -// map here the Block Storage Interface to the CC32xx driver -IBlockStorageDevice CC32xxFlash_BlockStorageInterface = -{ - &CC32xxFlashDriver_InitializeDevice, - &CC32xxFlashDriver_UninitializeDevice, - &CC32xxFlashDriver_GetDeviceInfo, - &CC32xxFlashDriver_Read, - &CC32xxFlashDriver_Write, - NULL, - &CC32xxFlashDriver_IsBlockErased, - &CC32xxFlashDriver_EraseBlock, - &CC32xxFlashDriver_SetPowerState -}; diff --git a/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c b/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c index 3ff331ce8a..7b8fb8da6a 100644 --- a/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c +++ b/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c @@ -23,8 +23,6 @@ bool CC32xxFlashDriver_UninitializeDevice(void* context) DeviceBlockInfo* CC32xxFlashDriver_GetDeviceInfo(void* context) { - (void)context; - MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = context; return config->BlockConfig.BlockDeviceInformation; @@ -58,11 +56,3 @@ bool CC32xxFlashDriver_EraseBlock(void* context, ByteAddress address) return true; } - -void CC32xxFlashDriver_SetPowerState(void* context, unsigned int state) -{ - (void)context; - (void)state; - - // nothing to be done here -} diff --git a/targets/TI-SimpleLink/common/platform_BlockStorage.c b/targets/TI-SimpleLink/common/platform_BlockStorage.c new file mode 100644 index 0000000000..0af51e547b --- /dev/null +++ b/targets/TI-SimpleLink/common/platform_BlockStorage.c @@ -0,0 +1,22 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// map here the Block Storage Interface to the CC32xx driver +IBlockStorageDevice CC32xxFlash_BlockStorageInterface = +{ + &CC32xxFlashDriver_InitializeDevice, + &CC32xxFlashDriver_UninitializeDevice, + &CC32xxFlashDriver_GetDeviceInfo, + &CC32xxFlashDriver_Read, + &CC32xxFlashDriver_Write, + NULL, + &CC32xxFlashDriver_IsBlockErased, + &CC32xxFlashDriver_EraseBlock, + NULL, + NULL +}; From 602a8b6603909d1945e2415a5c8dfc6d2313e93b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Feb 2019 17:38:14 +0000 Subject: [PATCH 20/90] Enable execution of CLR thread MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 38 +++++++++---------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index 343188ca31..bef93dd031 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -855,26 +855,26 @@ void * mainThread(void *arg) } } - // // CLR thread - // pthread_attr_init(&slThreadAttributes); - // priorityParams.sched_priority = 1; - // retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); - // retc |= pthread_attr_setstacksize(&threadAttributes, 10000); - // if (retc != 0) { - // /* failed to set attributes */ - // while (1) {} - // } + // CLR thread + pthread_attr_init(&slThreadAttributes); + priorityParams.sched_priority = 1; + retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&threadAttributes, 10000); + if (retc != 0) { + /* failed to set attributes */ + while (1) {} + } - // // forward CLR_SETTINGS to CLR startup thread - // retc = pthread_create(&nanoCLRThread, &threadAttributes, CLRStartupThread, arg); - // if(retc != 0) - // { - // /* pthread_create() failed */ - // while(1) - // { - // ; - // } - // } + // forward CLR_SETTINGS to CLR startup thread + retc = pthread_create(&nanoCLRThread, &threadAttributes, CLRStartupThread, arg); + if(retc != 0) + { + /* pthread_create() failed */ + while(1) + { + ; + } + } while(1) From d5354918e2cd038ec75979b9b65234bcf877852b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Feb 2019 17:39:08 +0000 Subject: [PATCH 21/90] Initial work on block storage configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../common/Device_BlockStorage-DEBUG.c | 25 ++++++------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index 4d3dd41b6c..e328f543ad 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -6,14 +6,13 @@ #include #include +// 2k blocks const BlockRange BlockRange1[] = { - { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x01000800 nanoCLR -}; - -const BlockRange BlockRange2[] = -{ - { BlockRange_BLOCKTYPE_DEPLOYMENT , 0, 0 }, // 0x08000000 nanoCLR + // the 1st block is reserved for the flash header + // so we don't take it into account for the map + { BlockRange_BLOCKTYPE_CODE , 0 , 99 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 100, 510 }, // 0x01032000 deployment }; const BlockRegionInfo BlockRegions[] = @@ -21,19 +20,11 @@ const BlockRegionInfo BlockRegions[] = { (0), // no attributes for this region 0x01000800, // start address for block region - 1, // total number of blocks in this region - 0x0FF800, // total number of bytes per block + 511, // total number of blocks in this region + 0x800, // total number of bytes per block ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, - }, - { - (0), // no attributes for this region - 0x08000000, // start address for block region - 1, // total number of blocks in this region - 0x0FF800, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange2, - }, + } }; const DeviceBlockInfo Device_BlockInfo = From 41c3d05bfbed331360d506c4dda7412771e994da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Feb 2019 19:02:43 +0000 Subject: [PATCH 22/90] Add Flash driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../Target_BlockStorage_CC32xxFlashDriver.c | 41 +++++++++++++++++-- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c b/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c index 7b8fb8da6a..41f07d897f 100644 --- a/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c +++ b/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c @@ -5,6 +5,13 @@ #include +// includes from SimpleLink +#include "inc/hw_types.h" +#include + +// local defines +#define FLASH_ERASED_WORD 0x0FFFFFFFFU + bool CC32xxFlashDriver_InitializeDevice(void* context) { (void)context; @@ -39,20 +46,46 @@ bool CC32xxFlashDriver_Read(void* context, ByteAddress startAddress, unsigned in bool CC32xxFlashDriver_Write(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite) { (void)context; + (void)readModifyWrite; + + if(FlashProgram((unsigned long*)buffer, (unsigned long) startAddress, (unsigned long) numBytes) == 0) + { + return true; + } - return true; + return false; } - + bool CC32xxFlashDriver_IsBlockErased(void* context, ByteAddress blockAddress, unsigned int length) { (void)context; - return true; + unsigned long* cursor = (unsigned long *)blockAddress; + unsigned long* endAddress = (unsigned long *)(blockAddress + length); + + // an erased flash address has to read FLASH_ERASED_WORD + // OK to check by word (32 bits) because the erase is performed by 'block' whose size is word multiple + while(cursor < endAddress) + { + if(*cursor++ != FLASH_ERASED_WORD) + { + // found an address with something other than FLASH_ERASED_WORD!! + return false; + } + } + + // reached here so the block must be erased + return true; } bool CC32xxFlashDriver_EraseBlock(void* context, ByteAddress address) { (void)context; - return true; + if(FlashErase((unsigned long) address) == 0) + { + return true; + } + + return false; } From 2f0e7625a04273b16793237ada84de6b991384d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Feb 2019 09:59:59 +0000 Subject: [PATCH 23/90] Fix BASE_PATH_FOR_CLASS_LIBRARIES_MODULES MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- CMakeLists.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4bd4ca7522..1130057ec3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1130,13 +1130,15 @@ elseif(RTOS_TI_SIMPLELINK_CHECK) # can't continue message(FATAL_ERROR "\n\nSorry but support for ${TI_BOARD} target is not available...\n\nYou can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") endif() + + # Define base path for the class libraries + set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/nanoCLR") - # add target TI SimpliLink dirs + # add target TI SimpleLink dirs add_subdirectory(targets/TI-SimpleLink/common) add_subdirectory(targets/TI-SimpleLink/Include) add_subdirectory(targets/TI-SimpleLink/nanoCLR) - if("${TARGET_SERIES}" STREQUAL "CC32xx") # CC32xx series is using TI SimpleLink CC32xx SDK and FreeRTOS @@ -1343,8 +1345,8 @@ elseif(RTOS_TI_SIMPLELINK_CHECK) endif() - # Define base path for the class libraries - set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/${TI_BOARD}/nanoCLR") + # # Define base path for the class libraries + # set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/nanoCLR") add_subdirectory(targets/TI-SimpleLink/${TI_BOARD}) From 017123ae8654a67be8403132b819d3d9b0e6a5ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Feb 2019 10:00:31 +0000 Subject: [PATCH 24/90] Add missing include path for SimpleLink MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake index 719ce8f6fd..2ad1b7effc 100644 --- a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake +++ b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake @@ -5,6 +5,7 @@ # includes for SimpleLink CC32xx SDK list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers") list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/posix/gcc") list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/boards/CC3220SF_LAUNCHXL") list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx") From 30ee6ddebb84510360aae018bffc5b54b392bb18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Feb 2019 10:00:59 +0000 Subject: [PATCH 25/90] Add compiler defs to target CMake MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt index 63723fa606..e2d046934e 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt @@ -106,7 +106,10 @@ target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) # set compiler definitions -nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) +############################################### +# add -DUSE_CC3220_ROM_DRV_API to use ROM API # +############################################### +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf -DDeviceFamily_CC3220) # set linker files if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) From 61c8f95ae907481ace5eba5a31a285f0be78a4e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Feb 2019 10:01:26 +0000 Subject: [PATCH 26/90] Adjust deployment region for CLR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c | 4 ++-- .../TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index e328f543ad..aa0108fbf1 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -11,8 +11,8 @@ const BlockRange BlockRange1[] = { // the 1st block is reserved for the flash header // so we don't take it into account for the map - { BlockRange_BLOCKTYPE_CODE , 0 , 99 }, // 0x01000800 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT , 100, 510 }, // 0x01032000 deployment + { BlockRange_BLOCKTYPE_CODE , 0 , 101 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 102, 510 }, // 0x01033000 deployment }; const BlockRegionInfo BlockRegions[] = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index 2da13f2e66..9488a17881 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x0FF800 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x032800 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } From 38e48870430501a11928391c9e4e6143ca5b52bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Feb 2019 10:20:34 +0000 Subject: [PATCH 27/90] Clean-up and tidy code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/nanoCLR/main.c | 26 +- .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 224 +++++------------- 2 files changed, 69 insertions(+), 181 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c index 2b55ff707c..9283109b61 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c @@ -1,27 +1,28 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// #include #include -/* POSIX Header files */ +// POSIX Header files #include #include -/* RTOS header files */ +// RTOS header files #include "FreeRTOS.h" #include "task.h" -/* Example/Board Header files */ +// board Header files #include "Board.h" ////////////////////////////// -/* Stack size in bytes */ +// Stack size in bytes #define THREADSTACKSIZE 2024 extern void * mainThread(void *arg0); -/* - * ======== main ======== - */ int main(void) { pthread_t thread; @@ -30,19 +31,18 @@ int main(void) int retc; - /* Call board init functions */ + // Call board init functions Board_initGeneral(); - // CLR settings to launch CLR thread CLR_SETTINGS clrSettings; (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); clrSettings.MaxContextSwitches = 50; clrSettings.WaitForDebugger = false; - clrSettings.EnterDebuggerLoopAfterExit = false; + clrSettings.EnterDebuggerLoopAfterExit = true; - /* Set priority and stack size attributes */ + // Set priority and stack size attributes pthread_attr_init(&threadAttributes); priorityParameters.sched_priority = 1; @@ -53,14 +53,14 @@ int main(void) retc |= pthread_create(&thread, &threadAttributes, mainThread, &clrSettings); if(retc != 0) { - /* pthread_create() failed */ + // pthread_create() while(1) { ; } } - /* Start the FreeRTOS scheduler */ + // Start the FreeRTOS scheduler vTaskStartScheduler(); return (0); diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index bef93dd031..fe4814cf1a 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -6,18 +6,18 @@ #include #include -/* POSIX Header files */ +// POSIX Header files #include #include -/* RTOS header files */ +// RTOS header files #include "FreeRTOS.h" #include "task.h" -/* TI-RTOS Header files */ +// TI-RTOS Header files #include -/* Example/Board Header files */ +// Example/Board Header files #include "Board.h" #include @@ -42,7 +42,7 @@ extern void * ReceiverThread(void *arg0); ////////////////////////////// -/* Stack size in bytes */ +// Stack size in bytes #define THREADSTACKSIZE 4096 pthread_t provisioningThread = (pthread_t)NULL; @@ -78,16 +78,15 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_Ipv6gAcquired); - /* - Information about the connected AP (like name, MAC etc) will be - available in 'slWlanConnectAsyncResponse_t'-Applications - can use it if required: + // Information about the connected AP (like name, MAC etc) will be + // available in 'slWlanConnectAsyncResponse_t'-Applications + // can use it if required: - slWlanConnectAsyncResponse_t *pEventData = NULL; - pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected; - */ + // slWlanConnectAsyncResponse_t *pEventData = NULL; + // pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected; + - /* Copy new connection SSID and BSSID to global parameters */ + // Copy new connection SSID and BSSID to global parameters // memcpy(nF_ControlBlock.connectionSSID, // pWlanEvent->Data.Connect.SsidName, // pWlanEvent->Data.Connect.SsidLen); @@ -126,9 +125,9 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) pEventData = &pWlanEvent->Data.Disconnect; - /* If the user has initiated 'Disconnect' request, - 'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED. - */ + // If the user has initiated 'Disconnect' request, + // 'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED. + if(SL_WLAN_DISCONNECT_USER_INITIATED == pEventData->ReasonCode) { //UART_PRINT( @@ -261,8 +260,8 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) case SL_WLAN_PROVISIONING_AUTO_STARTED: { //UART_PRINT("[WLAN EVENT] Auto-Provisioning Started\r\n"); - /* stop auto provisioning - - may trigger in case of returning to default */ + // stop auto provisioning - + // may trigger in case of returning to default // SignalProvisioningEvent(PrvnEvent_Stopped); } break; @@ -287,8 +286,8 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) // nF_ControlBlock.ssidLen = // pWlanEvent->Data.ProvisioningStatus.Ssidlen; - /* Provisioning is stopped by the device and - provisioning is done successfully */ + // Provisioning is stopped by the device and + // provisioning is done successfully // SignalProvisioningEvent(PrvnEvent_Stopped); break; @@ -304,8 +303,8 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_Ipv6gAcquired); - /* Provisioning is stopped by the device and provisioning - is not done yet, still need to connect to AP */ + // Provisioning is stopped by the device and provisioning + // is not done yet, still need to connect to AP // SignalProvisioningEvent(PrvnEvent_WaitForConn); break; @@ -472,10 +471,10 @@ void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) SET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpAcquired); - /* Ip Acquired Event Data */ + // Ip Acquired Event Data pEventData = &pNetAppEvent->Data.IpAcquiredV4; - /* Gateway IP address */ + // Gateway IP address // nF_ControlBlock.gatewayIP = pEventData->Gateway; //UART_PRINT("[NETAPP EVENT] IP Acquired: IP=%d.%d.%d.%d , " @@ -600,7 +599,7 @@ void SimpleLinkHttpServerEventHandler(SlNetAppHttpServerEvent_t *pHttpEvent, SlNetAppHttpServerResponse_t * pHttpResponse) { - /* Unused in this application */ + // Unused in this application //UART_PRINT("[HTTP SERVER EVENT] Unexpected HTTP server event \n\r"); } @@ -618,10 +617,9 @@ void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent) uint8_t msg = 4; int32_t msgqRetVal; - /* - Most of the general errors are not FATAL are are to be handled - appropriately by the application. - */ + // Most of the general errors are not FATAL are are to be handled + // appropriately by the application. + if(NULL == pDevEvent) { return; @@ -696,7 +694,7 @@ void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) } } - /* This application doesn't work w/ socket - Events are not expected */ + // This application doesn't work w/ socket - Events are not expected switch(pSock->Event) { case SL_SOCKET_TX_FAILED_EVENT: @@ -724,7 +722,7 @@ void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) void SimpleLinkNetAppRequestMemFreeEventHandler(uint8_t *buffer) { - /* Unused in this application */ + // Unused in this application } @@ -736,12 +734,6 @@ void SimpleLinkSocketTriggerEventHandler(SlSockTriggerEvent_t *pSlTriggerEvent) (void)pSlTriggerEvent; } - - - -/* - * ======== main ======== - */ void * mainThread(void *arg) { struct sched_param priorityParams; @@ -752,20 +744,19 @@ void * mainThread(void *arg) int retc; struct timespec ts = {0}; - GPIO_init(); UART_init(); SPI_init(); I2C_init(); - /* initialize the realtime clock */ + // initialize the realtime clock clock_settime(CLOCK_REALTIME, &ts); // Switch off all LEDs on boards GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); - /* clear SimpleLink Status */ + // clear SimpleLink Status nF_ControlBlock.status = 0; // initializes signals for all tasks @@ -788,7 +779,7 @@ void * mainThread(void *arg) if(retc) { - /* Handle Error */ + // Handle Error ////UART_PRINT("Unable to create sl_Task thread \n"); while(1) { @@ -820,14 +811,14 @@ void * mainThread(void *arg) // retc |= pthread_attr_setstacksize(&threadAttributes, TASK_STACK_SIZE); // retc = pthread_create(&provisioningThread, &threadAttributes, provisioningTask, NULL); // if (retc != 0) { - // /* failed to set attributes */ + // // failed to set attributes // while (1) {} // } // retc |= pthread_attr_setstacksize(&threadAttributes, 2048); // if(retc) // { - // /* Handle Error */ + // // Handle Error // // UART_PRINT("Unable to create provisioningTask thread \n"); // while(1) // { @@ -841,14 +832,14 @@ void * mainThread(void *arg) retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); retc |= pthread_attr_setstacksize(&threadAttributes, 2048); if (retc != 0) { - /* failed to set attributes */ + // failed to set attributes while (1) {} } retc = pthread_create(&receiverThread, &threadAttributes, ReceiverThread, NULL); if(retc != 0) { - /* pthread_create() failed */ + // pthread_create() failed while(1) { ; @@ -861,7 +852,7 @@ void * mainThread(void *arg) retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); retc |= pthread_attr_setstacksize(&threadAttributes, 10000); if (retc != 0) { - /* failed to set attributes */ + // failed to set attributes while (1) {} } @@ -869,23 +860,13 @@ void * mainThread(void *arg) retc = pthread_create(&nanoCLRThread, &threadAttributes, CLRStartupThread, arg); if(retc != 0) { - /* pthread_create() failed */ + // pthread_create() failed while(1) { ; } } - -while(1) -{ - - GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); - vTaskDelay(500); - GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); - vTaskDelay(500); - -} return (0); } @@ -900,7 +881,7 @@ while(1) //***************************************************************************** void vApplicationMallocFailedHook() { - /* Handle Memory Allocation Errors */ + // Handle Memory Allocation Errors while(1) { } @@ -926,13 +907,12 @@ void vApplicationStackOverflowHook(TaskHandle_t pxTask, void vApplicationTickHook(void) { - /* - * This function will be called by each tick interrupt if - * configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - * added here, but the tick hook is called from an interrupt context, so - * code must not attempt to block, and only the interrupt safe FreeRTOS API - * functions can be used (those that end in FromISR()). - */ + // This function will be called by each tick interrupt if + // configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + // added here, but the tick hook is called from an interrupt context, so + // code must not attempt to block, and only the interrupt safe FreeRTOS API + // functions can be used (those that end in FromISR()). + } void vPreSleepProcessing(uint32_t ulExpectedIdleTime) @@ -951,7 +931,7 @@ void vPreSleepProcessing(uint32_t ulExpectedIdleTime) void vApplicationIdleHook(void) { - /* Handle Idle Hook for Profiling, Power Management etc */ + // Handle Idle Hook for Profiling, Power Management etc } //***************************************************************************** @@ -966,7 +946,7 @@ vApplicationIdleHook(void) //***************************************************************************** void * _sbrk(uint32_t delta) { - extern char _end; /* Defined by the linker */ + extern char _end; // Defined by the linker extern char __HeapLimit; static char *heap_end; static char *heap_limit; @@ -991,98 +971,6 @@ void * _sbrk(uint32_t delta) // /***************************************************************************** // Local Functions // *****************************************************************************/ -// //***************************************************************************** -// // -// //! Application Boarders display on UART -// //! -// //! \param ch - Character to be displayed , n - number of time to display -// //! -// //! \return none -// //! -// //***************************************************************************** -// void printBorder(char ch, -// int n) -// { -// int i = 0; - -// for(i = 0; i < n; i++) -// { -// putch(ch); -// } -// } - -// //***************************************************************************** -// // -// //! Application startup display on UART -// //! -// //! \param none -// //! -// //! \return none -// //! -// //***************************************************************************** -// int32_t DisplayBanner(char * AppName, -// char * AppVer) -// { -// int32_t ret = 0; -// uint8_t macAddress[SL_MAC_ADDR_LEN]; -// uint16_t macAddressLen = SL_MAC_ADDR_LEN; -// uint16_t ConfigSize = 0; -// uint8_t ConfigOpt = SL_DEVICE_GENERAL_VERSION; -// SlDeviceVersion_t ver = {0}; -// char lineBreak[] = "\n\r"; -// ConfigSize = sizeof(SlDeviceVersion_t); - -// /* Print device version info. */ -// ret = -// sl_DeviceGet(SL_DEVICE_GENERAL, &ConfigOpt, &ConfigSize, -// (uint8_t*)(&ver)); -// ASSERT_ON_ERROR(ret); - -// /* Print device Mac address */ -// ret = sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, -// &macAddress[0]); -// ASSERT_ON_ERROR(ret); - -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t"); -// printBorder('=', 44); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t %s Example Ver: %s",AppName, AppVer); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t"); -// printBorder('=', 44); -// //UART_PRINT(lineBreak); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t CHIP: 0x%x",ver.ChipId); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t MAC: %d.%d.%d.%d",ver.FwVersion[0],ver.FwVersion[1], -// ver.FwVersion[2], -// ver.FwVersion[3]); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t PHY: %d.%d.%d.%d",ver.PhyVersion[0],ver.PhyVersion[1], -// ver.PhyVersion[2], -// ver.PhyVersion[3]); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t NWP: %d.%d.%d.%d",ver.NwpVersion[0],ver.NwpVersion[1], -// ver.NwpVersion[2], -// ver.NwpVersion[3]); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t ROM: %d",ver.RomVersion); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t HOST: %s", SL_DRIVER_VERSION); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t MAC address: %02x:%02x:%02x:%02x:%02x:%02x", macAddress[0], -// macAddress[1], macAddress[2], macAddress[3], macAddress[4], -// macAddress[5]); -// //UART_PRINT(lineBreak); -// //UART_PRINT(lineBreak); -// //UART_PRINT("\t"); -// printBorder('=', 44); -// //UART_PRINT(lineBreak); -// //UART_PRINT(lineBreak); - -// return(ret); -// } //***************************************************************************** // @@ -1104,7 +992,7 @@ void Platform_TimerInit(void (*timerIntHandler)(sigval val), { sigevent sev; - /* Create Timer */ + // Create Timer sev.sigev_notify = SIGEV_SIGNAL; sev.sigev_notify_function = timerIntHandler; timer_create(CLOCK_MONOTONIC, &sev, timerId); @@ -1116,7 +1004,7 @@ void Platform_TimerStart(uint32_t asyncEvtTimeoutMsec, { struct itimerspec value; - /* set the timeout */ + // set the timeout value.it_value.tv_sec = (asyncEvtTimeoutMsec / 1000); value.it_value.tv_nsec = (asyncEvtTimeoutMsec % 1000) * 1000000; @@ -1125,18 +1013,18 @@ void Platform_TimerStart(uint32_t asyncEvtTimeoutMsec, if(periodic) { - /* set as periodic timer */ + // set as periodic timer value.it_interval.tv_sec = value.it_value.tv_sec; value.it_interval.tv_nsec = value.it_value.tv_nsec; } else { - /* set as one shot timer */ + // set as one shot timer value.it_interval.tv_sec = 0; value.it_interval.tv_nsec = 0; } - /* kick the timer */ + // kick the timer timer_settime(timerId, 0, &value, NULL); } @@ -1144,7 +1032,7 @@ void Platform_TimerStop(timer_t timerId) { struct itimerspec value; - /* stop timer */ + // stop timer value.it_interval.tv_sec = 0; value.it_interval.tv_nsec = 0; value.it_value.tv_sec = 0; @@ -1154,7 +1042,7 @@ void Platform_TimerStop(timer_t timerId) void Platform_TimerInterruptClear(void) { - /* Do nothing... */ + // Do nothing... } //***************************************************************************** @@ -1168,11 +1056,11 @@ void Platform_TimerInterruptClear(void) //**************************************************************************** void mcuReboot(void) { - /* stop network processor activities before reseting the MCU */ + // stop network processor activities before reseting the MCU sl_Stop(SL_STOP_TIMEOUT); // UART_PRINT("[Common] CC32xx MCU reset request\r\n"); - /* Reset the MCU in order to test the bundle */ + // Reset the MCU in order to test the bundle PRCMHibernateCycleTrigger(); } From 88dd7720cfdf3f59463debeea3b9192f03abe710 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Feb 2019 14:28:36 +0000 Subject: [PATCH 28/90] Move board files into target folder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- CMake/Modules/FindTI_SimpleLink.cmake | 21 - .../TI_SimpleLink_CC32xx_sources.cmake | 22 - .../TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c | 853 ++++++++++++++++++ .../TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h | 222 +++++ .../TI_CC3220SF_LAUNCHXL/CMakeLists.txt | 1 + 5 files changed, 1076 insertions(+), 43 deletions(-) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h diff --git a/CMake/Modules/FindTI_SimpleLink.cmake b/CMake/Modules/FindTI_SimpleLink.cmake index 16d9d4280a..72be92ce01 100644 --- a/CMake/Modules/FindTI_SimpleLink.cmake +++ b/CMake/Modules/FindTI_SimpleLink.cmake @@ -90,27 +90,6 @@ foreach(SRC_FILE ${FreeRTOS_SRCS}) list(APPEND TI_SimpleLink_SOURCES ${FreeRTOS_SCR_FILE}) endforeach() -# other source files -set(Other_SRCS - - # board files - CC3220SF_LAUNCHXL.c - -) - -foreach(SRC_FILE ${Other_SRCS}) - set(Other_SCR_FILE SRC_FILE -NOTFOUND) - find_file(Other_SCR_FILE ${SRC_FILE} - PATHS - - "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/boards/CC3220SF_LAUNCHXL" - - CMAKE_FIND_ROOT_PATH_BOTH - ) - # message("${SRC_FILE} >> ${Other_SCR_FILE}") # debug helper - list(APPEND TI_SimpleLink_SOURCES ${Other_SCR_FILE}) -endforeach() - include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(TI_SimpleLink DEFAULT_MSG TI_SimpleLink_INCLUDE_DIRS TI_SimpleLink_SOURCES) diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake index 2ad1b7effc..78b963eb5f 100644 --- a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake +++ b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake @@ -172,28 +172,6 @@ foreach(SRC_FILE ${SimpleLink_SRCS}) list(APPEND TI_SimpleLink_SOURCES ${SimpleLink_SCR_FILE}) endforeach() - -# other source files -set(Other_SRCS - - # board files - CC3220SF_LAUNCHXL.c - -) - -foreach(SRC_FILE ${Other_SRCS}) - set(Other_SCR_FILE SRC_FILE -NOTFOUND) - find_file(Other_SCR_FILE ${SRC_FILE} - PATHS - - "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/boards/CC3220SF_LAUNCHXL" - - CMAKE_FIND_ROOT_PATH_BOTH - ) - # message("${SRC_FILE} >> ${Other_SCR_FILE}") # debug helper - list(APPEND TI_SimpleLink_SOURCES ${Other_SCR_FILE}) -endforeach() - include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(SimpleLinkCC32xxSDK DEFAULT_MSG TI_SimpleLink_INCLUDE_DIRS TI_SimpleLink_SOURCES) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c new file mode 100644 index 0000000000..7aa6f58201 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -0,0 +1,853 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ======== CC3220SF_LAUNCHXL.c ======== + * This file is responsible for setting up the board specific items for the + * CC3220SF_LAUNCHXL board. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "CC3220SF_LAUNCHXL.h" + +/* + * This define determines whether to use the UARTCC32XXDMA driver + * or the UARTCC32XX (no DMA) driver. Set to 1 to use the UARTCC32XXDMA + * driver. + */ +#ifndef TI_DRIVERS_UART_DMA +#define TI_DRIVERS_UART_DMA 0 +#endif + +/* + * =============================== ADC =============================== + */ +#include +#include + +ADCCC32XX_Object adcCC3220SObjects[CC3220SF_LAUNCHXL_ADCCOUNT]; + +const ADCCC32XX_HWAttrsV1 adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADCCOUNT] = { + { + .adcPin = ADCCC32XX_PIN_59_CH_2 + }, + { + .adcPin = ADCCC32XX_PIN_60_CH_3 + } +}; + +const ADC_Config ADC_config[CC3220SF_LAUNCHXL_ADCCOUNT] = { + { + .fxnTablePtr = &ADCCC32XX_fxnTable, + .object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC0], + .hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC0] + }, + { + .fxnTablePtr = &ADCCC32XX_fxnTable, + .object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC1], + .hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC1] + } +}; + +const uint_least8_t ADC_count = CC3220SF_LAUNCHXL_ADCCOUNT; + +/* + * =============================== Capture =============================== + */ +#include +#include + +CaptureCC32XX_Object captureCC3220SFObjects[CC3220SF_LAUNCHXL_CAPTURECOUNT]; + +const CaptureCC32XX_HWAttrs captureCC3220SFHWAttrs[CC3220SF_LAUNCHXL_CAPTURECOUNT] = +{ + { + .capturePin = CaptureCC32XX_PIN_04, + .intPriority = ~0 + }, + { + .capturePin = CaptureCC32XX_PIN_05, + .intPriority = ~0 + }, +}; + +const Capture_Config Capture_config[CC3220SF_LAUNCHXL_CAPTURECOUNT] = { + { + .fxnTablePtr = &CaptureCC32XX_fxnTable, + .object = &captureCC3220SFObjects[CC3220SF_LAUNCHXL_CAPTURE0], + .hwAttrs = &captureCC3220SFHWAttrs[CC3220SF_LAUNCHXL_CAPTURE0] + }, + { + .fxnTablePtr = &CaptureCC32XX_fxnTable, + .object = &captureCC3220SFObjects[CC3220SF_LAUNCHXL_CAPTURE1], + .hwAttrs = &captureCC3220SFHWAttrs[CC3220SF_LAUNCHXL_CAPTURE1] + } +}; + +const uint_least8_t Capture_count = CC3220SF_LAUNCHXL_CAPTURECOUNT; + +/* + * =============================== Crypto =============================== + */ +#include + +CryptoCC32XX_Object cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTOCOUNT]; + +const CryptoCC32XX_Config CryptoCC32XX_config[CC3220SF_LAUNCHXL_CRYPTOCOUNT] = { + { + .object = &cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTO0] + } +}; + +const uint_least8_t CryptoCC32XX_count = CC3220SF_LAUNCHXL_CRYPTOCOUNT; + +/* + * =============================== DMA =============================== + */ +#include + +static tDMAControlTable dmaControlTable[64] __attribute__ ((aligned (1024))); + +/* + * ======== dmaErrorFxn ======== + * This is the handler for the uDMA error interrupt. + */ +static void dmaErrorFxn(uintptr_t arg) +{ + int status = MAP_uDMAErrorStatusGet(); + MAP_uDMAErrorStatusClear(); + + /* Suppress unused variable warning */ + (void)status; + + while (1); +} + +UDMACC32XX_Object udmaCC3220SObject; + +const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = { + .controlBaseAddr = (void *)dmaControlTable, + .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn, + .intNum = INT_UDMAERR, + .intPriority = (~0) +}; + +const UDMACC32XX_Config UDMACC32XX_config = { + .object = &udmaCC3220SObject, + .hwAttrs = &udmaCC3220SHWAttrs +}; + +/* + * =============================== General =============================== + */ +/* + * ======== CC3220SF_LAUNCHXL_initGeneral ======== + */ +void CC3220SF_LAUNCHXL_initGeneral(void) +{ + PRCMCC3200MCUInit(); + Power_init(); +} + +/* + * =============================== GPIO =============================== + */ +#include +#include + +/* + * Array of Pin configurations + * NOTE: The order of the pin configurations must coincide with what was + * defined in CC3220SF_LAUNCHXL.h + * NOTE: Pins not used for interrupts should be placed at the end of the + * array. Callback entries can be omitted from callbacks array to + * reduce memory usage. + */ +GPIO_PinConfig gpioPinConfigs[] = { + /* input pins with callbacks */ + /* CC3220SF_LAUNCHXL_GPIO_SW2 */ + GPIOCC32XX_GPIO_13 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, + /* CC3220SF_LAUNCHXL_GPIO_SW3 */ + GPIOCC32XX_GPIO_22 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, + + /* CC3220SF_LAUNCHXL_SPI_MASTER_READY */ + GPIOCC32XX_GPIO_28 | GPIO_DO_NOT_CONFIG, + /* CC3220SF_LAUNCHXL_SPI_SLAVE_READY */ + GPIOCC32XX_GPIO_12 | GPIO_DO_NOT_CONFIG, + + /* output pins */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D10 */ + GPIOCC32XX_GPIO_09 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + + /* + * CC3220SF_LAUNCHXL_GPIO_LED_D8 and CC3220SF_LAUNCHXL_GPIO_LED_D9 are shared with the + * I2C and PWM peripherals. In order for those examples to work, these + * LEDs are taken out of gpioPinConfig[] + */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D9 */ + /* GPIOCC32XX_GPIO_10 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D8 */ + GPIOCC32XX_GPIO_11 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + + GPIOCC32XX_GPIO_30 | GPIO_DO_NOT_CONFIG, /* TMP116 EN */ + + /* Sharp Display - GPIO configurations will be done in the Display files */ + GPIOCC32XX_GPIO_12 | GPIO_DO_NOT_CONFIG, /* SPI chip select */ + GPIOCC32XX_GPIO_06 | GPIO_DO_NOT_CONFIG, /* LCD power control */ + GPIOCC32XX_GPIO_03 | GPIO_DO_NOT_CONFIG, /*LCD enable */ +}; + +/* + * Array of callback function pointers + * NOTE: The order of the pin configurations must coincide with what was + * defined in CC3220SF_LAUNCHXL.h + * NOTE: Pins not used for interrupts can be omitted from callbacks array to + * reduce memory usage (if placed at end of gpioPinConfigs array). + */ +GPIO_CallbackFxn gpioCallbackFunctions[] = { + NULL, /* CC3220SF_LAUNCHXL_GPIO_SW2 */ + NULL, /* CC3220SF_LAUNCHXL_GPIO_SW3 */ + NULL, /* CC3220SF_LAUNCHXL_SPI_MASTER_READY */ + NULL /* CC3220SF_LAUNCHXL_SPI_SLAVE_READY */ +}; + +/* The device-specific GPIO_config structure */ +const GPIOCC32XX_Config GPIOCC32XX_config = { + .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + .intPriority = (~0) +}; + +/* + * ============================= Display ============================= + */ +#include +#include +#include +#define MAXPRINTLEN 1024 + +/* This value can be changed to 96 for use with the 430BOOST-SHARP96 BoosterPack. */ +#define BOARD_DISPLAY_SHARP_SIZE 128 + +DisplayUart_Object displayUartObject; +DisplaySharp_Object displaySharpObject; + +static char displayBuf[MAXPRINTLEN]; +static uint_least8_t sharpDisplayBuf[BOARD_DISPLAY_SHARP_SIZE * BOARD_DISPLAY_SHARP_SIZE / 8]; + +const DisplayUart_HWAttrs displayUartHWAttrs = { + .uartIdx = 0, + .baudRate = 115200, + .mutexTimeout = (unsigned int)(-1), + .strBuf = displayBuf, + .strBufLen = MAXPRINTLEN +}; + +const DisplaySharp_HWAttrsV1 displaySharpHWattrs = { + .spiIndex = CC3220SF_LAUNCHXL_SPI1, + .csPin = CC3220SF_LAUNCHXL_LCD_CS, + .powerPin = CC3220SF_LAUNCHXL_LCD_POWER, + .enablePin = CC3220SF_LAUNCHXL_LCD_ENABLE, + .pixelWidth = BOARD_DISPLAY_SHARP_SIZE, + .pixelHeight = BOARD_DISPLAY_SHARP_SIZE, + .displayBuf = sharpDisplayBuf, +}; + +#ifndef BOARD_DISPLAY_USE_UART +#define BOARD_DISPLAY_USE_UART 1 +#endif +#ifndef BOARD_DISPLAY_USE_UART_ANSI +#define BOARD_DISPLAY_USE_UART_ANSI 0 +#endif +#ifndef BOARD_DISPLAY_USE_LCD +#define BOARD_DISPLAY_USE_LCD 0 +#endif + +const Display_Config Display_config[] = { + { +# if (BOARD_DISPLAY_USE_UART_ANSI) + .fxnTablePtr = &DisplayUartAnsi_fxnTable, +# else /* Default to minimal UART with no cursor placement */ + .fxnTablePtr = &DisplayUartMin_fxnTable, +# endif + .object = &displayUartObject, + .hwAttrs = &displayUartHWAttrs + }, +#if (BOARD_DISPLAY_USE_LCD) + { + .fxnTablePtr = &DisplaySharp_fxnTable, + .object = &displaySharpObject, + .hwAttrs = &displaySharpHWattrs + }, +#endif +}; + +const uint_least8_t Display_count = sizeof(Display_config) / sizeof(Display_Config); + + + +/* + * =============================== I2C =============================== + */ +#include +#include + +I2CCC32XX_Object i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2CCOUNT]; + +const I2CCC32XX_HWAttrsV1 i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2CCOUNT] = { + { + .baseAddr = I2CA0_BASE, + .intNum = INT_I2CA0, + .intPriority = (~0), + .clkPin = I2CCC32XX_PIN_01_I2C_SCL, + .dataPin = I2CCC32XX_PIN_02_I2C_SDA + } +}; + +const I2C_Config I2C_config[CC3220SF_LAUNCHXL_I2CCOUNT] = { + { + .fxnTablePtr = &I2CCC32XX_fxnTable, + .object = &i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2C0], + .hwAttrs = &i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2C0] + } +}; + +const uint_least8_t I2C_count = CC3220SF_LAUNCHXL_I2CCOUNT; + +/* + * =============================== I2S =============================== + */ +#include +#include + +I2SCC32XXDMA_Object i2sCC3220SObjects[CC3220SF_LAUNCHXL_I2SCOUNT]; + +const I2SCC32XXDMA_HWAttrsV1 i2sCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2SCOUNT] = { + { + .baseAddr = I2S_BASE, + .intNum = INT_I2S, + .intPriority = (~0), + .rxChannelIndex = UDMA_CH4_I2S_RX, + .txChannelIndex = UDMA_CH5_I2S_TX, + .xr0Pin = I2SCC32XXDMA_PIN_64_McAXR0, + .xr1Pin = I2SCC32XXDMA_PIN_50_McAXR1, + .clkxPin = I2SCC32XXDMA_PIN_62_McACLKX, + .clkPin = I2SCC32XXDMA_PIN_53_McACLK, + .fsxPin = I2SCC32XXDMA_PIN_63_McAFSX, + } +}; + +const I2S_Config I2S_config[CC3220SF_LAUNCHXL_I2SCOUNT] = { + { + .fxnTablePtr = &I2SCC32XXDMA_fxnTable, + .object = &i2sCC3220SObjects[CC3220SF_LAUNCHXL_I2S0], + .hwAttrs = &i2sCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2S0] + } +}; + +const uint_least8_t I2S_count = CC3220SF_LAUNCHXL_I2SCOUNT; + +/* + * =============================== Power =============================== + */ +/* + * This table defines the parking state to be set for each parkable pin + * during LPDS. (Device pins must be parked during LPDS to achieve maximum + * power savings.) If the pin should be left unparked, specify the state + * PowerCC32XX_DONT_PARK. For example, for a UART TX pin, the device + * will automatically park the pin in a high state during transition to LPDS, + * so the Power Manager does not need to explictly park the pin. So the + * corresponding entries in this table should indicate PowerCC32XX_DONT_PARK. + */ +PowerCC32XX_ParkInfo parkInfo[] = { +/* PIN PARK STATE PIN ALIAS (FUNCTION) + ----------------- ------------------------------ -------------------- */ + {PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10 */ + {PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11 */ + {PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12 */ + {PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13 */ + {PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14 */ + {PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15 */ + {PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16 */ + {PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17 */ + {PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN */ + {PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22 */ + {PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG) */ + {PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG) */ + {PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG) */ + {PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG) */ + {PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28 */ + {PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2 */ + {PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1 */ + {PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2 */ + {PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P */ + {PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0 */ + {PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N */ + {PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30 */ + {PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO1 (XDS_UART_RX) */ + {PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO2 (XDS_UART_TX) */ + {PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3 */ + {PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4 */ + {PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5 */ + {PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6 */ + {PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7 */ + {PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8 */ + {PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9 */ +}; + +/* + * This structure defines the configuration for the Power Manager. + * + * In this configuration the Power policy is disabled by default (because + * enablePolicy is set to false). The Power policy can be enabled dynamically + * at runtime by calling Power_enablePolicy(), or at build time, by changing + * enablePolicy to true in this structure. + */ +const PowerCC32XX_ConfigV1 PowerCC32XX_config = { + .policyInitFxn = &PowerCC32XX_initPolicy, + .policyFxn = &PowerCC32XX_sleepPolicy, + .enterLPDSHookFxn = NULL, + .resumeLPDSHookFxn = NULL, + .enablePolicy = false, + .enableGPIOWakeupLPDS = true, + .enableGPIOWakeupShutdown = true, + .enableNetworkWakeupLPDS = true, + .wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13, + .wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE, + .wakeupGPIOFxnLPDS = NULL, + .wakeupGPIOFxnLPDSArg = 0, + .wakeupGPIOSourceShutdown = PRCM_HIB_GPIO13, + .wakeupGPIOTypeShutdown = PRCM_HIB_RISE_EDGE, + .ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 | + PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4, + .keepDebugActiveDuringLPDS = false, + .ioRetentionShutdown = PRCM_IO_RET_GRP_1, + .pinParkDefs = parkInfo, + .numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo) +}; + +/* + * =============================== PWM =============================== + */ +#include +#include + +PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; + +const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { + { /* CC3220SF_LAUNCHXL_PWM6 */ + .pwmPin = PWMTimerCC32XX_PIN_01 + }, + { /* CC3220SF_LAUNCHXL_PWM7 */ + .pwmPin = PWMTimerCC32XX_PIN_02 + } +}; + +const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] + }, + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] + } +}; + +const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; + +/* + * =============================== SDFatFS =============================== + */ +#include +#include + +/* + * Note: The SDFatFS driver provides interface functions to enable FatFs + * but relies on the SD driver to communicate with SD cards. Opening a + * SDFatFs driver instance will internally try to open a SD driver instance + * reusing the same index number (opening SDFatFs driver at index 0 will try to + * open SD driver at index 0). This requires that all SDFatFs driver instances + * have an accompanying SD driver instance defined with the same index. It is + * acceptable to have more SD driver instances than SDFatFs driver instances + * but the opposite is not supported & the SDFatFs will fail to open. + */ +SDFatFS_Object sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFSCOUNT]; + +const SDFatFS_Config SDFatFS_config[CC3220SF_LAUNCHXL_SDFatFSCOUNT] = { + { + .object = &sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFS0] + } +}; + +const uint_least8_t SDFatFS_count = CC3220SF_LAUNCHXL_SDFatFSCOUNT; + +/* + * =============================== SD =============================== + */ +#include +#include + +SDHostCC32XX_Object sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SDCOUNT]; + +/* SDHost configuration structure, describing which pins are to be used */ +const SDHostCC32XX_HWAttrsV1 sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SDCOUNT] = { + { + .clkRate = 8000000, + .intPriority = ~0, + .baseAddr = SDHOST_BASE, + .rxChIdx = UDMA_CH23_SDHOST_RX, + .txChIdx = UDMA_CH24_SDHOST_TX, + .dataPin = SDHostCC32XX_PIN_06_SDCARD_DATA, + .cmdPin = SDHostCC32XX_PIN_08_SDCARD_CMD, + .clkPin = SDHostCC32XX_PIN_07_SDCARD_CLK + } +}; + +const SD_Config SD_config[CC3220SF_LAUNCHXL_SDCOUNT] = { + { + .fxnTablePtr = &sdHostCC32XX_fxnTable, + .object = &sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SD0], + .hwAttrs = &sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SD0] + }, +}; + +const uint_least8_t SD_count = CC3220SF_LAUNCHXL_SDCOUNT; + +/* + * =============================== SPI =============================== + */ +#include +#include + +SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT]; + +uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT]; + +const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = { + /* index 0 is reserved for LSPI that links to the NWP */ + { + .baseAddr = LSPI_BASE, + .intNum = INT_LSPI, + .intPriority = (~0), + .spiPRCM = PRCM_LSPI, + .csControl = SPI_SW_CTRL_CS, + .csPolarity = SPI_CS_ACTIVEHIGH, + .pinMode = SPI_4PIN_MODE, + .turboMode = SPI_TURBO_OFF, + .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CH12_LSPI_RX, + .txChannelIndex = UDMA_CH13_LSPI_TX, + .minDmaTransferSize = 100, + .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG, + .misoPin = SPICC32XXDMA_PIN_NO_CONFIG, + .clkPin = SPICC32XXDMA_PIN_NO_CONFIG, + .csPin = SPICC32XXDMA_PIN_NO_CONFIG + }, + { + .baseAddr = GSPI_BASE, + .intNum = INT_GSPI, + .intPriority = (~0), + .spiPRCM = PRCM_GSPI, + .csControl = SPI_HW_CTRL_CS, + .csPolarity = SPI_CS_ACTIVELOW, + .pinMode = SPI_4PIN_MODE, + .turboMode = SPI_TURBO_OFF, + .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CH6_GSPI_RX, + .txChannelIndex = UDMA_CH7_GSPI_TX, + .minDmaTransferSize = 10, + .mosiPin = SPICC32XXDMA_PIN_07_MOSI, + .misoPin = SPICC32XXDMA_PIN_06_MISO, + .clkPin = SPICC32XXDMA_PIN_05_CLK, + .csPin = SPICC32XXDMA_PIN_08_CS + } +}; + +const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = { + { + .fxnTablePtr = &SPICC32XXDMA_fxnTable, + .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0], + .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0] + }, + { + .fxnTablePtr = &SPICC32XXDMA_fxnTable, + .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1], + .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1] + } +}; + +const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT; + +/* + * =============================== Timer =============================== + */ +#include +#include + +TimerCC32XX_Object timerCC3220SFObjects[CC3220SF_LAUNCHXL_TIMERCOUNT]; + +const TimerCC32XX_HWAttrs timerCC3220SFHWAttrs[CC3220SF_LAUNCHXL_TIMERCOUNT] = { + { + .baseAddress = TIMERA0_BASE, + .subTimer = TimerCC32XX_timer32, + .intNum = INT_TIMERA0A, + .intPriority = ~0 + }, + { + .baseAddress = TIMERA1_BASE, + .subTimer = TimerCC32XX_timer16A, + .intNum = INT_TIMERA1A, + .intPriority = ~0 + }, + { + .baseAddress = TIMERA1_BASE, + .subTimer = TimerCC32XX_timer16B, + .intNum = INT_TIMERA1B, + .intPriority = ~0 + }, +}; + +const Timer_Config Timer_config[CC3220SF_LAUNCHXL_TIMERCOUNT] = { + { + .fxnTablePtr = &TimerCC32XX_fxnTable, + .object = &timerCC3220SFObjects[CC3220SF_LAUNCHXL_TIMER0], + .hwAttrs = &timerCC3220SFHWAttrs[CC3220SF_LAUNCHXL_TIMER0] + }, + { + .fxnTablePtr = &TimerCC32XX_fxnTable, + .object = &timerCC3220SFObjects[CC3220SF_LAUNCHXL_TIMER1], + .hwAttrs = &timerCC3220SFHWAttrs[CC3220SF_LAUNCHXL_TIMER1] + }, + { + .fxnTablePtr = &TimerCC32XX_fxnTable, + .object = &timerCC3220SFObjects[CC3220SF_LAUNCHXL_TIMER2], + .hwAttrs = &timerCC3220SFHWAttrs[CC3220SF_LAUNCHXL_TIMER2] + }, +}; + +const uint_least8_t Timer_count = CC3220SF_LAUNCHXL_TIMERCOUNT; + +/* + * =============================== UART =============================== + */ +#include +#if TI_DRIVERS_UART_DMA +#include + +UARTCC32XXDMA_Object uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UARTCOUNT]; + +/* UART configuration structure */ +const UARTCC32XXDMA_HWAttrsV1 uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .baseAddr = UARTA0_BASE, + .intNum = INT_UARTA0, + .intPriority = (~0), + .flowControl = UARTCC32XXDMA_FLOWCTRL_NONE, + .rxChannelIndex = UDMA_CH8_UARTA0_RX, + .txChannelIndex = UDMA_CH9_UARTA0_TX, + .rxPin = UARTCC32XXDMA_PIN_57_UART0_RX, + .txPin = UARTCC32XXDMA_PIN_55_UART0_TX, + .ctsPin = UARTCC32XXDMA_PIN_UNASSIGNED, + .rtsPin = UARTCC32XXDMA_PIN_UNASSIGNED, + .errorFxn = NULL + }, + { + .baseAddr = UARTA1_BASE, + .intNum = INT_UARTA1, + .intPriority = (~0), + .flowControl = UARTCC32XXDMA_FLOWCTRL_NONE, + .rxChannelIndex = UDMA_CH10_UARTA1_RX, + .txChannelIndex = UDMA_CH11_UARTA1_TX, + .rxPin = UARTCC32XXDMA_PIN_08_UART1_RX, + .txPin = UARTCC32XXDMA_PIN_07_UART1_TX, + .ctsPin = UARTCC32XXDMA_PIN_UNASSIGNED, + .rtsPin = UARTCC32XXDMA_PIN_UNASSIGNED, + .errorFxn = NULL + } +}; + +const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .fxnTablePtr = &UARTCC32XXDMA_fxnTable, + .object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART0], + .hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART0] + }, + { + .fxnTablePtr = &UARTCC32XXDMA_fxnTable, + .object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART1], + .hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART1] + } +}; + +#else +#include + +UARTCC32XX_Object uartCC3220SObjects[CC3220SF_LAUNCHXL_UARTCOUNT]; +unsigned char uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UARTCOUNT][32]; + +/* UART configuration structure */ +const UARTCC32XX_HWAttrsV1 uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .baseAddr = UARTA0_BASE, + .intNum = INT_UARTA0, + .intPriority = (~0), + .flowControl = UARTCC32XX_FLOWCTRL_NONE, + .ringBufPtr = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0], + .ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0]), + .rxPin = UARTCC32XX_PIN_57_UART0_RX, + .txPin = UARTCC32XX_PIN_55_UART0_TX, + .ctsPin = UARTCC32XX_PIN_UNASSIGNED, + .rtsPin = UARTCC32XX_PIN_UNASSIGNED, + .errorFxn = NULL + }, + { + .baseAddr = UARTA1_BASE, + .intNum = INT_UARTA1, + .intPriority = (~0), + .flowControl = UARTCC32XX_FLOWCTRL_NONE, + .ringBufPtr = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1], + .ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1]), + .rxPin = UARTCC32XX_PIN_08_UART1_RX, + .txPin = UARTCC32XX_PIN_07_UART1_TX, + .ctsPin = UARTCC32XX_PIN_UNASSIGNED, + .rtsPin = UARTCC32XX_PIN_UNASSIGNED, + .errorFxn = NULL + } +}; + +const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .fxnTablePtr = &UARTCC32XX_fxnTable, + .object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART0], + .hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART0] + }, + { + .fxnTablePtr = &UARTCC32XX_fxnTable, + .object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART1], + .hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART1] + } +}; +#endif /* TI_DRIVERS_UART_DMA */ + +const uint_least8_t UART_count = CC3220SF_LAUNCHXL_UARTCOUNT; + +/* + * =============================== Watchdog =============================== + */ +#include +#include + +WatchdogCC32XX_Object watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOGCOUNT]; + +const WatchdogCC32XX_HWAttrs watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = { + { + .baseAddr = WDT_BASE, + .intNum = INT_WDT, + .intPriority = (~0), + .reloadValue = 80000000 /* 1 second period at default CPU clock freq */ + } +}; + +const Watchdog_Config Watchdog_config[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = { + { + .fxnTablePtr = &WatchdogCC32XX_fxnTable, + .object = &watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOG0], + .hwAttrs = &watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOG0] + } +}; + +const uint_least8_t Watchdog_count = CC3220SF_LAUNCHXL_WATCHDOGCOUNT; + +/* + * ======== Board_debugHeader ======== + * This structure prevents the CC32XXSF bootloader from overwriting the + * internal FLASH; this allows us to flash a program that will not be + * overwritten by the bootloader with the encrypted program saved in + * "secure/serial flash". + * + * This structure must be placed at the beginning of internal FLASH (so + * the bootloader is able to recognize that it should not overwrite + * internal FLASH). + */ +#if defined (__SF_DEBUG__) || defined(__SF_NODEBUG__) +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(Board_debugHeader, ".dbghdr") +#pragma RETAIN(Board_debugHeader) +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma location=".dbghdr" +#elif defined(__GNUC__) +__attribute__ ((section (".dbghdr"))) +#endif +#if defined(__SF_DEBUG__) +const uint32_t Board_debugHeader[] = { + 0x5AA5A55A, + 0x000FF800, + 0xEFA3247D +}; +#elif defined (__SF_NODEBUG__) +const uint32_t Board_debugHeader[] = { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF +}; +#endif +#endif diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h new file mode 100644 index 0000000000..5ca85f3ccb --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2016-2018, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file C3220SF_LAUNCHXL.h + * + * @brief CC3220 Board Specific APIs + * + * The CC3220SF_LAUNCHXL header file should be included in an application as + * follows: + * @code + * #include + * @endcode + * + * ============================================================================ + */ +#ifndef __CC3220SF_LAUNCHXL_H +#define __CC3220SF_LAUNCHXL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define CC3220SF_LAUNCHXL_GPIO_LED_OFF (0) +#define CC3220SF_LAUNCHXL_GPIO_LED_ON (1) + +/*! + * @def CC3220SF_LAUNCHXL_ADCName + * @brief Enum of ADC names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_ADCName { + CC3220SF_LAUNCHXL_ADC0 = 0, + CC3220SF_LAUNCHXL_ADC1, + + CC3220SF_LAUNCHXL_ADCCOUNT +} CC3220SF_LAUNCHXL_ADCName; + +/*! + * @def CC3220SF_LAUNCHXL_CaptureName + * @brief Enum of Capture names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_CaptureName { + CC3220SF_LAUNCHXL_CAPTURE0 = 0, + CC3220SF_LAUNCHXL_CAPTURE1, + + CC3220SF_LAUNCHXL_CAPTURECOUNT +} CC3220SF_LAUNCHXL_CaptureName; + +/*! + * @def CC3220SF_LAUNCHXL_CryptoName + * @brief Enum of Crypto names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_CryptoName { + CC3220SF_LAUNCHXL_CRYPTO0 = 0, + + CC3220SF_LAUNCHXL_CRYPTOCOUNT +} CC3220SF_LAUNCHXL_CryptoName; + +/*! + * @def CC3220SF_LAUNCHXL_GPIOName + * @brief Enum of GPIO names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_GPIOName { + CC3220SF_LAUNCHXL_GPIO_SW2 = 0, + CC3220SF_LAUNCHXL_GPIO_SW3, + CC3220SF_LAUNCHXL_SPI_MASTER_READY, + CC3220SF_LAUNCHXL_SPI_SLAVE_READY, + CC3220SF_LAUNCHXL_GPIO_LED_D10, + + /* + * CC3220SF_LAUNCHXL_GPIO_LED_D8 and CC3220SF_LAUNCHXL_GPIO_LED_D9 are shared with the + * I2C and PWM peripherals. In order for those examples to work, these + * LEDs are taken out of gpioPinCOnfig[] + */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D9, */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D8, */ + + CC3220SF_LAUNCHXL_GPIO_TMP116_EN, + + /* Sharp LCD Pins */ + CC3220SF_LAUNCHXL_LCD_CS, + CC3220SF_LAUNCHXL_LCD_POWER, + CC3220SF_LAUNCHXL_LCD_ENABLE, + + CC3220SF_LAUNCHXL_GPIOCOUNT +} CC3220SF_LAUNCHXL_GPIOName; + +/*! + * @def CC3220SF_LAUNCHXL_I2CName + * @brief Enum of I2C names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_I2CName { + CC3220SF_LAUNCHXL_I2C0 = 0, + + CC3220SF_LAUNCHXL_I2CCOUNT +} CC3220SF_LAUNCHXL_I2CName; + +/*! + * @def CC3220SF_LAUNCHXL_I2SName + * @brief Enum of I2S names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_I2SName { + CC3220SF_LAUNCHXL_I2S0 = 0, + + CC3220SF_LAUNCHXL_I2SCOUNT +} CC3220SF_LAUNCHXL_I2SName; + +/*! + * @def CC3220SF_LAUNCHXL_PWMName + * @brief Enum of PWM names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_PWMName { + CC3220SF_LAUNCHXL_PWM6 = 0, + CC3220SF_LAUNCHXL_PWM7, + + CC3220SF_LAUNCHXL_PWMCOUNT +} CC3220SF_LAUNCHXL_PWMName; + +/*! + * @def CC3220SF_LAUNCHXL_SDFatFSName + * @brief Enum of SDFatFS names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDFatFSName { + CC3220SF_LAUNCHXL_SDFatFS0 = 0, + + CC3220SF_LAUNCHXL_SDFatFSCOUNT +} CC3220SF_LAUNCHXL_SDFatFSName; + +/*! + * @def CC3220SF_LAUNCHXL_SDName + * @brief Enum of SD names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDName { + CC3220SF_LAUNCHXL_SD0 = 0, + + CC3220SF_LAUNCHXL_SDCOUNT +} CC3220SF_LAUNCHXL_SDName; + +/*! + * @def CC3220SF_LAUNCHXL_SPIName + * @brief Enum of SPI names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SPIName { + CC3220SF_LAUNCHXL_SPI0 = 0, + CC3220SF_LAUNCHXL_SPI1, + + CC3220SF_LAUNCHXL_SPICOUNT +} CC3220SF_LAUNCHXL_SPIName; + +/*! + * @def CC3220SF_LAUNCHXL_TimerName + * @brief Enum of Timer names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_TimerName { + CC3220SF_LAUNCHXL_TIMER0 = 0, + CC3220SF_LAUNCHXL_TIMER1, + CC3220SF_LAUNCHXL_TIMER2, + + CC3220SF_LAUNCHXL_TIMERCOUNT +} CC3220SF_LAUNCHXL_TimerName; + +/*! + * @def CC3220SF_LAUNCHXL_UARTName + * @brief Enum of UARTs on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_UARTName { + CC3220SF_LAUNCHXL_UART0 = 0, + CC3220SF_LAUNCHXL_UART1, + + CC3220SF_LAUNCHXL_UARTCOUNT +} CC3220SF_LAUNCHXL_UARTName; + +/*! + * @def CC3220SF_LAUNCHXL_WatchdogName + * @brief Enum of Watchdogs on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_WatchdogName { + CC3220SF_LAUNCHXL_WATCHDOG0 = 0, + + CC3220SF_LAUNCHXL_WATCHDOGCOUNT +} CC3220SF_LAUNCHXL_WatchdogName; + +/*! + * @brief Initialize the general board specific settings + * + * This function initializes the general board specific settings. + */ +extern void CC3220SF_LAUNCHXL_initGeneral(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CC3220SF_LAUNCHXL_H */ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt index e2d046934e..121f74dfd1 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt @@ -45,6 +45,7 @@ add_executable( ${NANOCLR_PROJECT_NAME}.elf "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/CC3220SF_LAUNCHXL.c" ${COMMON_PROJECT_SOURCES} ${NANOCLR_PROJECT_SOURCES} From b8c417658a09c0a065ecc69aeb7619221e5ff152 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Feb 2019 14:31:18 +0000 Subject: [PATCH 29/90] Add Devices.Gpio implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../win_dev_gpio_native.cpp | 85 ++++ .../win_dev_gpio_native.h | 92 ++++ ...ve_Windows_Devices_Gpio_GpioController.cpp | 19 + ...io_native_Windows_Devices_Gpio_GpioPin.cpp | 446 ++++++++++++++++++ 4 files changed, 642 insertions(+) create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.h create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp new file mode 100644 index 0000000000..defcbb4918 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp @@ -0,0 +1,85 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_gpio_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController::get_PinCount___I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Read___WindowsDevicesGpioGpioPinValue, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Toggle___VOID, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::DisposeNative___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeInit___BOOLEAN__I4, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDebounceTimeout___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::WriteNative___VOID__WindowsDevicesGpioGpioPinValue, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetAlternateFunction___VOID__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Gpio = +{ + "Windows.Devices.Gpio", + 0xB1F30A6A, + method_lookup, + { 1, 0, 5, 1 } +}; diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.h b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.h new file mode 100644 index 0000000000..91b387a43c --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.h @@ -0,0 +1,92 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_GPIO_NATIVE_H_ +#define _WIN_DEV_GPIO_NATIVE_H_ + +#include +#include +#include + +#include "rom.h" +#include "rom_map.h" +#include +#include +#include +#include +#include +#include + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_instance = 1; + + NANOCLR_NATIVE_DECLARE(get_PinCount___I4); + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin +{ + static const int FIELD_STATIC__s_eventListener = 2; + + static const int FIELD___syncLock = 1; + static const int FIELD___pinNumber = 2; + static const int FIELD___driveMode = 3; + static const int FIELD___debounceTimeout = 4; + static const int FIELD___callbacks = 5; + static const int FIELD___lastOutputValue = 6; + static const int FIELD___lastInputValue = 7; + static const int FIELD___disposedValue = 8; + + NANOCLR_NATIVE_DECLARE(Read___WindowsDevicesGpioGpioPinValue); + NANOCLR_NATIVE_DECLARE(Toggle___VOID); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode); + NANOCLR_NATIVE_DECLARE(NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode); + NANOCLR_NATIVE_DECLARE(NativeInit___BOOLEAN__I4); + NANOCLR_NATIVE_DECLARE(NativeSetDebounceTimeout___VOID); + NANOCLR_NATIVE_DECLARE(WriteNative___VOID__WindowsDevicesGpioGpioPinValue); + NANOCLR_NATIVE_DECLARE(NativeSetAlternateFunction___VOID__I4); + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinEvent +{ + static const int FIELD__PinNumber = 3; + static const int FIELD__Edge = 4; + + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinEventListener +{ + static const int FIELD___pinMap = 1; + + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinValueChangedEventArgs +{ + static const int FIELD___edge = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Gpio; + +#endif //_WIN_DEV_GPIO_NATIVE_H_ diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp new file mode 100644 index 0000000000..6987df124b --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp @@ -0,0 +1,19 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_gpio_native.h" + + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // return count ot available GPIO pins + stack.SetResult_I4( 256 ); // Fixme: temporary arbitrary value + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp new file mode 100644 index 0000000000..e6b3a5c6c1 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp @@ -0,0 +1,446 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_gpio_native.h" +#include "nf_rt_events_native.h" + +#include + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Gpio.GpioPinDriveMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum GpioPinDriveMode +{ + GpioPinDriveMode_Input = 0, + GpioPinDriveMode_InputPullDown, + GpioPinDriveMode_InputPullUp, + GpioPinDriveMode_Output, + GpioPinDriveMode_OutputOpenDrain, + GpioPinDriveMode_OutputOpenDrainPullUp, + GpioPinDriveMode_OutputOpenSource, + GpioPinDriveMode_OutputOpenSourcePullDown +}; + +/////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Gpio.GpioPinValue (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////// + +enum GpioPinValue +{ + GpioPinValue_Low = 0, + GpioPinValue_High, +}; + +/////////////////////////////////////////////////////////////////////////////////// + +// this array points to the GPIO managed object that has interrupt active +CLR_RT_HeapBlock* indexPinMapping[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + +// this array points to the active debounce timers +TimerHandle_t debounceTimerMapping[ARRAYSIZE_CONST_EXPR(indexPinMapping)]; + +// this arrays points to the last read value to be used by the debounce timers +uint_fast8_t lastReadValueMapping[ARRAYSIZE_CONST_EXPR(indexPinMapping)]; + +static void debounceTimer_Callback(TimerHandle_t xTimer) +{ + (void)xTimer; + + int16_t index; + + // loop through timers to find the index for this + for(index = 0; index < ARRAYSIZE_CONST_EXPR(indexPinMapping); index++) + { + if(debounceTimerMapping[index] == xTimer) + { + // found it! + + // get current value + uint_fast8_t currentValue = GPIO_read(index); + + // get last read value + uint_fast8_t lastRead = (uint_fast8_t) pvTimerGetTimerID( xTimer ); + + if(lastRead == currentValue) + { + // value hasn't change during debounce interval so this is a valid change + + // get managed GPIO object + CLR_RT_HeapBlock* pThis = (CLR_RT_HeapBlock*)indexPinMapping[index]; + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___callbacks ].Dereference() != NULL); + + // post a managed event with the current pin value, only if there is anyone listening otherwise don't bother + if(callbacksRegistered) + { + PostManagedEvent( EVENT_GPIO, 0, index, currentValue ); + } + } + + xTimerDelete(xTimer, 0); + } + } +} + +static void GpioEventCallback(uint_least8_t index) +{ + NATIVE_INTERRUPT_START + + CLR_RT_HeapBlock* pThis = indexPinMapping[index]; + + if(pThis == NULL) + { + // no Gpio pin here, leave now + NATIVE_INTERRUPT_END + return; + } + + // check if object has been disposed + if( pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + // object has been disposed, leave now + NATIVE_INTERRUPT_END + return; + } + + // check if there is a debounce time set + int64_t debounceTimeoutMilsec = (CLR_INT64_TEMP_CAST) pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___debounceTimeout ].NumericByRefConst().s8 / TIME_CONVERSION__TO_MILLISECONDS; + + // store current value + uint_fast8_t lastRead = GPIO_read(index); + + if(debounceTimeoutMilsec > 0) + { + // debounce set, need to handle it + + if(debounceTimerMapping[index] != NULL) + { + // there is a debounce timer already running so this change in pin value should be discarded + NATIVE_INTERRUPT_END + return; + } + + // setup timer + debounceTimerMapping[index] = xTimerCreate( NULL, (debounceTimeoutMilsec / portTICK_PERIOD_MS), pdFALSE, (void*)lastRead, debounceTimer_Callback); + xTimerStart(debounceTimerMapping[index], 0); + } + else + { + // read pin + pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___lastInputValue ].NumericByRef().s4 = lastRead; + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___callbacks ].Dereference() != NULL); + + // post a managed event with the current pin reading, only if there is anyone listening otherwise don't bother + if(callbacksRegistered) + { + PostManagedEvent( EVENT_GPIO, 0, index, lastRead ); + } + } + + NATIVE_INTERRUPT_END +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Read___WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + stack.SetResult_I4(GPIO_read(pinNumber)); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Toggle___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[ FIELD___driveMode ].NumericByRefConst().s4; + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + GPIO_toggle(pinNumber); + + // store new state + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = (GpioPinValue)(GpioPinValue_High ^ (GpioPinValue)pThis[ FIELD___lastOutputValue ].NumericByRef().s4); + } + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + // it's OK to do always this, no matter if interrupts are enabled or not + // disable interrupts + GPIO_disableInt(pinNumber); + + // clear assignment + indexPinMapping[pinNumber] = NULL; + + // set pin to input to save power + GPIO_setConfig(pinNumber, GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_NONE); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + GpioPinDriveMode driveMode = (GpioPinDriveMode)stack.Arg1().NumericByRef().s4; + + bool driveModeSupported = false; + + // check if the requested drive mode is supported by SimpleLink + if ((driveMode == GpioPinDriveMode_Input) || + (driveMode == GpioPinDriveMode_InputPullDown) || + (driveMode == GpioPinDriveMode_InputPullUp) || + (driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + driveModeSupported = true; + } + + // Return value to the managed application + stack.SetResult_Boolean( driveModeSupported ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // get pin number + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + // it's better cast this this to the appropriate enum + GpioPinDriveMode driveMode = (GpioPinDriveMode)stack.Arg1().NumericByRef().s4; + + // check if drive mode is input + bool driveModeIsInput = false; + + if( driveMode == GpioPinDriveMode_Input || + driveMode == GpioPinDriveMode_InputPullDown || + driveMode == GpioPinDriveMode_InputPullUp) + { + driveModeIsInput = true; + } + + // flag to signal that interrupts need to be setup + bool setupInterrupt = false; + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ FIELD___callbacks ].Dereference() != NULL); + + // disable interrupt as default + GPIO_disableInt(pinNumber); + + switch (driveMode) + { + case GpioPinDriveMode_Input: + GPIO_setConfig(pinNumber, GPIO_CFG_IN_NOPULL); + setupInterrupt = true; + break; + + case GpioPinDriveMode_InputPullDown: + GPIO_setConfig(pinNumber, GPIO_CFG_IN_PD); + setupInterrupt = true; + break; + + case GpioPinDriveMode_InputPullUp: + GPIO_setConfig(pinNumber, GPIO_CFG_IN_PU); + setupInterrupt = true; + break; + + case GpioPinDriveMode_Output: + GPIO_setConfig(pinNumber, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_LOW); + break; + + case GpioPinDriveMode_OutputOpenDrain: + GPIO_setConfig(pinNumber, GPIO_CFG_OUT_OD_NOPULL); + break; + + case GpioPinDriveMode_OutputOpenDrainPullUp: + GPIO_setConfig(pinNumber, GPIO_CFG_OUT_OD_PU); + break; + + case GpioPinDriveMode_OutputOpenSourcePullDown: + GPIO_setConfig(pinNumber, GPIO_CFG_OUT_OD_PD); + break; + + default: + // all other modes are NOT supported + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // if drive mode is output, read the pad to update the managed field _lastOutputValue + if(!driveModeIsInput) + { + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = GPIO_read(pinNumber); + } + + if(callbacksRegistered && setupInterrupt) + { + // there are callbacks registered and... + // the drive mode is input so need to setup the interrupt + + // save pin + indexPinMapping[pinNumber] = pThis; + + // get current config + GPIO_PinConfig currentPinConfig; + GPIO_getConfig(pinNumber, ¤tPinConfig); + + // set interrupt on both edges + GPIO_setConfig(pinNumber, currentPinConfig | GPIO_CFG_IN_INT_BOTH_EDGES); + GPIO_setCallback(pinNumber, &GpioEventCallback); + + GPIO_enableInt(pinNumber); + + // protect this from GC so that the callback is where it's supposed to + CLR_RT_ProtectFromGC gc( *pThis ); + } + else + { + // clear assignment + indexPinMapping[pinNumber] = NULL; + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeInit___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int16_t pinNumber = stack.Arg1().NumericByRef().s4; + + // TODO is probably a good idea keep track of the used pins, so we can check that here + // TODO is probably a good idea to check if this pin exists + + // clear assignment, to make sure it's empty + indexPinMapping[pinNumber] = NULL; + + // Return value to the managed application + stack.SetResult_Boolean(true ); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDebounceTimeout___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // nothing to do here as the debounce timeout is grabbed from the managed object when required + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::WriteNative___VOID__WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[ FIELD___driveMode ].NumericByRefConst().s4; + + GpioPinValue state = (GpioPinValue)stack.Arg1().NumericByRef().s4; + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + GPIO_write(pinNumber, state); + + // store new state + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = state; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetAlternateFunction___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + // get alternate function argument + int32_t alternateFunction = stack.Arg1().NumericByRef().s4; + + GPIO_setConfig(pinNumber, alternateFunction); + + } + NANOCLR_NOCLEANUP(); +} From 1d7168ed63b1b5e4277fd3b424b576db1a127d98 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 22 Feb 2019 12:35:14 +0000 Subject: [PATCH 30/90] Implement target implementation of time and hal inline functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Increase size of CLR region storage Signed-off-by: José Simões --- targets/TI-SimpleLink/Include/targetHAL.h | 16 -------- .../common/Device_BlockStorage-DEBUG.c | 4 +- .../nanoCLR/CC3220SF_CLR-DEBUG.ld | 2 +- targets/TI-SimpleLink/common/CMakeLists.txt | 4 ++ targets/TI-SimpleLink/common/platformHAL.c | 37 +++++++++++++++++++ .../TI-SimpleLink/common/platformHAL_Time.cpp | 21 +++++++++++ .../TI-SimpleLink/nanoCLR/targetHAL_Time.cpp | 6 --- 7 files changed, 65 insertions(+), 25 deletions(-) create mode 100644 targets/TI-SimpleLink/common/platformHAL.c create mode 100644 targets/TI-SimpleLink/common/platformHAL_Time.cpp diff --git a/targets/TI-SimpleLink/Include/targetHAL.h b/targets/TI-SimpleLink/Include/targetHAL.h index 880267d9ee..09d9249464 100644 --- a/targets/TI-SimpleLink/Include/targetHAL.h +++ b/targets/TI-SimpleLink/Include/targetHAL.h @@ -7,7 +7,6 @@ #define _TARGET_HAL_H_ #include -#include #define GLOBAL_LOCK(x) portENTER_CRITICAL(); #define GLOBAL_UNLOCK(x) portEXIT_CRITICAL(); @@ -31,8 +30,6 @@ #if !defined(BUILD_RTM) -inline void HARD_Breakpoint() { }; - #define HARD_BREAKPOINT() HARD_Breakpoint() // #if defined(_DEBUG) @@ -48,21 +45,8 @@ inline void HARD_Breakpoint() { }; #endif // !defined(BUILD_RTM) -inline bool Target_HasNanoBooter() { return false; }; - #define NANOCLR_STOP() HARD_BREAKPOINT() -inline void HAL_AssertEx() -{ - __asm__("BKPT"); - while(true) { /*nop*/ } -} - -// Provides information whether the configuration block storage requires erase command before sending the update command -// The 'weak' implementation for TI SimpleLink targets is false -// If a target implements the store differently it has to provide a 'strong' implementation of this. -__nfweak bool Target_ConfigUpdateRequiresErase() { return false; }; - extern int HeapBegin; extern int HeapEnd; diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index aa0108fbf1..795ac7e3e1 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -11,8 +11,8 @@ const BlockRange BlockRange1[] = { // the 1st block is reserved for the flash header // so we don't take it into account for the map - { BlockRange_BLOCKTYPE_CODE , 0 , 101 }, // 0x01000800 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT , 102, 510 }, // 0x01033000 deployment + { BlockRange_BLOCKTYPE_CODE , 0 , 105 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 106, 510 }, // 0x01035000 deployment }; const BlockRegionInfo BlockRegions[] = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index 9488a17881..f621df06de 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x032800 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x035000 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } diff --git a/targets/TI-SimpleLink/common/CMakeLists.txt b/targets/TI-SimpleLink/common/CMakeLists.txt index dc25728d4f..a2c7e14fba 100644 --- a/targets/TI-SimpleLink/common/CMakeLists.txt +++ b/targets/TI-SimpleLink/common/CMakeLists.txt @@ -17,5 +17,9 @@ list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Fre # list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/GenericPort.cpp") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/syscalls.c") +# append nanoHAL +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platformHAL.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platformHAL_Time.cpp") + # make var global set(TARGET_TI_SimpleLink_COMMON_SOURCES ${TARGET_TI_SimpleLink_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/TI-SimpleLink/common/platformHAL.c b/targets/TI-SimpleLink/common/platformHAL.c new file mode 100644 index 0000000000..7c8c986d2d --- /dev/null +++ b/targets/TI-SimpleLink/common/platformHAL.c @@ -0,0 +1,37 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +void HAL_AssertEx() +{ + __asm__("BKPT"); + while(true) { /*nop*/ } +} + +#if !defined(BUILD_RTM) + +void HARD_Breakpoint() +{ + __asm__("BKPT"); + while(true) { /*nop*/ } +}; + +#endif // !defined(BUILD_RTM) + + +// Provides information whether the configuration block storage requires erase command before sending the update command +// The 'weak' implementation for TI SimpleLink targets is false +// If a target implements the store differently it has to provide a 'strong' implementation of this. +__nfweak bool Target_ConfigUpdateRequiresErase() +{ + return false; +}; + +bool Target_HasNanoBooter() +{ + return false; +}; diff --git a/targets/TI-SimpleLink/common/platformHAL_Time.cpp b/targets/TI-SimpleLink/common/platformHAL_Time.cpp new file mode 100644 index 0000000000..bcb1856813 --- /dev/null +++ b/targets/TI-SimpleLink/common/platformHAL_Time.cpp @@ -0,0 +1,21 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// Converts FreeRTOS Tickcount to .NET ticks (100 nanoseconds) +uint64_t HAL_Time_SysTicksToTime(unsigned int sysTicks) +{ + return (((int64_t)sysTicks * (int64_t)1000000 + (int64_t)configTICK_RATE_HZ - 1) / (int64_t)configTICK_RATE_HZ) * 10; +} + +// because HAL_Time_SysTicksToTime needs to be called from C we need a proxy to allow it to be called from 'C' code +extern "C" { + + uint64_t HAL_Time_SysTicksToTime_C(unsigned int sysTicks) + { + return HAL_Time_SysTicksToTime(sysTicks); + } +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp b/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp index 171e965f5b..fcc46f3969 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp +++ b/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp @@ -12,12 +12,6 @@ #include #include -// Converts FreeRTOS Tickcount to .NET ticks (100 nanoseconds) -uint64_t HAL_Time_SysTicksToTime(unsigned int sysTicks) -{ - return (((int64_t)sysTicks * (int64_t)1000000 + (int64_t)configTICK_RATE_HZ - 1) / (int64_t)configTICK_RATE_HZ) * 10; -} - // Returns the current date time from the RTC uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) { From c4846723c7df06f869ce21a55281e3fa14d59d2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 22 Feb 2019 16:55:36 +0000 Subject: [PATCH 31/90] Enable all GPIO pins on the board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c | 2 +- .../TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c index 7aa6f58201..996f790c00 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -237,7 +237,7 @@ GPIO_PinConfig gpioPinConfigs[] = { * LEDs are taken out of gpioPinConfig[] */ /* CC3220SF_LAUNCHXL_GPIO_LED_D9 */ - /* GPIOCC32XX_GPIO_10 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, */ + GPIOCC32XX_GPIO_10 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, /* CC3220SF_LAUNCHXL_GPIO_LED_D8 */ GPIOCC32XX_GPIO_11 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h index 5ca85f3ccb..ba9a0425b3 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h @@ -100,8 +100,8 @@ typedef enum CC3220SF_LAUNCHXL_GPIOName { * I2C and PWM peripherals. In order for those examples to work, these * LEDs are taken out of gpioPinCOnfig[] */ - /* CC3220SF_LAUNCHXL_GPIO_LED_D9, */ - /* CC3220SF_LAUNCHXL_GPIO_LED_D8, */ + CC3220SF_LAUNCHXL_GPIO_LED_D9, + CC3220SF_LAUNCHXL_GPIO_LED_D8, CC3220SF_LAUNCHXL_GPIO_TMP116_EN, From b579b08f6bed92cf97d4a78e2c84a609325c2801 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 22 Feb 2019 19:36:13 +0000 Subject: [PATCH 32/90] Enable all GPIO pins on the board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/Board.h | 36 ++----------- .../TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c | 45 +++------------- .../TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h | 52 +++---------------- .../nanoCLR/ti_drivers_net_wifi_Config.c | 19 ++++--- 4 files changed, 32 insertions(+), 120 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h index 9f41650760..0866af850a 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h @@ -1,34 +1,8 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// #ifndef __BOARD_H #define __BOARD_H diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c index 996f790c00..e9cbfccc20 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -1,40 +1,11 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * ======== CC3220SF_LAUNCHXL.c ======== - * This file is responsible for setting up the board specific items for the - * CC3220SF_LAUNCHXL board. - */ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// This file is responsible for setting up the board specific items for the +// CC3220SF_LAUNCHXL board #include #include diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h index ba9a0425b3..438f06c406 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h @@ -1,47 +1,11 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file C3220SF_LAUNCHXL.h - * - * @brief CC3220 Board Specific APIs - * - * The CC3220SF_LAUNCHXL header file should be included in an application as - * follows: - * @code - * #include - * @endcode - * - * ============================================================================ - */ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// CC3220 Board Specific APIs + #ifndef __CC3220SF_LAUNCHXL_H #define __CC3220SF_LAUNCHXL_H diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c index 789076f16c..8806c8f011 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c @@ -1,20 +1,23 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// -/* TI-DRIVERS Header files */ +// TI-DRIVERS Header files #include -/* - * =============================== SimpleLink Wifi =============================== - */ -/* - * ======== SimpleLinkWifi_config ======== - */ +///////////////////////////////////////////////// +// Default Wi-Fi configuration for this target // +///////////////////////////////////////////////// + const SlWifiCC32XXConfig_t SimpleLinkWifiCC32XX_config = { .Mode = ROLE_STA, .Ipv4Mode = SL_NETCFG_IPV4_STA_ADDR_MODE, .ConnectionPolicy = SL_WLAN_CONNECTION_POLICY(1,0,0,1), - .PMPolicy = SL_WLAN_NORMAL_POLICY, + .PMPolicy = SL_WLAN_ALWAYS_ON_POLICY,//SL_WLAN_NORMAL_POLICY, .MaxSleepTimeMS = 0, .ScanPolicy = SL_WLAN_SCAN_POLICY(0,0), .ScanIntervalInSeconds = 0, From 0c8870fc1ec7037a0a45215300f6902ead0273f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 22 Feb 2019 19:37:04 +0000 Subject: [PATCH 33/90] Add configuration mamager MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/common/CMakeLists.txt | 5 + .../targetHAL_ConfigurationManager_CC32xx.cpp | 342 ++++++++++++++++++ 2 files changed, 347 insertions(+) create mode 100644 targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp diff --git a/targets/TI-SimpleLink/common/CMakeLists.txt b/targets/TI-SimpleLink/common/CMakeLists.txt index a2c7e14fba..eb9c88e27a 100644 --- a/targets/TI-SimpleLink/common/CMakeLists.txt +++ b/targets/TI-SimpleLink/common/CMakeLists.txt @@ -21,5 +21,10 @@ list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/sys list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platformHAL.c") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platformHAL_Time.cpp") +# append configuration manager according to target +if("${TARGET_SERIES}" STREQUAL "CC32xx") + list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager_CC32xx.cpp") +endif() + # make var global set(TARGET_TI_SimpleLink_COMMON_SOURCES ${TARGET_TI_SimpleLink_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp new file mode 100644 index 0000000000..ff2553a248 --- /dev/null +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -0,0 +1,342 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + + +// This configuration manager implementation is valid for CC32xx devices. +// Because everything that is meant to be stored in the configure block is handled by the SimpleLink +// persistent storage, this code is either empty or acts as a proxy to the SimpleLink API + +// initialization of configuration manager +void ConfigurationManager_Initialize() +{ + // enumerate the blocks + ConfigurationManager_EnumerateConfigurationBlocks(); +}; + +// Enumerates the configuration blocks from the configuration flash sector +void ConfigurationManager_EnumerateConfigurationBlocks() +{ + // // find network configuration blocks + // HAL_CONFIGURATION_NETWORK* networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManager_FindNetworkConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + + // // find wireless 80211 network configuration blocks + // HAL_CONFIGURATION_NETWORK_WIRELESS80211* networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + + // // find X509 certificate blocks + // HAL_CONFIGURATION_X509_CERTIFICATE* certificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)ConfigurationManager_FindX509CertificateConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + + // // alloc memory for g_TargetConfiguration + // // because this is a struct of structs that use flexible members the memory has to be allocated from the heap + // // the malloc size for each struct is computed separately + // uint32_t sizeOfNetworkInterfaceConfigs = offsetof(HAL_CONFIGURATION_NETWORK, Configs) + networkConfigs->Count * sizeof(networkConfigs->Configs[0]); + // uint32_t sizeOfWireless80211Configs = offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + networkWirelessConfigs->Count * sizeof(networkWirelessConfigs->Configs[0]); + // uint32_t sizeOfX509CertificateStore = offsetof(HAL_CONFIGURATION_X509_CERTIFICATE, Certificates) + certificateStore->Count * sizeof(certificateStore->Certificates[0]); + + // g_TargetConfiguration.NetworkInterfaceConfigs = (HAL_CONFIGURATION_NETWORK*)platform_malloc(sizeOfNetworkInterfaceConfigs); + // g_TargetConfiguration.Wireless80211Configs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)platform_malloc(sizeOfWireless80211Configs); + // g_TargetConfiguration.CertificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)platform_malloc(sizeOfX509CertificateStore); + + // // copy structs to g_TargetConfiguration + // memcpy((HAL_CONFIGURATION_NETWORK*)g_TargetConfiguration.NetworkInterfaceConfigs, networkConfigs, sizeOfNetworkInterfaceConfigs); + // memcpy((HAL_CONFIGURATION_NETWORK_WIRELESS80211*)g_TargetConfiguration.Wireless80211Configs, networkWirelessConfigs, sizeOfWireless80211Configs); + // memcpy((HAL_CONFIGURATION_X509_CERTIFICATE*)g_TargetConfiguration.CertificateStore, certificateStore, sizeOfX509CertificateStore); + + // // now free the memory of the original structs + // platform_free(networkConfigs); + // platform_free(networkWirelessConfigs); + // platform_free(certificateStore); +} + +// Gets the network configuration block from the configuration flash sector +bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + // int sizeOfBlock = 0; + // uint8_t* blockAddress = NULL; + + // // validate if the requested block exists + // // Count has to be non zero + // // requested Index has to exist (array index starts at zero, so need to add one) + // if(configuration == DeviceConfigurationOption_Network) + // { + // if(g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0) + // { + // // there is no network config block, init one with default settings + // if(!InitialiseNetworkDefaultConfig(NULL, 0)) + // { + // return FALSE; + // } + // } + // else + // { + // if((configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + // { + // return FALSE; + // } + // } + + // // set block size + // sizeOfBlock = sizeof(HAL_Configuration_NetworkInterface); + + // // get block address + // blockAddress = (uint8_t*)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; + // } + // else if(configuration == DeviceConfigurationOption_Wireless80211Network) + // { + // if(g_TargetConfiguration.Wireless80211Configs->Count == 0 || + // (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) + // { + // return FALSE; + // } + + // // set block size + // sizeOfBlock = sizeof(HAL_Configuration_Wireless80211); + + // // get block address + // blockAddress = (uint8_t*)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; + // } + // else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + // { + // if(g_TargetConfiguration.CertificateStore->Count == 0 || + // (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) + // { + // return FALSE; + // } + + // // get block address + // blockAddress = (uint8_t*)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // // set block size + // // because X509 certificate has a variable length need to compute the block size in two steps + // sizeOfBlock = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + // sizeOfBlock += ((HAL_Configuration_X509CaRootBundle*)blockAddress)->CertificateSize; + // } + + // // copy the config block content to the pointer in the argument + // memcpy(configurationBlock, blockAddress, sizeOfBlock); + + return TRUE; +} + +// Stores the configuration block to the configuration flash sector +// NOTE: because inserting or removing a configuration block it's very 'RAM expensive' we choose not to support those operations +// the host debugger will have to be used to manage these operations on the device configuration collection +bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex, uint32_t blockSize, uint32_t offset) +{ + // ByteAddress storageAddress = 0; + // bool requiresEnumeration = FALSE; + bool success = FALSE; + + // if(configuration == DeviceConfigurationOption_Network) + // { + // if( g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 || + // (configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + // { + // // there is no room for this block, or there are no blocks stored at all + // // failing the operation + // return FALSE; + // } + + // // set storage address from block address, plus the requested offset + // storageAddress = (ByteAddress)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex] + offset; + + // // set block size, in case it's not already set + // blockSize = sizeof(HAL_Configuration_NetworkInterface); + + // // make sure the config block marker is set + // memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + // _ASSERTE(((HAL_Configuration_NetworkInterface*)configurationBlock)->StartupAddressMode > 0); + // } + // else if(configuration == DeviceConfigurationOption_Wireless80211Network) + // { + // if( g_TargetConfiguration.Wireless80211Configs->Count == 0 || + // (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) + // { + // // there is no room for this block, or there are no blocks stored at all + // // failing the operation + // return FALSE; + // } + + // // set storage address from block address, plus the requested offset + // storageAddress = (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex] + offset; + + // // set block size, in case it's not already set + // blockSize = sizeof(HAL_Configuration_Wireless80211); + + // // make sure the config block marker is set + // memcpy(configurationBlock, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + // } + // else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + // { + // if( g_TargetConfiguration.CertificateStore->Count == 0 || + // (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) + // { + // // there is no room for this block, or there are no blocks stored at all + // // failing the operation + // return FALSE; + // } + + // // set storage address from block address, plus the requested offset + // storageAddress = (ByteAddress)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex] + offset; + + // // set block size, in case it's not already set + // // because X509 certificate has a variable length need to compute the block size in two steps + // blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + // blockSize += ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize; + + // // make sure the config block marker is set + // memcpy(configurationBlock, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1, sizeof(c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1)); + // } + // else if(configuration == DeviceConfigurationOption_All) + // { + // // particular situation where we are receiving the full configuration block + + // // set storage address as the start of the flash configuration sector, plus the requested offset + // storageAddress = (ByteAddress)&__nanoConfig_start__ + offset; + + // // always enumerate the blocks again after storing it + // requiresEnumeration = TRUE; + + // // for save all the block size has to be provided, check that + // if(blockSize == 0) + // { + // return FALSE; + // } + // } + + // // copy the config block content to the config block storage + // success = STM32FlashDriver_Write(NULL, storageAddress, blockSize, (unsigned char*)configurationBlock, true); + + // if(success == TRUE && requiresEnumeration) + // { + // // free the current allocation(s) + // platform_free(g_TargetConfiguration.NetworkInterfaceConfigs); + // platform_free(g_TargetConfiguration.Wireless80211Configs); + // platform_free(g_TargetConfiguration.CertificateStore); + + // // perform enumeration of configuration blocks + // ConfigurationManager_EnumerateConfigurationBlocks(); + // } + + return success; +} + +// Updates a configuration block +bool ConfigurationManager_UpdateConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + // ByteAddress storageAddress; + // uint32_t blockOffset; + // uint8_t* blockAddressInCopy; + // uint32_t blockSize; + bool success = FALSE; + + // // config sector size + // int sizeOfConfigSector = (uint32_t)&__nanoConfig_end__ - (uint32_t)&__nanoConfig_start__; + + // // allocate memory from CRT heap + // uint8_t* configSectorCopy = (uint8_t*)platform_malloc(sizeOfConfigSector); + + // if(configSectorCopy != NULL) + // { + // // copy config sector from flash to RAM + // memcpy(configSectorCopy, &__nanoConfig_start__, sizeOfConfigSector); + + // // find out the address for the config block to update in the configSectorCopy + // // because we are copying back the config block to flash and just replacing the config block content + // // the addresses in g_TargetConfiguration will remain the same + // // plus we can calculate the offset of the config block from g_TargetConfiguration + // if(configuration == DeviceConfigurationOption_Network) + // { + // // get storage address from block address + // storageAddress = (ByteAddress)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; + + // // set block size, in case it's not already set + // blockSize = sizeof(HAL_Configuration_NetworkInterface); + + // // make sure the config block marker is set + // memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + // _ASSERTE(((HAL_Configuration_NetworkInterface*)configurationBlock)->StartupAddressMode > 0); + // } + // else if(configuration == DeviceConfigurationOption_Wireless80211Network) + // { + // // storage address from block address + // storageAddress = (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; + + // // set block size, in case it's not already set + // blockSize = sizeof(HAL_Configuration_Wireless80211); + + // // make sure the config block marker is set + // memcpy(configurationBlock, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + // } + // else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + // { + // // storage address from block address + // storageAddress = (ByteAddress)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // // set block size, in case it's not already set + // // because X509 certificate has a variable length need to compute the block size in two steps + // blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + // blockSize += ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize; + + // // make sure the config block marker is set + // memcpy(configurationBlock, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1, sizeof(c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1)); + // } + // else + // { + // // this not a valid configuration option to update, quit + // // free memory first + // platform_free(configSectorCopy); + + // return FALSE; + // } + + // // erase config sector + // if(STM32FlashDriver_EraseBlock(NULL, (uint32_t)&__nanoConfig_start__) == TRUE) + // { + // // flash block is erased + + // // subtract the start address of config sector to get the offset + // blockOffset = storageAddress - (uint32_t)&__nanoConfig_start__; + + // // set pointer to block to udpate + // blockAddressInCopy = configSectorCopy + blockOffset; + + // // replace config block with new content by replacing memory + // memcpy(blockAddressInCopy, configSectorCopy, blockSize); + + // // copy the config block copy back to the config block storage + // success = STM32FlashDriver_Write(NULL, (uint32_t)&__nanoConfig_start__, sizeOfConfigSector, (unsigned char*)configSectorCopy, true); + // } + + // // free memory + // platform_free(configSectorCopy); + // } + + return success; +} + +// Default initialisation for wireless config block +void InitialiseWirelessDefaultConfig(HAL_Configuration_Wireless80211 * pconfig, uint32_t configurationIndex) +{ + (void)pconfig; + (void)configurationIndex; + + // TODO +} + +// Default initialisation for Network interface config blocks +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) +{ + (void)pconfig; + (void)configurationIndex; + + // TODO + return true; +} From 2288a3b2b4ff67ea52b0b3be745add0ddfb4e5c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 22 Feb 2019 19:37:48 +0000 Subject: [PATCH 34/90] Add SimpleLink net Wi-Fi source files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_SimpleLink_CC32xx_sources.cmake | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake index 78b963eb5f..0d47f0bce5 100644 --- a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake +++ b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake @@ -10,6 +10,8 @@ list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSD list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/boards/CC3220SF_LAUNCHXL") list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx") list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx/driverlib") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/net") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/bsd") # source files for board drivers set(BoardDrivers_SRCS @@ -172,6 +174,42 @@ foreach(SRC_FILE ${SimpleLink_SRCS}) list(APPEND TI_SimpleLink_SOURCES ${SimpleLink_SCR_FILE}) endforeach() + +# source files for SimpleLink net Wi-Fi +set(SLNetWiFi_SRCS + + slnetsock.c + slnetutils.c + slnetif.c + + # bsd + netdb.c + socket.c + errnoutil.c + + # drivers + eventreg.c + slnetifwifi.c +) + +foreach(SRC_FILE ${SLNetWiFi_SRCS}) + set(SLNetWiFi_SCR_FILE SRC_FILE -NOTFOUND) + find_file(SLNetWiFi_SCR_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/net" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/net/bsd" + + # drivers + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi/slnetif" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${SLNetWiFi_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${SLNetWiFi_SCR_FILE}) +endforeach() + include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(SimpleLinkCC32xxSDK DEFAULT_MSG TI_SimpleLink_INCLUDE_DIRS TI_SimpleLink_SOURCES) From 12cb4cb001e0d2feb7c83a783c60eefc91013f40 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 22 Feb 2019 19:38:17 +0000 Subject: [PATCH 35/90] Work on main thread, provisioning and connection tasks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../Include/targetSimpleLinkCC32xx_Threads.h | 13 +- .../nanoCLR/CMakeLists.txt | 2 + .../targetSimpleLinkCC32xx_LinkLocalTask.c | 244 +++++++++--------- .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 125 +++++---- 4 files changed, 212 insertions(+), 172 deletions(-) diff --git a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h index a7fc8466bc..c8d3bca67a 100644 --- a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h +++ b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h @@ -86,9 +86,16 @@ typedef enum // nF Control block for SimpleLink typedef struct nanoFramework_ControlBlock_t { - - uint32_t status;/* SimpleLink Status */ - + // This bit-wise status variable shows the state of the NWP + uint32_t Status; + // This field keeps the device's role (STA, P2P or AP) + uint32_t Role; + + int16_t socket; + int16_t sockTcpServer; + uint8_t configurationDone; + uint8_t tcpConnected; + // uint32_t gatewayIP;/* Network Gateway IP address */ // uint8_t connectionSSID[SL_WLAN_SSID_MAX_LENGTH + 1];/* Connection SSID */ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt index 07917ed851..605070bbaa 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt @@ -6,6 +6,8 @@ # append nanoCLR source files list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# default Wi-Fi configuration for this target list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/ti_drivers_net_wifi_Config.c") # make var global diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c index 07cc62dadd..2532191bfd 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c @@ -703,7 +703,7 @@ int32_t otaPutCallback(uint8_t requestIdx, uint8_t *argvArray; uint16_t metadataLen; uint8_t *filename; - int32_t status; + int32_t Status; uint32_t flags; uint32_t fileLen = 0; uint16_t elementType; @@ -715,7 +715,7 @@ int32_t otaPutCallback(uint8_t requestIdx, StartLedEvtTimer(LED_TOGGLE_OTA_PROCESS_TIMEOUT); - status = 0; + Status = 0; accumulatedLen = 0; deviceType = getDeviceType(); argvArray = *argvCallback; @@ -762,7 +762,7 @@ int32_t otaPutCallback(uint8_t requestIdx, { //UART_PRINT( // "[Link local task] OTA filename should be in *.tar format\n\r"); - status = -1; + Status = -1; goto exit_ota_put; } @@ -771,7 +771,7 @@ int32_t otaPutCallback(uint8_t requestIdx, sl_Memcpy(gPayloadBuffer, netAppRequest->requestData.pPayload, netAppRequest->requestData.PayloadLen); - // status = + // Status = // (int32_t)OtaArchive_Process(&gOtaArcive, gPayloadBuffer, // netAppRequest->requestData.PayloadLen, // &processedBytes); @@ -779,11 +779,11 @@ int32_t otaPutCallback(uint8_t requestIdx, // netAppRequest->requestData.PayloadLen, // processedBytes); - // if(status < 0) + // if(Status < 0) // { // goto exit_ota_put; // } - // else if(status == ARCHIVE_STATUS_DOWNLOAD_DONE) + // else if(Status == ARCHIVE_STATUS_DOWNLOAD_DONE) // { // otaProgressBar = 100; // mq_send(LinkLocal_ControlBlock.reportServerMQueue, @@ -796,7 +796,7 @@ int32_t otaPutCallback(uint8_t requestIdx, // // "Download file completed %s\r\n", // // filename); - // status = 0; + // Status = 0; // goto exit_ota_put; // } @@ -821,18 +821,18 @@ int32_t otaPutCallback(uint8_t requestIdx, if(OOB_IS_NETAPP_MORE_DATA(flags)) { chunkLen = NETAPP_MAX_RX_FRAGMENT_LEN - unprocessedBytes; - status = + Status = sl_NetAppRecv(netAppRequest->Handle, (uint16_t *)&chunkLen, &gPayloadBuffer[unprocessedBytes], (unsigned long *)&flags); //INFO_PRINT( // "[Link local task] sl_NetAppRecv payload=%d, flags=%d \n\r", // chunkLen, flags); - if(status < 0) + if(Status < 0) { //UART_PRINT( // "[Link local task] sl_NetAppRecv error=%d, flags=%d \n\r", - // status, flags); + // Status, flags); /* Stop the parsing of the archive file */ // OtaArchive_Abort(&gOtaArcive); @@ -847,7 +847,7 @@ int32_t otaPutCallback(uint8_t requestIdx, //INFO_PRINT( // "[Link local task] No more data in NetApp but archive module " // "still has processing to do \n\r"); - status = 0; + Status = 0; chunkLen = 0; } @@ -899,7 +899,7 @@ int32_t otaPutCallback(uint8_t requestIdx, // } otaChunkLen = chunkLen + unprocessedBytes; - // status = + // Status = // (int32_t)OtaArchive_Process(&gOtaArcive, gPayloadBuffer, // otaChunkLen, // &processedBytes); @@ -907,12 +907,12 @@ int32_t otaPutCallback(uint8_t requestIdx, //INFO_PRINT( // "[Link local task] Received OTA payload=%d. Processed=%d \n\r", // otaChunkLen, processedBytes); - if(status < 0) + if(Status < 0) { - //UART_PRINT("[Link local task] OtaArchive error %d \n\r", status); + //UART_PRINT("[Link local task] OtaArchive error %d \n\r", Status); goto exit_ota_put; } - // else if(status == ARCHIVE_STATUS_DOWNLOAD_DONE) + // else if(Status == ARCHIVE_STATUS_DOWNLOAD_DONE) // { // clock_gettime(CLOCK_REALTIME, &ts); // ts.tv_nsec += 1000000; @@ -932,7 +932,7 @@ int32_t otaPutCallback(uint8_t requestIdx, // // "file completed %s\r\n", // // filename); - // status = 0; + // Status = 0; // goto exit_ota_put; // } @@ -962,7 +962,7 @@ int32_t otaPutCallback(uint8_t requestIdx, ▼use case▼| good | bad | no rx bufer | internal error | --------------------------------------------------------------- - status | 0 | <0 | 0 | 0 | + Status | 0 | <0 | 0 | 0 | --------------------------------------------------------------- progress bar| 100 | <100 | <100 | <100 | --------------------------------------------------------------- @@ -979,10 +979,10 @@ int32_t otaPutCallback(uint8_t requestIdx, /* progress bar is not yet 100% - bad case*/ if(otaProgressBar != 100) { - status = -1; + Status = -1; } - //UART_PRINT("[Link local task] ota put done. status=%d \r\n", status); - if(status == 0) + //UART_PRINT("[Link local task] ota put done. Status=%d \r\n", Status); + if(Status == 0) { /* flush the netapp data from client */ otaFlushNetappReq(netAppRequest, &flags); @@ -996,14 +996,14 @@ int32_t otaPutCallback(uint8_t requestIdx, } else { - metadataLen = preparePostMetadata(status); + metadataLen = preparePostMetadata(Status); //INFO_PRINT("[Link local task] ota put, sending metadata \r\n"); sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA); } - if(status != 0) + if(Status != 0) { /* mark progress bar to 0xFF so ota task would get restarted to reopen socket */ @@ -1029,7 +1029,7 @@ int32_t otaPutCallback(uint8_t requestIdx, sem_wait(&LinkLocal_ControlBlock.otaReportServerStopSignal); StopLedEvtTimer(); - if(status == 0) + if(Status == 0) { //GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); } @@ -1038,14 +1038,14 @@ int32_t otaPutCallback(uint8_t requestIdx, //GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); } - if(status == 0) + if(Status == 0) { /* it means Tar file is downloaded and parsed correctly. Need to reset the MCU */ mcuReboot(); } - return(status); + return(Status); } //***************************************************************************** @@ -1070,7 +1070,7 @@ int32_t otaGetCallback(uint8_t requestIdx, { uint8_t *argvArray, *pPayload; uint16_t metadataLen, elementType; - int32_t status = 0; + int32_t Status = 0; argvArray = *argvCallback; pPayload = gPayloadBuffer; @@ -1085,14 +1085,14 @@ int32_t otaGetCallback(uint8_t requestIdx, { case OtaIdx_Version: - // status = OtaArchive_GetCurrentVersion(gOtaVersion); - // if(status < 0) + // Status = OtaArchive_GetCurrentVersion(gOtaVersion); + // if(Status < 0) // { // //UART_PRINT( // // "[Link local task] ota bundle version file does " // // "not exist\r\n"); // strcpy((char *)gMetadataBuffer, "no version file exists"); - // status = 0; + // Status = 0; // } // else // { @@ -1132,7 +1132,7 @@ int32_t otaGetCallback(uint8_t requestIdx, *(pPayload - 1) = '\0'; metadataLen = - prepareGetMetadata(status, strlen( + prepareGetMetadata(Status, strlen( (const char *)gPayloadBuffer), HttpContentTypeList_UrlEncoded); @@ -1148,7 +1148,7 @@ int32_t otaGetCallback(uint8_t requestIdx, //INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", // strlen ((const char *)gPayloadBuffer)); - return(status); + return(Status); } //***************************************************************************** @@ -1360,22 +1360,22 @@ int32_t sensorGetCallback(uint8_t requestIdx, uint8_t *argvArray, *pPayload; uint16_t metadataLen, elementType; int16_t value = 0; - int32_t status; + int32_t Status; argvArray = *argvCallback; pPayload = gPayloadBuffer; /* Read accelerometer axis values */ - status = accelarometerReading(); - if(status != 0) + Status = accelarometerReading(); + if(Status != 0) { //UART_PRINT( // "[Link local task] Failed to read data from accelerometer\n\r"); } /* Read temperature sensor values */ - status = temperatureReading(); - if(status != 0) + Status = temperatureReading(); + if(Status != 0) { //UART_PRINT( // "[Link local task] Failed to" @@ -1472,7 +1472,7 @@ int32_t deviceGetCallback(uint8_t requestIdx, { uint8_t *argvArray, *pPayload; uint16_t metadataLen, elementType; - int32_t status; + int32_t Status; uint32_t deviceType; argvArray = *argvCallback; @@ -1488,29 +1488,29 @@ int32_t deviceGetCallback(uint8_t requestIdx, switch(*(argvArray + ARGV_VALUE_OFFSET)) { case DeviceIdx_Ssid: - status = getDeviceSSID(); - if(status != 0) + Status = getDeviceSSID(); + if(Status != 0) { //UART_PRINT( // "[Link local task] failed to get SSID. IP_ACQ=%d, " // "IP_LEASED=%d\n\r", - // GET_STATUS_BIT(OutOfBox_ControlBlock.status, + // GET_STATUS_BIT(OutOfBox_ControlBlock.Status, // AppStatusBits_IpAcquired), - // GET_STATUS_BIT(OutOfBox_ControlBlock.status, + // GET_STATUS_BIT(OutOfBox_ControlBlock.Status, // AppStatusBits_IpLeased)); goto exit_device_get; } break; case DeviceIdx_IpAddress: - status = getDeviceIpAddress(); - if(status != 0) + Status = getDeviceIpAddress(); + if(Status != 0) { goto exit_device_get; } break; case DeviceIdx_MacAddress: - status = getDeviceMacAddress(gMetadataBuffer); - if(status != 0) + Status = getDeviceMacAddress(gMetadataBuffer); + if(Status != 0) { goto exit_device_get; } @@ -1546,12 +1546,12 @@ int32_t deviceGetCallback(uint8_t requestIdx, //UART_PRINT( // "[Link local task] device type %d is not supported\n\r", // deviceType); - status = -1; + Status = -1; goto exit_device_get; } - status = 0; + Status = 0; break; } @@ -1584,16 +1584,16 @@ int32_t deviceGetCallback(uint8_t requestIdx, /* NULL terminate the payload */ *(pPayload - 1) = '\0'; - status = 0; + Status = 0; exit_device_get: - if(status != 0) + if(Status != 0) { strcpy((char *)gPayloadBuffer, (const char *)pageNotFound); } metadataLen = - prepareGetMetadata(status, + prepareGetMetadata(Status, strlen((const char *)gPayloadBuffer), HttpContentTypeList_UrlEncoded); @@ -1607,7 +1607,7 @@ int32_t deviceGetCallback(uint8_t requestIdx, //INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", // strlen ((const char *)gPayloadBuffer)); - return(status); + return(Status); } //***************************************************************************** @@ -1651,18 +1651,18 @@ int32_t getDeviceMacAddress(uint8_t *macAddress) { uint8_t macAddressVal[6]; uint16_t macAddressLen; - int32_t status; + int32_t Status; macAddress[0] = '\0'; /* Get the device's MAC address */ macAddressLen = 6; - status = + Status = sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,NULL,&macAddressLen, (uint8_t *)macAddressVal); - if(status < 0) + if(Status < 0) { - return(status); + return(Status); } snprintf((char *)macAddress, MAC_ADDR_STR_LEN, @@ -1689,7 +1689,7 @@ int32_t getDeviceMacAddress(uint8_t *macAddress) uint8_t accelarometerReading(void) { int8_t xValRead, yValRead, zValRead; - int32_t status; + int32_t Status; if(sensorLockObj != NULL) { @@ -1697,19 +1697,19 @@ uint8_t accelarometerReading(void) } /* Read accelarometer axis values */ - status = BMA2xxReadNew(i2cHandle, &xValRead, &yValRead, &zValRead); - if(status != 0) + Status = BMA2xxReadNew(i2cHandle, &xValRead, &yValRead, &zValRead); + if(Status != 0) { /* try to read again */ - status = BMA2xxReadNew(i2cHandle, &xValRead, &yValRead, &zValRead); - if(status != 0) /* leave previous values */ + Status = BMA2xxReadNew(i2cHandle, &xValRead, &yValRead, &zValRead); + if(Status != 0) /* leave previous values */ { //UART_PRINT( // "[Link local task] Failed to read data from accelarometer\n\r"); } } - if(status == 0) + if(Status == 0) { xVal = xValRead; yVal = yValRead; @@ -1721,7 +1721,7 @@ uint8_t accelarometerReading(void) pthread_mutex_unlock(sensorLockObj); } - return(status); + return(Status); } //***************************************************************************** @@ -1735,16 +1735,16 @@ uint8_t accelarometerReading(void) //***************************************************************************** uint8_t temperatureReading(void) { - int32_t status; + int32_t Status; float fTempRead; /* Read temperature axis values */ - status = TMP006DrvGetTemp(i2cHandle, &fTempRead); - if(status != 0) + Status = TMP006DrvGetTemp(i2cHandle, &fTempRead); + if(Status != 0) { /* try to read again */ - status = TMP006DrvGetTemp(i2cHandle, &fTempRead); - if(status != 0) /* leave previous values */ + Status = TMP006DrvGetTemp(i2cHandle, &fTempRead); + if(Status != 0) /* leave previous values */ { //UART_PRINT( // "[Link local task] Failed to read data from" @@ -1752,13 +1752,13 @@ uint8_t temperatureReading(void) } } - if(status == 0) + if(Status == 0) { fTempRead = (fTempRead > 100) ? 100 : fTempRead; temperatureVal = fTempRead; } - return(status); + return(Status); } //***************************************************************************** @@ -1811,7 +1811,7 @@ uint16_t prepareGetMetadata(int32_t parsingStatus, pMetadata = gMetadataBuffer; - /* http status */ + /* http Status */ *pMetadata = (uint8_t) SL_NETAPP_REQUEST_METADATA_TYPE_STATUS; pMetadata++; *(uint16_t *)pMetadata = (uint16_t) 2; @@ -1865,7 +1865,7 @@ uint16_t preparePostMetadata(int32_t parsingStatus) pMetadata = gMetadataBuffer; - /* http status */ + /* http Status */ *pMetadata = (uint8_t) SL_NETAPP_REQUEST_METADATA_TYPE_STATUS; pMetadata++; *(uint16_t *)pMetadata = (uint16_t) 2; @@ -1903,19 +1903,19 @@ int32_t getDeviceIpAddress(void) uint16_t ConfigOpt; uint16_t ipLen; SlNetCfgIpV4Args_t ipV4 = {0}; - int32_t status; + int32_t Status; gMetadataBuffer[0] = '\0'; /* Get the device's IP address */ ipLen = sizeof(SlNetCfgIpV4Args_t); ConfigOpt = 0; - status = + Status = sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&ipLen, (uint8_t *)&ipV4); - if(status < 0) + if(Status < 0) { - return(status); + return(Status); } snprintf((char *)gMetadataBuffer, IP_ADDR_STR_LEN, "%d.%d.%d.%d", @@ -1941,9 +1941,9 @@ int32_t getDeviceSSID(void) uint16_t len = 32; uint16_t config_opt = SL_WLAN_AP_OPT_SSID; /* simplelink as station connected to AP */ - if(GET_STATUS_BIT(nF_ControlBlock.status, + if(GET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired) && - GET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_Connection)) + GET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection)) { // sl_Memcpy ((uint8_t *)gMetadataBuffer, // (const uint8_t *)nF_ControlBlock.connectionSSID, @@ -1951,9 +1951,9 @@ int32_t getDeviceSSID(void) // gMetadataBuffer[nF_ControlBlock.ssidLen] = '\0'; } /* simplelink as AP with connected client */ - else if(GET_STATUS_BIT(nF_ControlBlock.status, + else if(GET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired) && - GET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpLeased)) + GET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased)) { // sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, // (uint8_t *)nF_ControlBlock.connectionSSID); @@ -1985,24 +1985,24 @@ int32_t getDeviceSSID(void) int32_t otaFlushNetappReq(SlNetAppRequest_t *netAppRequest, uint32_t *flags) { - int32_t status; + int32_t Status; int32_t chunkLen; - status = 0; + Status = 0; while((*flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) == SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) { chunkLen = NETAPP_MAX_RX_FRAGMENT_LEN; - status = + Status = sl_NetAppRecv(netAppRequest->Handle, (uint16_t *)&chunkLen, gPayloadBuffer, (_u32 *)flags); //INFO_PRINT("[Link local task] flushing NetApp packet, len=%d \n\r", // chunkLen); - if(status < 0) + if(Status < 0) { - return(status); + return(Status); } if(*flags == 0) @@ -2011,7 +2011,7 @@ int32_t otaFlushNetappReq(SlNetAppRequest_t *netAppRequest, } } - return(status); + return(Status); } //***************************************************************************** @@ -2090,7 +2090,7 @@ int32_t parseUrlEncoded(uint8_t requestIdx, { uint8_t *token; uint8_t characteristic, value, isValueExpected, loopIdx; - int32_t status = -1; + int32_t Status = -1; uint8_t *argvArray; uint8_t remainingLen, actualLen; uint16_t elementType; @@ -2139,7 +2139,7 @@ int32_t parseUrlEncoded(uint8_t requestIdx, while(token && ((pPhrase + phraseLen) > token)) { - status = -1; + Status = -1; characteristic = 0; /* run over all possible characteristics, if exist */ @@ -2154,7 +2154,7 @@ int32_t parseUrlEncoded(uint8_t requestIdx, [ characteristic].characteristic))) { - status = 0; + Status = 0; /* found a characteristic. save its index number */ (*argcCallback)++; @@ -2183,16 +2183,16 @@ int32_t parseUrlEncoded(uint8_t requestIdx, } } /* it means the characteristics is not valid/known */ - if(-1 == status) + if(-1 == Status) { - return(status); + return(Status); } token = (uint8_t *)strtok(NULL, "=&"); if(isValueExpected) { - status = -1; + Status = -1; value = 0; if(token != NULL) @@ -2202,7 +2202,7 @@ int32_t parseUrlEncoded(uint8_t requestIdx, httpRequest[requestIdx]. charValues[characteristic].value[value]) { - status = 0; + Status = 0; /* found a string value. copy its content */ (*argcCallback)++; @@ -2241,7 +2241,7 @@ int32_t parseUrlEncoded(uint8_t requestIdx, ].charValues[ characteristic].value[value]))) { - status = 0; + Status = 0; /* found a value. save its index number */ (*argcCallback)++; @@ -2267,9 +2267,9 @@ int32_t parseUrlEncoded(uint8_t requestIdx, } } /* it means the value is not valid/known */ - if(-1 == status) + if(-1 == Status) { - return(status); + return(Status); } } } @@ -2277,7 +2277,7 @@ int32_t parseUrlEncoded(uint8_t requestIdx, } } - return(status); + return(Status); } //***************************************************************************** @@ -2338,7 +2338,7 @@ int32_t parseHttpRequestMetadata(uint8_t requestType, uint8_t *pTlv; uint8_t *pEnd; - int32_t status = -1; + int32_t Status = -1; uint8_t loopIdx; uint8_t type; uint16_t len; @@ -2386,7 +2386,7 @@ int32_t parseHttpRequestMetadata(uint8_t requestType, case SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN: /* it means there is a content length and URI is OK. Add it to the argv */ - if(0 == status) + if(0 == Status) { /* it means parameters already exist from query type */ if(*argcCallback > 0) @@ -2431,7 +2431,7 @@ int32_t parseHttpRequestMetadata(uint8_t requestType, { if(requestType == httpRequest[loopIdx].httpMethod) { - status = 0; + Status = 0; *requestIdx = httpRequest[loopIdx].requestIdx; //INFO_PRINT ("%s\n\r", httpRequest[loopIdx].service); @@ -2440,7 +2440,7 @@ int32_t parseHttpRequestMetadata(uint8_t requestType, } } - if(status != 0) + if(Status != 0) { //INFO_PRINT ("unknown service\n\r"); } @@ -2448,12 +2448,12 @@ int32_t parseHttpRequestMetadata(uint8_t requestType, break; case SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_QUERY_STRING: - if(0 == status) + if(0 == Status) { - status = parseUrlEncoded(*requestIdx, pTlv, len, argcCallback, + Status = parseUrlEncoded(*requestIdx, pTlv, len, argcCallback, argvCallback); - if(status != 0) + if(Status != 0) { //INFO_PRINT ( // "query string in metadata section is not" @@ -2474,7 +2474,7 @@ int32_t parseHttpRequestMetadata(uint8_t requestType, pTlv += len; } - return(status); + return(Status); } //***************************************************************************** @@ -2501,19 +2501,19 @@ int32_t parseHttpRequestPayload(uint8_t requestIdx, uint8_t *argcCallback, uint8_t **argvCallback) { - int32_t status = -1; + int32_t Status = -1; - status = parseUrlEncoded(requestIdx, pPayload, payloadLen, argcCallback, + Status = parseUrlEncoded(requestIdx, pPayload, payloadLen, argcCallback, argvCallback); - if(status != 0) + if(Status != 0) { //UART_PRINT ( // "[Link local task] query string in payload section is " // "not valid/known\n\r"); } - return(status); + return(Status); } //***************************************************************************** @@ -2540,14 +2540,14 @@ int32_t httpCheckContentInDB(SlNetAppRequest_t *netAppRequest, uint8_t *argcCallback, uint8_t **argvCallback) { - int32_t status = -1; + int32_t Status = -1; if(netAppRequest->AppId != SL_NETAPP_HTTP_SERVER_ID) { - return(status); + return(Status); } - status = + Status = parseHttpRequestMetadata(netAppRequest->Type, netAppRequest->requestData.pMetadata, netAppRequest->requestData.MetadataLen, @@ -2555,10 +2555,10 @@ int32_t httpCheckContentInDB(SlNetAppRequest_t *netAppRequest, argvCallback); /* PUT does not contain parseable data - only POST does */ - if((0 == status) && (netAppRequest->requestData.PayloadLen != 0) && + if((0 == Status) && (netAppRequest->requestData.PayloadLen != 0) && (netAppRequest->Type != SL_NETAPP_REQUEST_HTTP_PUT)) { - status = + Status = parseHttpRequestPayload(*requestIdx, netAppRequest->requestData.pPayload, netAppRequest->requestData.PayloadLen, @@ -2566,7 +2566,7 @@ int32_t httpCheckContentInDB(SlNetAppRequest_t *netAppRequest, argvCallback); } - return(status); + return(Status); } //***************************************************************************** @@ -2581,7 +2581,7 @@ int32_t httpCheckContentInDB(SlNetAppRequest_t *netAppRequest, void httpGetHandler(SlNetAppRequest_t *netAppRequest) { uint16_t metadataLen; - int32_t status; + int32_t Status; uint8_t requestIdx; uint8_t argcCallback; @@ -2590,13 +2590,13 @@ void httpGetHandler(SlNetAppRequest_t *netAppRequest) argvArray = gHttpGetBuffer; - status = httpCheckContentInDB(netAppRequest, &requestIdx, &argcCallback, + Status = httpCheckContentInDB(netAppRequest, &requestIdx, &argcCallback, argvCallback); - if(status < 0) + if(Status < 0) { metadataLen = - prepareGetMetadata(status, strlen ( + prepareGetMetadata(Status, strlen ( (const char *)pageNotFound), HttpContentTypeList_TextHtml); @@ -2633,7 +2633,7 @@ void httpGetHandler(SlNetAppRequest_t *netAppRequest) void httpPostHandler(SlNetAppRequest_t *netAppRequest) { uint16_t metadataLen; - int32_t status; + int32_t Status; uint8_t requestIdx; uint8_t argcCallback; @@ -2642,12 +2642,12 @@ void httpPostHandler(SlNetAppRequest_t *netAppRequest) argvArray = gHttpPostBuffer; - status = httpCheckContentInDB(netAppRequest,&requestIdx,&argcCallback, + Status = httpCheckContentInDB(netAppRequest,&requestIdx,&argcCallback, argvCallback); - if(status < 0) + if(Status < 0) { - metadataLen = preparePostMetadata(status); + metadataLen = preparePostMetadata(Status); sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA); diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index fe4814cf1a..2519d75d21 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -6,9 +6,11 @@ #include #include + // POSIX Header files #include #include +#include // RTOS header files #include "FreeRTOS.h" @@ -16,10 +18,11 @@ // TI-RTOS Header files #include +#include +#include -// Example/Board Header files +// Board Header files #include "Board.h" -#include #include #include @@ -27,7 +30,6 @@ #include #include #include -#include extern void * CLRStartupThread(void *arg0); extern void * ReceiverThread(void *arg0); @@ -37,8 +39,10 @@ extern void * ReceiverThread(void *arg0); #define APPLICATION_NAME "out of box" #define APPLICATION_VERSION "1.00.00.09" -#define SPAWN_TASK_PRIORITY (9) -#define TASK_STACK_SIZE (2048) +#define SPAWN_TASK_PRIORITY (9) +#define TASK_STACK_SIZE (2048) + +#define SLNET_IF_WIFI_PRIO (5) ////////////////////////////// @@ -71,11 +75,11 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) { case SL_WLAN_EVENT_CONNECT: { - SET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_Connection); - CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpAcquired); - CLR_STATUS_BIT(nF_ControlBlock.status, + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6lAcquired); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6gAcquired); // Information about the connected AP (like name, MAC etc) will be @@ -116,11 +120,11 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) { SlWlanEventDisconnect_t* pEventData = NULL; - CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_Connection); - CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpAcquired); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6lAcquired); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6gAcquired); pEventData = &pWlanEvent->Data.Disconnect; @@ -192,14 +196,14 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) case SL_WLAN_EVENT_PROVISIONING_STATUS: { - uint16_t status = + uint16_t Status = pWlanEvent->Data.ProvisioningStatus.ProvisioningStatus; - switch(status) + switch(Status) { case SL_WLAN_PROVISIONING_GENERAL_ERROR: case SL_WLAN_PROVISIONING_ERROR_ABORT: { - //UART_PRINT("[WLAN EVENT] Provisioning Error status=%d\r\n",status); + //UART_PRINT("[WLAN EVENT] Provisioning Error Status=%d\r\n",Status); // SignalProvisioningEvent(PrvnEvent_Error); } break; @@ -207,7 +211,7 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) case SL_WLAN_PROVISIONING_ERROR_ABORT_HTTP_SERVER_DISABLED: case SL_WLAN_PROVISIONING_ERROR_ABORT_PROFILE_LIST_FULL: { - //UART_PRINT("[WLAN EVENT] Provisioning Error status=%d\r\n",status); + //UART_PRINT("[WLAN EVENT] Provisioning Error Status=%d\r\n",Status); // SignalProvisioningEvent(PrvnEvent_StartFailed); } break; @@ -294,13 +298,13 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) } else { - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6lAcquired); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6gAcquired); // Provisioning is stopped by the device and provisioning @@ -324,13 +328,13 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) case SL_WLAN_PROVISIONING_CONFIRMATION_WLAN_CONNECT: { - SET_STATUS_BIT(nF_ControlBlock.status, + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6lAcquired); - CLR_STATUS_BIT(nF_ControlBlock.status, + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6gAcquired); //UART_PRINT("[WLAN EVENT] Connection to AP succeeded\r\n"); @@ -339,7 +343,7 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) case SL_WLAN_PROVISIONING_CONFIRMATION_IP_ACQUIRED: { - SET_STATUS_BIT(nF_ControlBlock.status, + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); //UART_PRINT("[WLAN EVENT] IP address acquired\r\n"); @@ -469,7 +473,7 @@ void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) { SlIpV4AcquiredAsync_t *pEventData = NULL; - SET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpAcquired); + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); // Ip Acquired Event Data pEventData = &pNetAppEvent->Data.IpAcquiredV4; @@ -494,16 +498,16 @@ void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) case SL_NETAPP_EVENT_IPV6_ACQUIRED: { - if(!GET_STATUS_BIT(nF_ControlBlock.status, + if(!GET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6lAcquired)) { - SET_STATUS_BIT(nF_ControlBlock.status, + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6lAcquired); //UART_PRINT("[NETAPP EVENT] Local IPv6 Acquired\n\r"); } else { - SET_STATUS_BIT(nF_ControlBlock.status, + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Ipv6gAcquired); //UART_PRINT("[NETAPP EVENT] Global IPv6 Acquired\n\r"); } @@ -514,7 +518,7 @@ void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) case SL_NETAPP_EVENT_DHCPV4_LEASED: { - SET_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpLeased); + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased); //UART_PRINT( // "[NETAPP EVENT] IPv4 leased %d.%d.%d.%d for " @@ -534,7 +538,7 @@ void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) case SL_NETAPP_EVENT_DHCPV4_RELEASED: { - CLR_STATUS_BIT(nF_ControlBlock.status, AppStatusBits_IpLeased); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased); //UART_PRINT( // "[NETAPP EVENT] IPv4 released %d.%d.%d.%d for " @@ -738,12 +742,13 @@ void * mainThread(void *arg) { struct sched_param priorityParams; - pthread_attr_t slThreadAttributes; pthread_attr_t threadAttributes; int retc; struct timespec ts = {0}; + // peripherals initialization + // make this dependent on having the corresponding NF FEATURE enabled GPIO_init(); UART_init(); SPI_init(); @@ -755,9 +760,15 @@ void * mainThread(void *arg) // Switch off all LEDs on boards GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); - // clear SimpleLink Status - nF_ControlBlock.status = 0; + nF_ControlBlock.Status = 0; + + // reset control block vars + nF_ControlBlock.socket = -1; + nF_ControlBlock.sockTcpServer = -1; + nF_ControlBlock.configurationDone = 0; + nF_ControlBlock.tcpConnected = 0; + // initializes signals for all tasks sem_init(&Provisioning_ControlBlock.connectionAsyncEvent, 0, 0); @@ -768,15 +779,19 @@ void * mainThread(void *arg) sem_init(&LinkLocal_ControlBlock.otaReportServerStartSignal, 0, 0); sem_init(&LinkLocal_ControlBlock.otaReportServerStopSignal, 0, 0); - - // create the sl_Task - pthread_attr_init(&slThreadAttributes); + // Create the sl_Task internal spawn thread + pthread_attr_init(&threadAttributes); priorityParams.sched_priority = SPAWN_TASK_PRIORITY; - retc = pthread_attr_setschedparam(&slThreadAttributes, &priorityParams); - retc |= pthread_attr_setstacksize(&slThreadAttributes, TASK_STACK_SIZE); - - retc = pthread_create(&slThread, &slThreadAttributes, sl_Task, NULL); - + retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&threadAttributes, TASK_STACK_SIZE); + + // The SimpleLink host driver architecture mandate spawn + // thread to be created prior to calling Sl_start (turning the NWP on). + // The purpose of this thread is to handle + // asynchronous events sent from the NWP. + // Every event is classified and later handled + // by the Host driver event handlers. + retc = pthread_create(&slThread, &threadAttributes, sl_Task, NULL); if(retc) { // Handle Error @@ -787,10 +802,24 @@ void * mainThread(void *arg) } } + // Before turning on the NWP on, reset any previously configured parameters + // TODO: check if we should have a better reset implementation instead of using the standard one + retc = sl_WifiConfig(); + if(retc < 0) + { + // Handle Error + //UART_PRINT("Network Terminal - Couldn't configure Network Processor - %d\n",RetVal); + return(NULL); + } + + // start network processor retc = sl_Start(NULL, NULL, NULL); if(retc > 0) { // we are good! + // sl_Start returns on success the role that device started on + nF_ControlBlock.Role = retc; + } else if((retc < 0) && (retc != SL_ERROR_RESTORE_IMAGE_COMPLETE)) { @@ -827,11 +856,12 @@ void * mainThread(void *arg) // } // receiver thread - pthread_attr_init(&slThreadAttributes); + pthread_attr_init(&threadAttributes); priorityParams.sched_priority = 1; retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); retc |= pthread_attr_setstacksize(&threadAttributes, 2048); - if (retc != 0) { + if (retc != 0) + { // failed to set attributes while (1) {} } @@ -847,11 +877,12 @@ void * mainThread(void *arg) } // CLR thread - pthread_attr_init(&slThreadAttributes); + pthread_attr_init(&threadAttributes); priorityParams.sched_priority = 1; retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); retc |= pthread_attr_setstacksize(&threadAttributes, 10000); - if (retc != 0) { + if (retc != 0) + { // failed to set attributes while (1) {} } From 348b7aadf4b5308df89d030574f83636b98c9812 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 26 Feb 2019 16:06:14 +0000 Subject: [PATCH 36/90] Work on CC32xx configuration manager MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../targetHAL_ConfigurationManager_CC32xx.cpp | 317 +++++++++++++----- 1 file changed, 233 insertions(+), 84 deletions(-) diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp index ff2553a248..cff65c1977 100644 --- a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -7,11 +7,112 @@ #include #include +#include + +// we'll store up to 4 network configuration blocks +#define NETWORK_CONFIG_MAX_COUNT (4) +// files with network configuration have this namming patter "network-config-N.bin" +#define NETWORK_CONFIG_FILE_NAME "nf/network-config0.bin" +// position of the index in the file name above (that's the 0) +#define NETWORK_CONFIG_FILE_INDEX_POSITION (17) + +typedef struct +{ + SlFileAttributes_t attribute; + char fileName[SL_FS_MAX_FILE_NAME_LENGTH]; +}slGetfileList_t; // This configuration manager implementation is valid for CC32xx devices. // Because everything that is meant to be stored in the configure block is handled by the SimpleLink // persistent storage, this code is either empty or acts as a proxy to the SimpleLink API +// network configuration blocks are stored as files in file storage +void* ConfigurationManagerCC32xx_FindNetworkConfigurationBlocks() +{ + int32_t ret = 1; + int32_t retGetFileList = 1; + slGetfileList_t* fileList; + int32_t index = -1; + + int32_t i; + uint32_t fileCount = 0; + + // allocate memory for file list buffer + fileList = (slGetfileList_t*)platform_malloc(sizeof(slGetfileList_t) * NETWORK_CONFIG_MAX_COUNT); + + // check succesfull malloc + if (fileList == NULL) + { + return NULL; + } + + // clear memory + memset(fileList, 0x0, sizeof(sizeof(SlFileAttributes_t) * NETWORK_CONFIG_MAX_COUNT)); + + // first pass: find out how many files of this type we have + while(retGetFileList > 0) + { + retGetFileList = sl_FsGetFileList( &index, NETWORK_CONFIG_MAX_COUNT, + (uint8_t)(SL_FS_MAX_FILE_NAME_LENGTH + sizeof(SlFileAttributes_t)), + (unsigned char*)fileList, SL_FS_GET_FILE_ATTRIBUTES); + if (retGetFileList < 0) + { + // error getting file list, or no more files + break; + } + + for (i = 0; i < retGetFileList; i++) + { + // check file name + if(memcmp(fileList[i].fileName, NETWORK_CONFIG_FILE_NAME, sizeof(NETWORK_CONFIG_FILE_NAME)) == 0) + { + fileCount++; + } + } + } + + // allocate config struct + HAL_CONFIGURATION_NETWORK *networkConfigs = (HAL_CONFIGURATION_NETWORK *)platform_malloc(offsetof(HAL_CONFIGURATION_NETWORK, Configs) + fileCount * sizeof(networkConfigs->Configs[0])); + // set collection count + networkConfigs->Count = fileCount; + + // clear memory for file list + platform_free(fileList); + + return networkConfigs; +} + +// wireless profiles are stored as SimpleLink WLAN profile +void* ConfigurationManagerCC32xx_FindNetworkWireless80211ConfigurationBlocks() +{ + uint16_t index, status; + signed char name[32]; + int16_t nameLength; + unsigned char macAddr[6]; + SlWlanSecParams_t secParams; + SlWlanGetSecParamsExt_t secExtParams; + uint32_t priority; + uint16_t profileCount = 0; + + // first pass: find out how many profiles are stored + for(index = 0; index < SL_WLAN_MAX_PROFILES; index++) + { + status = sl_WlanProfileGet(index, name, &nameLength, macAddr, &secParams, &secExtParams, &priority); + if( status > 0) + { + profileCount++; + } + } + + // allocate config struct + HAL_CONFIGURATION_NETWORK_WIRELESS80211 *networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)platform_malloc(offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + profileCount * sizeof(networkWirelessConfigs->Configs[0])); + + // set collection count + networkWirelessConfigs->Count = profileCount; + + return networkWirelessConfigs; +} + // initialization of configuration manager void ConfigurationManager_Initialize() { @@ -22,105 +123,95 @@ void ConfigurationManager_Initialize() // Enumerates the configuration blocks from the configuration flash sector void ConfigurationManager_EnumerateConfigurationBlocks() { - // // find network configuration blocks - // HAL_CONFIGURATION_NETWORK* networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManager_FindNetworkConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + // find network configuration blocks + HAL_CONFIGURATION_NETWORK* networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManagerCC32xx_FindNetworkConfigurationBlocks(); - // // find wireless 80211 network configuration blocks - // HAL_CONFIGURATION_NETWORK_WIRELESS80211* networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + // find wireless 80211 network configuration blocks + HAL_CONFIGURATION_NETWORK_WIRELESS80211* networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)ConfigurationManagerCC32xx_FindNetworkWireless80211ConfigurationBlocks(); // // find X509 certificate blocks // HAL_CONFIGURATION_X509_CERTIFICATE* certificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)ConfigurationManager_FindX509CertificateConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); - // // alloc memory for g_TargetConfiguration - // // because this is a struct of structs that use flexible members the memory has to be allocated from the heap - // // the malloc size for each struct is computed separately - // uint32_t sizeOfNetworkInterfaceConfigs = offsetof(HAL_CONFIGURATION_NETWORK, Configs) + networkConfigs->Count * sizeof(networkConfigs->Configs[0]); - // uint32_t sizeOfWireless80211Configs = offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + networkWirelessConfigs->Count * sizeof(networkWirelessConfigs->Configs[0]); + // alloc memory for g_TargetConfiguration + // because this is a struct of structs that use flexible members the memory has to be allocated from the heap + // the malloc size for each struct is computed separately + uint32_t sizeOfNetworkInterfaceConfigs = offsetof(HAL_CONFIGURATION_NETWORK, Configs) + networkConfigs->Count * sizeof(networkConfigs->Configs[0]); + uint32_t sizeOfWireless80211Configs = offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + networkWirelessConfigs->Count * sizeof(networkWirelessConfigs->Configs[0]); // uint32_t sizeOfX509CertificateStore = offsetof(HAL_CONFIGURATION_X509_CERTIFICATE, Certificates) + certificateStore->Count * sizeof(certificateStore->Certificates[0]); - // g_TargetConfiguration.NetworkInterfaceConfigs = (HAL_CONFIGURATION_NETWORK*)platform_malloc(sizeOfNetworkInterfaceConfigs); - // g_TargetConfiguration.Wireless80211Configs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)platform_malloc(sizeOfWireless80211Configs); + g_TargetConfiguration.NetworkInterfaceConfigs = (HAL_CONFIGURATION_NETWORK*)platform_malloc(sizeOfNetworkInterfaceConfigs); + g_TargetConfiguration.Wireless80211Configs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)platform_malloc(sizeOfWireless80211Configs); // g_TargetConfiguration.CertificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)platform_malloc(sizeOfX509CertificateStore); - // // copy structs to g_TargetConfiguration - // memcpy((HAL_CONFIGURATION_NETWORK*)g_TargetConfiguration.NetworkInterfaceConfigs, networkConfigs, sizeOfNetworkInterfaceConfigs); - // memcpy((HAL_CONFIGURATION_NETWORK_WIRELESS80211*)g_TargetConfiguration.Wireless80211Configs, networkWirelessConfigs, sizeOfWireless80211Configs); + // copy structs to g_TargetConfiguration + memcpy((HAL_CONFIGURATION_NETWORK*)g_TargetConfiguration.NetworkInterfaceConfigs, networkConfigs, sizeOfNetworkInterfaceConfigs); + memcpy((HAL_CONFIGURATION_NETWORK_WIRELESS80211*)g_TargetConfiguration.Wireless80211Configs, networkWirelessConfigs, sizeOfWireless80211Configs); // memcpy((HAL_CONFIGURATION_X509_CERTIFICATE*)g_TargetConfiguration.CertificateStore, certificateStore, sizeOfX509CertificateStore); - // // now free the memory of the original structs - // platform_free(networkConfigs); - // platform_free(networkWirelessConfigs); + // now free the memory of the original structs + platform_free(networkConfigs); + platform_free(networkWirelessConfigs); // platform_free(certificateStore); } // Gets the network configuration block from the configuration flash sector bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) { - // int sizeOfBlock = 0; - // uint8_t* blockAddress = NULL; + int sizeOfBlock = 0; + + // validate if the requested block exists + // Count has to be non zero + // requested Index has to exist (array index starts at zero, so need to add one) + if(configuration == DeviceConfigurationOption_Network) + { + if(g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0) + { + // there is no network config block, init one with default settings + if(!InitialiseNetworkDefaultConfig((HAL_Configuration_NetworkInterface*)configurationBlock, 0)) + { + return false; + } + } + else + { + if((configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + { + return false; + } + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_NetworkInterface); + } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + if(g_TargetConfiguration.Wireless80211Configs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) + { + return false; + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_Wireless80211); + } + else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + { + if(g_TargetConfiguration.CertificateStore->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) + { + return false; + } + + // // get block address + // blockAddress = (uint8_t*)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // // set block size + // // because X509 certificate has a variable length need to compute the block size in two steps + // sizeOfBlock = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + // sizeOfBlock += ((HAL_Configuration_X509CaRootBundle*)blockAddress)->CertificateSize; + } - // // validate if the requested block exists - // // Count has to be non zero - // // requested Index has to exist (array index starts at zero, so need to add one) - // if(configuration == DeviceConfigurationOption_Network) - // { - // if(g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0) - // { - // // there is no network config block, init one with default settings - // if(!InitialiseNetworkDefaultConfig(NULL, 0)) - // { - // return FALSE; - // } - // } - // else - // { - // if((configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) - // { - // return FALSE; - // } - // } - - // // set block size - // sizeOfBlock = sizeof(HAL_Configuration_NetworkInterface); - - // // get block address - // blockAddress = (uint8_t*)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; - // } - // else if(configuration == DeviceConfigurationOption_Wireless80211Network) - // { - // if(g_TargetConfiguration.Wireless80211Configs->Count == 0 || - // (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) - // { - // return FALSE; - // } - - // // set block size - // sizeOfBlock = sizeof(HAL_Configuration_Wireless80211); - - // // get block address - // blockAddress = (uint8_t*)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; - // } - // else if(configuration == DeviceConfigurationOption_X509CaRootBundle) - // { - // if(g_TargetConfiguration.CertificateStore->Count == 0 || - // (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) - // { - // return FALSE; - // } - - // // get block address - // blockAddress = (uint8_t*)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; - - // // set block size - // // because X509 certificate has a variable length need to compute the block size in two steps - // sizeOfBlock = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); - // sizeOfBlock += ((HAL_Configuration_X509CaRootBundle*)blockAddress)->CertificateSize; - // } - - // // copy the config block content to the pointer in the argument - // memcpy(configurationBlock, blockAddress, sizeOfBlock); - - return TRUE; + return true; } // Stores the configuration block to the configuration flash sector @@ -132,6 +223,57 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi // bool requiresEnumeration = FALSE; bool success = FALSE; + unsigned char* fileName = NULL; + + int32_t fileHandle; + uint32_t token = 0; + int32_t retVal; + + if(configuration == DeviceConfigurationOption_Network) + { + // network config blocks are stored as files + + // compose file name + fileName = (unsigned char*)platform_malloc(sizeof(NETWORK_CONFIG_FILE_NAME)); + memcpy(fileName, NETWORK_CONFIG_FILE_NAME, sizeof(NETWORK_CONFIG_FILE_NAME)); + // insert index number at position N as char + fileName[NETWORK_CONFIG_FILE_INDEX_POSITION] = '0' + configurationIndex; + + fileHandle = sl_FsOpen( fileName, + SL_FS_CREATE | SL_FS_OVERWRITE | + SL_FS_CREATE_MAX_SIZE(sizeof(HAL_Configuration_NetworkInterface)) | + SL_FS_CREATE_PUBLIC_WRITE | SL_FS_CREATE_NOSIGNATURE, + (uint32_t *)&token); + + // on error there is no file handle, rather a negative error code + if(fileHandle > 0) + { + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + retVal = sl_FsWrite(fileHandle, 0, (unsigned char*)configurationBlock, sizeof(HAL_Configuration_NetworkInterface)); + + // on success the return value is the amount of bytes written + if(retVal == sizeof(HAL_Configuration_NetworkInterface)) + { + retVal = sl_FsClose(fileHandle, 0, 0, 0); + + if( retVal < 0 ) + { + // error closing file, API ceremony suggests calling "abort" operation + uint8_t signature = 'A'; + sl_FsClose(fileHandle, 0, &signature, 1); + } + } + } + + if(fileName != NULL) + { + platform_free(fileName); + } + } + + // if(configuration == DeviceConfigurationOption_Network) // { // if( g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 || @@ -334,9 +476,16 @@ void InitialiseWirelessDefaultConfig(HAL_Configuration_Wireless80211 * pconfig, // Default initialisation for Network interface config blocks bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) { - (void)pconfig; - (void)configurationIndex; + uint8_t macAddress[SL_MAC_ADDR_LEN]; + uint16_t macAddressLen = SL_MAC_ADDR_LEN; + + memset(pconfig, 0, sizeof(HAL_Configuration_NetworkInterface)); + + pconfig->InterfaceType = NetworkInterfaceType_Wireless80211; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->SpecificConfigId = 0; + + sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, pconfig->MacAddress); - // TODO return true; } From cbb4209bd6fcaa0b58247b7ac0a8fcd3a2391960 Mon Sep 17 00:00:00 2001 From: sjmneves Date: Tue, 26 Feb 2019 16:16:34 +0000 Subject: [PATCH 37/90] Add support for PWM --- .../target_windows_devices_pwm_config.h | 7 + .../win_dev_pwm_native.cpp | 65 ++++++++++ .../Windows.Devices.Pwm/win_dev_pwm_native.h | 79 ++++++++++++ ...tive_Windows_Devices_Pwm_PwmController.cpp | 73 +++++++++++ ..._pwm_native_Windows_Devices_Pwm_PwmPin.cpp | 120 ++++++++++++++++++ .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 3 + 6 files changed, 347 insertions(+) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_pwm_config.h create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.h create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_pwm_config.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_pwm_config.h new file mode 100644 index 0000000000..e3c11018ca --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_pwm_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// number of PWM pins available in this target +#define PWM_PIN_COUNT (2) diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.cpp new file mode 100644 index 0000000000..4639237572 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.cpp @@ -0,0 +1,65 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_pwm_native.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFrequency___R8, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MinFrequency___R8, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCount___I4, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetDesiredFrequency___U4__U4, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeInit___VOID, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetActiveDutyCyclePercentage___VOID__U4, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetPolarity___VOID__U1, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStart___VOID, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStop___VOID, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::DisposeNative___VOID, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Pwm = +{ + "Windows.Devices.Pwm", + 0x75280B26, + method_lookup, + { 1, 1, 3, 1 } +}; diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.h b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.h new file mode 100644 index 0000000000..503b8a0bcc --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native.h @@ -0,0 +1,79 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_PWM_NATIVE_H_ +#define _WIN_DEV_PWM_NATIVE_H_ + +#include +#include +#include + +#include "Board.h" +#include + +#include + +struct Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController +{ + static const int FIELD___controllerId = 1; + static const int FIELD___actualFrequency = 2; + static const int FIELD___pwmTimer = 3; + + NANOCLR_NATIVE_DECLARE(get_MaxFrequency___R8); + NANOCLR_NATIVE_DECLARE(get_MinFrequency___R8); + NANOCLR_NATIVE_DECLARE(get_PinCount___I4); + NANOCLR_NATIVE_DECLARE(NativeSetDesiredFrequency___U4__U4); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmControllerManager +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +struct Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin +{ + static const int FIELD___syncLock = 1; + static const int FIELD___pwmController = 2; + static const int FIELD___polarity = 3; + static const int FIELD___dutyCyclePercentage = 4; + static const int FIELD___dutyCycle = 5; + static const int FIELD___pinNumber = 6; + static const int FIELD___pwmTimer = 7; + static const int FIELD___isStarted = 8; + static const int FIELD___disposed = 9; + + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeSetActiveDutyCyclePercentage___VOID__U4); + NANOCLR_NATIVE_DECLARE(NativeSetPolarity___VOID__U1); + NANOCLR_NATIVE_DECLARE(NativeStart___VOID); + NANOCLR_NATIVE_DECLARE(NativeStop___VOID); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + + //--// + + static int GetChannel (int pin, int timerId); + static int GetAlternateFunction (int timerId); + // static PWMDriver * GetDriver(int timerId); + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Pwm; + +///////////////////////////////////// +// Array of PWM handlers // +// these live in the target folder // +///////////////////////////////////// +extern PWM_Handle PwmPins[PWM_PIN_COUNT]; + +#endif //_WIN_DEV_PWM_NATIVE_H_ diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp new file mode 100644 index 0000000000..c0e212d438 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp @@ -0,0 +1,73 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_pwm_native.h" + +// PWMConfig _pwmConfig; + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // FIXME : how can this value be determined ? + stack.SetResult_R8(1.0); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MinFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // FIXME : how can this value be determined ? + stack.SetResult_R8(1.0); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // TODO + // this is now hardcoded to TWO because this is the available PWM outputs in CC3220SF launchpad + // ideally it should come from the PWM config file at target level + stack.SetResult_I4(2); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetDesiredFrequency___U4__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // the SimpleLink PWM driver doesn't require any general setting + // so there is nothing to do here, just keeping the ceremony for the managed API + unsigned int desiredFrequency = (unsigned int)stack.Arg1().NumericByRef().u4; + + stack.SetResult_R8(desiredFrequency); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // this is now hardcoded to ONE because there is only one PWM controller in CC3220SF launchpad + // ideally it should come from the PWM config file at target level + char deviceSelectorString[] = "TIM0"; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp new file mode 100644 index 0000000000..601057d014 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp @@ -0,0 +1,120 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_pwm_native.h" + +//////////////////////////////////////////////////////////////////// + + +PWM_Handle PwmPins[PWM_PIN_COUNT]; + + +int Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::GetChannel (int pin, int timerId) +{ + // TODO + return -1; +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetActiveDutyCyclePercentage___VOID__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // Retrieves the needed parameters from method parameters + unsigned int dutyCycle = (unsigned int)stack.Arg1().NumericByRef().u4; + + PWM_setDuty(PwmPins[pinNumber], dutyCycle); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetPolarity___VOID__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStart___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // get the controller + CLR_RT_HeapBlock* controller = pThis[ FIELD___pwmController ].Dereference(); + + // get the frequency from the controller + double frequency = controller[ Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::FIELD___actualFrequency ].NumericByRef().r8; + + PWM_Params params; + PWM_Params_init(¶ms); + params.dutyUnits = PWM_DUTY_US; + params.dutyValue = 0; + params.periodUnits = PWM_PERIOD_HZ; + params.periodValue = frequency; + PwmPins[pinNumber] = PWM_open(pinNumber, ¶ms); + if (PwmPins[pinNumber] == NULL) + { + // Board_PWM did not open + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + PWM_start(PwmPins[pinNumber]); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStop___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // Stops PWM output on the channel associated with this handler + PWM_stop(PwmPins[pinNumber]); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + PWM_close(PwmPins[pinNumber]); + } + NANOCLR_NOCLEANUP(); +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index 2519d75d21..ec078c8101 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -753,6 +753,9 @@ void * mainThread(void *arg) UART_init(); SPI_init(); I2C_init(); + ADC_init(); + PWM_init(); + // initialize the realtime clock clock_settime(CLOCK_REALTIME, &ts); From 5555c46c99025764d18c9b9db2492d94ccc269ee Mon Sep 17 00:00:00 2001 From: sjmneves Date: Tue, 26 Feb 2019 18:31:37 +0000 Subject: [PATCH 38/90] Add support to ADC --- .../target_windows_devices_adc_config.cpp | 8 ++ .../win_dev_adc_native.cpp | 65 +++++++++ .../Windows.Devices.Adc/win_dev_adc_native.h | 73 ++++++++++ ..._native_Windows_Devices_Adc_AdcChannel.cpp | 74 ++++++++++ ...tive_Windows_Devices_Adc_AdcController.cpp | 133 ++++++++++++++++++ 5 files changed, 353 insertions(+) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_adc_config.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native.h create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_adc_config.cpp b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_adc_config.cpp new file mode 100644 index 0000000000..d7b7376bc0 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_adc_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native.cpp new file mode 100644 index 0000000000..5b9d47ef48 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native.cpp @@ -0,0 +1,65 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_adc_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeReadValue___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeDisposeChannel___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeOpenChannel___VOID__I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetChannelCount___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMaxValue___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMinValue___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetResolutionInBits___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeInit___VOID, + NULL, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Adc = +{ + "Windows.Devices.Adc", + 0xE5D11571, + method_lookup, + { 1, 1, 3, 1 } +}; diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native.h b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native.h new file mode 100644 index 0000000000..705a9416f6 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native.h @@ -0,0 +1,73 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_ADC_NATIVE_H_ +#define _WIN_DEV_ADC_NATIVE_H_ + +#include +#include +#include +#include "Board.h" +#include + +struct Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel +{ + static const int FIELD___syncLock = 1; + static const int FIELD___channelNumber = 2; + static const int FIELD___adcController = 3; + static const int FIELD___disposed = 4; + + NANOCLR_NATIVE_DECLARE(NativeReadValue___I4); + NANOCLR_NATIVE_DECLARE(NativeDisposeChannel___VOID); + + //--// + +}; + +struct Library_win_dev_adc_native_Windows_Devices_Adc_AdcController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___controllerId = 2; + static const int FIELD___channelMode = 3; + static const int FIELD__s_deviceCollection = 4; + + NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); + NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___I4); + NANOCLR_NATIVE_DECLARE(NativeGetMaxValue___I4); + NANOCLR_NATIVE_DECLARE(NativeGetMinValue___I4); + NANOCLR_NATIVE_DECLARE(NativeIsChannelModeSupported___BOOLEAN__I4); + NANOCLR_NATIVE_DECLARE(NativeGetResolutionInBits___I4); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_adc_native_Windows_Devices_Adc_AdcControllerManager +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Adc; + +// struct NF_PAL_ADC_PORT_PIN_CHANNEL +// { +// uint8_t adcIndex; +// stm32_gpio_t* portId; +// uint8_t pin; +// uint32_t adcChannel; +// }; + +//extern const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[]; +//extern const int AdcChannelCount; + +#endif //_WIN_DEV_ADC_NATIVE_H_ diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp new file mode 100644 index 0000000000..0a11a9004f --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp @@ -0,0 +1,74 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native.h" + +// // this has to be an array because ChibiOS ADC API expects that +// static adcsample_t sampleBuffer[1 * 1]; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-function" +#endif + +// // not used, just left here if needed for debugging purposes +// static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) +// { +// (void)adcp; +// (void)err; +// } + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeReadValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + int channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + uint16_t adcValue0; + uint32_t adcValue0MicroVolt; + + ADC_Params params; + ADC_Params_init(¶ms); + ADC_Handle adcHandler = ADC_open(channelNumber, ¶ms); FAULT_ON_NULL(adcHandler); + + int_fast16_t res = ADC_convert(adcHandler, &adcValue0); + + if (res == ADC_STATUS_SUCCESS) + { + adcValue0MicroVolt = ADC_convertRawToMicroVolts(adcHandler, adcValue0); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + + ADC_close(adcHandler); + + stack.SetResult_I4(adcValue0MicroVolt); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeDisposeChannel___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // left empty on purpose, nothing to do here + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp new file mode 100644 index 0000000000..3b0db76acb --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp @@ -0,0 +1,133 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native.h" + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Adc.AdcChannelMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum AdcChannelMode +{ + SingleEnded = 0, + Differential +}; + +extern const uint_least8_t ADC_count; + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeOpenChannel___VOID__I4( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // left empty on purpose, nothing to do here + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetChannelCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int channelCount; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + int controllerId = pThis[ FIELD___controllerId ].NumericByRefConst().s4; + + switch(controllerId) + { + case 1: + channelCount = ADC_count; + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Return value to the managed application + stack.SetResult_I4(channelCount); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMaxValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Currently fixed at 12 bit so return 4095 = ((2^12) - 1) + stack.SetResult_I4(4095); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMinValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + stack.SetResult_I4(0); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int mode = stack.Arg1().NumericByRef().s4; + + // Only support Single ended mode for now + stack.SetResult_Boolean( (mode == (int)AdcChannelMode::SingleEnded) ) ; + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetResolutionInBits___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Fixed at 12 bit + stack.SetResult_I4(12); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + int controllerId; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get pointer to _controllerId field in AdcController + controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + switch(controllerId) + { + case 1: + ADC_init(); + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String("ADC1"); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} From cc3fd2056795098c95a74063c2684f665d5c2e1e Mon Sep 17 00:00:00 2001 From: sjmneves Date: Thu, 28 Feb 2019 09:49:57 +0000 Subject: [PATCH 39/90] Increased CLR region - needed to increase for UART code --- .../TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c | 4 ++-- .../TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index 795ac7e3e1..d937745a52 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -11,8 +11,8 @@ const BlockRange BlockRange1[] = { // the 1st block is reserved for the flash header // so we don't take it into account for the map - { BlockRange_BLOCKTYPE_CODE , 0 , 105 }, // 0x01000800 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT , 106, 510 }, // 0x01035000 deployment + { BlockRange_BLOCKTYPE_CODE , 0 , 107 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 108, 510 }, // 0x01036000 deployment }; const BlockRegionInfo BlockRegions[] = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index f621df06de..64bf5890db 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x035000 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x036000 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } From a0b25f1640663a2fe6ba26dd0693d88293884306 Mon Sep 17 00:00:00 2001 From: sjmneves Date: Fri, 1 Mar 2019 12:30:09 +0000 Subject: [PATCH 40/90] Add support to I2C --- .../target_windows_devices_i2c_config.cpp | 10 + .../win_dev_i2c_native.cpp | 65 +++++ .../Windows.Devices.I2c/win_dev_i2c_native.h | 93 ++++++ ...c_native_Windows_Devices_I2C_I2cDevice.cpp | 270 ++++++++++++++++++ ...tive_Windows_Devices_I2c_I2cController.cpp | 33 +++ 5 files changed, 471 insertions(+) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_i2c_config.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.h create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_i2c_config.cpp b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_i2c_config.cpp new file mode 100644 index 0000000000..a4c5f1c086 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_i2c_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native.h" + +////////// +// I2C1 // +////////// diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.cpp new file mode 100644 index 0000000000..afe2427d87 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.cpp @@ -0,0 +1,65 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::NativeInit___VOID, + NULL, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeInit___VOID, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::DisposeNative___VOID, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit___WindowsDevicesI2cI2cTransferResult__SZARRAY_U1__SZARRAY_U1, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_I2c = +{ + "Windows.Devices.I2c", + 0xA44C698B, + method_lookup, + { 1, 1, 3, 1 } +}; diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.h b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.h new file mode 100644 index 0000000000..7c3a0dedd9 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.h @@ -0,0 +1,93 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_I2C_NATIVE_H_ +#define _WIN_DEV_I2C_NATIVE_H_ + +#include +#include +#include +// #include +#include "Board.h" +#include + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cConnectionSettings +{ + static const int FIELD___slaveAddress = 1; + static const int FIELD___busSpeed = 2; + static const int FIELD___sharingMode = 3; + + + //--// + +}; + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___controllerId = 2; + static const int FIELD__s_deviceCollection = 3; + + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cControllerManager +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice +{ + static const int FIELD___syncLock = 1; + static const int FIELD___deviceId = 2; + static const int FIELD___connectionSettings = 3; + static const int FIELD___disposed = 4; + + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeTransmit___WindowsDevicesI2cI2cTransferResult__SZARRAY_U1__SZARRAY_U1); + + //--// + +}; + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult +{ + static const int FIELD___bytesTransferred = 1; + static const int FIELD___status = 2; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_I2c; + +// struct representing the I2C +struct NF_PAL_I2C +{ + float ByteTime; + + I2C_Handle i2c; + I2C_Params i2cParams; + I2C_Transaction i2cTransaction; +}; + +/////////////////////////////////////////// +// declaration of the the I2C PAL strucs // +/////////////////////////////////////////// +extern NF_PAL_I2C I2C1_PAL; + + +#endif //_WIN_DEV_I2C_NATIVE_H_ diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp new file mode 100644 index 0000000000..ca51ba5a24 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp @@ -0,0 +1,270 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_dev_i2c_native.h" + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.I2c.I2cSharingMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum I2cSharingMode +{ + Exclusive = 0, + Shared +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.I2c.I2cTransferStatus (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + enum I2cTransferStatus +{ + I2cTransferStatus_FullTransfer = 0, + I2cTransferStatus_ClockStretchTimeout, + I2cTransferStatus_PartialTransfer, + I2cTransferStatus_SlaveAddressNotAcknowledged, + I2cTransferStatus_UnknownError +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.I2c.I2cBusSpeed (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum I2cBusSpeed +{ + I2cBusSpeed_StandardMode = 0, + I2cBusSpeed_FastMode +}; + +typedef Library_win_dev_i2c_native_Windows_Devices_I2c_I2cConnectionSettings I2cConnectionSettings; + + +///////////////////////////////////////////////////// +// I2C PAL strucs declared in win_dev_i2c_native.h // +///////////////////////////////////////////////////// +NF_PAL_I2C I2C1_PAL; + + +void HostI2C_CallbackFxn(I2C_Handle handle, I2C_Transaction *transaction, bool transferStatus) +{ + NATIVE_INTERRUPT_START + + // fire event for I2C transaction complete + Events_Set(SYSTEM_EVENT_FLAG_I2C_MASTER); + + NATIVE_INTERRUPT_END +} + +// estimate the time required to perform the I2C transaction +uint32_t GetEstimatedDuration(uint16_t writeSize, uint16_t readSize, float byteTime) +{ + // add an extra byte to account for the address + uint32_t estimatedDurationMiliseconds = byteTime * (writeSize + readSize + 1); + + // despite the transaction taking less than the thread time quantum + // we need to set it's timeout to a reasonable value + // because this will always execute on the next thread execution + if(estimatedDurationMiliseconds < CLR_RT_Thread::c_TimeQuantum_Milliseconds) + { + return CLR_RT_Thread::c_TimeQuantum_Milliseconds; + } + + return estimatedDurationMiliseconds; +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_I2C* palI2c = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed I2C connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the I2cDevice() constructor in managed code for details + uint8_t busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // config GPIO pins used by the I2C peripheral + // init the PAL struct for this I2C bus and assign the respective driver + // all this occurs if not already done + // why do we need to check if this is already done? because several I2cDevice objects can be created associated to the same bus just using different addresses + switch (busIndex) + { + case 1: + if(I2C1_PAL.i2c == NULL) + { + palI2c = &I2C1_PAL; + } + break; + + default: + // this I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // Create I2C for usage + I2C_Params_init(&palI2c->i2cParams); + palI2c->i2cParams.bitRate = (I2cBusSpeed)pConfig[ I2cConnectionSettings::FIELD___busSpeed ].NumericByRef().s4 == I2cBusSpeed_StandardMode ? I2C_100kHz : I2C_400kHz; + palI2c->i2cParams.transferMode = I2C_MODE_CALLBACK; + palI2c->i2cParams.transferCallbackFxn = HostI2C_CallbackFxn; + palI2c->i2c = I2C_open(Board_I2C_TMP, &palI2c->i2cParams); FAULT_ON_NULL(palI2c->i2c); + palI2c->i2cTransaction.slaveAddress = (I2cBusSpeed)pConfig[ I2cConnectionSettings::FIELD___slaveAddress ].NumericByRef().s4; + + // compute rough estimate on the time to tx/rx a byte (in milliseconds) + if((I2cBusSpeed)pConfig[ I2cConnectionSettings::FIELD___busSpeed ].NumericByRef().s4 == I2cBusSpeed_StandardMode) + { + // 100kbit/s: this is roughly 0.10ms per byte, give or take + palI2c->ByteTime = 0.1; + } + else + { + // 400kbit/s: this is roughly 0.02ms per byte, give or take + palI2c->ByteTime = 0.02; + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + I2C_close(I2C1_PAL.i2c); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit___WindowsDevicesI2cI2cTransferResult__SZARRAY_U1__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint8_t busIndex; + NF_PAL_I2C* palI2c = NULL; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + uint32_t estimatedDurationMiliseconds; + + CLR_RT_HeapBlock_Array* writeBuffer; + CLR_RT_HeapBlock_Array* readBuffer; + CLR_RT_HeapBlock* result; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // // get pointer to connection settings field + // CLR_RT_HeapBlock* connectionSettings = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the I2cDevice() constructor in managed code for details + busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // get the driver for the I2C bus + switch (busIndex) + { + case 1 : + palI2c = &I2C1_PAL; + break; + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // dereference the write and read buffers from the arguments + writeBuffer = stack.Arg1().DereferenceArray(); + if (writeBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + palI2c->i2cTransaction.writeCount = writeBuffer->m_numOfElements; + } + else + { + // nothing to write, have to zero this + palI2c->i2cTransaction.writeCount = 0; + } + + readBuffer = stack.Arg2().DereferenceArray(); + if (readBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + palI2c->i2cTransaction.readCount = readBuffer->m_numOfElements; + } + else + { + // nothing to read, have to zero this + palI2c->i2cTransaction.readCount = 0; + } + + // calculate estimated transaction duration + estimatedDurationMiliseconds = GetEstimatedDuration(palI2c->i2cTransaction.writeCount, palI2c->i2cTransaction.readCount, palI2c->ByteTime); + + // set a timeout equal to the estimated transaction duration in milliseconds + // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() bellow + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer( *writeBuffer ); + CLR_RT_ProtectFromGC gcReadBuffer( *readBuffer ); + + if (writeBuffer != NULL) + { + palI2c->i2cTransaction.writeBuf = (uint8_t*)writeBuffer->GetFirstElement(); + } + + if (readBuffer != NULL) + { + palI2c->i2cTransaction.readBuf = (uint8_t*)readBuffer->GetFirstElement(); + } + + // perform I2C transaction using driver's callback which will set the appropriate event on completion + if(stack.m_customState == 1) + { + I2C_transfer(palI2c->i2c, &palI2c->i2cTransaction); + + // bump custom state + stack.m_customState = 2; + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_I2cMaster, eventResult )); + + if(!eventResult) + { + // event occurred + + // create the return object (I2cTransferResult) + // only at this point we are sure that there will be a return from this thread so it's OK to use the managed stack + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_I2cTransferResult)); + result = top.Dereference(); FAULT_ON_NULL(result); + + // successfull transaction + // set the result field + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___status ].SetInteger((CLR_UINT32)I2cTransferStatus_FullTransfer); + + // set the bytes transferred field + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___bytesTransferred ].SetInteger((CLR_UINT32)(palI2c->i2cTransaction.writeCount + palI2c->i2cTransaction.readCount)); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + } + NANOCLR_NOCLEANUP(); +} diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp new file mode 100644 index 0000000000..686e548426 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp @@ -0,0 +1,33 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_dev_i2c_native.h" + + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "I2C1,I2C2,I2C3,I2C4," + terminator and init with the terminator + char deviceSelectorString[] = { "I2C1" }; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} \ No newline at end of file From bd2d54b1be60e4e723404ca25b4ee84b82eb1a80 Mon Sep 17 00:00:00 2001 From: sjmneves Date: Fri, 1 Mar 2019 17:40:34 +0000 Subject: [PATCH 41/90] - correct timeout waiting for I2C transfer --- ...v_i2c_native_Windows_Devices_I2C_I2cDevice.cpp | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp index ca51ba5a24..703c72a8e9 100644 --- a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp @@ -211,7 +211,11 @@ HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit // set a timeout equal to the estimated transaction duration in milliseconds // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() bellow - hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); +// hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + // we set this to an infinite timeout + // the catch is that the working thread MUST ALWAYS return at some point + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); @@ -243,7 +247,7 @@ HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_I2cMaster, eventResult )); - if(!eventResult) + if(eventResult) { // event occurred @@ -259,6 +263,13 @@ HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit // set the bytes transferred field result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___bytesTransferred ].SetInteger((CLR_UINT32)(palI2c->i2cTransaction.writeCount + palI2c->i2cTransaction.readCount)); + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); } } From 3e00d70cf29c960e459c2b92d8ad501fbc30b2b4 Mon Sep 17 00:00:00 2001 From: sjmneves Date: Fri, 1 Mar 2019 17:41:57 +0000 Subject: [PATCH 42/90] - missing changes from last commit --- .../Windows.Devices.I2c/win_dev_i2c_native.h | 2 - ...c_native_Windows_Devices_I2C_I2cDevice.cpp | 37 +------------------ 2 files changed, 1 insertion(+), 38 deletions(-) diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.h b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.h index 7c3a0dedd9..6fd7371eff 100644 --- a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.h +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native.h @@ -77,8 +77,6 @@ extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_I2c; // struct representing the I2C struct NF_PAL_I2C { - float ByteTime; - I2C_Handle i2c; I2C_Params i2cParams; I2C_Transaction i2cTransaction; diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp index 703c72a8e9..1f537353ed 100644 --- a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp @@ -55,23 +55,6 @@ void HostI2C_CallbackFxn(I2C_Handle handle, I2C_Transaction *transaction, bool t NATIVE_INTERRUPT_END } -// estimate the time required to perform the I2C transaction -uint32_t GetEstimatedDuration(uint16_t writeSize, uint16_t readSize, float byteTime) -{ - // add an extra byte to account for the address - uint32_t estimatedDurationMiliseconds = byteTime * (writeSize + readSize + 1); - - // despite the transaction taking less than the thread time quantum - // we need to set it's timeout to a reasonable value - // because this will always execute on the next thread execution - if(estimatedDurationMiliseconds < CLR_RT_Thread::c_TimeQuantum_Milliseconds) - { - return CLR_RT_Thread::c_TimeQuantum_Milliseconds; - } - - return estimatedDurationMiliseconds; -} - HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) { NANOCLR_HEADER(); @@ -115,18 +98,6 @@ HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeInit___V palI2c->i2cParams.transferCallbackFxn = HostI2C_CallbackFxn; palI2c->i2c = I2C_open(Board_I2C_TMP, &palI2c->i2cParams); FAULT_ON_NULL(palI2c->i2c); palI2c->i2cTransaction.slaveAddress = (I2cBusSpeed)pConfig[ I2cConnectionSettings::FIELD___slaveAddress ].NumericByRef().s4; - - // compute rough estimate on the time to tx/rx a byte (in milliseconds) - if((I2cBusSpeed)pConfig[ I2cConnectionSettings::FIELD___busSpeed ].NumericByRef().s4 == I2cBusSpeed_StandardMode) - { - // 100kbit/s: this is roughly 0.10ms per byte, give or take - palI2c->ByteTime = 0.1; - } - else - { - // 400kbit/s: this is roughly 0.02ms per byte, give or take - palI2c->ByteTime = 0.02; - } } NANOCLR_NOCLEANUP(); } @@ -206,13 +177,7 @@ HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit palI2c->i2cTransaction.readCount = 0; } - // calculate estimated transaction duration - estimatedDurationMiliseconds = GetEstimatedDuration(palI2c->i2cTransaction.writeCount, palI2c->i2cTransaction.readCount, palI2c->ByteTime); - - // set a timeout equal to the estimated transaction duration in milliseconds - // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() bellow -// hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); - // we set this to an infinite timeout + // set a timeout to an infinite timeout // the catch is that the working thread MUST ALWAYS return at some point // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite hbTimeout.SetInteger((CLR_INT64)-1); From 849142f0df42c6429bdee96602e0a9662e74ee56 Mon Sep 17 00:00:00 2001 From: sjmneves Date: Wed, 6 Mar 2019 17:19:02 +0000 Subject: [PATCH 43/90] Add support to SPI - untested --- .../target_windows_devices_spi_config.cpp | 10 + .../win_dev_spi_native.cpp | 78 +++++ .../Windows.Devices.Spi/win_dev_spi_native.h | 102 +++++++ ..._native_Windows_Devices_Spi_SpiBusInfo.cpp | 28 ++ ...tive_Windows_Devices_Spi_SpiController.cpp | 22 ++ ...i_native_Windows_Devices_Spi_SpiDevice.cpp | 287 ++++++++++++++++++ 6 files changed, 527 insertions(+) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_spi_config.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp create mode 100644 targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_spi_config.cpp b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_spi_config.cpp new file mode 100644 index 0000000000..ef2d3a1000 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp new file mode 100644 index 0000000000..0c9ee3b525 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp @@ -0,0 +1,78 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockFrequency___I4, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockFrequency___I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::DisposeNative___VOID, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Spi = +{ + "Windows.Devices.Spi", + 0x083DBB79, + method_lookup, + { 1, 1, 3, 0 } +}; diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h new file mode 100644 index 0000000000..bef699f7fe --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h @@ -0,0 +1,102 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_SPI_NATIVE_H_ +#define _WIN_DEV_SPI_NATIVE_H_ + + +#include +#include +#include + +#include "Board.h" +#include + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo +{ + static const int FIELD___chipSelectLineCount = 1; + + NANOCLR_NATIVE_DECLARE(get_MaxClockFrequency___I4); + NANOCLR_NATIVE_DECLARE(get_MinClockFrequency___I4); + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings +{ + static const int FIELD___csLine = 1; + static const int FIELD___clockFrequency = 2; + static const int FIELD___databitLength = 3; + static const int FIELD___spiMode = 4; + static const int FIELD___spiSharingMode = 5; + static const int FIELD___bitOrder = 6; + + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___controllerId = 2; + static const int FIELD__s_deviceCollection = 3; + + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiControllerManager +{ + static const int FIELD_STATIC__s_syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice +{ + static const int FIELD___syncLock = 1; + static const int FIELD___spiBus = 2; + static const int FIELD___deviceId = 3; + static const int FIELD___connectionSettings = 4; + static const int FIELD___disposedValue = 5; + + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + + //--// + + // static uint16_t ComputeBaudRate(uint8_t bus, int32_t requestedFrequency, int32_t& actualFrequency); + static void GetSPIConfig(int busIndex, CLR_RT_HeapBlock* config, bool bufferIs16bits); + static bool IsLongRunningOperation(uint32_t writeSize, uint32_t readSize, bool bufferIs16bits, float byteTime, uint32_t& estimatedDurationMiliseconds); + static HRESULT NativeTransfer(CLR_RT_StackFrame& stack, bool bufferIs16bits); +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Spi; + +// struct representing the SPI +struct NF_PAL_SPI +{ + SPI_Handle masterSpi; + SPI_Params spiParams; + SPI_Transaction* transactions; + uint8_t transactionCount; +}; + +/////////////////////////////////////////// +// declaration of the the SPI PAL strucs // +/////////////////////////////////////////// +extern NF_PAL_SPI SPI1_PAL; + +#endif //_WIN_DEV_SPI_NATIVE_H_ diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp new file mode 100644 index 0000000000..cd3e29a6df --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp @@ -0,0 +1,28 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native.h" + + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // return dummy value + stack.SetResult_I4 (0); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // return dummy value + stack.SetResult_I4 (0); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp new file mode 100644 index 0000000000..bb5b5aada7 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp @@ -0,0 +1,22 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native.h" + + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "SPI1" + terminator and init with the terminator + char deviceSelectorString[] = { "SPI1" }; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp new file mode 100644 index 0000000000..65874bf234 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp @@ -0,0 +1,287 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include +#include "win_dev_spi_native.h" + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Spi.SpiMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum DataBitOrder +{ + DataBitOrder_MSB = 0, + DataBitOrder_LSB +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Spi.SpiMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum SpiModes +{ + SpiModes_Mode0 = 0, + SpiModes_Mode1, + SpiModes_Mode2, + SpiModes_Mode3 +}; + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +// define this type here to make it shorter and improve code readability +typedef Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings SpiConnectionSettings; + + +///////////////////////////////////////////////////// +// SPI PAL strucs declared in win_dev_spi_native.h // +///////////////////////////////////////////////////// +NF_PAL_SPI SPI1_PAL; + + +void SpiCallback(SPI_Handle handle, SPI_Transaction *transaction) +{ + NATIVE_INTERRUPT_START + + // are there any other transactions pending? + if(SPI1_PAL.transactionCount) + { + // start transfer of 1st transaction + SPI_transfer(SPI1_PAL.masterSpi, &SPI1_PAL.transactions[SPI1_PAL.transactionCount--]); + } + else + { + // no more transactions + // fire event for SPI transaction complete + Events_Set( SYSTEM_EVENT_FLAG_SPI_MASTER ); + } + + NATIVE_INTERRUPT_END +} + +// Give a complete low-level SPI configuration from user's managed connectionSettings +void Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetSPIConfig(int busIndex, CLR_RT_HeapBlock* config, bool bufferIs16bits) +{ + SPI_Params spiParams; + + // Open SPI as slave (default) + SPI_Params_init(&spiParams); + spiParams.frameFormat = (SPI_FrameFormat)config[ SpiConnectionSettings::FIELD___spiMode ].NumericByRef().s4; + spiParams.transferMode = SPI_MODE_CALLBACK; + spiParams.mode = SPI_SLAVE; + spiParams.transferCallbackFxn = SpiCallback; + spiParams.dataSize = bufferIs16bits ? 16 : 8; + spiParams.bitRate = (uint32_t)config[ SpiConnectionSettings::FIELD___clockFrequency ].NumericByRef().s4; + SPI1_PAL.masterSpi = SPI_open(Board_SPI_SLAVE, &spiParams); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + return NativeTransfer( stack, false ); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + return NativeTransfer( stack, true ); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer( CLR_RT_StackFrame& stack, bool bufferIs16bits ) +{ + NANOCLR_HEADER(); + { + bool fullDuplex; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // Are we using SPI full-duplex for transfer? + fullDuplex = (bool)stack.Arg3().NumericByRef().u1; + + // dereference the write and read buffers from the arguments + CLR_RT_HeapBlock_Array* writeBuffer = stack.Arg1().DereferenceArray(); + CLR_RT_HeapBlock_Array* readBuffer = stack.Arg2().DereferenceArray(); + + // set a timeout to an infinite timeout + // the catch is that the working thread MUST ALWAYS return at some point + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer( *writeBuffer ); + CLR_RT_ProtectFromGC gcReadBuffer( *readBuffer ); + + // setup the operation and init buffers + if(stack.m_customState == 1) + { + // get the LL SPI configuration, depending on user's managed parameters and buffer element size + GetSPIConfig(0, pConfig, bufferIs16bits); // index '0' in this case is a dummy value... there is only one SPI available + + // alloc mem for transactions + if(fullDuplex) + { + // we'll be doing this on a single transaction + SPI1_PAL.transactions = (SPI_Transaction*)platform_malloc(sizeof(SPI_Transaction)); + SPI1_PAL.transactionCount = 1; + } + else + { + // we need two transactions + SPI1_PAL.transactions = (SPI_Transaction*)platform_malloc(sizeof(SPI_Transaction) * 2); + SPI1_PAL.transactionCount = 2; + } + + // check allocation + if(SPI1_PAL.transactions == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + else + { + if(fullDuplex) + { + if (writeBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + SPI1_PAL.transactions[0].count = writeBuffer->m_numOfElements; + + // set DMA write buffer + if(bufferIs16bits) + { + // buffer data width is 16bits + // get the pointer to the write buffer as UINT16 because it's really an UINT16 (2 bytes) + SPI1_PAL.transactions[0].txBuf = (uint16_t*)writeBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the write buffer as BYTE + SPI1_PAL.transactions[0].txBuf = (uint8_t*)writeBuffer->GetFirstElement(); + } + } + + if (readBuffer != NULL) + { + // we are in full duplex, the count for the SPI transaction was already set on the write + + if(bufferIs16bits) + { + // buffer data width is 16bits + SPI1_PAL.transactions[0].rxBuf = (uint16_t*)readBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the read buffer as BYTE + SPI1_PAL.transactions[0].rxBuf = (uint8_t*)readBuffer->GetFirstElement(); + } + } + } + else + { + // on a sequential transmition we TX first and then RX + + // TX on 1st transaction + if (writeBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + SPI1_PAL.transactions[0].count = writeBuffer->m_numOfElements; + + // set DMA write buffer + if(bufferIs16bits) + { + // buffer data width is 16bits + // get the pointer to the write buffer as UINT16 because it's really an UINT16 (2 bytes) + SPI1_PAL.transactions[0].txBuf = (uint16_t*)writeBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the write buffer as BYTE + SPI1_PAL.transactions[0].txBuf = (uint8_t*)writeBuffer->GetFirstElement(); + } + } + + // RX on 2nd transaction + if (readBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + SPI1_PAL.transactions[1].count = readBuffer->m_numOfElements; + + if(bufferIs16bits) + { + // buffer data width is 16bits + SPI1_PAL.transactions[1].rxBuf = (uint16_t*)readBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the read buffer as BYTE + SPI1_PAL.transactions[1].rxBuf = (uint8_t*)readBuffer->GetFirstElement(); + } + } + } + + // start transfer of 1st transaction + SPI_transfer(SPI1_PAL.masterSpi, &SPI1_PAL.transactions[0]); + + // take one from pending transcations counter + SPI1_PAL.transactionCount--; + + // bump custom state + stack.m_customState = 2; + } + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the Spi transaction to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_SpiMaster, eventResult )); + + if(!eventResult) + { + // timeout occurred + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + // null pointers and vars + pThis = NULL; + pConfig = NULL; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + SPI_close(SPI1_PAL.masterSpi); + + NANOCLR_NOCLEANUP_NOLABEL(); +} From 67cb84bb962b4e91a71961e626661643ee3abc31 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 7 Mar 2019 01:45:33 +0000 Subject: [PATCH 44/90] Add windows storage target header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/Include/Target_Windows_Storage.h | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 targets/TI-SimpleLink/Include/Target_Windows_Storage.h diff --git a/targets/TI-SimpleLink/Include/Target_Windows_Storage.h b/targets/TI-SimpleLink/Include/Target_Windows_Storage.h new file mode 100644 index 0000000000..888c34fef1 --- /dev/null +++ b/targets/TI-SimpleLink/Include/Target_Windows_Storage.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_WINDOWS_STORAGE_H_ +#define _TARGET_WINDOWS_STORAGE_H_ 1 + +#endif //_TARGET_WINDOWS_STORAGE_H_ From 3708550ff6a6600d07dd5f0d275bc3ea5dadf149 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 7 Mar 2019 02:56:41 +0000 Subject: [PATCH 45/90] Implement get network confing block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../targetHAL_ConfigurationManager_CC32xx.cpp | 56 ++++++++++++++++--- 1 file changed, 47 insertions(+), 9 deletions(-) diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp index cff65c1977..cd6199233d 100644 --- a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -157,7 +157,11 @@ void ConfigurationManager_EnumerateConfigurationBlocks() // Gets the network configuration block from the configuration flash sector bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) { - int sizeOfBlock = 0; + unsigned char* fileName = NULL; + + int32_t fileHandle; + uint32_t token = 0; + int32_t retVal; // validate if the requested block exists // Count has to be non zero @@ -167,9 +171,9 @@ bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, Device if(g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0) { // there is no network config block, init one with default settings - if(!InitialiseNetworkDefaultConfig((HAL_Configuration_NetworkInterface*)configurationBlock, 0)) + if(InitialiseNetworkDefaultConfig((HAL_Configuration_NetworkInterface*)configurationBlock, 0)) { - return false; + return true; } } else @@ -179,9 +183,6 @@ bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, Device return false; } } - - // set block size - sizeOfBlock = sizeof(HAL_Configuration_NetworkInterface); } else if(configuration == DeviceConfigurationOption_Wireless80211Network) { @@ -190,9 +191,6 @@ bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, Device { return false; } - - // set block size - sizeOfBlock = sizeof(HAL_Configuration_Wireless80211); } else if(configuration == DeviceConfigurationOption_X509CaRootBundle) { @@ -211,6 +209,46 @@ bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, Device // sizeOfBlock += ((HAL_Configuration_X509CaRootBundle*)blockAddress)->CertificateSize; } + if(configuration == DeviceConfigurationOption_Network) + { + // network config blocks are stored as files + + // compose file name + fileName = (unsigned char*)platform_malloc(sizeof(NETWORK_CONFIG_FILE_NAME)); + memcpy(fileName, NETWORK_CONFIG_FILE_NAME, sizeof(NETWORK_CONFIG_FILE_NAME)); + // insert index number at position N as char + fileName[NETWORK_CONFIG_FILE_INDEX_POSITION] = '0' + configurationIndex; + + fileHandle = sl_FsOpen( fileName, + SL_FS_READ, + (uint32_t *)&token); + + // on error there is no file handle, rather a negative error code + if(fileHandle > 0) + { + retVal = sl_FsRead(fileHandle, 0, (unsigned char*)configurationBlock, sizeof(HAL_Configuration_NetworkInterface)); + + // on success the return value is the amount of bytes written + if(retVal == sizeof(HAL_Configuration_NetworkInterface)) + { + retVal = sl_FsClose(fileHandle, 0, 0, 0); + + if( retVal < 0 ) + { + // error closing file, API ceremony suggests calling "abort" operation + uint8_t signature = 'A'; + sl_FsClose(fileHandle, 0, &signature, 1); + } + } + } + + if(fileName != NULL) + { + platform_free(fileName); + } + } + + return true; } From a4ef49000a99c44ba6a3386214da3229073040cd Mon Sep 17 00:00:00 2001 From: sjmneves Date: Thu, 7 Mar 2019 09:57:46 +0000 Subject: [PATCH 46/90] Adjust flash memory use (2 more blocks) --- .../TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c | 4 ++-- .../TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index d937745a52..8b8b95b655 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -11,8 +11,8 @@ const BlockRange BlockRange1[] = { // the 1st block is reserved for the flash header // so we don't take it into account for the map - { BlockRange_BLOCKTYPE_CODE , 0 , 107 }, // 0x01000800 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT , 108, 510 }, // 0x01036000 deployment + { BlockRange_BLOCKTYPE_CODE , 0 , 109 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 110, 510 }, // 0x01037000 deployment }; const BlockRegionInfo BlockRegions[] = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index 64bf5890db..5c689b4f80 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x036000 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x037000 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } From 9101476b4545a128b3341a168657d702001e8414 Mon Sep 17 00:00:00 2001 From: sjmneves Date: Fri, 8 Mar 2019 18:08:56 +0000 Subject: [PATCH 47/90] Complete provisioning task (task disabled for now) --- .../Include/targetSimpleLinkCC32xx_Threads.h | 12 ++ .../targetSimpleLinkCC32xx_ProvisioningTask.c | 197 +++++++++--------- .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 26 ++- 3 files changed, 134 insertions(+), 101 deletions(-) diff --git a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h index c8d3bca67a..257f661f94 100644 --- a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h +++ b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h @@ -48,6 +48,18 @@ #define APPS_WDT_START_KEY 0xAE42DB15 #define HWREG(x) (*((volatile unsigned long *)(x))) +#define IS_CONNECTED(status_variable) \ + GET_STATUS_BIT(status_variable, AppStatusBits_Connection) + +#define IS_IP_ACQUIRED(status_variable) \ + GET_STATUS_BIT(status_variable, AppStatusBits_IpAcquired) + +#define IS_IPV6L_ACQUIRED(status_variable) \ + GET_STATUS_BIT(status_variable, AppStatusBits_Ipv6lAcquired) + +#define IS_IPV6G_ACQUIRED(status_variable) \ + GET_STATUS_BIT(status_variable, AppStatusBits_Ipv6gAcquired) + typedef enum { /* If this bit is set: Network Processor is powered up */ diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c index 50354c154a..5342272461 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c @@ -43,6 +43,10 @@ #define ROLE_SELECTION_BY_SL (0xFF) +/* OCP register used to store device role when coming out of hibernate */ +#define OCP_REGISTER_INDEX (0) +/* if ocpRegOffset is set -> AP role, otherwise -> STATION role */ +#define OCP_REGISTER_OFFSET (10) /*! * \brief Provisioning modes @@ -1123,95 +1127,92 @@ static int32_t validateLocalLinkConnection(SlWlanMode_e *deviceRole) ASSERT_ON_ERROR(retVal); } - // /* if in AP role - // * 1) check OCP register value - // * 2) if set, it means user set AP mode via switch. - // * check for IP_ACQUIRED to indicate NWP is running - // * 4) if not set, procede with STATION role - // */ - // if(retVal == ROLE_AP) - // { - // *deviceRole = ROLE_AP; - // ocpRegVal = MAP_PRCMOCRRegisterRead(OCP_REGISTER_INDEX); - // ocpRegVal &= (1 << OCP_REGISTER_OFFSET); - // if(ocpRegVal) - // { - // if(IS_IP_ACQUIRED(OutOfBox_ControlBlock.status)) - // { - // return(0); - // } - // else - // { - // clock_gettime(CLOCK_REALTIME, &ts); - // ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; - - // retVal = sem_timedwait( - // &Provisioning_ControlBlock.connectionAsyncEvent, &ts); - // /* freertos return -1 in case of timeout */ - // if((retVal == 116) || (retVal == -1)) - // { - // UART_PRINT( - // "[Provisioning task] AP role failed to initialize\n\r"); - // GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); - // retVal = -1; - // } - // return(retVal); - // } - // } - // } + /* if in AP role + * 1) check OCP register value + * 2) if set, it means user set AP mode via switch. + * check for IP_ACQUIRED to indicate NWP is running + * 4) if not set, procede with STATION role + */ + if(retVal == ROLE_AP) + { + *deviceRole = ROLE_AP; + ocpRegVal = MAP_PRCMOCRRegisterRead(OCP_REGISTER_INDEX); + ocpRegVal &= (1 << OCP_REGISTER_OFFSET); + if(ocpRegVal) + { + if(IS_IP_ACQUIRED(nF_ControlBlock.Status)) + { + return(0); + } + else + { + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; - // if(retVal != ROLE_STA) - // { - // retVal = sl_WlanSetMode(ROLE_STA); - // ASSERT_ON_ERROR(retVal); + retVal = sem_timedwait( + &Provisioning_ControlBlock.connectionAsyncEvent, &ts); + /* freertos return -1 in case of timeout */ + if((retVal == 116) || (retVal == -1)) + { + // UART_PRINT("[Provisioning task] AP role failed to initialize\n\r"); + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + retVal = -1; + } + return(retVal); + } + } + } + + if(retVal != ROLE_STA) + { + retVal = sl_WlanSetMode(ROLE_STA); + ASSERT_ON_ERROR(retVal); - // retVal = sl_Stop(SL_STOP_TIMEOUT); - // ASSERT_ON_ERROR(retVal); + retVal = sl_Stop(SL_STOP_TIMEOUT); + ASSERT_ON_ERROR(retVal); - // retVal = sl_Start(0, 0, 0); - // if(retVal < 0 || (retVal != ROLE_STA)) - // { - // ASSERT_ON_ERROR(retVal); - // } - // UART_PRINT("[Provisioning task] Device started as STATION \n\r"); - // } + retVal = sl_Start(0, 0, 0); + if(retVal < 0 || (retVal != ROLE_STA)) + { + ASSERT_ON_ERROR(retVal); + } + // UART_PRINT("[Provisioning task] Device started as STATION \n\r"); + } - // *deviceRole = ROLE_STA; + *deviceRole = ROLE_STA; - // while(((!IS_IPV6L_ACQUIRED(OutOfBox_ControlBlock.status) || - // !IS_IPV6G_ACQUIRED(OutOfBox_ControlBlock.status)) && - // !IS_IP_ACQUIRED(OutOfBox_ControlBlock.status)) || - // !IS_CONNECTED(OutOfBox_ControlBlock.status)) - // { - // clock_gettime(CLOCK_REALTIME, &ts); - // ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; + while(((!IS_IPV6L_ACQUIRED(nF_ControlBlock.Status) || + !IS_IPV6G_ACQUIRED(nF_ControlBlock.Status)) && + !IS_IP_ACQUIRED(nF_ControlBlock.Status)) || + !IS_CONNECTED(nF_ControlBlock.Status)) + { + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; - // retVal = sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, - // &ts); - // /* freertos return -1 in case of timeout */ - // if((retVal == 116) || (retVal == -1)) - // { - // UART_PRINT( - // "[Provisioning task] Cannot connect to AP or" - // " profile does not exist\n\r"); - // GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); - // retVal = -1; + retVal = sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, &ts); + // freertos return -1 in case of timeout + if((retVal == 116) || (retVal == -1)) + { + // UART_PRINT( + // "[Provisioning task] Cannot connect to AP or" + // " profile does not exist\n\r"); + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + retVal = -1; - // return(retVal); - // } - // } + return(retVal); + } + } // UART_PRINT("[Provisioning task] Connection to AP succeeded\n\r"); - // /* Get the device's IP address */ - // ipLen = sizeof(SlNetCfgIpV4Args_t); - // ConfigOpt = 0; - // sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&ipLen, - // (uint8_t *)&ipV4); - // if(retVal < 0) - // { - // return(retVal); - // } + // Get the device's IP address + ipLen = sizeof(SlNetCfgIpV4Args_t); + ConfigOpt = 0; + sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE, &ConfigOpt, &ipLen, (uint8_t *)&ipV4); + if(retVal < 0) + { + return(retVal); + } // UART_PRINT("[Provisioning task] IP address is %d.%d.%d.%d\n\r", \ // SL_IPV4_BYTE(ipV4.Ip,3), \ @@ -1457,9 +1458,9 @@ void * provisioningTask(void *pvParameters) flash and connect immediately * 2) check if pending commit and set commit the bundle * 3) On failure, reset the MCU to rollback */ -/* it means OtaArchive is in - SL_FS_BUNDLE_STATE_PENDING_COMMIT */ - // if(OtaArchive_GetPendingCommit()) + /* it means OtaArchive is in + SL_FS_BUNDLE_STATE_PENDING_COMMIT */ + // if(OtaArchive_GetPendingCommit()) // {/* validation of new ota bundle failed, // reverting to previous bundle */ // if(retVal != 0) @@ -1503,36 +1504,36 @@ void * provisioningTask(void *pvParameters) if(deviceRole == ROLE_STA) { - /* it means a connection to AP has been established, - no need to trigger provisioning */ - if(retVal == 0) + /* it means a connection to AP has been established, + no need to trigger provisioning */ + if(retVal == 0) { GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); - /* signal to linklocal task */ - sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); + /* signal to linklocal task */ + sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); - /* signal to report server task */ - sem_post( + /* signal to report server task */ + sem_post( &Provisioning_ControlBlock. provisioningConnDoneToOtaServerSignal); } - /* it means a connection to AP failed, trigger provisioning */ - else if(retVal < 0) + /* it means a connection to AP failed, trigger provisioning */ + else if(retVal < 0) { SignalProvisioningEvent(PrvnEvent_Triggered); } } -/* it means device is initialized as AP, no need to trigger provisioning */ - if((retVal == 0) && (deviceRole == ROLE_AP)) + /* it means device is initialized as AP, no need to trigger provisioning */ + if((retVal == 0) && (deviceRole == ROLE_AP)) { GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); - /* signal to linklocal task */ - sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); + /* signal to linklocal task */ + sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); - /* signal to report server task */ - sem_post( + /* signal to report server task */ + sem_post( &Provisioning_ControlBlock.provisioningConnDoneToOtaServerSignal); } @@ -1540,7 +1541,7 @@ void * provisioningTask(void *pvParameters) { retVal = provisioningAppTask(); } - while(!retVal); /* Exit on failure */ + while(!retVal); /* Exit on failure */ return(0); } diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index ec078c8101..7bc3a49d88 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -817,12 +817,23 @@ void * mainThread(void *arg) // start network processor retc = sl_Start(NULL, NULL, NULL); - if(retc > 0) + if(retc >= 0) { // we are good! // sl_Start returns on success the role that device started on nF_ControlBlock.Role = retc; - + ////////////////////////////////////// **** uncomment this if using provisioning + // retc = sl_Stop(SL_STOP_TIMEOUT); + // if(retc < 0) + // { + // /* Handle Error */ + // // UART_PRINT("\n sl_Stop failed\n"); + // while(1) + // { + // ; + // } + // } + ////////////////////////////////////// **** } else if((retc < 0) && (retc != SL_ERROR_RESTORE_IMAGE_COMPLETE)) { @@ -841,9 +852,18 @@ void * mainThread(void *arg) // priorityParams.sched_priority = 1; // retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); // retc |= pthread_attr_setstacksize(&threadAttributes, TASK_STACK_SIZE); + // if(retc) + // { + // // Handle Error + // // UART_PRINT("Unable to configure provisioningTask thread parameters \n"); + // while(1) + // { + // ; + // } + // } // retc = pthread_create(&provisioningThread, &threadAttributes, provisioningTask, NULL); // if (retc != 0) { - // // failed to set attributes + // // Unable to create provisioningTask thread // while (1) {} // } From 9a7934e81ee66824c7614e872e9e18146bf939da Mon Sep 17 00:00:00 2001 From: sjmneves Date: Fri, 8 Mar 2019 18:14:09 +0000 Subject: [PATCH 48/90] - Complete ConfigurationManager_GetConfigurationBlock and ConfigurationManager_StoreConfigurationBlock for Wireless80211Network devices configuration blocks --- .../targetHAL_ConfigurationManager_CC32xx.cpp | 145 +++++++++++++++++- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp index cd6199233d..6675d080e6 100644 --- a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -85,7 +85,7 @@ void* ConfigurationManagerCC32xx_FindNetworkConfigurationBlocks() // wireless profiles are stored as SimpleLink WLAN profile void* ConfigurationManagerCC32xx_FindNetworkWireless80211ConfigurationBlocks() { - uint16_t index, status; + int16_t index, status; signed char name[32]; int16_t nameLength; unsigned char macAddr[6]; @@ -154,6 +154,50 @@ void ConfigurationManager_EnumerateConfigurationBlocks() // platform_free(certificateStore); } +EncryptionType GetEncryption(SlWlanSecParams_t secParams) +{ + switch (secParams.Type) + { + case SL_WLAN_SEC_TYPE_WEP: + return EncryptionType_WEP; + + // deprecated + // case SL_WLAN_SEC_TYPE_WPA: + // return EncryptionType_WPA; + + case SL_WLAN_SEC_TYPE_WPA_WPA2: + return EncryptionType_WPA2; + + default: + return EncryptionType_None; + } +} + +AuthenticationType GetAuthentication(SlWlanSecParams_t secParams) +{ + switch (secParams.Type) + { + case SL_WLAN_SEC_TYPE_OPEN: + return AuthenticationType_Open; + + case SL_WLAN_SEC_TYPE_WEP: + return AuthenticationType_WEP; + + // deprecated + // case SL_WLAN_SEC_TYPE_WPA: + // return AuthenticationType_WPA; + + case SL_WLAN_SEC_TYPE_WPA_WPA2: + return AuthenticationType_WPA2; + + case SL_WLAN_SEC_TYPE_WEP_SHARED: + return AuthenticationType_Shared; + + default: + return AuthenticationType_None; + } +} + // Gets the network configuration block from the configuration flash sector bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) { @@ -162,6 +206,13 @@ bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, Device int32_t fileHandle; uint32_t token = 0; int32_t retVal; + SlWlanSecParams_t secParams; + int16_t dummyNameLen; + uint8_t dummyMAC[SL_MAC_ADDR_LEN]; + uint32_t dummyPriority; + + HAL_Configuration_Wireless80211* wirelessConfigBlock = NULL; + // validate if the requested block exists // Count has to be non zero @@ -173,7 +224,20 @@ bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, Device // there is no network config block, init one with default settings if(InitialiseNetworkDefaultConfig((HAL_Configuration_NetworkInterface*)configurationBlock, 0)) { - return true; + // force storing profile + if(ConfigurationManager_StoreConfigurationBlock(configurationBlock, DeviceConfigurationOption_Network, 0, sizeof(HAL_Configuration_NetworkInterface), 0)) + { + // need to enumerate blocks + ConfigurationManager_EnumerateConfigurationBlocks(); + + // done here + return true; + } + else + { + // couldn't store the config block + return false; + } } } else @@ -246,10 +310,61 @@ bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, Device { platform_free(fileName); } + + // done! + return true; } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + wirelessConfigBlock = (HAL_Configuration_Wireless80211*)configurationBlock; + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); - return true; + // get profile from SimpleLink + retVal = sl_WlanProfileGet(configurationIndex, (signed char *)wirelessConfigBlock->Ssid, &dummyNameLen, &dummyMAC[0], &secParams, NULL, &dummyPriority); + if(retVal == SL_ERROR_WLAN_GET_PROFILE_INVALID_INDEX) + { + return false; + } + + // fill struct fields + wirelessConfigBlock->Id = configurationIndex; + wirelessConfigBlock->Authentication = GetAuthentication(secParams); + wirelessConfigBlock->Encryption = GetEncryption(secParams); + + // password is hidden, NULL the string + memset(wirelessConfigBlock->Password, 0, sizeof(wirelessConfigBlock->Password)); + //wirelessConfigBlock->Radio + + + // done + return true; + } + + return false; +} + +uint8_t GetSecurityType(AuthenticationType authentication) +{ + switch (authentication) + { + case AuthenticationType_Open: + return SL_WLAN_SEC_TYPE_OPEN; + + case AuthenticationType_WEP: + return SL_WLAN_SEC_TYPE_WEP; + + case AuthenticationType_WPA: + case AuthenticationType_WPA2: + return SL_WLAN_SEC_TYPE_WPA_WPA2; + + case AuthenticationType_Shared: + return SL_WLAN_SEC_TYPE_WEP_SHARED; + + default: + return SL_WLAN_SEC_TYPE_OPEN; + } } // Stores the configuration block to the configuration flash sector @@ -266,6 +381,7 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi int32_t fileHandle; uint32_t token = 0; int32_t retVal; + SlWlanSecParams_t secParams; if(configuration == DeviceConfigurationOption_Network) { @@ -310,6 +426,25 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi platform_free(fileName); } } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + HAL_Configuration_Wireless80211* wirelessConfigBlock = (HAL_Configuration_Wireless80211*)configurationBlock; + + secParams.Type = GetSecurityType(wirelessConfigBlock->Authentication); + secParams.Key = (signed char *)wirelessConfigBlock->Password; + secParams.KeyLen = hal_strlen_s((const char *)secParams.Key); + + // add profile to SimpleLink + // TODO - default priority is 0 + retVal = sl_WlanProfileAdd((const signed char *)wirelessConfigBlock->Ssid, hal_strlen_s((const char *)(wirelessConfigBlock->Ssid)), NULL, &secParams, NULL, 0, 0); + if(retVal < 0) + { + return false; + } + + // done + success = true; + } // if(configuration == DeviceConfigurationOption_Network) @@ -514,10 +649,12 @@ void InitialiseWirelessDefaultConfig(HAL_Configuration_Wireless80211 * pconfig, // Default initialisation for Network interface config blocks bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) { - uint8_t macAddress[SL_MAC_ADDR_LEN]; uint16_t macAddressLen = SL_MAC_ADDR_LEN; memset(pconfig, 0, sizeof(HAL_Configuration_NetworkInterface)); + + // make sure the config block marker is set + memcpy(pconfig->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); pconfig->InterfaceType = NetworkInterfaceType_Wireless80211; pconfig->StartupAddressMode = AddressMode_DHCP; From d29f9069527b48a74f046693615b7efae9bdde4d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Mar 2019 20:09:11 +0000 Subject: [PATCH 49/90] Implement CPU_Reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c b/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c index 4f5e6a9616..77101acda0 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c +++ b/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c @@ -5,8 +5,17 @@ #include +#define SL_STOP_TIMEOUT (200) + // FIXME TODO -inline void CPU_Reset(){ }; +void CPU_Reset() +{ + // stop network processor activities before reseting the MCU + sl_Stop(SL_STOP_TIMEOUT); + + // Reset the MCU + PRCMHibernateCycleTrigger(); +}; // CPU sleep is not currently implemented in this target inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents){ (void)level; (void)wakeEvents; }; From bff4c2e38743788b09b7a98584e23ee843cce093 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 8 Mar 2019 20:09:49 +0000 Subject: [PATCH 50/90] Increase CLR block storage for networking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c | 4 ++-- .../TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index 8b8b95b655..06d80aabe1 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -11,8 +11,8 @@ const BlockRange BlockRange1[] = { // the 1st block is reserved for the flash header // so we don't take it into account for the map - { BlockRange_BLOCKTYPE_CODE , 0 , 109 }, // 0x01000800 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT , 110, 510 }, // 0x01037000 deployment + { BlockRange_BLOCKTYPE_CODE , 0 , 116 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 117, 510 }, // 0x0103A800 deployment }; const BlockRegionInfo BlockRegions[] = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index 5c689b4f80..db4888ec31 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x037000 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03A800 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } From ae58493e41e95c6a75ef57f86f0eb6ca9d33d9ca Mon Sep 17 00:00:00 2001 From: sjmneves Date: Mon, 11 Mar 2019 15:52:43 +0000 Subject: [PATCH 51/90] Fix return network config --- .../common/targetHAL_ConfigurationManager_CC32xx.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp index 6675d080e6..f436655a48 100644 --- a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -418,6 +418,11 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi uint8_t signature = 'A'; sl_FsClose(fileHandle, 0, &signature, 1); } + else + { + // configuration stored + success = TRUE; + } } } From c303555541df26c249d57c4736458274f413e08d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 14 Mar 2019 17:45:33 +0000 Subject: [PATCH 52/90] Add define for activity heart beat MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/Include/targetHAL.h | 16 ++++++++++++++++ .../TI_CC3220SF_LAUNCHXL/target_common.h.in | 4 ++++ .../TI-SimpleLink/nanoCLR/targetPAL_Events.cpp | 2 ++ 3 files changed, 22 insertions(+) diff --git a/targets/TI-SimpleLink/Include/targetHAL.h b/targets/TI-SimpleLink/Include/targetHAL.h index 09d9249464..f544847b89 100644 --- a/targets/TI-SimpleLink/Include/targetHAL.h +++ b/targets/TI-SimpleLink/Include/targetHAL.h @@ -7,6 +7,8 @@ #define _TARGET_HAL_H_ #include +#include +#include #define GLOBAL_LOCK(x) portENTER_CRITICAL(); #define GLOBAL_UNLOCK(x) portEXIT_CRITICAL(); @@ -47,6 +49,20 @@ #define NANOCLR_STOP() HARD_BREAKPOINT() +///////////////////////////////////////////////////////////////////////////////////////////////////// +// DEBUGGER HELPER // +// The line bellow is meant to be used as helper on checking that the execution engine is running. // +// This can be inferred by checking if Events_WaitForEvents loop is running. // +// The implementation should is to be provided by each target at target_common.h.in // +//////////////////////////////////////////////////////////////////////////////////////////////////// +#if defined(BUILD_RTM) + #define EVENTS_HEART_BEAT +#else + #ifndef EVENTS_HEART_BEAT + #define EVENTS_HEART_BEAT __asm__ __volatile__ ("nop") + #endif // EVENTS_HEART_BEAT +#endif + extern int HeapBegin; extern int HeapEnd; diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in index 605485b882..2e6a552907 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in @@ -35,4 +35,8 @@ #define OEMSYSTEMINFOSTRING "nanoCLR running @ @TI_BOARD@ built with TI SL CC32xx SDK v2.40.01.01" +///////////////////////////////////// +//#define EVENTS_HEART_BEAT GPIO_toggle(Board_GPIO_LED0) +///////////////////////////////////// + #endif /* _TARGET_COMMON_H_ */ diff --git a/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp b/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp index bb79b5b357..680ac0d96d 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp +++ b/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp @@ -129,6 +129,8 @@ uint32_t Events_WaitForEvents( uint32_t powerLevel, uint32_t wakeupSystemEvents, while(true) { + EVENTS_HEART_BEAT; + uint32_t events = Events_MaskedRead( wakeupSystemEvents ); if(events) { From f09f08e5b5b4f484343053444ab1008105224772 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 15 Mar 2019 15:25:00 +0000 Subject: [PATCH 53/90] Add platform implementation of PLATFORM_DELAY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/Include/targetHAL.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/TI-SimpleLink/Include/targetHAL.h b/targets/TI-SimpleLink/Include/targetHAL.h index f544847b89..f1ca72429c 100644 --- a/targets/TI-SimpleLink/Include/targetHAL.h +++ b/targets/TI-SimpleLink/Include/targetHAL.h @@ -14,6 +14,9 @@ #define GLOBAL_UNLOCK(x) portEXIT_CRITICAL(); #define ASSERT_IRQ_MUST_BE_OFF() // TODO need to determine if this needs implementation +// platform dependent delay +#define PLATFORM_DELAY(milliSecs) vTaskDelay(milliSecs); + // Definitions for Sockets/Network #define GLOBAL_LOCK_SOCKETS(x) From 3fb5d017a104acbb878bdc4eb7631b9f1658a242 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Mar 2019 12:41:07 +0000 Subject: [PATCH 54/90] Add calls to various SimpleLink inits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index 7bc3a49d88..277237636e 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -756,6 +756,14 @@ void * mainThread(void *arg) ADC_init(); PWM_init(); + // Initialize SlNetSock layer + SlNetIf_init(0); + SlNetIf_add(SLNETIF_ID_1, "nF", + (const SlNetIf_Config_t *)&SlNetIfConfigWifi, + SLNET_IF_WIFI_PRIO); + + SlNetSock_init(0); + SlNetUtil_init(0); // initialize the realtime clock clock_settime(CLOCK_REALTIME, &ts); From 80ea6aefe5c10e83173f89c161177d41192e040b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Mar 2019 12:41:29 +0000 Subject: [PATCH 55/90] Add calls to HAL_AssertEx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index 277237636e..94a931d2fa 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -807,6 +807,7 @@ void * mainThread(void *arg) { // Handle Error ////UART_PRINT("Unable to create sl_Task thread \n"); + HAL_AssertEx(); while(1) { ; @@ -820,6 +821,7 @@ void * mainThread(void *arg) { // Handle Error //UART_PRINT("Network Terminal - Couldn't configure Network Processor - %d\n",RetVal); + HAL_AssertEx(); return(NULL); } @@ -849,6 +851,7 @@ void * mainThread(void *arg) // //UART_PRINT("\n sl_Start failed\n"); // //UART_PRINT("\n %s Example Ver. %s\n",APPLICATION_NAME, // APPLICATION_VERSION); + HAL_AssertEx(); while(1) { ; @@ -901,6 +904,7 @@ void * mainThread(void *arg) if(retc != 0) { // pthread_create() failed + HAL_AssertEx(); while(1) { ; @@ -923,6 +927,7 @@ void * mainThread(void *arg) if(retc != 0) { // pthread_create() failed + HAL_AssertEx(); while(1) { ; From 25536ea73a1acf2e87664ae634d97c9e9e536c9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Mar 2019 12:43:02 +0000 Subject: [PATCH 56/90] Fix call to sockets error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Should be calling SOCK_getsocklasterror and not the HAL implementation Signed-off-by: José Simões --- .../sys_net_native_System_Net_Sockets_NativeSocket.cpp | 2 +- src/PAL/Include/nanoPAL_Sockets.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp index 47737964c2..eb2c456ee0 100644 --- a/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp +++ b/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp @@ -441,7 +441,7 @@ HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::BindConnectHelpe fThrowOnWouldBlock = (stack.Arg2().NumericByRefConst().s4 != 0); - if(!fThrowOnWouldBlock && HAL_SOCK_getsocklasterror( handle ) == SOCK_EWOULDBLOCK) + if(!fThrowOnWouldBlock && SOCK_getsocklasterror( handle ) == SOCK_EWOULDBLOCK) { NANOCLR_SET_AND_LEAVE(S_OK); } diff --git a/src/PAL/Include/nanoPAL_Sockets.h b/src/PAL/Include/nanoPAL_Sockets.h index 82a3203e1a..427fb56823 100644 --- a/src/PAL/Include/nanoPAL_Sockets.h +++ b/src/PAL/Include/nanoPAL_Sockets.h @@ -586,6 +586,7 @@ int SOCK_getaddrinfo( const char* nodename, char* servname, const struct SOCK_a void SOCK_freeaddrinfo( struct SOCK_addrinfo* ai ); int SOCK_ioctl( int socket, int cmd, int* data ); int SOCK_getlasterror(); +int SOCK_getsocklasterror( int socket ); int SOCK_select( int socket, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* except, const struct SOCK_timeval* timeout ); int SOCK_setsockopt( int socket, int level, int optname, const char* optval, int optlen ); int SOCK_getsockopt( int socket, int level, int optname, char* optval, int* optlen ); From 69f08b33dfa918ff7a493544bd80f503e19d3360 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Mar 2019 12:43:52 +0000 Subject: [PATCH 57/90] Add check for network security on TI SimpleLink RTOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 1130057ec3..2f936e0494 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -578,6 +578,8 @@ if(USE_NETWORKING_OPTION) message(STATUS "Support for networking enabled with security from OpenSSL") elseif(NF_SECURITY_MBEDTLS) message(STATUS "Support for networking enabled with security from mbed TLS") + elseif(RTOS_TI_SIMPLELINK_CHECK) + message(STATUS "Support for networking enabled with security") else() message(STATUS "Support for networking enabled WITHOUT security") endif() From 9c33a5edb60106b1bb04ca1147a4efbd9e96e903 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Mar 2019 12:44:19 +0000 Subject: [PATCH 58/90] Update Devices.Gpio declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp index defcbb4918..4e11db02cb 100644 --- a/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp +++ b/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp @@ -81,5 +81,5 @@ const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Gpio = "Windows.Devices.Gpio", 0xB1F30A6A, method_lookup, - { 1, 0, 5, 1 } + { 1, 1, 0, 0 } }; From a6a32b77f5284df6da33eee00739a569daa0ef6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 20 Mar 2019 17:09:03 +0000 Subject: [PATCH 59/90] Update CC32xx SDK to v2.40.02.00 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 2f936e0494..393fdf56fb 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1167,8 +1167,8 @@ elseif(RTOS_TI_SIMPLELINK_CHECK) message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") endif() - message(STATUS "TI SimpleLink CC32xx SDK (latest available code from v2.40.01.01") - set(TI_SL_CC32xx_SDK_TAG "2.40.01.01") + message(STATUS "TI SimpleLink CC32xx SDK (latest available code from v2.40.02.00") + set(TI_SL_CC32xx_SDK_TAG "2.40.02.00") # need to setup a separate CMake project to download the code from the GitHub repository # otherwise it won't be available before the actual build step From 25be217b12acb797569e5512940a4e34ef61408a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Mar 2019 11:01:27 +0000 Subject: [PATCH 60/90] Increase CLR region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c | 4 ++-- .../TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index 06d80aabe1..0e4f82a874 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -11,8 +11,8 @@ const BlockRange BlockRange1[] = { // the 1st block is reserved for the flash header // so we don't take it into account for the map - { BlockRange_BLOCKTYPE_CODE , 0 , 116 }, // 0x01000800 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT , 117, 510 }, // 0x0103A800 deployment + { BlockRange_BLOCKTYPE_CODE , 0 , 117 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 118, 510 }, // 0x0103B000 deployment }; const BlockRegionInfo BlockRegions[] = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index db4888ec31..f207810849 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03A800 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03B000 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } From 4aadfc3d592316704d61d3f5a9e3543af47771eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Mar 2019 11:12:03 +0000 Subject: [PATCH 61/90] Adjust stack size of CLR thread MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index 94a931d2fa..25e944024e 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -915,7 +915,7 @@ void * mainThread(void *arg) pthread_attr_init(&threadAttributes); priorityParams.sched_priority = 1; retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); - retc |= pthread_attr_setstacksize(&threadAttributes, 10000); + retc |= pthread_attr_setstacksize(&threadAttributes, 8192); if (retc != 0) { // failed to set attributes From a55d1e226ca1aa94684efb8b4ad677e098906ead Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Mar 2019 12:04:35 +0000 Subject: [PATCH 62/90] Initial support for Simple Link sockets and network interface calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/common/CMakeLists.txt | 6 + .../common/simplelink_sockets.cpp | 739 ++++++++++++++++++ .../TI-SimpleLink/common/simplelink_sockets.h | 126 +++ .../common/simplelink_sockets_functions.cpp | 165 ++++ .../common/sockets_simplelink.cpp | 657 ++++++++++++++++ .../TI-SimpleLink/common/sockets_simplelink.h | 188 +++++ .../TI-SimpleLink/common/ssl_simplelink.cpp | 120 +++ 7 files changed, 2001 insertions(+) create mode 100644 targets/TI-SimpleLink/common/simplelink_sockets.cpp create mode 100644 targets/TI-SimpleLink/common/simplelink_sockets.h create mode 100644 targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp create mode 100644 targets/TI-SimpleLink/common/sockets_simplelink.cpp create mode 100644 targets/TI-SimpleLink/common/sockets_simplelink.h create mode 100644 targets/TI-SimpleLink/common/ssl_simplelink.cpp diff --git a/targets/TI-SimpleLink/common/CMakeLists.txt b/targets/TI-SimpleLink/common/CMakeLists.txt index eb9c88e27a..6bbe6947d6 100644 --- a/targets/TI-SimpleLink/common/CMakeLists.txt +++ b/targets/TI-SimpleLink/common/CMakeLists.txt @@ -26,5 +26,11 @@ if("${TARGET_SERIES}" STREQUAL "CC32xx") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager_CC32xx.cpp") endif() +# append sockets and SSL driver +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/simplelink_sockets_functions.cpp") +# list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/simplelink_sockets.cpp") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/sockets_simplelink.cpp") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/ssl_simplelink.cpp") + # make var global set(TARGET_TI_SimpleLink_COMMON_SOURCES ${TARGET_TI_SimpleLink_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/targets/TI-SimpleLink/common/simplelink_sockets.cpp b/targets/TI-SimpleLink/common/simplelink_sockets.cpp new file mode 100644 index 0000000000..49bec50e54 --- /dev/null +++ b/targets/TI-SimpleLink/common/simplelink_sockets.cpp @@ -0,0 +1,739 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "simplelink_sockets.h" + +// extern "C" +// { +// #include "lwip\init.h" +// #include "lwip\tcpip.h" +// #include "lwip\dns.h" +// #include "lwip\netifapi.h" +// #include "lwip\Netdb.h" +// #include "lwip\tcp.h" +// #include "lwip\Sockets.h" +// #include "lwip\dhcp.h" +// #include "lwip\netif.h" +// } + + +//--// + +#if defined(DEBUG) +#define DEBUG_HANDLE_SOCKET_ERROR(t,a) +// assume there is something to add in later?? +#else +#define DEBUG_HANDLE_SOCKET_ERROR(t,a) +#endif + +//--// + +SimpleLink_SOCKETS_Driver g_SimpleLink_SOCKETS_Driver; + +//--// +static HAL_CONTINUATION PostAddressChangedContinuation; +static HAL_CONTINUATION PostAvailabilityOnContinuation; +static HAL_CONTINUATION PostAvailabilityOffContinuation; + +void SimpleLink_SOCKETS_Driver::PostAddressChanged(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AddressChanged, 0); +} + +void SimpleLink_SOCKETS_Driver::PostAvailabilityOn(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AvailabilityChanged, NetworkEventFlags_NetworkAvailable); +} + +void SimpleLink_SOCKETS_Driver::PostAvailabilityOff(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AvailabilityChanged, NetworkEventFlags_NetworkNOTAvailable); +} + +void SimpleLink_SOCKETS_Driver::Link_callback() +{ + // if (netif_is_link_up(netif)) + // { + // if (!PostAvailabilityOnContinuation.IsLinked()) + // PostAvailabilityOnContinuation.Enqueue(); + // } + // else + // { + // if (!PostAvailabilityOffContinuation.IsLinked()) + // PostAvailabilityOffContinuation.Enqueue(); + // } + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); + Events_Set(SYSTEM_EVENT_FLAG_NETWORK); +} + +void SimpleLink_SOCKETS_Driver::Status_callback() +{ + if (!PostAddressChangedContinuation.IsLinked()) + PostAddressChangedContinuation.Enqueue(); + +#if !defined(BUILD_RTM) + // lcd_printf("\f\n\n\n\n\n\nLink Update: %s\n", (netif_is_up(netif) ? "UP " : "DOWN")); + // lcd_printf(" IP: %d.%d.%d.%d\n", (netif->ip_addr.addr >> 0) & 0xFF, + // (netif->ip_addr.addr >> 8) & 0xFF, + // (netif->ip_addr.addr >> 16) & 0xFF, + // (netif->ip_addr.addr >> 24) & 0xFF); + // lcd_printf(" SM: %d.%d.%d.%d\n", (netif->netmask.addr >> 0) & 0xFF, + // (netif->netmask.addr >> 8) & 0xFF, + // (netif->netmask.addr >> 16) & 0xFF, + // (netif->netmask.addr >> 24) & 0xFF); + // lcd_printf(" GW: %d.%d.%d.%d\n", (netif->gw.addr >> 0) & 0xFF, + // (netif->gw.addr >> 8) & 0xFF, + // (netif->gw.addr >> 16) & 0xFF, + // (netif->gw.addr >> 24) & 0xFF); + +//FIXME debug_printf("IP Address: %d.%d.%d.%d\n", (netif->ip_addr.u_addr.ip4.addr >> 0) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 8) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 16) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 24) & 0xFF); +#if LWIP_DNS + if (netif->flags & NETIF_FLAG_ETHARP) + { + //ip_addr_t * dns1 = dns_getserver(0); + //ip_addr_t * dns2 = dns_getserver(1); + + // lcd_printf(" dns1: %d.%d.%d.%d\n", (dns1.addr >> 0) & 0xFF, + // (dns1.addr >> 8) & 0xFF, + // (dns1.addr >> 16) & 0xFF, + // (dns1.addr >> 24) & 0xFF); + + // lcd_printf(" dns2: %d.%d.%d.%d\n", (dns2.addr >> 0) & 0xFF, + // (dns2.addr >> 8) & 0xFF, + // (dns2.addr >> 16) & 0xFF, + // (dns2.addr >> 24) & 0xFF); + } +#endif + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); + Events_Set(SYSTEM_EVENT_FLAG_NETWORK); +} +#endif + +bool SimpleLink_SOCKETS_Driver::Initialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + + struct netif *networkInterface; + HAL_Configuration_NetworkInterface networkConfiguration; + int interfaceNumber; + + PostAddressChangedContinuation.InitializeCallback(PostAddressChanged, NULL); + PostAvailabilityOnContinuation.InitializeCallback(PostAvailabilityOn, NULL); + PostAvailabilityOffContinuation.InitializeCallback(PostAvailabilityOff, NULL); + + // create m_interfaceNumber array + int interfaceCount = g_TargetConfiguration.NetworkInterfaceConfigs->Count; + // FIXME + // g_SimpleLink_SOCKETS_Driver.m_interfaces = (LWIP_DRIVER_INTERFACE_DATA*)platform_malloc(interfaceCount * sizeof(LWIP_DRIVER_INTERFACE_DATA)); + + // FIXME + // already done? + /* Initialize the target board lwIP stack */ + //nanoHAL_Network_Initialize(); + + for (int i = 0; i < g_TargetConfiguration.NetworkInterfaceConfigs->Count; i++) + { + // load network interface configuration from storage + if(!ConfigurationManager_GetConfigurationBlock((void*)&networkConfiguration, DeviceConfigurationOption_Network, i)) + { + // failed to load configuration + // FIXME output error? + // move to the next, if any + continue; + } + _ASSERTE(networkConfiguration.StartupAddressMode > 0); + + /* Bind and Open the Ethernet driver */ + Network_Interface_Bind(i); + interfaceNumber = Network_Interface_Open(i); + + if (interfaceNumber == SOCK_SOCKET_ERROR) + { + DEBUG_HANDLE_SOCKET_ERROR("Network init", FALSE); +//FIXME debug_printf("SocketError: %d\n", errorCode); + continue; + } + + g_SimpleLink_SOCKETS_Driver.m_interfaces[i].m_interfaceNumber = interfaceNumber; + +// UpdateAdapterConfiguration(i, (UpdateOperation_Dhcp | UpdateOperation_Dns), &networkConfiguration); + +// networkInterface = netif_find_interface(interfaceNumber); + +// if (networkInterface) +// { +// netif_set_link_callback(networkInterface, Link_callback); + +// if (netif_is_link_up(networkInterface)) +// { +// Link_callback(networkInterface); +// } + +// netif_set_status_callback(networkInterface, Status_callback); + +// if (netif_is_up(networkInterface)) +// { +// Status_callback(networkInterface); +// } + +// // default debugger interface +// if (0 == i) +// { +// #if LWIP_IPV6 +// //uint8_t* addr = (uint8_t*)&networkInterface->ip_addr.u_addr.ip4.addr; +// #else +// //uint8_t* addr = (uint8_t*)&networkInterface->ip_addr.addr; +// #endif +// // lcd_printf("\f\n\n\n\n\n\n\nip address: %d.%d.%d.%d\r\n", addr[0], addr[1], addr[2], addr[3]); +// // FIXME debug_printf("ip address from interface info: %d.%d.%d.%d\r\n", addr[0], addr[1], addr[2], addr[3]); +// } +// } + } + + return TRUE; +} + +bool SimpleLink_SOCKETS_Driver::Uninitialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + + PostAddressChangedContinuation.Abort(); + PostAvailabilityOnContinuation.Abort(); + PostAvailabilityOffContinuation.Abort(); + + for(int i=0; iCount; i++) + { + Network_Interface_Close(i); + } + +//FIXME tcpip_shutdown(); +// tcpip_shutdown is MS method added to lwip tcpip.c + + return TRUE; +} + +SOCK_SOCKET SimpleLink_SOCKETS_Driver::Accept(SOCK_SOCKET socket, SOCK_sockaddr* address, int* addressLen) +{ + NATIVE_PROFILE_PAL_NETWORK(); + SOCK_SOCKET ret; + + sockaddr_in addr; + + if (address) + { + SOCK_SOCKADDR_TO_SOCKADDR(address, addr, addressLen); + } + + ret = lwip_accept(socket, address?(sockaddr*)&addr:NULL, (u32_t*)addressLen); + + if(address) + { + SOCKADDR_TO_SOCK_SOCKADDR(address, addr, addressLen); + } + + return ret; +} + +int SimpleLink_SOCKETS_Driver::SetSockOpt( SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeLevel; + int nativeOptionName; + int nativeIntValue; + char *pNativeOptionValue = (char*)optval; + struct linger lopt = {0,0}; + + switch(level) + { + case SOCK_IPPROTO_IP: + nativeLevel = IPPROTO_IP; + nativeOptionName = GetNativeIPOption(optname); + break; + case SOCK_IPPROTO_TCP: + nativeLevel = IPPROTO_TCP; + nativeOptionName = GetNativeTcpOption(optname); + break; + case SOCK_IPPROTO_UDP: + case SOCK_IPPROTO_ICMP: + case SOCK_IPPROTO_IGMP: + case SOCK_IPPROTO_IPV4: + case SOCK_SOL_SOCKET: + nativeLevel = SOL_SOCKET; + nativeOptionName = GetNativeSockOption(optname); + + switch(optname) + { + // If linger value negative then linger off + // otherwise enabled and linger value is number of seconds + case SOCK_SOCKO_LINGER: + { + int lingerValue = *(int*)optval; + if ( lingerValue >= 0 ) + { + lopt.l_onoff = 1; + lopt.l_linger = abs(lingerValue); + } + pNativeOptionValue = (char*)&lopt; + optlen = sizeof(lopt); + } + break; + + case SOCK_SOCKO_DONTLINGER: + case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + nativeIntValue = !*(int*)optval; + pNativeOptionValue = (char*)&nativeIntValue; + break; + default: + break; + } + break; + default: + nativeLevel = 0; + nativeOptionName = 0; + break; + } + + return lwip_setsockopt(socket, nativeLevel, nativeOptionName, pNativeOptionValue, optlen); +} + +int SimpleLink_SOCKETS_Driver::GetSockOpt( SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeLevel; + int nativeOptionName; + char* pNativeOptval = optval; + int ret; + + switch(level) + { + case SOCK_IPPROTO_IP: + nativeLevel = IPPROTO_IP; + nativeOptionName = GetNativeIPOption(optname); + break; + case SOCK_IPPROTO_TCP: + nativeLevel = IPPROTO_TCP; + nativeOptionName = GetNativeTcpOption(optname); + break; + case SOCK_IPPROTO_UDP: + case SOCK_IPPROTO_ICMP: + case SOCK_IPPROTO_IGMP: + case SOCK_IPPROTO_IPV4: + case SOCK_SOL_SOCKET: + nativeLevel = SOL_SOCKET; + nativeOptionName = GetNativeSockOption(optname); + break; + default: + nativeLevel = level; + nativeOptionName = optname; + break; + } + + ret = lwip_getsockopt(socket, nativeLevel, nativeOptionName, pNativeOptval, (u32_t*)optlen); + + if(ret == 0) + { + switch(level) + { + case SOCK_SOL_SOCKET: + switch(optname) + { + case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + case SOCK_SOCKO_DONTLINGER: + *optval = !(*(int*)optval != 0); + break; + + case SOCK_SOCKO_ACCEPTCONNECTION: + case SOCK_SOCKO_BROADCAST: + case SOCK_SOCKO_KEEPALIVE: + *optval = (*(int*)optval != 0); + break; + } + break; + } + } + + return ret; +} + +int SimpleLink_SOCKETS_Driver::GetSockName( SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int ret; + + sockaddr_in addr; + + SOCK_SOCKADDR_TO_SOCKADDR(name, addr, namelen); + + ret = lwip_getsockname(socket, (sockaddr*)&addr, (u32_t*)namelen); + + SOCKADDR_TO_SOCK_SOCKADDR(name, addr, namelen); + + return ret; +} + +int SimpleLink_SOCKETS_Driver::RecvFrom( SOCK_SOCKET socket, char* buf, int len, int flags, SOCK_sockaddr* from, int* fromlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + sockaddr_in addr; + sockaddr *pFrom = NULL; + int ret; + + if(from) + { + SOCK_SOCKADDR_TO_SOCKADDR(from, addr, fromlen); + pFrom = (sockaddr*)&addr; + } + + ret = lwip_recvfrom(socket, buf, len, flags, pFrom, (u32_t*)fromlen); + + if(from && ret != SOCK_SOCKET_ERROR) + { + SOCKADDR_TO_SOCK_SOCKADDR(from, addr, fromlen); + } + + return ret; +} + +int SimpleLink_SOCKETS_Driver::SendTo( SOCK_SOCKET socket, const char* buf, int len, int flags, const SOCK_sockaddr* to, int tolen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + sockaddr_in addr; + + SOCK_SOCKADDR_TO_SOCKADDR(to, addr, &tolen); + + return lwip_sendto(socket, buf, len, flags, (sockaddr*)&addr, (u32_t)tolen); +} + +struct dhcp_client_id +{ + uint8_t code; + uint8_t length; + uint8_t type; + uint8_t clientId[6]; +}; + +int SimpleLink_SOCKETS_Driver::GetNativeTcpOption (int optname) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_TCP_NODELAY: + nativeOptionName = TCP_NODELAY; + break; + + case SOCK_SOCKO_KEEPALIVE: + nativeOptionName = TCP_KEEPALIVE; + break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + } + return nativeOptionName; +} + +int SimpleLink_SOCKETS_Driver::GetNativeSockOption (int optname) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_SOCKO_DONTLINGER: + case SOCK_SOCKO_LINGER: + nativeOptionName = SO_LINGER; + break; + case SOCK_SOCKO_SENDTIMEOUT: + nativeOptionName = SO_SNDTIMEO; + break; + case SOCK_SOCKO_RECEIVETIMEOUT: + nativeOptionName = SO_RCVTIMEO; + break; + case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + case SOCK_SOCKO_REUSEADDRESS: + nativeOptionName = SO_REUSEADDR; + break; + case SOCK_SOCKO_KEEPALIVE: + nativeOptionName = SO_KEEPALIVE; + break; + case SOCK_SOCKO_ERROR: + nativeOptionName = SO_ERROR; + break; + case SOCK_SOCKO_BROADCAST: + nativeOptionName = SO_BROADCAST; + break; + case SOCK_SOCKO_RECEIVEBUFFER: + nativeOptionName = SO_RCVBUF; + break; + case SOCK_SOCKO_SENDBUFFER: + nativeOptionName = SO_SNDBUF; + break; + case SOCK_SOCKO_ACCEPTCONNECTION: + nativeOptionName = SO_ACCEPTCONN; + break; + case SOCK_SOCKO_TYPE: + nativeOptionName = SO_TYPE; + break; + + case SOCK_SOCKO_USELOOPBACK: + nativeOptionName = SO_USELOOPBACK; + break; + case SOCK_SOCKO_DONTROUTE: + nativeOptionName = SO_DONTROUTE; + break; + case SOCK_SOCKO_OUTOFBANDINLINE: + nativeOptionName = SO_OOBINLINE; + break; + + case SOCK_SOCKO_DEBUG: + nativeOptionName = SO_DEBUG; + break; + + case SOCK_SOCKO_SENDLOWWATER: + nativeOptionName = SO_SNDLOWAT; + break; + + case SOCK_SOCKO_RECEIVELOWWATER: + nativeOptionName = SO_RCVLOWAT; + break; + +// case SOCK_SOCKO_MAXCONNECTIONS: //don't support + case SOCK_SOCKO_UPDATE_ACCEPT_CTX: + case SOCK_SOCKO_UPDATE_CONNECT_CTX: + nativeOptionName = 0; + break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + + } + + return nativeOptionName; +} + +int SimpleLink_SOCKETS_Driver::GetNativeIPOption (int optname) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_IPO_TTL: + nativeOptionName = IP_TTL; + break; + case SOCK_IPO_TOS: + nativeOptionName = IP_TOS; + break; +#if LWIP_IGMP + case SOCK_IPO_MULTICAST_IF: + nativeOptionName = IP_MULTICAST_IF; + break; + case SOCK_IPO_MULTICAST_TTL: + nativeOptionName = IP_MULTICAST_TTL; + break; + case SOCK_IPO_MULTICAST_LOOP: + nativeOptionName = IP_MULTICAST_LOOP; + break; + case SOCK_IPO_ADD_MEMBERSHIP: + nativeOptionName = IP_ADD_MEMBERSHIP; + break; + case SOCK_IPO_DROP_MEMBERSHIP: + nativeOptionName = IP_DROP_MEMBERSHIP; + break; +#else + case SOCK_IPO_MULTICAST_IF: + case SOCK_IPO_MULTICAST_TTL: + case SOCK_IPO_MULTICAST_LOOP: + case SOCK_IPO_ADD_MEMBERSHIP: + case SOCK_IPO_DROP_MEMBERSHIP: +#endif + case SOCK_IPO_ADD_SOURCE_MEMBERSHIP: + case SOCK_IPO_DROP_SOURCE_MEMBERSHIP: + case SOCK_IPO_OPTIONS: + case SOCK_IPO_HDRINCL: + case SOCK_IPO_IP_DONTFRAGMENT: + case SOCK_IPO_BLOCK_SOURCE: + case SOCK_IPO_UBLOCK_SOURCE: + case SOCK_IPO_PACKET_INFO: + nativeOptionName = 0; + break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + } + + return nativeOptionName; +} + +int SimpleLink_SOCKETS_Driver::GetNativeError ( int error ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int ret; + + switch(error) + { + case EINTR: + ret = SOCK_EINTR; + break; + + case EACCES: + ret = SOCK_EACCES; + break; + + case EFAULT: + ret = SOCK_EFAULT; + break; + + case EINVAL: + ret = SOCK_EINVAL; + break; + + case EMFILE: + ret = SOCK_EMFILE; + break; + + case EAGAIN: + case EBUSY: + /* case EWOULDBLOCK: same as EINPROGRESS */ + case EINPROGRESS: + ret = SOCK_EWOULDBLOCK; + break; + + case EALREADY: + ret = SOCK_EALREADY; + break; + + case ENOTSOCK: + ret = SOCK_ENOTSOCK; + break; + + case EDESTADDRREQ: + ret = SOCK_EDESTADDRREQ; + break; + + case EMSGSIZE: + ret = SOCK_EMSGSIZE; + break; + + case EPROTOTYPE: + ret = SOCK_EPROTOTYPE; + break; + + case ENOPROTOOPT: + ret = SOCK_ENOPROTOOPT; + break; + + case EPROTONOSUPPORT: + ret = SOCK_EPROTONOSUPPORT; + break; +// TODO nanoframework check why missing + // case ESOCKTNOSUPPORT: + // ret = SOCK_ESOCKTNOSUPPORT; + // break; + + case EPFNOSUPPORT: + ret = SOCK_EPFNOSUPPORT; + break; + + case EAFNOSUPPORT: + ret = SOCK_EAFNOSUPPORT; + break; + + case EADDRINUSE: + ret = SOCK_EADDRINUSE; + break; + + case EADDRNOTAVAIL: + ret = SOCK_EADDRNOTAVAIL; + break; + + case ENETDOWN: + ret = SOCK_ENETDOWN; + break; + + case ENETUNREACH: + ret = SOCK_ENETUNREACH; + break; + + case ENETRESET: + ret = SOCK_ENETRESET; + break; + + case ECONNABORTED: + ret = SOCK_ECONNABORTED; + break; + + case ECONNRESET: + ret = SOCK_ECONNRESET; + break; + + case ENOBUFS: + case ENOMEM: + ret = SOCK_ENOBUFS; + break; + + case EISCONN: + ret = SOCK_EISCONN; + break; + + case ENOTCONN: + ret = SOCK_EISCONN; + break; + +#if !defined(__GNUC__) // same as ENOTSOCK for GCC + case ESHUTDOWN: + ret = SOCK_ESHUTDOWN; + break; +#endif + + case ETIMEDOUT: + ret = SOCK_ETIMEDOUT; + break; + + case ECONNREFUSED: + ret = SOCK_ECONNREFUSED; + break; + + case EHOSTDOWN: + ret = SOCK_EHOSTDOWN; + break; + + case EHOSTUNREACH: + ret = SOCK_EHOSTUNREACH; + break; + + case ENODATA: + ret = SOCK_NO_DATA; + break; + + default: + ret = error; + break; + } + + return (ret); +} diff --git a/targets/TI-SimpleLink/common/simplelink_sockets.h b/targets/TI-SimpleLink/common/simplelink_sockets.h new file mode 100644 index 0000000000..2f99320314 --- /dev/null +++ b/targets/TI-SimpleLink/common/simplelink_sockets.h @@ -0,0 +1,126 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SIMPLELINK_SOCKETS_H_ +#define _SIMPLELINK_SOCKETS_H_ + +#include +#include + +#define NATIVE_PROFILE_PAL_NETWORK() + +////////////////////////////////////////////////////////////////////////////// +// SOCKET driver +// + +// struct LWIP_DRIVER_INTERFACE_DATA +// { +// int m_interfaceNumber; +// }; + +// #define SOCK_SOCKADDR_TO_SOCKADDR(ssa, sa, addrLen) \ +// sa.sin_len = (u8_t)sizeof(sa); \ +// sa.sin_family = (u8_t)((SOCK_sockaddr_in*)ssa)->sin_family; \ +// sa.sin_port = ((SOCK_sockaddr_in*)ssa)->sin_port; \ +// sa.sin_addr.s_addr = ((SOCK_sockaddr_in*)ssa)->sin_addr.S_un.S_addr; \ +// memcpy(sa.sin_zero, ((SOCK_sockaddr_in*)ssa)->sin_zero, sizeof(sa.sin_zero)); \ +// *addrLen = sizeof(sa) + +// #define SOCKADDR_TO_SOCK_SOCKADDR(ssa, sa, addrLen) \ +// ((SOCK_sockaddr_in*)ssa)->sin_port = sa.sin_port; \ +// ((SOCK_sockaddr_in*)ssa)->sin_addr.S_un.S_addr = sa.sin_addr.s_addr; \ +// ((SOCK_sockaddr_in*)ssa)->sin_family = sa.sin_family; \ +// memcpy(((SOCK_sockaddr_in*)ssa)->sin_zero, sa.sin_zero, sizeof(((SOCK_sockaddr_in*)ssa)->sin_zero)); \ +// *addrLen = sizeof(SOCK_sockaddr_in) + + +struct SimpleLink_SOCKETS_Driver +{ + static bool Initialize(); + + static bool Uninitialize(); + + static SOCK_SOCKET Socket( int family, int type, int protocol ); + + static int Bind( SOCK_SOCKET socket, const SOCK_sockaddr* address, int addressLen ); + + static int Connect(SOCK_SOCKET socket, const SOCK_sockaddr* address, int addressLen); + + static int Send(SOCK_SOCKET socket, const char* buf, int len, int flags); + + static int Recv(SOCK_SOCKET socket, char* buf, int len, int flags); + + static int Close(SOCK_SOCKET socket); + + static int Listen(SOCK_SOCKET socket, int backlog ); + + static SOCK_SOCKET Accept(SOCK_SOCKET socket, SOCK_sockaddr* address, int* addressLen ); + + + static int Shutdown(SOCK_SOCKET socket, int how ); + + static int GetAddrInfo(const char* nodename, + char* servname, + const SOCK_addrinfo* hints, + SOCK_addrinfo** res ); + + static void FreeAddrInfo(SOCK_addrinfo* ai ); + + static int Ioctl(SOCK_SOCKET socket, int cmd, int* data ); + + static int GetLastError(); + + static int GetSockLastError(SOCK_SOCKET socket); + + static int GetNativeTcpOption (int optname); + + static int GetNativeSockOption (int optname); + + static int GetNativeError( int error ); + + static int GetNativeIPOption (int optname); + + static int Select(int nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* exceptfds, const SOCK_timeval* timeout ); + + static int SetSockOpt(SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ); + + static int GetSockOpt(SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ); + + static int GetPeerName(SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ); + + static int GetSockName(SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ); + + static int RecvFrom(SOCK_SOCKET s, char* buf, int len, int flags, SOCK_sockaddr* from, int* fromlen ); + + static int SendTo(SOCK_SOCKET s, const char* buf, int len, int flags, const SOCK_sockaddr* to, int tolen ); + + static HRESULT LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex); + + static HRESULT UpdateAdapterConfiguration( uint32_t interfaceIndex, uint32_t updateFlags, HAL_Configuration_NetworkInterface* config ); + + static HRESULT LoadWirelessConfiguration( uint32_t interfaceIndex, HAL_Configuration_Wireless80211* wirelessConfig ); + + +private: + static void Status_callback(); + + static void Link_callback(); + + static void PostAddressChanged(void* arg); + + static void PostAvailabilityOn(void* arg); + + static void PostAvailabilityOff(void* arg); + + //LWIP_DRIVER_INTERFACE_DATA* m_interfaces; +}; + +// +// SOCKET driver +///////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // _SIMPLELINK_SOCKETS_H_ 1 + diff --git a/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp b/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp new file mode 100644 index 0000000000..2105865889 --- /dev/null +++ b/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp @@ -0,0 +1,165 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include + +#define NATIVE_PROFILE_PAL_NETWORK() + +HRESULT HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + uint16_t configOptions; + uint16_t ipLen = sizeof(SlNetCfgIpV4Args_t); + SlNetCfgIpV4Args_t ipV4 = {0}; + + if(config->StartupAddressMode == AddressMode_DHCP) + { + // if this is on DHCP we need to load whatever we have on top of the stored configuration +#if LWIP_IPV6 + { + // FIXME IPV6 + // config->IPv6Address = networkInterface->ip_addr.u_addr.ip6.addr; + // config->IPv6NetMask = networkInterface->netmask.u_addr.ip6.addr; + // config->IPv6GatewayAddress = networkInterface->gw.u_addr.ip6.addr; + } +#else + if (sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE, &configOptions, &ipLen, (uint8_t *)&ipV4) >= 0) + { + config->IPv4Address = sl_Ntohl(ipV4.Ip); + config->IPv4NetMask = sl_Ntohl(ipV4.IpMask); + config->IPv4GatewayAddress = sl_Ntohl(ipV4.IpGateway); + config->IPv4DNSAddress1 = sl_Ntohl(ipV4.IpDnsServer); + config->IPv4DNSAddress2 = 0; + } + else + { + config->IPv4Address = 0; + config->IPv4NetMask = 0; + config->IPv4GatewayAddress = 0; + config->IPv4DNSAddress1 = 0; + config->IPv4DNSAddress2 = 0; + } +#endif + } + + return S_OK; +} + +HRESULT HAL_SOCK_CONFIGURATION_UpdateAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex, uint32_t updateFlags) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + uint16_t configOptions; + uint16_t ipLen = sizeof(SlNetCfgIpV4Args_t); + SlNetCfgIpV4Args_t ipV4 = {0}; + + bool enableDHCP = (config->StartupAddressMode == AddressMode_DHCP); + + if (sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE, &configOptions, &ipLen, (uint8_t *)&ipV4) >= 0) + { + // when using DHCP do not use the static settings + if(0 != (updateFlags & UpdateOperation_Dns)) + { + // FIXME IPV6 + if(config->AutomaticDNS == 0) + { + // user defined DNS addresses + if(config->IPv4DNSAddress1 != 0) + { + ipV4.IpDnsServer = sl_Htonl(config->IPv4DNSAddress1); + } + + // this interface doesn't have a secondary DNS + + // update configuration + if(sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_STATIC, sizeof(SlNetCfgIpV4Args_t), (uint8_t*)&ipV4) < 0) + { + return CLR_E_FAIL; + } + } + } + + if(0 != (updateFlags & UpdateOperation_Dhcp)) + { + if(enableDHCP) + { + // need to start DHCP + if(sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_DHCP ,0 ,0 ) < 0) + { + return CLR_E_FAIL; + } + } + else + { + // we should be polite and let the DHCP server that we are now using a static IP + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_RELEASE_IP_SET, 0, 0); + + ipV4.Ip = sl_Htonl(config->IPv4Address); + ipV4.IpMask = sl_Htonl(config->IPv4NetMask); + ipV4.IpGateway = sl_Htonl(config->IPv4GatewayAddress); + ipV4.IpDnsServer = sl_Htonl(config->IPv4DNSAddress1); + + if(sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_STATIC, sizeof(SlNetCfgIpV4Args_t), (uint8_t*)&ipV4) < 0) + { + return CLR_E_FAIL; + } + + } + } + + if(enableDHCP) + { + if(0 != (updateFlags & UpdateOperation_DhcpRelease)) + { + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_RELEASE_IP_SET, 0, 0); + } + else if(0 != (updateFlags & UpdateOperation_DhcpRenew)) + { + //dhcp_renew(networkInterface); + } + else if(0 != (updateFlags & (UpdateOperation_DhcpRelease | UpdateOperation_DhcpRenew)) ) + { + return CLR_E_INVALID_PARAMETER; + } + } + + if(0 != (updateFlags & UpdateOperation_Mac)) + { + uint8_t macAddress[SL_MAC_ADDR_LEN]; + + memcpy(macAddress, config->MacAddress, SL_MAC_ADDR_LEN); + + if(sl_NetCfgSet(SL_NETCFG_MAC_ADDRESS_SET, 1, SL_MAC_ADDR_LEN, (uint8_t*)macAddress) < 0) + { + return CLR_E_FAIL; + } + } + } + + // all changes require SL reinit + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + + return S_OK; +} + +void HAL_SOCK_EventsSet( uint32_t events ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + ASSERT( (events == SOCKET_EVENT_FLAG_SOCKET) || (events == SOCKET_EVENT_FLAG_SOCKETS_READY)); + + Events_Set( SYSTEM_EVENT_FLAG_SOCKET ); +} + +void * HAL_SOCK_GlobalLockContext() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return NULL; +} diff --git a/targets/TI-SimpleLink/common/sockets_simplelink.cpp b/targets/TI-SimpleLink/common/sockets_simplelink.cpp new file mode 100644 index 0000000000..6539c85077 --- /dev/null +++ b/targets/TI-SimpleLink/common/sockets_simplelink.cpp @@ -0,0 +1,657 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//#include "sockets_simplelink.h" +#include + +#include +#include +#include + +//--// + +// this is to store the return value of the calls to sockets APIs +static int socketErrorCode = 0; + +static int MARSHAL_SOCK_FDSET_TO_SL_SDSET(SOCK_fd_set* sf, SlNetSock_SdSet_t* f) +{ + if(f != NULL && sf != NULL) + { + SlNetSock_sdsClrAll(f); + + for(unsigned int i=0; i < sf->fd_count; i++) + { + SlNetSock_sdsSet(sf->fd_array[i], f); + } + + return sf->fd_count; + } + + return 0; +} + +static void MARSHAL_SL_SDSET_TO_SOCK_FDSET(SOCK_fd_set* sf, SlNetSock_SdSet_t* f) +{ + if(sf != NULL && f != NULL) + { + int cnt = sf->fd_count; + sf->fd_count = 0; + + for(int i=0; ifd_array[i], f)) + { + sf->fd_array[sf->fd_count] = sf->fd_array[i]; + sf->fd_count++; + } + } + } +} + +SOCK_SOCKET SOCK_socket( int family, int type, int protocol ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_create(family, type, protocol, 0, 0); + + return socketErrorCode; +} + +int SOCK_bind( SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int addressLen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_bind( socket, (const SlNetSock_Addr_t*)address, addressLen ); + + return socketErrorCode; +} + +int SOCK_connect(SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int addressLen) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_connect(socket, (const SlNetSock_Addr_t*)address, addressLen); + + return socketErrorCode; +} + +int SOCK_send(SOCK_SOCKET socket, const char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_send(socket, buf, len, flags); + + return socketErrorCode; +} + +int SOCK_recv(SOCK_SOCKET socket, char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_COM(); + + // check for SOCKET_READ_PEEK_OPTION because Simple Link doesn't support this flag + if(flags == SOCKET_READ_PEEK_OPTION) + { + socketErrorCode = SLNETERR_BSD_EINVAL; + } + else + { + socketErrorCode = SlNetSock_recv(socket, buf, len, flags); + } + + return socketErrorCode; +} + +int SOCK_close(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_close(socket); + + return socketErrorCode; +} + +int SOCK_listen( SOCK_SOCKET socket, int backlog ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_listen( socket, backlog ); + + return socketErrorCode; +} + +SOCK_SOCKET SOCK_accept( SOCK_SOCKET socket, struct SOCK_sockaddr* address, int* addressLen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_accept( socket, (SlNetSock_Addr_t*)address, (SlNetSocklen_t*)addressLen ); + + return socketErrorCode; +} + +int SOCK_shutdown( SOCK_SOCKET socket, int how ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_shutdown( socket, how ); + + return socketErrorCode; +} + +int SOCK_getaddrinfo( const char* nodename, char* servname, const struct SOCK_addrinfo* hints, struct SOCK_addrinfo** res ) +{ + NATIVE_PROFILE_PAL_COM(); + + SOCK_addrinfo *ai; + SOCK_sockaddr_in *sa = NULL; + int total_size = sizeof(SOCK_addrinfo) + sizeof(SOCK_sockaddr_in); + struct SlNetUtil_addrInfo_t* addrInfo = NULL; + + if(res == NULL) return SOCK_SOCKET_ERROR; + + *res = NULL; + + // if the nodename == "" then return the IP address of this device + if(nodename[0] == 0 && servname == NULL) + { + uint16_t configOptions; + uint16_t ipLen = sizeof(SlNetCfgIpV4Args_t); + SlNetCfgIpV4Args_t ipV4 = {0}; + + if (sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE, &configOptions, &ipLen, (uint8_t *)&ipV4) >= 0) + { + ai = (SOCK_addrinfo*)platform_malloc(total_size); + + if (ai != NULL) + { + memset(ai, 0, total_size); + sa = (SOCK_sockaddr_in*)((uint8_t*)ai + sizeof(SOCK_addrinfo)); + + /* set up sockaddr */ + #if LWIP_IPV6 + // TODO + //sa->sin_addr.S_un.S_addr = networkInterface->ip_addr.u_addr.ip4.addr; + #else + sa->sin_addr.S_un.S_addr = sl_Ntohl(ipV4.Ip); + #endif + + sa->sin_family = SL_AF_INET; + sa->sin_port = 0; + + // set up addrinfo + ai->ai_family = SL_AF_INET; + if (hints != NULL) + { + // copy socktype & protocol from hints if specified + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + } + + ai->ai_addrlen = sizeof(SOCK_sockaddr_in); + ai->ai_addr = (SOCK_sockaddr*)sa; + + *res = ai; + + return 0; + } + } + } + else + { + int err = SlNetUtil_getAddrInfo(0, nodename, servname, (SlNetUtil_addrInfo_t*)hints, &addrInfo ); + socketErrorCode = err; + + if(err >= 0) + { + /// + /// Marshal addrinfo data + /// + SlNetSock_AddrIn_t* sockaddr_in; + + ai = (SOCK_addrinfo*)platform_malloc(total_size); + if (ai == NULL) + { + SlNetUtil_freeAddrInfo(addrInfo); + } + else + { + memset(ai, 0, total_size); + + sockaddr_in = (SlNetSock_AddrIn_t*)addrInfo->ai_addr; + + sa = (SOCK_sockaddr_in*)((uint8_t*)ai + sizeof(SOCK_addrinfo)); + /* set up sockaddr */ + sa->sin_addr.S_un.S_addr = sockaddr_in->sin_addr.s_addr; + sa->sin_family = sockaddr_in->sin_family; + sa->sin_port = sockaddr_in->sin_port; + + /* set up addrinfo */ + ai->ai_family = addrInfo->ai_family; + if (hints != NULL) + { + /* copy socktype & protocol from hints if specified */ + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + } + + ai->ai_addrlen = sizeof(SOCK_sockaddr_in); + ai->ai_addr = (SOCK_sockaddr*)sa; + + *res = ai; + + // free marshalled addrinfo + SlNetUtil_freeAddrInfo(addrInfo); + + return 0; + } + } + } + + return SOCK_SOCKET_ERROR; +} + +void SOCK_freeaddrinfo( struct SOCK_addrinfo* ai ) +{ + NATIVE_PROFILE_PAL_COM(); + SlNetUtil_freeAddrInfo( (SlNetUtil_addrInfo_t*)ai ); +} + +int SOCK_ioctl( SOCK_SOCKET socket, int cmd, int* data ) +{ + NATIVE_PROFILE_PAL_COM(); + + if(cmd == SOCK_FIONBIO) + { + // adjust setting for socket blocking/non-blocking + SlNetSock_Nonblocking_t enableOption; + enableOption.nonBlockingEnabled = *data; + + socketErrorCode = SlNetSock_setOpt(socket, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_BLOCKING, (uint8_t *)&enableOption, sizeof(enableOption)); + + return socketErrorCode; + } + else if(cmd == SOCK_IPPROTO_TCP) + { + // TODO + HAL_AssertEx(); + } + else if(cmd == SOCK_SOL_SOCKET) + { + // TODO + HAL_AssertEx(); + } + + // unknown command + return -1; +} + +int SOCK_getlasterror() +{ + NATIVE_PROFILE_PAL_COM(); + // FIXME + return 0;//SlNetSock_getlasterror(); +} + +int SOCK_getsocklasterror(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_COM(); + + int errorNo; + + if(socketErrorCode >= 0) + { + return socketErrorCode; + } + + /* This switch case block is necessary for translating the SlNetSock error codes + * to BSD ones. The #ifdef in each case are made in order to reduce code footprint: + * This cases are compiled if and only if there's a discrepancy between the BSD error + * number and the error code returned by the SlNetSock layer. + */ + switch(socketErrorCode) + { +#if EBADF != SLNETERR_BSD_EBADF + case SLNETERR_BSD_EBADF: + errorNo = EBADF; + break; +#endif +#if ENFILE != SLNETERR_BSD_ENSOCK + case SLNETERR_BSD_ENSOCK: + errorNo = ENFILE; + break; +#endif +#if EAGAIN != SLNETERR_BSD_EAGAIN + case SLNETERR_BSD_EAGAIN: + errorNo = EAGAIN; + break; +#endif +#if ENOMEM != SLNETERR_BSD_ENOMEM + case SLNETERR_BSD_ENOMEM: + errorNo = ENOMEM; + break; +#endif +#if EACCES != SLNETERR_BSD_EACCES + case SLNETERR_BSD_EACCES: + errorNo = EACCES; + break; +#endif +#if EFAULT != SLNETERR_BSD_EFAULT + case SLNETERR_BSD_EFAULT: + errorNo = EFAULT; + break; +#endif +#if EINVAL != SLNETERR_BSD_EINVAL + case SLNETERR_BSD_EINVAL: + errorNo = EINVAL; + break; +#endif +#if EDESTADDRREQ != SLNETERR_BSD_EDESTADDRREQ + case SLNETERR_BSD_EDESTADDRREQ: + errorNo = EDESTADDRREQ; + break; +#endif +#if EPROTOTYPE != SLNETERR_BSD_EPROTOTYPE + case SLNETERR_BSD_EPROTOTYPE: + errorNo = EPROTOTYPE; + break; +#endif +#if ENOPROTOOPT != SLNETERR_BSD_ENOPROTOOPT + case SLNETERR_BSD_ENOPROTOOPT: + errorNo = ENOPROTOOPT; + break; +#endif +#if EPROTONOSUPPORT != SLNETERR_BSD_EPROTONOSUPPORT + case SLNETERR_BSD_EPROTONOSUPPORT: + errorNo = EPROTONOSUPPORT; + break; +#endif +#if EOPNOTSUPP != SLNETERR_BSD_EOPNOTSUPP + case SLNETERR_BSD_EOPNOTSUPP: + errorNo = EOPNOTSUPP; + break; +#endif +#if EAFNOSUPPORT != SLNETERR_BSD_EAFNOSUPPORT + case SLNETERR_BSD_EAFNOSUPPORT: + errorNo = EAFNOSUPPORT; + break; +#endif +#if EADDRINUSE != SLNETERR_BSD_EADDRINUSE + case SLNETERR_BSD_EADDRINUSE: + errorNo = EADDRINUSE; + break; +#endif +#if EADDRNOTAVAIL != SLNETERR_BSD_EADDRNOTAVAIL + case SLNETERR_BSD_EADDRNOTAVAIL: + errorNo = EADDRNOTAVAIL; + break; +#endif +#if ENETDOWN != SLNETERR_BSD_ENETDOWN + case SLNETERR_BSD_ENETDOWN: + errorNo = ENETDOWN; + break; +#endif +#if ENETUNREACH != SLNETERR_BSD_ENETUNREACH + case SLNETERR_BSD_ENETUNREACH: + errorNo = ENETUNREACH; + break; +#endif +#if ENOBUFS != SLNETERR_BSD_ENOBUFS + case SLNETERR_BSD_ENOBUFS: + errorNo = ENOBUFS; + break; +#endif +#if EISCONN != SLNETERR_BSD_EISCONN + case SLNETERR_BSD_EISCONN: + errorNo = EISCONN; + break; +#endif +#if ENOTCONN != SLNETERR_BSD_ENOTCONN + case SLNETERR_BSD_ENOTCONN: + errorNo = ENOTCONN; + break; +#endif +#if ETIMEDOUT != SLNETERR_BSD_ETIMEDOUT + case SLNETERR_BSD_ETIMEDOUT: + errorNo = ETIMEDOUT; + break; +#endif +#if ECONNREFUSED != SLNETERR_BSD_ECONNREFUSED + case SLNETERR_BSD_ECONNREFUSED: + errorNo = ECONNREFUSED; + break; +#endif + case SL_ERROR_BSD_EALREADY: + errorNo = SOCK_EWOULDBLOCK; + break; + + /* The cases below are propriety driver errors, which can + * be returned by the SimpleLink Driver, in various cases of failure. + * Each is mapped to the corresponding BSD error. + */ + case SLNETERR_POOL_IS_EMPTY: + case SLNETERR_RET_CODE_NO_FREE_SPACE: + case SLNETERR_RET_CODE_MUTEX_CREATION_FAILED: + case SLNETERR_RET_CODE_MALLOC_ERROR: + errorNo = ENOMEM; + break; + case SLNETERR_RET_CODE_INVALID_INPUT: + case SLNETERR_EZEROLEN: + case SLNETERR_ESMALLBUF: + case SLNETERR_INVALPARAM: + errorNo = EINVAL; + break; + case SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN: + errorNo = EOPNOTSUPP; + break; + case SLNETERR_RET_CODE_COULDNT_FIND_RESOURCE: + errorNo = EBADF; + break; + default: + /* Do nothing .. + * If no case is true, that means that the BSD error + * code and the code returned by the NWP are either identical, + * or no propriety error has occurred. + */ + break; + } + + return errorNo; +} + +int SOCK_select( int nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* exceptfds, const struct SOCK_timeval* timeout ) +{ + NATIVE_PROFILE_PAL_COM(); + + int ret = 0; + + // TODO + // If the network goes down then we should alert any pending socket actions + if(exceptfds != NULL && exceptfds->fd_count > 0) + { + if(SlNetIf_getConnectionStatus(0) == SLNETIF_STATUS_DISCONNECTED) + { + if(readfds != NULL) + { + readfds->fd_count = 0; + } + if(writefds != NULL) + { + writefds->fd_count = 0; + } + + socketErrorCode = ENETDOWN; + + return exceptfds->fd_count; + } + } + + // developer note: + // The original code, being lwIP based, uses the convention that 0 is infinite timeout + // Because SimpleLink infinite timeout is negative or NULL we need to translate it. + SlNetSock_Timeval_t timeoutCopy; + if(timeout->tv_sec == 0 && timeout->tv_usec == 0) + { + timeoutCopy.tv_sec = -1; + timeoutCopy.tv_usec = 0; + } + + ret = SlNetSock_select( SLNETSOCK_MAX_CONCURRENT_SOCKETS, (SlNetSock_SdSet_t*)readfds, (SlNetSock_SdSet_t*)writefds, (SlNetSock_SdSet_t*)exceptfds, &timeoutCopy ); + socketErrorCode = ret; + + // developer notes: + // SlNetSock_select() call doesn't touch the exception SDSET. + // In SimpleLink socket exceptions are handled differently. + // We need to clear that one here because the way the caller is implemented it will think there is an exception + // because it has forced it. + SlNetSock_sdsClrAll((SlNetSock_SdSet_t*)exceptfds); + + return ret; +} + +int SOCK_setsockopt( SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_setOpt( socket, level, optname, (void *) optval, optlen ); + + return socketErrorCode; +} + +int SOCK_getsockopt( SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_getOpt( socket, level, optname, (void *)optval, (SlNetSocklen_t *)optlen ); + + return socketErrorCode; +} + +int SOCK_getpeername( SOCK_SOCKET socket, struct SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_getPeerName( socket, (SlNetSock_Addr_t*)name, (SlNetSocklen_t*)namelen ); + + return socketErrorCode; +} + +int SOCK_getsockname( SOCK_SOCKET socket, struct SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_getSockName( socket, (SlNetSock_Addr_t*)name, (SlNetSocklen_t*)namelen ); + + return socketErrorCode; +} + +int SOCK_recvfrom( SOCK_SOCKET s, char* buf, int len, int flags, struct SOCK_sockaddr* from, int* fromlen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_recvFrom( s, buf, len, flags, (SlNetSock_Addr_t*)from, (SlSocklen_t*)fromlen ); + + return socketErrorCode; +} + +int SOCK_sendto( SOCK_SOCKET s, const char* buf, int len, int flags, const struct SOCK_sockaddr* to, int tolen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_sendTo( s, buf, len, flags, (SlNetSock_Addr_t*)to, (SlSocklen_t)tolen ); + + return socketErrorCode; +} + +bool Network_Initialize() +{ + NATIVE_PROFILE_PAL_COM(); + + // network initialization is taken care of by SimpleLink + return true; +} + +bool Network_Uninitialize() +{ + NATIVE_PROFILE_PAL_COM(); + + // not required SimpleLink + return true; +} + +void SOCKETS_CloseConnections() +{ + NATIVE_PROFILE_PAL_COM(); + // FIXME + //Sockets_SimpleLink_Driver::CloseConnections(FALSE); +} + +HRESULT SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(config, interfaceIndex); +} + +HRESULT SOCK_CONFIGURATION_UpdateAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex, uint32_t updateFlags) +{ + NATIVE_PROFILE_PAL_COM(); + HRESULT hr = S_OK; + bool success = FALSE; + + const uint32_t c_reInitFlag = UpdateOperation_Dhcp | + UpdateOperation_DhcpRenew | + UpdateOperation_Mac; + + const uint32_t c_uninitFlag = c_reInitFlag | UpdateOperation_DhcpRelease; + + if(0 != (updateFlags & c_uninitFlag)) + { + success = SOCKETS_DbgUninitialize(COM_SOCKET_DBG); + } + + hr = HAL_SOCK_CONFIGURATION_UpdateAdapterConfiguration(config, interfaceIndex, updateFlags); + + if(!SUCCEEDED(hr)) + { + return S_FALSE; + } + + if(0 != (updateFlags & c_reInitFlag)) + { + if(success) SOCKETS_DbgInitialize(COM_SOCKET_DBG); + } + + return hr; +} + +HRESULT SOCK_CONFIGURATION_LoadConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_COM(); + HRESULT hr = S_OK; + + // load current DCHP settings + hr = SOCK_CONFIGURATION_LoadAdapterConfiguration(config, interfaceIndex); + + return hr; +} + +#define SOCKET_SHUTDOWN_READ 0 +#define SOCKET_SHUTDOWN_WRITE 1 +#define SOCKET_SHUTDOWN_READ_WRITE 2 + +#define ISSET_SOCKET_FLAG(x,y) ((y) == ((y) & (x).m_flags)) +#define SET_SOCKET_FLAG(x,y) (x).m_flags |= (y) +#define CLEAR_SOCKET_FLAG(x,y) (x).m_flags &= ~(y) + +bool SOCKETS_DbgInitialize( int ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + + return true; +} + +bool SOCKETS_DbgUninitialize( int ComPortNum ) +{ + return true; +} diff --git a/targets/TI-SimpleLink/common/sockets_simplelink.h b/targets/TI-SimpleLink/common/sockets_simplelink.h new file mode 100644 index 0000000000..6a738fcf30 --- /dev/null +++ b/targets/TI-SimpleLink/common/sockets_simplelink.h @@ -0,0 +1,188 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SOCKETS_H_ +#define _SOCKETS_H_ 1 + +//--// + +#include +#include + +//--// + +#define SOCKET_CHECK_ENTER() \ + int32_t ret=0 \ + +#define SOCKET_CLEANUP() \ + goto RETURN_OK; \ + SOCKET_CHECK_RETURN: \ + +#define SOCKET_CHECK_EXIT_CLEANUP() \ + RETURN_OK: \ + ASSERT(ret != SOCK_SOCKET_ERROR); \ + return ret; \ + +#define SOCKET_CHECK_EXIT() \ + SOCKET_CLEANUP() \ + RETURN_OK: \ + ASSERT(ret != SOCK_SOCKET_ERROR); \ + return ret; \ + +#define SOCKET_CHECK_EXIT_bool() \ + SOCKET_CLEANUP() \ + RETURN_OK: \ + return ret != SOCK_SOCKET_ERROR; \ + +#define SOCKET_CHECK_EXIT_bool_CLEANUP()\ + RETURN_OK: \ + return ret != SOCK_SOCKET_ERROR; \ + +#define SOCKET_CHECK_RESULT(x) \ + if((ret = (x)) == SOCK_SOCKET_ERROR)\ + { \ + goto SOCKET_CHECK_RETURN; \ + } \ + +#define SOCKET_CHECK_bool(x) \ + if(!(x)) \ + { \ + ret = SOCK_SOCKET_ERROR; \ + goto SOCKET_CHECK_RETURN; \ + } \ + +#define SOCKET_CHECK_EXIT_NORETURN() \ + RETURN_OK: \ + +struct Sockets_SimpleLink_Driver +{ + static SOCK_SOCKET Socket( int32_t family, int32_t type, int32_t protocol, bool fDebug ); + static int Connect(SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int32_t addressLen) ; + static int Send(SOCK_SOCKET socket, const char* buf, int32_t len, int32_t flags) ; + static int Recv(SOCK_SOCKET socket, char* buf, int32_t len, int32_t flags); + static int Close(SOCK_SOCKET socket); + static int Listen( SOCK_SOCKET socket, int32_t backlog ); + static SOCK_SOCKET Accept( SOCK_SOCKET socket, struct SOCK_sockaddr* address, int* addressLen, bool fDebug ); + static int Select( int32_t nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* except, const struct SOCK_timeval* timeout ); + static int RecvFrom( SOCK_SOCKET s, char* buf, int32_t len, int32_t flags, struct SOCK_sockaddr* from, int* fromlen ); + static int SendTo( SOCK_SOCKET s, const char* buf, int32_t len, int32_t flags, const struct SOCK_sockaddr* to, int32_t tolen ); + static int Shutdown( SOCK_SOCKET s, int32_t how); + + static bool Initialize(); + static bool Uninitialize(); + static void CloseConnections(bool fCloseDbg); + + static void SaveConfig(int32_t index, HAL_Configuration_NetworkInterface *cfg); + + // Debugger methods ( socket_debugger.cpp ) + static void Debugger_Initialize(); + static void Debugger_Uninitialize(); + static void Debugger_Abort(); + + static bool InitializeDbgListener( int ComPortNum ); + static bool UninitializeDbgListener( int ComPortNum ); + static int Write( int ComPortNum, const char* Data, size_t size ); + static int Read ( int ComPortNum, char* Data, size_t size ); + static bool UpgradeToSsl( int ComPortNum, const int8_t* pCACert, uint32_t caCertLen, const int8_t* pDeviceCert, uint32_t deviceCertLen, const char* szTargetHost ); + static bool IsUsingSsl( int ComPortNum ); + + void* GetSocketSslData(SOCK_SOCKET socket) + { + int32_t tmp; + + return GetSocketSslData(socket, tmp); + } + + void* GetSocketSslData(SOCK_SOCKET socket, int32_t &sockIndex) + { + GLOBAL_LOCK_SOCKETS(x); + + for(int i=m_cntSockets-1; i>=0; i--) + { + if(socket == m_socketHandles[i].m_socket) + { + sockIndex = i; + return m_socketHandles[i].m_sslData; + } + } + + return NULL; + } + + void SetSocketSslData(SOCK_SOCKET socket, void* sslObj) + { + GLOBAL_LOCK_SOCKETS(x); + + for(int i=m_cntSockets-1; i>=0; i--) + { + if(socket == m_socketHandles[i].m_socket) + { + m_socketHandles[i].m_sslData = sslObj; + + break; + } + } + } + + // required by SSL + static void UnregisterSocket( int index ); + + + static void ClearStatusBitsForSocket(SOCK_SOCKET sock, bool fWrite); + static bool InitializeMulticastDiscovery(); + +private: + + static void RegisterSocket( SOCK_SOCKET sock, bool selectable, bool fDebug ); + + struct SocketRegisterMap + { + SOCK_SOCKET m_socket; + uint32_t m_flags; + void* m_sslData; + + static const uint32_t c_SelectableSocket = 0x0001; + static const uint32_t c_DebugSocket = 0x0002; + static const uint32_t c_CloseSocket = 0x0004; + }; + + enum DebuggerState + { + DbgSock_Uninitialized = 0, + DbgSock_Listening = 1, + DbgSock_Connected = 2, + } m_stateDebugSocket; + + bool m_usingSSL; + + static void MulticastDiscoveryRespond(void* arg); + static void MulticastDiscoverySchedule(); + + static void CloseDebuggerSocket(); + static void OnDebuggerTimeout(void* arg); + + static HAL_COMPLETION s_DebuggerTimeoutCompletion; + + SOCK_SOCKET m_SocketDebugListener; + SOCK_SOCKET m_SocketDebugStream; + SOCK_SOCKET m_multicastSocket; + + bool m_fShuttingDown; + + int32_t m_cntSockets; + struct SocketRegisterMap m_socketHandles[SOCKETS_MAX_COUNT]; + + static bool s_initialized; + static bool s_initializedDbg; + static const int32_t c_WellKnownDebugPort = DEBUG_SOCKET_PORT; + static bool s_wirelessInitialized; + static bool s_discoveryInitialized; +}; + +extern Sockets_SimpleLink_Driver g_Sockets_SimpleLink_Driver; + +#endif //_SOCKETS_H_ + diff --git a/targets/TI-SimpleLink/common/ssl_simplelink.cpp b/targets/TI-SimpleLink/common/ssl_simplelink.cpp new file mode 100644 index 0000000000..168ffb43ad --- /dev/null +++ b/targets/TI-SimpleLink/common/ssl_simplelink.cpp @@ -0,0 +1,120 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nanoHal.h" + +//--// + +extern "C" +{ +void ssl_rand_seed(const void *seed, int length) +{ + (void)seed; + (void)length; +} +} + +__nfweak bool SSL_Initialize() +{ + NATIVE_PROFILE_PAL_COM(); + return FALSE; +} + +__nfweak bool SSL_Uninitialize() +{ + NATIVE_PROFILE_PAL_COM(); + return TRUE; +} + +__nfweak bool SSL_ServerInit( int sslMode, int sslVerify, const char* certificate, int certLength, const char* certPassword, int& sslContextHandle ) +{ + (void)sslMode; (void)sslVerify; (void)certificate; (void)certLength; (void)certPassword; (void)sslContextHandle; + NATIVE_PROFILE_PAL_COM(); + return TRUE; +} + +__nfweak bool SSL_ClientInit( int sslMode, int sslVerify, const char* certificate, int certLength, const char* certPassword, int& sslContextHandle ) +{ + (void)sslMode; (void)sslVerify; (void)certificate; (void)certLength; (void)certPassword; (void)sslContextHandle; + NATIVE_PROFILE_PAL_COM(); + return TRUE; +} + +__nfweak bool SSL_AddCertificateAuthority( int sslContextHandle, const char* certificate, int certLength, const char* certPassword ) +{ + (void)sslContextHandle; (void)certificate; (void)certLength; (void)certPassword; + NATIVE_PROFILE_PAL_COM(); + return TRUE; +} + +__nfweak bool SSL_ExitContext( int sslContextHandle ) +{ + (void)sslContextHandle; + NATIVE_PROFILE_PAL_COM(); + return TRUE; +} + +__nfweak int SSL_Accept( SOCK_SOCKET socket, int sslContextHandle ) +{ + (void)socket; (void)sslContextHandle; + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak int SSL_Connect( SOCK_SOCKET socket, const char* szTargetHost, int sslContextHandle ) +{ + (void)socket; (void)szTargetHost; (void)sslContextHandle; + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak int SSL_Write( SOCK_SOCKET socket, const char* Data, size_t size ) +{ + (void)socket; (void)Data; (void)size; + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak int SSL_Read( SOCK_SOCKET socket, char* Data, size_t size ) +{ + (void)socket; (void)Data; (void)size; + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak int SSL_CloseSocket( SOCK_SOCKET socket ) +{ + (void)socket; + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak void SSL_GetTime(DATE_TIME_INFO* pdt) +{ + (void)pdt; + NATIVE_PROFILE_PAL_COM(); +} + +__nfweak void SSL_RegisterTimeCallback(SSL_DATE_TIME_FUNC pfn) +{ + (void)pfn; + NATIVE_PROFILE_PAL_COM(); +} + +__nfweak bool SSL_ParseCertificate( const char* certificate, size_t certLength, const char* password, X509CertData* certData ) +{ + (void)certificate; (void)certLength; (void)password; (void)certData; + + NATIVE_PROFILE_PAL_COM(); + return TRUE; +} + +__nfweak int SSL_DataAvailable( SOCK_SOCKET socket ) +{ + (void)socket; + NATIVE_PROFILE_PAL_COM(); + return 0; +} From 33aafe25d904bb07f87834eeb0a7ce4e85d0aedc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Mar 2019 18:37:14 +0000 Subject: [PATCH 63/90] Increase CLR flash region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c | 4 ++-- .../TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index 0e4f82a874..64b0885fa7 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -11,8 +11,8 @@ const BlockRange BlockRange1[] = { // the 1st block is reserved for the flash header // so we don't take it into account for the map - { BlockRange_BLOCKTYPE_CODE , 0 , 117 }, // 0x01000800 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT , 118, 510 }, // 0x0103B000 deployment + { BlockRange_BLOCKTYPE_CODE , 0 , 118 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 119, 510 }, // 0x0103B800 deployment }; const BlockRegionInfo BlockRegions[] = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index f207810849..0971256dbc 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03B000 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03B800 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } From d3738fb5d1ae1d125b8d7383cc9edb95f5d7bd67 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Mar 2019 18:39:53 +0000 Subject: [PATCH 64/90] Add define for chip family in CMake toolchain MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- CMake/toolchain.TI_SimpleLink.GCC.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMake/toolchain.TI_SimpleLink.GCC.cmake b/CMake/toolchain.TI_SimpleLink.GCC.cmake index 1ff59ecb6f..c1b3e10a8f 100644 --- a/CMake/toolchain.TI_SimpleLink.GCC.cmake +++ b/CMake/toolchain.TI_SimpleLink.GCC.cmake @@ -125,7 +125,7 @@ function(NF_SET_COMPILER_DEFINITIONS TARGET) target_compile_definitions(${TARGET} PUBLIC "-DPLATFORM_ARM ") # definitions required for SimpleLink CC32xx SDK - target_compile_definitions(${TARGET} PUBLIC -Dgcc -DPTLS_TLS_INDEX=0 -DBOARD_DISPLAY_USE_UART_ANSI=0 -DBOARD_DISPLAY_USE_LCD=0 -DconfigNUM_THREAD_LOCAL_STORAGE_POINTERS=1 -DSL_PLATFORM_MULTI_THREADED) + target_compile_definitions(${TARGET} PUBLIC -Dgcc -DPTLS_TLS_INDEX=0 -DCC32XX -DBOARD_DISPLAY_USE_UART_ANSI=0 -DBOARD_DISPLAY_USE_LCD=0 -DconfigNUM_THREAD_LOCAL_STORAGE_POINTERS=1 -DSL_PLATFORM_MULTI_THREADED) # build types that have debugging capabilities AND are NOT RTM have to have the define 'NANOCLR_ENABLE_SOURCELEVELDEBUGGING' if((NOT NF_BUILD_RTM) OR NF_FEATURE_DEBUGGER) From ab4e19a235b0a7acfe0cb267f44421aaf5c72c24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Thu, 21 Mar 2019 18:41:29 +0000 Subject: [PATCH 65/90] Add implementation of SNTP for SimpleLink MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- CMakeLists.txt | 4 +- .../Networking.Sntp/nf_networking_sntp.h | 8 +- .../Include/targetSimpleLinkCC32xx_Sntp.h | 153 ++++++++ .../TI_CC3220SF_LAUNCHXL/target_sntp_opts.h | 24 ++ targets/TI-SimpleLink/nanoCLR/CMakeLists.txt | 5 + .../nanoCLR/targetSimpleLinkCC32xx_Sntp.c | 355 ++++++++++++++++++ .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 12 +- .../nanoCLR/target_platform.h.in | 5 +- 8 files changed, 556 insertions(+), 10 deletions(-) create mode 100644 targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Sntp.h create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_sntp_opts.h create mode 100644 targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Sntp.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 393fdf56fb..b00339a454 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -561,9 +561,9 @@ endif() if(API_System.Net) # manage inclusion of SNTP if(NF_NETWORKING_SNTP) - set(API_nanoFramework.Networking.Sntp ON CACHE INTERNAL "enable API_nanoFramework..Networking.Sntp") + set(API_nanoFramework.Networking.Sntp ON CACHE INTERNAL "enable API_nanoFramework.Networking.Sntp") else() - set(API_nanoFramework.Networking.Sntp OFF CACHE INTERNAL "disable API_nanoFramework..Networking.Sntp") + set(API_nanoFramework.Networking.Sntp OFF CACHE INTERNAL "disable API_nanoFramework.Networking.Sntp") endif() endif() diff --git a/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.h b/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.h index 90c307ba00..50db1aebcd 100644 --- a/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.h +++ b/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.h @@ -15,10 +15,12 @@ extern "C" { -#ifndef PLATFORM_ESP32 -#include -#else +#ifdef PLATFORM_ESP32 #include +#elif CC32XX +#include +#else +#include #endif } diff --git a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Sntp.h b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Sntp.h new file mode 100644 index 0000000000..29ee542538 --- /dev/null +++ b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Sntp.h @@ -0,0 +1,153 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_SNTP_H_ +#define _TARGET_SNTP_H_ 1 + +#include +#include +#include + +#include +#include + +// default SNTP server address +#ifndef SNTP_SERVER_DEFAULT_ADDRESS +#define SNTP_SERVER_DEFAULT_ADDRESS "0.pool.ntp.org" +#endif + +// Must wait at least 15 sec to retry NTP server (RFC 4330) +#ifndef SNTP_UPDATE_DELAY +#define SNTP_UPDATE_DELAY (15) +#endif + +// better have a startup delay because we can have DHCP enabled (default 30 seconds) +// value in seconds +#ifndef SNTP_STARTUP_DELAY +#define SNTP_STARTUP_DELAY (30) +#endif + +// retry timeout (15 minutes) +// value in seconds +#ifndef SNTP_RETRY_TIMEOUT +#define SNTP_RETRY_TIMEOUT (15 * 60) +#endif + +#define NTP_SERVERS 1 +#define NTP_SERVER_PORT 123 + +// Time to wait for reply from server (seconds) +#define NTP_REPLY_WAIT_TIME 5 + +#define TIME_BASEDIFF ((((uint32_t)70 * 365 + 17) * 24 * 3600)) +#define TIME_NTP_TO_LOCAL(t) ((t) - TIME_BASEDIFF) + +// SNTP Error Codes +// Failed to resolve Host address +#define SNTP_EGETHOSTBYNAMEFAIL (-100) + +// Input arguments are invalid +#define SNTP_EINVALIDARGS (-101) + +// Failed to create a socket +#define SNTP_ESOCKCREATEFAIL (-102) + +// The input socket address is not of AF_INET (IPv4) or AF_INET6 +// (IPv6) family type +#define SNTP_EINVALIDFAMILY (-103) + +// Failed to set receive timeout on socket +#define SNTP_ESOCKOPTFAIL (-104) + +// Failed to connect to the NTP server +#define SNTP_ECONNECTFAIL (-105) + +// Failed to send a time request to the NTP server +#define SNTP_ESENDFAIL (-106) + +// Failed to recieve the new time from the NTP server +#define SNTP_ERECVFAIL (-107) + +// NTP Server requests to reduce the update rate (RFC 5905 kiss code RATE) + +#define SNTP_ERATEBACKOFF (-108) + +// NTP Server invalid or server requests to end all communications (RFC +// 5905 kiss code DENY or RSTR) +#define SNTP_EFATALNORETRY (-109) + +// Server response with stratum == 0, with no kiss code +#define SNTP_EINVALIDRESP (-110) + +// KOD error code: rate exceeded, server requesting NTP client to back off +#define SNTP_KOD_RATE_STR "RATE" +#define SNTP_KOD_RATE_CODE 3 + +// KOD error code: access denied, server requests client to end all comm +#define SNTP_KOD_DENY_STR "DENY" +#define SNTP_KOD_DENY_CODE 2 + +// KOD error code: access denied, server requests client to end all comm +#define SNTP_KOD_RSTR_STR "RSTR" +#define SNTP_KOD_RSTR_CODE 1 + +// Size of KOD error codes +#define SNTP_KOD_ERROR_CODE_SIZE 4 + +// Use NTP version 4 +#define SNTP_VERSION 4 + +// Flag value for unsync'ed leap indicator field, signifying server error +#define SNTP_NOSYNC 3 + +// NTP mode defined in RFC 4330 +#define SNTP_MODE_CLIENT 3 + +// SNTP Header (as specified in RFC 4330) +typedef struct _SNTP_Header_t_ +{ + // + // 'flags' stores three values: + // + // - 2 bit Leap Indicator (LI) + // - 3 bit Version Number (VN) + // - 3 bit Mode. + + uint8_t flags; + uint8_t stratum; + uint8_t poll; + int8_t precision; + int32_t rootDelay; + uint32_t rootDispersion; + uint32_t referenceID; + + // NTP time stamps + uint32_t referenceTS[2]; + uint32_t originateTS[2]; + uint32_t receiveTS[2]; + uint32_t transmitTS[2]; +} SNTP_Header_t; + +struct sntp_server +{ + char* name; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +void sntp_init(void); +void sntp_stop(void); +bool sntp_enabled(void); +char* sntp_getservername(int index); +void sntp_setservername(int index, char* server); + +#ifdef __cplusplus +} +#endif + +#endif //_TARGET_SNTP_H_ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_sntp_opts.h b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_sntp_opts.h new file mode 100644 index 0000000000..849e2dd2cc --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_sntp_opts.h @@ -0,0 +1,24 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_SNTP_OPTS_H_ +#define _TARGET_SNTP_OPTS_H_ 1 + +#define SNTP_SERVER_DEFAULT_ADDRESS "0.pool.ntp.org" + +// update delay (default 1 hour) +// (value in seconds) +// Must wait at least 15 sec to retry NTP server (RFC 4330) +#define SNTP_UPDATE_DELAY (60 * 60) + +// better have a startup delay because we can have DHCP enabled (default 30 seconds) +// value in seconds +#define SNTP_STARTUP_DELAY 30 + +// retry timeout (15 minutes) +// value in seconds +#define SNTP_RETRY_TIMEOUT (15 * 60) + +#endif // _TARGET_SNTP_OPTS_H_ diff --git a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt index f8e474b643..cc03a038ed 100644 --- a/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt +++ b/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt @@ -27,6 +27,11 @@ list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/ta # list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Watchdog.c") # endif() +# append SNTP only if option is ON +if(NF_NETWORKING_SNTP) + list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetSimpleLinkCC32xx_Sntp.c") +endif() + # append target PAL source files list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Events.cpp") list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Time.cpp") diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Sntp.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Sntp.c new file mode 100644 index 0000000000..0b108dbdd0 --- /dev/null +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Sntp.c @@ -0,0 +1,355 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +// POSIX Header files +#include +#include +#include + +// RTOS header files +#include "FreeRTOS.h" +#include "task.h" + +#include +#include + + +static struct sntp_server SNTP_ServersList[NTP_SERVERS]; + +pthread_t sntpWorkingThread = (pthread_t)NULL; +void * SntpWorkingThread(void *arg0); + +void sntp_init(void) +{ + struct sched_param priorityParams; + pthread_attr_t threadAttributes; + int retc; + + if(sntpWorkingThread == NULL) + { + pthread_attr_init(&threadAttributes); + priorityParams.sched_priority = 1; + retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&threadAttributes, 2048); + if (retc != 0) + { + // failed to set attributes + while (1) {} + } + + retc = pthread_create(&sntpWorkingThread, &threadAttributes, SntpWorkingThread, NULL); + if(retc != 0) + { + // pthread_create() failed + HAL_AssertEx(); + while(1) + { + ; + } + } + } +} + +void sntp_stop(void) +{ + pthread_cancel(sntpWorkingThread); + sntpWorkingThread = NULL; +} + +bool sntp_enabled(void) +{ + return (sntpWorkingThread != NULL)? true : false; +} + +char* sntp_getservername(int index) +{ + if(index < NTP_SERVERS) + { + return SNTP_ServersList[index].name; + } + + return NULL; +} + +void sntp_setservername(int index, char* server) +{ + if(index < NTP_SERVERS) + { + SNTP_ServersList[index].name = server; + } +} + +static int32_t getAddrByName(const char *name, uint32_t *addr, uint16_t *family) +{ + int32_t ifID; + uint16_t addrLen = 1; + + /* Query DNS for IPv4 address. */ + ifID = SlNetUtil_getHostByName(0, (char *)name, strlen(name), addr, &addrLen, SLNETSOCK_AF_INET); + + if(ifID < 0) + { + /* If call fails, try again for IPv6. */ + ifID = SlNetUtil_getHostByName(0, (char *)name, strlen(name), addr, &addrLen, SLNETSOCK_AF_INET6); + if(ifID < 0) + { + /* return an error */ + return -1; + } + else + { + *family = SLNETSOCK_AF_INET6; + } + } + else + { + *family = SLNETSOCK_AF_INET; + } + + /* Return the interface ID */ + return (ifID); +} + +static int32_t hasKissCode(char *str) +{ + if (strncmp((char *)SNTP_KOD_RATE_STR, str, SNTP_KOD_ERROR_CODE_SIZE) == 0) + { + return (SNTP_KOD_RATE_CODE); + } + else if (strncmp((char *)SNTP_KOD_DENY_STR, str, SNTP_KOD_ERROR_CODE_SIZE) == 0) + { + return (SNTP_KOD_DENY_CODE); + } + else if (strncmp((char *)SNTP_KOD_RSTR_STR, str, SNTP_KOD_ERROR_CODE_SIZE) == 0) + { + return (SNTP_KOD_RSTR_CODE); + } + else + { + return (0); + } +} + +static int32_t getTime(SlNetSock_Addr_t *server, uint16_t ifID, + SlNetSock_Timeval_t *timeout, uint64_t *ntpTimeStamp) +{ + SNTP_Header_t sntpPkt; + int32_t ret = 0; + int16_t sd = -1; + SlNetSocklen_t saLen; + uint32_t integrityCheck; + struct timespec tspec; + + if (server->sa_family == SLNETSOCK_AF_INET) + { + saLen = sizeof(SlNetSock_AddrIn_t); + } + else if (server->sa_family == SLNETSOCK_AF_INET6) + { + saLen = sizeof(SlNetSock_AddrIn6_t); + } + else + { + return (SNTP_EINVALIDFAMILY); + } + + /* Create a UDP socket to communicate with NTP server */ + sd = SlNetSock_create(server->sa_family, SLNETSOCK_SOCK_DGRAM, SLNETSOCK_PROTO_UDP, ifID, 0); + if (sd < 0) + { + return (SNTP_ESOCKCREATEFAIL); + } + + ret = SlNetSock_connect(sd, server, saLen); + if (ret < 0) + { + SlNetSock_close(sd); + return (SNTP_ECONNECTFAIL); + } + + if (timeout != NULL) + { + /* Set the timeout for the server response to the user's value */ + ret = SlNetSock_setOpt(sd, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_TIMEO, timeout, sizeof(SlNetSock_Timeval_t)); + if (ret < 0) + { + SlNetSock_close(sd); + return (SNTP_ESOCKOPTFAIL); + } + } + + /* Initialize the SNTP packet, setting version and mode = client */ + memset(&sntpPkt, 0, sizeof(SNTP_Header_t)); + sntpPkt.flags = SNTP_VERSION << 3; + sntpPkt.flags |= SNTP_MODE_CLIENT; + + /* Set packet's transmit time as integrity check value */ + clock_gettime(CLOCK_REALTIME, &tspec); + integrityCheck = tspec.tv_sec; + sntpPkt.transmitTS[0] = integrityCheck; + + /* Send out our SNTP request to the current server */ + ret = SlNetSock_send(sd, (void *)&sntpPkt, sizeof(SNTP_Header_t), 0); + if (ret < 0) + { + SlNetSock_close(sd); + return (SNTP_ESENDFAIL); + } + + memset(&sntpPkt, 0, sizeof(SNTP_Header_t)); + + /* Retrieve the NTP packet from the socket and update our time. */ + ret = SlNetSock_recv(sd, &sntpPkt, sizeof(SNTP_Header_t), 0); + if ((ret < 0) || (ret != sizeof(SNTP_Header_t)) || (sntpPkt.originateTS[0] != integrityCheck)) + { + SlNetSock_close(sd); + return (SNTP_ERECVFAIL); + } + + /* Check for errors in server response */ + if (sntpPkt.stratum == 0) + { + /* Per RFC5905, we MUST handle Kiss O' Death packet */ + if ((sntpPkt.flags >> 6) == SNTP_NOSYNC) + { + /* KOD recv'd. Inspect kiss code & handle accordingly */ + ret = hasKissCode((char *)&sntpPkt.referenceID); + + if (ret == SNTP_KOD_RATE_CODE) + { + SlNetSock_close(sd); + return (SNTP_ERATEBACKOFF); + } + /* Check for fatal kiss codes */ + else if ((ret == SNTP_KOD_DENY_CODE) || (ret == SNTP_KOD_RSTR_CODE)) + { + SlNetSock_close(sd); + return (SNTP_EFATALNORETRY); + } + /* Per RFC5905, other kiss codes are ignored */ + } + else + { + /* + * A server response with stratum == 0, with no kiss + * code, is a fatal error. Mark server as invalid + */ + SlNetSock_close(sd); + return (SNTP_EINVALIDRESP); + } + } + + /* return the time in seconds */ + sntpPkt.transmitTS[0] = SlNetUtil_ntohl(sntpPkt.transmitTS[0]); + sntpPkt.transmitTS[1] = SlNetUtil_ntohl(sntpPkt.transmitTS[1]); + + *ntpTimeStamp = ((uint64_t)sntpPkt.transmitTS[0] << 32) | sntpPkt.transmitTS[1]; + + SlNetSock_close(sd); + return (0); +} + +int32_t SNTP_getTime(SlNetSock_Timeval_t *timeout, uint64_t *ntpTimeStamp) +{ + int32_t ret = 0; + int32_t ifID; + SlNetSock_AddrIn_t sa4; + SlNetSock_AddrIn6_t sa6; + SlNetSock_Addr_t *sa; + uint32_t addr[4]; + uint16_t family; + uint32_t i; + size_t count = NTP_SERVERS; + + for (i = 0; i < count; i++) + { + memset(&addr, 0, sizeof(addr)); + ifID = getAddrByName(SNTP_ServersList[i].name, addr, &family); + if(ifID >= 0) + { + if (family == SLNETSOCK_AF_INET) + { + sa4.sin_family = SLNETSOCK_AF_INET; + sa4.sin_port = SlNetUtil_htons(NTP_SERVER_PORT); + sa4.sin_addr.s_addr = SlNetUtil_htonl(addr[0]); + sa = (SlNetSock_Addr_t *)&sa4; + } + else + { + sa6.sin6_family = SLNETSOCK_AF_INET6; + sa6.sin6_port = SlNetUtil_htons(NTP_SERVER_PORT); + sa6.sin6_addr._S6_un._S6_u32[0] = SlNetUtil_htonl(addr[0]); + sa6.sin6_addr._S6_un._S6_u32[1] = SlNetUtil_htonl(addr[1]); + sa6.sin6_addr._S6_un._S6_u32[2] = SlNetUtil_htonl(addr[2]); + sa6.sin6_addr._S6_un._S6_u32[3] = SlNetUtil_htonl(addr[3]); + sa = (SlNetSock_Addr_t *)&sa6; + } + } + else + { + ret = SNTP_EGETHOSTBYNAMEFAIL; + continue; + } + + ret = getTime(sa, ifID, timeout, ntpTimeStamp); + if (ret == 0) + { + break; + } + } + + return (ret); +} + +//////////////////////////////////////////////////////////////////////////////// +// SNTP working thread +//////////////////////////////////////////////////////////////////////////////// +void* SntpWorkingThread(void* argument) +{ + (void)argument; + + uint64_t ntpTimeStamp; + uint32_t currentTime; + int32_t retval; + time_t ts; + SlNetSock_Timeval_t timeval; + struct timespec tspec; + + // Set timeout value for NTP server reply + timeval.tv_sec = NTP_REPLY_WAIT_TIME; + timeval.tv_usec = 0; + + while(1) + { + // Get the time use the SNTP_ServersList + retval = SNTP_getTime(&timeval, &ntpTimeStamp); + + if (retval != 0) + { + // sleep before retrying + sleep(SNTP_RETRY_TIMEOUT); + } + + currentTime = ntpTimeStamp >> 32; + currentTime = TIME_NTP_TO_LOCAL(currentTime); + + tspec.tv_nsec = 0; + tspec.tv_sec = currentTime; + + if (clock_settime(CLOCK_REALTIME, &tspec) != 0) + { + // failed to set current time + // don't do anything, just wait for the next attempt + } + + // sleep until next update time + sleep(SNTP_UPDATE_DELAY); + } + + pthread_exit(0); +} diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index 25e944024e..204354eff6 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -21,6 +21,8 @@ #include #include +#include + // Board Header files #include "Board.h" @@ -33,6 +35,7 @@ extern void * CLRStartupThread(void *arg0); extern void * ReceiverThread(void *arg0); +extern void sntp_init(void); ////////////////////////////// #define SL_STOP_TIMEOUT (200) @@ -794,7 +797,7 @@ void * mainThread(void *arg) pthread_attr_init(&threadAttributes); priorityParams.sched_priority = SPAWN_TASK_PRIORITY; retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); - retc |= pthread_attr_setstacksize(&threadAttributes, TASK_STACK_SIZE); + retc |= pthread_attr_setstacksize(&threadAttributes, 2 * TASK_STACK_SIZE); // The SimpleLink host driver architecture mandate spawn // thread to be created prior to calling Sl_start (turning the NWP on). @@ -915,7 +918,7 @@ void * mainThread(void *arg) pthread_attr_init(&threadAttributes); priorityParams.sched_priority = 1; retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); - retc |= pthread_attr_setstacksize(&threadAttributes, 8192); + retc |= pthread_attr_setstacksize(&threadAttributes, 4092); if (retc != 0) { // failed to set attributes @@ -934,6 +937,11 @@ void * mainThread(void *arg) } } + #ifdef SL_APP_SNTP + sntp_setservername(0, SNTP_SERVER_DEFAULT_ADDRESS); + sntp_init(); + #endif + return (0); } diff --git a/targets/TI-SimpleLink/nanoCLR/target_platform.h.in b/targets/TI-SimpleLink/nanoCLR/target_platform.h.in index 04cdd7d1c8..bfb0d3ebdf 100644 --- a/targets/TI-SimpleLink/nanoCLR/target_platform.h.in +++ b/targets/TI-SimpleLink/nanoCLR/target_platform.h.in @@ -11,8 +11,7 @@ #ifndef _TARGET_TI_SIMPLELINK_NANOCLR_H_ #define _TARGET_TI_SIMPLELINK_NANOCLR_H_ -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +// enable SNTP app +#define SL_APP_SNTP @NF_NETWORKING_SNTP@ #endif /* _TARGET_TI_SIMPLELINK_NANOCLR_H_ */ From acd4d29adf32e98e6b0d4fc5064c00a1b80c1c58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 23 Mar 2019 12:05:48 +0000 Subject: [PATCH 66/90] Moved config block defines to header --- .../targetHAL_ConfigurationManager_CC32xx.h | 19 +++++++++++++++++++ .../targetHAL_ConfigurationManager_CC32xx.cpp | 8 +------- 2 files changed, 20 insertions(+), 7 deletions(-) create mode 100644 targets/TI-SimpleLink/Include/targetHAL_ConfigurationManager_CC32xx.h diff --git a/targets/TI-SimpleLink/Include/targetHAL_ConfigurationManager_CC32xx.h b/targets/TI-SimpleLink/Include/targetHAL_ConfigurationManager_CC32xx.h new file mode 100644 index 0000000000..4a9313626a --- /dev/null +++ b/targets/TI-SimpleLink/Include/targetHAL_ConfigurationManager_CC32xx.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_CONFIGURATIONMANAGER_CC32XX_H_ +#define _TARGET_CONFIGURATIONMANAGER_CC32XX_H_ 1 + +// we'll store up to 4 network configuration blocks +#define NETWORK_CONFIG_MAX_COUNT (4) +// files with network configuration have this namming patter "network-config-N.bin" +#define NETWORK_CONFIG_FILE_NAME "nf/network-config0.bin" +// position of the index in the file name above (that's the 0) +#define NETWORK_CONFIG_FILE_INDEX_POSITION (17) + +// CA (Certificate Authority) root file name +#define CA_ROOT_CERT_FILE_NAME "ca-cert.pem" + +#endif //_TARGET_CONFIGURATIONMANAGER_CC32XX_H_ diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp index f436655a48..440d5d5ef1 100644 --- a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -7,15 +7,9 @@ #include #include +#include #include -// we'll store up to 4 network configuration blocks -#define NETWORK_CONFIG_MAX_COUNT (4) -// files with network configuration have this namming patter "network-config-N.bin" -#define NETWORK_CONFIG_FILE_NAME "nf/network-config0.bin" -// position of the index in the file name above (that's the 0) -#define NETWORK_CONFIG_FILE_INDEX_POSITION (17) - typedef struct { SlFileAttributes_t attribute; From 906000e45ab5c5d11025b470b992d7576ad73e6d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 23 Mar 2019 12:06:31 +0000 Subject: [PATCH 67/90] Wrok get and set socket options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../common/simplelink_sockets.cpp | 222 ------------------ .../common/sockets_simplelink.cpp | 203 +++++++++++++++- 2 files changed, 202 insertions(+), 223 deletions(-) diff --git a/targets/TI-SimpleLink/common/simplelink_sockets.cpp b/targets/TI-SimpleLink/common/simplelink_sockets.cpp index 49bec50e54..eb274542ff 100644 --- a/targets/TI-SimpleLink/common/simplelink_sockets.cpp +++ b/targets/TI-SimpleLink/common/simplelink_sockets.cpp @@ -309,65 +309,6 @@ int SimpleLink_SOCKETS_Driver::SetSockOpt( SOCK_SOCKET socket, int level, int op return lwip_setsockopt(socket, nativeLevel, nativeOptionName, pNativeOptionValue, optlen); } -int SimpleLink_SOCKETS_Driver::GetSockOpt( SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ) -{ - NATIVE_PROFILE_PAL_NETWORK(); - int nativeLevel; - int nativeOptionName; - char* pNativeOptval = optval; - int ret; - - switch(level) - { - case SOCK_IPPROTO_IP: - nativeLevel = IPPROTO_IP; - nativeOptionName = GetNativeIPOption(optname); - break; - case SOCK_IPPROTO_TCP: - nativeLevel = IPPROTO_TCP; - nativeOptionName = GetNativeTcpOption(optname); - break; - case SOCK_IPPROTO_UDP: - case SOCK_IPPROTO_ICMP: - case SOCK_IPPROTO_IGMP: - case SOCK_IPPROTO_IPV4: - case SOCK_SOL_SOCKET: - nativeLevel = SOL_SOCKET; - nativeOptionName = GetNativeSockOption(optname); - break; - default: - nativeLevel = level; - nativeOptionName = optname; - break; - } - - ret = lwip_getsockopt(socket, nativeLevel, nativeOptionName, pNativeOptval, (u32_t*)optlen); - - if(ret == 0) - { - switch(level) - { - case SOCK_SOL_SOCKET: - switch(optname) - { - case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: - case SOCK_SOCKO_DONTLINGER: - *optval = !(*(int*)optval != 0); - break; - - case SOCK_SOCKO_ACCEPTCONNECTION: - case SOCK_SOCKO_BROADCAST: - case SOCK_SOCKO_KEEPALIVE: - *optval = (*(int*)optval != 0); - break; - } - break; - } - } - - return ret; -} - int SimpleLink_SOCKETS_Driver::GetSockName( SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ) { NATIVE_PROFILE_PAL_NETWORK(); @@ -426,169 +367,6 @@ struct dhcp_client_id uint8_t clientId[6]; }; -int SimpleLink_SOCKETS_Driver::GetNativeTcpOption (int optname) -{ - NATIVE_PROFILE_PAL_NETWORK(); - int nativeOptionName = 0; - - switch(optname) - { - case SOCK_TCP_NODELAY: - nativeOptionName = TCP_NODELAY; - break; - - case SOCK_SOCKO_KEEPALIVE: - nativeOptionName = TCP_KEEPALIVE; - break; - - // allow the C# user to specify LWIP options that our managed enum - // doesn't support - default: - nativeOptionName = optname; - break; - } - return nativeOptionName; -} - -int SimpleLink_SOCKETS_Driver::GetNativeSockOption (int optname) -{ - NATIVE_PROFILE_PAL_NETWORK(); - int nativeOptionName = 0; - - switch(optname) - { - case SOCK_SOCKO_DONTLINGER: - case SOCK_SOCKO_LINGER: - nativeOptionName = SO_LINGER; - break; - case SOCK_SOCKO_SENDTIMEOUT: - nativeOptionName = SO_SNDTIMEO; - break; - case SOCK_SOCKO_RECEIVETIMEOUT: - nativeOptionName = SO_RCVTIMEO; - break; - case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: - case SOCK_SOCKO_REUSEADDRESS: - nativeOptionName = SO_REUSEADDR; - break; - case SOCK_SOCKO_KEEPALIVE: - nativeOptionName = SO_KEEPALIVE; - break; - case SOCK_SOCKO_ERROR: - nativeOptionName = SO_ERROR; - break; - case SOCK_SOCKO_BROADCAST: - nativeOptionName = SO_BROADCAST; - break; - case SOCK_SOCKO_RECEIVEBUFFER: - nativeOptionName = SO_RCVBUF; - break; - case SOCK_SOCKO_SENDBUFFER: - nativeOptionName = SO_SNDBUF; - break; - case SOCK_SOCKO_ACCEPTCONNECTION: - nativeOptionName = SO_ACCEPTCONN; - break; - case SOCK_SOCKO_TYPE: - nativeOptionName = SO_TYPE; - break; - - case SOCK_SOCKO_USELOOPBACK: - nativeOptionName = SO_USELOOPBACK; - break; - case SOCK_SOCKO_DONTROUTE: - nativeOptionName = SO_DONTROUTE; - break; - case SOCK_SOCKO_OUTOFBANDINLINE: - nativeOptionName = SO_OOBINLINE; - break; - - case SOCK_SOCKO_DEBUG: - nativeOptionName = SO_DEBUG; - break; - - case SOCK_SOCKO_SENDLOWWATER: - nativeOptionName = SO_SNDLOWAT; - break; - - case SOCK_SOCKO_RECEIVELOWWATER: - nativeOptionName = SO_RCVLOWAT; - break; - -// case SOCK_SOCKO_MAXCONNECTIONS: //don't support - case SOCK_SOCKO_UPDATE_ACCEPT_CTX: - case SOCK_SOCKO_UPDATE_CONNECT_CTX: - nativeOptionName = 0; - break; - - // allow the C# user to specify LWIP options that our managed enum - // doesn't support - default: - nativeOptionName = optname; - break; - - } - - return nativeOptionName; -} - -int SimpleLink_SOCKETS_Driver::GetNativeIPOption (int optname) -{ - NATIVE_PROFILE_PAL_NETWORK(); - int nativeOptionName = 0; - - switch(optname) - { - case SOCK_IPO_TTL: - nativeOptionName = IP_TTL; - break; - case SOCK_IPO_TOS: - nativeOptionName = IP_TOS; - break; -#if LWIP_IGMP - case SOCK_IPO_MULTICAST_IF: - nativeOptionName = IP_MULTICAST_IF; - break; - case SOCK_IPO_MULTICAST_TTL: - nativeOptionName = IP_MULTICAST_TTL; - break; - case SOCK_IPO_MULTICAST_LOOP: - nativeOptionName = IP_MULTICAST_LOOP; - break; - case SOCK_IPO_ADD_MEMBERSHIP: - nativeOptionName = IP_ADD_MEMBERSHIP; - break; - case SOCK_IPO_DROP_MEMBERSHIP: - nativeOptionName = IP_DROP_MEMBERSHIP; - break; -#else - case SOCK_IPO_MULTICAST_IF: - case SOCK_IPO_MULTICAST_TTL: - case SOCK_IPO_MULTICAST_LOOP: - case SOCK_IPO_ADD_MEMBERSHIP: - case SOCK_IPO_DROP_MEMBERSHIP: -#endif - case SOCK_IPO_ADD_SOURCE_MEMBERSHIP: - case SOCK_IPO_DROP_SOURCE_MEMBERSHIP: - case SOCK_IPO_OPTIONS: - case SOCK_IPO_HDRINCL: - case SOCK_IPO_IP_DONTFRAGMENT: - case SOCK_IPO_BLOCK_SOURCE: - case SOCK_IPO_UBLOCK_SOURCE: - case SOCK_IPO_PACKET_INFO: - nativeOptionName = 0; - break; - - // allow the C# user to specify LWIP options that our managed enum - // doesn't support - default: - nativeOptionName = optname; - break; - } - - return nativeOptionName; -} - int SimpleLink_SOCKETS_Driver::GetNativeError ( int error ) { NATIVE_PROFILE_PAL_NETWORK(); diff --git a/targets/TI-SimpleLink/common/sockets_simplelink.cpp b/targets/TI-SimpleLink/common/sockets_simplelink.cpp index 6539c85077..cb6e1e6b45 100644 --- a/targets/TI-SimpleLink/common/sockets_simplelink.cpp +++ b/targets/TI-SimpleLink/common/sockets_simplelink.cpp @@ -51,6 +51,156 @@ static void MARSHAL_SL_SDSET_TO_SOCK_FDSET(SOCK_fd_set* sf, SlNetSock_SdSet_t* f } } +int GetNativeTcpOption (int optname) +{ + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_TCP_NODELAY: + nativeOptionName = SLNETSOCK_TCP_NODELAY; + break; + + // case SOCK_SOCKO_KEEPALIVE: + // nativeOptionName = TCP_KEEPALIVE; + // break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + } + return nativeOptionName; +} + +int GetNativeSockOption (int optname) +{ + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_SOCKO_DONTLINGER: + case SOCK_SOCKO_LINGER: + nativeOptionName = SLNETSOCK_OPSOCK_LINGER; + break; + // case SOCK_SOCKO_SENDTIMEOUT: + // nativeOptionName = SO_SNDTIMEO; + // break; + case SOCK_SOCKO_RECEIVETIMEOUT: + nativeOptionName = SLNETSOCK_OPSOCK_RCV_TIMEO; + break; + // case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + // case SOCK_SOCKO_REUSEADDRESS: + // nativeOptionName = SO_REUSEADDR; + // break; + case SOCK_SOCKO_KEEPALIVE: + nativeOptionName = SLNETSOCK_OPSOCK_KEEPALIVE; + break; + case SOCK_SOCKO_ERROR: + nativeOptionName = SLNETSOCK_OPSOCK_ERROR; + break; + case SOCK_SOCKO_BROADCAST: + nativeOptionName = SLNETSOCK_OPSOCK_BROADCAST; + break; + case SOCK_SOCKO_RECEIVEBUFFER: + nativeOptionName = SLNETSOCK_OPSOCK_RCV_BUF; + break; + // case SOCK_SOCKO_SENDBUFFER: + // nativeOptionName = SO_SNDBUF; + // break; + // case SOCK_SOCKO_ACCEPTCONNECTION: + // nativeOptionName = SO_ACCEPTCONN; + // break; + // case SOCK_SOCKO_USELOOPBACK: + // nativeOptionName = SO_USELOOPBACK; + // break; + // case SOCK_SOCKO_DONTROUTE: + // nativeOptionName = SO_DONTROUTE; + // break; + // case SOCK_SOCKO_OUTOFBANDINLINE: + // nativeOptionName = SO_OOBINLINE; + // break; + + // case SOCK_SOCKO_DEBUG: + // nativeOptionName = SO_DEBUG; + // break; + + // case SOCK_SOCKO_SENDLOWWATER: + // nativeOptionName = SO_SNDLOWAT; + // break; + + // case SOCK_SOCKO_RECEIVELOWWATER: + // nativeOptionName = SO_RCVLOWAT; + // break; + + // case SOCK_SOCKO_MAXCONNECTIONS: //don't support + // case SOCK_SOCKO_UPDATE_ACCEPT_CTX: + // case SOCK_SOCKO_UPDATE_CONNECT_CTX: + // nativeOptionName = 0; + // break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + + } + + return nativeOptionName; +} + +int GetNativeIPOption (int optname) +{ + int nativeOptionName = 0; + + switch(optname) + { + // case SOCK_IPO_TTL: + // nativeOptionName = IP_TTL; + // break; + // case SOCK_IPO_TOS: + // nativeOptionName = IP_TOS; + // break; + + // case SOCK_IPO_MULTICAST_IF: + // nativeOptionName = IP_MULTICAST_IF; + // break; + // case SOCK_IPO_MULTICAST_TTL: + // nativeOptionName = SLNETSOCK_OPIP_MULTICAST_TTL; + // break; + // case SOCK_IPO_MULTICAST_LOOP: + // nativeOptionName = IP_MULTICAST_LOOP; + // break; + case SOCK_IPO_ADD_MEMBERSHIP: + nativeOptionName = SLNETSOCK_OPIP_ADD_MEMBERSHIP; + break; + case SOCK_IPO_DROP_MEMBERSHIP: + nativeOptionName = SLNETSOCK_OPIP_DROP_MEMBERSHIP; + break; + + // case SOCK_IPO_ADD_SOURCE_MEMBERSHIP: + // case SOCK_IPO_DROP_SOURCE_MEMBERSHIP: + // case SOCK_IPO_OPTIONS: + // case SOCK_IPO_HDRINCL: + // case SOCK_IPO_IP_DONTFRAGMENT: + // case SOCK_IPO_BLOCK_SOURCE: + // case SOCK_IPO_UBLOCK_SOURCE: + // case SOCK_IPO_PACKET_INFO: + // nativeOptionName = 0; + // break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + } + + return nativeOptionName; +} + SOCK_SOCKET SOCK_socket( int family, int type, int protocol ) { NATIVE_PROFILE_PAL_COM(); @@ -523,7 +673,58 @@ int SOCK_getsockopt( SOCK_SOCKET socket, int level, int optname, char* optval, i { NATIVE_PROFILE_PAL_COM(); - socketErrorCode = SlNetSock_getOpt( socket, level, optname, (void *)optval, (SlNetSocklen_t *)optlen ); + int nativeLevel; + int nativeOptionName; + char* pNativeOptval = optval; + int ret; + + switch(level) + { + case SOCK_IPPROTO_IP: + nativeLevel = SLNETSOCK_LVL_PHY; + nativeOptionName = GetNativeIPOption(optname); + break; + case SOCK_IPPROTO_TCP: + nativeLevel = SLNETSOCK_PROTO_TCP; + nativeOptionName = GetNativeTcpOption(optname); + break; + case SOCK_IPPROTO_UDP: + case SOCK_IPPROTO_ICMP: + case SOCK_IPPROTO_IGMP: + case SOCK_IPPROTO_IPV4: + case SOCK_SOL_SOCKET: + nativeLevel = SLNETSOCK_LVL_SOCKET; + nativeOptionName = GetNativeSockOption(optname); + break; + default: + nativeLevel = level; + nativeOptionName = optname; + break; + } + + socketErrorCode = SlNetSock_getOpt( socket, nativeLevel, nativeOptionName, (void *)pNativeOptval, (SlNetSocklen_t *)optlen ); + + if(socketErrorCode == 0) + { + switch(level) + { + case SOCK_SOL_SOCKET: + switch(optname) + { + case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + case SOCK_SOCKO_DONTLINGER: + *optval = !(*(int*)optval != 0); + break; + + case SOCK_SOCKO_ACCEPTCONNECTION: + case SOCK_SOCKO_BROADCAST: + case SOCK_SOCKO_KEEPALIVE: + *optval = (*(int*)optval != 0); + break; + } + break; + } + } return socketErrorCode; } From 54ff5212e6e16c665a2b8c00231b45f8fb119a5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 25 Mar 2019 18:14:31 +0000 Subject: [PATCH 68/90] Fix HAL_CONTINUATION::Dequeue_And_Execute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - The IRQ lock/unlock and execution sequence wasn't implemented correctly. Signed-off-by: José Simões --- src/PAL/AsyncProcCall/AsyncContinuations.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/PAL/AsyncProcCall/AsyncContinuations.cpp b/src/PAL/AsyncProcCall/AsyncContinuations.cpp index 0d8dc6bd0d..2b8983c916 100644 --- a/src/PAL/AsyncProcCall/AsyncContinuations.cpp +++ b/src/PAL/AsyncProcCall/AsyncContinuations.cpp @@ -58,16 +58,17 @@ bool HAL_CONTINUATION::Dequeue_And_Execute() return FALSE; } - //SystemState_SetNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); + SystemState_SetNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); HAL_CALLBACK call = ptr->Callback; GLOBAL_UNLOCK(irq); call.Execute(); - //irq.Acquire(); - //SystemState_ClearNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); // nestable + GLOBAL_LOCK(irq); + + SystemState_ClearNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); // nestable GLOBAL_UNLOCK(irq); return TRUE; From facae42366c69e7afe8f0245aa0b85061eed7c1f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 25 Mar 2019 18:15:21 +0000 Subject: [PATCH 69/90] Increase CLR region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c | 4 ++-- .../TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c index 64b0885fa7..4e2706c987 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -11,8 +11,8 @@ const BlockRange BlockRange1[] = { // the 1st block is reserved for the flash header // so we don't take it into account for the map - { BlockRange_BLOCKTYPE_CODE , 0 , 118 }, // 0x01000800 nanoCLR - { BlockRange_BLOCKTYPE_DEPLOYMENT , 119, 510 }, // 0x0103B800 deployment + { BlockRange_BLOCKTYPE_CODE , 0 , 119 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 120, 510 }, // 0x0103C000 deployment }; const BlockRegionInfo BlockRegions[] = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld index 0971256dbc..b5491c68e6 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03B800 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03C000 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } From eb7d76b1cf8ab2ed5f3235991856cf8005b98a89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 25 Mar 2019 18:17:54 +0000 Subject: [PATCH 70/90] Work in equivalent to lwIP drivers and low level functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Implementation of all SSL/TLS functions. - Add managed events for sockets and network. - Clean-up code and headers. Signed-off-by: José Simões --- .../TI_SimpleLink_CC32xx_sources.cmake | 25 + .../TI-SimpleLink/Include/ssl_simplelink.h | 18 + .../Include/targetSimpleLinkCC32xx_Threads.h | 9 + .../TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c | 3 + targets/TI-SimpleLink/common/CMakeLists.txt | 2 +- .../common/simplelink_sockets.cpp | 430 +----------------- .../TI-SimpleLink/common/simplelink_sockets.h | 120 +---- .../common/simplelink_sockets_functions.cpp | 13 + .../common/sockets_simplelink.cpp | 15 +- .../TI-SimpleLink/common/sockets_simplelink.h | 188 -------- .../TI-SimpleLink/common/ssl_simplelink.cpp | 374 ++++++++++++--- .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 110 +++-- 12 files changed, 480 insertions(+), 827 deletions(-) create mode 100644 targets/TI-SimpleLink/Include/ssl_simplelink.h delete mode 100644 targets/TI-SimpleLink/common/sockets_simplelink.h diff --git a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake index 0d47f0bce5..02a742aac6 100644 --- a/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake +++ b/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake @@ -13,6 +13,10 @@ list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSD list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/net") list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/bsd") +# includes for nanoFramework SSL driver +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/PAL/Com/sockets/ssl") + + # source files for board drivers set(BoardDrivers_SRCS @@ -210,6 +214,27 @@ foreach(SRC_FILE ${SLNetWiFi_SRCS}) list(APPEND TI_SimpleLink_SOURCES ${SLNetWiFi_SCR_FILE}) endforeach() + +# source files for nanoFramework SSL driver +set(nanoSsl_SRCS + + ssl.cpp +) + +foreach(SRC_FILE ${nanoSsl_SRCS}) + set(nanoSsl_SCR_FILE SRC_FILE -NOTFOUND) + find_file(nanoSsl_SCR_FILE ${SRC_FILE} + PATHS + + "${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoSsl_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${nanoSsl_SCR_FILE}) +endforeach() + + include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(SimpleLinkCC32xxSDK DEFAULT_MSG TI_SimpleLink_INCLUDE_DIRS TI_SimpleLink_SOURCES) diff --git a/targets/TI-SimpleLink/Include/ssl_simplelink.h b/targets/TI-SimpleLink/Include/ssl_simplelink.h new file mode 100644 index 0000000000..063d426c76 --- /dev/null +++ b/targets/TI-SimpleLink/Include/ssl_simplelink.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _SSL_SIMPLELINK_H_ +#define _SSL_SIMPLELINK_H_ 1 + +#include + +struct SlSSL_Context +{ + SlNetSockSecAttrib_t* SecurityAttributes; + uint32_t SocketFd; + bool IsServer; +}; + +#endif //_SSL_SIMPLELINK_H_ diff --git a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h index 257f661f94..12f92a8130 100644 --- a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h +++ b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h @@ -13,6 +13,7 @@ #include #include #include +#include #include // #include @@ -60,6 +61,12 @@ #define IS_IPV6G_ACQUIRED(status_variable) \ GET_STATUS_BIT(status_variable, AppStatusBits_Ipv6gAcquired) +typedef struct +{ + _u8 Sd; + _u8 Type; +} nFSlSocketAsyncEvent_t; + typedef enum { /* If this bit is set: Network Processor is powered up */ @@ -107,6 +114,8 @@ typedef struct nanoFramework_ControlBlock_t int16_t sockTcpServer; uint8_t configurationDone; uint8_t tcpConnected; + + mqd_t socketAsyncEvent; // uint32_t gatewayIP;/* Network Gateway IP address */ diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c index e9cbfccc20..255d7d5fdb 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -170,6 +170,9 @@ void CC3220SF_LAUNCHXL_initGeneral(void) { PRCMCC3200MCUInit(); Power_init(); + + // Mux Pin62 to mode 1 for outputing NWP logs + //MAP_PinTypeUART(PIN_62, PIN_MODE_1); } /* diff --git a/targets/TI-SimpleLink/common/CMakeLists.txt b/targets/TI-SimpleLink/common/CMakeLists.txt index 6bbe6947d6..ad8acd2185 100644 --- a/targets/TI-SimpleLink/common/CMakeLists.txt +++ b/targets/TI-SimpleLink/common/CMakeLists.txt @@ -28,7 +28,7 @@ endif() # append sockets and SSL driver list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/simplelink_sockets_functions.cpp") -# list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/simplelink_sockets.cpp") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/simplelink_sockets.cpp") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/sockets_simplelink.cpp") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/ssl_simplelink.cpp") diff --git a/targets/TI-SimpleLink/common/simplelink_sockets.cpp b/targets/TI-SimpleLink/common/simplelink_sockets.cpp index eb274542ff..4845b9b8f3 100644 --- a/targets/TI-SimpleLink/common/simplelink_sockets.cpp +++ b/targets/TI-SimpleLink/common/simplelink_sockets.cpp @@ -4,23 +4,8 @@ // See LICENSE file in the project root for full license information. // - #include "simplelink_sockets.h" -// extern "C" -// { -// #include "lwip\init.h" -// #include "lwip\tcpip.h" -// #include "lwip\dns.h" -// #include "lwip\netifapi.h" -// #include "lwip\Netdb.h" -// #include "lwip\tcp.h" -// #include "lwip\Sockets.h" -// #include "lwip\dhcp.h" -// #include "lwip\netif.h" -// } - - //--// #if defined(DEBUG) @@ -32,51 +17,50 @@ //--// -SimpleLink_SOCKETS_Driver g_SimpleLink_SOCKETS_Driver; - //--// static HAL_CONTINUATION PostAddressChangedContinuation; static HAL_CONTINUATION PostAvailabilityOnContinuation; static HAL_CONTINUATION PostAvailabilityOffContinuation; -void SimpleLink_SOCKETS_Driver::PostAddressChanged(void* arg) +void PostAddressChanged(void* arg) { (void)arg; Network_PostEvent(NetworkEventType_AddressChanged, 0); } -void SimpleLink_SOCKETS_Driver::PostAvailabilityOn(void* arg) +void PostAvailabilityOn(void* arg) { (void)arg; Network_PostEvent(NetworkEventType_AvailabilityChanged, NetworkEventFlags_NetworkAvailable); } -void SimpleLink_SOCKETS_Driver::PostAvailabilityOff(void* arg) +void PostAvailabilityOff(void* arg) { (void)arg; Network_PostEvent(NetworkEventType_AvailabilityChanged, NetworkEventFlags_NetworkNOTAvailable); } -void SimpleLink_SOCKETS_Driver::Link_callback() +void Link_callback(bool linkUp) { - // if (netif_is_link_up(netif)) - // { - // if (!PostAvailabilityOnContinuation.IsLinked()) - // PostAvailabilityOnContinuation.Enqueue(); - // } - // else - // { - // if (!PostAvailabilityOffContinuation.IsLinked()) - // PostAvailabilityOffContinuation.Enqueue(); - // } + if (linkUp) + { + if (!PostAvailabilityOnContinuation.IsLinked()) + PostAvailabilityOnContinuation.Enqueue(); + } + else + { + if (!PostAvailabilityOffContinuation.IsLinked()) + PostAvailabilityOffContinuation.Enqueue(); + } + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); Events_Set(SYSTEM_EVENT_FLAG_NETWORK); } -void SimpleLink_SOCKETS_Driver::Status_callback() +void Status_callback() { if (!PostAddressChangedContinuation.IsLinked()) PostAddressChangedContinuation.Enqueue(); @@ -122,396 +106,24 @@ void SimpleLink_SOCKETS_Driver::Status_callback() } #endif -bool SimpleLink_SOCKETS_Driver::Initialize() +bool SimpleLink_SOCKETS_Initialize() { NATIVE_PROFILE_PAL_NETWORK(); - struct netif *networkInterface; - HAL_Configuration_NetworkInterface networkConfiguration; - int interfaceNumber; - PostAddressChangedContinuation.InitializeCallback(PostAddressChanged, NULL); PostAvailabilityOnContinuation.InitializeCallback(PostAvailabilityOn, NULL); PostAvailabilityOffContinuation.InitializeCallback(PostAvailabilityOff, NULL); - // create m_interfaceNumber array - int interfaceCount = g_TargetConfiguration.NetworkInterfaceConfigs->Count; - // FIXME - // g_SimpleLink_SOCKETS_Driver.m_interfaces = (LWIP_DRIVER_INTERFACE_DATA*)platform_malloc(interfaceCount * sizeof(LWIP_DRIVER_INTERFACE_DATA)); - - // FIXME - // already done? - /* Initialize the target board lwIP stack */ - //nanoHAL_Network_Initialize(); - - for (int i = 0; i < g_TargetConfiguration.NetworkInterfaceConfigs->Count; i++) - { - // load network interface configuration from storage - if(!ConfigurationManager_GetConfigurationBlock((void*)&networkConfiguration, DeviceConfigurationOption_Network, i)) - { - // failed to load configuration - // FIXME output error? - // move to the next, if any - continue; - } - _ASSERTE(networkConfiguration.StartupAddressMode > 0); - - /* Bind and Open the Ethernet driver */ - Network_Interface_Bind(i); - interfaceNumber = Network_Interface_Open(i); - - if (interfaceNumber == SOCK_SOCKET_ERROR) - { - DEBUG_HANDLE_SOCKET_ERROR("Network init", FALSE); -//FIXME debug_printf("SocketError: %d\n", errorCode); - continue; - } - - g_SimpleLink_SOCKETS_Driver.m_interfaces[i].m_interfaceNumber = interfaceNumber; - -// UpdateAdapterConfiguration(i, (UpdateOperation_Dhcp | UpdateOperation_Dns), &networkConfiguration); - -// networkInterface = netif_find_interface(interfaceNumber); - -// if (networkInterface) -// { -// netif_set_link_callback(networkInterface, Link_callback); - -// if (netif_is_link_up(networkInterface)) -// { -// Link_callback(networkInterface); -// } - -// netif_set_status_callback(networkInterface, Status_callback); - -// if (netif_is_up(networkInterface)) -// { -// Status_callback(networkInterface); -// } - -// // default debugger interface -// if (0 == i) -// { -// #if LWIP_IPV6 -// //uint8_t* addr = (uint8_t*)&networkInterface->ip_addr.u_addr.ip4.addr; -// #else -// //uint8_t* addr = (uint8_t*)&networkInterface->ip_addr.addr; -// #endif -// // lcd_printf("\f\n\n\n\n\n\n\nip address: %d.%d.%d.%d\r\n", addr[0], addr[1], addr[2], addr[3]); -// // FIXME debug_printf("ip address from interface info: %d.%d.%d.%d\r\n", addr[0], addr[1], addr[2], addr[3]); -// } -// } - } - - return TRUE; + return true; } -bool SimpleLink_SOCKETS_Driver::Uninitialize() +bool SimpleLink_SOCKETS_Uninitialize() { - NATIVE_PROFILE_PAL_NETWORK(); + NATIVE_PROFILE_PAL_NETWORK(); PostAddressChangedContinuation.Abort(); PostAvailabilityOnContinuation.Abort(); PostAvailabilityOffContinuation.Abort(); - for(int i=0; iCount; i++) - { - Network_Interface_Close(i); - } - -//FIXME tcpip_shutdown(); -// tcpip_shutdown is MS method added to lwip tcpip.c - - return TRUE; -} - -SOCK_SOCKET SimpleLink_SOCKETS_Driver::Accept(SOCK_SOCKET socket, SOCK_sockaddr* address, int* addressLen) -{ - NATIVE_PROFILE_PAL_NETWORK(); - SOCK_SOCKET ret; - - sockaddr_in addr; - - if (address) - { - SOCK_SOCKADDR_TO_SOCKADDR(address, addr, addressLen); - } - - ret = lwip_accept(socket, address?(sockaddr*)&addr:NULL, (u32_t*)addressLen); - - if(address) - { - SOCKADDR_TO_SOCK_SOCKADDR(address, addr, addressLen); - } - - return ret; -} - -int SimpleLink_SOCKETS_Driver::SetSockOpt( SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ) -{ - NATIVE_PROFILE_PAL_NETWORK(); - int nativeLevel; - int nativeOptionName; - int nativeIntValue; - char *pNativeOptionValue = (char*)optval; - struct linger lopt = {0,0}; - - switch(level) - { - case SOCK_IPPROTO_IP: - nativeLevel = IPPROTO_IP; - nativeOptionName = GetNativeIPOption(optname); - break; - case SOCK_IPPROTO_TCP: - nativeLevel = IPPROTO_TCP; - nativeOptionName = GetNativeTcpOption(optname); - break; - case SOCK_IPPROTO_UDP: - case SOCK_IPPROTO_ICMP: - case SOCK_IPPROTO_IGMP: - case SOCK_IPPROTO_IPV4: - case SOCK_SOL_SOCKET: - nativeLevel = SOL_SOCKET; - nativeOptionName = GetNativeSockOption(optname); - - switch(optname) - { - // If linger value negative then linger off - // otherwise enabled and linger value is number of seconds - case SOCK_SOCKO_LINGER: - { - int lingerValue = *(int*)optval; - if ( lingerValue >= 0 ) - { - lopt.l_onoff = 1; - lopt.l_linger = abs(lingerValue); - } - pNativeOptionValue = (char*)&lopt; - optlen = sizeof(lopt); - } - break; - - case SOCK_SOCKO_DONTLINGER: - case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: - nativeIntValue = !*(int*)optval; - pNativeOptionValue = (char*)&nativeIntValue; - break; - default: - break; - } - break; - default: - nativeLevel = 0; - nativeOptionName = 0; - break; - } - - return lwip_setsockopt(socket, nativeLevel, nativeOptionName, pNativeOptionValue, optlen); -} - -int SimpleLink_SOCKETS_Driver::GetSockName( SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ) -{ - NATIVE_PROFILE_PAL_NETWORK(); - int ret; - - sockaddr_in addr; - - SOCK_SOCKADDR_TO_SOCKADDR(name, addr, namelen); - - ret = lwip_getsockname(socket, (sockaddr*)&addr, (u32_t*)namelen); - - SOCKADDR_TO_SOCK_SOCKADDR(name, addr, namelen); - - return ret; -} - -int SimpleLink_SOCKETS_Driver::RecvFrom( SOCK_SOCKET socket, char* buf, int len, int flags, SOCK_sockaddr* from, int* fromlen ) -{ - NATIVE_PROFILE_PAL_NETWORK(); - sockaddr_in addr; - sockaddr *pFrom = NULL; - int ret; - - if(from) - { - SOCK_SOCKADDR_TO_SOCKADDR(from, addr, fromlen); - pFrom = (sockaddr*)&addr; - } - - ret = lwip_recvfrom(socket, buf, len, flags, pFrom, (u32_t*)fromlen); - - if(from && ret != SOCK_SOCKET_ERROR) - { - SOCKADDR_TO_SOCK_SOCKADDR(from, addr, fromlen); - } - - return ret; -} - -int SimpleLink_SOCKETS_Driver::SendTo( SOCK_SOCKET socket, const char* buf, int len, int flags, const SOCK_sockaddr* to, int tolen ) -{ - NATIVE_PROFILE_PAL_NETWORK(); - - sockaddr_in addr; - - SOCK_SOCKADDR_TO_SOCKADDR(to, addr, &tolen); - - return lwip_sendto(socket, buf, len, flags, (sockaddr*)&addr, (u32_t)tolen); -} - -struct dhcp_client_id -{ - uint8_t code; - uint8_t length; - uint8_t type; - uint8_t clientId[6]; -}; - -int SimpleLink_SOCKETS_Driver::GetNativeError ( int error ) -{ - NATIVE_PROFILE_PAL_NETWORK(); - int ret; - - switch(error) - { - case EINTR: - ret = SOCK_EINTR; - break; - - case EACCES: - ret = SOCK_EACCES; - break; - - case EFAULT: - ret = SOCK_EFAULT; - break; - - case EINVAL: - ret = SOCK_EINVAL; - break; - - case EMFILE: - ret = SOCK_EMFILE; - break; - - case EAGAIN: - case EBUSY: - /* case EWOULDBLOCK: same as EINPROGRESS */ - case EINPROGRESS: - ret = SOCK_EWOULDBLOCK; - break; - - case EALREADY: - ret = SOCK_EALREADY; - break; - - case ENOTSOCK: - ret = SOCK_ENOTSOCK; - break; - - case EDESTADDRREQ: - ret = SOCK_EDESTADDRREQ; - break; - - case EMSGSIZE: - ret = SOCK_EMSGSIZE; - break; - - case EPROTOTYPE: - ret = SOCK_EPROTOTYPE; - break; - - case ENOPROTOOPT: - ret = SOCK_ENOPROTOOPT; - break; - - case EPROTONOSUPPORT: - ret = SOCK_EPROTONOSUPPORT; - break; -// TODO nanoframework check why missing - // case ESOCKTNOSUPPORT: - // ret = SOCK_ESOCKTNOSUPPORT; - // break; - - case EPFNOSUPPORT: - ret = SOCK_EPFNOSUPPORT; - break; - - case EAFNOSUPPORT: - ret = SOCK_EAFNOSUPPORT; - break; - - case EADDRINUSE: - ret = SOCK_EADDRINUSE; - break; - - case EADDRNOTAVAIL: - ret = SOCK_EADDRNOTAVAIL; - break; - - case ENETDOWN: - ret = SOCK_ENETDOWN; - break; - - case ENETUNREACH: - ret = SOCK_ENETUNREACH; - break; - - case ENETRESET: - ret = SOCK_ENETRESET; - break; - - case ECONNABORTED: - ret = SOCK_ECONNABORTED; - break; - - case ECONNRESET: - ret = SOCK_ECONNRESET; - break; - - case ENOBUFS: - case ENOMEM: - ret = SOCK_ENOBUFS; - break; - - case EISCONN: - ret = SOCK_EISCONN; - break; - - case ENOTCONN: - ret = SOCK_EISCONN; - break; - -#if !defined(__GNUC__) // same as ENOTSOCK for GCC - case ESHUTDOWN: - ret = SOCK_ESHUTDOWN; - break; -#endif - - case ETIMEDOUT: - ret = SOCK_ETIMEDOUT; - break; - - case ECONNREFUSED: - ret = SOCK_ECONNREFUSED; - break; - - case EHOSTDOWN: - ret = SOCK_EHOSTDOWN; - break; - - case EHOSTUNREACH: - ret = SOCK_EHOSTUNREACH; - break; - - case ENODATA: - ret = SOCK_NO_DATA; - break; - - default: - ret = error; - break; - } - - return (ret); + return true; } diff --git a/targets/TI-SimpleLink/common/simplelink_sockets.h b/targets/TI-SimpleLink/common/simplelink_sockets.h index 2f99320314..d7cf746528 100644 --- a/targets/TI-SimpleLink/common/simplelink_sockets.h +++ b/targets/TI-SimpleLink/common/simplelink_sockets.h @@ -12,115 +12,21 @@ #define NATIVE_PROFILE_PAL_NETWORK() -////////////////////////////////////////////////////////////////////////////// -// SOCKET driver -// +#ifdef __cplusplus +extern "C" { +#endif -// struct LWIP_DRIVER_INTERFACE_DATA -// { -// int m_interfaceNumber; -// }; +bool SimpleLink_SOCKETS_Initialize(); +bool SimpleLink_SOCKETS_Uninitialize(); -// #define SOCK_SOCKADDR_TO_SOCKADDR(ssa, sa, addrLen) \ -// sa.sin_len = (u8_t)sizeof(sa); \ -// sa.sin_family = (u8_t)((SOCK_sockaddr_in*)ssa)->sin_family; \ -// sa.sin_port = ((SOCK_sockaddr_in*)ssa)->sin_port; \ -// sa.sin_addr.s_addr = ((SOCK_sockaddr_in*)ssa)->sin_addr.S_un.S_addr; \ -// memcpy(sa.sin_zero, ((SOCK_sockaddr_in*)ssa)->sin_zero, sizeof(sa.sin_zero)); \ -// *addrLen = sizeof(sa) +void Status_callback(); +void Link_callback(bool linkUp); +// void PostAddressChanged(void* arg); +// void PostAvailabilityOn(void* arg); +// void PostAvailabilityOff(void* arg); -// #define SOCKADDR_TO_SOCK_SOCKADDR(ssa, sa, addrLen) \ -// ((SOCK_sockaddr_in*)ssa)->sin_port = sa.sin_port; \ -// ((SOCK_sockaddr_in*)ssa)->sin_addr.S_un.S_addr = sa.sin_addr.s_addr; \ -// ((SOCK_sockaddr_in*)ssa)->sin_family = sa.sin_family; \ -// memcpy(((SOCK_sockaddr_in*)ssa)->sin_zero, sa.sin_zero, sizeof(((SOCK_sockaddr_in*)ssa)->sin_zero)); \ -// *addrLen = sizeof(SOCK_sockaddr_in) - - -struct SimpleLink_SOCKETS_Driver -{ - static bool Initialize(); - - static bool Uninitialize(); - - static SOCK_SOCKET Socket( int family, int type, int protocol ); - - static int Bind( SOCK_SOCKET socket, const SOCK_sockaddr* address, int addressLen ); - - static int Connect(SOCK_SOCKET socket, const SOCK_sockaddr* address, int addressLen); - - static int Send(SOCK_SOCKET socket, const char* buf, int len, int flags); - - static int Recv(SOCK_SOCKET socket, char* buf, int len, int flags); - - static int Close(SOCK_SOCKET socket); - - static int Listen(SOCK_SOCKET socket, int backlog ); - - static SOCK_SOCKET Accept(SOCK_SOCKET socket, SOCK_sockaddr* address, int* addressLen ); - - - static int Shutdown(SOCK_SOCKET socket, int how ); - - static int GetAddrInfo(const char* nodename, - char* servname, - const SOCK_addrinfo* hints, - SOCK_addrinfo** res ); - - static void FreeAddrInfo(SOCK_addrinfo* ai ); - - static int Ioctl(SOCK_SOCKET socket, int cmd, int* data ); - - static int GetLastError(); - - static int GetSockLastError(SOCK_SOCKET socket); - - static int GetNativeTcpOption (int optname); - - static int GetNativeSockOption (int optname); - - static int GetNativeError( int error ); - - static int GetNativeIPOption (int optname); - - static int Select(int nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* exceptfds, const SOCK_timeval* timeout ); - - static int SetSockOpt(SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ); - - static int GetSockOpt(SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ); - - static int GetPeerName(SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ); - - static int GetSockName(SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ); - - static int RecvFrom(SOCK_SOCKET s, char* buf, int len, int flags, SOCK_sockaddr* from, int* fromlen ); - - static int SendTo(SOCK_SOCKET s, const char* buf, int len, int flags, const SOCK_sockaddr* to, int tolen ); - - static HRESULT LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex); - - static HRESULT UpdateAdapterConfiguration( uint32_t interfaceIndex, uint32_t updateFlags, HAL_Configuration_NetworkInterface* config ); - - static HRESULT LoadWirelessConfiguration( uint32_t interfaceIndex, HAL_Configuration_Wireless80211* wirelessConfig ); - - -private: - static void Status_callback(); - - static void Link_callback(); - - static void PostAddressChanged(void* arg); - - static void PostAvailabilityOn(void* arg); - - static void PostAvailabilityOff(void* arg); - - //LWIP_DRIVER_INTERFACE_DATA* m_interfaces; -}; - -// -// SOCKET driver -///////////////////////////////////////////////////////////////////////////////////////////////// +#ifdef __cplusplus +} +#endif #endif // _SIMPLELINK_SOCKETS_H_ 1 - diff --git a/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp b/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp index 2105865889..9f8dbcb9cb 100644 --- a/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp +++ b/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp @@ -6,11 +6,24 @@ #include #include +#include "simplelink_sockets.h" #include #define NATIVE_PROFILE_PAL_NETWORK() +bool HAL_SOCK_Initialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return SimpleLink_SOCKETS_Initialize(); +} + +bool HAL_SOCK_Uninitialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return SimpleLink_SOCKETS_Uninitialize(); +} + HRESULT HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) { NATIVE_PROFILE_PAL_NETWORK(); diff --git a/targets/TI-SimpleLink/common/sockets_simplelink.cpp b/targets/TI-SimpleLink/common/sockets_simplelink.cpp index cb6e1e6b45..9e6ad9b2f5 100644 --- a/targets/TI-SimpleLink/common/sockets_simplelink.cpp +++ b/targets/TI-SimpleLink/common/sockets_simplelink.cpp @@ -4,8 +4,8 @@ // See LICENSE file in the project root for full license information. // -//#include "sockets_simplelink.h" #include +#include "simplelink_sockets.h" #include #include @@ -14,7 +14,7 @@ //--// // this is to store the return value of the calls to sockets APIs -static int socketErrorCode = 0; +int socketErrorCode; static int MARSHAL_SOCK_FDSET_TO_SL_SDSET(SOCK_fd_set* sf, SlNetSock_SdSet_t* f) { @@ -769,6 +769,9 @@ bool Network_Initialize() { NATIVE_PROFILE_PAL_COM(); + // call our equivalent to lwIP driver + return SimpleLink_SOCKETS_Initialize(); + // network initialization is taken care of by SimpleLink return true; } @@ -837,14 +840,6 @@ HRESULT SOCK_CONFIGURATION_LoadConfiguration(HAL_Configuration_NetworkInterface* return hr; } -#define SOCKET_SHUTDOWN_READ 0 -#define SOCKET_SHUTDOWN_WRITE 1 -#define SOCKET_SHUTDOWN_READ_WRITE 2 - -#define ISSET_SOCKET_FLAG(x,y) ((y) == ((y) & (x).m_flags)) -#define SET_SOCKET_FLAG(x,y) (x).m_flags |= (y) -#define CLEAR_SOCKET_FLAG(x,y) (x).m_flags &= ~(y) - bool SOCKETS_DbgInitialize( int ComPortNum ) { NATIVE_PROFILE_PAL_COM(); diff --git a/targets/TI-SimpleLink/common/sockets_simplelink.h b/targets/TI-SimpleLink/common/sockets_simplelink.h deleted file mode 100644 index 6a738fcf30..0000000000 --- a/targets/TI-SimpleLink/common/sockets_simplelink.h +++ /dev/null @@ -1,188 +0,0 @@ -// -// Copyright (c) 2019 The nanoFramework project contributors -// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. -// See LICENSE file in the project root for full license information. -// - -#ifndef _SOCKETS_H_ -#define _SOCKETS_H_ 1 - -//--// - -#include -#include - -//--// - -#define SOCKET_CHECK_ENTER() \ - int32_t ret=0 \ - -#define SOCKET_CLEANUP() \ - goto RETURN_OK; \ - SOCKET_CHECK_RETURN: \ - -#define SOCKET_CHECK_EXIT_CLEANUP() \ - RETURN_OK: \ - ASSERT(ret != SOCK_SOCKET_ERROR); \ - return ret; \ - -#define SOCKET_CHECK_EXIT() \ - SOCKET_CLEANUP() \ - RETURN_OK: \ - ASSERT(ret != SOCK_SOCKET_ERROR); \ - return ret; \ - -#define SOCKET_CHECK_EXIT_bool() \ - SOCKET_CLEANUP() \ - RETURN_OK: \ - return ret != SOCK_SOCKET_ERROR; \ - -#define SOCKET_CHECK_EXIT_bool_CLEANUP()\ - RETURN_OK: \ - return ret != SOCK_SOCKET_ERROR; \ - -#define SOCKET_CHECK_RESULT(x) \ - if((ret = (x)) == SOCK_SOCKET_ERROR)\ - { \ - goto SOCKET_CHECK_RETURN; \ - } \ - -#define SOCKET_CHECK_bool(x) \ - if(!(x)) \ - { \ - ret = SOCK_SOCKET_ERROR; \ - goto SOCKET_CHECK_RETURN; \ - } \ - -#define SOCKET_CHECK_EXIT_NORETURN() \ - RETURN_OK: \ - -struct Sockets_SimpleLink_Driver -{ - static SOCK_SOCKET Socket( int32_t family, int32_t type, int32_t protocol, bool fDebug ); - static int Connect(SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int32_t addressLen) ; - static int Send(SOCK_SOCKET socket, const char* buf, int32_t len, int32_t flags) ; - static int Recv(SOCK_SOCKET socket, char* buf, int32_t len, int32_t flags); - static int Close(SOCK_SOCKET socket); - static int Listen( SOCK_SOCKET socket, int32_t backlog ); - static SOCK_SOCKET Accept( SOCK_SOCKET socket, struct SOCK_sockaddr* address, int* addressLen, bool fDebug ); - static int Select( int32_t nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* except, const struct SOCK_timeval* timeout ); - static int RecvFrom( SOCK_SOCKET s, char* buf, int32_t len, int32_t flags, struct SOCK_sockaddr* from, int* fromlen ); - static int SendTo( SOCK_SOCKET s, const char* buf, int32_t len, int32_t flags, const struct SOCK_sockaddr* to, int32_t tolen ); - static int Shutdown( SOCK_SOCKET s, int32_t how); - - static bool Initialize(); - static bool Uninitialize(); - static void CloseConnections(bool fCloseDbg); - - static void SaveConfig(int32_t index, HAL_Configuration_NetworkInterface *cfg); - - // Debugger methods ( socket_debugger.cpp ) - static void Debugger_Initialize(); - static void Debugger_Uninitialize(); - static void Debugger_Abort(); - - static bool InitializeDbgListener( int ComPortNum ); - static bool UninitializeDbgListener( int ComPortNum ); - static int Write( int ComPortNum, const char* Data, size_t size ); - static int Read ( int ComPortNum, char* Data, size_t size ); - static bool UpgradeToSsl( int ComPortNum, const int8_t* pCACert, uint32_t caCertLen, const int8_t* pDeviceCert, uint32_t deviceCertLen, const char* szTargetHost ); - static bool IsUsingSsl( int ComPortNum ); - - void* GetSocketSslData(SOCK_SOCKET socket) - { - int32_t tmp; - - return GetSocketSslData(socket, tmp); - } - - void* GetSocketSslData(SOCK_SOCKET socket, int32_t &sockIndex) - { - GLOBAL_LOCK_SOCKETS(x); - - for(int i=m_cntSockets-1; i>=0; i--) - { - if(socket == m_socketHandles[i].m_socket) - { - sockIndex = i; - return m_socketHandles[i].m_sslData; - } - } - - return NULL; - } - - void SetSocketSslData(SOCK_SOCKET socket, void* sslObj) - { - GLOBAL_LOCK_SOCKETS(x); - - for(int i=m_cntSockets-1; i>=0; i--) - { - if(socket == m_socketHandles[i].m_socket) - { - m_socketHandles[i].m_sslData = sslObj; - - break; - } - } - } - - // required by SSL - static void UnregisterSocket( int index ); - - - static void ClearStatusBitsForSocket(SOCK_SOCKET sock, bool fWrite); - static bool InitializeMulticastDiscovery(); - -private: - - static void RegisterSocket( SOCK_SOCKET sock, bool selectable, bool fDebug ); - - struct SocketRegisterMap - { - SOCK_SOCKET m_socket; - uint32_t m_flags; - void* m_sslData; - - static const uint32_t c_SelectableSocket = 0x0001; - static const uint32_t c_DebugSocket = 0x0002; - static const uint32_t c_CloseSocket = 0x0004; - }; - - enum DebuggerState - { - DbgSock_Uninitialized = 0, - DbgSock_Listening = 1, - DbgSock_Connected = 2, - } m_stateDebugSocket; - - bool m_usingSSL; - - static void MulticastDiscoveryRespond(void* arg); - static void MulticastDiscoverySchedule(); - - static void CloseDebuggerSocket(); - static void OnDebuggerTimeout(void* arg); - - static HAL_COMPLETION s_DebuggerTimeoutCompletion; - - SOCK_SOCKET m_SocketDebugListener; - SOCK_SOCKET m_SocketDebugStream; - SOCK_SOCKET m_multicastSocket; - - bool m_fShuttingDown; - - int32_t m_cntSockets; - struct SocketRegisterMap m_socketHandles[SOCKETS_MAX_COUNT]; - - static bool s_initialized; - static bool s_initializedDbg; - static const int32_t c_WellKnownDebugPort = DEBUG_SOCKET_PORT; - static bool s_wirelessInitialized; - static bool s_discoveryInitialized; -}; - -extern Sockets_SimpleLink_Driver g_Sockets_SimpleLink_Driver; - -#endif //_SOCKETS_H_ - diff --git a/targets/TI-SimpleLink/common/ssl_simplelink.cpp b/targets/TI-SimpleLink/common/ssl_simplelink.cpp index 168ffb43ad..46fdd8659f 100644 --- a/targets/TI-SimpleLink/common/ssl_simplelink.cpp +++ b/targets/TI-SimpleLink/common/ssl_simplelink.cpp @@ -4,10 +4,26 @@ // See LICENSE file in the project root for full license information. // -#include "nanoHal.h" +#include +#include +#include +#include +#include + +#include +#include +#include //--// +// TODO +bool ssl_parse_certificate_internal(void* buf, size_t size, void* pwd, void* x509 ){(void)buf;(void)size;(void)pwd;(void)x509;} +int ssl_accept_internal( int socket, int sslContextHandle ){(void)socket;(void)sslContextHandle;} +bool ssl_add_cert_auth_internal( int sslContextHandle, const char* certificate, int certLength, const char* certPassword ){(void)sslContextHandle;(void)certificate;(void)certLength;(void)certPassword;} + +// declared at sockets_simplelink +extern int socketErrorCode; + extern "C" { void ssl_rand_seed(const void *seed, int length) @@ -17,104 +33,324 @@ void ssl_rand_seed(const void *seed, int length) } } -__nfweak bool SSL_Initialize() +bool ssl_initialize_internal() { - NATIVE_PROFILE_PAL_COM(); - return FALSE; + memset(&g_SSL_Driver, 0, sizeof(g_SSL_Driver)); + + return true; } -__nfweak bool SSL_Uninitialize() +bool ssl_generic_init_internal( int sslMode, int sslVerify, const char* certificate, + int certLength, const char* certPassword, int& sslContextHandle, bool isServer ) { - NATIVE_PROFILE_PAL_COM(); - return TRUE; -} + (void)certPassword; -__nfweak bool SSL_ServerInit( int sslMode, int sslVerify, const char* certificate, int certLength, const char* certPassword, int& sslContextHandle ) -{ - (void)sslMode; (void)sslVerify; (void)certificate; (void)certLength; (void)certPassword; (void)sslContextHandle; - NATIVE_PROFILE_PAL_COM(); - return TRUE; -} + int sslContexIndex = -1; + + SlSSL_Context* context; + SlNetSockSecAttrib_e attribName; + int32_t status; + uint32_t dummyVal = 1; + uint8_t securityMethod; + uint32_t securityCypher = SLNETSOCK_SEC_CIPHER_FULL_LIST; + + // we only have one CA root bundle, so this is fixed to 0 + uint32_t configIndex = 0; + + /////////////////////// + for(uint32_t i=0; iSecurityAttributes = SlNetSock_secAttribCreate(); + if (context->SecurityAttributes == NULL) + { + goto error; + } + + context->IsServer = isServer; + + // configure protocol + switch((SslProtocols)sslMode) + { + case SslProtocols_SSLv3: + securityMethod = SLNETSOCK_SEC_METHOD_SSLV3; + break; + + case SslProtocols_TLSv1: + securityMethod = SLNETSOCK_SEC_METHOD_TLSV1; + break; + + case SslProtocols_TLSv11: + securityMethod = SLNETSOCK_SEC_METHOD_TLSV1_1; + break; + + case SslProtocols_TLSv12: + securityMethod = SLNETSOCK_SEC_METHOD_TLSV1_2; + break; + + default: + // shouldn't reach here! + goto error; + } + status = SlNetSock_secAttribSet(context->SecurityAttributes, SLNETSOCK_SEC_ATTRIB_METHOD, (void *)&(securityMethod), sizeof(securityMethod)); + if (status < 0) + { + goto error; + } + + // enable all cyphers (this is Simple Link default, so nothing to do about this) + + // CA root certs are taken from Simple Link trusted root-certificate catalog, so nothing to do here + + // // parse "own" certificate if passed + // if(certificate != NULL && certLength > 0) + // { + // // TODO + // // this isn't required for client authentication + + // // mbedtls_x509_crt_init( &clicert ); + + // // ///////////////////////////////////////////////////////////////////////////////////////////////// + // // // developer notes: // + // // // this call parses certificates in both string and binary formats // + // // // when the formart is a string it has to include the terminator otherwise the parse will fail // + // // ///////////////////////////////////////////////////////////////////////////////////////////////// + // // if(mbedtls_x509_crt_parse( &clicert, (const unsigned char*)certificate, certLength ) != 0) + // // { + // // // x509_crt_parse_failed + // // goto error; + // // } + + // // if( mbedtls_pk_parse_key( &pkey, (const unsigned char *) mbedtls_test_cli_key, mbedtls_test_cli_key_len, NULL, 0 ) != 0) + // // { + // // // failed parsing the + // // } + + // // if( mbedtls_ssl_conf_own_cert( &conf, &clicert, &pkey ) != 0 ) + // // { + // // // configuring own certificate failed + // // goto error; + // // } + // } + + // set certificate verification + // the current options provided by Simple Link API are only verify or don't verify + if((SslVerification)sslVerify == SslVerification_NoVerification) + { + status = SlNetSock_secAttribSet(context->SecurityAttributes, SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE, (void *)&dummyVal, sizeof(dummyVal)); + if (status < 0) + { + goto error; + } + } + + ////////////////////////////////////// + + // the equivalent of SSL contex in Simple Link is the Security Attribute that we've been building + g_SSL_Driver.m_sslContextArray[sslContexIndex].SslContext = context; + g_SSL_Driver.m_sslContextCount++; + + sslContextHandle = sslContexIndex; + + return true; -__nfweak bool SSL_ClientInit( int sslMode, int sslVerify, const char* certificate, int certLength, const char* certPassword, int& sslContextHandle ) -{ - (void)sslMode; (void)sslVerify; (void)certificate; (void)certLength; (void)certPassword; (void)sslContextHandle; - NATIVE_PROFILE_PAL_COM(); - return TRUE; + error: + + // check for any memory allocation that needs to be freed before exiting + if(context != NULL) + { + platform_free(context); + } + + if(context->SecurityAttributes != NULL) + { + SlNetSock_secAttribDelete(context->SecurityAttributes); + } + + return false; } -__nfweak bool SSL_AddCertificateAuthority( int sslContextHandle, const char* certificate, int certLength, const char* certPassword ) +bool ssl_exit_context_internal(int sslContextHandle) { - (void)sslContextHandle; (void)certificate; (void)certLength; (void)certPassword; - NATIVE_PROFILE_PAL_COM(); - return TRUE; -} + SlSSL_Context* context = NULL; -__nfweak bool SSL_ExitContext( int sslContextHandle ) -{ - (void)sslContextHandle; - NATIVE_PROFILE_PAL_COM(); - return TRUE; -} + // Check sslContextHandle range + if((sslContextHandle >= (int)ARRAYSIZE(g_SSL_Driver.m_sslContextArray)) || (sslContextHandle < 0) || (g_SSL_Driver.m_sslContextArray[sslContextHandle].SslContext == NULL)) + { + return false; + } -__nfweak int SSL_Accept( SOCK_SOCKET socket, int sslContextHandle ) -{ - (void)socket; (void)sslContextHandle; - NATIVE_PROFILE_PAL_COM(); - return 0; -} + context = (SlSSL_Context*)g_SSL_Driver.m_sslContextArray[sslContextHandle].SslContext; + if (context == NULL) + { + return false; + } -__nfweak int SSL_Connect( SOCK_SOCKET socket, const char* szTargetHost, int sslContextHandle ) -{ - (void)socket; (void)szTargetHost; (void)sslContextHandle; - NATIVE_PROFILE_PAL_COM(); - return 0; -} + SlNetSock_secAttribDelete(context->SecurityAttributes); + + platform_free(context); -__nfweak int SSL_Write( SOCK_SOCKET socket, const char* Data, size_t size ) -{ - (void)socket; (void)Data; (void)size; - NATIVE_PROFILE_PAL_COM(); - return 0; + memset(&g_SSL_Driver.m_sslContextArray[sslContextHandle], 0, sizeof(g_SSL_Driver.m_sslContextArray[sslContextHandle])); + + g_SSL_Driver.m_sslContextCount --; + + return true; } -__nfweak int SSL_Read( SOCK_SOCKET socket, char* Data, size_t size ) -{ - (void)socket; (void)Data; (void)size; - NATIVE_PROFILE_PAL_COM(); - return 0; +int ssl_connect_internal(int sd, const char* szTargetHost, int sslContextHandle) +{ + SlSSL_Context* context; + int32_t status; + int nonblock = 0; + int32_t dummyVar; + nFSlSocketAsyncEvent_t handShakeResult; + struct timespec ts; + + // Check sslContextHandle range + if((sslContextHandle >= (int)ARRAYSIZE(g_SSL_Driver.m_sslContextArray)) || (sslContextHandle < 0)) + { + return SOCK_SOCKET_ERROR; + } + + // Retrieve SSL context from g_SSL_Driver + // sd should already have been created + // Now do the SSL negotiation + context = (SlSSL_Context*)g_SSL_Driver.m_sslContextArray[sslContextHandle].SslContext; + if (context == NULL) + { + return SOCK_SOCKET_ERROR; + } + + // set socket in network context + context->SocketFd = sd; + + if(szTargetHost != NULL && szTargetHost[0] != 0) + { + status = SlNetSock_secAttribSet(context->SecurityAttributes, SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME, (void *)szTargetHost, hal_strlen_s(szTargetHost)); + if (status < 0) + { + // hostname_failed + return status; + } + } + + // setup socket for blocking operation + SOCK_ioctl(sd, SOCK_FIONBIO, &nonblock); + + // start security context on socket + status = SlNetSock_startSec(context->SocketFd, context->SecurityAttributes, context->IsServer ? + (SLNETSOCK_SEC_BIND_CONTEXT_ONLY | SLNETSOCK_SEC_IS_SERVER) : + (SLNETSOCK_SEC_BIND_CONTEXT_ONLY)); + if (status < 0) + { + return status; + } + + // perform SSL handshake + sl_SetSockOpt(context->SocketFd, SL_SOL_SOCKET, SL_SO_STARTTLS, &dummyVar, sizeof(dummyVar)); + + // wait 2 seconds for TLS handshake to complete + // TODO: evaluate this to use CLR events + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_sec += 2; + + while(true) + { + if(mq_timedreceive(nF_ControlBlock.socketAsyncEvent, + (char*)&handShakeResult, sizeof(nFSlSocketAsyncEvent_t), NULL, &ts) < 0) + { + // timeout occurred without receiving any message + return SOCK_SOCKET_ERROR; + } + else + { + // this event matches the socket we are waiting for + if(handShakeResult.Sd == sd) + { + break; + } + } + } + + // setup socket to non blocking operation + nonblock = 1; + SOCK_ioctl(sd, SOCK_FIONBIO, &nonblock); + + // go here, handshake is completed + // return handshake operation result + status = (handShakeResult.Type == SL_SSL_NOTIFICATION_CONNECTED_SECURED) ? 0 : SOCK_SOCKET_ERROR; + + return status; } -__nfweak int SSL_CloseSocket( SOCK_SOCKET socket ) +int ssl_pending_internal( int sd ) { - (void)socket; - NATIVE_PROFILE_PAL_COM(); + // Simple Link doesn't have an API to check for pending data + // just return 0 return 0; } -__nfweak void SSL_GetTime(DATE_TIME_INFO* pdt) +int ssl_write_internal( int sd, const char* data, size_t req_len) { - (void)pdt; - NATIVE_PROFILE_PAL_COM(); + int32_t status; + + socketErrorCode = SlNetSock_send(sd, (const void*)data, req_len, 0); + + // anything bellow 0 is considered an error, so we have to report that no bytes were sent + if (socketErrorCode < 0) + { + return 0; + } + + return req_len; } -__nfweak void SSL_RegisterTimeCallback(SSL_DATE_TIME_FUNC pfn) +int ssl_read_internal( int sd, char* data, size_t size ) { - (void)pfn; - NATIVE_PROFILE_PAL_COM(); + socketErrorCode = SlNetSock_recv(sd, (unsigned char *)(data), size, 0); + + return socketErrorCode; } -__nfweak bool SSL_ParseCertificate( const char* certificate, size_t certLength, const char* password, X509CertData* certData ) +int ssl_closesocket_internal( int sd ) { - (void)certificate; (void)certLength; (void)password; (void)certData; + // Simple Link takes care of everything for us, just call close socket + SOCK_close( sd ); - NATIVE_PROFILE_PAL_COM(); - return TRUE; + return 0; } -__nfweak int SSL_DataAvailable( SOCK_SOCKET socket ) +bool ssl_uninitialize_internal() { - (void)socket; - NATIVE_PROFILE_PAL_COM(); - return 0; + for(uint32_t i = 0; i #include +// externals from Simple Link sockets +extern void Status_callback(); +extern void Link_callback(bool linkUp); + extern void * CLRStartupThread(void *arg0); extern void * ReceiverThread(void *arg0); extern void sntp_init(void); @@ -116,6 +120,8 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) // nF_ControlBlock.connectionBSSID[5]); sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + + Link_callback(true); } break; @@ -166,6 +172,8 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) // sizeof(nF_ControlBlock.connectionSSID)); // memset(nF_ControlBlock.connectionBSSID, 0, // sizeof(nF_ControlBlock.connectionBSSID)); + + Link_callback(false); } break; @@ -496,6 +504,8 @@ void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,0)); sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + + Status_callback(); } break; @@ -516,6 +526,8 @@ void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) } sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + + Status_callback(); } break; @@ -672,58 +684,65 @@ void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) { if(SL_SOCKET_ASYNC_EVENT == pSock->Event) { - //UART_PRINT("[SOCK ERROR] an event received on socket %d\r\n", - // pSock->SocketAsyncEvent.SockAsyncData.Sd); - switch(pSock->SocketAsyncEvent.SockAsyncData.Type) - { - case SL_SSL_NOTIFICATION_CONNECTED_SECURED: - //UART_PRINT("[SOCK ERROR] SSL handshake done"); - break; - case SL_SSL_NOTIFICATION_HANDSHAKE_FAILED: - //UART_PRINT("[SOCK ERROR] SSL handshake failed with error %d\r\n", - // pSock->SocketAsyncEvent.SockAsyncData.Val); - break; - case SL_SSL_ACCEPT: - //UART_PRINT( - // "[SOCK ERROR] Recoverable error occurred " - // "during the handshake %d\r\n", - // pSock->SocketAsyncEvent.SockAsyncData.Val); - break; - case SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED: - //UART_PRINT("[SOCK ERROR] Other peer terminated the SSL layer.\r\n"); - break; - case SL_SSL_NOTIFICATION_WRONG_ROOT_CA: - //UART_PRINT("[SOCK ERROR] Used wrong CA to verify the peer.\r\n"); + nFSlSocketAsyncEvent_t event; + event.Sd = pSock->SocketAsyncEvent.SockAsyncData.Sd; + event.Type = pSock->SocketAsyncEvent.SockAsyncData.Type; - break; - default: - break; - } + mq_send(nF_ControlBlock.socketAsyncEvent, + (char *)&event, sizeof(nFSlSocketAsyncEvent_t), 0); + + // //UART_PRINT("[SOCK ERROR] an event received on socket %d\r\n", + // // pSock->SocketAsyncEvent.SockAsyncData.Sd); + //switch(pSock->SocketAsyncEvent.SockAsyncData.Type) + // { + // case SL_SSL_NOTIFICATION_CONNECTED_SECURED: + // //UART_PRINT("[SOCK ERROR] SSL handshake done"); + // break; + // case SL_SSL_NOTIFICATION_HANDSHAKE_FAILED: + // //UART_PRINT("[SOCK ERROR] SSL handshake failed with error %d\r\n", + // // pSock->SocketAsyncEvent.SockAsyncData.Val); + // break; + // case SL_SSL_ACCEPT: + // //UART_PRINT( + // // "[SOCK ERROR] Recoverable error occurred " + // // "during the handshake %d\r\n", + // // pSock->SocketAsyncEvent.SockAsyncData.Val); + // break; + // case SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED: + // //UART_PRINT("[SOCK ERROR] Other peer terminated the SSL layer.\r\n"); + // break; + // case SL_SSL_NOTIFICATION_WRONG_ROOT_CA: + // //UART_PRINT("[SOCK ERROR] Used wrong CA to verify the peer.\r\n"); + + // break; + // default: + // break; + // } } // This application doesn't work w/ socket - Events are not expected switch(pSock->Event) { - case SL_SOCKET_TX_FAILED_EVENT: - switch(pSock->SocketAsyncEvent.SockTxFailData.Status) - { - case SL_ERROR_BSD_ECLOSE: - //UART_PRINT("[SOCK ERROR] - close socket (%d) operation " - // "failed to transmit all queued packets\n\r", - // pSock->SocketAsyncEvent.SockTxFailData.Sd); + case SL_SOCKET_TX_FAILED_EVENT: + switch(pSock->SocketAsyncEvent.SockTxFailData.Status) + { + case SL_ERROR_BSD_ECLOSE: + //UART_PRINT("[SOCK ERROR] - close socket (%d) operation " + // "failed to transmit all queued packets\n\r", + // pSock->SocketAsyncEvent.SockTxFailData.Sd); + break; + default: + //UART_PRINT("[SOCK ERROR] - TX FAILED : socket %d , " + // "reason (%d) \n\n", + // pSock->SocketAsyncEvent.SockTxFailData.Sd, + // pSock->SocketAsyncEvent.SockTxFailData.Status); + break; + } break; + default: - //UART_PRINT("[SOCK ERROR] - TX FAILED : socket %d , " - // "reason (%d) \n\n", - // pSock->SocketAsyncEvent.SockTxFailData.Sd, - // pSock->SocketAsyncEvent.SockTxFailData.Status); + //UART_PRINT("[SOCK EVENT] - Unexpected Event [%x0x]\n\n",pSock->Event); break; - } - break; - - default: - //UART_PRINT("[SOCK EVENT] - Unexpected Event [%x0x]\n\n",pSock->Event); - break; } } @@ -783,6 +802,11 @@ void * mainThread(void *arg) nF_ControlBlock.configurationDone = 0; nF_ControlBlock.tcpConnected = 0; + // Create sockets Async event queue + mq_attr attr; + attr.mq_maxmsg = SLNETSOCK_MAX_CONCURRENT_SOCKETS; + attr.mq_msgsize = sizeof(nFSlSocketAsyncEvent_t); + nF_ControlBlock.socketAsyncEvent = mq_open("", O_CREAT, 0, &attr); // initializes signals for all tasks sem_init(&Provisioning_ControlBlock.connectionAsyncEvent, 0, 0); From 241a5b5b182cdd9e78befe2edd0a55c4142cba83 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 25 Mar 2019 18:18:20 +0000 Subject: [PATCH 71/90] Work on configuration manager to store CA root certificate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../targetHAL_ConfigurationManager_CC32xx.cpp | 41 ++++++++++--------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp index 440d5d5ef1..bf54a5d1b6 100644 --- a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -361,14 +361,11 @@ uint8_t GetSecurityType(AuthenticationType authentication) } } -// Stores the configuration block to the configuration flash sector -// NOTE: because inserting or removing a configuration block it's very 'RAM expensive' we choose not to support those operations -// the host debugger will have to be used to manage these operations on the device configuration collection +// Stores the configuration block to the file system bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex, uint32_t blockSize, uint32_t offset) { - // ByteAddress storageAddress = 0; - // bool requiresEnumeration = FALSE; - bool success = FALSE; + bool requiresEnumeration = false; + bool success = false; unsigned char* fileName = NULL; @@ -415,7 +412,8 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi else { // configuration stored - success = TRUE; + success = true; + requiresEnumeration = true; } } } @@ -443,8 +441,14 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi // done success = true; + requiresEnumeration = true; + } + else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + { + // CA root certificate bundle is stored as a file /sys/certstore.lst + // currently we don't support updating this + success = false; } - // if(configuration == DeviceConfigurationOption_Network) // { @@ -524,19 +528,16 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi // } // } - // // copy the config block content to the config block storage - // success = STM32FlashDriver_Write(NULL, storageAddress, blockSize, (unsigned char*)configurationBlock, true); - - // if(success == TRUE && requiresEnumeration) - // { - // // free the current allocation(s) - // platform_free(g_TargetConfiguration.NetworkInterfaceConfigs); - // platform_free(g_TargetConfiguration.Wireless80211Configs); - // platform_free(g_TargetConfiguration.CertificateStore); + if(success == true && requiresEnumeration) + { + // free the current allocation(s) + platform_free(g_TargetConfiguration.NetworkInterfaceConfigs); + platform_free(g_TargetConfiguration.Wireless80211Configs); + platform_free(g_TargetConfiguration.CertificateStore); - // // perform enumeration of configuration blocks - // ConfigurationManager_EnumerateConfigurationBlocks(); - // } + // perform enumeration of configuration blocks + ConfigurationManager_EnumerateConfigurationBlocks(); + } return success; } From d233eda6c50fb73a476128e4568cea05551206b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 25 Mar 2019 18:36:05 +0000 Subject: [PATCH 72/90] Major code clean-up in main thread MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../Include/targetSimpleLinkCC32xx_Threads.h | 3 - .../nanoCLR/targetSimpleLinkCC32xx_Threads.c | 737 +++++++----------- 2 files changed, 291 insertions(+), 449 deletions(-) diff --git a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h index 12f92a8130..f4e8b9ae37 100644 --- a/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h +++ b/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h @@ -110,10 +110,7 @@ typedef struct nanoFramework_ControlBlock_t // This field keeps the device's role (STA, P2P or AP) uint32_t Role; - int16_t socket; - int16_t sockTcpServer; uint8_t configurationDone; - uint8_t tcpConnected; mqd_t socketAsyncEvent; diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index d8bbe691cd..3e7fc4150d 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -80,86 +80,36 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) { switch(pWlanEvent->Id) { - case SL_WLAN_EVENT_CONNECT: - { - SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); - CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6lAcquired); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6gAcquired); - - // Information about the connected AP (like name, MAC etc) will be - // available in 'slWlanConnectAsyncResponse_t'-Applications - // can use it if required: - - // slWlanConnectAsyncResponse_t *pEventData = NULL; - // pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected; - - - // Copy new connection SSID and BSSID to global parameters - // memcpy(nF_ControlBlock.connectionSSID, - // pWlanEvent->Data.Connect.SsidName, - // pWlanEvent->Data.Connect.SsidLen); - - // nF_ControlBlock.ssidLen = pWlanEvent->Data.Connect.SsidLen; - - // memcpy(nF_ControlBlock.connectionBSSID, - // pWlanEvent->Data.Connect.Bssid, - // SL_WLAN_BSSID_LENGTH); - - //UART_PRINT( - // "[WLAN EVENT] STA Connected to the AP: %s ," - // "BSSID: %x:%x:%x:%x:%x:%x\n\r", - // nF_ControlBlock.connectionSSID, - // nF_ControlBlock.connectionBSSID[0], - // nF_ControlBlock.connectionBSSID[1], - // nF_ControlBlock.connectionBSSID[2], - // nF_ControlBlock.connectionBSSID[3], - // nF_ControlBlock.connectionBSSID[4], - // nF_ControlBlock.connectionBSSID[5]); - - sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); - - Link_callback(true); - } - break; + case SL_WLAN_EVENT_CONNECT: + { + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); - case SL_WLAN_EVENT_DISCONNECT: - { - SlWlanEventDisconnect_t* pEventData = NULL; + // Information about the connected AP (like name, MAC etc) will be + // available in 'slWlanConnectAsyncResponse_t'-Applications + // can use it if required: - CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); - CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6lAcquired); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6gAcquired); + // slWlanConnectAsyncResponse_t *pEventData = NULL; + // pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected; + + // Copy new connection SSID and BSSID to global parameters + // memcpy(nF_ControlBlock.connectionSSID, + // pWlanEvent->Data.Connect.SsidName, + // pWlanEvent->Data.Connect.SsidLen); - pEventData = &pWlanEvent->Data.Disconnect; + // nF_ControlBlock.ssidLen = pWlanEvent->Data.Connect.SsidLen; + + // memcpy(nF_ControlBlock.connectionBSSID, + // pWlanEvent->Data.Connect.Bssid, + // SL_WLAN_BSSID_LENGTH); - // If the user has initiated 'Disconnect' request, - // 'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED. - - if(SL_WLAN_DISCONNECT_USER_INITIATED == pEventData->ReasonCode) - { - //UART_PRINT( - // "[WLAN EVENT]Device disconnected from the " - // "AP: %s, BSSID: %x:%x:%x:%x:%x:%x " - // "on application's request \n\r", - // nF_ControlBlock.connectionSSID, - // nF_ControlBlock.connectionBSSID[0], - // nF_ControlBlock.connectionBSSID[1], - // nF_ControlBlock.connectionBSSID[2], - // nF_ControlBlock.connectionBSSID[3], - // nF_ControlBlock.connectionBSSID[4], - // nF_ControlBlock.connectionBSSID[5]); - } - else - { //UART_PRINT( - // "[WLAN ERROR]Device disconnected from the AP AP: %s," - // "BSSID: %x:%x:%x:%x:%x:%x on an ERROR..!! \n\r", + // "[WLAN EVENT] STA Connected to the AP: %s ," + // "BSSID: %x:%x:%x:%x:%x:%x\n\r", // nF_ControlBlock.connectionSSID, // nF_ControlBlock.connectionBSSID[0], // nF_ControlBlock.connectionBSSID[1], @@ -167,224 +117,210 @@ void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) // nF_ControlBlock.connectionBSSID[3], // nF_ControlBlock.connectionBSSID[4], // nF_ControlBlock.connectionBSSID[5]); - } - // memset(nF_ControlBlock.connectionSSID, 0, - // sizeof(nF_ControlBlock.connectionSSID)); - // memset(nF_ControlBlock.connectionBSSID, 0, - // sizeof(nF_ControlBlock.connectionBSSID)); - Link_callback(false); - } - break; - - case SL_WLAN_EVENT_STA_ADDED: - { - //UART_PRINT( - // "[WLAN EVENT] External Station connected to SimpleLink AP\r\n"); - - //UART_PRINT("[WLAN EVENT] STA BSSID: %02x:%02x:%02x:%02x:%02x:%02x\r\n", - // pWlanEvent->Data.STAAdded.Mac[0], - // pWlanEvent->Data.STAAdded.Mac[1], - // pWlanEvent->Data.STAAdded.Mac[2], - // pWlanEvent->Data.STAAdded.Mac[3], - // pWlanEvent->Data.STAAdded.Mac[4], - // pWlanEvent->Data.STAAdded.Mac[5]); - } - break; + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); - case SL_WLAN_EVENT_STA_REMOVED: - { - //UART_PRINT( - // "[WLAN EVENT] External Station disconnected from SimpleLink AP\r\n"); - } - break; - - case SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED: - { - //UART_PRINT("[WLAN EVENT] Profile Added\r\n"); - } - break; - - case SL_WLAN_EVENT_PROVISIONING_STATUS: - { - uint16_t Status = - pWlanEvent->Data.ProvisioningStatus.ProvisioningStatus; - switch(Status) - { - case SL_WLAN_PROVISIONING_GENERAL_ERROR: - case SL_WLAN_PROVISIONING_ERROR_ABORT: - { - //UART_PRINT("[WLAN EVENT] Provisioning Error Status=%d\r\n",Status); - // SignalProvisioningEvent(PrvnEvent_Error); - } - break; - case SL_WLAN_PROVISIONING_ERROR_ABORT_INVALID_PARAM: - case SL_WLAN_PROVISIONING_ERROR_ABORT_HTTP_SERVER_DISABLED: - case SL_WLAN_PROVISIONING_ERROR_ABORT_PROFILE_LIST_FULL: - { - //UART_PRINT("[WLAN EVENT] Provisioning Error Status=%d\r\n",Status); - // SignalProvisioningEvent(PrvnEvent_StartFailed); - } - break; - case SL_WLAN_PROVISIONING_ERROR_ABORT_PROVISIONING_ALREADY_STARTED: - { - //UART_PRINT("[WLAN EVENT] Provisioning already started"); + Link_callback(true); } break; - case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_NETWORK_NOT_FOUND: + case SL_WLAN_EVENT_DISCONNECT: { - //UART_PRINT("[WLAN EVENT] Confirmation fail: network not found\r\n"); - // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); - } - break; + SlWlanEventDisconnect_t* pEventData = NULL; - case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_CONNECTION_FAILED: - { - //UART_PRINT("[WLAN EVENT] Confirmation fail: Connection failed\r\n"); - // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); - } - break; + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); - case - SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_CONNECTION_SUCCESS_IP_NOT_ACQUIRED - : - { - //UART_PRINT( - // "[WLAN EVENT] Confirmation fail: IP address not acquired\r\n"); - // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + pEventData = &pWlanEvent->Data.Disconnect; + + // If the user has initiated 'Disconnect' request, + // 'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED. + + if(SL_WLAN_DISCONNECT_USER_INITIATED == pEventData->ReasonCode) + { + } + else + { + } + // memset(nF_ControlBlock.connectionSSID, 0, + // sizeof(nF_ControlBlock.connectionSSID)); + // memset(nF_ControlBlock.connectionBSSID, 0, + // sizeof(nF_ControlBlock.connectionBSSID)); + + Link_callback(false); } break; - case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS_FEEDBACK_FAILED: + case SL_WLAN_EVENT_STA_ADDED: { - //UART_PRINT( - // "[WLAN EVENT] Connection Success " - // "(feedback to Smartphone app failed)\r\n"); - // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); } break; - case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS: + case SL_WLAN_EVENT_STA_REMOVED: { - //UART_PRINT("[WLAN EVENT] Confirmation Success!\r\n"); - // SignalProvisioningEvent(PrvnEvent_ConfirmationSuccess); } break; - case SL_WLAN_PROVISIONING_AUTO_STARTED: + case SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED: { - //UART_PRINT("[WLAN EVENT] Auto-Provisioning Started\r\n"); - // stop auto provisioning - - // may trigger in case of returning to default - // SignalProvisioningEvent(PrvnEvent_Stopped); } break; - case SL_WLAN_PROVISIONING_STOPPED: + case SL_WLAN_EVENT_PROVISIONING_STATUS: { - //UART_PRINT("[WLAN EVENT] Provisioning stopped\r\n"); - if(ROLE_STA == pWlanEvent->Data.ProvisioningStatus.Role) + uint16_t Status = + pWlanEvent->Data.ProvisioningStatus.ProvisioningStatus; + switch(Status) { - //UART_PRINT(" [WLAN EVENT] - WLAN Connection Status:%d\r\n", - // pWlanEvent->Data.ProvisioningStatus.WlanStatus); + case SL_WLAN_PROVISIONING_GENERAL_ERROR: + case SL_WLAN_PROVISIONING_ERROR_ABORT: + { + // SignalProvisioningEvent(PrvnEvent_Error); + } + break; - if(SL_WLAN_STATUS_CONNECTED == - pWlanEvent->Data.ProvisioningStatus.WlanStatus) + case SL_WLAN_PROVISIONING_ERROR_ABORT_INVALID_PARAM: + case SL_WLAN_PROVISIONING_ERROR_ABORT_HTTP_SERVER_DISABLED: + case SL_WLAN_PROVISIONING_ERROR_ABORT_PROFILE_LIST_FULL: { - //UART_PRINT(" [WLAN EVENT] - Connected to SSID:%s\r\n", - // pWlanEvent->Data.ProvisioningStatus.Ssid); + // SignalProvisioningEvent(PrvnEvent_StartFailed); + } + break; - // memcpy (nF_ControlBlock.connectionSSID, - // pWlanEvent->Data.ProvisioningStatus.Ssid, - // pWlanEvent->Data.ProvisioningStatus.Ssidlen); - // nF_ControlBlock.ssidLen = - // pWlanEvent->Data.ProvisioningStatus.Ssidlen; + case SL_WLAN_PROVISIONING_ERROR_ABORT_PROVISIONING_ALREADY_STARTED: + { - // Provisioning is stopped by the device and - // provisioning is done successfully - // SignalProvisioningEvent(PrvnEvent_Stopped); + } + break; - break; + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_NETWORK_NOT_FOUND: + { + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); } - else + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_CONNECTION_FAILED: { - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Connection); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_IpAcquired); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6lAcquired); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6gAcquired); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; - // Provisioning is stopped by the device and provisioning - // is not done yet, still need to connect to AP - // SignalProvisioningEvent(PrvnEvent_WaitForConn); + case + SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_CONNECTION_SUCCESS_IP_NOT_ACQUIRED + : + { + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; - break; + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS_FEEDBACK_FAILED: + { + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); } - } - } + break; - // SignalProvisioningEvent(PrvnEvent_Stopped); + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS: + { + // SignalProvisioningEvent(PrvnEvent_ConfirmationSuccess); + } + break; - break; + case SL_WLAN_PROVISIONING_AUTO_STARTED: + { + // stop auto provisioning - + // may trigger in case of returning to default + // SignalProvisioningEvent(PrvnEvent_Stopped); + } + break; - case SL_WLAN_PROVISIONING_SMART_CONFIG_SYNCED: - { - //UART_PRINT("[WLAN EVENT] Smart Config Synced!\r\n"); - } - break; + case SL_WLAN_PROVISIONING_STOPPED: + { + if(ROLE_STA == pWlanEvent->Data.ProvisioningStatus.Role) + { + if(SL_WLAN_STATUS_CONNECTED == + pWlanEvent->Data.ProvisioningStatus.WlanStatus) + { + // memcpy (nF_ControlBlock.connectionSSID, + // pWlanEvent->Data.ProvisioningStatus.Ssid, + // pWlanEvent->Data.ProvisioningStatus.Ssidlen); + // nF_ControlBlock.ssidLen = + // pWlanEvent->Data.ProvisioningStatus.Ssidlen; + + // Provisioning is stopped by the device and + // provisioning is done successfully + // SignalProvisioningEvent(PrvnEvent_Stopped); + + break; + } + else + { + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); + + // Provisioning is stopped by the device and provisioning + // is not done yet, still need to connect to AP + // SignalProvisioningEvent(PrvnEvent_WaitForConn); + + break; + } + } + } + // SignalProvisioningEvent(PrvnEvent_Stopped); + break; - case SL_WLAN_PROVISIONING_CONFIRMATION_WLAN_CONNECT: - { - SET_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Connection); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_IpAcquired); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6lAcquired); - CLR_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6gAcquired); + case SL_WLAN_PROVISIONING_SMART_CONFIG_SYNCED: + { + } + break; - //UART_PRINT("[WLAN EVENT] Connection to AP succeeded\r\n"); - } - break; + case SL_WLAN_PROVISIONING_CONFIRMATION_WLAN_CONNECT: + { + SET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); + } + break; - case SL_WLAN_PROVISIONING_CONFIRMATION_IP_ACQUIRED: - { - SET_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_IpAcquired); + case SL_WLAN_PROVISIONING_CONFIRMATION_IP_ACQUIRED: + { + SET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_IpAcquired); + } + break; - //UART_PRINT("[WLAN EVENT] IP address acquired\r\n"); - } - break; + case SL_WLAN_PROVISIONING_SMART_CONFIG_SYNC_TIMEOUT: + { + } + break; - case SL_WLAN_PROVISIONING_SMART_CONFIG_SYNC_TIMEOUT: - { - //UART_PRINT("[WLAN EVENT] Smart Config Sync timeout\r\n"); + default: + { + } + break; + } } break; default: { - //UART_PRINT("[WLAN EVENT] Unknown Provisioning Status: %d\r\n", - // pWlanEvent->Data.ProvisioningStatus.ProvisioningStatus); + // SignalProvisioningEvent(PrvnEvent_Error); } break; - } - } - break; - - default: - { - //UART_PRINT("[WLAN EVENT] Unexpected event [0x%x]\n\r", - // pWlanEvent->Id); - - // SignalProvisioningEvent(PrvnEvent_Error); - } - break; } } @@ -404,46 +340,33 @@ void SimpleLinkFatalErrorEventHandler(SlDeviceFatal_t *slFatalErrorEvent) switch(slFatalErrorEvent->Id) { - case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: - { - //UART_PRINT("[ERROR] - FATAL ERROR: Abort NWP event detected: " - // "AbortType=%d, AbortData=0x%x\n\r", - // slFatalErrorEvent->Data.DeviceAssert.Code, - // slFatalErrorEvent->Data.DeviceAssert.Value); - } - break; - - case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: - { - //UART_PRINT("[ERROR] - FATAL ERROR: Driver Abort detected. \n\r"); - } - break; + case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: + { + } + break; - case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: - { - //UART_PRINT("[ERROR] - FATAL ERROR: No Cmd Ack detected " - // "[cmd opcode = 0x%x] \n\r", - // slFatalErrorEvent->Data.NoCmdAck.Code); - } - break; + case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: + { + } + break; - case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: - { - //UART_PRINT("[ERROR] - FATAL ERROR: Sync loss detected n\r"); - } - break; + case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: + { + } + break; - case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: - { - //UART_PRINT("[ERROR] - FATAL ERROR: Async event timeout detected " - // "[event opcode =0x%x] \n\r", - // slFatalErrorEvent->Data.CmdTimeout.Code); - } - break; + case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: + { + } + break; - default: - //UART_PRINT("[ERROR] - FATAL ERROR: Unspecified error detected \n\r"); + case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: + { + } break; + + default: + break; } // msgqRetVal = mq_send(controlMQueue, (char *)&msg, 1, 0); @@ -480,126 +403,77 @@ void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) switch(pNetAppEvent->Id) { - case SL_NETAPP_EVENT_IPV4_ACQUIRED: - { - SlIpV4AcquiredAsync_t *pEventData = NULL; - - SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); - - // Ip Acquired Event Data - pEventData = &pNetAppEvent->Data.IpAcquiredV4; + case SL_NETAPP_EVENT_IPV4_ACQUIRED: + { + SlIpV4AcquiredAsync_t *pEventData = NULL; - // Gateway IP address - // nF_ControlBlock.gatewayIP = pEventData->Gateway; + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); - //UART_PRINT("[NETAPP EVENT] IP Acquired: IP=%d.%d.%d.%d , " - // "Gateway=%d.%d.%d.%d\n\r", - // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Ip,3), - // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Ip,2), - // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Ip,1), - // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Ip,0), - // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,3), - // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,2), - // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,1), - // SL_IPV4_BYTE(pNetAppEvent->Data.IpAcquiredV4.Gateway,0)); + // Ip Acquired Event Data + pEventData = &pNetAppEvent->Data.IpAcquiredV4; - sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + // Gateway IP address + // nF_ControlBlock.gatewayIP = pEventData->Gateway; - Status_callback(); - } - break; + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); - case SL_NETAPP_EVENT_IPV6_ACQUIRED: - { - if(!GET_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6lAcquired)) - { - SET_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6lAcquired); - //UART_PRINT("[NETAPP EVENT] Local IPv6 Acquired\n\r"); + Status_callback(); } - else + break; + + case SL_NETAPP_EVENT_IPV6_ACQUIRED: { - SET_STATUS_BIT(nF_ControlBlock.Status, - AppStatusBits_Ipv6gAcquired); - //UART_PRINT("[NETAPP EVENT] Global IPv6 Acquired\n\r"); - } + if(!GET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired)) + { + SET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + } + else + { + SET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); + } - sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); - Status_callback(); - } - break; + Status_callback(); + } + break; - case SL_NETAPP_EVENT_DHCPV4_LEASED: - { - SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased); - - //UART_PRINT( - // "[NETAPP EVENT] IPv4 leased %d.%d.%d.%d for " - // "device %02x:%02x:%02x:%02x:%02x:%02x\n\r", \ - // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpLeased.IpAddress,3), \ - // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpLeased.IpAddress,2), \ - // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpLeased.IpAddress,1), \ - // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpLeased.IpAddress,0), \ - // pNetAppEventData->IpLeased.Mac[0], \ - // pNetAppEventData->IpLeased.Mac[1], \ - // pNetAppEventData->IpLeased.Mac[2], \ - // pNetAppEventData->IpLeased.Mac[3], \ - // pNetAppEventData->IpLeased.Mac[4], \ - // pNetAppEventData->IpLeased.Mac[5]); - } - break; + case SL_NETAPP_EVENT_DHCPV4_LEASED: + { + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased); + } + break; - case SL_NETAPP_EVENT_DHCPV4_RELEASED: - { - CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased); - - //UART_PRINT( - // "[NETAPP EVENT] IPv4 released %d.%d.%d.%d for " - // "device %02x:%02x:%02x:%02x:%02x:%02x\n\r", \ - // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpReleased.IpAddress, - // 3), \ - // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpReleased.IpAddress, - // 2), \ - // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpReleased.IpAddress, - // 1), \ - // (uint8_t)SL_IPV4_BYTE(pNetAppEventData->IpReleased.IpAddress, - // 0), \ - // pNetAppEventData->IpReleased.Mac[0], \ - // pNetAppEventData->IpReleased.Mac[1], \ - // pNetAppEventData->IpReleased.Mac[2], \ - // pNetAppEventData->IpReleased.Mac[3], \ - // pNetAppEventData->IpReleased.Mac[4], \ - // pNetAppEventData->IpReleased.Mac[5]); - - //UART_PRINT("Reason: "); - switch(pNetAppEventData->IpReleased.Reason) + case SL_NETAPP_EVENT_DHCPV4_RELEASED: { - case SL_IP_LEASE_PEER_RELEASE: //UART_PRINT("Peer released\n\r"); - break; + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased); - case SL_IP_LEASE_PEER_DECLINE: //UART_PRINT("Peer declined\n\r"); - break; + switch(pNetAppEventData->IpReleased.Reason) + { + case SL_IP_LEASE_PEER_RELEASE: + break; - case SL_IP_LEASE_EXPIRED: //UART_PRINT("Lease expired\n\r"); - break; + case SL_IP_LEASE_PEER_DECLINE: + break; + + case SL_IP_LEASE_EXPIRED: + break; + } } - } - break; + break; - case SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT: - { - //UART_PRINT("[NETAPP EVENT] DHCP IPv4 Acquire timeout\n\r"); - } - break; + case SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT: + { + } + break; - default: - { - //UART_PRINT("[NETAPP EVENT] Unexpected event [0x%x] \n\r", - // pNetAppEvent->Id); - } - break; + default: + { + } + break; } } @@ -619,7 +493,6 @@ void SimpleLinkHttpServerEventHandler(SlNetAppHttpServerEvent_t *pHttpEvent, pHttpResponse) { // Unused in this application - //UART_PRINT("[HTTP SERVER EVENT] Unexpected HTTP server event \n\r"); } //***************************************************************************** @@ -645,29 +518,24 @@ void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent) } switch(pDevEvent->Id) { - case SL_DEVICE_EVENT_RESET_REQUEST: - { - //UART_PRINT("[GENERAL EVENT] Reset Request Event\r\n"); - } - break; - - default: - { - //UART_PRINT("[GENERAL EVENT] - ID=[%d] Sender=[%d]\n\n", - // pDevEvent->Data.Error.Code, - // pDevEvent->Data.Error.Source); + case SL_DEVICE_EVENT_RESET_REQUEST: + { + } + break; - // msgqRetVal = mq_send(controlMQueue, (char *)&msg, 1, 0); - // if(msgqRetVal < 0) - // { - // //UART_PRINT("[Control task] could not send element to msg queue\n\r"); - // while(1) - // { - // ; - // } - // } - } - break; + default: + { + // msgqRetVal = mq_send(controlMQueue, (char *)&msg, 1, 0); + // if(msgqRetVal < 0) + // { + // //UART_PRINT("[Control task] could not send element to msg queue\n\r"); + // while(1) + // { + // ; + // } + // } + } + break; } } @@ -691,33 +559,21 @@ void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) mq_send(nF_ControlBlock.socketAsyncEvent, (char *)&event, sizeof(nFSlSocketAsyncEvent_t), 0); - // //UART_PRINT("[SOCK ERROR] an event received on socket %d\r\n", - // // pSock->SocketAsyncEvent.SockAsyncData.Sd); - //switch(pSock->SocketAsyncEvent.SockAsyncData.Type) - // { - // case SL_SSL_NOTIFICATION_CONNECTED_SECURED: - // //UART_PRINT("[SOCK ERROR] SSL handshake done"); - // break; - // case SL_SSL_NOTIFICATION_HANDSHAKE_FAILED: - // //UART_PRINT("[SOCK ERROR] SSL handshake failed with error %d\r\n", - // // pSock->SocketAsyncEvent.SockAsyncData.Val); - // break; - // case SL_SSL_ACCEPT: - // //UART_PRINT( - // // "[SOCK ERROR] Recoverable error occurred " - // // "during the handshake %d\r\n", - // // pSock->SocketAsyncEvent.SockAsyncData.Val); - // break; - // case SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED: - // //UART_PRINT("[SOCK ERROR] Other peer terminated the SSL layer.\r\n"); - // break; - // case SL_SSL_NOTIFICATION_WRONG_ROOT_CA: - // //UART_PRINT("[SOCK ERROR] Used wrong CA to verify the peer.\r\n"); - - // break; - // default: - // break; - // } + switch(pSock->SocketAsyncEvent.SockAsyncData.Type) + { + case SL_SSL_NOTIFICATION_CONNECTED_SECURED: + break; + case SL_SSL_NOTIFICATION_HANDSHAKE_FAILED: + break; + case SL_SSL_ACCEPT: + break; + case SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED: + break; + case SL_SSL_NOTIFICATION_WRONG_ROOT_CA: + break; + default: + break; + } } // This application doesn't work w/ socket - Events are not expected @@ -726,22 +582,14 @@ void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) case SL_SOCKET_TX_FAILED_EVENT: switch(pSock->SocketAsyncEvent.SockTxFailData.Status) { - case SL_ERROR_BSD_ECLOSE: - //UART_PRINT("[SOCK ERROR] - close socket (%d) operation " - // "failed to transmit all queued packets\n\r", - // pSock->SocketAsyncEvent.SockTxFailData.Sd); - break; - default: - //UART_PRINT("[SOCK ERROR] - TX FAILED : socket %d , " - // "reason (%d) \n\n", - // pSock->SocketAsyncEvent.SockTxFailData.Sd, - // pSock->SocketAsyncEvent.SockTxFailData.Status); - break; + case SL_ERROR_BSD_ECLOSE: + break; + default: + break; } break; default: - //UART_PRINT("[SOCK EVENT] - Unexpected Event [%x0x]\n\n",pSock->Event); break; } } @@ -797,10 +645,7 @@ void * mainThread(void *arg) nF_ControlBlock.Status = 0; // reset control block vars - nF_ControlBlock.socket = -1; - nF_ControlBlock.sockTcpServer = -1; nF_ControlBlock.configurationDone = 0; - nF_ControlBlock.tcpConnected = 0; // Create sockets Async event queue mq_attr attr; From 90841fd360b9a3d8c0d13c61888719c17f847886 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 26 Mar 2019 10:46:33 +0000 Subject: [PATCH 73/90] Add code to generate default network config block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../targetHAL_ConfigurationManager_CC32xx.cpp | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp index bf54a5d1b6..22c183274e 100644 --- a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -120,6 +120,21 @@ void ConfigurationManager_EnumerateConfigurationBlocks() // find network configuration blocks HAL_CONFIGURATION_NETWORK* networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManagerCC32xx_FindNetworkConfigurationBlocks(); + // check network configs count + if(networkConfigs->Count == 0) + { + // there is no network config block available, get a default + HAL_Configuration_NetworkInterface* networkConfig = (HAL_Configuration_NetworkInterface*)platform_malloc(sizeof(HAL_Configuration_NetworkInterface)); + InitialiseNetworkDefaultConfig(networkConfig, 0); + + // store it + ConfigurationManager_StoreConfigurationBlock(networkConfig, DeviceConfigurationOption_Network, 0, sizeof(HAL_Configuration_NetworkInterface), 0); + platform_free(networkConfig); + + // have to enumerate again to pick it up + networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManagerCC32xx_FindNetworkConfigurationBlocks(); + } + // find wireless 80211 network configuration blocks HAL_CONFIGURATION_NETWORK_WIRELESS80211* networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)ConfigurationManagerCC32xx_FindNetworkWireless80211ConfigurationBlocks(); From 16b00911645916d2a314dbec520cf9fa5a8a317d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 26 Mar 2019 11:00:30 +0000 Subject: [PATCH 74/90] Implement UpdateConfigurationBlock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Clean-up StoreConfigurationBlock. Signed-off-by: José Simões --- .../targetHAL_ConfigurationManager_CC32xx.cpp | 178 ++---------------- 1 file changed, 12 insertions(+), 166 deletions(-) diff --git a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp index 22c183274e..eca1c8e5e4 100644 --- a/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp +++ b/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -465,84 +465,6 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi success = false; } - // if(configuration == DeviceConfigurationOption_Network) - // { - // if( g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 || - // (configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) - // { - // // there is no room for this block, or there are no blocks stored at all - // // failing the operation - // return FALSE; - // } - - // // set storage address from block address, plus the requested offset - // storageAddress = (ByteAddress)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex] + offset; - - // // set block size, in case it's not already set - // blockSize = sizeof(HAL_Configuration_NetworkInterface); - - // // make sure the config block marker is set - // memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); - - // _ASSERTE(((HAL_Configuration_NetworkInterface*)configurationBlock)->StartupAddressMode > 0); - // } - // else if(configuration == DeviceConfigurationOption_Wireless80211Network) - // { - // if( g_TargetConfiguration.Wireless80211Configs->Count == 0 || - // (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) - // { - // // there is no room for this block, or there are no blocks stored at all - // // failing the operation - // return FALSE; - // } - - // // set storage address from block address, plus the requested offset - // storageAddress = (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex] + offset; - - // // set block size, in case it's not already set - // blockSize = sizeof(HAL_Configuration_Wireless80211); - - // // make sure the config block marker is set - // memcpy(configurationBlock, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); - // } - // else if(configuration == DeviceConfigurationOption_X509CaRootBundle) - // { - // if( g_TargetConfiguration.CertificateStore->Count == 0 || - // (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) - // { - // // there is no room for this block, or there are no blocks stored at all - // // failing the operation - // return FALSE; - // } - - // // set storage address from block address, plus the requested offset - // storageAddress = (ByteAddress)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex] + offset; - - // // set block size, in case it's not already set - // // because X509 certificate has a variable length need to compute the block size in two steps - // blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); - // blockSize += ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize; - - // // make sure the config block marker is set - // memcpy(configurationBlock, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1, sizeof(c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1)); - // } - // else if(configuration == DeviceConfigurationOption_All) - // { - // // particular situation where we are receiving the full configuration block - - // // set storage address as the start of the flash configuration sector, plus the requested offset - // storageAddress = (ByteAddress)&__nanoConfig_start__ + offset; - - // // always enumerate the blocks again after storing it - // requiresEnumeration = TRUE; - - // // for save all the block size has to be provided, check that - // if(blockSize == 0) - // { - // return FALSE; - // } - // } - if(success == true && requiresEnumeration) { // free the current allocation(s) @@ -560,96 +482,20 @@ bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, Devi // Updates a configuration block bool ConfigurationManager_UpdateConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) { - // ByteAddress storageAddress; - // uint32_t blockOffset; - // uint8_t* blockAddressInCopy; - // uint32_t blockSize; - bool success = FALSE; - - // // config sector size - // int sizeOfConfigSector = (uint32_t)&__nanoConfig_end__ - (uint32_t)&__nanoConfig_start__; - - // // allocate memory from CRT heap - // uint8_t* configSectorCopy = (uint8_t*)platform_malloc(sizeOfConfigSector); - - // if(configSectorCopy != NULL) - // { - // // copy config sector from flash to RAM - // memcpy(configSectorCopy, &__nanoConfig_start__, sizeOfConfigSector); - - // // find out the address for the config block to update in the configSectorCopy - // // because we are copying back the config block to flash and just replacing the config block content - // // the addresses in g_TargetConfiguration will remain the same - // // plus we can calculate the offset of the config block from g_TargetConfiguration - // if(configuration == DeviceConfigurationOption_Network) - // { - // // get storage address from block address - // storageAddress = (ByteAddress)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; - - // // set block size, in case it's not already set - // blockSize = sizeof(HAL_Configuration_NetworkInterface); - - // // make sure the config block marker is set - // memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); - - // _ASSERTE(((HAL_Configuration_NetworkInterface*)configurationBlock)->StartupAddressMode > 0); - // } - // else if(configuration == DeviceConfigurationOption_Wireless80211Network) - // { - // // storage address from block address - // storageAddress = (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; - - // // set block size, in case it's not already set - // blockSize = sizeof(HAL_Configuration_Wireless80211); - - // // make sure the config block marker is set - // memcpy(configurationBlock, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); - // } - // else if(configuration == DeviceConfigurationOption_X509CaRootBundle) - // { - // // storage address from block address - // storageAddress = (ByteAddress)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; - - // // set block size, in case it's not already set - // // because X509 certificate has a variable length need to compute the block size in two steps - // blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); - // blockSize += ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize; - - // // make sure the config block marker is set - // memcpy(configurationBlock, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1, sizeof(c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1)); - // } - // else - // { - // // this not a valid configuration option to update, quit - // // free memory first - // platform_free(configSectorCopy); - - // return FALSE; - // } - - // // erase config sector - // if(STM32FlashDriver_EraseBlock(NULL, (uint32_t)&__nanoConfig_start__) == TRUE) - // { - // // flash block is erased - - // // subtract the start address of config sector to get the offset - // blockOffset = storageAddress - (uint32_t)&__nanoConfig_start__; - - // // set pointer to block to udpate - // blockAddressInCopy = configSectorCopy + blockOffset; - - // // replace config block with new content by replacing memory - // memcpy(blockAddressInCopy, configSectorCopy, blockSize); + // CC32xx stores the config blocks on the file system so we don't care about sizes - // // copy the config block copy back to the config block storage - // success = STM32FlashDriver_Write(NULL, (uint32_t)&__nanoConfig_start__, sizeOfConfigSector, (unsigned char*)configSectorCopy, true); - // } - - // // free memory - // platform_free(configSectorCopy); - // } + switch(configuration) + { + case DeviceConfigurationOption_Network: + case DeviceConfigurationOption_Wireless80211Network: + return ConfigurationManager_StoreConfigurationBlock(configurationBlock, configuration, configurationIndex, 0, 0); - return success; + // this configuration option is not supported + case DeviceConfigurationOption_X509CaRootBundle: + default: + // shouldn't ever reach here + return FALSE; + } } // Default initialisation for wireless config block From 61585e977fb1301b08f42033a6fe6d14a8cc36d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 26 Mar 2019 12:06:19 +0000 Subject: [PATCH 75/90] Enable IPv6 on network interface to fix sockets issues MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index 3e7fc4150d..c12c2144c4 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -697,6 +697,13 @@ void * mainThread(void *arg) return(NULL); } + // need to setup the network interface to enable IPv6 otherwise there are errors in socket + // when IPv6 addresses are brought in (for example on a response to a DNS query) + // this can probably go away when support for IPv6 is official + uint32_t ifBitmap = 0; + ifBitmap = SL_NETCFG_IF_IPV6_LOCAL_STATEFUL | SL_NETCFG_IF_IPV6_GLOBAL_STATEFUL; + sl_NetCfgSet(SL_NETCFG_IF, SL_NETCFG_IF_STATE, sizeof(ifBitmap), &ifBitmap); + // start network processor retc = sl_Start(NULL, NULL, NULL); if(retc >= 0) From 17f418218897fad6528b6d30101761a763cd8c73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Tue, 26 Mar 2019 12:27:08 +0000 Subject: [PATCH 76/90] Code clean-up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index c12c2144c4..f5853dd675 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -43,8 +43,6 @@ extern void sntp_init(void); ////////////////////////////// #define SL_STOP_TIMEOUT (200) -#define APPLICATION_NAME "out of box" -#define APPLICATION_VERSION "1.00.00.09" #define SPAWN_TASK_PRIORITY (9) #define TASK_STACK_SIZE (2048) @@ -727,9 +725,6 @@ void * mainThread(void *arg) else if((retc < 0) && (retc != SL_ERROR_RESTORE_IMAGE_COMPLETE)) { // Handle Error - // //UART_PRINT("\n sl_Start failed\n"); - // //UART_PRINT("\n %s Example Ver. %s\n",APPLICATION_NAME, - // APPLICATION_VERSION); HAL_AssertEx(); while(1) { From 1571b77184d9ca679f66da41f715c459964d0ac1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 29 Mar 2019 08:53:41 +0000 Subject: [PATCH 77/90] Replace CRC32 software calculation with call to hardware engine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c | 7 +++++++ targets/TI-SimpleLink/common/CMakeLists.txt | 1 + .../TI-SimpleLink/common/nanoSupport_CRC32.c | 21 +++++++++++++++++++ 3 files changed, 29 insertions(+) create mode 100644 targets/TI-SimpleLink/common/nanoSupport_CRC32.c diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c index 255d7d5fdb..9f8f0ddbea 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -171,6 +172,12 @@ void CC3220SF_LAUNCHXL_initGeneral(void) PRCMCC3200MCUInit(); Power_init(); + // enable clock on the DTHE + MAP_PRCMPeripheralClkEnable(PRCM_DTHE, PRCM_RUN_MODE_CLK); + + // init CRC engine + MAP_CRCConfigSet(DTHE_BASE, (CRC_CFG_INIT_SEED | CRC_CFG_SIZE_8BIT | CRC_CFG_TYPE_P4C11DB7) ); + // Mux Pin62 to mode 1 for outputing NWP logs //MAP_PinTypeUART(PIN_62, PIN_MODE_1); } diff --git a/targets/TI-SimpleLink/common/CMakeLists.txt b/targets/TI-SimpleLink/common/CMakeLists.txt index ad8acd2185..dd85c4a02b 100644 --- a/targets/TI-SimpleLink/common/CMakeLists.txt +++ b/targets/TI-SimpleLink/common/CMakeLists.txt @@ -16,6 +16,7 @@ list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Fre # list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/GenericPort.cpp") list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/syscalls.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c") # append nanoHAL list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platformHAL.c") diff --git a/targets/TI-SimpleLink/common/nanoSupport_CRC32.c b/targets/TI-SimpleLink/common/nanoSupport_CRC32.c new file mode 100644 index 0000000000..0f7b0e6030 --- /dev/null +++ b/targets/TI-SimpleLink/common/nanoSupport_CRC32.c @@ -0,0 +1,21 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +// strong implementation of this function specific to the TI Simple Link targets +unsigned int SUPPORT_ComputeCRC(const void* rgBlock, int nLength, unsigned int crc) +{ + MAP_CRCSeedSet(DTHE_BASE, crc); + + crc = MAP_CRCDataProcess(DTHE_BASE, rgBlock, nLength, CRC_CFG_SIZE_8BIT); + + return crc; +}; From c709e4a3b4eb235621079f5f98c99d07354fc389 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 Apr 2019 16:20:37 +0100 Subject: [PATCH 78/90] Change nF tasks priority to fix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Fix ocasional and potential priority inversion problem with managed events. Signed-off-by: José Simões --- .../TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c index f5853dd675..dc544909b8 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c +++ b/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -45,6 +45,7 @@ extern void sntp_init(void); #define SL_STOP_TIMEOUT (200) #define SPAWN_TASK_PRIORITY (9) +#define NF_TASK_PRIORITY (5) #define TASK_STACK_SIZE (2048) #define SLNET_IF_WIFI_PRIO (5) @@ -734,7 +735,7 @@ void * mainThread(void *arg) // // provisioning task // pthread_attr_init(&threadAttributes); - // priorityParams.sched_priority = 1; + // priorityParams.sched_priority = NF_TASK_PRIORITY; // retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); // retc |= pthread_attr_setstacksize(&threadAttributes, TASK_STACK_SIZE); // if(retc) @@ -765,7 +766,7 @@ void * mainThread(void *arg) // receiver thread pthread_attr_init(&threadAttributes); - priorityParams.sched_priority = 1; + priorityParams.sched_priority = NF_TASK_PRIORITY; retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); retc |= pthread_attr_setstacksize(&threadAttributes, 2048); if (retc != 0) @@ -787,7 +788,7 @@ void * mainThread(void *arg) // CLR thread pthread_attr_init(&threadAttributes); - priorityParams.sched_priority = 1; + priorityParams.sched_priority = NF_TASK_PRIORITY; retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); retc |= pthread_attr_setstacksize(&threadAttributes, 4092); if (retc != 0) From e549bfba3295bd48454883ae1284eeed0f486caf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 5 Apr 2019 18:23:55 +0100 Subject: [PATCH 79/90] Add managed helper class for GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Add nuspec - Add helper class for GPIO Signed-off-by: José Simões --- .../managed_helpers/README.md | 5 +++ .../STM32F769I_DISCOVERY.Gpio.cs | 38 +++++++++++++++++++ .../managed_helpers/package.nuspec | 28 ++++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/README.md create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/STM32F769I_DISCOVERY.Gpio.cs create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/package.nuspec diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/README.md b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/README.md new file mode 100644 index 0000000000..3fedf32894 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](TI_CC3220SF_LAUNCHXL.Adc.cs) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/STM32F769I_DISCOVERY.Gpio.cs b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/STM32F769I_DISCOVERY.Gpio.cs new file mode 100644 index 0000000000..1a9adc02d3 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/STM32F769I_DISCOVERY.Gpio.cs @@ -0,0 +1,38 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.TI_CC3220SF_LAUNCHXL +{ + /// + /// Enumeration of GPIO pins in TI_CC3220SF_LAUNCHXL + /// + public static class GpioPins + { + /// + /// Switch 2, connected to CC32XX GPIO 13 + /// + public const int SW2 = 0; + + /// + /// Switch 3, connected to CC32XX GPIO 22 + /// + public const int SW3 = 1; + + /// + /// LED D10, connected to CC32XX GPIO 09 + /// + public const int LED_D10 = 4; + + /// + /// LED D9, connected to CC32XX GPIO 10 + /// + public const int LED_D9 = 5; + + /// + /// LED D8, connected to CC32XX GPIO 11 + /// + public const int LED_D8 = 6; + } +} diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/package.nuspec b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/package.nuspec new file mode 100644 index 0000000000..8553a224bd --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/package.nuspec @@ -0,0 +1,28 @@ + + + + nanoFramework.Targets.TI_CC3220SF_LAUNCHXL + nanoFramework.Targets.TI_CC3220SF_LAUNCHXL + 1.0.0 + nanoFramework project contributors + nanoFramework project contributors + false + + Helper classes to use TI_CC3220SF_LAUNCHXL target in C# applications. + + + + + This is an extension for .NET nanoFramework providing the GPIO pins when coding for the TI_CC3220SF_LAUNCHXL. + + https://github.com/nanoframework + https://secure.gravatar.com/avatar/97d0e092247f0716db6d4b47b7d1d1ad + https://github.com/nanoframework/nf-interpreter/blob/develop/LICENSE.md + Copyright (c) 2019 The nanoFramework project contributors + + nanoFramework, nano Framework, NETNF, NETMF, Micro Framework,.net + + + + + From 99463177256a0411f2e04a865a3049a57a0dcec3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 8 Apr 2019 14:52:25 +0100 Subject: [PATCH 80/90] Add readme for new target MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/README.md | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md new file mode 100644 index 0000000000..de4221c6f7 --- /dev/null +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md @@ -0,0 +1,70 @@ +# TI CC3220SF LAUNCHXL + +The CC3220SF LAUNCHXL board contains a TI CC3220SF device. + +## Jumper Settings + +* Set __RX__ and __TX__ to provide UART communications via the onboard USB debugger. + +## Board Resources + +The following table lists the Board names of the resources and their corresponding pins. + + |Board Resource|Pins| + |--------------|:---| + |`Board_ADC0`|P59 (Connect to analog signal)| + |`Board_ADC1`|P60 (Connect to analog signal)| + |`Board_CAPTURE0`|P04 | + |`Board_CAPTURE1`|P05 | + |`Board_GPIO_LED0`|P64 (__LED EN__ must be jumpered)| + |`Board_GPIO_LED1`|P64 (__LED EN__ must be jumpered)| + |`Board_GPIO_LED2`|P64 (__LED EN__ must be jumpered)| + |`Board_GPIO_BUTTON0`|P04 (`SW2`)| + |`Board_GPIO_BUTTON1`|P15 (`SW3`)| + |`Board_I2C0`|P01 - `SCL`, P02 - `SDA`| + |`Board_I2C_TMP`|P01 - `SCL`, P02 - `SDA` (__SCL__ and __SDA__ must be jumpered)| + |`Board_I2S0`|P50 - `XR1`, P53 - `CLK`, P62 - `CLKX`, P63 - `FSX`, P64 - `XR0`| + |`Board_PWM0`|P01 (__LED EN__ must be jumpered)| + |`Board_PWM1`|P02 (__LED EN__ must be jumpered)| + |`Board_SD0`|P06 - `DATA`, P07 - `CLK`, P08 - `CMD`| + |`Board_SDFatFS0`|P06 - `DATA`, P07 - `CLK`, P08 - `CMD`| + |`Board_SPI0`|P05 - `CLK`, P06 - `MISO`, P07 - `MOSI`, P08 - `CS`| + |`Board_SPI_MASTER`|P05 - `CLK`, P06 - `MISO`, P07 - `MOSI`, P08 - `CS`| + |`Board_SPI_SLAVE`|P05 - `CLK`, P06 - `MISO`, P07 - `MOSI`, P08 - `CS`| + |`Board_SPI_MASTER_READY`|P18| + |`Board_SPI_SLAVE_READY`|P03| + |`Board_UART0`|P57 - `RX`, P55 - `TX` (UART provided through emulation, __RX__ and __TX__ must be jumpered)| + |`Board_UART1`|P08 - `RX`, P07 - `TX`| + +## ADC Examples Pin Connections + +>__Important:__ The inputs to the ADC are required to be well within 1.4 VDC to avoid clipping, which will cause distortion. +The ADC inputs can be damaged if an input voltage higher than 1.8 VDC is applied to these pin. The 1.8 VDC hard limit must be considered from both the SW and HW points of view. +Always add a resistor divider/buffer to bring down the measurement signal voltage to within the ADC limits. See the [CC32xx ADC Appnote](http://processors.wiki.ti.com/index.php/CC32xx_ADC_Appnote) +for more details. + +The __CC3220SF LAUNCHXL__ has a protective circuit to allow an input of 3.3 VDC. +The `5V` should NOT be used for this may damage the ADC inputs. For testing, the following jumpers must be present: +`J5` = `OPAMP EN`, `J10` = `GND`, `J13` = `BRD`. + +>__Note:__ There are duplicate pins P59 and P60 on the board. Choose the ones connected to the BoosterPack headers (the pins not connected to the BoosterPack headers have an asterisk next to them). + +## Reset Behavior + +By default, the application is not retained after a power reset. To enable +retention of the application for debug purposes, the application should +add the following pre-defined symbol: `__SF_DEBUG__`. This will place a header, +`Board_debugHeader`, into flash. This header is defined in the Board.c file. + +>__Note:__ The user should ensure the `Board_debugHeader` is erased if +retention of the application is no longer desired. The Board.c file +will erase the `Board_debugHeader` if `__SF_NODEBUG__` is defined. + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. + +## nanoBooter + +Because this CPU uses a proprietary boot mechanism that copies the application from the SPI flash memory to the Cortex-M application core, it does not use nanoBooter. From d6396f2a501bff07413c982a7379726b4bad3fd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 4 May 2019 11:06:18 +0100 Subject: [PATCH 81/90] Add link to doc on how to flash CC3200SF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md index de4221c6f7..6d408e8c86 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md @@ -68,3 +68,7 @@ Meaning that `System.Math` API supports only the `float` overloads. The `double` ## nanoBooter Because this CPU uses a proprietary boot mechanism that copies the application from the SPI flash memory to the Cortex-M application core, it does not use nanoBooter. + +## Flashing nanoCLR + +Follow the instructions [here](http://docs.nanoframework.net/articles/ti-cc32xx/flash-nanoclr.html) on how to flash nanoCLR image in the board. From efd85e324924320516a7e58a535aca6d36246f29 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 4 May 2019 11:07:30 +0100 Subject: [PATCH 82/90] Update README with TI_CC3220SF_LAUNCHXL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 40b4a5dd6c..3beb1280bd 100644 --- a/README.md +++ b/README.md @@ -30,6 +30,8 @@ This repo contains: * [STM32 Random number generator driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_rng) * Target reference for FreeRTOS * [ESP32_WROOM_32](targets/FreeRTOS_ESP32/ESP32_WROOM_32) +* Target references for TI SimpleLink + * [TI CC3220SF_LAUNCHXL](targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL) * Target reference for other OSes * [Win32 OS (test project only at this time)](targets/os/win32) * [CMake files for the build system](CMake) @@ -61,6 +63,7 @@ The **preview** versions are continuous builds of the reference targets. They in | MBN_QUAIL | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/MBN_QUAIL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/MBN_QUAIL/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/MBN_QUAIL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/MBN_QUAIL/_latestVersion) | | NETDUINO3_WIFI | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/NETDUINO3_WIFI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/NETDUINO3_WIFI/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/NETDUINO3_WIFI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/NETDUINO3_WIFI/_latestVersion) | | ESP32_WROOM_32 | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ESP32_WROOM_32/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ESP32_WROOM_32/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ESP32_WROOM_32/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ESP32_WROOM_32/_latestVersion) | +| TI_CC3220SF_LAUNCHXL | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/TI_CC3220SF_LAUNCHXL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/TI_CC3220SF_LAUNCHXL/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/TI_CC3220SF_LAUNCHXL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/TI_CC3220SF_LAUNCHXL/_latestVersion) | The above firmware builds include support for the class libraries and features marked bellow. @@ -74,6 +77,7 @@ The above firmware builds include support for the class libraries and features m | MBN_QUAIL | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | | NETDUINO3_WIFI | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | | ESP32_WROOM_32 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | :heavy_check_mark: | | +| TI_CC3220SF_LAUNCHXL | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | | :heavy_check_mark: | | ## Feedback and documentation From 0a571af694df22c5e0b6fd9de626bd1813df8a96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 4 May 2019 11:58:23 +0100 Subject: [PATCH 83/90] Update Azure pipelines to build TI_CC3220SF_LAUNCHXL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../build-ti-simplelink.yml | 19 ++++++++ azure-pipelines.yml | 45 ++++++++++++++++++- 2 files changed, 62 insertions(+), 2 deletions(-) create mode 100644 azure-pipelines-templates/build-ti-simplelink.yml diff --git a/azure-pipelines-templates/build-ti-simplelink.yml b/azure-pipelines-templates/build-ti-simplelink.yml new file mode 100644 index 0000000000..647eb02fe0 --- /dev/null +++ b/azure-pipelines-templates/build-ti-simplelink.yml @@ -0,0 +1,19 @@ +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +parameters: + buildDirectory: '$(Build.SourcesDirectory)\build' + +steps: + + - task: CMake@1 + inputs: + cmakeArgs: '-G Ninja -DTOOLCHAIN_PREFIX=$(GNU_GCC_TOOLCHAIN_PATH) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_Version) -DTI_BOARD=$(BoardName) $(BuildOptions) ..' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Setup build with CMake + + - task: CMake@1 + inputs: + cmakeArgs: '--build ${{ parameters.buildDirectory }} --target all --config MinSizeRel' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Build with CMake diff --git a/azure-pipelines.yml b/azure-pipelines.yml index 146f147357..a993d0564b 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -166,6 +166,45 @@ jobs: - template: azure-pipelines-templates/publish-bintray.yml +################# +# TI SimpleLink +- job: Build_TI_SimpleLink_targets + # skip build if this is a PR, submitted by nfbot and the commit message contains [version update] + # not( and( eq(variables['Build.Reason'], 'PullRequest'), eq(variables['Build.RequestedForId'], 'nfbot'), contains(variables['Build.SourceVersionMessage'], '[version update]') ) ) + condition: not( and( startsWith(variables['Build.SourceBranch'], 'refs/pull'), eq( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ) )) + + dependsOn: + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + strategy: + matrix: + TI_CC3220SF_LAUNCHXL: + BoardName: TI_CC3220SF_LAUNCHXL + BuildOptions: -DTARGET_SERIES=CC32xx -DRTOS=TI_SIMPLELINK -DSUPPORT_ANY_BASE_CONVERSION=OFF -DNF_FEATURE_DEBUGGER=ON -DNF_FEATURE_RTC=ON -DNF_FEATURE_WATCHDOG=OFF -DNF_FEATURE_HAS_CONFIG_BLOCK=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=OFF -DAPI_Windows.Devices.Adc=ON -DAPI_System.Net=ON + GccArm_Version: + + variables: + GNU_GCC_TOOLCHAIN_PATH: $(Agent.TempDirectory)\GNU_Tools_ARM_Embedded + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + + steps: + - template: azure-pipelines-templates/nb-gitversioning.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + + - template: azure-pipelines-templates/download-install-ninja.yml + + - template: azure-pipelines-templates/build-ti-simplelink.yml + + - template: azure-pipelines-templates/pack-publish-artifacts.yml + + - template: azure-pipelines-templates/publish-bintray.yml + + - template: azure-pipelines-templates/pack-publish-managed-helpers.yml + ################# # WIN32 - job: Build_WIN32_nanoCLR @@ -194,8 +233,9 @@ jobs: dependsOn: - Build_STM32_targets - Build_ESP32_targets + - Build_TI_SimpleLink_targets # skip build if this is a PR, submitted by nfbot and the commit message contains [version update] - condition: and( succeeded('Build_STM32_targets'), succeeded('Build_ESP32_targets'), not( eq(variables['Build.Reason'], 'PullRequest') ), not( and( eq(variables['Build.RequestedForId'], 'nfbot'), contains(variables['Build.SourceVersionMessage'], '[version update]') ) ) ) + condition: and( succeeded('Build_STM32_targets'), succeeded('Build_ESP32_targets'), succeeded('Build_TI_SimpleLink_targets'), not( eq(variables['Build.Reason'], 'PullRequest') ), not( and( eq(variables['Build.RequestedForId'], 'nfbot'), contains(variables['Build.SourceVersionMessage'], '[version update]') ) ) ) pool: vmImage: 'VS2017-Win2016' @@ -244,7 +284,8 @@ jobs: dependsOn: - Build_STM32_targets - Build_ESP32_targets - condition: or( failed('Build_STM32_targets'), failed('Build_ESP32_targets'), failed('Build_WIN32_nanoCLR')) + - Build_TI_SimpleLink_targets + condition: or( failed('Build_STM32_targets'), failed('Build_ESP32_targets'), failed('Build_TI_SimpleLink_targets'), failed('Build_WIN32_nanoCLR')) pool: vmImage: 'VS2017-Win2016' From cd4f3fb8291a448926d6c61e6428c5749d7aafa2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 4 May 2019 12:51:30 +0100 Subject: [PATCH 84/90] Add CMake to download TI SimpleLink from repo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Update main CMake accordingly. Signed-off-by: José Simões --- CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in | 25 +++++++++++++++++++ CMakeLists.txt | 2 +- 2 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in diff --git a/CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in b/CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in new file mode 100644 index 0000000000..8892b9dbea --- /dev/null +++ b/CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in @@ -0,0 +1,25 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +project(SimpleLinkCC32xxSDK-download NONE) + +include(ExternalProject) + +# download SimpleLinkCC32xx SDK from nanoFramework repo +ExternalProject_Add( + SimpleLinkCC32xxSDK + PREFIX SimpleLinkCC32xxSdk + SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source + GIT_REPOSITORY https://github.com/nanoframework/SimpleLink_CC32xx_SDK + GIT_TAG ${TI_SL_CC32xx_SDK_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" +) diff --git a/CMakeLists.txt b/CMakeLists.txt index b00339a454..be48ea2fa6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1190,7 +1190,7 @@ elseif(RTOS_TI_SIMPLELINK_CHECK) SimpleLinkCC32xxSDK PREFIX SimpleLinkCC32xxSdk SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source - GIT_REPOSITORY https://github.com/nanoframework/ChibiOS + GIT_REPOSITORY https://github.com/nanoframework/SimpleLink_CC32xx_SDK GIT_TAG ${TI_SL_CC32xx_SDK_TAG} # target specified branch GIT_SHALLOW 1 # download only the tip of the branch, not the complete history TIMEOUT 10 From d48c190761a21d905e9ab9b855990f97f503b941 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 4 May 2019 16:15:16 +0100 Subject: [PATCH 85/90] Add missing declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c b/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c index 77101acda0..d81f534d5b 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c +++ b/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c @@ -6,6 +6,7 @@ #include #define SL_STOP_TIMEOUT (200) +extern uint16_t sl_Stop(const uint16_t Timeout); // FIXME TODO void CPU_Reset() From 5666517848a789f9dd89df637c444ff175af521d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sat, 4 May 2019 16:16:02 +0100 Subject: [PATCH 86/90] Add missing inclusion of managedf heap ram region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld index bed7cf8700..b5491c68e6 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x0FF800 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03C000 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } @@ -139,6 +139,9 @@ SECTIONS { } > REGION_STACK AT> REGION_STACK } +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", SRAM); + /* nanoCLR rules inclusion.*/ INCLUDE rules_clr.ld From c388990c7204e43af573e2487f1cb727f0d622f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sun, 5 May 2019 23:20:57 +0100 Subject: [PATCH 87/90] Add workaround for linker optimizing functions called in asm code --- targets/TI-SimpleLink/nanoCLR/targetPAL.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/targets/TI-SimpleLink/nanoCLR/targetPAL.c b/targets/TI-SimpleLink/nanoCLR/targetPAL.c index d7b7376bc0..1ccb8e63e0 100644 --- a/targets/TI-SimpleLink/nanoCLR/targetPAL.c +++ b/targets/TI-SimpleLink/nanoCLR/targetPAL.c @@ -3,6 +3,15 @@ // See LICENSE file in the project root for full license information. // -/////////////////////////////////////////////////////////////////////////////////////////////////// -// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // -/////////////////////////////////////////////////////////////////////////////////////////////////// +// Need to have calls to these two functions in C code. +// Because they are called only on asm code, GCC linker with LTO option thinks they are not used and just removes them. +// Having them called from a dummy function that is never called it a workaround for this. +// The clean alternative would be to add the GCC attribute used in those functions, but that's not our code to touch. + +void dummyFunction(void) __attribute__((used)); + +// Never called. +void dummyFunction(void) { + vTaskSwitchContext(); + localProgramStart(); +} From 3dc2cec59c8cb531347011e871c6484986eb607a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Sun, 5 May 2019 23:31:07 +0100 Subject: [PATCH 88/90] Adjust definition for nanoCLR size in minsizerel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Adjust block storage defintion for minsizerel build. - Adjust linker file for minsizerel build. Signed-off-by: José Simões --- .../common/Device_BlockStorage.c | 26 ++++++------------- .../nanoCLR/CC3220SF_CLR.ld | 2 +- 2 files changed, 9 insertions(+), 19 deletions(-) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c index b3095c5b6d..6f64e01092 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c @@ -6,15 +6,13 @@ #include #include -// 32kB blocks +// 2k blocks const BlockRange BlockRange1[] = { - { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x01000800 nanoCLR -}; - -const BlockRange BlockRange2[] = -{ - { BlockRange_BLOCKTYPE_DEPLOYMENT , 0, 0 }, // 0x08000000 nanoCLR + // the 1st block is reserved for the flash header + // so we don't take it into account for the map + { BlockRange_BLOCKTYPE_CODE , 0 , 92 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 93, 510 }, // 0x 102F000 deployment }; const BlockRegionInfo BlockRegions[] = @@ -22,19 +20,11 @@ const BlockRegionInfo BlockRegions[] = { (0), // no attributes for this region 0x01000800, // start address for block region - 1, // total number of blocks in this region - 0x0FF800, // total number of bytes per block + 511, // total number of blocks in this region + 0x800, // total number of bytes per block ARRAYSIZE_CONST_EXPR(BlockRange1), BlockRange1, - }, - { - (0), // no attributes for this region - 0x08000000, // start address for block region - 1, // total number of blocks in this region - 0x0FF800, // total number of bytes per block - ARRAYSIZE_CONST_EXPR(BlockRange1), - BlockRange2, - }, + } }; const DeviceBlockInfo Device_BlockInfo = diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld index b5491c68e6..04bcec44b6 100644 --- a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld +++ b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld @@ -35,7 +35,7 @@ STACKSIZE = 0x800; MEMORY { FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF - FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03C000 + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x02E800 SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } From f94c315997e54972313b14bc09c68f87a8e16dda Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 6 May 2019 01:38:05 +0100 Subject: [PATCH 89/90] Fox nameof managed helper source file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- ...{STM32F769I_DISCOVERY.Gpio.cs => TI_CC3220SF_LAUNCHXL.Gpio.cs} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/{STM32F769I_DISCOVERY.Gpio.cs => TI_CC3220SF_LAUNCHXL.Gpio.cs} (100%) diff --git a/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/STM32F769I_DISCOVERY.Gpio.cs b/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/TI_CC3220SF_LAUNCHXL.Gpio.cs similarity index 100% rename from targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/STM32F769I_DISCOVERY.Gpio.cs rename to targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/TI_CC3220SF_LAUNCHXL.Gpio.cs From 451a9cc2e0035675b9a4b207cb3138e7f8f3ef9f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Mon, 6 May 2019 08:54:05 +0100 Subject: [PATCH 90/90] Add Azure Pipeline template for TI SimpleLink targets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: José Simões --- .../pack-publish-ti-sl-managed-helpers.yml | 62 +++++++++++++++++++ azure-pipelines.yml | 2 +- 2 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml diff --git a/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml b/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml new file mode 100644 index 0000000000..acbf53a4a5 --- /dev/null +++ b/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml @@ -0,0 +1,62 @@ +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + + # check if managed helper files where changed + - powershell: | + git config --global user.email "nanoframework@outlook.com" + git config --global user.name "nfbot" + + $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes(":$(GitHubToken)"))))" + + $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/commits/$(Build.SourceVersion)" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET + Write-host "Files changed:" + $commit.files | % {$_.filename} + + if ( $commit.files.filename -like "*$(BoardName)/managed_helpers*" ) + { + echo "##vso[task.setvariable variable=BUILD_NUGET_PACKAGE]true" + + $counter = $env:HelperPackageVersion + $version = [int]$counter + $packageVersion = "1.0." + $version.ToString() + + echo "##vso[task.setvariable variable=PACKAGE_NUGET_VERSION]$packageVersion" + + Write-host "Package version is: $packageVersion" + } + else + { + echo "##vso[task.setvariable variable=BUILD_NUGET_PACKAGE]False" + } + + condition: succeeded() + displayName: Check if managed helpers files were changed + + - task: NuGetCommand@2 + inputs: + command: 'custom' + arguments: 'pack targets\TI-SimpleLink\$(BoardName)\managed_helpers\package.nuspec -Version $(PACKAGE_NUGET_VERSION)' + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true) ) + displayName: Pack managed helpers NuGet + + - task: CopyFiles@1 + inputs: + sourceFolder: $(Build.SourcesDirectory) + Contents: | + **\nanoFramework.Targets*.nupkg + TargetFolder: '$(Build.ArtifactStagingDirectory)' + flattenFolders: true + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true) ) + displayName: Collecting managed helpers deployable artifacts + + # push NuGet packages to NuGet (happens except on PR builds) + - task: NuGetCommand@2 + inputs: + command: push + nuGetFeedType: external + packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' + publishFeedCredentials: 'NuGet' + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true), not( startsWith(variables['Build.SourceBranch'], 'refs/pull') ) ) + displayName: Push managed helpers NuGet packages to NuGet diff --git a/azure-pipelines.yml b/azure-pipelines.yml index a993d0564b..beb1ffb839 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -203,7 +203,7 @@ jobs: - template: azure-pipelines-templates/publish-bintray.yml - - template: azure-pipelines-templates/pack-publish-managed-helpers.yml + - template: azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml ################# # WIN32