From c2dbadafb64ff00c5c12b87676aefa37bf236d18 Mon Sep 17 00:00:00 2001 From: Christophe Gerbier Date: Sun, 31 Dec 2017 22:23:59 +0100 Subject: [PATCH] PWM - Add more MCUs (#558) * PWM first draft Initial commit Signed-off-by: Christophe Gerbier * Add missing files Mising files * Update win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp Forgot to remove the PWM_OUTPUT_ACTIVE_LOW test... * Add new MCU for PWM Added support for F746xx, F769xx and F091xxC. Signed-off-by: Christophe Gerbier --- .../ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h | 14 +- .../ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h | 6 +- .../ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h | 14 +- ...tive_Windows_Devices_Pwm_PwmController.cpp | 2 +- ..._pwm_native_Windows_Devices_Pwm_PwmPin.cpp | 378 +++++++++++++++++- 5 files changed, 395 insertions(+), 19 deletions(-) diff --git a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h index f15910f965..1eb52832a4 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h @@ -227,14 +227,14 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 diff --git a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h index 06cfa0d130..eeb497eed2 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h @@ -128,10 +128,10 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM3 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 3 #define STM32_PWM_TIM2_IRQ_PRIORITY 3 #define STM32_PWM_TIM3_IRQ_PRIORITY 3 diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h index bb4cdabd29..9657a62132 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h @@ -229,14 +229,14 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE -#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE #define STM32_PWM_USE_TIM2 FALSE -#define STM32_PWM_USE_TIM3 FALSE -#define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM5 FALSE -#define STM32_PWM_USE_TIM8 FALSE -#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp index a58a653234..8866ba8b96 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp @@ -27,7 +27,7 @@ HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFre if (timerId == 1 || timerId >= 8) maxFrequency = (double)STM32_PCLK2_MAX; // TIM1, TIM8 and TIM9 on APB2 else maxFrequency = (double)STM32_PCLK1_MAX; // other timers on APB1 #elif defined(STM32F0xx_MCUCONF) - maxFrequency = (double)STM32_PCLK1_MAX; // Only APB1 on this MCU + maxFrequency = (double)STM32_PCLK_MAX; // Only APB1 on this MCU #endif stack.SetResult_R8(maxFrequency); } diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp index 2e5d41a840..bf92af09c3 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp @@ -174,7 +174,8 @@ int Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::GetChannel (int pin, channel = 0xFF; break; } -#elif defined(STM32F411xx) +#endif +#if defined(STM32F411xx) switch (timerId) { case 1 : @@ -287,6 +288,381 @@ switch (timerId) channel = 0xFF; break; } +#endif +#if defined(STM32F746xx) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8, PE9 + case 4*16+9 : + channel = 0; + break; + case 9 : // PA9, PE11 + case 4*16+11 : + channel = 1; + break; + case 10 : // PA10, PE13 + case 4*16+13 : + channel = 2; + break; + case 11 : // PA11, PE14 + case 4*16+14 : + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1*16+6 : // PB6, PD12 + case 3*16+12 : + channel = 0; + break; + case 1*16+7 : // PB7, PD13 + case 3*16+13 : + channel = 1; + break; + case 1*16+8 : // PB8, PD14 + case 3*16+14 : + channel = 2; + break; + case 1*16+9 : // PB9, PD15 + case 3*16+15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0 + channel = 0; + break; + case 1 : // PA1 + channel = 1; + break; + case 2 : // PA2 + channel = 2; + break; + case 3 : // PA3 + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2*16+6 : // PC6 + channel = 0; + break; + case 2*16+7 : // PC7 + channel = 1; + break; + case 2*16+8 : // PC8 + channel = 2; + break; + case 2*16+9 : // PC9 + channel = 3; + break; + } + break; + + + case 9 : + switch (pin) + { + case 2 : // PA2, PE5 + case 4*16+5 : + channel = 0; + break; + case 3 : // PA3, PE6 + case 4*16+6 : + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F769xx) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8, PE9 + case 4*16+9 : + channel = 0; + break; + case 9 : // PA9, PE11 + case 4*16+11 : + channel = 1; + break; + case 10 : // PA10, PE13 + case 4*16+13 : + channel = 2; + break; + case 11 : // PA11, PE14 + case 4*16+14 : + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1*16+6 : // PB6, PD12 + case 3*16+12 : + channel = 0; + break; + case 1*16+7 : // PB7, PD13 + case 3*16+13 : + channel = 1; + break; + case 1*16+8 : // PB8, PD14 + case 3*16+14 : + channel = 2; + break; + case 1*16+9 : // PB9, PD15 + case 3*16+15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0, PH10 + case 7*16+10 : + channel = 0; + break; + case 1 : // PA1, PH11 + case 7*16+11 : + channel = 1; + break; + case 2 : // PA2, PH12 + case 7*16+12 : + channel = 2; + break; + case 3 : // PA3, PI0 + case 8*16+0 : + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2*16+6 : // PC6, PI5 + case 8*16+5 : + channel = 0; + break; + case 2*16+7 : // PC7, PI6 + case 8*16+6 : + channel = 1; + break; + case 2*16+8 : // PC8, PI7 + case 8*16+7 : + channel = 2; + break; + case 2*16+9 : // PC9, PI2 + case 8*16+2 : + channel = 3; + break; + } + break; + + + case 9 : + switch (pin) + { + case 2 : // PA2, PE5 + case 4*16+5 : + channel = 0; + break; + case 3 : // PA3, PE6 + case 4*16+6 : + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F091xC) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8 + channel = 0; + break; + case 9 : // PA9 + channel = 1; + break; + case 10 : // PA10 + channel = 2; + break; + case 11 : // PA11 + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + default : + channel = 0xFF; + break; + } #endif return channel; }