diff --git a/src/CLR/Core/Execution.cpp b/src/CLR/Core/Execution.cpp index 86b25527ed..07ef7f7e00 100644 --- a/src/CLR/Core/Execution.cpp +++ b/src/CLR/Core/Execution.cpp @@ -155,6 +155,14 @@ HRESULT CLR_RT_ExecutionEngine::AllocateHeaps() CLR_RT_HeapCluster* hc = (CLR_RT_HeapCluster*) heapFirstFree; CLR_UINT32 size = (heapFree < c_HeapClusterSize) ? heapFree : c_HeapClusterSize; +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_1_HeapBlocksAndUnlink + + CLR_Debug::Printf( "Heap Cluster information\r\n"); + CLR_Debug::Printf( "Start: %08x\r\n", (size_t)heapFirstFree); + CLR_Debug::Printf( "Free: %08x\r\n", (size_t)heapFree); + CLR_Debug::Printf( "Block size: %d\r\n", sizeof(CLR_RT_HeapBlock)); + +#endif /// /// Speed up heap initialization for devices with very large heaps > 1MB /// Exponentially increase the size of a default heap block diff --git a/src/HAL/Include/nanoHAL_v2.h b/src/HAL/Include/nanoHAL_v2.h index 6137b3ba86..3c1c26daa1 100644 --- a/src/HAL/Include/nanoHAL_v2.h +++ b/src/HAL/Include/nanoHAL_v2.h @@ -9,6 +9,7 @@ #include #include +#include typedef enum SYSTEM_STATE { @@ -151,6 +152,10 @@ extern "C" { void nanoHAL_Initialize_C(); void HeapLocation_C(unsigned char** baseAddress, unsigned int* sizeInBytes); +// Call to the external memory configuration and initialization function +// If a target has external memory it has to provide the implementation for it. +void Target_ExternalMemoryInit(); + #ifdef __cplusplus } #endif diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt index e712dd26f4..186d63f9d6 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt @@ -93,6 +93,8 @@ add_executable( ${NANOCLR_PROJECT_NAME}.elf "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + # the next one is required is the target implements and it's using external memory + "${CMAKE_CURRENT_SOURCE_DIR}/target_external_memory.c" ${COMMON_PROJECT_SOURCES} ${NANOCLR_PROJECT_SOURCES} diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld index 8817a7f2cd..bd27c82947 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld @@ -24,6 +24,7 @@ MEMORY ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram6 : org = 0x00000000, len = 0 ram7 : org = 0x00000000, len = 0 + ext_ram : org = 0xD0000000, len = 8M /* external SDRAM */ } /* For each data/text section two region are defined, a virtual region @@ -71,6 +72,6 @@ REGION_ALIAS("BSS_RAM", ram0); REGION_ALIAS("HEAP_RAM", ram4); /* RAM region to be used for the nanoFramework CLR managed heap.*/ -REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); INCLUDE rules.ld diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h index c710062b71..370ea95871 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h @@ -16,5 +16,9 @@ #define HAL_USE_STM32_FLASH TRUE #endif -#endif // _HALCONF_NF_H_ +// Enables the FSMC subsystem. +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC TRUE +#endif +#endif // _HALCONF_NF_H_ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c index eda6974960..d8248a3ce5 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c @@ -36,6 +36,10 @@ int main(void) { // main() is executing with absolute priority but interrupts are already enabled. osKernelInitialize(); + // config and init external memory + // this has to be called after osKernelInitialize, otherwise an hard fault will occur + Target_ExternalMemoryInit(); + // Initializes a serial-over-USB CDC driver. sduObjectInit(&SDU1); sduStart(&SDU1, &serusbcfg); diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h index 574b9636f7..b34976b479 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h @@ -6,5 +6,20 @@ #ifndef _MCUCONF_NF_H_ #define _MCUCONF_NF_H_ + +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 TRUE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 +#define STM32_FSMC_DMA_CHN 0x03010201 + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE +#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE + #endif // _MCUCONF_NF_H_ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in index 101f177226..bdf31944de 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in @@ -18,9 +18,9 @@ // they also must be coherent with what's in the linker file for nanoBooter and nanoCLR // RAM base address -#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0) +#define RAM1_MEMORY_StartAddress ((uint32_t)0xD0000000) // RAM size -#define RAM1_MEMORY_Size ((uint32_t)0x00030000) +#define RAM1_MEMORY_Size ((uint32_t)0x00800000) // FLASH base address #define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_external_memory.c b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_external_memory.c new file mode 100644 index 0000000000..61e2bfae73 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_external_memory.c @@ -0,0 +1,106 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "hal.h" +#include "fsmc_sdram_lld.h" + + +// SDRAM Mode definition register defines +#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +// FMC_ReadPipe_Delay +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) +#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) + +// FMC_Read_Burst +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) +#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) + +// FMC_SDClock_Period +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) +#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) + +// FMC_ColumnBits_Number +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +// FMC_RowBits_Number +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +// FMC_SDMemory_Data_Width +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +// FMC_InternalBank_Number +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +// FMC_CAS_Latency +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +// FMC_Write_Protection +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + +#define SDRAM_SIZE (8 * 1024 * 1024) +#define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE) + + +// SDRAM driver configuration structure. +static const SDRAMConfig sdram_cfg = { + .sdcr = (uint32_t) FMC_ColumnBits_Number_8b | + FMC_RowBits_Number_12b | + FMC_SDMemory_Width_16b | + FMC_InternalBank_Number_4 | + FMC_CAS_Latency_3 | + FMC_Write_Protection_Disable | + FMC_SDClock_Period_2 | + FMC_Read_Burst_Enable | + FMC_ReadPipe_Delay_1, + .sdtr = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) + (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns)) + (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) + (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns)) + (3 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns)) + (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns) + (2 << 24), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) + // NRFS = 4-1 + .sdcmr = (3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 | + FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | + FMC_SDCMR_MRD_CAS_LATENCY_3 | + FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | + FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9, + + .sdrtr = (uint32_t)(683 << 1), +}; + +void Target_ExternalMemoryInit() +{ + fsmcSdramInit(); + fsmcSdramStart(&SDRAMD, &sdram_cfg); +} diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld index d5d6ebc965..fa391da264 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld @@ -30,7 +30,6 @@ MEMORY ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ ram6 : org = 0x00000000, len = 0 ram7 : org = 0x00000000, len = 0 - sram : org = 0xC0000000, len = 2M } /* For each data/text section two region are defined, a virtual region diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h index 5ad8166f84..7b316d2225 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h @@ -16,9 +16,4 @@ #define HAL_USE_STM32_FLASH TRUE #endif -// Enables the Flexible Memory Controller subsystem. -#if !defined(HAL_USE_FSMC) -#define HAL_USE_FSMC TRUE -#endif - #endif // _HALCONF_NF_H_ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c index 6779793afe..708fcdf21b 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c @@ -15,50 +15,6 @@ #include #include -#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -// SDRAM driver configuration structure -// need this definition here because it depends on the specifics of the target -#if (HAL_USE_FSMC == TRUE) -static const SDRAMConfig sdram_cfg = -{ - .sdcr = (uint32_t) FMC_SDRAM_COLUMN_BITS_NUM_8 | - FMC_SDRAM_ROW_BITS_NUM_12 | - FMC_SDRAM_MEM_BUS_WIDTH_16 | - FMC_SDRAM_INTERN_BANKS_NUM_4 | - FMC_SDRAM_CAS_LATENCY_2 | - FMC_SDRAM_WRITE_PROTECTION_DISABLE | - FMC_SDRAM_CLOCK_PERIOD_2 | - FMC_SDRAM_RBURST_ENABLE | - FMC_SDRAM_RPIPE_DELAY_0, - .sdtr = (uint32_t) ((2 - 1) | // FSMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) - ((6 - 1) << 4) | // FSMC_ExitSelfRefreshDelay = 6 (TXSR: min=70ns (6x11.11ns)) - ((4 - 1) << 8) | // FSMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) - ((6 - 1) << 12) | // FSMC_RowCycleDelay = 6 (TRC: min=70 (6x11.11ns)) - ((2 - 1) << 16) | // FSMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns)) - ((2 - 1) << 20) | // FSMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns) - ((2 - 1) << 24)), // FSMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) - /* NRFS = 4-1*/ - .sdcmr = (SDRAM_MODEREG_BURST_LENGTH_1 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_2 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE) << 9, - - // Set the refresh rate counter - // (15.62 us x Freq) - 20 - .sdrtr = (uint32_t)(1292 << 1), -}; - -#define SDRAM_BANK_ADDR ((uint32_t)0xC0000000) -#define WRITE_READ_ADDR ((uint32_t)0x0800) -#endif - -uint32_t __attribute__((section (".myBufSection"))) aTxBuffer[255]; -uint32_t aRxBuffer[255]; - // need to declare the Receiver thread here osThreadDef(ReceiverThread, osPriorityNormal, 2048, "ReceiverThread"); // declare CLRStartup thread here @@ -80,47 +36,6 @@ int main(void) { // main() is executing with absolute priority but interrupts are already enabled. osKernelInitialize(); - #if (HAL_USE_FSMC == TRUE) - - /* Enable I-Cache */ - SCB_EnableICache(); - - /* Enable D-Cache */ - SCB_EnableDCache(); - - - fsmcSdramInit(); - fsmcSdramStart(&SDRAMD, &sdram_cfg); - - uint32_t tmpIndex = 0; - - /* Put in global buffer different values */ - for (tmpIndex = 0; tmpIndex < 255; tmpIndex++ ) - { - aTxBuffer[tmpIndex] = tmpIndex + 0xA244250F; - } - -uint32_t uwIndex = 0; - // /* Write data to the SDRAM memory */ - // for (uwIndex = 0; uwIndex < 255; uwIndex++) - // { - // (*((volatile unsigned long *) (SDRAM_BANK_ADDR + 4*uwIndex))) = aTxBuffer[uwIndex]; - // } - - /* Read back data from the SDRAM memory */ - for (uwIndex = 0; uwIndex < 255; uwIndex++) - { - aRxBuffer[uwIndex] = (*((volatile unsigned long *) (SDRAM_BANK_ADDR + 4*uwIndex))); - } - - - //*(__IO uint16_t*) (SDRAM_BANK_ADDR ) = 0xDEAD; - - -volatile int testValue = *(__IO uint16_t*) (SDRAM_BANK_ADDR); - - #endif - // Initializes a serial-over-USB CDC driver. sduObjectInit(&SDU1); sduStart(&SDU1, &serusbcfg); diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h index b6d6ef8bbd..5ff03534b6 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h @@ -6,27 +6,4 @@ #ifndef _MCUCONF_NF_H_ #define _MCUCONF_NF_H_ -// FSMC driver system settings -#define STM32_FSMC_USE_FSMC1 TRUE -#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 - -// FSMC NAND driver system settings -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE - -// FCM SDRAM driver system settings -#define STM32_USE_FSMC_SDRAM TRUE -#define STM32_SDRAM_USE_FSMC_SDRAM1 TRUE -#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE - -// FCM SRAM driver system settings -#define STM32_USE_FSMC_SRAM FALSE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE - -// FCM PC card driver system settings -#define STM32_USE_FSMC_PCCARD FALSE - #endif // _MCUCONF_NF_H_ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_fsmc/hal_stm32_fsmc.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_fsmc/hal_stm32_fsmc.h index 318518f4e7..7388310ab2 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_fsmc/hal_stm32_fsmc.h +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_fsmc/hal_stm32_fsmc.h @@ -1,100 +1,245 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -// FSMC Driver subsystem low level driver header. +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// #ifndef HAL_FSMC_H_ #define HAL_FSMC_H_ #if (HAL_USE_FSMC == TRUE) -#include "stm32_registry.h" +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ +// (Re)define if needed base address constants supplied in ST's CMSIS +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + #if !defined(FSMC_Bank1_R_BASE) + #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) + #endif + #if !defined(FSMC_Bank1E_R_BASE) + #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) + #endif + #if !defined(FSMC_Bank2_R_BASE) + #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) + #endif + #if !defined(FSMC_Bank3_R_BASE) + #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) + #endif + #if !defined(FSMC_Bank4_R_BASE) + #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) + #endif + #if !defined(FSMC_Bank5_R_BASE) + #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + #endif +#else + #if !defined(FSMC_Bank1_R_BASE) + #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) + #endif + #if !defined(FSMC_Bank1E_R_BASE) + #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) + #endif + #if !defined(FSMC_Bank2_R_BASE) + #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + #endif + #if !defined(FSMC_Bank3_R_BASE) + #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) + #endif + #if !defined(FSMC_Bank4_R_BASE) + #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + #endif +#endif -// map to STM32 HAL defines -#define _MC_Bank1_R_BASE FMC_Bank1_R_BASE -#define _MC_Bank1E_R_BASE FMC_Bank1E_R_BASE -#define _MC_Bank2_R_BASE FMC_Bank2_R_BASE -#define _MC_Bank3_R_BASE FMC_Bank3_R_BASE -#define _MC_Bank4_R_BASE FMC_Bank4_R_BASE -#define _MC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE +/* + * Base bank mappings + */ +#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000) +#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000) +#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) +#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) + #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) + #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) +#endif -#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef -#define FMC_NAND_TypeDef FMC_Bank3_TypeDef -#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef +/* + * Subbunks of bank1 + */ +#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64) +#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE) +#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET) +#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET) +#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET) +/* + * Bank 2 (NAND) + */ +#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0) +#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000) -// Base address of banks -#define _MC_Bank1_MAP_BASE ((uint32_t) 0x60000000) -#define _MC_Bank2_MAP_BASE ((uint32_t) 0x70000000) -#define _MC_Bank3_MAP_BASE ((uint32_t) 0x80000000) -#define _MC_Bank4_MAP_BASE ((uint32_t) 0x90000000) -#define _MC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) -#define _MC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) +#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0) +#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000) +#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000) -// Sub-banks of bank1 -#define _MC_SUBBANK_OFFSET (1024 * 1024 * 64) -#define _MC_Bank1_1_MAP (_MC_Bank1_MAP_BASE) -#define _MC_Bank1_2_MAP (_MC_Bank1_1_MAP + _MC_SUBBANK_OFFSET) -#define _MC_Bank1_3_MAP (_MC_Bank1_2_MAP + _MC_SUBBANK_OFFSET) -#define _MC_Bank1_4_MAP (_MC_Bank1_3_MAP + _MC_SUBBANK_OFFSET) +#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0) +#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000) +#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000) -// Bank 2 (NAND) -#define _MC_Bank2_MAP_COMMON (_MC_Bank2_MAP_BASE + 0) -#define _MC_Bank2_MAP_ATTR (_MC_Bank2_MAP_BASE + 0x8000000) +/* + * Bank 3 (NAND) + */ +#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0) +#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000) -#define _MC_Bank2_MAP_COMMON_DATA (_MC_Bank2_MAP_COMMON + 0) -#define _MC_Bank2_MAP_COMMON_CMD (_MC_Bank2_MAP_COMMON + 0x10000) -#define _MC_Bank2_MAP_COMMON_ADDR (_MC_Bank2_MAP_COMMON + 0x20000) +#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0) +#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000) +#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000) -#define _MC_Bank2_MAP_ATTR_DATA (_MC_Bank2_MAP_ATTR + 0) -#define _MC_Bank2_MAP_ATTR_CMD (_MC_Bank2_MAP_ATTR + 0x10000) -#define _MC_Bank2_MAP_ATTR_ADDR (_MC_Bank2_MAP_ATTR + 0x20000) +#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0) +#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000) +#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000) -// Bank 3 (NAND) -#define _MC_Bank3_MAP_COMMON (_MC_Bank3_MAP_BASE + 0) -#define _MC_Bank3_MAP_ATTR (_MC_Bank3_MAP_BASE + 0x8000000) +/* + * Bank 4 (PC card) + */ +#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0) +#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000) +#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000) -#define _MC_Bank3_MAP_COMMON_DATA (_MC_Bank3_MAP_COMMON + 0) -#define _MC_Bank3_MAP_COMMON_CMD (_MC_Bank3_MAP_COMMON + 0x10000) -#define _MC_Bank3_MAP_COMMON_ADDR (_MC_Bank3_MAP_COMMON + 0x20000) +/* + * More convenient typedefs than CMSIS has + */ +typedef struct { + __IO uint32_t PCR; /**< NAND Flash control */ + __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */ + __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */ + __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */ + uint32_t RESERVED0; /**< Reserved, 0x70 */ + __IO uint32_t ECCR; /**< NAND Flash ECC result registers */ +} FSMC_NAND_TypeDef; + +typedef struct { + __IO uint32_t PCR; /**< PC Card control */ + __IO uint32_t SR; /**< PC Card FIFO status and interrupt */ + __IO uint32_t PMEM; /**< PC Card Common memory space timing */ + __IO uint32_t PATT; /**< PC Card Attribute memory space timing */ + __IO uint32_t PIO; /**< PC Card I/O space timing */ +} FSMC_PCCard_TypeDef; + +typedef struct { + __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */ + __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ + uint32_t RESERVED[63]; /**< Reserved */ + __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ +} FSMC_SRAM_NOR_TypeDef; -#define _MC_Bank3_MAP_ATTR_DATA (_MC_Bank3_MAP_ATTR + 0) -#define _MC_Bank3_MAP_ATTR_CMD (_MC_Bank3_MAP_ATTR + 0x10000) -#define _MC_Bank3_MAP_ATTR_ADDR (_MC_Bank3_MAP_ATTR + 0x20000) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) -// Bank 4 (PC card) -#define _MC_Bank4_MAP_COMMON (_MC_Bank4_MAP_BASE + 0) -#define _MC_Bank4_MAP_ATTR (_MC_Bank4_MAP_BASE + 0x8000000) -#define _MC_Bank4_MAP_IO (_MC_Bank4_MAP_BASE + 0xC000000) +typedef struct { + __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */ + __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */ + __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */ + __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */ + __IO uint32_t SDCMR; /**< SDRAM comand mode register */ + __IO uint32_t SDRTR; /**< SDRAM refresh timer register */ + __IO uint32_t SDSR; /**< SDRAM status register */ +} FSMC_SDRAM_TypeDef; +#endif + +/** + * @brief PCR register + */ +#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1) +#define FSMC_PCR_PBKEN ((uint32_t)1 << 2) +#define FSMC_PCR_PTYP ((uint32_t)1 << 3) +#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4) +#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4) +#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4) +#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4) +#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4) +#define FSMC_PCR_ECCEN ((uint32_t)1 << 6) +#define FSMC_PCR_PTYP_PCCARD 0 +#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP + +/** + * @brief SR register + */ +#define FSMC_SR_IRS ((uint8_t)0x01) +#define FSMC_SR_ILS ((uint8_t)0x02) +#define FSMC_SR_IFS ((uint8_t)0x04) +#define FSMC_SR_IREN ((uint8_t)0x08) +#define FSMC_SR_ILEN ((uint8_t)0x10) +#define FSMC_SR_IFEN ((uint8_t)0x20) +#define FSMC_SR_FEMPT ((uint8_t)0x40) +#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS) + +/** + * @brief BCR register + */ +#define FSMC_BCR_MBKEN ((uint32_t)1 << 0) +#define FSMC_BCR_MUXEN ((uint32_t)1 << 1) +#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2) +#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2) +#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2) +#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2) +#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4) +#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) +#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4) +#else +#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4) +#endif +#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4) +#define FSMC_BCR_FACCEN ((uint32_t)1 << 6) +#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8) +#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9) +#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10) +#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11) +#define FSMC_BCR_WREN ((uint32_t)1 << 12) +#define FSMC_BCR_WAITEN ((uint32_t)1 << 13) +#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14) +#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15) +#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) +#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) +#endif +#if (defined(STM32F7)) +#define FSMC_BCR_WFDIS ((uint32_t)1 << 21) +#endif /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ -// FSMC driver enable switch. -// If set to TRUE the support for the Flexible Memory Controller is included +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC driver enable switch. + * @details If set to @p TRUE the support for FSMC is included. + */ #if !defined(STM32_FSMC_USE_FSMC1) #define STM32_FSMC_USE_FSMC1 FALSE #endif +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -106,121 +251,64 @@ /* Driver data structures and types. */ /*===========================================================================*/ -// Type of a structure representing an FSMC driver. +/** + * @brief Type of a structure representing an FSMC driver. + */ typedef struct FSMCDriver FSMCDriver; -// Driver state machine possible states. -typedef enum -{ +/** + * @brief Driver state machine possible states. + */ +typedef enum { FSMC_UNINIT = 0, /**< Not initialized. */ FSMC_STOP = 1, /**< Stopped. */ FSMC_READY = 2, /**< Ready. */ -} FSMCstate_t; - -// Structure representing an FSMC driver. -struct FSMCDriver -{ - // Driver state. - FSMCstate_t state; +} fsmcstate_t; + +/** + * @brief Structure representing an FSMC driver. + */ +struct FSMCDriver { + /** + * @brief Driver state. + */ + fsmcstate_t state; + /* End of the mandatory fields.*/ #if STM32_SRAM_USE_FSMC_SRAM1 - FMC_NORSRAM_TypeDef *sram1; + FSMC_SRAM_NOR_TypeDef *sram1; #endif #if STM32_SRAM_USE_FSMC_SRAM2 - FMC_NORSRAM_TypeDef *sram2; + FSMC_SRAM_NOR_TypeDef *sram2; #endif #if STM32_SRAM_USE_FSMC_SRAM3 - FMC_NORSRAM_TypeDef *sram3; + FSMC_SRAM_NOR_TypeDef *sram3; #endif #if STM32_SRAM_USE_FSMC_SRAM4 - FMC_NORSRAM_TypeDef *sram4; + FSMC_SRAM_NOR_TypeDef *sram4; #endif #if STM32_NAND_USE_FSMC_NAND1 - FMC_NAND_TypeDef *nand1; + FSMC_NAND_TypeDef *nand1; #endif #if STM32_NAND_USE_FSMC_NAND2 - FMC_NAND_TypeDef *nand2; + FSMC_NAND_TypeDef *nand2; #endif #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ defined(STM32F7)) #if STM32_USE_FSMC_SDRAM - FMC_SDRAM_TypeDef *sdram; + FSMC_SDRAM_TypeDef *sdram; #endif #endif }; -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// -// From STMicroelectronics Cube HAL -// SDRAM Mode definition register defines -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -// FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay -#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U) -#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U) -#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U) -//#define FSMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) - -// FMC_SDRAM_Read_Burst FMC SDRAM Read Burst -#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U) -#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U) -// #define FSMC_Read_Burst_Mask ((uint32_t)0x00001000) - -// FMC_SDRAM_Clock_Period FMC SDRAM Clock Period -#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U) -#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U) -#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) -// #define FSMC_SDClock_Period_Mask ((uint32_t)0x00000C00) - -// FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number -#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U) -#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U) -#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U) -#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U) - -// FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number -#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U) -#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U) -#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U) - -// FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width -#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) -#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) - -// FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number -#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U) -#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U) - -// FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency -#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U) -#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U) -#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) - -// FMC_SDRAM_Write_Protection FMC SDRAM Write Protection -#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U) -#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#include "fsmc_nand_lld.h" -#include "fsmc_sdram_lld.h" -#include "fsmc_sram_lld.h" +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// #if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__) extern FSMCDriver FSMCD1; @@ -229,11 +317,9 @@ extern FSMCDriver FSMCD1; #ifdef __cplusplus extern "C" { #endif - void stm32FsmcInit(void); - void stm32FsmcStart(FSMCDriver *fsmc); - void stm32FsmcStop(FSMCDriver *fsmc); - + void fsmc_start(FSMCDriver *fsmcp); + void fsmc_stop(FSMCDriver *fsmcp); #ifdef __cplusplus } #endif diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/README.md b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/README.md index a9bf3e0d66..2324fcee2e 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/README.md +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/README.md @@ -1,4 +1,4 @@ # External flexible memory controller (FSMC) driver V1 This driver supports F4 and F7 series. -The low level driver code is taken or heavily inspired in the STCube MX HAL drivers from STMicroelectronics. +The low level driver code is taken from or heavily inspired in the ChibiOS community contribution repository. diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c index f0f8d3fc9d..8d942279bc 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c @@ -1,86 +1,52 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand_lld.c - * @brief NAND Driver subsystem low level driver source. - * - * @addtogroup NAND - * @{ - */ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// #include "hal.h" #if (HAL_USE_NAND == TRUE) -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// #define NAND_DMA_CHANNEL \ STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ STM32_FSMC_DMA_CHN) -/** - * @brief Bus width of NAND IC. - * @details Must be 8 or 16 - */ +// Bus width of NAND IC. +// Must be 8 or 16 #if ! defined(STM32_NAND_BUS_WIDTH) #define STM32_NAND_BUS_WIDTH 8 #endif -/** - * @brief DMA transaction width on AHB bus in bytes - */ +// DMA transaction width on AHB bus in bytes #define AHB_TRANSACTION_WIDTH 2 -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// -/** - * @brief NAND1 driver identifier. - */ +// NAND1 driver identifier. #if STM32_NAND_USE_FSMC_NAND1 NANDDriver NANDD1; #endif -/** - * @brief NAND2 driver identifier. - */ +// NAND2 driver identifier. #if STM32_NAND_USE_FSMC_NAND2 NANDDriver NANDD2; #endif -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Helper function. - * - * @notapi - */ +// Helper function. static void align_check(const void *ptr, uint32_t len) { osalDbgCheck((((uint32_t)ptr % AHB_TRANSACTION_WIDTH) == 0) && ((len % AHB_TRANSACTION_WIDTH) == 0) && @@ -89,17 +55,13 @@ static void align_check(const void *ptr, uint32_t len) { (void)len; } -/** - * @brief Work around errata in STM32's FSMC core. - * @details Constant output clock (if enabled) disappears when CLKDIV value - * sets to 1 (FSMC_CLK period = 2 × HCLK periods) AND 8-bit async - * transaction generated on AHB. This workaround eliminates 8-bit - * transactions on bus when you use 8-bit memory. It suitable only - * for 8-bit memory (i.e. PWID bits in PCR register must be set - * to 8-bit mode). - * - * @notapi - */ +// Work around errata in STM32's FSMC core. +// Constant output clock (if enabled) disappears when CLKDIV value +// sets to 1 (FMC_CLK period = 2 × HCLK periods) AND 8-bit async +// transaction generated on AHB. This workaround eliminates 8-bit +// transactions on bus when you use 8-bit memory. It suitable only +// for 8-bit memory (i.e. PWID bits in PCR register must be set +// to 8-bit mode). static void set_16bit_bus(NANDDriver *nandp) { #if STM32_NAND_BUS_WIDTH nandp->nand->PCR |= FSMC_PCR_PWID_16; @@ -116,35 +78,24 @@ static void set_8bit_bus(NANDDriver *nandp) { #endif } -/** - * @brief Wakes up the waiting thread. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] msg wakeup message - * - * @notapi - */ +// Wakes up the waiting thread. +// nandp pointer to the @p NANDDriver object +// msg wakeup message static void wakeup_isr(NANDDriver *nandp) { osalDbgCheck(nandp->thread != NULL); osalThreadResumeI(&nandp->thread, MSG_OK); } -/** - * @brief Put calling thread in suspend and switch driver state - * - * @param[in] nandp pointer to the @p NANDDriver object - */ +// Put calling thread in suspend and switch driver state +// nandp pointer to the @p NANDDriver object static void nand_lld_suspend_thread(NANDDriver *nandp) { osalThreadSuspendS(&nandp->thread); } -/** - * @brief Caclulate ECCPS register value - * - * @param[in] nandp pointer to the @p NANDDriver object - */ +// Caclulate ECCPS register value +// nandp pointer to the @p NANDDriver object static uint32_t calc_eccps(NANDDriver *nandp) { uint32_t i = 0; @@ -159,17 +110,20 @@ static uint32_t calc_eccps(NANDDriver *nandp) { return i << 17; } -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief Enable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver interrupt handlers. // +/////////////////////////////////////////////////////////////////////////////// + +// Enable interrupts from NAND +// nandp pointer to the @p NANDDriver object static void nand_ready_isr_enable(NANDDriver *nandp) { nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | @@ -177,30 +131,20 @@ static void nand_ready_isr_enable(NANDDriver *nandp) { nandp->nand->SR |= FSMC_SR_IREN; } -/** - * @brief Disable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ +// Disable interrupts from NAND +// nandp pointer to the @p NANDDriver object static void nand_ready_isr_disable(NANDDriver *nandp) { nandp->nand->SR &= ~FSMC_SR_IREN; } -/** - * @brief Ready interrupt handler - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ +// Ready interrupt handler +// nandp pointer to the @p NANDDriver object static void nand_isr_handler(NANDDriver *nandp) { osalSysLockFromISR(); - osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ + osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); // spurious interrupt happened nandp->nand->SR &= ~FSMC_SR_IRS; switch (nandp->state){ @@ -208,12 +152,12 @@ static void nand_isr_handler(NANDDriver *nandp) { nandp->state = NAND_DMA_RX; dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata, nandp->datalen/AHB_TRANSACTION_WIDTH); - /* thread will be waked up from DMA ISR */ + // thread will be waked up from DMA ISR break; - case NAND_ERASE: /* NAND reports about erase finish */ - case NAND_PROGRAM: /* NAND reports about page programming finish */ - case NAND_RESET: /* NAND reports about finished reset recover */ + case NAND_ERASE: // NAND reports about erase finish + case NAND_PROGRAM: // NAND reports about page programming finish + case NAND_RESET: // NAND reports about finished reset recover nandp->state = NAND_READY; wakeup_isr(nandp); break; @@ -225,16 +169,11 @@ static void nand_isr_handler(NANDDriver *nandp) { osalSysUnlockFromISR(); } -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ +// DMA RX end IRQ handler. +// nandp pointer to the @p NANDDriver object +// flags pre-shifted content of the ISR register static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { - /* DMA errors handling.*/ + // DMA errors handling. #if defined(STM32_NAND_DMA_ERROR_HOOK) if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { STM32_NAND_DMA_ERROR_HOOK(nandp); @@ -251,7 +190,7 @@ static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { case NAND_DMA_TX: nandp->state = NAND_PROGRAM; nandp->map_cmd[0] = NAND_CMD_PAGEPROG; - /* thread will be woken up from ready_isr() */ + // thread will be woken up from ready_isr() break; case NAND_DMA_RX: @@ -269,21 +208,17 @@ static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { osalSysUnlockFromISR(); } -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// -/** - * @brief Low level NAND driver initialization. - * - * @notapi - */ -void nand_lld_init(void) { +// Low level NAND driver initialization. +void fsmcNandInit(void) { stm32FsmcInit(); #if STM32_NAND_USE_FSMC_NAND1 - /* Driver initialization.*/ + // Driver initialization. nandObjectInit(&NANDD1); NANDD1.rxdata = NULL; NANDD1.datalen = 0; @@ -294,10 +229,10 @@ void nand_lld_init(void) { NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD; NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR; NANDD1.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND1 */ +#endif // STM32_NAND_USE_FSMC_NAND1 #if STM32_NAND_USE_FSMC_NAND2 - /* Driver initialization.*/ + // Driver initialization. nandObjectInit(&NANDD2); NANDD2.rxdata = NULL; NANDD2.datalen = 0; @@ -308,24 +243,19 @@ void nand_lld_init(void) { NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD; NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR; NANDD2.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND2 */ +#endif // STM32_NAND_USE_FSMC_NAND2 } -/** - * @brief Configures and activates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_start(NANDDriver *nandp) { +// Configures and activates the NAND peripheral. +// nandp pointer to the @p NANDDriver object +void fsmcNandStart(NANDDriver *nandp) { bool b; uint32_t dmasize; uint32_t pcr_bus_width; if (FSMCD1.state == FSMC_STOP) - stm32FsmcStart(&FSMCD1); + fsmc_start(&FSMCD1); if (nandp->state == NAND_STOP) { b = dmaStreamAllocate(nandp->dma, @@ -367,14 +297,9 @@ void nand_lld_start(NANDDriver *nandp) { } } -/** - * @brief Deactivates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_stop(NANDDriver *nandp) { +// Deactivates the NAND peripheral. +// nandp pointer to the @p NANDDriver object +void fsmcNandStop(NANDDriver *nandp) { if (nandp->state == NAND_READY) { dmaStreamRelease(nandp->dma); @@ -384,18 +309,13 @@ void nand_lld_stop(NANDDriver *nandp) { } } -/** - * @brief Read data from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[out] data pointer to data buffer - * @param[in] datalen size of data buffer in bytes - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @notapi - */ +// Read data from NAND. +// nandp pointer to the @p NANDDriver object +// data pointer to data buffer +// datalen size of data buffer in bytes +// addr pointer to address buffer +// addrlen length of address +// ecc pointer to store computed ECC. Ignored when NULL. void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){ @@ -412,9 +332,9 @@ void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, nand_lld_write_cmd(nandp, NAND_CMD_READ0_CONFIRM); set_8bit_bus(nandp); - /* Here NAND asserts busy signal and starts transferring from memory - array to page buffer. After the end of transmission ready_isr functions - starts DMA transfer from page buffer to MCU's RAM.*/ + // Here NAND asserts busy signal and starts transferring from memory + // array to page buffer. After the end of transmission ready_isr functions + // starts DMA transfer from page buffer to MCU's RAM. osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, "State machine broken. ECCEN must be previously disabled."); @@ -425,7 +345,7 @@ void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, nand_lld_suspend_thread(nandp); osalSysUnlock(); - /* thread was woken up from DMA ISR */ + // thread was woken up from DMA ISR if (NULL != ecc){ while (! (nandp->nand->SR & FSMC_SR_FEMPT)) ; @@ -434,20 +354,14 @@ void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, } } -/** - * @brief Write data to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] data buffer with data to be written - * @param[in] datalen size of data buffer in bytes - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ +// Write data to NAND. +// nandp pointer to the @p NANDDriver object +// data buffer with data to be written +// datalen size of data buffer in bytes +// addr pointer to address buffer +// addrlen length of address +// ecc pointer to store computed ECC. Ignored when NULL. +// The operation status reported by NAND IC (0x70 command). uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { @@ -461,8 +375,8 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, nand_lld_write_addr(nandp, addr, addrlen); set_8bit_bus(nandp); - /* Now start DMA transfer to NAND buffer and put thread in sleep state. - Tread will be woken up from ready ISR. */ + // Now start DMA transfer to NAND buffer and put thread in sleep state. + // Tread will be woken up from ready ISR. nandp->state = NAND_DMA_TX; osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, "State machine broken. ECCEN must be previously disabled."); @@ -487,13 +401,8 @@ uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, return nand_lld_read_status(nandp); } -/** - * @brief Soft reset NAND device. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ +// Soft reset NAND device. +// nandp pointer to the @p NANDDriver object void nand_lld_reset(NANDDriver *nandp) { nandp->state = NAND_RESET; @@ -507,17 +416,11 @@ void nand_lld_reset(NANDDriver *nandp) { osalSysUnlock(); } -/** - * @brief Erase block. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ +// Erase block. +// nandp pointer to the @p NANDDriver object +// addr pointer to address buffer +// addrlen length of address +// return The operation status reported by NAND IC (0x70 command). uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { nandp->state = NAND_ERASE; @@ -535,15 +438,10 @@ uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { return nand_lld_read_status(nandp); } -/** - * @brief Send addres to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] len length of address array - * @param[in] addr pointer to address array - * - * @notapi - */ +// Send addres to NAND. +// nandp pointer to the @p NANDDriver object +// len length of address array +// addr pointer to address array void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { size_t i = 0; @@ -551,27 +449,16 @@ void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { nandp->map_addr[i] = addr[i]; } -/** - * @brief Send command to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] cmd command value - * - * @notapi - */ +// Send command to NAND. +// nandp pointer to the @p NANDDriver object +// cmd command value void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { nandp->map_cmd[0] = cmd; } -/** - * @brief Read status byte from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @return Status byte. - * - * @notapi - */ +// Read status byte from NAND. +// nandp pointer to the @p NANDDriver object +// return Status byte. uint8_t nand_lld_read_status(NANDDriver *nandp) { uint16_t status; @@ -584,4 +471,4 @@ uint8_t nand_lld_read_status(NANDDriver *nandp) { return status & 0xFF; } -#endif /* HAL_USE_NAND */ +#endif // HAL_USE_NAND diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.h index 6808870e93..91d4a028c1 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.h +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.h @@ -1,116 +1,78 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand_lld.h - * @brief NAND Driver subsystem low level driver header. - * - * @addtogroup NAND - * @{ - */ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// #ifndef HAL_NAND_LLD_H_ #define HAL_NAND_LLD_H_ -#include "hal_stm32_fsmc.h" -//#include "bitmap.h" +#include "hal_stm32_fsmc" #if (HAL_USE_NAND == TRUE) -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// #define NAND_MIN_PAGE_SIZE 256 #define NAND_MAX_PAGE_SIZE 8192 -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC1 interrupt priority level setting. - */ +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +// Configuration options + +// FSMC1 interrupt priority level setting. #if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) #define STM32_EMC_FSMC1_IRQ_PRIORITY 10 #endif -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND1 is included. - */ +// NAND driver enable switch. +// If set to @p TRUE the support for NAND1 is included. + #if !defined(STM32_NAND_USE_NAND1) #define STM32_NAND_USE_NAND1 FALSE #endif -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND2 is included. - */ +// NAND driver enable switch. +// If set to @p TRUE the support for NAND2 is included. #if !defined(STM32_NAND_USE_NAND2) #define STM32_NAND_USE_NAND2 FALSE #endif -/** - * @brief NAND DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ +// NAND DMA error hook. +// The default action for DMA errors is a system halt because DMA +// error can only happen because programming errors. #if !defined(STM32_NAND_DMA_ERROR_HOOK) #define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") #endif -/** - * @brief NAND interrupt enable switch. - * @details If set to @p TRUE the support for internal FSMC interrupt included. - */ +// NAND interrupt enable switch. +// If set to @p TRUE the support for internal FSMC interrupt included. #if !defined(STM32_NAND_USE_INT) #define STM32_NAND_USE_INT FALSE #endif -/** -* @brief NAND1 DMA priority (0..3|lowest..highest). -*/ +// NAND1 DMA priority (0..3|lowest..highest). #if !defined(STM32_NAND_NAND1_DMA_PRIORITY) #define STM32_NAND_NAND1_DMA_PRIORITY 0 #endif -/** -* @brief NAND2 DMA priority (0..3|lowest..highest). -*/ +// NAND2 DMA priority (0..3|lowest..highest). #if !defined(STM32_NAND_NAND2_DMA_PRIORITY) #define STM32_NAND_NAND2_DMA_PRIORITY 0 #endif -/** - * @brief DMA stream used for NAND operations. - * @note This option is only available on platforms with enhanced DMA. - */ +// DMA stream used for NAND operations. +// This option is only available on platforms with enhanced DMA. #if !defined(STM32_NAND_DMA_STREAM) #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// #if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2 #error "NAND driver activated but no NAND peripheral assigned" @@ -124,156 +86,119 @@ #define STM32_DMA_REQUIRED #endif -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// -/** - * @brief Type of a structure representing an NAND driver. - */ +// Type of a structure representing an NAND driver. typedef struct NANDDriver NANDDriver; -/** - * @brief Type of interrupt handler function. - */ +// Type of interrupt handler function. typedef void (*nandisrhandler_t)(NANDDriver *nandp); -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ +// Driver configuration structure. +// It could be empty on some architectures. typedef struct { - /** - * @brief Number of erase blocks in NAND device. - */ + // Number of erase blocks in NAND device. uint32_t blocks; - /** - * @brief Number of data bytes in page. - */ + + // Number of data bytes in page. uint32_t page_data_size; - /** - * @brief Number of spare bytes in page. - */ + + // Number of spare bytes in page. uint32_t page_spare_size; - /** - * @brief Number of pages in block. - */ + + // Number of pages in block. uint32_t pages_per_block; - /** - * @brief Number of write cycles for row addressing. - */ + + // Number of write cycles for row addressing. uint8_t rowcycles; - /** - * @brief Number of write cycles for column addressing. - */ + + // Number of write cycles for column addressing. uint8_t colcycles; - /* End of the mandatory fields.*/ - /** - * @brief Number of wait cycles. This value will be used both for - * PMEM and PATTR registers - * - * @note For proper calculation procedure please look at AN2784 document - * from STMicroelectronics. - */ + // End of the mandatory fields. + // Number of wait cycles. This value will be used both for + // PMEM and PATTR registers + // For proper calculation procedure please look at AN2784 document from STMicroelectronics uint32_t pmem; + } NANDConfig; -/** - * @brief Structure representing an NAND driver. - */ +// Structure representing an NAND driver. struct NANDDriver { - /** - * @brief Driver state. - */ + // Driver state. nandstate_t state; - /** - * @brief Current configuration data. - */ + + // Current configuration data. const NANDConfig *config; - /** - * @brief Array to store bad block map. - */ + + // Array to store bad block map. #if NAND_USE_MUTUAL_EXCLUSION #if CH_CFG_USE_MUTEXES - /** - * @brief Mutex protecting the bus. - */ + // Mutex protecting the bus. mutex_t mutex; #elif CH_CFG_USE_SEMAPHORES semaphore_t semaphore; #endif -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Function enabling interrupts from FSMC. - */ +#endif // NAND_USE_MUTUAL_EXCLUSION + // End of the mandatory fields. + + // Function enabling interrupts from FSMC. nandisrhandler_t isr_handler; - /** - * @brief Pointer to current transaction buffer. - */ + + // Pointer to current transaction buffer. void *rxdata; - /** - * @brief Current transaction length in bytes. - */ + + // Current transaction length in bytes. size_t datalen; - /** - * @brief DMA mode bit mask. - */ + + // DMA mode bit mask. uint32_t dmamode; - /** - * @brief DMA channel. - */ + + // DMA channel. const stm32_dma_stream_t *dma; - /** - * @brief Thread waiting for I/O completion. - */ + + // Thread waiting for I/O completion. thread_t *thread; - /** - * @brief Pointer to the FSMC NAND registers block. - */ - FMC_NAND_TypeDef *nand; - /** - * @brief Memory mapping for data. - */ + + // Pointer to the FSMC NAND registers block. + FSMC_NAND_TypeDef *nand; + + // Memory mapping for data. uint16_t *map_data; - /** - * @brief Memory mapping for commands. - */ + + // Memory mapping for commands. uint16_t *map_cmd; - /** - * @brief Memory mapping for addresses. - */ + + // Memory mapping for addresses. uint16_t *map_addr; - /** - * @brief Pointer to bad block map. - * @details One bit per block. All memory allocation is user's responsibility. - */ - bitmap_t *bb_map; + }; -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// -#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__) +#if STM32_NAND_USE_FSMC_NAND1 extern NANDDriver NANDD1; #endif -#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__) +#if STM32_NAND_USE_FSMC_NAND2 extern NANDDriver NANDD2; #endif #ifdef __cplusplus extern "C" { #endif - void nand_lld_init(void); - void nand_lld_start(NANDDriver *nandp); - void nand_lld_stop(NANDDriver *nandp); + + void fsmcNandInit(void); + void fsmcNandStart(NANDDriver *nandp); + void fsmcNandStop(NANDDriver *nandp); uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); @@ -283,10 +208,11 @@ extern "C" { size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); uint8_t nand_lld_read_status(NANDDriver *nandp); void nand_lld_reset(NANDDriver *nandp); + #ifdef __cplusplus } #endif -#endif /* HAL_USE_NAND */ +#endif // HAL_USE_NAND -#endif /* HAL_NAND_LLD_H_ */ +#endif // HAL_NAND_LLD_H_ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c index 8ddb65c911..a6b8377649 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c @@ -1,97 +1,60 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_FSMC_sdram.c - * @brief SDRAM Driver subsystem low level driver source. - * - * @addtogroup SDRAM - * @{ - */ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess and Nick Klimov aka progfin +// See LICENSE file in the project root for full license information. +// #include "hal.h" #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F769xx)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #if (STM32_USE_FSMC_SDRAM == TRUE) -#include "FSMC_sdram_lld.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * FSMC_Command_Mode - */ -#define FSMCCM_NORMAL ((uint32_t)0x00000000) -#define FSMCCM_CLK_ENABLED ((uint32_t)0x00000001) -#define FSMCCM_PALL ((uint32_t)0x00000002) -#define FSMCCM_AUTO_REFRESH ((uint32_t)0x00000003) -#define FSMCCM_LOAD_MODE ((uint32_t)0x00000004) -#define FSMCCM_SELFREFRESH ((uint32_t)0x00000005) -#define FSMCCM_POWER_DOWN ((uint32_t)0x00000006) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SDRAM driver identifier. - */ +#include "fsmc_sdram_lld.h" + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +// FMC_Command_Mode +#define FMCCM_NORMAL ((uint32_t)0x00000000) +#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) +#define FMCCM_PALL ((uint32_t)0x00000002) +#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) +#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) +#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) +#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// +// SDRAM driver identifier. SDRAMDriver SDRAMD; -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wait until the SDRAM controller is ready. - * - * @notapi - */ +// Wait until the SDRAM controller is ready. static void _sdram_wait_ready(void) { - /* Wait until the SDRAM controller is ready */ + // Wait until the SDRAM controller is ready while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); } -/** - * @brief Executes the SDRAM memory initialization sequence. - * - * @param[in] cfgp pointer to the @p SDRAMConfig object - * - * @notapi - */ -static void _sdram_init_sequence(const SDRAMConfig *cfg) -{ +// Executes the SDRAM memory initialization sequence. +// cfgp pointer to the @p SDRAMConfig object +static void _sdram_init_sequence(const SDRAMConfig *cfgp) { uint32_t command_target = 0; - __IO uint32_t tmpr = 0; #if STM32_SDRAM_USE_FSMC_SDRAM1 command_target |= FMC_SDCMR_CTB1; @@ -100,52 +63,49 @@ static void _sdram_init_sequence(const SDRAMConfig *cfg) command_target |= FMC_SDCMR_CTB2; #endif - // Step 3: Configure a clock configuration enable command + // Step 3: Configure a clock configuration enable command. _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; - tmpr = FSMCCM_CLK_ENABLED | command_target | 0 | 0; - SDRAMD.sdram->SDCMR = tmpr; - - // Step 4: Insert delay (tipically 100uS) - osalThreadSleepMilliseconds(2); + // Step 4: Insert delay (tipically 100uS). + osalThreadSleepMilliseconds(1); - // Step 5: Configure a PALL (precharge all) command + // Step 5: Configure a PALL (precharge all) command. _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; - tmpr = FSMCCM_PALL | command_target | 0 | 0; - SDRAMD.sdram->SDCMR = tmpr; - - // Step 6 Configure a Auto-Refresh command + // Step 6.1: Configure a Auto-Refresh command: send the first command. _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (cfgp->sdcmr & FMC_SDCMR_NRFS); - tmpr = FSMCCM_AUTO_REFRESH | command_target | ((8-1) << 5) | 0; - SDRAMD.sdram->SDCMR = tmpr; - - // Step 7: Program the external memory mode register + // Step 6.2: Send the second command. _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (cfgp->sdcmr & FMC_SDCMR_NRFS); - tmpr = FSMCCM_LOAD_MODE | command_target | 0 | cfg->sdcmr; - SDRAMD.sdram->SDCMR = tmpr; - - // Step 8: Set clock + // Step 7: Program the external memory mode register. _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | + (cfgp->sdcmr & FMC_SDCMR_MRD); - SDRAMD.sdram->SDRTR |= cfg->sdrtr; + // Step 8: Set clock. + _sdram_wait_ready(); + SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; _sdram_wait_ready(); } -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver interrupt handlers. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// -/** - * @brief Low level SDRAM driver initialization. - */ +// Low level SDRAM driver initialization. + void fsmcSdramInit(void) { stm32FsmcInit(); @@ -154,65 +114,36 @@ void fsmcSdramInit(void) { SDRAMD.state = SDRAM_STOP; } -/** - * @brief Configures and activates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * @param[in] cfgp pointer to the @p SDRAMConfig object - */ -void fsmcSdramStart(SDRAMDriver *sdram, const SDRAMConfig *cfg) -{ - uint32_t tmpr1 = 0; +// Configures and activates the SDRAM peripheral. +// sdramp pointer to the @p SDRAMDriver object +// cfgp pointer to the @p SDRAMConfig object +void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { if (FSMCD1.state == FSMC_STOP) - stm32FsmcStart(&FSMCD1); + fsmc_start(&FSMCD1); - osalDbgAssert((sdram->state == SDRAM_STOP) || (sdram->state == SDRAM_READY), + osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), "SDRAM. Invalid state."); - if (sdram->state == SDRAM_STOP) - { - - // Initializes the FMC_SDRAM device according to the specified control parameters - // load load current SDCR register value - tmpr1 = sdram->sdram->SDCR[0]; - - // Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr1 |= cfg->sdcr; - - sdram->sdram->SDCR[0] = tmpr1; - - // Initializes the FMC_SDRAM device timing according to the specified parameters - // load current SDTR register value - tmpr1 = sdram->sdram->SDTR[0]; - - // Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr1 |= cfg->sdtr; + if (sdramp->state == SDRAM_STOP) { - sdram->sdram->SDTR[0] = tmpr1; + // Even if you need only bank2 you must properly set up SDCR and SDTR + // regitsters for bank1 too. Both banks will be tuned equally assuming + // connected memory ICs are equal. + sdramp->sdram->SDCR1 = cfgp->sdcr; + sdramp->sdram->SDTR1 = cfgp->sdtr; + sdramp->sdram->SDCR2 = cfgp->sdcr; + sdramp->sdram->SDTR2 = cfgp->sdtr; - _sdram_init_sequence(cfg); + _sdram_init_sequence(cfgp); - sdram->state = SDRAM_READY; + sdramp->state = SDRAM_READY; } } -/** - * @brief Deactivates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * - * @notapi - */ -void fsmcSdramStop(SDRAMDriver *sdram) { +// Deactivates the SDRAM peripheral. +// sdramp pointer to the @p SDRAMDriver object +void fsmcSdramStop(SDRAMDriver *sdramp) { uint32_t command_target = 0; @@ -223,12 +154,13 @@ void fsmcSdramStop(SDRAMDriver *sdram) { command_target |= FMC_SDCMR_CTB2; #endif - if (sdram->state == SDRAM_READY) { - SDRAMD.sdram->SDCMR = FSMCCM_POWER_DOWN | command_target; - sdram->state = SDRAM_STOP; + if (sdramp->state == SDRAM_READY) { + SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target; + sdramp->state = SDRAM_STOP; } } -#endif /* STM32_USE_FSMC_SDRAM */ +#endif // STM32_USE_FSMC_SDRAM -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ +#endif //STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx / STM32F745xx / STM32F746xx + // STM32F756xx / STM32F767xx / STM32F769xx / STM32F777xx / STM32F779xx diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.h index a66b1a0405..3a1491b74b 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.h +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.h @@ -1,170 +1,130 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_FSMC_sdram.h - * @brief SDRAM Driver subsystem low level driver header. - * - * @addtogroup SDRAM - * @{ - */ - -#ifndef HAL_FSMC_SDRAM_H_ -#define HAL_FSMC_SDRAM_H_ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess and Nick Klimov aka progfin +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_FMC_SDRAM_H_ +#define HAL_FMC_SDRAM_H_ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #include "hal_stm32_fsmc.h" #if (STM32_USE_FSMC_SDRAM == TRUE) -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM1 is included. - */ +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// +// Configuration options + +// SDRAM driver enable switch. +// If set to @p TRUE the support for SDRAM1 is included. #if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) #define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE #else #define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE #endif -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM2 is included. - */ +// SDRAM driver enable switch. +// If set to @p TRUE the support for SDRAM2 is included. #if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) #define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE #else #define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE #endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// #if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2 #error "SDRAM driver activated but no SDRAM peripheral assigned" #endif #if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" +#error "FMC not present in the selected device" #endif -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -typedef enum +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// Driver state machine possible states. +typedef enum { - SDRAM_UNINIT = 0, /**< Not initialized. */ - SDRAM_STOP = 1, /**< Stopped. */ - SDRAM_READY = 2, /**< Ready. */ + SDRAM_UNINIT = 0, //*< Not initialized. + SDRAM_STOP = 1, //*< Stopped. + SDRAM_READY = 2, //*< Ready. } sdramstate_t; -/** - * @brief Type of a structure representing an SDRAM driver. - */ +// Type of a structure representing an SDRAM driver. typedef struct SDRAMDriver SDRAMDriver; -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct -{ - /** - * @brief SDRAM control register. - * @note Its value will be used for both banks. - */ +// Driver configuration structure. +// It could be empty on some architectures. +typedef struct { + // SDRAM control register. + // Its value will be used for both banks. uint32_t sdcr; - /** - * @brief SDRAM timing register. - * @note Its value will be used for both banks. - */ + // SDRAM timing register. + // Its value will be used for both banks. uint32_t sdtr; - /** - * @brief SDRAM command mode register. - * @note Only its MRD and NRFS bits will be used. - */ + // SDRAM command mode register. + // Only its MRD and NRFS bits will be used. uint32_t sdcmr; - /** - * @brief SDRAM refresh timer register. - * @note Only its COUNT bits will be used. - */ + // SDRAM refresh timer register. + // Only its COUNT bits will be used. uint32_t sdrtr; + } SDRAMConfig; -/** - * @brief Structure representing an SDRAM driver. - */ -struct SDRAMDriver -{ - /** - * @brief Driver state. - */ +// Structure representing an SDRAM driver. +struct SDRAMDriver { + // Driver state. sdramstate_t state; - /** - * @brief Pointer to the FSMC SDRAM registers block. - */ - FMC_SDRAM_TypeDef *sdram; + + // Pointer to the FMC SDRAM registers block. + FSMC_SDRAM_TypeDef *sdram; }; -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// extern SDRAMDriver SDRAMD; #ifdef __cplusplus extern "C" { #endif + void fsmcSdramInit(void); void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); void fsmcSdramStop(SDRAMDriver *sdramp); + #ifdef __cplusplus } #endif -#endif /* STM32_USE_FSMC_SDRAM */ +#endif // STM32_USE_FSMC_SDRAM -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx / STM32F7xx */ +#endif //STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx / STM32F745xx / STM32F746xx + // STM32F756xx / STM32F767xx / STM32F769xx / STM32F777xx / STM32F779xx -#endif /* HAL_FSMC_SDRAM_H_ */ +#endif // HAL_FMC_SDRAM_H_ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c index 9728585a98..4e2cd5fc4d 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c @@ -1,91 +1,58 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_FSMC_sram.c - * @brief SRAM Driver subsystem low level driver source. - * - * @addtogroup SRAM - * @{ - */ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// + #include "hal.h" -#include "FSMC_sram_lld.h" +#include "fsmc_sram_lld.h" #if (STM32_USE_FSMC_SRAM == TRUE) -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SRAM1 driver identifier. - */ +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// +// SRAM1 driver identifier. #if STM32_SRAM_USE_FSMC_SRAM1 SRAMDriver SRAMD1; #endif -/** - * @brief SRAM2 driver identifier. - */ +// SRAM2 driver identifier. #if STM32_SRAM_USE_FSMC_SRAM2 SRAMDriver SRAMD2; #endif -/** - * @brief SRAM3 driver identifier. - */ +// SRAM3 driver identifier. #if STM32_SRAM_USE_FSMC_SRAM3 SRAMDriver SRAMD3; #endif -/** - * @brief SRAM4 driver identifier. - */ +// SRAM4 driver identifier. #if STM32_SRAM_USE_FSMC_SRAM4 SRAMDriver SRAMD4; #endif -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver interrupt handlers. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// -/** - * @brief Low level SRAM driver initialization. - * - * @notapi - */ +// Low level SRAM driver initialization. void fsmcSramInit(void) { stm32FsmcInit(); @@ -111,49 +78,44 @@ void fsmcSramInit(void) { #endif /* STM32_SRAM_USE_FSMC_SRAM4 */ } -/** - * @brief Configures and activates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * @param[in] cfgp pointer to the @p SRAMConfig object - * - * @notapi - */ -void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfg) { +// Configures and activates the SRAM peripheral. +// sramp pointer to the @p SRAMDriver object +// cfgp pointer to the @p SRAMConfig object +void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { if (FSMCD1.state == FSMC_STOP) - stm32FsmcStart(&FSMCD1); + fsmc_start(&FSMCD1); osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), "invalid state"); if (sramp->state == SRAM_STOP) { - sramp->sram->BTR = cfg->btr; - sramp->sram->BWTR = cfg->bwtr; - sramp->sram->BCR = cfg->bcr | FSMC_BCR_MBKEN; + sramp->sram->BTR = cfgp->btr; + sramp->sram->BWTR = cfgp->bwtr; + sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; sramp->state = SRAM_READY; } } -/** - * @brief Deactivates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * - * @notapi - */ -void fsmcSramStop(SRAMDriver *sram) { +// Deactivates the SRAM peripheral. +// sramp pointer to the @p SRAMDriver object +void fsmcSramStop(SRAMDriver *sramp) { - if (sram->state == SRAM_READY) { + if (sramp->state == SRAM_READY) { uint32_t mask = FSMC_BCR_MBKEN; + #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) mask |= FSMC_BCR_CCLKEN; #endif - sram->sram->BCR &= ~mask; - sram->state = SRAM_STOP; + + sramp->sram->BCR &= ~mask; + sramp->state = SRAM_STOP; } } -#endif /* STM32_USE_FSMC_SRAM */ +#endif // STM32_USE_FSMC_SRAM */ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.h b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.h index 6979b16f35..fb2fbd9e38 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.h +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.h @@ -1,26 +1,8 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_FSMC_sram.h - * @brief SRAM Driver subsystem low level driver header. - * - * @addtogroup SRAM - * @{ - */ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// #ifndef HAL_FSMC_SRAM_H_ #define HAL_FSMC_SRAM_H_ @@ -29,55 +11,41 @@ #if (STM32_USE_FSMC_SRAM == TRUE) -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM1 is included. - */ +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +// SRAM driver enable switch. +// If set to @p TRUE the support for SRAM1 is included. #if !defined(STM32_SRAM_USE_FSMC_SRAM1) #define STM32_SRAM_USE_FSMC_SRAM1 FALSE #endif -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM2 is included. - */ +// SRAM driver enable switch. +// If set to @p TRUE the support for SRAM2 is included. #if !defined(STM32_SRAM_USE_FSMC_SRAM2) #define STM32_SRAM_USE_FSMC_SRAM2 FALSE #endif -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM3 is included. - */ +// SRAM driver enable switch. +// If set to @p TRUE the support for SRAM3 is included. #if !defined(STM32_SRAM_USE_FSMC_SRAM3) #define STM32_SRAM_USE_FSMC_SRAM3 FALSE #endif -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM4 is included. - */ +// SRAM driver enable switch. +// If set to @p TRUE the support for SRAM4 is included. #if !defined(STM32_SRAM_USE_FSMC_SRAM4) #define STM32_SRAM_USE_FSMC_SRAM4 FALSE #endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// #if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 @@ -89,55 +57,45 @@ #error "FSMC not present in the selected device" #endif -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// Driver state machine possible states. typedef enum { - SRAM_UNINIT = 0, /**< Not initialized. */ - SRAM_STOP = 1, /**< Stopped. */ - SRAM_READY = 2, /**< Ready. */ + SRAM_UNINIT = 0, // Not initialized + SRAM_STOP = 1, // Stopped + SRAM_READY = 2, // Ready } sramstate_t; -/** - * @brief Type of a structure representing an NAND driver. - */ +// Type of a structure representing an NAND driver. typedef struct SRAMDriver SRAMDriver; -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - * @note Some bits in BCR register will be forced by driver. - */ +// Driver configuration structure. +// It could be empty on some architectures. +// Some bits in BCR register will be forced by driver. typedef struct { uint32_t bcr; uint32_t btr; uint32_t bwtr; } SRAMConfig; -/** - * @brief Structure representing an NAND driver. - */ +// Structure representing an NAND driver. struct SRAMDriver { - /** - * @brief Driver state. - */ + // Driver state sramstate_t state; - /** - * @brief Pointer to the FSMC SRAM registers block. - */ - FMC_NORSRAM_TypeDef *sram; + + // Pointer to the FSMC SRAM registers block. + FSMC_SRAM_NOR_TypeDef *sram; }; -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// #if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD1; @@ -158,13 +116,15 @@ extern SRAMDriver SRAMD4; #ifdef __cplusplus extern "C" { #endif + void fsmcSramInit(void); - void fsmcSramStart(SRAMDriver *sram, const SRAMConfig *cfg); - void fsmcSramStop(SRAMDriver *sram); + void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); + void fsmcSramStop(SRAMDriver *sramp); + #ifdef __cplusplus } #endif -#endif /* STM32_USE_FSMC_SRAM */ +#endif // STM32_USE_FSMC_SRAM -#endif /* HAL_FSMC_SRAM_H_ */ +#endif // HAL_FSMC_SRAM_H_ diff --git a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc/hal_stm32_fsmc.c b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc/hal_stm32_fsmc.c index e9e13a3044..7e35c365ba 100644 --- a/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc/hal_stm32_fsmc.c +++ b/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc/hal_stm32_fsmc.c @@ -1,38 +1,20 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_FSMC.c - * @brief FSMC Driver subsystem low level driver source template. - * - * @addtogroup FSMC - * @{ - */ #include "hal.h" #include "hal_stm32_fsmc.h" #if (HAL_USE_FSMC == TRUE) +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// /** * @brief FSMC1 driver identifier. @@ -41,86 +23,72 @@ FSMCDriver FSMCD1; #endif -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// -/** - * @brief Low level FSMC driver initialization. - * - * @notapi - */ +// Low level FSMC driver initialization. void stm32FsmcInit(void) { if (FSMCD1.state == FSMC_UNINIT) { FSMCD1.state = FSMC_STOP; #if STM32_SRAM_USE_FSMC_SRAM1 - FSMCD1.sram1 = (FMC_NORSRAM_TypeDef *)(_MC_Bank1_R_BASE); + FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); #endif #if STM32_SRAM_USE_FSMC_SRAM2 - FSMCD1.sram2 = (FMC_NORSRAM_TypeDef *)(_MC_Bank1_R_BASE + 8); + FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); #endif #if STM32_SRAM_USE_FSMC_SRAM3 - FSMCD1.sram3 = (FMC_NORSRAM_TypeDef *)(_MC_Bank1_R_BASE + 8 * 2); + FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); #endif #if STM32_SRAM_USE_FSMC_SRAM4 - FSMCD1.sram4 = (FMC_NORSRAM_TypeDef *)(_MC_Bank1_R_BASE + 8 * 3); + FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); #endif #if STM32_NAND_USE_FSMC_NAND1 - FSMCD1.nand1 = (FMC_NAND_TypeDef *)_MC_Bank2_R_BASE; + FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; #endif #if STM32_NAND_USE_FSMC_NAND2 - FSMCD1.nand2 = (FMC_NAND_TypeDef *)_MC_Bank3_R_BASE; + FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; #endif #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #if STM32_USE_FSMC_SDRAM - FSMCD1.sdram = (FMC_SDRAM_TypeDef *)_MC_Bank5_6_R_BASE; + FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif #endif } } -/** - * @brief Configures and activates the FSMC peripheral. - * - * @param[in] FSMCp pointer to the @p FSMCDriver object - * - * @notapi - */ -void stm32FsmcStart(FSMCDriver *FSMCp) { +// Configures and activates the FSMC peripheral. +// fsmcp pointer to the @p FSMCDriver object +void fsmc_start(FSMCDriver *fsmcp) { - osalDbgAssert((FSMCp->state == FSMC_STOP) || (FSMCp->state == FSMC_READY), + osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), "invalid state"); - if (FSMCp->state == FSMC_STOP) { + if (fsmcp->state == FSMC_STOP) { /* Enables the peripheral.*/ #if STM32_FSMC_USE_FSMC1 - if (&FSMCD1 == FSMCp) { + if (&FSMCD1 == fsmcp) { #ifdef rccResetFSMC rccResetFSMC(); #endif @@ -131,21 +99,15 @@ void stm32FsmcStart(FSMCDriver *FSMCp) { } #endif /* STM32_FSMC_USE_FSMC1 */ - FSMCp->state = FSMC_READY; + fsmcp->state = FSMC_READY; } } -/** - * @brief Deactivates the FSMC peripheral. - * - * @param[in] emcp pointer to the @p FSMCDriver object - * - * @notapi - */ -void stm32FsmcStop(FSMCDriver *fsmc) -{ +// Deactivates the FSMC peripheral. +// emcp pointer to the @p FSMCDriver object +void fsmc_stop(FSMCDriver *fsmcp) { - if (fsmc->state == FSMC_READY) { + if (fsmcp->state == FSMC_READY) { /* Resets the peripheral.*/ #ifdef rccResetFSMC rccResetFSMC(); @@ -153,7 +115,7 @@ void stm32FsmcStop(FSMCDriver *fsmc) /* Disables the peripheral.*/ #if STM32_FSMC_USE_FSMC1 - if (&FSMCD1 == fsmc) { + if (&FSMCD1 == fsmcp) { #if HAL_USE_NAND nvicDisableVector(STM32_FSMC_NUMBER); #endif @@ -161,15 +123,11 @@ void stm32FsmcStop(FSMCDriver *fsmc) } #endif /* STM32_FSMC_USE_FSMC1 */ - fsmc->state = FSMC_STOP; + fsmcp->state = FSMC_STOP; } } -/** - * @brief FSMC shared interrupt handler. - * - * @notapi - */ +// FSMC shared interrupt handler. CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_PROLOGUE();