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‎.github/workflows/regress.yml

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name: regress
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on:
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push:
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branches: [ main ]
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pull_request:
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branches: [ main ]
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env:
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# Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
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BUILD_TYPE: Debug
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jobs:
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build:
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# The CMake configure and build commands are platform agnostic and should work equally
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# well on Windows or Mac. You can convert this to a matrix build if you need
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# cross-platform coverage.
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# See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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with:
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submodules: true
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- name: create docker regress image
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run: docker build . --file Dockerfile.regress -t regress
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- name: run regress
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run: docker run regress

‎.gitignore

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*~
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*.log
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*.pyc
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*.snl
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*.mf
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*/*/primitives.v
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*/*/verif.*
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*/*/verilator.gold
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designs/adder/adder_snl.v
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designs/arm_core/arm_core_netlist.v
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designs/arm_core/arm_core_snl_error.v
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designs/arm_core/arm_core_snl.v
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designs/arm_core/*.list

‎Dockerfile.regress

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# SPDX-FileCopyrightText: 2024 The Naja authors <https://github.com/najaeda/naja/blob/main/AUTHORS>
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#
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# SPDX-License-Identifier: Apache-2.0
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FROM alpine:3.19.1 as builder
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# Install required packages
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RUN apk --no-cache add ca-certificates
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RUN apk update && apk upgrade
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RUN apk add --no-cache \
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autoconf automake \
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g++ python3 make \
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flex-dev bison \
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help2man
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#compile verilator
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RUN wget https://github.com/verilator/verilator/archive/refs/tags/v5.022.tar.gz
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RUN tar xvzf v5.022.tar.gz
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WORKDIR /verilator-5.022
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RUN autoconf && ./configure --prefix=/verilator-install && make -j$(nproc)
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RUN make install
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#compile yosys
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RUN apk add pkgconfig tcl-dev readline-dev libffi-dev git
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WORKDIR /
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RUN wget https://github.com/YosysHQ/yosys/archive/refs/tags/yosys-0.38.tar.gz
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RUN tar xvzf yosys-0.38.tar.gz
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WORKDIR /yosys-yosys-0.38
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RUN make config-gcc
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RUN make -j$(nproc)
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RUN make install PREFIX=/yosys-install
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#compile naja
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RUN apk add cmake \
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capnproto capnproto-dev \
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python3-dev \
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boost-dev onetbb-dev
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COPY / /naja
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RUN rm -rf /naja/build
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RUN rm -rf /naja-install
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WORKDIR /naja/build
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RUN cmake .. -DCMAKE_INSTALL_PREFIX=/naja-install && make -j$(nproc) && make install
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WORKDIR /naja/regress
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ENV SET_PYTHONPATH=/naja-install/lib/python
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ENV LD_LIBRARY_PATH=/naja-install/lib
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ENV NAJA_EDIT=/naja-install/bin/naja_edit
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ENV PRIMITIVES=/naja-install/shared/primitives/xilinx.py
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ENV YOSYS=/yosys-install/bin/yosys
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ENV VERILATOR=/verilator-install/bin/verilator
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CMD /yosys-install/bin/yosys -V; /verilator-install/bin/verilator -V; make clean; make

‎designs/Makefile

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all:
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cd adder && make
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cd arm_core && make
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cd test_args && make
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#cd vexriscv && make
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cd jpeg && make
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cd black_parrot && make
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clean:
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cd adder && make clean
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cd arm_core && make clean
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cd test_args && make clean
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cd vexriscv && make clean
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cd jpeg && make clean
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cd black_parrot && make clean

‎designs/Makefile.inc

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YOSYS ?= yosys
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EQY ?= eqy
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VERILATOR ?= verilator
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NAJA_EDIT ?= $(NAJA_INSTALL)/bin/naja_edit
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PRIMITIVES ?= $(NAJA_INSTALL)/shared/primitives/xilinx.py
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ASAP7_PRIMITIVES ?= $(NAJA_INSTALL)/shared/primitives/asap7.py
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NANGATE45_PRIMITIVES ?= $(NAJA_INSTALL)/shared/primitives/nangate45.py
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SET_PYTHONPATH ?= $(NAJA_INSTALL)/lib/python

‎designs/adder/Makefile

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include ../Makefile.inc
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all: adder_snl.v primitives.v verilator
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verilator: adder_snl.v primitives.v
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${VERILATOR} --top-module adder --lint-only primitives.v adder_snl.v
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adder_netlist.v: src/adder.v
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${YOSYS} src/synth.ys
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adder_snl.v primitives.v: adder_netlist.v
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export PYTHONPATH=${SET_PYTHONPATH}; \
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${NAJA_EDIT} -f verilog -t verilog -p ${PRIMITIVES} -i $< -o adder_snl.v -d primitives.v
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clean:
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-rm adder_snl.v primitives.v adder_netlist.v

‎designs/adder/adder_netlist.v

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/* Generated by Yosys 0.38 (git sha1 543faed9c8c, clang 15.0.0 -fPIC -Os) */
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(* top = 1 *)
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(* src = "src/adder.v:1.1-8.10" *)
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module adder(a, b, s);
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wire _00_;
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(* force_downto = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:30.21-30.22" *)
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wire [1:0] _01_;
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(* force_downto = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:30.21-30.22" *)
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wire [5:0] _02_;
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(* force_downto = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:30.21-30.22" *)
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wire [3:0] _03_;
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(* force_downto = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:30.21-30.22" *)
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wire [1:0] _04_;
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(* force_downto = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:30.21-30.22" *)
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wire [5:0] _05_;
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(* src = "src/adder.v:2.14-2.15" *)
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input [7:0] a;
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wire [7:0] a;
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(* src = "src/adder.v:3.14-3.15" *)
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input [7:0] b;
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wire [7:0] b;
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(* src = "src/adder.v:4.10-4.11" *)
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output s;
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wire s;
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(* module_not_derived = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:61.26-63.41" *)
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LUT6 #(
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.INIT(64'hefffffffffffffff)
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) _06_ (
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.I0(_05_[0]),
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.I1(_05_[1]),
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.I2(_05_[2]),
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.I3(_05_[3]),
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.I4(_05_[4]),
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.I5(_05_[5]),
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.O(_00_)
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);
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(* module_not_derived = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:43.26-44.30" *)
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LUT2 #(
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.INIT(4'h1)
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) _07_ (
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.I0(_04_[0]),
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.I1(_04_[1]),
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.O(_05_[4])
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);
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(* module_not_derived = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:61.26-63.41" *)
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LUT6 #(
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.INIT(64'h0000000000000001)
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) _08_ (
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.I0(_02_[0]),
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.I1(_02_[1]),
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.I2(_02_[2]),
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.I3(_02_[3]),
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.I4(_02_[4]),
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.I5(_02_[5]),
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.O(_05_[5])
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);
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(* module_not_derived = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:43.26-44.30" *)
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LUT2 #(
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.INIT(4'h1)
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) _09_ (
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.I0(_01_[0]),
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.I1(_01_[1]),
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.O(_05_[2])
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);
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(* module_not_derived = 32'd1 *)
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(* src = "/opt/homebrew/bin/../share/yosys/xilinx/lut_map.v:51.26-53.19" *)
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LUT4 #(
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.INIT(16'h0001)
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) _10_ (
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.I0(_03_[0]),
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.I1(_03_[1]),
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.I2(_03_[2]),
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.I3(_03_[3]),
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.O(_05_[3])
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);
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(* keep = 32'd1 *)
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IBUF _11_ (
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.I(a[0]),
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.O(_02_[0])
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);
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(* keep = 32'd1 *)
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IBUF _12_ (
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.I(a[1]),
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.O(_03_[0])
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);
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(* keep = 32'd1 *)
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IBUF _13_ (
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.I(a[2]),
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.O(_04_[0])
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);
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(* keep = 32'd1 *)
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IBUF _14_ (
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.I(a[3]),
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.O(_02_[1])
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);
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(* keep = 32'd1 *)
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IBUF _15_ (
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.I(a[4]),
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.O(_03_[1])
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);
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(* keep = 32'd1 *)
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IBUF _16_ (
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.I(a[5]),
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.O(_01_[0])
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);
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(* keep = 32'd1 *)
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IBUF _17_ (
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.I(a[6]),
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.O(_05_[0])
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);
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(* keep = 32'd1 *)
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IBUF _18_ (
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.I(a[7]),
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.O(_03_[2])
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);
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(* keep = 32'd1 *)
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IBUF _19_ (
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.I(b[0]),
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.O(_05_[1])
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);
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(* keep = 32'd1 *)
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IBUF _20_ (
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.I(b[1]),
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.O(_02_[2])
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);
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(* keep = 32'd1 *)
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IBUF _21_ (
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.I(b[2]),
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.O(_02_[3])
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);
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(* keep = 32'd1 *)
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IBUF _22_ (
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.I(b[3]),
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.O(_01_[1])
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);
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(* keep = 32'd1 *)
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IBUF _23_ (
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.I(b[4]),
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.O(_02_[4])
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);
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(* keep = 32'd1 *)
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IBUF _24_ (
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.I(b[5]),
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.O(_04_[1])
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);
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(* keep = 32'd1 *)
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IBUF _25_ (
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.I(b[6]),
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.O(_03_[3])
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);
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(* keep = 32'd1 *)
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IBUF _26_ (
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.I(b[7]),
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.O(_02_[5])
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);
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(* keep = 32'd1 *)
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OBUF _27_ (
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.I(_00_),
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.O(s)
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);
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endmodule

‎designs/adder/src/adder.v

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module adder(a, b, s);
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input [7:0] a;
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input [7:0] b;
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output s;
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assign s = a || b;
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endmodule

‎designs/adder/src/comp.ys

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# gold design
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read_verilog primitives.v arm_core_netlist.v
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prep -top arm_core
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splitnets -ports;;
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design -stash gold
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#naja design
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read_verilog primitives.v arm_core_snl.v
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prep -top arm_core
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splitnets -ports;;
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design -stash naja
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# prove equivalence
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design -copy-from gold -as gold arm_core
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design -copy-from naja -as naja arm_core
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equiv_make gold naja equiv
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hierarchy -top equiv
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equiv_simple
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equiv_status -assert

‎designs/adder/src/synth.ys

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read_verilog src/adder.v
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synth_xilinx -top adder
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write_verilog adder_netlist.v

‎designs/arm_core/Makefile

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include ../Makefile.inc
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all: edges.list verif.gold verilator.gold verif.error
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verif.error: arm_core_snl_error.v primitives.v
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${YOSYS} src/comp_error.ys
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touch $@
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verif.gold: arm_core_snl.v primitives.v
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${YOSYS} src/comp_gold.ys
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touch $@
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eqy.gold: arm_core_snl.v primitives.v
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-rm -rf comp
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${EQY} src/comp.eqy
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touch $@
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verilator.gold: arm_core_snl.v primitives.v
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${VERILATOR} --top-module arm_core --lint-only primitives.v arm_core_snl.v
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touch $@
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arm_core_netlist.v: src/arm_core.v
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${YOSYS} src/synth.ys
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arm_core_snl/snl.mf: arm_core_netlist.v
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export PYTHONPATH=${SET_PYTHONPATH}; \
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${PYTHON_ENV} ${NAJA_EDIT} -f verilog -t snl -i $< -o arm_core_snl -p ${PRIMITIVES}
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edges.list: arm_core_snl/snl.mf gen_edge_list.py
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export PYTHONPATH=${SET_PYTHONPATH}; \
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${NAJA_EDIT} -f snl -i arm_core_snl -e gen_edge_list.py
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arm_core_snl.v primitives.v: arm_core_netlist.v
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export PYTHONPATH=${SET_PYTHONPATH}; \
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${NAJA_EDIT} -f verilog -t verilog -p ${PRIMITIVES} -i arm_core_netlist.v -o arm_core_snl.v -d primitives.v
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arm_core_snl_error.v: arm_core_netlist.v src/add_error.py
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export PYTHONPATH=${SET_PYTHONPATH}; \
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${NAJA_EDIT} -e src/add_error.py -f verilog -t verilog -p ${PRIMITIVES} -i arm_core_netlist.v -o arm_core_snl_error.v -d primitives.v
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clean:
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-rm arm_core_snl.v primitives.v arm_core_netlist.v

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