diff --git a/src/modm/platform/clock/stm32/rcc.cpp.in b/src/modm/platform/clock/stm32/rcc.cpp.in
index 3e1c73ae44..63d51d2c66 100644
--- a/src/modm/platform/clock/stm32/rcc.cpp.in
+++ b/src/modm/platform/clock/stm32/rcc.cpp.in
@@ -315,6 +315,15 @@ Rcc::enablePll{{id}}(PllSource source, const PllFactors& pllFactors, uint32_t wa
 %% endif
 }
 
+bool
+Rcc::disablePll{{id}}(uint32_t waitCycles)
+{
+	RCC->CR &= ~RCC_CR_PLL{{id}}ON;
+	while ((RCC->CR & RCC_CR_PLL{{id}}RDY) and --waitCycles)
+		;
+	return waitCycles > 0;
+}
+
 %% endfor
 
 %% if pllsai_p_usb
@@ -349,6 +358,15 @@ Rcc::enablePllSai(const PllSaiFactors& pllFactors, uint32_t waitCycles)
 
 	return tmp;
 }
+
+bool
+Rcc::disablePllSai(uint32_t waitCycles)
+{
+	RCC->CR &= ~RCC_CR_PLLSAION;
+	while ((RCC->CR & RCC_CR_PLLSAIRDY) and --waitCycles)
+		;
+	return waitCycles > 0;
+}
 %% endif
 
 %% if overdrive
diff --git a/src/modm/platform/clock/stm32/rcc.hpp.in b/src/modm/platform/clock/stm32/rcc.hpp.in
index b91529ef38..a3da541383 100644
--- a/src/modm/platform/clock/stm32/rcc.hpp.in
+++ b/src/modm/platform/clock/stm32/rcc.hpp.in
@@ -597,6 +597,14 @@ public:
 	static bool
 	enablePll{{id}}(PllSource source, const PllFactors& pllFactors, uint32_t waitCycles = 2048);
 
+	/**
+	 * Disable PLL{{id}}.
+	 *
+	 * \param	waitCycles
+	 * 		Number of cycles to wait for the pll to stabilise. Default: 2048.
+	 */
+	static bool
+	disablePll{{id}}(uint32_t waitCycles = 2048);
 %% endfor
 
 %% if pllsai_p_usb
@@ -613,6 +621,15 @@ public:
 	 */
 	static bool
 	enablePllSai(const PllSaiFactors& pllFactors, uint32_t waitCycles = 2048);
+
+	/**
+	 * Disable PLLSAI.
+	 *
+	 * \param	waitCycles
+	 * 		Number of cycles to wait for the pll to stabilise. Default: 2048.
+	 */
+	static bool
+	disablePllSai(uint32_t waitCycles = 2048);
 %% endif
 
 %% if target.family == "l0"