[board] Correcly enable overdrive mode for STM32 boards with >=180 MH…

…z clock
modm-io · Jan 10, 2021 · 02b1571 · 02b1571
1 parent cbaf940
commit 02b1571
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Showing 6 changed files with 12 additions and 10 deletions.
diff --git a/src/modm/board/disco_f429zi/board.hpp b/src/modm/board/disco_f429zi/board.hpp
@@ -83,8 +83,8 @@ struct SystemClock
 			.pllP = 2		// 360MHz / P=2 -> 180MHz = F_cpu
 		};
 		Rcc::enablePll(Rcc::PllSource::ExternalCrystal, pllFactors);
-		PWR->CR |= PWR_CR_ODEN; // Enable overdrive mode
-		while (not (PWR->CSR & PWR_CSR_ODRDY)) ;
+		// Required for 180 MHz clock
+		Rcc::enableOverdriveMode();
 		Rcc::setFlashLatency<Frequency>();
 		Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
 		Rcc::setApb1Prescaler(Rcc::Apb1Prescaler::Div4);

diff --git a/src/modm/board/disco_f469ni/board.hpp b/src/modm/board/disco_f469ni/board.hpp
@@ -91,8 +91,8 @@ struct SystemClock
 			.pllP = 2,		// 360MHz / P=2 -> 180MHz = F_cpu
 		};
 		Rcc::enablePll(Rcc::PllSource::ExternalCrystal, pllFactors);
-		PWR->CR |= PWR_CR_ODEN; // Enable overdrive mode
-		while (not (PWR->CSR & PWR_CSR_ODRDY)) ;
+		// Required for 180 MHz clock
+		Rcc::enableOverdriveMode();
 		Rcc::setFlashLatency<Frequency>();
 		Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
 		Rcc::setApb1Prescaler(Rcc::Apb1Prescaler::Div4);

diff --git a/src/modm/board/disco_f746ng/board.hpp b/src/modm/board/disco_f746ng/board.hpp
@@ -91,8 +91,8 @@ struct SystemClock
 			.pllQ = 9		// 432MHz / Q=9 -> 48MHz = F_usb
 		};
 		Rcc::enablePll(Rcc::PllSource::ExternalClock, pllFactors);
-		PWR->CR1 |= PWR_CR1_ODEN; // Enable overdrive mode
-		while (not (PWR->CSR1 & PWR_CSR1_ODRDY)) ;
+		// Required for 216 MHz clock
+		Rcc::enableOverdriveMode();
 
 		Rcc::setFlashLatency<Frequency>();
 		Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);

diff --git a/src/modm/board/disco_f769ni/board.hpp b/src/modm/board/disco_f769ni/board.hpp
@@ -88,8 +88,8 @@ struct SystemClock
 			.pllP = 2		// 432MHz / P=2 -> 216MHz = F_cpu
 		};
 		Rcc::enablePll(Rcc::PllSource::ExternalClock, pllFactors);
-		PWR->CR1 |= PWR_CR1_ODEN; // Enable overdrive mode
-		while (not (PWR->CSR1 & PWR_CSR1_ODRDY)) ;
+		// Required for 216 MHz clock
+		Rcc::enableOverdriveMode();
 		Rcc::setFlashLatency<Frequency>();
 		Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
 		// APB1 is running only at 27MHz, since AHB / 4 = 54MHz > 45MHz limit!

diff --git a/src/modm/board/nucleo_f446re/board.hpp b/src/modm/board/nucleo_f446re/board.hpp
@@ -76,6 +76,8 @@ struct SystemClock {
 			.pllP = 2,		// 360MHz / P=  2 -> 180MHz = F_cpu
 		};
 		Rcc::enablePll(Rcc::PllSource::InternalClock, pllFactors);
+		// Required for 180 MHz clock
+		Rcc::enableOverdriveMode();
 		// set flash latency
 		Rcc::setFlashLatency<Frequency>();
 		// switch system clock to PLL output

diff --git a/src/modm/board/nucleo_f746zg/board.hpp b/src/modm/board/nucleo_f746zg/board.hpp
@@ -94,8 +94,8 @@ struct SystemClock
 			//.pllQ = 9		// 432MHz / P=2 -> 48MHz (USB, etc.)
 		};
 		Rcc::enablePll(Rcc::PllSource::ExternalClock, pllFactors);
-		PWR->CR1 |= PWR_CR1_ODEN; // Enable overdrive mode
-		while (not (PWR->CSR1 & PWR_CSR1_ODRDY)) ;
+		// Required for 216 MHz clock
+		Rcc::enableOverdriveMode();
 		Rcc::setFlashLatency<Frequency>();
 		Rcc::enableSystemClock(Rcc::SystemClockSource::Pll);
 		// APB1 is running at 54MHz, since AHB / 4 = 54MHz (= limit)