@@ -467,12 +467,13 @@ void HLSignatureLower::CreateDxilSignatures() {
467467 if (HLModule::IsStreamOutputPtrType (Ty))
468468 continue ;
469469
470- // Skip OutIndices and InPayload
470+ // Skip OutIndices, InPayload, and NodeIO
471471 DxilParameterAnnotation ¶mAnnotation =
472472 EntryAnnotation->GetParameterAnnotation (arg.getArgNo ());
473473 hlsl::DxilParamInputQual qual = paramAnnotation.GetParamInputQual ();
474474 if (qual == hlsl::DxilParamInputQual::OutIndices ||
475- qual == hlsl::DxilParamInputQual::InPayload)
475+ qual == hlsl::DxilParamInputQual::InPayload ||
476+ qual == hlsl::DxilParamInputQual::NodeIO)
476477 continue ;
477478
478479 ProcessArgument (Entry, EntryAnnotation, arg, props, pSM,
@@ -523,17 +524,15 @@ void HLSignatureLower::AllocateDxilInputOutputs() {
523524 " Failed to allocate all input signature elements in available space." );
524525 }
525526
526- if (props.shaderKind != DXIL::ShaderKind::Amplification ) {
527+ if (! props.IsAS () ) {
527528 hlsl::PackDxilSignature (EntrySig.OutputSignature , packing);
528529 if (!EntrySig.OutputSignature .IsFullyAllocated ()) {
529530 llvm_unreachable (" Failed to allocate all output signature elements in "
530531 " available space." );
531532 }
532533 }
533534
534- if (props.shaderKind == DXIL::ShaderKind::Hull ||
535- props.shaderKind == DXIL::ShaderKind::Domain ||
536- props.shaderKind == DXIL::ShaderKind::Mesh) {
535+ if (props.UsesPatchConstOrPrimSignature ()) {
537536 hlsl::PackDxilSignature (EntrySig.PatchConstOrPrimSignature , packing);
538537 if (!EntrySig.PatchConstOrPrimSignature .IsFullyAllocated ()) {
539538 llvm_unreachable (" Failed to allocate all patch constant signature "
@@ -886,7 +885,7 @@ struct InputOutputAccessInfo {
886885void collectInputOutputAccessInfo (
887886 Value *GV, Constant *constZero,
888887 std::vector<InputOutputAccessInfo> &accessInfoList, bool hasVertexOrPrimID,
889- bool bInput, bool bRowMajor, bool isMS ) {
888+ bool bInput, bool bRowMajor) {
890889 // merge GEP use for input output.
891890 dxilutil::MergeGepUse (GV);
892891 for (auto User = GV->user_begin (); User != GV->user_end ();) {
@@ -1129,8 +1128,8 @@ void HLSignatureLower::GenerateDxilInputsOutputs(DXIL::SignatureKind SK) {
11291128 opcode = OP::OpCode::LoadInput;
11301129 break ;
11311130 case DXIL::SignatureKind::Output:
1132- opcode =
1133- props. IsMS () ? OP::OpCode::StoreVertexOutput : OP::OpCode::StoreOutput;
1131+ opcode = props. IsMS () || props. IsMeshNode () ? OP::OpCode::StoreVertexOutput
1132+ : OP::OpCode::StoreOutput;
11341133 break ;
11351134 case DXIL::SignatureKind::PatchConstOrPrim:
11361135 opcode = OP::OpCode::StorePrimitiveOutput;
@@ -1141,7 +1140,7 @@ void HLSignatureLower::GenerateDxilInputsOutputs(DXIL::SignatureKind SK) {
11411140 bool bInput = SK == DXIL::SignatureKind::Input;
11421141 bool bNeedVertexOrPrimID =
11431142 bInput && (props.IsGS () || props.IsDS () || props.IsHS ());
1144- bNeedVertexOrPrimID |= !bInput && props.IsMS ();
1143+ bNeedVertexOrPrimID |= !bInput && ( props.IsMS () || props. IsMeshNode () );
11451144
11461145 Constant *OpArg = hlslOP->GetU32Const ((unsigned )opcode);
11471146
@@ -1155,7 +1154,7 @@ void HLSignatureLower::GenerateDxilInputsOutputs(DXIL::SignatureKind SK) {
11551154
11561155 Constant *constZero = hlslOP->GetU32Const (0 );
11571156
1158- Value *undefVertexIdx = props.IsMS () || !bInput
1157+ Value *undefVertexIdx = props.IsMS () || props. IsMeshNode () || !bInput
11591158 ? nullptr
11601159 : UndefValue::get (Type::getInt32Ty (HLM.GetCtx ()));
11611160
@@ -1236,7 +1235,7 @@ void HLSignatureLower::GenerateDxilInputsOutputs(DXIL::SignatureKind SK) {
12361235 std::vector<InputOutputAccessInfo> accessInfoList;
12371236 collectInputOutputAccessInfo (GV, constZero, accessInfoList,
12381237 bNeedVertexOrPrimID && bIsArrayTy, bInput,
1239- bRowMajor, props. IsMS () );
1238+ bRowMajor);
12401239
12411240 for (InputOutputAccessInfo &info : accessInfoList) {
12421241 GenerateInputOutputUserCall (
@@ -1258,6 +1257,14 @@ void HLSignatureLower::GenerateDxilComputeAndNodeCommonInputs() {
12581257 DxilParameterAnnotation ¶mAnnotation =
12591258 funcAnnotation->GetParameterAnnotation (arg.getArgNo ());
12601259
1260+ DxilParamInputQual inputQual = paramAnnotation.GetParamInputQual ();
1261+ // Skip mesh node out params
1262+ if (funcProps.IsMeshNode () &&
1263+ (inputQual == DxilParamInputQual::OutIndices ||
1264+ inputQual == DxilParamInputQual::OutVertices ||
1265+ inputQual == DxilParamInputQual::OutPrimitives))
1266+ continue ;
1267+
12611268 llvm::StringRef semanticStr = paramAnnotation.GetSemanticString ();
12621269
12631270 if (semanticStr.empty ()) {
@@ -1424,8 +1431,7 @@ void HLSignatureLower::GenerateDxilPatchConstantLdSt() {
14241431 }
14251432 std::vector<InputOutputAccessInfo> accessInfoList;
14261433 collectInputOutputAccessInfo (GV, constZero, accessInfoList,
1427- bNeedVertexOrPrimID, bIsInput, bRowMajor,
1428- false );
1434+ bNeedVertexOrPrimID, bIsInput, bRowMajor);
14291435
14301436 bool bIsArrayTy = GV->getType ()->getPointerElementType ()->isArrayTy ();
14311437 bool isPrecise = m_preciseSigSet.count (SE);
@@ -1499,8 +1505,7 @@ void HLSignatureLower::GenerateDxilPatchConstantFunctionInputs() {
14991505 }
15001506 std::vector<InputOutputAccessInfo> accessInfoList;
15011507 collectInputOutputAccessInfo (&arg, constZero, accessInfoList,
1502- /* hasVertexOrPrimID*/ true , true , bRowMajor,
1503- false );
1508+ /* hasVertexOrPrimID*/ true , true , bRowMajor);
15041509 for (InputOutputAccessInfo &info : accessInfoList) {
15051510 Constant *OpArg = hlslOP->GetU32Const ((unsigned )opcode);
15061511 if (LoadInst *ldInst = dyn_cast<LoadInst>(info.user )) {
@@ -1802,6 +1807,13 @@ void HLSignatureLower::Run() {
18021807 GenerateDxilPrimOutputs ();
18031808 }
18041809 } else if (props.IsCS () || props.IsNode ()) {
1810+ if (props.IsMeshNode ()) {
1811+ GenerateEmitIndicesOperations ();
1812+ CreateDxilSignatures ();
1813+ AllocateDxilInputOutputs ();
1814+ GenerateDxilOutputs ();
1815+ GenerateDxilPrimOutputs ();
1816+ }
18051817 GenerateDxilComputeAndNodeCommonInputs ();
18061818 }
18071819
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