utils_rom.v

/*
This module generates few values accessible from RISC-V programs:
- 64 bit tick count (clocks since last CPU reset completion)
- 64 bit overlay tick count (clocks since last overlay loading)
- 64 bit random number (generated by linear-feedback shift register, using "$urandom")
*/

`timescale 1ns/10ps

module utils_rom (
    input wire clk,
    input wire cpu_reset_completed,
    input wire [1:0] addr,
    output wire [63:0] dout
);
    reg [63:0] tick_count = 0;
    reg [63:0] overlay_tick_count = 0;
    reg [63:0] random_number = 0;

    wire [63:0] mem [3:0];
    assign mem[0] = tick_count;
    assign mem[1] = overlay_tick_count;
    assign mem[2] = random_number;
    assign mem[3] = 0;
    
    assign dout = mem[addr];

    always @(posedge clk) begin
        // cpu_reset_completed goes low when CPU reset begins and high when CPU reset completes (stays high until next reset)
        // so it can be used to reset tick_count (instead of capturing its rising edge, which isn't necessary)
        if (~cpu_reset_completed) begin 
            tick_count <= 0;
        end else begin
            tick_count <= tick_count + 1;
        end 
        overlay_tick_count <= overlay_tick_count + 1;
        random_number <= $urandom;
    end

endmodule